ELEC 4200 Digital System Design

Spring 2013 – Lecture: WF 3-3:50pm in Broun 306

Lab in Broun 320: Section 1 M 4-6:50pm & Section 2 W 5-7:50pm
Instructor: Dr. Charles E. Stroud Office hours: 12-1pm MWF, 3-4pm M & 4-5pm WF Broun 325
GTA: Brian Pappas Office hours: TBA Office: TBA Broun Hall
2004 Catalog Data: ELEC 4200 DIGITAL SYSTEM DESIGN (3) LEC. 2. LAB 3. Pr. ELEC 2210 and ELEC
2220. Hierarchical, modular design of digital systems; computer-aided digital system modeling, simulation,
analysis, and synthesis; design implementation with programmable logic devices and field programmable gate
arrays.
Textbook: Digital Systems Design Using VHDL 2nd Ed., by Chas Roth and Lizy John, Thomson, 2008.
Goals: This course introduces the student to the design of digital logic circuits, both combinational and
sequential, and the design of digital systems in a hierarchical, top-down manner. The student is also
introduced to the use of computer-aided design tools to develop complex digital circuits and to prototyping
designs using programmable logic devices and field-programmable gate arrays.
Course Objectives:
1. Ability to use computer-aided design tools for design of complex digital logic circuits
2. Ability to model, simulate, verify, and synthesize with hardware description languages
3. Ability to design and prototype with programmable logic
Prerequisites by topic:
1. Digital logic design and analysis or switching theory
2. Computer system organization and design

Course Outline:
Wk Lecture Topic Ch Tentative Laboratory Projects
1 Overview of HDLs and programmable logic No lab
Review of combinational and sequential
2 logic circuit design and design verification 1 0) Introduction to lab hardware and software
Flip-flop/latch implementations and system-
3 level timing issues and analysis 1 No lab – MLK holiday
1) Schematic capture, simulation and synthesis of combinational
4 VHDL syntax, entities, and architectures 2
logic
5 VHDL concurrent and sequential constructs 2 2) Schematic capture, simulation and synthesis of sequential logic
VHDL modeling guidelines and
6 parameterization 2 3) VHDL modeling, simulation and synthesis of combinational logic
7 VHDL hierarchical design and test benches 4 4) VHDL modeling, simulation and synthesis of sequential logic
5) VHDL parameterized modeling, simulation and synthesis of a
8 Test #1 2/27, VHDL data type definitions 5
universal register/counter
6) VHDL parameterized register file with hierarchical modeling and
9 VHDL FSM modeling and simulation 8
test bench for design verification
7) VHDL hierarchical modeling, simulation and synthesis of
10 Boundary Scan Interface 10
manually controlled display system
PicoBlaze microcontroller architecture, 8) VHDL hierarchical modeling, simulation and synthesis of
11 operation and instruction set 9
Boundary Scan controlled display system
Programmable logic arrays, programming
12 technologies and interfaces 3 9) PicoBlaze programming, simulation & synthesis
FPGA and PLD/CPLD architectures and
13 operation 6
10) VHDL hierarchical modeling, simulation and synthesis of
14 Introduction to Verilog 3 PicoBlaze controlled display system
15 Test #2 4/24, Verilog and semester review
16 Final Exam: Thursday 5/2, 4-6:30pm
Method of evaluating student performance: There will be two exams and a comprehensive final exam,
contributing equally for a total of 60% to the final course grade. All exams will be closed-book, closed-
notes, closed-electronics (of all types) and closed-neighbor. Laboratory projects/exercises contribute 40% to
the final course grade. Note that each student (or designated lab group) is expected to do his/her (or their)
own laboratory project. Discussion of various aspects of the project with fellow students (groups) is
acceptable, provided that designs are not copied. All laboratory assignments (pre-lab and lab reports) and
projects must be turned in on or before the designated date/time to receive credit.
Class attendance and behavior: Students are expected to attend class regularly and on time as indicated by
the Auburn University “Policy on Class Attendance”. In case of absence, the student is responsible for all
course business conducted in class. Make-up exams will be scheduled for excused absences covered by
Paragraph 4 of the AU “Policy on Class Attendance”. There should be no distractive talking or cell phone
usage during class as well as no audio/video recording during class without prior approval of the instructor or
any other behavior deemed improper under Paragraph 1 the Auburn University “Policy on Classroom
Behavior”.
Accommodations: Students who need accommodations should arrange a meeting during office hours
within the first two weeks of classes, or as soon as possible if accommodations are needed
immediately. If you have a conflict with office hours given above, an alternate time can be
arranged. To arrange for this meeting, please contact me via e-mail. If you do not have an
Accommodation Memo but need accommodations, make an appointment with the Program for
Students with Disabilities, 1228 Haley Center, 844-2096.
Computer usage: VHDL modeling, simulation, and synthesis assignments will require the use of Mentor
Graphics and Xilinx ISE. Some information regarding these CAD tools is available on the ELEC 4200 class
web page link at www.eng.auburn.edu/~strouce.
Lab groups: Students may work alone or in groups of two (maximum) for the lab sessions. Lab partners must
be established by the first regular lab session (Lab #1) and continue with the same partner throughout the
entire semester. Lab partners are expected to contribute equally to the pre-lab and lab exercises as well as in
writing the lab report. Lab reports are due at the beginning of the lab session following the scheduled date
for that lab exercise.
Guidelines and format for lab reports: Lab reports are to be typed with a word processor such as MS Word
with figures, tables, and any hand drawings clearly labeled, attached, introduced and explained at the
appropriate point in the typed text portion of the lab report. All lab reports should include:
1. Title and number of lab session.
2. Name(s) of person(s) in lab group.
3. Goal of the lab session – this section should describe in detail the objective of the lab session in terms
was what was being designed and implemented and what skills are begin developed.
4. Design process – this section should describe in detail all of the the steps of the process used for the
complete design and implementation including both pre-lab and lab exercises.
5. Detailed design – this section should present and describe the details of the design (i.e., K-maps, state
diagrams/tables, logic equations, VHDL model). VHDL models should be described in terms of how
and what each portion of the VHDL code does.
6. Design verification – this section should provide a detailed explanation of the steps performed to verify
the design including simulation results as well as a detailed discussion of the thoroughness of the design
verification process during simulation. This section should also include a discussion of the design
verification process on the FPGA and whether the design implementation worked in the FPGA once
simulation based design verification was completed; if the design did not work, described why the
design error was not detected during simulation and what modifications to the simulation stimuli must
be made to detect and correct the design error.
7. Conclusions – this section should describe in detail what you learned from the lab session including
what went right and/or wrong, as well as what you would have done differently if you had the chance to
do the lab over again.