The International journal of analytical and experimental modal analysis ISSN NO: 0886-9367

CONTROLLING AND VOLTAGE BALANCING OF A NEW H-BRIDGE

HYBRID MODULAR CONVERTER (HBHMC) FOR HVDC
APPLICATION BY USING FUZZY LOGIC CONTROLLER
Paritala nagababu1 Dr.A.srinivasa reddy2 B.Sambasiva Rao3
1
PARITALA NAGABABU is pursuing his M.tech in power systems Control& Automation at Sir CR REDDY COLLEGE
OF ENGINEERING vatluru, eluru, West Godavari district. 2DR.A.SRINIVASA REDDY is working as HOD of EEE.dep
at Sir CR REDDY COLLEGE OF ENGINEERING. 3B.SAMBASIVA RAO is working as assistant professor at Sir CR
REDDY COLLEGE OF ENGINEERING.

Abstract: In this paper H-bridge hybrid modular Moreover, during a dc side fault, a high fault current
converter (HBHMC) with fuzzy logic controller is flows through freewheeling diodes connected across
proposed for HVDC applications. The operating modes each IGBTs in the MMC [5]-[17]. One of the
of HBHMC, novel modulation strategies for voltage approaches to tackle this problem is to use a dc
balancing of FBSMs, and control of HBHMC based circuit breaker as recently proposed in [14]-[17]. In
HVDC system is presented in this paper. It uses a wave-
the second approach, instead of the HBSM, another
shaping circuit (WSC) consisting of series-connected
SM with the capability to produce the opposite
full-bridge sub-modules (FBSMs) at the output of the
main H-bridge converter (MHBC). A detailed
polarity voltage is used that blocks/limits the fault
comparison between HBHMC and other hybrid current magnitude in case of dc side fault [18]-[22].
topologies is performed on the basis of required number In the third approach, the converter configuration
of switches and capacitors between PI and fuzzy itself is modified and by using the FBSMs, the fault
controller. The efficacy of the HBHMC based HVDC current limitation is achieved. This family of
system for three-phase balanced and unbalanced grid converters is called as the HMCs [23]-[34]. HMCs
conditions and its fault tolerant capability are validated consists of mainly two parts, a DS and a WSC. DSs
using PSCAD simulation studies. This paper shows the
are the series connection of semiconductor switches
comparative analysis between PI and FUZZY
and WSC is formed by connecting stacks of FBSMs
controller. This paper was implemented in
MATLAB/SIMULINK .
in series.

1.INTRODUCTION Among the HMCs, the HCMC has dc fault

tolerant capability, lower number of SMs in WSC
Modular multilevel converter is fast and quarter the number of SM capacitors to that in
becoming one of the most preferred topologies for MMC, which leads to smaller footprint and lower
VSC based HVDC transmission systems [1]-[4]. This losses [23]-[26], [30]. However, it has higher losses
is primarily due to its advantages like modularity, in the DSs because of hard switching and it requires
scalability, low conduction losses, low harmonic low order harmonic filters to mitigate low energy
filter requirement, and low dv/dt, which allows the spikes due to mis-synchronization of DSs and WSC
use of transformer with low insulation requirement. [24]. Moreover, for balancing of SMs capacitor
However, MMC has limitations such as, the voltages either more number of SMs are required or
requirement of a large number of devices and the DSs are required to switch at higher frequency,
capacitors, inability to block/limit fault current in the which leads to higher losses [24], [25], [31]. The
event of a dc side fault without using a dc circuit AAMMC, proposed in [27]-[29], has features like, dc
breaker, and the presence of circulating currents in fault tolerant capability, half the number of SMs to
each phase-leg of the MMC [5]-[10]. The circulating that in the MMC and lower losses. However, for the
current has a significant impact on the ratings of the smooth current commutation between upper and
converter components, capacitors voltage ripples and lower arms and for the capacitor voltage balancing in
power losses. A circulating current control is WSC, a short duration overlap period is required
necessary to reduce such impacts [11]-[13]. [31]. It creates a high inrush current in the arms and a

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suitably sized arm inductor is required for between the proposed and the other existing hybrid
suppressing this inrush current. The parallel hybrid converter topologies.
MMC is another promising topology for HVDC
applications because of lower component count and 2.H-BRIDGE HYBRID MODULAR
soft switching of DSs [33], [34]. However, its main CONVERTER
limitations are that it cannot block/limit dc fault
A. Single-phase configuration
current and it has lower order harmonics at the dc-
link. Due to these harmonics the dc voltage cannot be The proposed single-phase HBHMC is
regulated to a constant value, which compromises the shown in Fig. 1. Like other HMCs discussed in the
power control [34]. Recently, another HMC is previous section, this converter also has two main
proposed which uses the WSC across the load [35]. parts, a MHBC and WSC. The MHBC consists of
The DSs of this topology are operated diagonally four switches (DSx1-DSx4), which are series
when the output voltage is clamped to dc-link voltage connection of fully controllable semiconductor
value, thus allowing the energy exchange between switches to withstand high per phase dc-link voltage
the dc-link and FBSMs. This time period is small and (Vdcx). These switches are operated at the
in case of high active power requirement the fundamental frequency. The switches of MHBC
converter is required to take energy from dc-link direct the current either to the positive dc terminal,
within that small period, which may cause high negative dc terminal, or it freewheels either through
inrush current. Hence, it requires a dc side inductor DSx1 and DSx2 or through D Sx3 and DSx4. To
and circulating device to limit the inrush current. generate sinusoidal output voltage across the load,
Moreover, this converter does not have dc fault the WSC is used at the output of MHBC. The WSC is
tolerant capability. a series connection of FBSMs and these are switched
at a higher frequency. The WSC is responsible for the
This paper proposes an H-bridge hybrid
multilevel converter output voltage waveform
modular converter (HBHMC) topology, which
generation with very low distortion.
addresses some of the issues of the existing HMC
topologies as discussed above. The HBHMC The output voltage states of the MHBC can
topology has dc fault tolerant capability, small be either +Vdcx, 0, or –Vdcx as summarized in Table I.
footprint structure, high dc-link utilization, an extra For simplicity only two FBSMs are considered to be
degree of freedom for SM capacitor voltage connected in series with MHBC as shown in Fig. 1. If
balancing, and it can be extended to high voltage-low the voltage of each FBSM capacitor is regulated to
current or low voltage-high current applications. In Vdcx/2, five output voltage (Vx) levels (+Vdcx, +Vdcx/2,
this paper, the single phase and three phase HBHMC 0, -Vdcx/2, and -Vdcx) can be obtained. The different
structures, modes of operation of HBHMC, the WSC switching states for generating five voltage levels and
capacitor voltage balancing scheme by appropriately the corresponding states of capacitor voltages are
selecting powering and isolation modes, and summarized in Table II. The symbols ↑,↓ and →
individual capacitor voltage balancing scheme of indicate charging, discharging, and no change in
WSC SMs of HBHMC are presented. The efficacy of capacitor voltage, respectively.
the proposed voltage control schemes, modulation
and control of HBHMC and dc fault tolerant In Table II, the highlighted states are the
capability of the converter are validated using both additional switching states obtained compared to that
simulation and experimental studies. The detailed in the HCMC topology presented in [25], [26]. These
simulation studies of an HBHMC based HVDC states give an extra degree of freedom for the
system for various different operating conditions are capacitor voltage balancing of WSC in HBHMC.
carried out using PSCAD/EMTDC. The experimental This is because, for the same direction of current and
studies are performed using a three-phase grid for a given voltage level output, the SM capacitors
connected HBHMC hardware prototype. can be either charged or discharged in the desired
Furthermore, a comparative study is performed manner. This degree of freedom is not present in the
existing HCMC. Moreover, the

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B. Three-phase configuration

To obtain the three-phase output, three

HBHMCs (Fig. 1) can be connected either in series
(series-HBHMC) or in parallel (parallel-HBHMC).
(Figs. 2 (a) and (b)). The three MHBCs of the three-
phase converter operate at the fundamental frequency
with 120° phase displaced outputs with respect to
each other. For series-HBHMC, three separate dc
capacitors are required to equally divide the total dc-
link voltage (Vdct) such that 3Vdcx = Vdct (Fig. 2 (a)).
For series-HBHMC, the MHBC outputs are either +
Vdct /3, 0 or ‒ Vdct /3, and for the parallel-HBHMC
the outputs are + Vdct, 0 or ‒ Vdct (Figs. 2(a) and
2(b)). For an N number of series connected FBSMs
per phase in WSC, the series-HBHMC capacitor
voltage of each SM is regulated to Vdct /3N, and in
the parallel-HBHMC it is regulated to Vdct /N. These
converters are connected to an ac network through
three units of single-phase transformers. These
transformers are used

Fig. 2 (a) Illustration of a three-phase series H-bridge

hybrid modular converter (series-HBHMC), (b)
illustration of a three-phase parallel H-bridge hybrid
modular converter (parallel-HBHMC).

HBHMC provides full dc bus utilization compared to to provide isolation between the three-phase outputs
the HCMC topology [25], [26], which utilizes only of the converter and to match the ac and dc voltage
half of the dc- link voltage. levels [34]. As three separate transformers are used
for each phase, it eases the shipment of transformers

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and also reduces the spare holding requirements. complementary to DSx3 and DSx2 is complementary
These are important considerations for HVDC to DSx4. Similarly, Sj1is complementary to Sj3 and
applications [34]. As the series-HBHMC uses 1/3 of Sj2 is complementary to Sj4 in jth FBSM of the WSC.
Vdct for each phase, it is more suitable for the For N number of FBSMs in the WSC, if the capacitor
applications like tapping of existing HVDC lines voltage of each SM (Vcj) is Vdcx/N then depending on
[36], where the dc-link voltage is high and current is the switching states, the FBSM output voltage is
low. The parallel-HBHMC uses full Vdct for each either +Vdcx/N(positively inserted), ‒
phase. Hence it is more suitable for applications Vdcx/N(negatively inserted), or zero (bypassed),
requiring high current with low dc-link voltage like similar to as that in MHBC.
back to back HVDC system [32]and medium voltage 2) Isolation Mode:
dc transmission system [37]. In this mode, the dc voltage source is
bypassed and the output current freewheels through
C. Modes of operation MHBC. Henceforth, there is no power exchange
between dc-link and ac system. The equivalent circuit
The normal steady-state HBHMC operation can be
diagrams for isolation mode are shown in Figs. 3(c)
categorized into two operating modes depending on
and (d). These two switching states of MHBC can be
the MHBC switching states as explained below.
alternatively used to have uniform loss distribution
(1) Powering Mode: among the MHBC switches. The output voltage in
In powering mode, the output of MHBC is a square this mode is the negative of voltage across the WSC
wave and the WSC is responsible to obtain the (Figs. 3(c) and (d)) and given by,
multilevel output voltage waveform from the output Vx = -Vwscx …….(3)
of HBHMC. In this case, the dc-link is connected to
Where Vwscx is the voltage across WSC.
load through WSC and it supplies power to both
WSC and load. This mode is termed as powering It is clear from (1) and (3) that the output
mode because the energy is exchanged between the voltage can either be the difference of dc-link voltage
dc-link and the ac system. In this mode, for the and the voltage across WSC (powering mode) or just
positive half-cycle of output voltage DSx1 is on and be the voltage across WSC (isolation mode). Thus,
DSx2is off, and for the negative half-cycle DSx1is for the same number of output voltage levels in
off and DSx2is on. Here, x represents phase-a, b, or powering and isolation modes, if n number of FBSMs
c. In this mode, the phase-x converter output voltage of WSC are required to be positively inserted in the
(Vx) depends on the per phase dc-link voltage (Vdcx) powering mode then (N ‒ n) FBSMs of WSC should
and the voltage across WSC (Vwscx). For series- be negatively inserted in the isolation mode. This
HBHMC, Vdcx= Vdct/3 and for parallel-HBHMC, Vdcx implies that, for the same direction of load current
= Vdct. The equivalent circuit schematics for positive and for the same output voltage level, if n number of
and negative half-cycles of the powering mode are capacitors of WSC FBSMs are getting charged
shown in Figs. 3 (a) and (b), respectively. From Figs. (discharged) in powering mode, then the (N ‒ n)
1 and 3, Vx and Vwscx for N FBSMs in the WSC are capacitors of WSC FBSMs get discharged (charged)
expressed as, in isolation mode. This gives an extra degree of
freedom for capacitor voltage balancing of WSC
𝑉𝑥 = (𝐷𝑆𝑋1 − 𝐷𝑠𝑋2 )𝑉𝑑𝑐𝑥 − 𝑉𝑤𝑠𝑐𝑥 …..(1) SMs, which is achieved without the need of any
𝑁
additional SMs or any zero-sequence component
𝑉𝑤𝑠𝑐𝑥 = ∑(𝑆𝑗1 − 𝑆𝑗2 ) ∗ 𝑉𝑐𝑗 … … . (2) injection. In contrast to this, in HCMC since the
𝑗=1
isolation mode is not available the SMs capacitor
voltage balancing would require extra efforts in terms
where DSx1 and DSx2 are the switching states of the
of using more number of SMs or injecting third
MHBC upper switches of phase-x, Sj1and Sj2are the
harmonic component to the modulation signal [24],
switching states of the jth FBSM in the WSC and Vcj
[25], [31].
is the capacitor voltage of jth FBSM in the WSC of
phase-x of HBHMC. The MHBC switches DSx1 is

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Pwscx (t) = Vwscx (t)Ix (t)………(7)

1) Powering Mode:
From (1) and (4), the WSC voltage of phase-x for
powering mode of operation is expressed as

𝑉𝑤𝑠𝑐𝑥 (𝑡) = 𝑆𝑥 𝑉𝑑𝑐𝑥 − 𝑉𝑚 sin⁡(𝑤𝑡 + 𝜑1 )…..(8)

where Sx is 1 when DSx1is on and DSx2is off and it

is ‒1 when DSx1is off and DSx2is on. Substituting
the values of Ix and Vwscx from (5) and (8) in (7), the
instantaneous power of WSC of phase-x is calculated
as

𝑃𝑤𝑠𝑐𝑥 (𝑡) = (𝑆𝑥 𝑉𝑑𝑐𝑥

− 𝑉𝑚 sin(𝑤𝑡 + 𝜑1 ))𝐼𝑚 sin(𝑤𝑡
+ 𝜑1 − 𝜑2 ) … … (9)
Fig. 3 Equivalent circuit diagrams of HBHMC for
𝑃𝑤𝑠𝑐𝑥 (𝑡)
different modes of operation (a) positive half cycle of
𝑆𝑥
powering mode, (b) negative half cycle of powering sin((𝑤𝑡 + 𝜑1 − 𝜑2 ))
= 𝑉𝑚 𝐼𝑚 ( 𝑚𝑖 )
mode, (c) and (d) isolation modes. 1
3.CAPACITOR VOLTAGE BALANCING IN + (cos(2𝑤𝑡 + 2𝜑1 − 𝜑2 ) − 𝑐𝑜𝑠𝜑2 )
2
HBHMC
For satisfactory operation of converter it is necessary Integrating (10) over one fundamental cycle yields
to have the net active power absorption by WSC to the following expression of the energy exchange
be zero. At the same time the average capacitor between the WSC and the load (Wwscx).
voltages of each SMs of WSC should remain equal 2𝜋−𝜑1⁄
𝑤
and constant.
𝑊𝑤𝑠𝑐𝑥 = ∫ 𝑃𝑤𝑠𝑐𝑥 (𝑡)𝑑𝑥
A. Voltage balancing of WSC of HBHMC:
−𝜑1⁄
It is assumed that the converter output voltage 𝑤
𝑉𝑚𝐼𝑚 cos⁡(𝜑2 ) 4
quality is sufficiently good and the converter 𝑊𝑤𝑠𝑐𝑥 = [ − 𝜋]…(11)
𝑤 𝑚𝑖
switching effects are ignored. The converter phase-x It is clear from (11) that the energy exchanged by the
output voltage (Vx) can be expressed as, WSC is zero only when mi= 4/π. For mi other
𝑉𝑥 (𝑡) = 𝑉𝑚 sin(𝑤𝑡 + 𝜑1 ) … … … … (4) than4/π the energy exchanged by WSC is either
positive or negative, which will result in increase or
where Vm is the phase voltage amplitude, ω is the decrease of the WSC capacitor voltage, respectively.
angular frequency, ϕ1 is 0, ‒2π/3, and 2π/3 for phases To make the energy exchanged by WSC equal to zero
a, b, and c, respectively. The output current of phase- for mi < 4/π, the isolation mode of operation is
x of the converter is assumed to be sinusoidal with introduced.
the current amplitude of I m and with an arbitrary 2) Isolation Mode:
phase shift of ϕ2and is expressed as In this mode, the capacitors of WSC are
𝐼𝑥 (𝑡) = 𝐼𝑚 sin(𝑤𝑡 + 𝜑1 − 𝜑2 ) … … … … (5) only supplying power to the ac load and the dc source
is bypassed. From (3) and (4), the voltage across
The modulation index miof the HBHMC can be phase-x WSC can be expressed as
expressed as (Fig. 2), 𝑉𝑤𝑠𝑐𝑥 (𝑡) = −𝑉𝑚 sin⁡(𝑤𝑡 + 𝜑1 )…(12)
Substituting (5) and (12) in (7), the instantaneous
𝑉𝑚
𝑚𝑖 = … … … . . (6) power of phase-x of the converter in isolation mode
𝑉𝑑𝑐𝑥
The instantaneous power flowing through the WSC is calculated as
of phase x can be expressed as,

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𝑃𝑤𝑠𝑐𝑥 = (−𝑉𝑚 sin(𝑤𝑡 + 𝜑1 ))𝐼𝑚 sin(𝑤𝑡 + 𝜑1 the other hand, if Vavg is greater than Vrefavg then
− 𝜑2 ) … … … … (13) isolation mode is selected by turning on the MHBC
1 switches (either Dx1 and Dx2 or Dx3 and Dx4). The
𝑃𝑤𝑠𝑐𝑥 (𝑡) = 𝑉𝑚 𝐼𝑚 ( (cos(2𝑤𝑡 + 2𝜑1 − 𝜑2
2 mode selection is performed in the manner as shown
− 𝑐𝑜𝑠𝜑2 )) … … (14) in Fig. 4(a). The voltage waveforms at the different
Hence, the energy exchanged by WSC over one stages of converter are shown in Fig. 4(b). As the
fundamental cycle is calculated as converter operates in powering mode or isolation
mode, at least for half of the fundamental cycle the
2𝜋−𝜑1⁄
𝑊𝑤𝑠𝑐𝑥 = ∫−𝜑1⁄ 𝑤
𝑃𝑤𝑠𝑐𝑥 (𝑡)𝑑𝑡 = capacitors of WSC SMs continue to charge or
𝑤 discharge for half cycle although the average WSC
𝜋
− 𝑉𝑚 𝐼𝑚 𝑐𝑜𝑠𝜑2 …..(15) SMs voltage is changed from its initial state. Next
𝑤
It is clear from (15) that for the isolation change of mode is selected only at next zero crossing
mode the energy exchanged by WSC is always of output voltage. This increases the fluctuations of
negative regardless of the mi value for powering both capacitor voltages and hence capacitor value of WSC
the positive and negative half-cycles of output SMs [40]-[43]. Moreover, in this method during the
voltage. In the isolation mode the WSC supplies isolation mode, only WSC is generating output and
power to load by releasing the energy stored in its with N FBSMs the maximum output voltage obtained
FBSMs. By controlling the duration for which the from the WSC is Vdcx. This restricts HBHMC to
MHBC operates in isolation mode, depending on the operate in the over modulation region where the peak
current magnitude, the net energy exchanged by of per phase output voltage should be greater than
WSC in a fundamental cycle can be equated to zero Vdcx. Hence in this method additional SMs are
and hence the capacitor voltage balancing can be required for the HBHMC to operate in the over-
achieved. Thus, it is evident that the energy modulation region
exchanged by WSC can be controlled by
appropriately selecting powering and isolation modes
for 0 ≤ mi ≤ 4/π. For selecting one of these two
operating modes without increasing the switching
frequency of MHBC from fundamental, two
techniques (HCI and AZCI methods) for capacitor
voltage balancing are proposed. The detailed
description of these two methods is given below.
a) Half cycle isolation method:
In this method, depending upon the average
capacitor voltage of WSC, the HBHMC operates
either in powering mode or isolation mode. The mode
selection is carried at every zero crossing of output
voltage and the selected mode remains active for the
next half of the fundamental cycle. Thus the MHBC
operates at fundamental frequency, which keeps the
switching losses of MHBC to minimal. For the HCI
mode selection, as shown in Fig. 4(a), the average Fig. 4 HCI method; (a) Control block diagram for
capacitor voltage of the WSC SMs (Vavg) is obtained.
selecting isolation and powering modes, and (b)
At every zero crossing of the reference output voltage
Voltage waveforms at different stages of HBHMC.
(Vxref), this average capacitor voltage is compared
b) Across zero crossing isolation method:
with the reference capacitor voltage (Vrefavg), which is
In this method, instead of keeping the
set to the Vdcx/N. If Vavgis less than Vrefavg then the isolation mode active for complete half of the
powering mode is selected by turning on the MHBC
fundamental cycle, which increases the capacitor
switches Dx1and Dx4, Dx2and Dx3 for positive and
voltage fluctuation as discussed above, it is activated
negative cycles of output voltage, respectively. On

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only across the zero crossing of output voltage. A link capacitor of that phase is bypassed and only
control block diagram illustrating this method is WSC supplies power to load. In case of half cycle
shown in Fig. 5(a). In this method, to decide the time
duration for which the isolation mode is active the
average capacitor voltage of WSC (Vavg) is compared
with reference voltage (Vrefavg). This error is passed
through a PI controller as shown in Fig. 5(a) and
output of PI controller (e) is compared with output
voltage reference (Vxref) to obtain the isolation and
powering mode signals. The output voltage
waveforms of converter at different stages of
converter are shown in Fig. 5(b). The converter
output voltage (Vx) with reference to Fig. 1 is given
as
𝑉𝑥 = 𝑉𝐴𝐵𝑥 − 𝑉𝑤𝑠𝑐𝑥 …….(16)

where VABx is the output voltage of MHBC. Fig. 5 AZCI method; (a) Control block diagram for
VABxis +Vdcx for positive half cycle and –Vdcx for selecting isolation and powering modes, and (b)
negative half cycle. If the voltage across WSC is Voltage waveforms at different stages of HBHMC.
positive (positively inserted) in positive half cycle
and negative (negatively inserted) in the negative half Isolation (HCI) method, the isolation period
cycle then the output voltage will always be less than is active for half cycle. During this period the
Vdcx, i.e. the dc-link voltage for each phase. isolation modes of other two phases may or may not
However, if the voltage across WSC is negative in be active. For the series-HBHMC, during isolation
positive half cycle and positive in negative half cycle interval of one phase, if the other two phases are in
then the output voltage can be greater than Vdcx. powering mode (isolation modes are not active), the
This is because the WSC voltage gets added to the dc current flowing through dc-link capacitor of that
voltage to obtain the output voltage, as described phase (the phase for which isolation mode is active)
above by(16). As the maximum voltage across the is the sum of currents of other two phases. Thus this
WSC is kept at Vdcx, the converter operation can capacitor is handling two phase power. So the
ideally be extended up to the modulation index of 2. capacitor size requirement is more as compared to
However, to keep the net energy exchanged by WSC that in the converter operating without isolation mode
capacitors to be zero and hence maintain the [43]. However, for the across zero crossing isolation
capacitors voltage constant, as explained earlier in (AZCI) method, the isolation period is small and
Sec. IIIA, the maximum modulation index is occurs only across the voltage zero crossing. For a
restricted to 4/π. This indicates that, by using the three-phase system, the isolation period comes after
AZCI method the HBHMC can be operated in the every 60 degrees as shown in the Fig. 6. Fig. 6 shows
over modulation region without the need of the three-phase reference signals and corresponding
additional SMs in the WSC. isolation signals for AZCI method. In Fig. 6, when
In both HCI and AZCI methods, during the the isolation signal of a particular converter phase is
isolation period the load current is supplied by WSC high then that phase operates in the isolation mode.
and the dc-link capacitor is bypassed. For three-phase On the other hand, the corresponding converter phase
HBHMC, the isolation mode of operation for each operates in powering mode when its isolation signal
phase depends on the WSC capacitor voltage of that is zero. For small isolation period in the AZCI
particular phase and becomes active only if the WSC method the capacitor size requirement is less as
capacitor voltage is greater than the reference value. compared to the HCI method but more than the
Thus the isolation periods in all the three phases may capacitance requirement for system without isolation.
or may not be active simultaneously. When the
isolation period of a particular phase is active the dc-

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Fig. 6 Three-phase output voltage references

and corresponding isolation signals for AZCI
method.
B. Individual FBSM capacitor voltage balancing
in WSC
As explained in the previous subsection, it is
possible to keep the average capacitor voltage of
WSC constant b y properly selecting isolation and
powering modes of operation for HBHMC. However,
it does not guarantee equal capacitor voltages for all
FBSMs. At every change in the converter output Fig. 7. Flow chart of sorting and obtaining gate
voltage level when a SM is either required to be signals of FBSM of WSC.
inserted or bypassed, if any arbitrary SM is chosen manner as explained in the previous subsection.
then some of capacitors can get overcharged and Depending on the converter mode of operation the
some discharged as the energy will not be evenly WSC voltage reference signal (Vwscxref) is obtained.
distributed among all of them. To maintain each For powering mode of operation of the converter,
capacitors voltage equal, a sorting and insertion Vwscxref is obtained by subtracting the converter
technique for HBHMC is proposed with the flow output voltage reference signal (Vxref) from the
chart shown in Fig. 7. In this technique, all SMs MHBC output voltage reference (VABxref). For
capacitor voltages are first measured and they are isolation mode of operation V wscxref is the negative of
sorted in ascending or descending order as shown in Vxref (Figs. 3 ‒ 5). After obtaining the reference
Fig. 7. Then the converter mode selection is signal Vwscxref, it is compared with the phase-
performed in the disposed triangular carrier signals (since the phase
disposition strategy provides the lowest line-to-line
total harmonic distortion [38], [39]), to calculate the
required number of FBSMs to be inserted (n) in the
WSC. If Vwscxref is positive then n numbers of FBSMs
are inserted positively to obtain the desired positive
voltage across the WSC. Similarly, n FBSMs are
negatively inserted if Vwscxref is negative to obtain the
desired negative voltage across the WSC. Assuming
all the capacitor voltages are sorted from the low to
high value and the corresponding FBSMs are
numbered in ascending order then, depending on the
current direction, the insertion or bypassing of the
SMs are performed in the manner as illustrated in

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Fig. 7. Thus, this technique ensures equal charge Defuzzification: De fuzzification component of
distribution over all the SM capacitors. fuzzy logic converts the fuzzy data values into real
4.PROPOSED TOPOLOGY life data values after examining the fuzzy rules but
Fuzzy logic is a many valued logic in which truth these real-life data values depend upon the De
values of variables may be any real number between fuzzification method. Different methods are used for
0 and 1. This logic is employed for obtaining the De fuzzification process such center of gravity
partial truth between true and false values. If we (SOG), weighted average method, mean of maxima
compare it with Boolean logic then in Boolean logic (MOM) and smallest of maxima (SOM). Each
there are only two integer values 0 and 1 but in fuzzy method has different advantages and disadvantages.
logic system linguistic variables are used means non- These methods are set by the controller designer.
numeric values such as age temperature etc. with 5.HBHMC VALIDATION AND
their relative degrees and these degrees are managed APPLICABILITY TO HVDCSYSTEM
by membership function. A. Standalone mode
The fuzzy logic control system consists of three main To validate the effectiveness of the proposed
components, converter and its associated control schemes, a
Fuzzification: Fuzzification component consists of standalone model of series HBHMC with two
two further components that is called membership FBSMs (N = 2) per phase (Fig. 1) is simulated using
function and labels. Fuzzy logic controller converts PSCAD. The simulation parameters are listed in
input data or variable data into fuzzy membership Table III. The capacitance values of FBSMs and dc-
function according to user defined chart such as link are selected such that the maximum voltage
temperature is too cold, motor speed is too low and deviation is 10% of their respective reference voltage
assign the grade of this data value from 0 to 1. values [40]-[43], [45]. These capacitor values of SMs
Different shapes could be used for membership result in the capacitance energy storage of 25
function such as S, A, π and Z. A shape of kJ/MVA and 5.2 kJ/MVA for HCI and AZCI
membership functions with labels such as low, methods, respectively. Moreover, this also results in
medium and very low. the dc-link capacitance energy storages of 15.75
Inference Mechanism: Inference mechanism kJ/MVA and 12 kJ/MVA for HCI and AZCI
component of fuzzy logic control system consists of methods, respectively. Thus, the capacitance energy
fuzzy rules which are settled by controller designer storage is higher for HCI method as compared to
shown in figure 2. Based on these fuzzy rules, AZCI method as discussed earlier in Sec. III A. It is
controller decided the output of fuzzy logic also clear from these values that a significant
controller. This is the main intelligent control of this reduction in the net capacitance
system.

a)

energy storage requirement is achieved in the

b) proposed converter controlled using the AZCI
Fig 8. a) member ship functions of input ID .b) method as compared to that in the MMC, which
Membership function for Input Iq

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requires the capacitance energy storages of 39 output voltage and current waveforms are shown in
kJ/MVA [43]. Figs. 10(a) and (b), respectively. Here, the AZCI
The series-HBHMC is operated with mi= method is used for controlling the WSC capacitors
0.95 and with a passive R-Lload of 0.9 power factor voltage. The modulation signals for phase-a using the
at 50 Hz. The converter modulation is performed AZCI method are shown in Fig. 10(c). It can be
using PDPWM technique [38], [39], with a carrier observed from Fig. 10(c) that around the peak of
frequency of 2 kHz. Figs. 8 and 9 show the output voltage reference, the reference signal of WSC
simulation results of series-HBHMC system is negative in the positive half cycle and positive in
controlled using the HCI (Fig. 4), and the AZCI the negative half cycle of output voltage reference.
methods (Fig. 5), respectively. It can be observed This is done to obtain the converter output voltage
from these waveforms that the proposed control greater than Vdcx, as explained earlier in Sec. III-A
schemes are able to effectively balance the capacitor (Fig. 5). It can be seen From Fig. 10 (a) that the
voltages and hence distinct five-level phase-voltage number of output voltage levels has increased from
waveforms are generated at the converter output. The five (for mi ≤ 1) to seven because of the over
series-HBHMC output voltage and output current modulation mode of operation. Moreover, the
waveforms using the two abovementioned proposed converter output voltage magnitude has also
control schemes are plotted in Figs. 8(a) and 9(a) increased as can be seen by comparing Fig. 10 (a)
respectively. Figs. 8(b) and 9(b) show the modulation with Figs. 8 (a) and 9 (a). It is also to be noted that,
signals used to obtain gate pulses for the FBSMs in like in the under modulation region (mi ≤ 1), in the
HCI and AZCI methods, respectively (Sec. III). It can over modulation region too (mi> 1), the WSC is
be seen from Figs. 8(b) and 9(b) that, as discussed in modulated at the frequency of
the previous section (Figs. 4 and 5), the isolation
period is active over half cycle for HCI method and
across zero crossing for AZCI method, respectively.
The switching signals of the upper two switches
(DSx1and DSx2) of MHBC for HCI and AZCI
methods are shown in Figs. 8(c) and 9(c),
respectively. The switch DSx3 is complimentary to
DSx1and DSx4is complimentary to DSx2. It can be
seen from Figs. 8(c) and 9(c) that the MHBC
switches are switched at the fundamental frequency
(50Hz in this case), which helps in keeping the
switching losses of the converter to minimal. Figs.
8(d) and 9(d) show the capacitor voltages of WSC
with and without the proposed voltage control
scheme for HCI and AZCI methods, respectively.
With reference to Figs. 8(d) and 9(d), in the initial
period of the simulation the HBHMC is operated Fig. 8 Waveforms of HBHMC using HCI method (a)
without using the proposed capacitor voltage control Output voltage and current waveforms, and (b)
methods, and at t1 the proposed voltage controllers Modulation signals for HCI method, (c) switching
are activated. It can be observed that the WSC signals of MHBC, and (d) individual capacitor
capacitor voltages tend to become unbalanced when voltages of WSC.
the control is inactive and they settle at the reference
value (half of the per phase dc-link voltage, i.e., 75
V) after the control is activated, which validates the
effectiveness of the proposed control techniques.
To validate the overmodulation capability of
HBHMC, the series-HBHMC is simulated for mi=
1.2 and the corresponding three-phase converter

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FBSMs per phase with the voltage rating of 5 kV

(Vdct/3N).The control of HBHMC based HVDC
system can be sectionalized in three different layers,
i.e., inner, intermediate and outer control layers, as
shown in Fig. 11 (b) [26], [30]. The outer control
layer includes the dc-link voltage (or active power)
controller and the reactive power (or ac voltage)
controller. These controllers provide the reference
values to the current controllers in the intermediate
control layer. As it is known that in a VSC-HVDC
system one of the converter stations is controlled to
follow an active power flow reference while the other
station is controlled to regulate the dc-link voltage
around its reference value. Therefore, depending on
Fig. 9. Waveforms of HBHMC using AZCI method the converter station under consideration, the current
(a) output voltage and output current waveform, (b) reference 𝑖 𝑑 ∗ is generated either by an active power
Modulation signals for ACZI method, (c) switching
controller or the dc-link voltage controller. Another
signals of MHBC, and (d) Individual capacitor
current reference 𝑖 𝑞 ∗ is generated either by the ac
voltages of wave shaping circuit.
voltage controller or by the reactive power controller.
In the intermediate control layer, the reference
currents output from the external control layer are
compared with their actual values, id and iq,
respectively and the errors are processed through PI
controllers. The outputs of this control layer are Vd
and Vq, which when converted back to the abc frame
provides the modulation signals for the converter.
The inner control layer is the capacitor voltage
control technique proposed earlier in Sec. III. Here,
Fig. 10. Series-HBHMC operating at mi= 1.2 (a) the AZCI method is used to control WSC capacitor
three-phase output voltage waveforms and, (b) three- voltage because of its advantages over HCI method,
phase output current waveforms (c) modulation such as, smaller value of submodules capacitance and
signals for ACZI method. overmodulation capability. This control layer
balances the overall capacitor voltage and individual
the carrier signals, as can be seen from Figs. 8-10. SM capacitor voltages and generates the gate pulses
Hence the converter output voltage waveform quality for WSC SMs and MHBC. The control scheme
does not deteriorate even in the overmodulation shown in Fig. 11 (b) can also be used for parallel-
region. HBHMC based HVDC system.
The simulation results presented in Figs. 8- 1) Series-HBHMC HVDC System Operation:
10 validate the efficacy of the proposed control The series-HBHMC HVDC system of Fig.
techniques and the operation of series-HBHMC. The 11(a), with the different control layers shown in Fig.
parallel-HBHMC can also be simulated using the 11(b), is simulated for a balanced three-phase system
proposed control techniques to obtain similar results. to test its performance under active and reactive
B. Applicability of series-HBHMC for HVDC system power control and power reversal modes of operation
To test the proposed HBHMC for HVDC application in this subsection. At converter station 1 (CS1), the
a test model is built in PSCAD/EMTDC using series- active and reactive power outputs of the converter are
HBHMC with the schematic shown in Fig. 11(a). The being controlled, while at converter station 2 (CS2),
simulation parameters are listed in Table IV. The dc- the dc-link voltage and the reactive power control
link voltage (Vdcx, Fig. 2 (a)) for each phase of actions are being implemented. Fig. 12 shows the
converter is 50 kV (Vdct/3). The converter uses 10 simulation results obtained when, at t= 0.5 s, the

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active power flow direction of CS1 is reversed, i.e. 𝑃

𝑠 ∗ is changed from ‒150MW to +150 MW. The
change rate of 𝑃 𝑠 ∗ is 1.2 MW/ms. The resulting
active power waveforms at the output terminals of
CS1 and CS2 are shown in Fig. 12(a). The
corresponding three-phase ac output currents are
shown in Fig. 12(b). Figs. 12(c) and 12(d) show the
dc-link capacitor voltages ofCS1 and CS2,
respectively. These
capacitor voltages are equal to one third of the total
dc-link voltage. Moreover, the phase-a WSC
capacitor voltage waveforms of CS1 and CS2 are
shown in Figs. 12(e) and 12(f), respectively. It can be
observed from Fig. 12 that the power reversal is
achieved with minimum transients in ac output
currents, dc-link capacitor voltages, and WSC
capacitor voltages of the converter. At t = 1.0 s, the
reactive power reference of CS1 (𝑄 𝑠 ∗ ) is changed
from ‒100MVAr to +100 MVAr, with 1.2 MVAr/ms
slope. The waveforms of active and reactive powers
at the output terminals of CS1 are shown in Fig. 14(a)
and the corresponding dc-link capacitor voltage
waveforms and phase-a WSC capacitor voltage
waveforms are shown in Figs. 14(b) and 14(c),
respectively. Similarly, at t = 1.5 s, the reactive
power reference of CS2 is changed from +100MVAr
to ‒100MVAr and resulting waveforms of active and
reactive powers at the converter output terminals, dc-
link capacitor voltage waveforms, and phase-a WSC
capacitor voltages of CS2 are shown in Figs. 15(a),
15(b), and 15(c), respectively. The results shown in
Figs. 12, 14, and 15 verify the effectiveness of the
proposed control schemes and satisfactory
performance of the HBHMC based HVDC system in
response to the active and reactive power reversal
commands. It is also observed that the FBSMs
capacitors voltages are well regulated and balanced at
their reference values in all cases.
2) Control of series-HBHMC HVDC System
under dc fault condition:
One of the important characteristics of
HBHMC is its ability to block dc fault current. As the
Fig. 11. (a) Schematic of HVDC system (b) Control HBHMC uses FBSMs, it is possible to apply an
block diagram of converter for HVDC system opposite polarity voltage in the event of a dc side
fault, thereby limiting/blocking the fault current
magnitude. The intended ability of the HBHMC to
block the dc fault current is tested for the worst case
scenario by creating a pole-to-pole dc side fault (Fig.
11). As soon as the fault is detected the IGBTs are

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turned off. The resulting equivalent circuits for operating conditions are restored using the control
positive and negative half-cycles of the grid voltage action (Fig. 11 (b)) after the fault is cleared.
are shown in Figs. 15 (a) and (b), respectively. In It can be concluded from above that even
both these cases, for the chosen system parameters though the test system is subjected to the most severe
(Table IV), since the net WSC capacitor voltage is type of dc fault, the ac grid contribution to the dc side
greater than the grid voltage, the antiparallel diodes fault current is blocked by the converter control
connected across the IGBTs in the WSC get reverse action and the risk of converter failure because of
biased (Fig. 15) and hence the flow of current is high current stresses is reduced.
ceased. Fig. 16 shows the results when the system is 3) Control of series-HBHMC HVDC System
subjected to the pole-to-pole dc fault (Fig. 11(a)). under grid voltage unbalance condition:
Before the fault occurrence the system of Fig. 11(a) In the previous sections, the simulations of
is in steady state condition and is controlled to HBHMC were presented by assuming balanced
operate with 𝑃 𝑠 ∗ = 150 MW and 𝑄 𝑠 ∗ = 100 MVAr three-phase grid conditions. With reference to the
at CS1 (Fig. 11 (b)). It can be seen from Fig. 16(a) series-HBHMC circuit (Fig. 2 (a)), the three dc
that the corresponding CS1 power references are capacitor voltages (Vdca, Vdcb, Vdcc) of the three
being tracked before 0.5 s in the simulation run. At t PI controller results
= 0.5 s, a dc side pole-to-pole short circuit fault is
created, which lasts for 200 ms. Following the fault
occurrence, it can be observed from Fig. 16 (a) that
the active and reactive powers exchange between the
converter and ac grid reduces to zero. This is because
of turning off of all of the converter switches, which
consequently activates the converter inherent dc fault
blocking capability as can be observed from the
resulting equivalent circuit shown in Fig. 15. It can
further be seen from Fig. 16 (b), where the converter
three-phase current waveforms are plotted, that the
converter phase currents are reduced to a very small
value during the fault condition. This confirms the
effectiveness of the proposed converter in blocking
the dc fault current. Fig. 16 (c) shows the converter
dc side voltage, which expectedly collapses to zero
during the fault period. Fig. 16 (d) shows the
capacitor voltages of FBSMs in phase-a, which have
negligible ripple and remain constant because the
current is blocked. After the fault is cleared at t = 0.7
s, the gating signals of switches of both the converter
stations are de-blocked and the reference power
settings (𝑃 𝑠 ∗ , 𝑄 𝑠 ∗ , Fig. 11 (b)) are ramped up
gradually from 0 to the pre-fault values. This allows
the converter active and reactive powers exchange
with the grid to be ramped up gradually from zero to
their pre-fault values as can be seen from Fig. 16 (a).
It can be observed from Fig. 16 (b) that the converter
experiences inrush currents for a short period of time
when the converter is de-blocked. These relatively
higher value of current flows because of the charging
of dc-link capacitors after the fault is cleared. It can
also be observed from Fig. 16 that the pre-fault

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f)
Fig.12. Responses of converter for HVDC system Fig.13. Responses of converter for HVDC system
when active power flow is reversed from -150MW to when active power flow is reversed from -150MW to
150MW at CS1 (a) active power at CS1 and CS2, (b) 150MW at CS1 (a) active power at CS1 and CS2, (b)
three-phase ac grid currents at CS1, (c) CS1 dc-link three-phase ac grid currents at CS1, (c) CS1 dc-link
voltages, (d) CS2 dc-link voltages, (e) capacitor voltages, (d) CS2 dc-link voltages, (e) capacitor
voltages of FBSMs of WSC of phase-at CS1, and (f) voltages of FBSMs of WSC of phase-at CS1, and (f)
capacitor voltages of FBSMs of WSC of phase-at capacitor voltages of FBSMs of WSC of phase-at
CS2. CS2
FUZZY controller results

a)

b)

Fig.13.(a) Active and reactive power waveforms of

CS1 when reactive power is changed from -100MW
C) to 100MW, (b) dc-link capacitor voltages, and (c)
capacitor voltages of WSC.

d)

e)

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Fig. 16. Responses of CS1 when dc fault occurs

during 0.5 to 0.7 sec (a) active and reactive power at
the time of dc side fault, (b) ac current during dc side
fault, (c) dc-link voltage during dc fault, and (d)
FBSM capacitor voltages of phase-a. Individual
phases, would depend on the respective magnitudes
of power transferred to the grid.
Fig.14.(a) Active and reactive power waveforms of
CS2 when reactive power is changed from 100MW WITH FUZZY RESULTS
to -100MW, (b) dc-link capacitor voltages, and (c)
capacitor voltages of WSC.

a)

Fig.15 HBHMC during dc fault, (a) Single-phase

equivalent diagram of HBHMC for positive grid
voltage,(b) Single-phase equivalent diagram of
HBHMC for negative grid voltage. b)

c)

d)
Fig. 17. Responses of CS1 when dc fault occurs
during 0.5 to 0.7 sec (a) active and reactive power at
the time of dc side fault, (b) ac current during dc side
fault, (c) dc-link voltage during dc fault, and (d)
FBSM capacitor voltages of phase-a. Individual
phases, would depend on the respective magnitudes
of power transferred to the grid.

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For a balanced three-phase system the power

transferred by each phase is same and equal to one
third of the total power transferred. Hence, the dc
capacitors would be having the same average steady
state voltage values. However, in certain conditions,
the grid voltage can be unbalanced. In such cases the
control scheme presented in [46]-[47]can be applied
for the HBHMC. In the simulation study presented
here, to control the WSC capacitor voltages the AZCI
method, as explained earlier in Section III, is used. In
order to investigate the transient response of the dc-
link capacitor voltages of the series-HBHMC under
unbalance grid voltage, the phase-a grid voltage is
reduced to one third of its nominal value at t= 2.0 s
and it lasts for 3 s. Figs. 18 and 19 show the transient
behavior of the system during the grid voltage
unbalance. Fig. 18 (a) shows the three-phase grid
voltages following the event of occurrence of
unbalance at t = 2.0 s. When the HBHMC is
subjected to the grid voltage unbalance and no post-
unbalance control is activated (i.e., from t = 2.0 to 3.0
s), the ac-side currents (Fig. 18(b)) and dc capacitor
voltages (Fig. 19(b)) of the series-HBHMC become
unbalanced before t= 3.0 s. This is due to the Fig. 18. (a) Unbalance in grid voltage at t = 2.0 s, (b)
presence of nonzero negative sequence current grid currents when positive and negative current
components. Thus, in the proposed grid-connected control is activated at t = 3.0 s, and (c) grid currents
series-HBHBMC, there are two control objectives to when dc capacitor voltage control is activated at t =
be exercised in order to deal with this issue. The first 4.0 s.
objective is to make the converter output current
balanced and the second is to equalize the dc
capacitor voltages of each phase. The converter
current can be balanced by introducing a negative
sequence current controller, as described in [47]for
the modular multilevel converter. A similar control
scheme has been implemented in the presented work
for the same objective and it can be seen from Fig.
18(b) that as soon as the said controller is applied at
t= 3.0 s in the simulation run, the converter currents
attain balanced condition. When the pos tun balance
control is active, the negative sequence current
components are reduced to zero and the ac-side
currents of Fig. 18(b) are balanced. It can be seen
from Figs. 18(b) and 19(b) that although the ac side
currents remain balanced by the virtue of a negative
sequence current controller, the dc-link capacitor
voltages are still unbalanced (i.e., from t= 3.0 to 4.0
s). Similar issue of unbalanced dc capacitor voltages
for parallel hybrid

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e)

Fig. 19. Responses of the series-HBHMC to ac side

unbalance voltage: (a) active and reactive power, (b)
dc-link capacitor voltages, and (c) average values of
WSC capacitor voltages.

f)
Fig. 21. Response of the series-HBHMC to ac side
FUZZY RESULTS
unbalances voltage: (a) active and reactive power,
(b) dc-link capacitor voltages, and (c) average
values of WSC capacitor voltages
Converter was discussed in [46] and a third
harmonic injection based control scheme was used
a) for balancing the dc capacitor voltages under similar
unbalanced grid conditions. Therefore, in order to
equalize these dc capacitor voltages of the proposed
series-HBHMC a control technique similar to the one
discussed in [46]is used. It can be observed from Fig.
18(b) that as soon as the said controller is activated at
t= 4.0 s in the simulation run, the capacitor voltages
b) are equalized. Fig. 17(c) also demonstrates that the
converter current remain balanced after the activation
of both the additional controllers. Hence both the
control objectives have been fulfilled. Fig. 18(c)
shows the average values of three-phase WSC
capacitor voltages, which validates the effectiveness
c) of the proposed voltage control technique (AZCI
Fig. 20 (a) Unbalance in grid voltage at t = 2.0 s, (b) method) even under unbalance grid conditions. Fig.
grid currents when positive and negative current 18(a) shows the active and reactive power transferred
control is activated at t = 3.0 s, and (c) grid currents by the HBHMC to grid. The active and reactive
when dc capacitor voltage control is activated at t = powers are reduced because the current references are
4.0 s. limited to avoid over current in the converter
6.COMPARISION BETWEEN PROPOSED AND
EXISTING METHOD
As we have discussed earlier, Existing method is PI
controller HVDC circuit and proposed method is
Fuzzy Controlled HVDC circuit.

Figure 12 (c) & (D) and Figure 13 (c) & (D) shows
d)
the DC-link voltages of the CS1 and CS2
respectively. Fluctuations in Figure 12 are more
compared with figure 13, so calculation of error and
rectification is less efficient with PI controller.

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Figure 16(a) & 17(a) shows the Active power and VSC-based dc network cables,” IEEE Trans. Ind.
reactive power and Figure 16(d) &17(d) shows Electron., vol. 59, no. 10, pp. 3827-3837, Oct. 2012.
voltage across capacitor. Gradual increment of Active [8] K. Friedrich, “Modern HVDC PLUS application
power shown in 16(a), whereas Sudden incremental of VSC in modular multilevel converter topology,” in
in 17(a).High voltage fluctuation in 16(d) & less Proc. IEEE Int. Symp. Ind. Electron., 2010, pp. 3807-
voltage fluctuation in 17(d). 3810.
Figure 19 and 21 describes about results in PI and [9] C. M. Franck, “HVDC circuit breakers: a review
Fuzzy. Figure 19 (d) & (e) having more fluctuations identifying future research needs,” IEEE Trans.
as compared with figure 21 (d) & (e) Power Delivery, vol. 26, no. 2, pp. 998-1007, April
In above comparison Fuzzy controller showing less 2011.
fluctuations as compared with PI. Because of writing [10] X. Q. Li, Q. Song, W. H. Liu, H. Rao, S. K. Xu
membership functions and execution of rules, error and L. C. Li, “Protection of nonpermanent faults on
calculation is make ease to controller and it calculates dc overhead lines in MMC-based HVDC systems,”
with accuracy. As we know as accuracy increases IEEE Trans. Power Delivery, vol. 28, no. 1, pp. 483-
efficiency increases. 490, Jan. 2013
CONCLUSION [11] Q. Tu , Z. Xu and L. Xu, “Reduced switching-
frequency modulation and circulating current
Application of Fuzzy controller in H-Bridge hybrid suppression for modular multilevel converters”, IEEE
multilevel topology was done. Better Results were Trans. Power Del., vol. 23, no. 3, pp.2009 -2017
observed with Fuzzy controller than PI. Fluctuations 2011.
in voltage across dc-link were reduced. [12] R. Picas, J. Pou, S. Ceballos, V. G. Agelidis, and
M. Saeedifard, “Minimization of the capacitor
REFERENCES
voltage fluctuations of a modular multilevel
[1]A. Lesnicar and R. Marquardt, “An innovative
converter by circulating current control,” in Proc.
modular multilevel converter topology suitable for a
IEEE Industrial Elect. Conf. (IECON), Montreal,
wide power range,” inProc. Power Tech Conf., 2003,
June 2012, pp. 25-28.
Vol. 3, pp.1-6.
[13] P. Josep, S. Ceballos, G. Konstantinou, V. G.
[2] S. Allebrod, R. Hamerski, and R. Marquardt,
Agelidis, R. Picas, and J. Zaragoza, “Circulating
“New transformer less, scalable modular multilevel
current injection methods based on instantaneous
converters for hvdc-transmission,” inProc. IEEE
information for the modular multilevel converter,”
Power Electron. Specialists Conf., 2008, pp. 174–
IEEE Trans. on Indust. Elect., vol. 2, pp.777-788,
179.
2015.
[3] J. Dorn, H. Huang, and D. Retzmann, “Novel
[14] Y. Wang and R. Marquardt, “Future HVDC-
voltage sourced converters for hvdc and facts
grids employing modular multilevel converters and
applications,” inProc. CIGRE, Osaka, Japan, 2007.
hybrid dc-breakers,” inProc. 15th European Conf. on
[4] R. Marquardt, “Modular multilevel converter: an
Power Electron. and Appl. (EPE), Sep. 2013, pp. 1-8.
universal concept for hvdc-networks and extended
[15] A. Shukla and G. D. Demetriades, “A survey on
dc-bus-applications,” in Proc. Int. Power Electron.
hybrid circuit-breaker topologies,” IEEE Trans.
Conf., 2010, pp. 502–507.
Power Del., Vol. 30, no. 2, pp. 627-641, 2015.
[5] L. X. Tang and B. T. Ooi, “Locating and isolating
[16] P. van Gelder and J. Ferreira, “Zero volt
dc faults in multiterminal dc systems,” IEEE Trans.
switching hybrid dc circuit breakers,” inProc. IEEE
Power Del., vol. 22, no. 3, pp. 1877-1884, Jul. 2007.
Ind. App. Conf., 2000, pp. 2923–2927.
[6] R. Marquardt, “Modular multilevel converter
[17] J. H¨afner and B. Jacobson, “Proactive hybrid
topologies with dc-short circuit current limitation,” in
HVDC breakers-a key innovation for reliable HVDC
Proc. IEEE Power Electron. And ECCE Asia, 2011,
grids,” Cigr`e Symposium, Sep. 2011.
pp. 1425-1431.
[18] S. Debnath, J. Qin, B. Bahrani, M. Saeedifard,
[7] J. Yang, J. E. Fletcher and J. O. Reilly, “Short-
and P. Barbosa, “Operation, control, and applications
circuit and ground fault analyses and location in
of the modular multilevel converter: a review,” IEEE

Volume XI, Issue VIII, August/2019 Page No:601

The International journal of analytical and experimental modal analysis ISSN NO: 0886-9367

Trans. Power Electron., vol. 30, no. 1, pp. 37–53, Montreal, QC, 2015, pp. 6790-6797. [29] E. C.
2015. Mathew, A. Shukla, “Modulation, control and
[19] R. Zeng, L. Xu, L. Yao, & B. W. Williams, capacitor voltage balancing of alternate arm modular
“Design and operation of a hybrid modular multilevel multilevel converter with dc fault blocking
converter,” IEEE Trans. Power Electron., vol. 30, no. capability,” in proc. Applied Power Electron. Conf.
3, pp. 1137-1146, March 2015. [20] G. P. Adam, & I. and Exp. (APEC),2014 , pp. 3329 –3336
E. Davidson, “Robust and generic control of full- [30] G. P. Adam, S. J. Finney, and B. W. Williams,
bridge modular multilevel converter high-voltage dc “Hybrid converter with ac side cascaded H-bridge
transmission systems,” IEEE Trans. Power Delivery, cells against H-bridge alternative arm modular
vol. 30, no. 6, pp. 2468-2476, Dec. 2015. multilevel converter: Steady-state and dynamic
[21] R. Zeng, L. Xu, & L. Yao, “An improved performance,” IET Generat., Transmiss. Distrib., vol.
modular multilevel converter with dc fault blocking 7, no. 3, pp. 318–328, Mar. 2013. [31] E. Mathew,
capability,” inProc. PES General Meeting Conf. & M. Ghat, and A. Shukla, “A generalized cross-
Exp., 2014 IEEE, National Harbor, MD, 2014, pp. 1- connected submodule structure for hybrid multilevel
5. converters,” IEEE Trans. Ind. Appl., vol. 52, no. 4,
[22] J. Qin, M. Saeedifard, A. Rockhill and R. Z.,, pp. 3159-3170, July-Aug. 2016.
“Hybrid design of modular multilevel converters for [32] G. P. Adam, I. A. Abdelsalam, K. H. Ahmed, B.
HVDC systems based on various submodule W. Willians, “Hybrid multilevel converter with
circuits,” IEEE Trans. Power Del., vol. 30 no. 1, pp. cascaded H-bridge cells for HVDC applications:
385–394, 2015. operating principle and scalability,” IEEE Trans.
[23] L. Yun-Feng, Z. Zheng-Ming, Q. Chang, Z. Power Electron., Vol. 30, no. 1, pp. 65-77, Jan. 2015.
Xigen, “A novel three-phase multilevel voltage [33] R. Feldman, M. Tomasini, J. C. Clare, P.
source converter,” in proc. The Third Int. Power Wheeler, D. R. Trainer, and R. S. Whitehouse, “A
Electron. And Motion Control Conf., 2000, vol. 3, hybrid voltage source converter arrangement for
pp. 1172-1175. HVDC power transmission and reactive power
[24] Y. Zhang, G. Adam, S. Finney, and B. Williams, compensation,” inproc. Power Elect. Machines and
“Improved pulse width modulation and capacitor Drives (PEMD 2010), 5th IET International Conf.,
voltage-balancing strategy for a scalable hybrid 2010, pp. 1-6.
cascaded multilevel converter,” IET Power Electron., [34] J. Qin, M. Saeedifard, “A zero-sequence voltage
vol. 6, no. 4, pp. 783–797, 2013 injection based control strategy for a parallel hybrid
[25] Y. Xue, Z. Xu, and Q. Tu, “Modulation and modular multilevel HVDC converter system,” IEEE
control for a new hybrid cascaded multilevel Trans. Power Del.,vol. 30, no. 2, pp. 728-736, April
converter with dc blocking capability,” IEEE Trans. 2015.
Power Delivery, vol. 27, no. 4, pp. 2227–2237, 2012. [35] P. Li, G. P. Adam, D. Holliday and B. Williams,
[26] G. Adam, K. Ahmed, S. Finney, K. Bell, and B. “Controlled transition full-bridge hybrid multilevel
Williams, “New breed of network fault-tolerant converter with chain-links of full-bridge cells,” IEEE
voltage-source-converter HVDC transmission Tran. Power Elect., vol. 32, no. 1, pp. 23-38, 2017.
system,” IEEE Trans. Power Systems, vol. 28, no. 1, [36] Jovcic, Dragan, and Boon Teck Ooi. “Tapping
pp. 335–346, 2013. on hvdc lines using dc transformers,” inproc. Elec.
[27] M. M. C. Merlin, T. C. Green, P. D. Mitcheson, Power Systems Research,2011, pp. 561-569.
D. Trainer, W. Critchley, R. Crookes, and F. Hassan, [37] V. Yaramasu, B. Wu, P. C. Sen, S. Kouro and
“The alternate arm converter: a new hybrid multilevel M. Narimani, "High-power wind energy conversion
converter with dc-fault blocking capability,” IEEE systems: state-of-the-art and emerging technologies,"
Trans. Power Del., vol. 29, no. 1, pp. 310–317, 2014. in Proc. of the IEEE, vol.103, no.5, pp.740-788, May
[28] V. Najmi, R. Burgos, & D. Boroyevich, “Design 2015.
and control of modular multilevel alternate arm [38] B. P. McGrath, & D. G. Holmes, “Multicarrier
converter (AAC) with zero current switching of PWM strategies for multilevel inverters,” IEEE
director switches,” inproc. Energy Conversion Trans. Ind. Electron., vol. 49, no. 4, pp. 858-867, Aug
Congress and Exposition (ECCE), 2015 IEEE, 2002.

Volume XI, Issue VIII, August/2019 Page No:602

The International journal of analytical and experimental modal analysis ISSN NO: 0886-9367

[39] G. Carrara, S. Gardella, M. Marchesoni, R.

Salutari, & G. Sciutto, “A new multilevel PWM
method: A theoretical analysis,” in proc. Power
Electron. Specialists Conf., 1990, pp. 363-371. [40]
M. Zygmanowski, B. Grzesik and R. Nalepa,
“Capacitance and inductance selection of the modular
multilevel converter,” in proc.Power Elect. and Appl.
(EPE), Lille, 2013, pp. 1-10.
[41] J. Peralta, H. Saad, S. Dennetière, J.
Mahseredjian, and S. Nguefeu, “Detailed and
averaged models for a 401-level MMC-HVDC
system,” IEEE Trans.on Power Del., vol. 27, no. 3,
pp. 1501–1508, Jul. 2012.
[42] K. Ilves, S. Norrga, L. Harnefors, and H. P. Nee,
“On energy storage requirements in modular
multilevel converters,” IEEE Trans.on Power Elect.,
vol. 29, no. 1, pp. 77–88, Jan. 2014.
[43] M. M. C. Merlin and T. C. Green, “Cell
capacitor sizing in multilevel converters: cases of the
modular multilevel converter and alternate arm
converter,” IET Power Electron., vol. 8, no. 2, pp.
350–360, Mar. 2015.
[44] W. Merwe, “Natural balancing of the 2-cell
modular multilevel converter,” IEEE Trans. Ind.
Appl., vol. 50, no. 6, pp. 4028–4035, 2014.
[45] Y. M. Chen, C. H. Chang and H. C. Wu, “DC-
link capacitor selections for the single-phase grid-
connected PV system,” 2009 International Conf. on
Power Electr. and Drive Systems (PEDS), Taipei,
2009, pp. 72-77.
[46] E. K. Amankwah, A. J. Watson and J. C. Clare,
“Operation of a hybrid modular multilevel converter
during grid voltage unbalance,” IET Generat.,
Transmiss. Distrib, vol. 10, no. 12, pp. 3102-3110,
Feb-2016.
[47] M. Saeedifard and R. Iravani, “Dynamic
Performance of a Modular Multilevel Back-to-Back
HVDC System,” in IEEE Transactions on Power
Delivery, vol. 25, no. 4, pp. 2903-2912, Oct. 2010.
[48] R. Li, J. E. Fletcher and B. W. Williams,
“Influence of third harmonic injection on modular
multilevel converter -based high-voltage direct
current transmission systems,” IET Generation,
Transmission & Distribution, vol. 10, no. 11, pp.
2764-2770, 2016.
[49] S. Poyiadjis, “A New Cell Bypass Arrangement
and Control for Modular Multilevel Converters based
on Thyristor Forced Commutation Circuit,” 2017.

Volume XI, Issue VIII, August/2019 Page No:603