The 2014 International Power Electronics Conference

A Multi-carrier PWM for AC-DC-AC Converter

without DC Link Electrolytic Capacitor

Chung-Chuan Hou Hsin-Ping Su

Dept. of Electrical Engineering Dept. of Electrical Engineering
Chung Hua University Chung Hua University
Hsinchu, Taiwan, R.O.C. Hsinchu, Taiwan, R.O.C.

Abstract-This study proposes a multi-carrier pulse AFE VSI+PMSM

width modulation (PWM) for AC-DC-AC converter without
DC link electrolytic capacitor. The AC-DC-AC converter
consists of an AC-DC active front-end converter, a DC-AC
voltage source inverter, and a 10 uF ceramic capacitor in dc
link. The DC bus voltage controller with load compensator
is utilized to maintain the voltage of the DC link capacitor at
designed value. Furthermore, the multi-carrier PWM is
utilized to reduce the common-mode voltage (CMV) of AC­
DC active front-end converter and DC-AC inverter. The
simulation and test results are presented to validate the
performances of the proposed scheme.

Keywords-AC-DC-AC converter; active front-end

converter; inverter; multi-carrier PWM. -------�---------
I
L
I
MqVdc I
I. INTRODUCTION T I
I
I
In variable speed drives systems, diode rectifiers are
I
used as the AC-DC front-end. The advantages of the I
diode rectifiers include low cost, simplicity and high I +

reliability. However, these rectifiers draw significant

I
I
Vdc iload
L.I' :c t
harmonic current from the utility grid and lack the
I
regeneration capability. Moreover, the electrolytic I
I
capacitor is used in dc link with low cost and high density
energy storage. The disadvantages of the electrolytic
capacitor are short life time, low reliability, and slow
down system response.
This study proposes an AC-DC-AC converter system
as shown in figure I [1, 2]. The AC-DC-AC converter
AFE
(a) Equivalent circuit of the A FE in a synchronous reference frame (O)e)
consists of an AC-DC active front-end (AFE) converter, a
1- - - - - rr;;;- - - - - - - - - - - - - - - - - - - - -l
DC-AC voltage source inverter (YSI), and a 10 uF Lq
I
ceramic capacitor in dc link. The advantages of the AFE I

converter are unity power factor with low current

distortion and regeneration capability [3, 4]. The load of
the AFE converter is a YSI supplying a permanent I +

magnet synchronous motor (PMSM) running at constant + : 0),

speed O)r- Instead of the electrolytic capacitor, ceramic

Vdcl J 1
I B
C I
capacitor is utilized for DC link energy storage to - I
I
improve the reliability and system response. I
I

I
II. DYNAMIC MODEL FOR AC-DC-AC CONVERTER :Vd,�mdVd
I

A. AFE converter model �-----�-----------------------�

Figure 2 shows the equivalent circuit of the AC-DC­ VSI PMSM

(b) Equivalent circuit of the VSI and PMSM in a rotor reference frame
AC converter system where the switches are replaced by (0),)
dependent voltage and current sources representing the Fig. 2. Equivalent circuit of the AC-DC-AC converter system.

978-1-4799-2705-0/14/$31.00 ©2014 IEEE 2821

 The 2014 International Power Electronics Conference

iload =1.5(mqiqr+mdidr) __

1-----------------------
1
1
1
1
1
1
1

V*I/,

1
1

Controller II
AFE L-__________ �------------�
1 :1
VSI+PMSM PMSM Controller
L ______________I

Fig. 3. The modeling and control of the AC-DC-AC converter system in the synchronous reference frame.

switching behavior [5]. The phase voltages vsa, Vsb, and adopts the proportional control gain Ki to determine the
Vse are transformed into the synchronous reference frame modulation index Mq and Md of the pulse width
( Vqe and Vde) as shown in figure 2(a). The frequency We is modulation (PWM) operation as in (2).
synchronized to the utility by a software phase lock loop. A
*
Mq=[V -OJ L i J -K.(i -i )]IVde
The phase currents i,a, ish, and i,c are transformed into the qe e s ue I qe qe
synchronous reference frame (iqe and i de). The following (2)
A
*
assumptions are made for the AFE converter: 1) line Md=[V +OJ L i -K.(i", -i", )]IVde
de e s qe I ue ue
inductance Ls = L.m = L,h = L,c; 2) the VSI-PMSM load is
�

represented as a dependent current source hJad. Assuming the estimated value L, approximates to the
The duty cycle of the upper switches for phases a, b,
line inductance L,. Applying equation (2) to (1) and
and c is Ma, Mb, and Me, and then is transformed into the
solving the state equation, the transfer function can be
synchronous reference frame (Mq and Md). The
obtained as in (3).
equivalent DC bus capacitance is C. Therefore, the
1.5M
equivalent equations of the AFE converter in the q 1
synchronous reference frame are given in (1). v (s) . /qe (s)--i (s)
de (sC) . (1+sIOJ.) sC load
I
d . 1
- I e. = - (V -M v - OJ L i) 1.5M
dt 'I L qe q de e s de d *
s + oi (s)
(sC) 0 (1+sIOJo) de
I
d . \
- l de = - (V -M v +OJLi) 1.5M
dt L de d de e s qe v
d
(s) q (3)
s (1) G (s)=__ c =
q z* (sC)o(l+sIOJ )
d 1 3 (s) i
qe
-v = [- (M i + M i) - i ]
-

dt de C 2 q qe d de load i (s)
1 G (s)=�= ---
= [i -i ] iq / (s) l+slOJ
AFE o
Zad i
C qe

i (s)
As indicated in (\), the model of the AFE converter in G s)=
de
=
the synchronous reference frame is as shown in figure 3. ii -:;;- - 1+sIOJ
I (s) i
de
where
B. Controller desig ofAFE converter
n wi ( =K/L , ) is the pole related to the current control loop;

The error between the DC bus voltage command V*dc Giis) is the transfer function between ide and i de;
*
and the actual DC bus voltage U de is fed into a Giq(s) is the transfer function between iqe and i 'Ie;
*
proportional-integral (PI) regulator (Kvp+Kv;ls) to Gq(s) is the transfer function between U de and i*qe.
establish the close-loop control of the dc bus voltage. In
order to draw power from the ac side at unity power The transfer functions have two poles as given in (3).
factor to maintain the dc bus voltage, the output of the PI The pole on the origin is related to the capacitor value for
regulator is then multiplied by the phase voltages Vqe and the DC bus voltage control, and the pole Wi is related to
Vde in the synchronous reference frame to generate the the current regulator for the current control. The control
current commands i qe and i
* de that are exactly in-phase
* block diagram of the AFE converter system in
with the phase voltages. The load current i/oad is synchronous reference frame is as shown in figure 4. The
multiplied by K'ood and is utilized as a feed-forward term DC bus voltage is affected by the load and the current
of the current command. The close loop current control commands of q-axis and d-axis.

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I As indicated in (5), the controller of the V SI-PM SM load

I in the rotor reference frame is as shown in figure 3.
roc
I The following assumptions are made in developing
I the control block diagram for the V SI-PM SM: 1) voltage
I Vdr = 0; 2) the cross coupling terms (WrLdidr and -wrLqiqr)
I
I are perfectly decoupling by the current controller of the
I
PM SM; 3) proportional gain Kqp = Kdp = Kp and integral
VSI+iMSKC - ------- gain Kq; = Kd; = Kc;. Therefore, the control block diagram
Kfoad i<------l iload q
G
AFE+ of the V SI-PM SM is as shown in figure 4.
---I
I
III. DC Bus VOLTAGE CONTROL
Figure 4 shows the control block diagram of the AC­
DC-AC converter system. There are two major control
loops in the AFE converter system, one is the current
control loop and the other is the DC bus voltage control
loop. The PI regulator (Kvp + K,,/s) is utilized for the
Fig. 4. Control block diagram of the AC-DC-AC converter system.
compensation of the DC bus voltage. The function of the
current control loop is to maintain the line currents
C. VSI-PMSM load tracking the current commands with predicted current
The V SI-PM SM load is represented as a dependent control gain K;. As indicated in (3), the DC bus voltage is
current source hoad on the previous discussion. Figure 2(b) affected by load disturbance. Therefore, the load
shows the equivalent circuit of the V SI and PM SM in a compensation gain KZood is utilized to suppress the
rotor reference frame (wr) [6]. The quantities Vqr and Vdr disturbance of load.
represent the phase voltages in the rotor reference frame. The d-axis current command i*de is controlled to be of
The quantities iqr and idr represent the phase currents in zero value for unity power factor. The pole of current
the rotor reference frame. The resistance of the armature regulator Wi is ten times large than Kv/Kvp and
winding is rm' The quantities Lq and Ld represent the 1.5MqKv/C. Therefore, the close loop transfer function
inductance in the rotor reference frame. The cross of the DC bus voltage controller is given in (6).
coupling terms (WrLdidr and -wrLqiqr) result from the rotor KVi 1.5Mq
(Kvp + )
S2(C /�)
reference frame transformation. The induced voltage
S
Kewr is proportional to the rotor speed of thePM SM. The
K. 1.5Mq
induced torque T is proportional to the current iqr. The
1 + -' + (Kvp + _VI) . 2
OJ
equivalent equations of the V SI-PM SM load are given in S S S (C /� )
(4) (6)
K 1.5Mq
Vqr =
mqVdc =
rmiqr + Lq
d'
;;' + �,Ldidr + Ke�' (K + Vi) 2
z ____ S
�_______ S (C /OJ�I�)_
__
_ �
�
- (1 + )(1 + )(1 + OJvi)
OJ V P
- T;n1'dr + Ld didr .
Vdr mdvdc - -OJr Liqr (4)
dt S S S
-T +J dOJr where poles wvp and Wvi (near the origin) are defined as
-KII'qr
T- -- + BOJr
- L
dt 4C Kv i 1.5MK q vp
1 _ ____
.). __

As indicated in (4), the model of the V SI-PM SM load in 1.5Mq K;p 2C

the rotor reference frame is as shown in figure 3.
4C K.1' / ) 1.5MK
___ . __ q VP
.

D. Controller desin
g ofVSI-PMSM K2vp 2C
The current commands of the PM SM in rotor
reference frame are i*qr and i*dr The current errors
'
underdamped : KVi /K;p > 1.5Mq /4C
(i*qr - iqr) and U*dr - idr) are fed into the PI regulators
criticallydamped : KVi /K;p 1.5M /4C
(Kqp+Kq/s) and (Kdp+Kd/S) to establish the close loop q =

control of the PM SM current. The modulation index mq

and md are the duty cycle in the rotor reference frame as
overdamped : KVi /K;p < 1.5Mq /4C
designed with the decoupling terms (WrLdidr and -wrLqiqr) The performance of the AC-DC-AC converter system
in (5) as follow: is affected by load disturbance. Therefore, the DC bus
* voltage disturbance rejection is defined as the magnitude
mq=[(K +K Is)(i -i )+mL i l/vd•
qp ql qr qr r d dr ' (5) of hood needed to affect a unit deviation in the DC bus
* voltage. The transfer function hoais) I U de (s) is given in
md=[(K +K /s)(i -i )-mL i l/vt.
d!p dI dr dr r q qr 'c (7) according to figure 4.

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� + (K" + K,,;
1 +- )
1.5Mq
2 v�r
�T Cn

T0
Vic'
v�;*
ti
T, Cn Vic'

I
iload (S)
p S- . S (C /
_ S �)
v�r o
Vde ( S ) OJ
-1
_

sC S
1.5Mq
(I + ----'- ) + Kload . ----=-
2 -�
S (C/ � ) (7)
v"h1
I I I I I '
1- Vtri
**
Vel
v**
hI , "
I - Vtri
Sai� Sal1: lQJ :
1
OJ OJ
(1 + � )(1 + vp)(1 + v; ) Shill • 0 0
do· � 0 Sbl � 0 0 0
-1 OJ
S

1.5Mq
S S
s,;1: 1� , 11
4 Vs i V6 y� V6: Vs Y4
S,I 0 0 III 0 �0
V2: V, : Vs: iV2
- (I + ----'- ) + Kload . --
2 -"-----
v v,

sC S S (C/ OJ;)

The VSI-PMSM load is represented as iload ( 1.5mqiqr +

I.5mdidr). Then, the current loop transfer function of VSI­
PM SM is given in (8) according to figure 4.
=

'"'}
-:::::;�
(b) 81 90° =

V2(110)
�,

iqr(s) sKcp + Kc;

i;r(s) S2 Lq + s(rlll + Kcp) + Kc; V4 ....
(OU)
f'j'\
/';t\
. ____----+. VI
(WO)
Vre! Vi
(100)
s (8)
1+-
OJep
"" -----'----
s s (001) V5 V6(101) V5 (001)
(1 + -)(1 + -)
OJep OJei (c) vector (8, 0°) = (d) vector (8, 90°) =

Fig. 5. Switching vector of one bi-carrier SVPWM cycle.

The pole wcp (= KjKcp) is related to the PI regulator. The
Figure 5 shows the switching vector of one bi-carrier
pole Wei (= Ke/Lq) is related to the current control loop.
SVPWM cycle [7]. As shown in figure 5(a) (91 = 0°),
The transfer function iq/i*qr is equivalent a low pass among the modified reference voltages, the minimum
filter to keep current iqr follows the current command i*qr. magnitude one (V**al) compares with the triangle wave
The d-axis current command i*dr is controlled to be of Cn, the others (V**hl and V**cl) compare with the triangle
zero value for voltage Vdr = ° and current idr = 0, and wave Cp respectively, and then generate the active
then iload is equivalent to 1.5mqiqr. Therefore, the DC bus vectors (V1=[1,0,0], V4=[0,1,1], Vs=[O, O, I], and
voltage is affected by q-axis current command as in (9). V6=[1,0, 1D. The zero vectors (Vo=[O, O, O] and V7=[1, 1,1D
i;r(s) i;r(s) . iqr(s) i;r(s) . �. iloai s) are replaced by the opposite active vectors (V1=[1,0,0]
= =
(9) and V4=[0,1,1D. The CMV of the AFE converter is
Vdc(S) iqr(s) Vdc(S) iqr(s) 3mq Vdc(S) contained within ± u d/6. Figure 5(b) shows the switching
vector of one bi-carrier SVPWM cycle (91 = 90°). Among
the modified reference voltages, the minimum magnitude
IV. M ULTI-CARRIERPWM one (V**el) compares with the triangle wave Cn, the
In the space vector PWM ( SVPWM) scheme, the AFE others (V**al and V**hl) compare with the triangle wave
reference voltages V*ah V*bh and V*el are utilized to Cp respectively, and then generate the active vectors
calculate a zero sequence signal VOl and the VSI-PMSM (V1=[1,0,0], V2=[I, I,0], and Vs= [0,0,1]). The zero
vectors (Vo=[O, O, O] and V7=[I, I, I]) are replaced by the
reference voltages v*a2. V*b2, and V*e2 are utilized to
opposite active vectors (V2=[I, I,0] and Vs=[O, O, ID. The
calculate a zero sequence signal V(J2.
CMV of the AFE converter is contained within ± u d/6.
VOl =
�
- [max(v(: I' V: I, v:I) + min(v; I' V: I, v:I)] Figure 5(c) and 5(d) show the reference voltage vector
2 (10) composition of the bi-carrier SVPWM. This bi-carrier
1 ')] SVPWM can synthesize the desired output voltage by
V02 = -- [max(va2' Vh2' vc2) + mln(va2, Vh2' vc2
* * ' . * *

using opposite active vectors instead of using zero vectors.

2
The choice of the triangle wave to be compared with the
Adding VOl to the AFE reference voltages, the modified modified reference voltages is given in table I and table II.
AFE reference voltages V**ah V**bh and v**cJ are
TAB LE I
obtained and then utilized to generate gating pulse for
AFE MODIFIED REFERENCE VOLTAGES AND CARRIER
PWM. Adding V(J2 to the VSI-PMSM reference voltages,
91 V**al V**bl V**el
the modified reference voltages V**a2, V**h2. and V**c2
-30° 30° � Cn (VmictJ Cp (Vmi,J Cp (vmCLJ
are obtained also. The CMV of the AC-DC-AC converter
30° 90° � Cp ( vmCLJ Cp (Vmi,J Cn (VmictJ
is defmed as the neutral points of the voltage source and
90° 150° � Cp (vmCLJ Cn (VmictJ Cp (Vmi,J
PM SM to the center of the DC bus in (I I).
150° 210° � Cn (VmictJ Cp (vmaxJ Cp (Vmi,J
Vnlo =
(valo +Vblo +velo)/3
(11) 210° 270° � Cp (Vmi,J Cp (vmaxJ Cn (VmictJ
vn20 =
(va20 +Vh20 +vc2o)/3 270° 330° � Cp (Vmi,J Cn (VmictJ Cp (vmCLJ

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TABLE II
VSI -PMSM REFERENCE VOLTAGES AND CARRIER
92 v**a2 V**h2 V**c2
-30° �30° Cn (Vrni,) Cp (VrnirJ Cp (VrnaJ
30° �90° Cp (Vrnax) Cp (VrnirJ Cn (Vrni,)
90°�150° Cp (Vrnax) Cn (Vrni,) Cp (VrnirJ
1500�210° Cn (Vrni,) Cp (VrnaJ Cp (VrnirJ
210° �270° Cp (VrnilJ Cp (VrnaJ Cn (Vrni,)
270°�330° Cp (VrnilJ Cn (Vrni,) Cp (VrnaJ
Fig. 7. Phase voltage and line current of AC-DC AFE converter (v sa :
100V/div; i.m: SAidiv; time base: Sms/div).
V. SIMULATION AND TEST RESULTS
Figure 7 shows the phase voltage and line current of
The parameters of the simulation and test bench are AC-DC AFE converter with constant load. The phase
given as follows: voltage and line current are in phase.
1) Utility: three-phase 220 Vrms/60Hz; Ls = 2.0 mHo
2) AC-DC-AC converter: switching frequency isisw = 10
kHz, sampling frequency is 20 kHz. VI. CONCLU SIONS
3) DC link: U de = 370V; 10 uF ceramic capacitor. This study proposes a multi-carrier PWM for AC-DC­
4) Controller: DSP is TMS320C28335, 150 MHz AC converter without DC link electrolytic capacitor. The
operating speed; CPLD is LCMX0640C, 50 MHz. dynamic model of the AC-DC-AC converter is presented.
According to the dynamic model, the controllers of the
Figure 6 shows the AC-DC-AC converter operated AC-DC AFE converter and DC-AC VSI-PMSM are
under load changed at time 0.8 second. As shown in designed. The DC bus voltage control and load
figure 6(a), line currents are 60 Hz sinusoidal wave and disturbance rejection are analyzed to improve the
are increased under load changed at time 0.8 second. As performances of the AC-DC-AC converter. Furthermore,
shown in figure 6(b), load currents are 50 Hz sinusoidal a multi-carrier PWM is utilized to reduce the CMV of
wave. The DC bus voltage is maintained within 20V the AC-DC-AC converter. Simulation and test results are
deviation from the operated value 370V with 10 uF presented to validate the performances of the proposed
ceramic capacitor. AC-DC-AC converter.

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