528 IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO.

6, JUNE 2010

Fabrication and Characterization

of the Charge-Plasma Diode
Bijoy Rajasekharan, Student Member, IEEE, Raymond J. E. Hueting, Senior Member, IEEE,
Cora Salm, Senior Member, IEEE, Tom van Hemert, Rob A. M. Wolters, and Jurriaan Schmitz, Senior Member, IEEE

Abstract—We present a new lateral Schottky-based rectifier

called the charge-plasma diode realized on ultrathin silicon-on-
insulator. The device utilizes the workfunction difference between
two metal contacts, palladium and erbium, and the silicon body.
We demonstrate that the proposed device provides a low and
constant reverse leakage-current density of about 1 fA/µm with
7
ON / OFF current ratios of around 10 at 1-V forward bias and room
temperature. In the forward mode, a current swing of 88 mV/dec
is obtained, which is reduced to 68 mV/dec by back-gate biasing.
Index Terms—Buried oxide (BOX), charge-plasma (CP) diode,
diode, p-i-n diode, Schottky barrier, silicon-on-insulator (SOI).

I. I NTRODUCTION

S ILICON-ON-INSULATOR (SOI)-based devices with ul-

trathin body are considered for future very large scale
integrated circuit (IC) applications [1]–[3]. A silicon p-i-n diode
acting as a rectifier is one such component. It plays an important
role in diverse research domains, like power ICs and light-
emitting devices [4], [5]. Desirable diode properties are a very
low forward voltage drop and small reverse leakage current to
reduce the power dissipated by the rectifier. For conventional Fig. 1. (a) Schematic cross section of a CP diode. Pd used as an anode and
p-n junctions with nanoscale dimensions, the key issue is dop- Er used as a cathode contacted the top and sidewall of the SOI. In the region
ing control: doping fluctuation [6], [7], doping activation [8], above the Si/SiO2 stack, the metals act as a gate. (b) Top-view image of the
fabricated device. (c) TEM cross section of the device with different layer stack.
and obtaining steep doping profiles demanding a low tempera- (d) Enlarged image showing the thin Si/SiO2 layer stack.
ture budget.
Schottky-based devices with metal or metal silicided the top of the thin silicon body in order to reduce the contact
source–drain contacts are reported to circumvent these resistance. As stated earlier [10], [11], there are two essential
fabrication-related issues and produce performance specifica- features in this concept. First, the workfunctions of the cathode
tions comparable with conventional diodes [9], [10]. Fig. 1(a) and the anode metals should fulfill ϕm,C < χSi + (EG /2) and
shows a schematic cross section of our realized device called ϕm,A > χSi + (EG /2) in terms of the electron affinity of bulk
the charge-plasma (CP) diode. Here, two separate metallic silicon (χSi = 4.17 eV), and the bandgap of bulk silicon (EG ).
gates are placed on top of a thin silicon body. The gates are For optimal rectifying behavior, the difference between both
isolated from the top of the body by a dielectric layer, and each workfunctions should be at least ∼0.5 eV. Second, the thickness
forms a contact at one side of the silicon body. In the devices of the silicon body should be around or less than the Debye
presented in this letter, the metallic contacts are extended to length [12]. For this situation, the charge underneath both gates
in the silicon is primarily determined by charge carriers, and
Manuscript received February 5, 2010. Date of publication April 19, 2010; the depletion charge can be neglected irrespective of the doping
date of current version May 26, 2010. The review of this letter was arranged by concentration in the silicon layer.
Editor M. Ostling. This letter deals with the fabrication and electrical character-
B. Rajasekharan, R. J. E. Hueting, C. Salm, T. van Hemert, and J. Schmitz
are with the MESA+ Institute for Nanotechnology, University of Twente, ization of the CP diodes. We will show that the CP diodes can
7500AE Enschede, The Netherlands (e-mail: b.rajasekharan@utwente.nl; perform comparably with conventional p-n diodes or junctions
r.j.e.hueting@utwente.nl; c.salm@utwente.nl; t.vanhemert@utwente.nl; with doped regions by making a wise choice of metal combina-
j.schmitz@utwente.nl).
R. A. M. Wolters is with the MESA+ Institute for Nanotechnology, tion and device dimensions.
University of Twente, 7500AE Enschede, The Netherlands and also with
the NXP Semiconductors, 5600KA Eindhoven, The Netherlands (e-mail:
R.A.M.Wolters@utwente.nl). II. E XPERIMENTAL P ROCEDURE
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org. The devices were fabricated using 4-in SOI wafers with a
Digital Object Identifier 10.1109/LED.2010.2045731 1-μm buried oxide (BOX) and almost intrinsic (6 · 1014 cm−3 )

0741-3106/$26.00 © 2010 IEEE

RAJASEKHARAN et al.: FABRICATION AND CHARACTERIZATION OF THE CHARGE-PLASMA DIODE 529

n-Si layer of 340-nm thick on top. The top Si layer was then
thinned down to 25 nm by thermal oxidation at 950 ◦ C in a
quartz furnace under oxygen ambient. The thinned-down Si
layer is patterned in a 30% tetramethylammonium hydroxide
solution using a silicon-oxide mask. After cleaning and removal
of the oxide mask, a 10-nm-thick gate oxide was grown by
thermal oxidation at 950 ◦ C on clean silicon surface resulting
in a final Si thickness of around 20 nm. The metal contacts
are then made to form the anode and cathode. The choice of
contact metals is based on their availability in our cleanroom
facility, ease of process integration, and extracted Schottky
barrier height to lowly doped bulk Si (1015 cm−3 ). For the
devices described here, we chose palladium (Pd), a metal with
high workfunction (4.9 eV), as the anode and erbium (Er), with
low workfunction (4.4 eV), as the cathode.
Both metals were sputtered immediately after an HF dip,
to minimize residual oxide. No thermal treatment was applied
after sputtering. Care should be taken that measurements do not
exceed 400 K due to the onset of Pd silicidation at temperatures
of as low as 330 K [13]. Increasing the measurement temper-
ature or time results in Pd2 Si formation observable as a slight
increase in the reverse current due to the lower workfunction
of the Pd2 Si (4.8 eV). Er silicidation is reported to significantly
reduce the Schottky barrier height [14]. We have not observed
instabilities in the Er contacts, but material analysis could
not exclude the possibility of Er silicidation. In Fig. 1(b),
the top-view image of a device on wafer is shown as seen
through a microscope. Fig. 1(c) and (d) shows a cross section
of a fabricated device obtained using transmission electron
microscopy (TEM). Electrical characterization was carried out
on a Suss MicroTec PM300 Manual Probe Station equipped
with a Keithley 4200 semiconductor characterization system. Fig. 2. Anode current Ia as a function of the anode-to-cathode voltage Vac
for (top) symmetric Er–Er electrode and (bottom) symmetric Pd–Pd electrode
transistor at RT (300 K). The anode is kept at 0 V, the substrate is used as back
III. R ESULTS AND D ISCUSSION gate, and its voltage is varied from −30 to 0 V for Er and 0 to −30 V for the
Pd devices, as indicated.
The electrical characteristics discussed here are for an in-
trinsic silicon area of 100 × 10 μm2 and a metal spacing of
3 μm unless specified otherwise. We began by investigating
the symmetric device structures in which the same metal was
employed for the anode and the cathode (either Pd or Er).
From these structures, we investigated the MOSFET behavior
by using the substrate as back gate. The cathode was kept at 0 V,
the anode voltage Vac was swept from 0 to 1 V, and the gate
voltage Vgc was stepped from 0 to −30 V. The resulting output
characteristics are shown in Fig. 2. High gate voltages had to be
applied because of the thick (∼1 μm) BOX layer between the
substrate and the SOI layer. The Ia −Vac output characteristics
of the Er–Er devices show a linear behavior in the linear region,
indicating good ohmic contacts. On the other hand, the Pd–Pd
devices show diode behavior in the “linear” region confirming
the Schottky behavior of these contacts to lowly doped n-type
Si [15].
Next, we examine the CP diode. The cathode (Er side) and
the back gate are kept at 0 V. The anode is biased from Vac =
−1 to 1 V. Fig. 3 shows the temperature-dependent Ia −Vac
characteristics of a diode under the aforementioned biasing Fig. 3. Measured temperature dependence of the anode current Ia to anode-
to-cathode voltage Vac for the CP diode. The anode voltage was swept, while
condition. The diode shows rectification in the whole range the cathode voltage was kept at 0 V. The diode shows rectification in the whole
from 288 to 398 K. In contrast to a conventional p-n diode, range from 288 to 398 K.
530 IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 6, JUNE 2010

control issues, and it can be processed at low temperatures.

Our experimental results show that high ON – OFF current ratios,
both at RT (107 ) and at elevated temperature (105 ), combined
with very low leakage currents (1 fA/μm at RT) are possible
to achieve using this technique. It is expected that compared
with conventional diodes, the ON – OFF ratio at elevated tem-
peratures is orders of magnitude better due to the exponential
increase in the ON current. Better CSs can be achieved by
reducing interface traps between SiO2 /Si interfaces. By using
the symmetrical metal contacts and the substrate as back gate,
MOSFET-like characteristics can be obtained. Thus, a new way
of making rectifiers and MOSFETs in a CMOS-compatible
manner is introduced.

R EFERENCES
[1] G. K. Celler and S. Cristoloveanu, “Frontiers of silicon-on-insulator,”
Fig. 4. Current–voltage relation of our CP diode at RT (300 K). The anode J. Appl. Phys., vol. 93, no. 9, pp. 4955–4978, May 2003.
current Ia is measured while sweeping the anode voltage Vac from −1 to 1 V. [2] F. N. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a
The cathode and substrate are kept at 0 V. The inset shows reduction in CS by silicon chip,” Nature Photon., vol. 1, no. 1, pp. 65–71, Jan. 2007.
increasing the substrate biases from 0 to −30 V. Further increase does not show [3] J. Knoch, M. Zhang, S. Mantl, and J. Appenzeller, “On the performance
additional improvement in the CS. of single-gated ultrathin-body SOI Schottky-barrier MOSFETs,” IEEE
Trans. Electron Devices, vol. 53, no. 7, pp. 1669–1674, Jul. 2006.
the ON current increases (exponentially) with the temperature, [4] B. J. Baliga, “Analysis of a high-voltage merged p-i-n/Schottky (MPS)
resulting in an Ion /Ioff ratio of 105 at 398 K, only two orders rectifier,” IEEE Electron Device Lett., vol. EDL-8, no. 9, pp. 407–409,
Sep. 1987.
of magnitude of reduction with respect to the 107 at room [5] M. A. Green, J. H. Zhao, A. H. Wang, P. J. Reece, and M. Gal, “Efficient
temperature (RT). This increase in Ion is attributed to the ON silicon light-emitting diodes,” Nature, vol. 412, no. 6849, pp. 805–808,
current being limited by diffusion since the gates are in weak Aug. 2001.
[6] M.-H. Chiang, J.-N. Lin, K. Kim, and C.-T. Chuang, “Random dopant
inversion mode at high forward bias. At RT (Fig. 4), a small and fluctuation in limited-width FinFET technologies,” IEEE Trans. Electron
almost constant leakage current of around 1 fA/μm is obtained Devices, vol. 54, no. 8, pp. 2055–2060, Aug. 2007.
which indicates a low density of active generation centers in [7] A. Martinez, J. R. Barker, A. Svizhenko, M. P. Anantram, and A. Asenov,
“The impact of random dopant aggregation in source and drain on the
the “bulk” silicon body. This also gives a confirmation that performance of ballistic DG nano-MOSFETs: A NEGF Study,” IEEE
the region under the Pd metal gate acts as a p/p+ region and Trans. Nanotechnol., vol. 6, no. 4, pp. 438–445, Jul. 2007.
under the Er metal gate as the n/n+ region and hence, forming [8] J. C. Ho, R. Yerushalmi, Z. A. Jacobson, Z. Fan, R. L. Alley, and
A. Javey, “Controlled nanoscale doping of semiconductors via molecular
a p-i-n diode. A high ON / OFF current ratio of around 107 and monolayers,” Nature Mater., vol. 7, no. 1, pp. 62–67, 2008.
a current swing (CS) of around 88 mV/dec at zero substrate [9] J. M. Larson and J. P. Snyder, “Overview and status of metal S/D
bias is obtained. The CS depends on the quality of the Si/SiO2 Schottky-barrier MOSFET technology,” IEEE Trans. Electron Devices,
vol. 53, no. 5, pp. 1048–1058, May 2006.
interface [12]. The presence of interface traps tends to degrade [10] R. J. E. Hueting, B. Rajasekharan, C. Salm, and J. Schmitz, “The charge
the fast switching of the diode from OFF to ON state and hence, plasma P-N diode,” IEEE Electron Device Lett., vol. 29, no. 12, pp. 1367–
results in poor CS. By applying a suitable substrate bias, it is 1369, Dec. 2008.
[11] B. Rajasekharan, C. Salm, R. J. E. Hueting, T. Hoang, and J. Schmitz,
possible to determine whether the interface traps at the BOX/Si “Dimensional scaling effects on transport properties of ultrathin p-i-n
interface play a role in weakening the CS from the ideal value diodes,” in Proc. ULIS, 2008, pp. 195–198.
of 60 mV/dec. On varying the substrate bias from 0 to −30 V, it [12] S. Sze, Physics of Semiconductor Devices, 2nd ed. Hoboken, NJ: Wiley,
1981.
can be seen that the CS changes from 88 to 68 mV/dec (Fig. 4 [13] E. J. Faber, R. A. M. Wolters, B. Rajasekharan, C. Salm, and J. Schmitz,
inset). No hysteresis was observed in the device characteristics. “Low temperature silicidation of Pd layers on crystalline silicon moni-
Interchanging the anode and cathode was reported to give a shift tored via in situ resistance measurements,” in Proc. Adv. Metallization
Conf., 2009, MRS Conference Proceedings Series, to be published.
in the characteristics for CNTs [16]. We do not see this in our [14] N. Reckinger, X. Tang, V. Bayot, D. A. Yarekha, E. Dubois, S. Godey,
devices. X. Wallart, G. Larrieu, A. Laszcz, J. Ratajczak, P. J. Jacques, and
J.-P. Raskin, “Schottky barrier lowering with the formation of crystalline
Er silicide on n-Si upon thermal annealing,” Appl. Phys. Lett., vol. 94,
IV. C ONCLUSION no. 19, pp. 191 913-1–191 913-3, May 2009.
[15] J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu,
We have fabricated a new rectifier called the CP diode that “Complementary silicide source/drain thin-body MOSFETs for the 20-nm
makes use of the workfunction difference between the metal gate length regime,” in IEDM Tech. Dig., 2000, pp. 57–60.
[16] J. Li, Z.-B. Zhang, Z. Qiu, and S.-L. Zhang, “Contact-electrode insensitive
contact and the intrinsic silicon body. This novel device requires rectifiers based on carbon nanotube network transistors,” IEEE Electron
no doping, avoiding statistical doping fluctuations and doping- Device Lett., vol. 29, no. 5, pp. 500–502, May 2008.