International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 9 - 371 -

FPGA based implementation of Baseline JPEG decoder

Jahanzeb Ahmad, Mansoor Ebrahim

Faculty of Engineering, Sciences and Technology, IQRA University, Karachi Pakistan.
jahanzeb.ahmad@iqra.edu.pk, mansoorebrahim99@hotmail.com

Abstract (TIFF) [11]. JPEG is a very well know image

compression standard. It is widely adopted as
The JPEG standard (ISO/ IEC 10918-1 ITU-T compression standard for still images. Joint
Recommendation T.81) defines compression Photographic Expert Group (JPEG) is a joint
techniques for image data. As a consequence, it allows workgroup of three international standard
to store and transfer image data with considerably organizations, International Organization for
reduced demand for storage space and bandwidth. Standardization (ISO), International Telegraph and
From the four processes provided in the JPEG telephone consultative committee (CCITT) and
standard, only one, the baseline process is widely International Electrotechnical commission (IEC).
used. In this paper FPGA based High speed, low Enormous amount of data storage is required for
complexity and low memory implementation of JPEG digital images/video. An uncompressed color image
decoder is presented. The pipeline implementation of requires 24 bits for each picture element (pixel). A 6
the system, allow decompressing multiple image blocks Mega pixel (3038 X 2012) camera requires 17.5 Mega
simultaneously. The hardware decoder is designed to Bytes, when stored uncompressed, same image when
operate at 100MHz on Altera Cyclon II or Xilinx compressed with JPEG take almost 1.7 Mega bytes
Spartan 3E FPGA or equivalent. The decoder is depending on the compression ratio. En-hui Yang,
capable of decoding Baseline JPEG color and gray Longji Wang [18] proposed an algorithm which can
images. Decoder is also capable of downscaling the further improve this ratio, the algorithm is iterative,
image by 8. The decoder is designed to meet industrial which is more complex to implement in Hardware.
needs. JFIF, DCF and EXIF standers are implemented Digital devices are now more popular then analog
in the design. devices especially in the field of multimedia (Audio,
Video and Image) because of amazing improvement in
1. Introduction digital signal processing algorithms and fast hardware.
Digital storage media is more reliable and less effected
Communication and storage cost are reduced by by noise and distortion.
doing data compression. Data compression techniques Real-time implementation of JPEG encoder or
can be divided into two categories “losy” and decoder requires efficient and fast hardware
“lossless”. Lossless compression model are based on architecture. So architecture specific implementation is
entropy coding schemes. This model is widely used for required to achieve real-time results. Variety of
text and data compression. In lossless compression architecture designs capable of supporting real time
model exact data is obtained at the receiver. Lossy image/video processing already exists such as ASIC,
compression model produces close approximation of FPGA, Microprocessor and Digital signal processor
the original data at the receiver. Video, Image and based design, which implements different algorithms
audio compression commonly use lossy compression. for image and video processing. But only a few
Compression ratio up to 100:1 can be achieved efficient architectures are implemented for Image and
depending on the fidelity of the data. video compression, decompression, processing [12, 13,
There are several standards/formats for image 14, 15, 16, 19, 20, 21, 22, 23, 32]. Shizhen Huang and
compression/ decompression. Joint Photographic Tianyi Zheng [12] proposed an architecture for PNG
Experts Group (JPEG) [1, 17], Graphics Interchange image decoding, they used combination hardware and
Format (GIF) [7 8], Portable Network Graphics (PNG) software approach which reduce the throughput of the
[9], JPEG 2000 [10], Tagged Image File Format system. Zulkalnain MohdYousof, et al. [13] proposed
a Digital Signal processor based JPEG Decoder but it

1916091 IJECS-IJENS @ International Journals of Engineering and Sciences IJENS

International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 9 - 372 -

can only support small resolution images. R. P. Jacobi completeness the “4:4:4” method should be mentioned
et al. [14] proposed an FPGA based JPEG decoder it does not reduce any component‘s resolution. For
design but its maximum operating frequency is 38.7 grayscale (“4:0:0”) images only the Y component is
MHz on Vertex 6 which is very slow for commercial processed. Figure. 3 illustrate the described sampling
design. Mario kovac and N. Ranganathan [15] methods. If the “4:2:0” or “4:2:2” sampling method is
presented encoder architecture which is capable of used this is one of two steps in the compression
operating at 100 MHz and can support 1024x1024 process where information is lost.
spatial color image resolution. Mohammed Elbadri et
al [16] also proposed a FPGA based design for JPEG
decoder this design also has low operating frequency,
67 MHz. Kyeong-Yuk Min and Jong-Wha Chong [19]
proposed an architecture for JPEG Encoder.
Zulkalnain MohdYusof et al [20], proposed a Digital
Signal Processor (DSP) based architecture, DSP based Figure 1. JPEG Encoder
systems have low development time and cost but low
throughput as compare to FPGA.
FPGA is relatively young technology. FPGA can
provide speed, performance and flexibility because
parallel and pipelined implementation of Algorithm is
possible. FPGA provide a better solution because
hardware is designed for specific algorithm. Figure 2. JPEG Decoder
In this paper we proposed a FPGA based JPEG
decoder architecture, which gives fast and efficient
results. The paper is organized as follow: In section 2
we discuss JPEG in general. In section 3 JPEG stream
is discussed. Hardware implementation is discussed in
section 4. Synthesis reports are discussed in
subsequent section. Finally, results and conclusions are
discussed.
Figure 3. Sampling
2. JPEG compression overview JPEG image is composed of smaller units. An
image is composed of Minimum coded Units (MCUs)
Principles of JPEG can be explained better to take a which consist of square blocks of 8x8 pixels. It
look at the steps of encoding rather than decoding. depends on the chosen sampling method how many
Therefore, despite the fact that a decoder has been 8x8 blocks form an MCU, in Figure 4 the 4:2:0
developed, due to better understanding the steps of sampling is shown. The order in which the units will
encoding. The steps of decoding will be the inverse of be processed is always from left to right and from top
the encoding steps but in reverse order (see Figure 1 to bottom as shown in figure 4. For the MCUs it is also
and Figure 2). important to keep the color-decomposition in mind.
The human eye is more sensitive to brightens then Picture when displayed on screen or printed on
colors [33]. Almost no loss in visual perception quality paper is in spatial domain. DCT transforms a picture
can be achieved if chrominance component is stored in into frequency domain [34]. Human vision system is
half resolution then luminance component [33]. JPEG more sensitive to low frequency then higher frequency
images are stored in YCbCr color space rather then [33]. Since neighbor pixels are highly correlated and
RGB. CCIR Rec 601 [6] defines the method of are in low frequency, the output of DCT result in most
conversion between RGB and YCbCr. of the block energy being stored in the lower spatial
Most JPEG encoders reduce the chrominance frequencies. Higher frequencies will have values equal
components to half of the resolution in both to or close to zero so they can be ignored without have
dimensions by taking the mean value of each 2x2 significant loss in image quality.
block. This sampling method is called “4:2:0”. Another The input data to be processed is a two-dimensional
sampling method evolved from analog television 8x8 block, therefore we need a two-dimensional
signals [33] is “4:2:2” where chrominance components version of the discrete cosine transformation. Since
are reduced only in the horizontal dimension. For each dimension can be handled separately, the two-

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International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 9 - 373 -

dimensional DCT follows straightforward form the one rearranges the coefficients in a one dimensional order,
dimensional DCT. A one-dimensional DCT is so that most of the zeroes will be placed at the end.
performed along the rows and then along the columns, This array with many consecutive zeroes at the end is
or vice versa. now optimized to achieve high compression in entropy
encoding.

Figure 4. 4:2:0 MCU

JPEG uses a zero-shift in the input samples to

convert 8-bit image data from the range 0 to 255 to the
range of -128 to +127. This is done by subtracting 128
before DCT is calculated. DCT is defined in equation
(1) and IDCT is defined in equation (2)
FDCT: 1 7 7
(2 x + 1)uπ (2 y + 1)vπ (1)
Svu = Cu Cv ∑ ∑ s yx cos cos
4 x=0 y =0 16 16
Figure 5
IDCT: 1 7 7
( 2 x + 1)uπ ( 2 y + 1)vπ (2)
s yx = ∑ ∑ Cu Cv S vu cos cos
4 u =0 v=0 16 16 The final step is a combination of three techniques:
Cu , Cv = 1 for u,v = 0 Cu , Cv = 1 otherwise run length encoding, variable length encoding, and
2
Huffman encoding.
The “Quantization” is a key step in the compression The first coefficient is called “DC”(#0) all other
process since less important information is discarded. coefficients are called “AC” (#1 till #63).
The advantage of the representation in the The first coefficient (DC) is the mean value of the
frequency domain is that, unlike in spatial domain original 8x8 block. There is a correlation between the
before the DCT, not every dimension has the same DC coefficients of neighboring blocks.
importance for the visual quality of the image. It is very likely that the first coefficient has the
Removing the higher frequencies components will largest value. This is the most significant coefficient
reduce the level of detail but the overall structure and therefore usually the least reduced one in the
remains, since it is dominated by the lower frequency quantization step.
components. Most zero coefficients appear at the end. The
The 64 values of a 8x8 block will be divided chance to find some consecutive zeroes followed by a
according to the 64 values of an 8x8 matrix called the non-zero component is good as well. Most non-zero
quantization table. There is no information lost in the coefficients have very small values.
division of the coefficients itself, but the result is then The DC coefficient will be decoded slightly
rounded to the next integer afterwards. The higher the different than the AC coefficients. Respecting the
divisor, the more information about the coefficient will correlation to the neighboring blocks, just for the first
be positioned after the decimal point hence lost in the block the whole DC coefficient is processed. Later
rounding operation. blocks will only encode the difference to the preceding
The two dimensional order of the DCT coefficients block’s DC component; this applies for each
refers to the two dimensions that the 8x8 block has in component separately. AC and DC coefficients have
spatial domain. After the quantization step most of the different Huffman tables.
coefficients towards the lower right corner are zero. Let’s look at an example block of coefficients (the
The Zigzag-Mapping - as shown in Figure 5(d) - one from Figure 5(e)):

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International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 9 - 374 -

29,-2, 3, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, . . . The final bit stream:

Let’s assume that the previously decoded block of 11011110 00110011 01101101 11111110 100
the same component had the DC coefficient 22, So we compressed the 64 bytes of input data down
therefore we decode the difference 29 - 22 = 7. to less than five bytes.
7,-2, 3, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, . . .
So now we take care of the zeroes using run length 3. JPEG stream
encoding. The tailing zeroes will be combined in one
code, called “EOB”. To each non-zero code we will JPEG standard has many parts, only parts which are
stick the information about preceding zeroes, so we compliance with applicable parts of DCF [2], Exif [4]
can remove the rest of the zeroes. For the DC and JFIF [3] are implemented. The resulting stream is
coefficient there will be no preceding zeroes, however, shown in Figure 6. The variables and parameters are
unlike for the AC coefficients, “zero” is still a valid defined in JPEG [1].
value that has to be concerned.
4. Hardware implementation
The system is consists of different blocks as shown
The remaining coefficients will probably be very in the block diagram in Figure 8. The interface of the
small so that variable lengths approach seams feasible. JPEG decoder is shown in Figure 7. The design
Therefore we switch to binary representation and add features are
the minimum number of bits needed to represent the
coefficients value to the information part. Negative • Efficient Design.
values will be represented by negating every bit (one’s • Minimum clock speed of 100 Mhz.
complement). This can be done because we have the • Target Independent design.
information about the length, so that every positive • Synchronous design
value starts with a 1.

[EOB] is coded as [0 0], [ZRL] as [15 0]; there is

no other code with the structure [X 0].
Since the coefficients are usually very small there is
not much gain in compressing them further. However
we have not thought about the information we attached
to the coefficients yet. We use 4 bits for the preceding
zeroes and 4 bits for the number of bits used to store
the value. These 8 bits are compressed using a
Huffman table which maps the frequently occurring
values to shorter bit strings and the rarely occurring
values to longer bit strings. How to choose the table is Figure 6. JPEG Stream
left to the encoder.
Let’s assume we have built the Huffman table and The system works on 8-bit data input. When the
find the following tables: start signal is asserted parser start to read data. If first
two bytes are not Start of Image Marker parser
generates the error. Otherwise it starts searching for
the next marker.
JPEG stream parser, parse the input stream.
Huffman tables, quantization tables and other
information of the image is extracted and stored in the
memory by this module. At the start of the entropy
Now we can construct the final bit stream: coded segment the control of the JPEG decoder is
transferred from parser to Huffman decoder controller.

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International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 9 - 375 -

own architecture. Our Huffman decoder decodes the

JPEG stream and generates the value in 11-bit. The
input of the Huffman decoder is a 8-bit data, Huffman
codes from Huffman memories block and image
parameters from parser. The controller is inside the
Huffman decoder top. Therefore, no extra controller is
needed. Inside Huffman decoder top there are 4 sub
blocks Huffman_decoder_controller , ecs_filter ,
value_wrapper and huffmandecoder. Huffmandecoder
has more blocks including huffmanstreamer,
decisionmaker and compareblock as shown in Figure
9.
FIFO stores the decoded codes from the Huffman
Figure 6. JPEG decoder top VHDL Interface decoder before it is dequantized and inverse zigzagged.
JPEG decoder can also downscale image in size by the
factor of 8 in both vertical and horizontal direction.
Therefore in downscale by 8 mode the IDCT is
bypassed. Bypassing IDCT increases the throughput of
the decoder.
The 2D DCT/IDCT is based on the 1D fast DCT
algorithm first described by Vetterli and Ligtenberg
[5]. The input is 8x8 blocks of data in frequency
domain and output is 8x8 block of data in time
domain.

5. RESULTS/SYNTHESIS REPORT
Synthesis report of JPEG decoder is shown in Table
4 and 5.
Figure 7. Block Diagram of the VHDL blocks
Table 1 Synthesis report (Altera)
Parameter Value
Device Altera cyclone II EP2C8T144C6
Synth/P&R Tool Altera Quartus II v8.1
Synth/P&R settings Timing constraint 100 MHz
Fmax 102.45
LEs 3996
Memory 15
Hard Multipliers 3
Clocks 1

Table 2 Synthesis report (Xilinx)

Figure 8. Huffman decoder Parameter Value
Device Xilinx Spartan-3E xc3s500e-5-
Dequantization is one process where we lose vq100
information, this loss can be reduced by using other Synth/P&R Tool Xilinx ISE v10.1
techniques [26, 27, 28, 29, 31], but these
Synth/P&R settings Time performance with physical
implementations are not the part of this project.
synthesis
Dequantization and inverse-zigzag is done by one
Fmax 101.8 MHz
block. Inverse-zigzag was implemented by using
Slices 3187
simple lookup table. Dequantization was done by
Memory 7 Block RAMs
multiplying the value with the quantization table.
There are few efficient Huffman decoder Hard Multipliers 2
architectures [24, 25, 30]. We have implemented our Clocks 1

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International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 9 - 376 -

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