Rathi classes Analog Electronics

a) diode that are to be used in a full wave

Chapter – 1 rectifier should be rated 2Vm and in bridge
rectifier equal to Vm
Diode Circuits b) The diodes that are to be used in a full wave
Rectifiers, filters, clippers & Clampers, rectifier should be rated Vm and in bridge
Precision Rectifiers voltage regulators. rectifier equal to 2Vm
c) All diodes should be rated for Vm only
Q.1) In a full-wave rectifier using two ideal d) All diodes should be rated for Vm
diodes, Vdc and Vm are the dc and peak values [IES – 2002 EC]
of the voltage respectively across a resistive
load. If PIV is the peak inverse voltage of the Q.4) In a half-wave rectifier, if an a.c. supply is
diode, then the appropriate relationships for this 60 Hz, then what is the a.c. ripple at output?
rectifier are a) 30 Hz b) 60 Hz
Vm
a) Vdc = π
, PIV = 2Vm c) 120 Hz d) 15 Hz
b)
2V
Vdc = πm , PIV = 2Vm [IES – 2005 EC]
2V
c) Vdc = m , PIV = Vm Q.5) A half-wave rectifier having an a.c. voltage
π
Vm
d) Vdc = π , PIV = Vm of 325 V peak value and the diode has a
forward resistance of 100 Ω. What is the RMS
[GATE – 2004 EC] value of the current?
a) 295.4 mA b) 94.0 mA
Q.2) The correct full wave rectifier circuit is c) 147.7 mA d) 208.0 mA
[IES – 2005 EC]
a) b)
Q.6) Silicon diodes are less suited for low
voltage rectifier operation because
a) It cannot withstand withstand high
Input
Input temperatures
Output Output
b) Its reverse saturation current is low
c) Its cut – in voltage is high
d) Its breakdown voltage is high
[IES – 2008 EC]
c) d)
Q.7) Consider the following statements:
When compared with a bridge rectifier, a centre
– tapped full wave rectifier:
Input
Input 1. Has larger transformer utilization factor.
Output Output 2. Can be used for floating output terminals i.e.
no input terminal is grounded.
3. Needs two diodes instead of four.
[GATE – 2007 EC] 4. Needs diodes of a lower PIV rating.

Q.3) The PIV rating of the diodes used in power Which of these statements is/are correct?
supply circuits are chosen by which one of the a) 1 and 2 Only b) 1, 2, 3
following criteria? (Vm is the peak input supply c) 3 Only d) 3 and 4 Only
voltage to the rectifier circuit used in the power [IES – 2010 EC]
supply)

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 Rathi classes Analog Electronics
Q.8) A rectifier (without filter) with fundamental D
ripple frequency equal to twice the mains
frequency, has ripple factor of 0.482 and power
conversion efficiency equal to 81.2%. The 10 sin ωt R C
rectifier is 100 Ω 4 mF
f = 50 Hz
1. Bridge rectifier
2. Full – wave (non bridge) rectifier
3. Half – wave rectifier
[GATE-2014, EC-03]
Which of these are correct?
a) 2 and 3 only b) 2 only Q.6) For the circuit with ideal diodes shown in
c) 1 and 2 only d) 1, 2 and 3 the figure, the shape of the output (vout) for the
[IES – 2010 EC] given sine wave input (vm) will be

Q.9) The correct waveform for output (V0) for

below network is

Vi
10V
t

-10V

a) b)
v0
v0
4.3 V
a) b)
t
t
- 4.3 V

c) d)
5V
+5 V
t
c) d)
t

-5V -5V

[IES – 2010 EC]

[GATE-2015, EC-01, 1 MARK]
Q.10) A half-wave rectifier has an input voltage
of 240 V rms. If the step-down transformer has
Q.13) The figure shows a half-wave rectifier
turns ratio of 8 : 1, what is the peak load
voltage? Ignore diode drop. circuit with input voltage V(t) = 10 sin (100 t )
a) 27.5 V b) 86.5 V volts. Assuming ideal diode characteristics with
c) 30.0 V d) 42.5 V zero forward voltage drop and zero reverse
[IES – 2011 EC] current, the average power consumed in watts
by the load resisrtance RL is ________ W.
Q.11) The figure shows a half-wave rectifier.
The diode D is ideal. The average steady-state
current(in Amperes) through the diode is
approximately ______________.

[GATE-2015, IN, 1 MARKS]

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4
 Rathi classes Analog Electronics
Q.14) The peak value of the output voltage Vo Q.18) The use of a rectifier filter in a capacitor
across the capacitor shown in the figure for a circuit given satisfactory performance only when
230 : 9 transformer and a 230 V, 50 Hz., input, the load
assuming 0.7 V diode drop and an ideal a) Current is high b) Current is low
transformer, is c) Voltage is high d) Voltage is low
230 V [IES – 2001 EC]
1000 mF
Vo Q.19) For a full-wave rectifier with shunt
~ capacitor filter, the peak-to-peak ripple voltage
is
230 : 9
a) 2IDC fc b) IDC fc
a) 12.73 b) 11.33 c) 7.6 d) 9.0 c) IDC 2fc d) IDC 4fc
[GATE – 2005 IE] (Where = fundamental power line frequency,
IDC = DC current)
Q.15) Consider the following statements in [IES – 2003 EC]
relation to a large value of capacitor filter used Q.20) The output Vdc from the below circuit is
in a full-wave rectifier: It gives the D(ideal)
1. low conduction period for the diode rectifier. +
2. increased peak current rating of the diode.
3. large peak inverse voltage rating of the
diode. 100µF
Which of these statements are correct? 230 V 12 V C Vdc
a) 1, 2 and 3 b) 2 and 3 50 Hz
c) 1 and 2 d) 1 and 3
[IES – 2000 EC]
-
Q.16) Consider the following statements: 12
a) 12√2 b) 𝜋
24 12
The function of bleeder resistance in filter circuit c) d)
𝜋 √2
is to
[IES – 2010 EC]
1. Maintain minimum current necessary for
optimum inductor filter operation
Q.21) The transfer characteristic for the
2. Work as voltage divider in order to provide
precision rectifier circuit shown below is
variable output from the supply.
(assume ideal OP – AMP and practical diodes)
3. Provide discharge path to capacitors so that
+20 V
output becomes zero when the circuit has
been de-energised. R
Which of these statements are correct?
4R
a) 1 and 2 b) 2 and 3
c) 1 and 3 d) 1, 2 and 3 D2
[IES – 2001 EC] Vi -
R V0
+ D1
Q.17) Consider the following rectifier circuits for
low load:
1. Half-wave rectifier without filter.
2. Full-wave rectifier without filter. a) b)
V0
3. Full-wave rectifier with series inductance
V0
filter.
10
4. Full-wave rectifier with capacitance filter.
The sequence of these rectifier circuits in 5
decreasing order of their ripple factor is
VI VI
a) 1, 2, 3, 4 b) 3, 4, 1, 2 -10 -5 0 -10 -5 0
c) 1, 4, 3, 2 d) 3, 2, 1, 4
[IES – 2001 EC]
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5
 Rathi classes Analog Electronics
R
c) d)
V0 V0 R
R +Vsat
10 vi R +Vsat
-
5 -
+
+ vo
-Vsat
VI VI R
0 +5 0 +5 -Vsat
R
[GATE – 2010 EC]

Q.22) Consider the following circuit:

a) b)
V0
1
-1 V0

Vi Vi

c) d)
What is the function of diode D2 in the above V0
V0
circuit?
a) To avoid saturation of the Op-Amp
1 Vi Vi -1
b) To provide negative feedback when the input
is negative
c) To reduced reverse breakdown voltage of D1
[GATE-2014, EE-03]
d) As a buffer
[IES – 2004 EC]
Q.25) Assuming the diodes D1 and D2 of the
Q.23) In the circuit shown below the switch (S)
circuit shown in figure to be ideal ones, the
is closed whenever the input voltage (Vin) is
transfer characteristics of the circuit will be
positive and open otherwise.
R R D1 V0
D2
2O
R Vi RL =
- 0.5 R
R -
10 V 5V
+ S Vout
+
a) b)
Vin
Vo Vo
The circuit is a
a) Low – pass filter b) Level shifter 10 5
c) Modulator d) Precision rectifier
[GATE – 2007 IE] 10 Vi 5 Vi

Q.24) The transfer characteristic of the Op-amp

circuit shown in figure is
c) d)
Vo

10

10 Vi

[GATE – 2006 EE]

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6
 Rathi classes Analog Electronics
Q.5) The equivalent circuits of a diode, during
forward biased and reverse biased conditions, c) d)
are shown in the figure 10 10
+ - + - Vo
Vo
- + 4.3 - 5.7
4.3 10 10
(a) Vi -5.7 Vi

Q.3) Consider the following circuit:

If such a diode is used in clipper circuit of figure For the circuit shown above, which one of the
given above, the output voltage (V0) of the following is a correct statement?
circuit will be a) D2 does not conduct for any value of Vi
a) b) b) v0 = 10 V for all values of vi > 10 V
+5V
10V c) v0 = 0 V for all values of vi < 0 V
0 00 2 d) v0 = 10 V for all values of vi > 0 V
0 2
-5V
- 5.7V
Q.29) The figure given below shows the transfer
characteristics of which one of the following:
c) d) Vout
+5.7V +5.7V Vf
0 2 0 2
-10V -5V Vin

Slope ‘s’
Q.27) A clipper circuit is shown below
a) Peak clipper b) Bottom clipper
c) Clamper d) Two level clipper
[IES – 2008 EC]

Q.4) Two silicon diodes, with a forward voltage

drop of 0.7 V, are used in the circuit shown in
the figure. The range of input voltage Vi for
which the output voltage Vo = Vi, is

Assuming forward voltage drops of the diodes + +

R
to be 0.7 V, the input-output transfer
D1 D2
characteristics of the circuit is Vi Vo
a) b) 2V
-1 V
- -
Vo
Vo a) -0.3 V < Vi < 1.3 V b) -0.3 V < Vi < 2 V
4.3 5.7
c) -1.0 V < Vi < 2.0 V d) -1.7 V < Vi < 2.7 V
- 0.7 [GATE-2014, EC-04]
Vi - 0.7 5.7
4.3 Vi

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 Rathi classes Analog Electronics
Q.5) Assuming the diodes to be ideal in the Which of the statements given above are
figure, for the output to be clipped, the input correct?
voltage vi must be outside the range a) 1 and 2 b) 2 and 3
c) 1 and 3 d) 1, 2 and 3
[IES – 2005 EC]
10k
Q.34) Select the correct output (v0) wave-shape
vi 10k vo for a given input (vi) in the clamping network
1V 2V given below:

a) -1 V to -2 V b) -2 V to -4 V t
c) +1 V to -2 V d) +2 V to -4 V
[GATE-2014, EE-02]
a) b)
Q.32) For a given sinusoidal input voltage, the
voltage waveform at point P of the clamper
circuit shown in figure will be

Vm +12V
- + c) d)
-
C RL
+ P
-
~ Vin - 12 V
+

Vin [IES – 2005 EC]

Q.35) If the circuit shown has to function as a

clamping circuit, then which one of the following
conditions should be satisfied for the sinusoidal
a) b) signal of period T?

c) d)

12 V

-0.7

[GATE – 2006 EE] a) RC << T b) RC = 0.35 T

c) RC  T d) RC >> T
Q.33) Consider the following statements: [GATE-2015, EC-02, 1 MARK]
A clamper circuit
1. Adds or subtracts a dc voltage to or from a
waveform.
2. Does not change the shape of the waveform.
3. Amplifier the waveform

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 Rathi classes Analog Electronics
Q.36) The circuit shown in the figure is best c) 2Vm d)-Vm
described as a [IES – 2010 EC]

Q.40) In the circuit shown, assume that diodes

D1 and D2 are ideal. In the steady state
Output condition, the average voltage Vab (in Volts)
across the 0.5 F capacitor is __________.

a) bridge rectifier b) ring modulator

c) frequency discriminatory d) voltage doubler
[GATE – 2003 EC]

Q.37) The diodes and capacitors in the circuit

shown are ideal. The voltage v(t) across the
diode D1 is
[GATE-2015, EC-03, 1 MARK]
C1 v(t) D2

+ Q.41) In the following circuit, the input voltage

Cos(ωt) C2 Vin is 100sin (100 t ) . For 100 RC = 50, the
-~
average voltage across R (in Volts) under
steady-state in nearest to
a) Cos(ωt) – 1 b) Sin(ωt)
c) 1 – cos(ωt) d) 1-sin(ωt)
[GATE – 2012 EC]

Q.38) The figure shown is a circuit of which one

of the following?
+ a) 100 b) 31.8
C c) 200 d) 63.6
-
RL V0 [GATE-2015, EE-02, 1 MARK]

Vin C Q.42) The transistor shunt regulator shown in

the figure has a regulated output voltage of
10V, when the input varies from 20V to 30V.
The relevant parameters for the zener diode
a) Bridge rectifier b) Voltage doubler and the transistor are: Vz = 9.5, VBE = 0.5V, β =
c) Rectifier with filter d) Comparator 99. Neglect the current through RB. Then the
[IES – 2008 EC] maximum power dissipated in the zener diode
(Pz) and the transistor (PT) are
Q.39) Consider the below circuit, for Vi = Vm sin 20Ω
ωt, the output voltage V0 for RL → ∞ will be
C D Iz Ic
Vz
Vin
RL Vo = 10V
20-30V +
+ D
RB VBE
Vi -
V0
- C
a) Pz = 75mW, PT = 7.9W
b) Pz = 85mW, PT = 8.9W
c) Pz = 95mW, PT = 9.9W
a) Zero b) Vm d) Pz=115mW, PT = 11.9W
[GATE – 2001 EC]
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9
 Rathi classes Analog Electronics
Q.43) A zener diode regulator in the figure is to Q.46) For the circuit shown below, assume that
be designed to meet the specifications: the zener diode is ideal with a breakdown
IL = 10mA, Vo=10V and Vin varies from 30V to voltage of 6 volts. The waveform observed
50V. The zener diode has Vz = 10V and Izk across R is
(knee current) = 1mA. For satisfactory operation 6V
R
+
IL = 10mA +
RL

Vin Vo RL 12sin t R VR
Dz

- -

a)
a) R ≤1800Ω 6V
b) 2000Ω ≤ R ≤ 2200Ω
c) 3700Ω ≤ R ≤ 4000Ω
d) R > 4000Ω
[GATE – 2002 EC] b)
6V

Q.44) In the voltage regulator shown in the

figure, the load current can vary from 100 mA to
-12V
500 mA. Assuming that the zener diode is ideal c)
(i.e., the Zener knee current is negligibly small 12V
and zener resistance is zero in the breakdown
region), the value of R is
-6V
d)

-6V

[GATE – 2006 EC]

70 Common Data for Questions 47 & 48.

a) 7Ω b) 70Ω c) 3
Ω d) 14Ω A regulated power supply, shown in figure
[GATE – 2004 EC] below, has an unregulated input (UR) of 15
Volts and generates a regulated output Vout.
Q.45) The zener diode in the regulator circuit Use the component values shown in the figure
shown in the figure has a Zener voltage of 5.8
volts and a Zener knee current of 0.5 mA. The
maximum load current drawn from its circuit
ensuring proper functioning over the input
voltage range between and 20 and 30 volts, is
1kΩ

Vi

20-30 V1=5.8V Load

a) 23.7 mA b) 14.2 mA
c) 13.7 mA d) 24.2 mA
[GATE – 2005 EC]
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 Rathi classes Analog Electronics
Q.47) The power dissipation across the
transistor Q1shown in the figure is
a) 4.8 Watts b) 5.0 Watts
c) 5.4 Watts d) 6.0 Watts
[GATE – 2006 EC]

Q.48) If the unregulated voltage increases by

20%, the power dissipation across the transistor
Q1
a) Increases by 20%
b) increases by 50% [GATE – 2014, IN]
c) remains unchanged
d) decreases by 20% Q.53) In the voltage regulator circuit shown in
[GATE – 2006 EC] the figure, the op-amp is ideal. The BJT has
VBE = 0.7 V and β = 100, and the zener voltage
Q.49) The Zener diode shown in the figure, the is 4.7 V. For a regulated output of 9 V, the value
Zener voltage at knee is 7 V, the knee current is of R (in Ω) is ____________.
negligible and the Zener dynamic resistance is VI = 12 V V o= 9 V
10Ω. If the input voltage (Vi) range is from 10 to
16 V, the output voltage (V0) ranges from
200 Ω +
1 kΩ 1 kΩ
+ -

Vi
Vo
R
Vz = 4.7 V
-

a) 7.00 to 7.29 V b) 7.14 to 7.29 V

c) 7.14 to 7.43 V d) 7.29 to 7.43 V
[GATE – 2007 EC] [GATE – 2014, EC]

Q.50) The input voltage of Zener regulator Q.54) In the circuit shown below, the Zener
varies from 20 V to 30 V. the load current varies diode is ideal and the Zener voltage is 6 V. The
from 10mA to 15 mA. If the Zener voltage is 5 output voltage V0 (in volts) is _________.
V, the value of series resistor will be
a) 1 kΩ b) 1.5 kΩ
c) 1.66 kΩ d) 2.5 kΩ
[IES – 2000 EC]

Q.51) A power supply has a full – load voltage

of 24 V. What is its no – load voltage for 5% [GATE-2015, EC-01, 1 MARK]
regulation (rounded to the nearest integer)?
a) 12 V b) 23 V c) 25 V d) 6 V
[IES – 2007 EC]

Q.52) For the circuit shown in the figure, the

transistor has β = 40, VBE = 0.7 V, and the
voltage across the Zener diode is 15 V.The
current (in mA) through the Zener diode is
___________.
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 Rathi classes Analog Electronics
Q.55) In the following limiter circuit, an input 10 kΩ
voltage Vi = 10sin 100πt is applied. Assume
that the diode drop is 0.7 V when it is forward
biased. The Zener breakdown voltage is 6.8 V. 10kΩ
10 V V0 15 V

10kΩ

a) 4V b) 5V c) 7.5V d) 12.12V
[GATE – 2010 EE]

The maximum and minimum values of the Q.6) A 40 V dc supply is connected across the
output voltage respectively are network comprising of Zener and silicon diodes
a) 6.1 V, -0.7 V b) 0.7 V, -7.5 V as shown. The regulated voltages V01, V02 and
c) 7.5 V, -0.7 V d) 7.5 V. - -7.5 V source current Is are
[GATE – 2008 EC] 1.5 K

Q.4 Assuming that the diodes are ideal in Is Ze 6V

figure, the current in diode D1 is
1kΩ 1kΩ V02
40V Si
D2
V01
D1 3.3 V Ze
5V
a) 2.4 V, 5.1 V and 21.7 mA
8V b) 3 V, 6 V and 22.7 mA
c) 3.3 V, 9.3 V and 20.5 mA
d) 4 V, 10 V and 20 mA
a) 8 mA b) 5 mA [IES – 2012 EC]
c) 0 mA d) -3 mA
[GATE – 2004 EE] Q.60) For a full wave rectifier, with sinusoidal
input and inductor as filter, ripple factor for
Q.2) What are the states of the three ideal maximum load current and minimum load
diodes of the circuit shown in figure? current conditions are respectively
1Ω a) 0.1 and 1 b) 0.1 and 0.47
1Ω c) 0 and 0.47 d) 0 and 0.22
[IES – 2012 EC]
D2
Q.3 For the circuit shown in the figure assume
D1 1Ω D3 5A
ideal diodes with zero forward resistance and
10 V zero forward voltage drop. The current through
the diode D2 in mA is _______.
a) D1 ON, D2 OFF, D3 OFF
b) D1 OFF, D2 ON, D3 OFFc) D1 D2
c) D1 ON, D2 OFF, D3 ON
d) D1 OFF, D2 ON, D3 ON
[GATE – 2006 EE] 200 
10 V 8V
Assuming that the diodes in the given circuit
are ideal, the voltage Vo is 10 V

[GATE – 2014, IN]

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 Rathi classes Analog Electronics
Q.62) The diode in the circuit given below has
VON = 0.7 V but is ideal other wise. The current
(in mA) in the 4 k resistor is _________.

[GATE-2015, EC-02, 2 MARK]

Q.63) For the voltage regulator circuit shown,

the input voltage (Vm) is 20 V  20% and the
regulated output voltage (Vout) is 10 V. Assume
the opamp to be ideal. For a load RL drawing
200 mA, the maximum power dissipation in Q1
(in Watts) is ______.

[GATE-2015, EC-02, 2 MARKS]

Q.64) In the circuit shown, assume that the

diodes D1 and D2 are ideal. The average value
of voltage Vab (in Volts), across terminals ‘a’ and
‘b’ is ________.

[GATE-2015, EC-03, 2 MARKS]

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 Rathi classes Analog Electronics

Chapter – 2 a) Cut-off
c) normal active
b) saturation
d) reverse active
Transistor Biasing, [GATE – 2007 EC]
Stabilization &
Q.4) The transistor circuit shown uses a silicon
Current Mirror Circuit transistor with VBE = 0.7 V, IC ≈ IE and a dc
current gain of 100. The value of Vo is
Q.1) Choose the correct match for input
resistance of various amplifier configurations
shown below

Configuration Input resistance

CB: Common Base LO: Low
CC: Common Collector MO: Moderate
CE: Common Emitter HI: High

a) CB-LO, CC-MO, CE-HI

b) CB-LO, CC-HI, CE-MO
C) CB-MO, CC-HI, CE-LO
d) CB-HI, CC-LO, CE-MO
[GATE – 2003 EC]

Q.2) For an npn transistor connected as shown a) 4.65 V b) 5 V

in the figure, VBE = 0.7 volts. Given that reverse c) 6.3 V d) 7.23 V
saturation current of the junction at room [GATE – 2010 EE]
temperature 300oK is 10-13A, the emitter current
is Q.5) Match List – I (Electronic Circuit) with List
– II (Characteristic) and select the correct
answer using the code given below the lists:
IC
List – I
A. CE
B. CB
C. CC
D. Darlington Pair
List – II
V BE 1. The circuit introduces a phase inversion
of 1800
a) 30 mA b) 39 mA 2. The circuit is rarely used
c) 49 mA d) 20 mA 3. The name, emitter follower is also used
[GATE – 2005 EC] for the circuit.
4. The circuit consists of two circuits
Q.3) For the BJT circuit shown, assume that the connected in cascade.
β of the transistor is very large and VBE = 0.7V. Codes:
The mode of operation o-f the BJT is A B C D
a) 1 2 3 4
b) 2 1 3 4
c) 2 1 4 3
d) 1 2 4 3
[IES – 2007 EC]

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 Rathi classes Analog Electronics
Q.6) CE configuration is the most preferred What is the output voltage V0 in the above
transistor configuration when used as a switch circuit?
because a) 0 V b) 12 V c) 9 V d) 7.5 V
a) It requires only one power supply [IES - 2004 EC]
b) It requires low voltage or current for
operating the switch Q.11) A BJT is biased in forward active mode.
c) It is easily understood by every one Assume VBE = 0.7 V, kT/q = 25 mV and reverse
d) It has small ICEO saturation current Is = 10-13 A. The
[IES – 2008 EC] transconductance of the BJT(in mA/V) is
_________.
Q.7) Why npn-transistors are preferred over [GATE – 2014, EC-01]
pnp-transistors?
a) Leakage current in npn-transistors is less Q.12) In the circuit of the figure, assume that
than pnp-transistors the transistor is in the active region. It has a
b) Mobility of majority carrier in npn-transistors large β and its base-emitter voltage is 0.7V. The
is greater than the mobility of majority carrier value of Ic is
in pnp-transistors 15V
c) Bias voltage required in npn is less than in
pnp-transistors
d) Bias voltage required in npn is greater than 10k Ω RC
in pnp-transistors. IC
[IES – 2009 EC]

Q.8) Assertion (A): It is not desirable to drive a 5k Ω

transistor into hard saturation in high speed 430 Ω
switching circuits.
Reason (R): It may not be possible to bring it
back to cut off state, if it is driven into hard a) Indeterminate since Rc is not given
saturation. b) 1mA
a) Both A and R are individually true and R is c) 5mA
the correct explanation of A d) 10mA
b) Both A and R are individually true but R is [GATE – 2000 EC]
not the correct explanation of A
c) A is true but R is false Q.13) In the amplifier circuit shown in the figure,
d) A is false but R is true the values of R1 and R2 are such that the
[IES – 2009 EC] transistor is operating at VCE = 3V and IC =
1.5mA when its β is 150. For a transistor with β
Q.9) A bipolar junction transistor with forward of 200, the operating point (VCE, IC) is
current transfer ratio α = 0.98, when working in
CE mode, provides current transfer ratio β as
a) 98 b) 0.02 c) 49 d) 0.49
[IES – 2012 EC]

Q.10) Consider the NPN transistor circuit shown

below:

a) (2V, 2mA) b) (3V, 2mA)

c) (4V, 2mA) d) (4V, 1mA)
[GATE – 2003 EC]

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 Rathi classes Analog Electronics
Q.14) Assuming VCEsat = 0.2V and β = 50, the 20V
minimum base current (IB) required to drive the 2kΩ Vo
430kΩ
transistor in the figure to saturation is
3V
IC
10µF
40µF
1kΩ 1kΩ

IB

a) 43μA and 11.4 Volts

b) 40μA and 16 Volts
c) 45μA and 11 Volts
d) 50μA and 10 Volts
[GATE – 2005 EC]

Q.17) In the circuit shown below, the silicon npn

a) 56μA b) 140µA transistor Q has a very high value of β. The
c) 60µA d) 3µA required value of R2 in kΩ to produce IC = 1 mA
[GATE – 2004 EC] is

Q.15) Assuming that the β of the transistor is

extremely large and VBE = 0.7 V, IC and VCE in
the circuit shown in the figure are
5V IC

2.2 kΩ

4kΩ
+
VCE
-
1kΩ
300Ω
a) 20 b) 30 c) 40 d) 50
[GATE – 2013 EC]

Q.18) In the circuit of figure, assume that the

a) IC = 1 mA, VCE = 4.7 V transistor has hFE = 99 and VBE = 0.7 v. the
b) IC = 0.5 mA, VCE = 3.75 V value of collector current ic of the transistor is
c) IC = 1 mA, VCE = 2.5 V approximately.
d) IC = 0.5 mA, VCE = 3.9 V
[GATE – 2004 EC] IC 3.3 kΩ
3.3 kΩ
Q.16) The circuit using a BJT with β = 50 and 12 V
VBE = 0.7V is shown in the figure. The base
current IB and collector voltage VC are
respectively 4V 3.3 kΩ

a) [3.3/3.3] mA. b) [3.3 /(3.3 +.33] mA

c) [3.3/.33] mA d) [3.3/(33+3.3] mA
[GATE – 2003 EE]

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 Rathi classes Analog Electronics
Q.19) Consider the circuit shown in figure. If the
β of the transistor is 30 and ICBO is 20 nA and
the input voltage is +5 V, the transistor would be 2.5 kΩ
operating in Si Transistor
+12 V β=100

2.2 kΩ

15kΩ
Vi Q

100kΩ The transistor is biased at

a) 0 mA b) 5 mA
-12 V c) 3.9 mA d) ∞
[IES – 2002 EC]
a) saturation region b) active region
c) breakdown region d) cut-off region
Q.23) Consider the following circuit:
[GATE – 2006 EE]

Q.20) transistor used in the circuit shown below

has a β of 30 and ICBO is negligible.
2.2 k
15 k
1k D VBE = 0.7 V
VCE(sat) = 0.2 V

Vz = 5V

-12 V

If the forward voltage drop of diode is 0.7 V, What is voltage difference between collector
then the current through collector will be and emitter (VCE) in the above circuit?
a) 168 mA b) 108 mA a) 10/3 V b) 0 V
c) 20.54 mA d) 5.36 mA c) 5 V d) 3 V
[GATE – 2011 EE] [IES – 2004 EC]

Q.24) The transistor circuit shown in the figure

Q.21) The collector voltage VC of the circuit given below is to function as an amplifier. If
shown in the given figure is approximately ICQ = 3 mA, what is the value of VCC
(approximate)?

a) 2 V b) 4.6 V c) 8 V d) 8.6 V
[IES – 1999 EC]

Q.22) In the circuit shown,

a) 15 V b) – 15 V
c) – 10 V d) – 13.5 V
[IES – 2006 EC]
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 Rathi classes Analog Electronics
Q.25) For a CE amplifier, d.c. load line is which 10 V
one of the following plots?
a) IC versus VCE for a given value of (RC + RE) RC
and VCC.
50 kΩ
b) IB versus VEE for a given value of (RC + RE) 5V
and VCC. RB
c) IB versus VCE for a given value of IB.
d) IC versus VCB for a given value of IE.
[IES – 2007 EC] a) For RC = 1 kΩ, the BJT operates in the
saturation region
Q.26) In the circuit shown, the PNP transistor b) For RC = 3 kΩ, the BJT operates in the
has |VBE| = 0.7 V and β = 50. Assume that RB = saturation region
100 kΩ. For V0 to be 5 V, the value of RC(in kΩ) c) For RC = 20 kΩ, the BJT operates in the cut-
is __________. off region
d) For RC = 20 kΩ, the BJT operates in the
linear region.
RC [GATE – 2014, EC-03]
V0 Q.29) The transistor in the given circuit should
always be in active region. Take VCE(sat) = 0.2
V, VBE = 0.7 V. The maximum value of RC in Ω
which can be used, is ____________.
RB VEE = 10 V

RC
+
[GATE – 2014, EC-03] RS= 2kΩ 5V
-
β =100
Q.27) For the common collector amplifier shown +
in the figure, the BJT has high β, negligible 5V
-
VCE(sat), and VBE = 0.7 V. The maximum
undistorted peak-to-peak output voltage vo(in
Volts) is ___________. [GATE – 2014, EE-02]

VCC = + 12 V Q.30) In the given circuit, the silicon transistor

has  = 75 and a collector voltage VC= 9 V.
R1 Then the ratio of RB and RC is ______.
5 kΩ
1 µF
vi
1 µF
R2 vo
10 kΩ RE
1 kΩ

[GATE – 2014, EC-04]

Q.28) In the circuit shown, the silicon BJT has β

= 50. Assume VBE = 0.7 V and VCE (sat) = 0.2 V.
[GATE-2015, EE-01, 1 MARK]
Which one of the following statements is
correct?

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 Rathi classes Analog Electronics
Q.31) In the following circuit, the transistor is in
Vcc = 5V
active mode and VC = 2 V. To get VC = 4 V, we
R
replace RC with RC . Then the ratio C is Rc = 1kΩ
RC
______.
Vout

β = 100
+
Vin 1 mA

[GATE-2015, EE-02, 1 MARK] a) 0 µA b) 10 µA

c) 100 µA d)1000 µA
Q.32) In the circuit shown in the figure, it is [GATE – 2005 EE]
found that VBE = 0.7 V and VE = 0 V. If dc = 99
Q.35) Which one of the following main
for the transistor, then the value of RB in kilo properties of a bipolar junction transistor makes
ohms is _________ k. it necessary for the transistor to have bias
stabilization?
1. Variation of VBE with temperature
2. Variation of hFE with temperature
3. Variation of ICO with temperature
4. Variation of hFE with transistor replacement
5. Variation of VBE with transistors replacement
6. Variation of ICO with transistor replacement
Select the correct answer using the codes given
below:
a) 1, 2 and 6 b) 1, 3 and 4
c) 2, 3 and 5 d) 3, 4, 5 and 6
[IES – 2003 EC]
[GATE-2015, IN, 2 MARKS]
Q.36) Assertion (A): A self-biased BJT circuit is
Q.33) Introducing a resistor in the emitter of a more stable as compared to a fixed to a biased
common amplifier stabilizes the dc operating one.
point against variations in Reason (R): A self-biased BJT circuit uses
a) Only the temperature more components as compared to a fixed
b) Only the β of the transistor biased one.
c) both temperature and β a) Both A and R are true and R is the correct
d) none of the above explanation of A
[GATE – 2000 EC] b) Both A and R are true but R is NOT the
correct explanation of A
Q.34) The common emitter amplifier shown in c) A is true but R is false
the figure is biased using a 1 mA ideal current d) A is false but R is true
source. The approximate base current value is [IES – 2003 EC]

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 Rathi classes Analog Electronics
Q.37) Operating point shift can occur in an Q.41) Consider the following statements:
amplifier due to which one of the following? Bias stabilization in a BJT circuit is very
a) Input frequency variation important, because it
b) Noise at the input 1. Provides high voltage and current gain.
c) Parasitic capacitances 2. Ensures large bandwidth of the amplifier.
d) Power supply fluctuation 3. Keeps the operating point unchanged with
[IES – 2007 EC] change of temperature.
Which of the above statement(s) is/are correct?
Q.38) Consider the following statements: a) 1 and 2 b) 2 and 3
The bias stability of an emitter – bias amplifier c) 3 only d) 1 and 3
circuit improves by [IES – 2008 EC]
1. Decreasing the value of RB.
2. Increasing the value of RE. Q.42) In the silicon BJT circuit shown below,
3. Decreasing the value of RE. assume that the emitter area of transistor Q1 is
4. Increasing the value of RB. half that of transistor Q2.
5. Increasing the value of RC. I0
Which of the above statements are correct?
a) 1 and 2 b) 2 and 3 R = 9.3 kΩ
c) 3 and 4 d) 4 and 5
[IES – 2009 EC]
Q1 Q2
Q.39) Consider the following statements: (β1 = 700) (β2 = 715)
The basic purpose of bias stabilization in a
transistor circuit is to
1. Increase the voltage and current gain of the
amplifier. -10 v
2. Make the operating point of the transistor
independent of temperature variation of the The value of current Io is approximately
transistor. a) 0.5 mA b) 2 mA
3. Make the operating point independent of the c) 9.3 mA d) 15 mA
replacement of the same type, Ge or Si. [GATE – 2010 EC]
Which of the statements given above are
correct? Q.43) Two perfectly matched silicon transistors
a) 1 and 2 only b) 2 and 3 only are connected as shown in figure. The value of
c) 1 and 3 only d) 1, 2 and 3 the current I is
[IES – 2007 EC] +3V

1kΩ I
Q.40) Assertion (A): A fixed bias BJT circuit
exhibits better performance as compared to a ß=1000 ß=1000
+
self bias BJT circuit. 0.7 V
Reason (R): A fixed bias BJT circuit uses less
components as compared to a self bias BJT
circuit.
a) Both A and R are individually true and R is -5V
the correct explanation of A. a) 0 mA b) 2.3 mA
b) Both A and R are individually true but R is c) 4.3 mA d) 7.3 mA
not the correct explanation of A. [GATE – 2004 EE]
c) A is true but R is false
d) A is false but R is true
[IES – 2009 EC]

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 Rathi classes Analog Electronics
Q.44) Two perfectly matched silicon transistor Q.47) In the circuit shown in the given figure,
are connected as shown in the figure. Assuming the current flowing through resistance of 100 Ω
the β of the transistors to be very high and the would be
forward voltage drop in diodes to be 0.7 V, the
value of current is
+5V
1kΩ

Q1 Q2
-5V
a) 0 mA b) 3.6 mA
c) 4.3 mA d) 5.7 mA

Q.45) The matched transistors Q1 and Q2

a) 8 mA b) 10 mA c) 20 mA d) 100 mA
shown in the adjoining figure have β = 100.
[IES – 2000 EC]
Assuming the base-emitter voltage to be 0.7 V,
the collector-emitter voltage V2 of the transistor
Q2 is
Q.48) In the circuit shown, I1 = 80 mA and I2 = 4
+12 V +50 V
mA. Transistors T1 and T2 are indentical.
10 kΩ 20 kΩ Assume that the thermal voltage VT is 26 mV at
27 °C. At 50 °C, the value of the voltage V12 =
V1 – V2 (in mV) is _______.
Q1 Q2

V2

a) 33.9 V b) 27.8 V
c) 16.2 V d) 0.7 V
[GATE - 2010 IE]

Q.46) In the figure, transistor, T1 and T2 have [GATE-2015, EC-01, 2 MARKS]

identical characteristics. VCE(sat) of transistor T3
is 0.1 V. The voltage V1 is high enough to put T3
in saturation. Voltage VBE of transistor T1, T2
and T3 is 0.7 V. The value of (V1 – V2) in V is
_______.

[GATE – 2014, IN]

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 Rathi classes Analog Electronics

Chapter – 3 Statement for linked Answer Questions 5

and 6:
Low frequency Analysis In the following transistor circuit, VBE = 0.7 V, re
= 25 mV/IE, and β and all the capacitances are
Of BJT very large.
Q.1) A bipolar transistor is operating in the V CC = 9V
active region with a collector current of 1mA. 20 k 3 k
Assuming that the β of the transistor is 100 and
the thermal voltage (VT) is 25mV, the
transconductance (gm) and the input resistance CC2
(rπ) of the transistor in the common emitter C C1
configuration, are 10 k IE
a) gm = 25mA/V and rπ = 15.625 kΩ 2.3 k CE 3 k
b) gm = 40mA/V and rπ = 4.0kΩ
c) gm = 25mA/V and rπ = 2.5kΩ
d) gm = 40mA/V and rπ = 2.5kΩ
[GATE – 2004 EC]
Q.5) The Value of DC current IE is
Common Data for Questions 2, 3 & 4 a) 1 mA b) 2 mA c) 5 mA d) 10 mA
In the transistor amplifier circuit shown in the [GATE – 2008 EC]
figure below, the transistor has the following
parameters: Q.6) The mid – band voltage gain of the
βDC = 60, VBE = 0.7V, hie → ∞, hfe → ∞ amplifier is approximately
The capacitance CC can be assumed to be a) -180 b) -120 c) -90 d) -60
infinite. [GATE – 2008 EC]
12V
Q.7) The amplifier circuit shown below uses a
1KΩ
53K silicon transistor. The capacitors CC and CE can
be assumed to be short at signal frequency and
+
5.3K the effect of output resistance r0 can be ignored.
Vo If CE is disconnected from the circuit, which one
Cc
of the following statements is TRUE?
Vs -
VCC = 9 V

Q.2) Under the DC conditions, the collector-to-

emitter voltage drop is
a) 4.8 Volts b) 5.3 Volts RB= 800 kΩ RC = 2.7 kΩ
Vo
c) 6.0 Volts d) 6.6 Volts
CC CC
[GATE – 2006 EC] β = 100
Vi
Q.3) If βDC is increased by 10%, the collector-to-
emitter voltage drop Vs
a) increases by less than or equal to 10% RE = 0.3 kΩ CE
b) decreases by less than or equal to 10% RI R0
c) increases by more than 10%
d) decreases by more than 10%
[GATE – 2006 EC]
a) The input resistance Ri increases and the
Q.4) The small-signal gain of the amplifier V0/Vs magnitude of voltage gain Av decreases.
is b) The input resistance Ri decreases and the
a) – 10 b) – 5.3 c) 5.3 d) 10 magnitude of voltage gain Av increases.
[GATE – 2006 EC]

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 Rathi classes Analog Electronics
c) Both input resistance Ri and the magnitude Q.11) The transconductance gm of the
of voltage gain Av decreases transistor shown in figure is 10 mS. The value
d) Both input resistance Ri and the magnitude of the input resistance RIN is
of voltage gain Av increase.
[GATE – 2010 EC]

Common Data for Questions 8 and 9:

Consider the common emitter amplifier shown
below with the following circuit parameters:
β = 100, gm = 0.3861 A/V, ro = ∞, rπ = 259 Ω, RS
= 1 kΩ, RB = 93 kΩ, RC = 250 Ω, RL = 1 kΩ, C1
= ∞ and C2 = 4.7 µF.
+10 V

RB RC

C2 a) 10.0 kΩ b) 8.3 kΩ
C1 + c) 5.0 kΩ d) 2.5 kΩ
RS V0 RL [GATE – 2004 EE]
+ -
Vs Q.12) In the amplifier circuit shown below,
- assume VBE = 0.7 V and the β of the transistor
and the values of C1 and C2 are extremely high.
If the amplifier is designed such that at the
quiescent point its VCE = VCC/2, where VCC is the
Q.8) The resistance seen by the source Vs is power supply voltage, its small signal
a) 250 Ω b) 1258 Ω c) 93 kΩ d) ∞ 𝑉
Voltage gain | 𝑉𝑜𝑢𝑡 | will be
[GATE – 2010 EC] 𝑖𝑛

Q.9) The lower cut – off frequency due to C2 is

a) 33.9 Hz b) 27.1 Hz
c) 13.6 Hz d) 16.9 Hz
[GATE – 2010 EC]

Q.10) The voltage gain AV, of the circuit shown

below is

a) 3.75 b) 4.5 c) 9 d) 19
[GATE - 2008 IE]

a) |AV| = 200 b) |Av| = 100

c) |Av| = 20 d) |Av| = 10
[GATE – 2012 EC]

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 Rathi classes Analog Electronics
Q.13) An amplifier circuit is shown in the given Q.17) A common emitter transistor amplifier has
figure: (VT = 25 mV) a collector load of 10 kΩ. If its
ℎ𝑓𝑒 = 100 𝑎𝑛𝑑 ℎ𝑖𝑒 = 2 𝑘𝛺 (ℎ𝑟𝑒 ≈ ℎ𝑜𝑒 ≈ 0), the
voltage amplification of the amplifier is nearly
equal to
a) 500 b) 200 c) 100 d) 50
[IES - 2011 EC]

Q.18) The amplifier shown below as a voltage

gain of -2.5, an input resistance of 10 kΩ and a
lower 3-dB cut – off frequency of 20 Hz. Which
The voltage gain (V0/VS) is one the following statements is TRUE when the
a) 4/3.33 b) 100 c) 150 d) 160 emitter resistance RE is doubled?
[IES - 2000 EC] V CC

Q.14) Which of the following will be true for a R1 RC

CE transistor amplifier if the emitter resistor VO
value is made equal to zero? CB CC
1. Its gain will increase Q1 RL
2. Its stability will increase
3. Its gain will decrease
4. Its stability will decrease. VS ~ R2
Select the correct answer from the codes given RE
below:
a) 1 and 2 b) 2 and 3
c) 3 and 4 d) 1 and 4
[IES - 2009 EC] a) Magnitude of voltage gain will decrease
b) Input resistance will decrease
Q.15) A small signal voltage amplifier in c) Collector bias current will increase
common emitter configuration was working d) Lower 3-dB cut-off frequency will increase
satisfactorily. Suddenly its emitter – bypass [GATE - 2011 IE]
capacitor (CE) got disconnected. Its:
Q.19) For the amplifier shown in the figure, the
1. Voltage gain will decreases BJT parameters are VBE = 0.7 V, β = 200, and
2. Voltage gain will increase thermal voltage VT = 25 mV. The voltage gain
3. Bandwidth will decreases (vo/vi) of the amplifier is ______________.
4. Bandwidth will increase
Which of these statements are correct? VCC = + 12 V
a) 1 and 4 only b) 2 and 3 only
c) 3 and 4 only d) 1, 2, 3 and 4 RC
R1
[IES - 2011 EC] 33 kΩ 5 kΩ
vo
1 µF
Q.16) A CE amplifier has an unbypassed 1 µF
vi
emitter resistance of 0.5 kΩ and a collector load
of 5 kΩ. The β of the transistor is 100 and it is
operating at 1 mA. The voltage gain of the R2 Rs
amplifier at mid band will be of the order of 11 kΩ 10 Ω
a) 200 b) 100 c) 10 d) 50
[IES - 2011 EC] RE CE
1 kΩ 1 mF

[GATE – 2014 EC-01]

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 Rathi classes Analog Electronics
Q.20) If the emitter resistance in a a) 1 b) 10 c) 20 d) 100
common-emitter voltage amplifier is not [GATE – 2014, EE-01]
bypassed, it will
a) reduce both the voltage gain and the input Q.23) In the ac equivalent circuit shown, the two
impedance BJT’s are biased in active region and have
b) reduce the voltage gain and increase the identical parameters with   1. The open
input impedance circuit small signal voltage gain is approximately
c) increase the voltage gain and reduce the ________.
input impedance
d) increase both the voltage gain and the input
impedance.
[GATE – 2014 EC-04]

Q.21) Consider the common-collector amplifier

in the figure (bias circuitry ensures that the
transistor operates in forward active region, but
has been omitted for simplicity). Let IC be the
collector current, VBE be the base-emitter
voltage and VT be the thermal voltage. Also, gm [GATE-2015, EC-02, 2 MARKS]
and ro are the small-signal transconductance
and output resistance of the transistor,
respectively. Which one of the following
conditions ensures a nearly constant small
signal voltage gain for a wide range of values of
RE?
VCC

Vin

Vout
RE

a) gmRE<<1 b) ICRE>>VT
c) gmro>>1 d) VBE >> VT
[GATE – 2014 EC-04]

Q.22) The magnitude of the mid-band voltage

gain of the circuit shown in figure is (assuming
hfe of the transistor to be 100)

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 Rathi classes Analog Electronics

Chapter – 4 ib B C

High frequency Analysis r0

rp
Of BJT
E

Q.1) An npn transistor (with C = 0.3 pF) has a

a) 250 Ω b) 27.5 Ω
unity – gain cutoff frequency fT of 400 MHz at a
dc bias current Ic = 1mA. The value of its Cμ (in c) 25 Ω d) 22.5 Ω
pF) is approximately (VT = 26mV) [GATE – 2012 EC]
a) 15 b) 30 c) 50 d) 96
[GATE – 1999 EC] Q.7) A BJT is to be used in a high frequency
circuit in common emitter amplifier. For a higher
upper cut-off frequency (Cµ, Cπ and r0 have their
Q.2) The current gain of a BJT is
gm gm
usual meanings)
a) gmro b) ro
c) gmrπ d) rπ a) Cµ should be as small as possible
[GATE – 2001 EC] b) r0 and Cµ should be as large as possible
c) Cπ and Cµ should be as large as possible
d) r0, Cπ and Cµ should be as large as possible
Q.3) The current gain of a bipolar transistor
[IES – 2002 EC]
drops at high frequencies because of
a) Transistor capacitances
Q.8) Consider the following statements:
b) high current effects in the base
1. To achieve wide bandwidth, a transistor with
c) parasitic inductive elements
a small Cb`c is chosen.
d) the Early effect 2. To achieve wide bandwidth, a transistor with
[GATE – 2000 EC] a small Cb`e is chosen.
3. To achieve wide bandwidth, a transistor with
Q.4) An npn BJT has gm = 38mA/V, Cπ = 10-14F, a small base spreading resistance is chosen.
Cπ = 4x10-13F, and DC current gain β0 = 90. For
this transistor fT and fβ are Which of the statements given above are
a) 8 10
fT = 1.64x10 Hz and fβ = 1.47x10 Hz correct?
b) fT = 1.47x1010 Hz and fβ = 1.64x108Hz a) 1 and 2 b) 2 and 3
c) fT = 1.33x1012 Hz and fβ = 1.47x1010Hz c) 1 and 3 d) 1, 2 and 3
d) fT = 1.47x1010 Hz and fβ = 1.33x1012Hz [IES – 2005 EC]
[GATE – 2001 EC]
Q.9) Which of the transistor models is most
Q.5) Generally, the gain of a transistor amplifier preferred for the analysis of a transistor circuit
falls at high frequencies due to the both at mid – band and at high frequencies?
a) internal capacitances of the device a) h – parameter model
b) coupling capacitor at the input b) y – parameter model
c) skin effect c) s – parameter model
d) coupling capacitor at the output d) hybrid – π model
[GATE – 2001 EC] [IES – 2009 EC]

Q.6) The current ib through the base of a silicon

npn transistor is 1 + 0.1 cos (10000 πt) mA. At
300 K, the rπ in the small signal model of the
transistor is
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 Rathi classes Analog Electronics
Q.10) The common emitter current gain-
bandwidth product of a transistor (fT) is defined
as the frequency at which
a) Alpha of the transistor falls by 3 dB
b) Beta of the transistor falls by 3 dB
c) Beta of the transistor falls to unity
d) Power gain of the transistor falls to unity
[IES – 2003 EC]

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 Rathi classes Analog Electronics

Chapter – 5 a)

Multistage Amplifiers & IGainl

Differential Amplifiers Frequency

b)
Q.1) In the cascode amplifier shown in the IGainl
figure, if the common-emitter stages (Q1) has a
transconductance gm1, and the common base Frequency
stage (Q2) has a transconductance gm2, then the c)
overall transconductance g(=i0/Vi) of the
cascade amplifier is IGainl
Q2
I0 Frequency
V0
d)

IGainl
RL
Vi Q1
Frequency
[GATE – 2005 EE]
a) gm1 b) gm2 c) gm1/2 d) gm2/2 Q.6) The given figure shown a composite
[GATE – 1999 EC] transistor consisting of a MOSFET and a bipolar
transistor in cascade
Q.2) An amplifier is assumed to have a single-
pole high-frequency transfer function. The rise
time of its output response to a step function
input is 35 nsec. The upper -3 dB frequency (in
MHz) for the amplifier to a sinusoidal input is
approximately at C is very large
a) 4.55 b) 10 c)20 d) 28.6
[GATE – 1999 EC]

Q.3) Three identical amplifiers with each one The MOSFET has a trans-conductance gm of 2
having a voltage gain of 50, input resistance of mA/V and the bipolar transistor has 𝛽( ∆= ℎ𝑓𝑒 ) of
1KΩ and output resistance of 250Ω, are 99. The overall transconductance of the
cascaded. The open circuit voltage gain of the composite transistor is
combined amplifier is a) 198 mA/V b) 19.8 mA/V
a) 49 dB b) 51 dB c) 1.98 A/V d) 1.98 mA/V
c) 98 dB d) 102 dB [IES – 1999 EC]
[GATE – 2003 EC]
Q.7) Consider the following statements
Q.4) The cascode amplifier is a multistage regarding the bootstrap biasing arrangement for
configuration of a BJT emitter follower:
a) CC-CB b) CE-CB 1. The input impedance is very high.
c) CB-CC d) CE-CC 2. The voltage gain is exactly equal to one.
[GATE – 2005 EC] 3. The output impedance is equal to zero.
Which of these statements is correct?
Q.5) The typical frequency response of a two- a) None b) 2 alone
stage direct coupled voltage amplifier is as c) 3 alone d) 1 alone
shown in [IES – 2000 EC]

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 Rathi classes Analog Electronics
Q.8) Consider the following statements: Select the correct answer the using the codes
The lower cut-off frequencies for an RC coupled given below:
CE amplifier depend on a) 1 and 2 b) 2 and 3
1. input and output coupling capacitors c) 3 and 4 d) 1, 2 and 4
2. emitter bypass capacitor [IES – 2003 EC]
3. junction capacitors
Which of these statements is/are correct? Q.14) Assertion (A): If the emitter bypass
a) 1 alone b) 2 alone capacitor of an R-C coupled, CE amplifier gets
c) 1 and 2 d) 2 and 3 disconnected, its voltage gain increase.
[IES – 2000 EC] Reason (R): The unbypassed emitter resistor
gives negative feedback.
Q.9) If the Q of a single-stage signal-tuned a) Both A and R are true and R is the correct
amplifier is doubled, then its bandwidth will explanation of A
a) remain same b) become half b) Both A and R are true but R is NOT the
c) become double d) become four times correct explanation of A
[IES – 2000 EC] c) A is true but R is false
d) A is false but R is true
Q.10) An RC amplifier stage has a bandwidth of [IES – 2003 EC]
500 kHz. What will be rise time of this amplifier
stage? Q.15) A tuned amplifier has a voltage gain of
a) 0.35 µs b) 0.7 µs 100 and a bandwidth of 10 kHz. It is required to
c) 1.0 µs d) 2.0 µs increase the bandwidth to 20 kHz. This can be
[IES – 2002 EC] achieved by which one of the following ways?
a) By doubling the gain
Q.11) Consider the following statements in b) By doubling the resonant frequency
respect of a transistor R-C coupled amplifier: c) By halving the Q of the coil
1. The low frequency response is determined d) By halving the power supply voltage
by the transistor junction capacitors. [IES – 2004 EC]
2. The high frequency response is limited by
coupling capacitors. Q.16) Assertion (A): In a Darlington connection,
3. The Miller capacitance reduces the gain at two transistors are connected in cascade in
high frequencies. common emitter configuration.
4. As the gain is increased the bandwidth gets
reduced. Reason (R): The Darlington connection aims at
Which of these statements are correct? making the current gain very high, almost equal
a) 1 and 2 b) 2 and 3 to the product of beta of individual transistors.
c) 3 and 4 d) 1 and 4
[IES – 2003 EC] a) Both A and R are true and R is the correct
explanation of A
Q.12) An amplifier has two identical cascaded b) Both A and R are true but R is NOT the
stages. Each stage has a bandwidth of 20 kHz. correct explanation of A
The overall bandwidth shall approximately be c) A is true but R is false
equal to d) A is false but R is true
a) 10 kHz b) 12.9 kHz [IES – 2005 EC]
c) 20 kHz d) 28.3 kHz
[IES – 2003 EC] Q.17) A transistor RC coupled amplifier is
designed for a voltage and band gain of 20. But
Q.13) Which of the following components a measurement at a particular frequency shows
control the low frequency of the R-C coupled the gain to be only 14. What is the likely phase
amplifier? shift at this frequency?
1. Wiring capacitance a) 1800 b) 1350
2. Parasitic capacitance of transistor c) 900 d) 450
3. Coupling capacitances [IES – 2005 EC]
4. Emitter bypass capacitance

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29
 Rathi classes Analog Electronics
Q.18) A cascaded amplifier comprises N c) 80 kHz, 2.04 MHz, 1.96 MHz
identical non-interacting of fL. If fL* is the lower 3 d) 80 kHz, 2.08 MHz, 1.92 MHz
dB frequency of the cascade amplifier, then [IES – 2007 EC]
which one of the following is correct?
Q.24) For the amplifier shown in the figure
a) 𝑓𝐿∗ = 𝑓𝐿 given below, the lower cut-off frequency
b) 𝑓𝐿∗ = 𝑓𝐿 √21/𝑁 − 1 depends on which of the following?
c) 𝑓𝐿∗ = 𝑓𝐿 /√21/𝑁 − 1 +V
+

𝑓𝐿∗
CC
d) = 𝑓𝐿 /𝑁
[IES – 2005 EC]
RC
Q.19) The two stages of a cascade amplifier R1 CC
have individual upper cut-off frequency f1 = 5 Vout
CS
MHz and f2 = 3.33 MHz. what is the best
approximation for the upper cut-off frequency of RL
the cascade combination? RS
a) 4.16 MHz b) 3.33 MHz R2
RE
c) 2.5 MHz d) 5.00 MHz CE
VS
[IES – 2006 EC]

Q.20) Which one of the following statements is

correct? a) CS, CE, internal junction capacitances of
The rise time of an amplifier is transistor.
a) Directly proportional to the upper 3-dB b) Strong wiring capacitance (Cw), CC
frequency c) CS, CE, CC
b) Inversely proportional to the upper 3-dB d) CS, CE only
frequency [IES - 2007 EC]
c) Directly proportional to the lower 3-dB
frequency Q.25) Consider the following statements:
d) Inversely proportional to the lower 3-dB Tuned amplifiers
frequency 1. Are wide band amplifier
[IES – 2007 EC] 2. Are used in radio transmitters and receivers
3. Performance is determined by Q of the circuit
Q.21) The 3-dB cut-off frequency of a d.c. Which of the statements given above are
amplifier is 5 MHz. What is its rise time? correct?
a) 350 ns b) 200 ns a) 1 and 2 only b) 2 and 3 only
c) 70 ns d) 35 ns c) 1 and 3 only d) 1, 2 and 3
[IES – 2007 EC] [IES – 2008 EC]

Q.22) In an amplifier, the power output is 2W at Q.26) Which of the following components
5 kHz, and 0.5 W at 50 Hz. If the input power is control the high frequency response of the R –
constant at 10 mW, what is the variation C coupled amplifier?
(approximate) of power gain in dB at two 1. Parasitic capacitances of the transistor
frequencies? (𝑙𝑜𝑔10 2 ≈ 0.30) 2. Coupling capacitance
a) 6 dB b) 8 dB 3. Stray capacitances
c) 3 dB d) 16 dB 4. Wiring capacitance
[IES – 2007 EC] Select the correct answer using the code given
below:
Q.23) A tuned amplifier has peak output at 2 a) 1 and 2 only b) 2 and 3 only
MHz and quality factor 50. The bandwidth and 3 c) 3 and 4 only d) 1, 3 and 4
– dB frequencies shall be at what values [IES – 2008 EC]
respectively?
a) 40 kHZ, 2.02 MHz, 1.98 MHz
b) 40 kHz, 2.04 MHz, 1.96 MHz
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 Rathi classes Analog Electronics
Q.27) In an RC coupled transistor amplifier respectively. If the resistance RE is increased,
then .
1. Low – frequency response is determined by VCC
coupling capacitors.
2. High – frequency response is determined by RC RC
junction capacitances.
VO
3. Mid – frequency response is determined by + -
both coupling and junction capacitances. +
Which of the following will be corrc? Vi
a) 1 and 2 only b) 1 and 3 only
c) 2 and 3 only d) 1, 2 and 3 -
[IES – 2011 EC]
RE IO
Q.28) The peak output of a tuned amplifier is at
6 MHz and has quality factor of 60. The
bandwidth and 3 dB frequencies shall be -VEE
a) 100 MHz, 6.05 MHz and 5.95 MHz a) Acm increases
b) 6 MHz, 9 MHz and 3 MHz b) common-mode rejection ratio increases
c) 600 kHz, 6.6 MHz and 5.4 MHz
c) Ad increases
d) 100 kHz, 6.05 MHz and 5.95 MHz
d) common-mode rejection ratio decreases
[IES – 2011 EC]
[GATE - 2014 EC-02]
Q.29) The lower 3 dB frequency of an n – stage
Q.33) A cascade connection of two voltage
amplifier with non – interacting stages is given
amplifiers A1 and A2 is shown in the figure. The
by
𝑓𝐿 open-loop gain Av0, input resistance Rin, and
a) 1/𝑛 b) 𝑓𝐿 [√21/𝑛 − 1]
√2 −1 output resistance Ro for A1 and A2 are as
follows:
𝑓𝐿
c) d) 𝑓𝐿 [√21/𝑛 − 𝑛] A1 : Av0 = 10, Rin = 10 kΩ, Ro = 1 kΩ.
√21/𝑛 −𝑛
[IES – 2012 EC] A2 : Av0 = 5, Rin = 5 kΩ, Ro = 200 Ω.
The approximate overall voltage gain Vout/Vin is
Q.30) A change in the value of the emitter __________.
resistance Re in a differential amplifier
a) Affects the difference mode gain, Ad
b) Affects the common mode gain, Ac + +
c) Affects both Ad and Ac
d) Does not affect either Ad or Ac Vin RL V
A1 A2 out
[IES – 2012 EC] 1 kΩ
- -
Q.31) The transfer function of a transistor
amplifier is given by
𝑉𝑜 4240 [GATE – 2014, EC-02]
𝐴v = =
𝑉𝑠 (1 + 𝑗 𝑓 𝑓
) (1 + 𝑗 )
4 × 105 4 × 106
Which one of the following gives the
approximate upper 3-dB frequency fH* of the
amplifier?
a) 4 × 105 𝐻𝑧 b) 2.2 × 106 𝐻𝑧
6
c) 4 × 10 𝐻𝑧 d) 4.4 × 106 𝐻𝑧
[IES - 2004 EC]

Q.32) In the differential amplifier shown in the

figure, the magnitudes of the common-mode
and differential- mode gains are Acm and Ad,
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 Rathi classes Analog Electronics

Chapter – 6 Q.4) ID and VDS under DC conditions are

respectively
Low & High Frequency a) 5.625 mA and 8.75 V
Analysis of FET b) 7.500 mA and 5.00 V
c) 4.500 mA and 11.00 V
V0 d) 6.250 mA and 7.50 V
Q.1) The voltage gain Av = of the JFET [GATE – 2005 EC]
Vi
amplifier shown in the figure is Q.5) Transconductance in milli-Siemens (mS)
VDD =+10V and voltage gain of the amplifier are
ID =1mA respectively
RD a) 1.875 mS and 3.41
C2
(3KΩ) b) 1.875 ms and - 3.41
C1
+
c) 3.3 mS and – 6
Vo
d) 3.3 mS and 6
+
Vi
RG
RS
[GATE – 2005 EC]
(1KΩ) CS
(2.5KΩ)
Q.6) Two identical NMOS transistors M1 and M2
are connected as shown below. Vbias is chosen
IDSS = 10mA Vp = -5V so that both transistors are in saturation. The
∂Iout
(Assume C1, C2 and Cs to be very large) equivalent gm of the pair is defined to be ∂V at
i
a) +18 b) – 18 c) +6 d) – 6 constant Vout.
[GATE – 2002 EC]
Iout
Q.2) The action of a JFET in its equivalent Vout
circuit can best be represented as a
a) Current Controlled Current Source Vbias M2
b) Current Controlled Voltage Source
c) Voltage Controlled Voltage Source
d) Voltage Controlled Current Source
Vi M1
[GATE – 2003 EC]

Common Data Questions 4, 5, 6

Given, rd=20kΩ, IDSS=10mA, Vp= -8V
The equivalent gm of the pair is
a) The sum of individual gm’s of the transistors
b) The product of individual gm’s of the
transistors
c) Nearly equal to the gm of M1
d) Nearly equal to gm/g0 of M2

Statement for common data Q. 7 and Q. 8

Assume that the threshold voltage of the N-
channel MOSFET shown in figure is + 0.75 V.
the output characteristics of the MOSFET are
also shown.
Q.3) Zi and Zo of the circuit are respectively

a) 2MΩ and 2kΩ

20
b) 2MΩ and kΩ
11
c) infinity and 2MΩ
20
d) infinity and 11 kΩ
[GATE – 2005 EC]
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32
 Rathi classes Analog Electronics
VDD = 25 V Q.10) Consider the following statements:
In JFET amplifiers, high frequency response
R = 10kΩ can be improved by using peaking circuits
containing inductors
Vout 1. In series with drain resistance RD
2. In series with the coupling capacitance
3. As a feedback element between drain and
+ gate
Vin = 2mV Which of the statements given above are
~ correct?
a) 1 and 2 b) 2 and 3
2V c) 1 and 3 d) 1, 2 and 3
[IES – 2004 EC]
IDs = 1 (mA)
Vgs = 4 V Q.11) Assertion (A): The self bias technique as
4 used for a JFET cannot be used for establishing
3V an operating point for the enhancement
3
MOSFET.
2V
2
Reason (R): The voltage drop across RS is such
1V that it reverses biases the gate
a) Both A and R are true and R is the correct
1 explanation of A
b) Both A and R are true but R is NOT the
0 correct explanation of A
VDs(V) c) A is true but R is false
d) A is false but R is true
Q.7) The transconductance of the MOSFET is [IES – 2005 EC]
a) 0.75 ms b) 1 ms
c) 2 ms d) 10 ms Q.12) For the circuit shown below if gm = 3 x
[GATE – 2005 EE] 10-3 & Rs = 3000 Ω, then what is the value of
R0?
Q.8) The voltage gain of the amplifier is
a) +5 b) -7.5 c) +10 d) -10
[GATE – 2005 EE]

Q.9) The parameters of the JEET in figure are :

gm = 1 mA/V, rd = 15 kΩ. Neglecting the effect of
the capacitor for A.C. analysis, the small signal
A.C. voltage gain for the circuit is

a) 3000 Ω b) 1000/3 Ω
c) 300 Ω d) 100 Ω
[IES – 2006 EC]

Q.13) What is the main advantage of a JFET-

cascade amplifier?
a) High voltage gain
b) Low input impedance
c) Very low input impedance
d) High input impedance
[IES – 2006 EC]
a) -30 b) -10 c) +4 d) +60
[GATE – 2004 IN]

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33
 Rathi classes Analog Electronics
Q.14) In an FET common-source high
frequency amplifier, which one of the following
is the correct expression for input capacitance
Ci?
a) 𝐶𝑖 = 𝐶𝑔𝑠 + (1 − 𝐴v )𝐶𝑔𝑑
b) 𝐶𝑖 = 𝐶𝑔𝑠 + (1 − 1/𝐴v )𝐶𝑔𝑑
c) 𝐶𝑖 = 𝐶𝑔𝑑 + (1 − 𝐴v )𝐶𝑔𝑠
d) 𝐶𝑖 = 𝐶𝑔𝑑 + (1 − 1/𝐴v )𝐶𝑔𝑠
[IES – 2006 EC]

Q.15) The drain gate capacitance of a junction

FET is 2pF. Assuming a common source
voltage gain of 20, what is the input capacitance
due to Miller effect?
a) 21 pF b) 40 pF
c) 42 pF d) 10 pF
[IES – 2006 EC]

Q.16) Which one of the following gain equations

is correct for a MOSFET common-source
amplifier? (gm is mutual conductance, and RD is
load resistance at the drain)
a) 𝐴v = 𝑔m /𝑅𝐷 b) 𝐴v = 𝑔m 𝑅𝐷
c) 𝐴v = 𝑔m /(1 + 𝑅𝐷 ) d) 𝐴v = 𝑅D /𝑔𝑚
[IES – 2007 EC]

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34
 Rathi classes Analog Electronics

Chapter – 7 c) decease both input and output

resistance
Feed Back Amplifiers d) decrease the input resistance and
increase the output resistance
Q.1) Negative feedback in an amplifier [GATE – 2005 EC]
a) Reduces gain
b) Increases frequency and phase distortions Q.6) In a transconductance amplifier, it is
c) Reduces bandwidth desirable to have
d) Increases noise a) a large input resistance and a large output
[GATE – 1999 EC] resistance
b) a large input resistance and a small output
Q.2) An amplifier has an open-loop gain of 100, resistance
an input impedance of 1kΩ, and output c) a small input resistance and a large output
impedance of 100 Ω. A feedback network with a resistance
feedback factor of 0.99 is connected to the d) a small input resistance and a small output
amplifier in a voltage series feedback mode. resistance
The new input and output impedances, [GATE – 2007 EC]
respectively, are
a) 10Ω and 1Ω b) 10Ω and 10Ω Q.7) In the circuit shown below, the op – amp is
c) 100Ω and 1Ω d) 100kΩ and 1kΩ ideal, the transistor has VBE = 0.6 V and β =
[GATE – 1999 EC] 150. Decide whether the feedback in the circuit
is positive or negative and determine the
Q.3) In a negative feedback amplifier using voltage V at the output of the op – amp.
voltage-series (i.e voltage-sampling, series 10 V
mixing) feedback.
5kΩ
a) Ri decreases and Ro decreases
b) Ri decreases and Ro increases V
c) Ri increases and Ro decreases +
d) Ri increases and Ro increases -
(Ri and Ro denote the input and output
resistance respectively) 1.4kΩ 5V
[GATE – 2002 EC]

Q.4) Voltage series feedback (also called a) Positive feedback, V = 10 V

series-shunt feedback) results in b) Positive feedback , V = 0 V
a) increase in both input and output c) Negative feedback, V = 5 V
impedances d) Negative feedback, V = 2 V
b) decrease in both input and output [GATE – 2009 EC]
impedances
c) increase in input impedance and decrease in Q.8) The feedback used in the circuit shown in
output impedance figure can be classified as
d) decrease in input impedance and increase
in output impedance
[GATE – 2004 EC]

Q.5) The effect of current shunt feedback in an

amplifier is to
a) increase the input resistance and
decrease the output resistance
b) increase both input and output
resistance

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 Rathi classes Analog Electronics
a) Shunt-series feedback +15 V
b) Shunt-shunt feedback
c) Series-shunt feedback
d) Series-series feedback
[GATE – 2003 EE] 1 µF
Vi
Q.9) The nature of feedback in the opamp
circuit shown is
+6V Vo
2kΩ
1kΩ
- 1 MΩ 1.5 MΩ
+
Vout

Vin ~ -6V
The nature of feedback in this circuit is
a) Positive current b)Negative current
a) Current – Current feedback c) Positive voltage d) Negative voltage
b) Voltage – Voltage feedback [GATE – 2007 IE]
c) Current – Voltage feedback
d) Voltage – Current feedback Q.12) (A): A large negative feedback is
[GATE – 2009 EE] deliberately introduced in an amplifier to make
its gain independent of the variation of
Q.10) In a Voltage feedback as shown below, parameters of the active device and other circuit
which one of the following statements is TRUE components.
if the gain k is increased? Reason (R): A large negative feedback result in
+ + A0 + a high value of return difference compared to
- Vin V1 - Vout -
unity, which makes the feedback gain inversely
proportional to the feedback factor.
a) Both A and R are true and R is the correct
explanation of A
b) Both A and R are true but R is NOT the
+ k + correct explanation of A
V f = k Vout - - c) A is true but R is false
d) A is false but R is true
a) The input impedance increases and output [IES – 1999 EC]
impedance decreases.
b) The input impedance increases and output Q.13) The given circuit has a feedback factor of
impedance also increases.
c) The input impedance decreases and output
impedance also decreases.
d) The input impedance decrease and output
impedance increases.
[GATE – 2013 EC/EE]

Q.11) A FET source follower is shown in the

figure below:

a) – 𝑅𝐶 /𝑅𝑆 b) – 𝑅𝐸 /𝑅𝐶
c) – 𝑅𝐸 /𝑅𝑆 d) – 𝑅𝐶 /𝑅𝐸
[IES – 1999 EC]

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 Rathi classes Analog Electronics
Q.14) The voltage gains of an amplifier without Q.19) A feedback amplifier has an open loop
feedback and with negative feedback gain of -100. If 4% of the output is fed back in a
respectively are 100 and 20. The percentage of degenerative loop, what is the closed loop gain
negative feedback (𝛽) would be of the amplifier?
a) 4% b) 5% c) 20% d) 80% a) -33.3 b) -25 c) -20 d) +25
[IES – 2000 EC] [IES – 2008 EC]

Q.15) Assertion (A): In an amplifier with Q.20) An amplifier has gain A = 100 ∠ 1800,
negative feedback, the gain-stability is improved upper cut off frequency of 100 kHz and lower
by the factor 1 + 𝐴𝛽 where A is the magnitude cut off frequency of 1 kHz. A negative feedback
of gain and 𝛽 is the feedback factor. of β = 0.1 is added. Which one of the flowing is
Reason (R): The relation between gain with not correct?
feedback Af and gain without feedback A, is a) Gain becomes 100/11
𝐴 dA 1 𝑑𝐴 b) Lower cur off frequency becomes (100/11)
𝐴𝑓 = 1+𝐴𝛽 . Thus 𝐴 f = 1+𝐴𝛽 | 𝐴 |
𝑓 kHz
a) Both A and R are true and R is the correct c) Upper cut off frequency becomes 1.1 MHz.
explanation of A d) dB of feedback is 20 log10 11
b) Both A and R are true but R is NOT the [IES – 2008 EC]
correct explanation of A
c) A is true but R is false Q.21) Match List – I (Type of feedback) with
d) A is false but R is true List – II (Effect on Rin and Rout) and select the
[IES – 2001 EC] correct answer using the code given below the
lists
Q.16) In a BJT amplifier with the introduction of List – I
feedback, the input impedance is reduced, A. Voltage series
output impedance is increased, bandwidth is B. Voltage Shunt
increased and distortion is reduced. The C. Current Series
feedback is D. Current shunt
a) Voltage series b) Current series List – II
c) Voltage shunt d) Current shunt 1. Rin increases and Rout decreases
[IES – 2003 EC] 2. Rin and Rout decrease
3. Rin and Rout increase
Q.17) An amplifier has an open loop gain of 4. Rin decreases and Rout increases.
1000 ± 10. Negative feedback is provided such Codes
that the gain variation remains within 0.1%. A B C D
What is the amount of feedback 𝛽𝐹 ? a) 1 4 3 2
a) 1/10 b) 1/9 c) 9/100 d) 9/1000 b) 3 2 1 4
[IES – 2006 EC] c) 3 4 1 2
d) 1 2 3 4
Q.18) In a negative feedback amplifier, when is [IES – 2008 EC]
the input impedance increased?
a) If the signal sampled is a voltage Q.22) Consider the following:
b) If the signal sampled is a current 1. Oscillator
c) If the feedback signal is a voltage 2. Emitter follower
d) If the feedback signal is a current 3. Cascaded amplifier
[IES – 2007 EC] 4. Power amplifier
Which of these use feedback amplifiers?
a) 1 and 2 b) 1 and 3
c) 2 and 4 d) 3 and 4
[IES – 2009 EC]

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 Rathi classes Analog Electronics
Q.23) Which of the following describe the Q.27) In the ac equivalent circuit shown in the
correct properties of an emitter follower circuit? figure, if iin is the input current and RF is very
1. It is a voltage series feedback circuit. large, the type of feedback is
2. It is a current series feedback circuit.
3. Its voltage gain is less than unity.
4. Its output impedance is very low.
Select the correct answer from the codes given RD
RD
below: vout
a) 1,3 and 4 b) 2, 3 and 4 M2
c) 2 and 3 only d) 2 and 4 only
[IES – 2009 EC] M1

Q.24) The amplifier circuit shown in the figure is

RF
an example of small signal i in
+VCC input

RC (A) voltage-voltage feedback

RF (B) voltage-current feedback
Vout (C) current-voltage feedback
(D) current-current feedback
[GATE - 2014 EC]
Vin
Q.28) The feedback topology in the amplifier
circuit(the base bias circuit is not shown for
simplicity) in the figure is
RE CE Vcc

Rc Io
a) voltage series feedback
b) voltage shunt feedback Vo
c) current series feedback
d) current shunt feedback
[IES – 2011 EC] Rs
RE
Q.25) The second – harmonic component in the Vs
output of a transistor amplifier, without
feedback, is B2. The second harmonic
a) Voltage shunt feedback
component, with negative feedback B’2 is equal
b) Current series feedback
to (where A = Amplifier gain and β = feedback
c) Current shunt feedback
factor).
𝐵2 d) Voltage series feedback
a) 1+𝐴𝛽 b) 𝐵2 ( 1 + 𝐴𝛽) [GATE - 2014 EC-02]

𝐵2 𝐵 Q.29) The desirable characteristics of a

c) 𝛽
d) 𝐴𝛽2
transconductance amplifier are
[IES – 2012 EC] a) high input resistance and high output
resistance
Q.26) If a common emitter amplifier with an b) high input resistance and low output
emitter resistance Re has an overall resistance
transconductance gain of −1 mA/V, a voltage c) low input resistance and high output
gain of −4 and desensitivity of 50, then the resistance
value of the emitter resistance Re would be d) low input resistance and low output
resistance
a) 50 kΩ b) 0.98 kΩ [GATE - 2014 EC-03]
c) 50 MΩ d) 0.98 MΩ
[IES - 2000 EC]
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 Rathi classes Analog Electronics

Chapter – 8 a)
1
b)
1
Oscillators ( 2 6RC ) ( RC )
2 
1 1
c) d)
Q.1) The configuration of the figure is a
R1 R2
( 6 RC ) 3 ( 2RC )
[GATE – 2003 EC]

Q.4) The value of C required for sinusoidal

- oscillations of frequency 1kHz in the circuit of
Vo the figure is
+ R
1kΩ 2.1kΩ
C

R C
-
Vout
a) Precision integrator + C
b) Hartley oscillator
1kΩ
c) Butterworth high pass filter
d) Wien-bridge oscillator
C
[GATE – 2000 EC]
1kΩ
Q.2) The oscillator circuit shown in the figure is
-Vcc
1
a) F b) 2F
Lc 2
1
c) F d) 2 6F
L=10μH 2 6
Vo [GATE – 2004 EC]
Cc R1

Q.5) Assertion (A): Wien bridge oscillator is

C1=2pF C2=2pF
generally used as a variable audio frequency
oscillator.
R2
Ro Co Reason (R): by varying either the capacitor or
resistor value in one of the arms of the bridge,
the frequency of the Wien bridge oscillator can
a) Hartley oscillator with foscillation = 79.6MHz be varied.
b) Colpitts oscillator with foscillation = 50.3MHz a) Both A and R are true and R is the correct
c) Hartley oscillator with foscillation = 159.2MHz explanation of A
d) Colpitts oscillator with foscillation = 159.2MHz b) Both A and R are true but R is NOT the
[GATE – 2001 EC] correct explanation of A
c) A is true but R is false
Q.3) The oscillator circuit shown in the figure d) A is false but R is true
has an ideal inverting amplifier. Its frequency of [IES – 2003 EC]
oscillation (in Hz) is
Q.6) Match List-I (Name of the Oscillator) with
List-II (Characteristics) and select the correct
answer using the codes given below the lists:
List-I
A. Colpitts Oscillator
B. Phase Shift Oscillator
C. Tunnel diode Oscillator
D. Relaxation Oscillator

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 Rathi classes Analog Electronics
List-II Q.9) The circuit shown in the figure has an ideal
1. RC Oscillator opamp. The oscillation frequency ane the
2. LC Oscillator condition to sustain the oscillations,
3. Negative resistance Oscillator respectively, are
4. Sweep circuits
Codes:
A B C D
(a) 1 2 3 4
(b) 2 1 3 4
(c) 1 2 4 3
(d) 2 1 4 3
[IES – 2005 EC]
1 1
Q.7) Which one of the following oscillators is a) and R1 = R2 b) and R1 = 4R2
well suited for the generation of wide range CR CR
audio – frequency sine waves? 1 1
c) and R1 = R2 d) and R1 = 4R2
a) RC phase – shift oscillator 2CR 2CR
b) Wien – bridge oscillator [GATE-2015, EC-01, 2 MARKS]
c) Colpitts oscillator
d) Hartley oscillator
[IES – 2009 EC]

Q.8) In the Wien Bridge oscillator circuit shown

in figure, the bridge is balanced when
C1
R1
+VCC
+
-
R3
-VCC

C2 R2 R4

𝑅3 𝑅1 1
a) = ,𝜔 =
𝑅4 𝑅2 √𝑅1 𝐶1 𝑅2 𝐶2

𝑅2 𝐶2 1
b) = ,𝜔 =
𝑅1 𝐶1 𝑅1 𝐶1 𝑅2 𝐶2

𝑅3 𝑅1 𝐶2 1
c) = + ,𝜔 =
𝑅4 𝑅2 𝐶1 √𝑅1 𝐶1 𝑅2 𝐶2

𝑅3 𝑅1 𝐶2 1
d) = + ,𝜔 =
𝑅4 𝑅2 𝐶1 𝑅1 𝐶1 𝑅2 𝐶2

[GATE – 2014, EE-01]

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 Rathi classes Analog Electronics

Chapter – 9 Q.6) A class-B push-pull type amplifier with

transformer coupled load uses two transistor
Power Amplifiers rate 10W each. What is the maximum power
output one can obtain at the load from this
Q.1)Crossover distortion behavior is circuit?
characteristic of a) 40 W b) 50 W
a) Class A output stage c) 60 W d) 70 W
b) Class B output stage [IES –2002 EC]
c) Class AB output stage
d) Common-base output stage Q.7) Match List-I (Type of Amplifier) with List-II
[GATE –1999 EC] (Property) and select the correct answer using
the code given below the lists:
Q.2) The input signal Vin shown in the figure is a List-I
1 kHz square wave voltage that alternates A. Single ended class A
between +7V and -7V with a 50% duty cycle. B. Class AB push-pull
Both transistors have the same current gain. C. Class B push-pull
Which is large. The circuit delivers power to the D. Class C
load resistor RL. What is the efficiency of this List-II
circuit for the given input? Closest answer. 1. Medium efficiency with minimum
+10V distortion
2. High efficiency with crossover
distortion
3. Harmonic generator with highest
possible conversion efficiency
4. Poor conversion efficiency with
Vin
minimum distortion
RL = 10Ω Codes:
A B C D
a) 2 3 4 1
-10V b) 4 1 2 3
c) 2 1 4 3
a) 46% b) 55% c) 63% d) 92% d) 4 3 2 1
[GATE – 2007 EE] [IES –2005 EC]

Q.3) If a class C power amplifier has an input Q.8) Where does the operating point of a class-
signal with frequency of 200 kHz and the width B power amplifier lie?
of collector current pulses of 0.1 µs, then the a) At the middle of a.c. load line
duty cycle of the amplifier will be b) Approximately at collector cut-off on both the
a) 1 % b) 2 % c) 10 % d) 20 % d.c. and a.c. load lines
c) Inside the collector cut-off region on a.c. load
Q.4) Which one of the following power line
amplifiers has the maximum efficiency? d) At the middle point of d.c. load line
a) Class A b) Class B [IES –2006 EC]
c) Class AB d) Class C
[IES –2000 EC] Q.9) In a class – B push – pull operation, the
d.c. power drawn in 28 W. What is the power
Q.5) The power input to an amplifier is 2µW. the delivered by the amplifier at the ideal maximum
power gain of the amplifier is 40 dB. The output efficiency of power conversion?
power of the amplifier is a) 28 W b) 14 W
a) 80 µW b) 200 µW c) 22W d) 7 W
c) 20 mW d) 80 mW [IES –2007 EC]
[IES –2002 EC]

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 Rathi classes Analog Electronics
Q.10) What is the collector circuit efficiency of a c) 1, 3 and 4 d) 2, 3 and 4
class B push – pull amplifier if [IES –2009 EC]

Vm = peak load voltage, and Q.15) Consider the following:

1. Distortion
VCC = collector supply voltage 2. Gain
3. Bias stabilization
𝜋 𝑉𝑚 𝜋 𝑉𝑚 4. Sensitivity
a) 𝜂 = 4 𝑉𝑐𝑐
𝑥 100% 𝑏) 𝜂 = 2 𝑉𝑐𝑐
𝑥 100%
5. Frequency response
𝑉𝑐𝑐 𝜋 𝑉𝑐𝑐 − 𝑉𝑚
Which of these properties of the power amplifier
c) 𝑉𝑚
𝑥 100% 𝑑) 𝜂 = 2 𝑉𝑚
𝑥 100% one should concentrate upon while designing a
[IES –2008 EC] good power amplifier circuit?
a) 1, 2 and 3 b) 1, 3 and 5
Q.11) Assertion (A): Complementary c) 2, 3 and 4 d) 4 and 5
transistors are used for class-B push-pull power [IES –2009 EC]
amplifier.
Reason (R): We don’t need transformers if we Q.16) Using transistors,
use complementary transistors in class B push 1. Class – A power amplifier has a minimum
– pull power amplifiers. efficiency of 50%.
a) Both A and R are individually true and R is 2. Class – B push – pull power amplifier gives
the correct explanation of A rise to crossover distortion.
b) Both A and R are individually true but R is 3. Class AB push – pull power amplifier has
not the correct explanation of A higher efficiency than Class – B push pull
c) A is true but R is false amplifier
d) A is false but R is true 4. Class – C power amplifier is generally used
[IES –2008 EC] with tuned load for RF amplification.

Q.12) In a class A amplifier, VCE(max) = 15 V and Which of these statements are correct?
VCE(min) = 1 V. The conversion efficiency for a a) 1,2,3 and 4 b) 2 and 4 only
series fed load will be equal to c) 3 and 4 only d) 1 and 2 only
a) 25% b) 23.33% [IES –2011 EC]
c) 12.5% d) 11.67%
[IES –2008 EC] Q.17) Direction
The following item consists of two statements,
Q.13) Which one of the following statements is one labelled as ‘Statement (I)’ and the other as
not correct with regard to power amplifiers? ‘Statement (II)’. You are to examine these two
a) The collector current is large statements carefully and select the answers to
b) They are used as the front end of these items using the code given below:
multi – stage amplifiers
c) They are used near the end of the Statement (I): In a transistor designed to be
multi – stage amplifiers used for power amplification, the collector size
1 is largest relative to the emitter and base.
d) They have a high power rating (> 2 𝑊)
[IES –2009 EC] Statement (II): The collector is connected to the
body of the transistor and hence to a heat sink
Q.14) Consider the following statements for heat dissipation to be effective.
regarding the class-B power amplifiers
(Complementary symmetry type) : a) Both Statement (I) and Statement (II) are
1. The efficiency of the amplifier is higher than individually true and Statement (II) is the
that of class-A amplifier. correct explanation of Statement (I).
2. The power output is low. b) Both Statement(I) and Statement(II) are
3. Cross over distortion is present. individually true but Statement(II) is not the
4. The standby power dissipation is absent. correct explanation of Statement (I).
Which of the above statements are correct?
a) 1, 2 and 3 b) 1, 2 and 4
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 Rathi classes Analog Electronics
c) Statement(I) is true but Statement (II) is
false.
d) Statement (I) is false but Statement (II) is
true.
[IES –2012 EC]

Q.18) An output signal of a power amplifier has

amplitudes of 2.5 V fundamental, 0.25 V second
harmonic. The total percentage harmonic
distortion of the signal is
a) 12.8 % b) 10.8%
c) 6.4 % d) 1.4 %
[IES –2012 EC]

Q.19) A BJT is biased with a power supply of 12

V. For minimum heat dissipation, the drop
across the transistor will be
a) 6 V b) 9 V
c) 12 V d) > 9V but < 12 V

[IES – 2012 EC]

Q.20) Thermal runaway will take place if the

quiescent point is such that
a) VCE > ½ VCC b) VCE < VCC
c) VCE < 2VCC d) VCE < ½ VCC

[IES – 1999 EC]

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 Rathi classes Analog Electronics

Chapter – 10 Q.4) The most commonly used amplifier in

sample and hold circuit is
Operational Amplifier a) a unity gain inverting amplifier
(Op – Amp) b) a unity gain non-inverting amplifier
c) an inverting amplifier with a gain of 10
Q.1) The first dominant pole encountered in the d) an inverting amplifier with a gain of 100
frequency response of a compensated op-amp [GATE – 2000 EC]
is approximately at
Q.5) If the op-amp in the figure has an input
a) 5 Hz b) 10kHz c) 1 MHz d) 100 MHz offset voltage of 5mV and an open-loop voltage
[GATE – 1999 EC] gain of 10,000, then vo will be
+15V

Q.2) If the op-amp in the figure, is ideal, then Vo

-
is
Vo
+

-15V

a) 0V b) 5mV
c) +15V or – 15V d) +50V or – 50V
[GATE – 2000 EC]

Q.6) The ideal OP-AMP has the following

characteristics.
a) Ri = ∞, A = ∞, R0 = 0
b) Ri = 0, A = ∞, R0 = 0
a) zero b) (V1 – V2) sinωt c) Ri = ∞, A = ∞, R0 = ∞
c) – (V1 + V2) sin𝜔t d) (V1 – V2) sin𝜔t d) Ri = 0, A = ∞, R0 = ∞
[GATE – 2000 EC] [GATE – 2001 EC]

Q.3) Assume that the op-amp of the figure is Q.7) The inverting OP-AMP shown in the figure
ideal. If vi is a triangular wave, then vo will be has an open-loop gain of 100. The closed-loop
V
gain V0 is
R s
R2 = 10K
C
Vi -
Vo R1 = 1K
+
-
+
Vs Vi
- + Vo

a) square wave b) triangular wave

c) parabolic wave d) sine wave
[GATE – 2000 EC]
a) – 8 b) – 9 c) – 10 d) – 11
[GATE – 2001 EC]

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 Rathi classes Analog Electronics
Q.8) In the figure assume the OP-AMPs to be
ideal. The output V0 of the circuit is: a) 1 V b) 6 V c) 14 V d) 17 V
[GATE – 2003 EC]

Vs Q.13) An ideal op-amp is an ideal

- a) voltage controlled current source
Vs = 10cos(100t) -
+ b) voltage controlled voltage source
+ Vo
c) current controlled current source
d) current controlled voltage source
[GATE – 2004 EC]

t Q.14) In the op-amp circuit given in the figure,

a) 10cos(100t) b)10∫0 cos(100𝜏)d𝜏
t d
the load current iL is
c) 10-4∫0 cos d) 10-4dtcos(100t) R1 R1

[GATE – 2001 EC] Vs

-
Q.9) A 741-type has a gain-band width product
of 1MHz. A non-inverting amplifier using this +
opamp and having a voltage gain of 20dB will R2

exhibit a – 3dB bandwidth of

R2
a) 50 KHz b) 100 KHz
1000 1000 iL RL
c) 17 KHz d) 7.07 KHz
[GATE – 2002 EC] −Vs V V V
a) R2
b) Rs c) - Rs d) Rs
2 L 1

Q.10) An amplifier using an opamp with a slew- [GATE – 2004 EC]

rate SR=1 V/μ sec has ‘a gain of 40 dB. If this
amplifier has to faithfully amplify sinusoidal Q.15) The input resistance Ri of the amplifier
signals from dc to 20 KHz without introducting shown in the figure is
any slew-rate induced distortion, then the input 30K
signal level must not exceed.
a) 795 mV b) 395 mV
10K
c) 79.5 mV d) 39.5 mV
[GATE – 2002 EC] -

+
Q.11) If the differential voltage gain and the
common mode voltage gain of a differential Ideal operational amplifier
amplifier are 48 dB and 2 dB respectively, then
its common mode rejection ratio is Ri
a) 23 dB b) 25 dB c) 46 dB d) 50 dB 30
a) kΩ b) 10kΩ
[GATE – 2003 EC] 4
c) 40kΩ d) infinite
Q.12) If the op-amp in the figure is idea, the [GATE – 2005 EC]
output voltage Vout will be equal to
5KΩ
1KΩ
2V
-
Vout
1KΩ
3V +

8KΩ

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 Rathi classes Analog Electronics
Q.16) The voltage e0 indicated in the figure has a) – 2 V b) – 1 V c) – 0.5 V d) 0.5 V
been measured by an ideal voltmeter. Which of [GATE – 2006 EC]
the following can be calculated?
1M Q.19) In the OP-Amp circuit shown, assume
that the current follows the equation I = Is exp
(V/VT). For Vi = 2 V, V0 = V01, and for Vi = 4 V,
V0 = V02. The relationship between V01 and V02
e0 is
-

1M Vi
2kΩ -
Vo
a) Bias current of the inverting input only +
b) Bias current of the inverting and non-
inverting inputs only
c) Input offset current only
d) Both the bias currents and the input offset
current a) V02 = √2 V01
[GATE – 2005 EC] b) V02 = e2 V01
c) V02 = V01 In 2
d) V01 – V02 = VT In 2
Q.17) The OP-amp circuit shown in the figure is [GATE – 2006 EC]
a filter. The type of filter and its cut-off
frequency are respectively Statement for linked Answer Questions
20 & 21:
10 k Ω Consider the Op-Amp circuit shown in the
figure.
10 k Ω R1
- R1

-
+ Vi
Vi Vo
1 µF +
1K Ω R
C

a) high pass, 1000 rad/sec.

b) low pass, 1000 rad/sec. Q.20) The transfer function V0(s)/Vi(s) is
c) high pass, 10000 rad/sec. 1−sRC 1+sRC 1 1
d) low pass,10000 rad/sec. a) 1+sRC b) 1−sRC c) 1−sRC d) 1+sRC
[GATE – 2007 EC]
Q.18) For the Op-Amp circuit shown in the
figure, V0 is Q.21) If Vi = V1 sin(ωt) and Vo = V2 sin (ωt + ϕ),
then the minimum and maximum values of ϕ (in
radians) are respectively)
2kΩ
a) –π/2 and π/2 b) 0 and π/2
1kΩ
c) –π and 0 d) –π/2 and 0
- [GATE – 2007 EC]
1V Vo
+

1kΩ
1kΩ

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 Rathi classes Analog Electronics
Q.22) Consider the following circuit using an
ideal OP – Amp. The I-V characteristics of the 𝑅
a) − 𝑅2 𝑏) − 𝑅3
𝑅

diode is described by the relation 1

𝑅2 ||𝑅3
1
𝑅2 ||𝑅3
V c) − ( 𝑅1
) d) − ( 𝑅1
)
I = I0 (e VT
− 1) where VT = 25 mV, I0 =
[GATE – 2010 EC]
1µA and V is the voltage across the diode (taken
as positive for forward bias). Q.25) The circuit below implement a filter
between the input current ii and output voltage
V0. Assume that the op – amp is ideal. The filter
implemented is a
L1

R1

Ii
-

+ +
For an input voltage Vi = -1V, the output voltage V0
V0 is -
a) 0 V b) 0.1 V
c) 0.7 V d) 1.1 V
[GATE – 2008 EC] a) low pass filter b) band pass filter
c) band stop filter d) high pass filter
Q.23) The Op – Amp circuit shown below [GATE – 2011 EC]
represents a
C
Q.26) The circuit shown is a

R2

Vi –
R1 L V0
+

1
a) High pass filter b) Low pass filter a) Low pass filter with f3dB = (R rad/s
1 + R2 )C
c) Band pass filter d) Band reject filter b) High pass filter with
1
f3dB = R C rad/s
[GATE – 2008 EC] 1
1
c) Low pass filter with f3dB = R C rad/s
Q.24) Assuming the OP – AMP to be ideal, the 1
1
voltage gain of the amplifier shown below is d) High pass filter with f3dB = (R1 + R2 )C
rad/s
R1 [GATE – 2012 EC]
-
V0 Q.27) Assertion (A): An operational amplifier
R2 + can amplify very low frequency including d.c.
signals.
Vi Reason (R): op-amp uses very large coupling
capacitor for cascading the various stages.
R3 a) Both A and R are ture and R is the correct
explanation of A

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 Rathi classes Analog Electronics
b) Both A and R are true but R is NOT the 10KΩ 10KΩ
correct explanation of A
c) A is true but R is false 1KΩ
d) A is false but R is true
[IES – 2002, EC]
-
Vin 1KΩ Vout
Q.28) In the circuit shown below the op – amps +
are ideal. Then Vout in Volts is
1 kΩ 1 kΩ

-2V +15V
-15V a) -1 b) -20 c) -100 d) -120
- [GATE – 2003 EE]
+
+ Vout
- Q.31) Consider the inverting amplifier, using an
-15V ideal operational amplifier shown in the figure.
1 kΩ -15V The designer wishes to realize the input
+1V 1 kΩ
resistance seen by the small-signal source to
1 kΩ be as large as possible, while keeping the
voltage gain between -10 and -25. The upper
limit on RF is 1 MΩ. The value of R1 should be.
a) 4 b) 6 c) 8 d) 10
RF
[GATE – 2013 EC/EE]

Q.29) For the circuit of figure with an ideal

operational amplifier, the maximum phase shift
of the output Vout with reference to the input Vin -
Vin R1 + Vout
is
R1

R1
- a) Infinity b) 1kΩ c) 100kΩ d) 40kΩ
+ [GATE – 2005 EE]
Vin R Vout
C Q.32) The circuit shown in the figure is

a) 00 b) − 900 c) + 900 d) ± 1800

[GATE – 2003 EE]

Q.30) Assuming the operational amplifier to be

ideal, the gain Vout/Vin for the circuit shown in
figure is

𝑟𝑉
a) A voltage source with voltage
𝑅1 ||𝑅2

𝑟||𝑅2
b) A voltage source with voltage 𝑅1
𝑉

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 Rathi classes Analog Electronics
𝑟||𝑅2 𝑉
c) A current source with current 𝑅 .
1 +𝑅2 𝑟 a) -5 V b) -3 V c) +3 V d) +5 V
[GATE – 2004 IE]
𝑅2 𝑉
d) A current source with current 𝑅 .𝑟
1 +𝑅2 𝑉
Q.36) The gain ( 0 ) of the amplifier circuit
[GATE – 2007 EE] 𝑉𝑖
shown in figure is
Q.33) The output of an opamp whose input is a
2.5 MHz square wave is shown in figure. The
slew rate of the opamp is

4V

-4 V
0.4 µs
a) 0.8 V/µs b) 8.0 V/µs 3𝑅
a) 8 b) 4 c) -4 d) 𝑅𝐿
c) 20.0 V/µs d) 40.0 V/µs
[GATE – 2004 IE]
[GATE – 2003 IE]
Q.37) The output voltage Vo in the circuit in
Q.34) The opamp and the 1 mA current source
figure is
in the circuit of figure are ideal. The output of
the op-amp is V

R1 R1 R2

- -
Vo
+ R(1+ R +

𝑅2 𝑅
a) 𝑉𝛿 b) 𝑅2 𝑉𝛿
a) -1.5 mA b) -1.5 V 𝑅 1
𝑅2 2𝑅
c) -7.5 V d) +1.5 V c) 𝑉 𝑑) 𝑅(1+𝛿) 𝑉
𝑅1 𝛿
[GATE – 2003 IE]
[GATE – 2004 IE]
Q.35) The value of Vo in the circuit, shown in
Q.38) V1 and V2 are the input voltages of an
figure is
instrumentation amplifier. The output of the
instrumentation amplifier is found to be 100 (V1-
V2) +10 -4 (V1 + V2). the gain and the common
mode rejection ratio (CMRR) of the
instrumentation amplifier respectively are
a) (50, 60 dB) b) (50, 120 dB)
c) (100, 60 dB) d) (100, 120 dB)
[GATE – 2004 IE]

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49
 Rathi classes Analog Electronics
Q.39) The circuit in figure is a Q.41) If the value of the resistance R in the
following figure is increased by 50%, then
voltage gain of the amplifier shown in the figure
will change by

a) Band – pass filter with

1
Lower cut – off 𝜔𝐿 = 𝑅 𝐶 𝑎𝑛𝑑
1 1
1
Higher cut – off 𝜔𝐻 =
𝑅2 𝐶2
b) Band – reject filter with a) 50% b) 5%
1 c) -50% d) Negligible amount
Lower cut – off 𝜔𝐿 = 𝑎𝑛𝑑
𝑅1 𝐶1
1
[GATE – 2006 IE]
Higher cut – off 𝜔𝐻 = 𝑅 𝐶
2 2
c) Band – pass filter with Q.42) In the circuit shown in the following figure,
1 the opamp has input bias current Ib<10nA, and
Lower cut – off 𝜔𝐿 = 𝑅 𝐶 𝑎𝑛𝑑
2 2 input offset voltage Vi0<1 mV. The maximum dc
1
Higher cut – off 𝜔𝐻 = error in the output voltage is
𝑅1 𝐶1
d) Band – reject filter with
Lower cut – off 𝜔𝐿 =
1
𝑎𝑛𝑑 100kΩ
𝑅2 𝐶2
1
Higher cut – off 𝜔𝐻 = 𝑅 𝐶 100kΩ
1 1
-
[GATE – 2004 IE]
Vo
+
Q.40) In the circuit shown in the given figure the
VS
input voltage Vin(t) is given by 2 sin(100 πt). For ~
RL in the range 0.5 kΩ to 1.5 kΩ, the current
through RL is

a) 1.0 mV b) 2.0 mV
c) 2.5 mV d) 3.0 mV
[GATE – 2006 IE]

Q.43) The potential difference between the

input terminals of an opamp may be treated to
be nearly zero, if
a) The two supply voltages are balanced
b) The output voltage is not saturated
c) The opamp is used in a circuit having
negative feedback
d) There is a dc bias path between each of the
terminals and the circuit ground
a) +2 sin (100πt) mA [GATE – 2006 IE]
b) -2 sin (100πt) mA
c) +0.5 sin (100 πt) mA
d) 1.5 sin(100πt) Ma
[GATE – 2005 IE]

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50
 Rathi classes Analog Electronics
Q.44) 20kΩ

V1 100 kΩ
1 2
R1
1’ 2’ -
V2 Vo
+

1 kΩ R2
Vi -
Let V1 = V2 = 0 and R1 = 20 kΩ. Assume that
+ Vo the op – amp is ideal except for a non-zero
input bias current. What is the value of R2 for
the output voltage of the op-amp to be zero?
a) 2.2 kΩ b) 9.1 kΩ
Consider the linear circuit with and ideal op – c) 20 kΩ d) 100 kΩ
amp shown in the figure shown above:
[GATE – 2007 IE]
The Z – parameters of the two port feedback
network are:
Q.47) The op-amp circuit shown below is that of
Z11 = Z22 = 11 kΩ, and
a
Z12 = Z21 = 1 kΩ
The gain of the amplifier is
Vin +
a) +110 b) +11 c) -1 d) -120 1 µF VO
[GATE – 2007 IE] -

Q.45) The figure shows a single op – amp 1 kΩ

differential amplifier circuit.
100 kΩ 1kΩ 1kΩ

500Ω 10 kΩ
-
+ 50Ω 10 Ω Vo a) Low-pass filter with a maximum gain of 1
10mV +
- +
b) Low –pass filter with a maximum gain of 2
20 mV 100 kΩ c) High- pass filter with a maximum gain of 1
d) High- pass filter with a maximum gain of 2
[GATE – 2008 IE]
Which one of the following statements about the Q.48) For the op- amp circuit shown below, Vo
output is correct? is approximately equal to
a) Vo ≤ 95 𝑚𝑉
b) 95 mV < Vo ≤ 98 𝑚𝑉
c) 98 mV < Vo ≤ 101 𝑚𝑉
d) Vo > 101 𝑚𝑉
[GATE – 2007 IE]

Q.46) Consider the op – amp circuit shown in

the figure below:

a) 10 V b) -5 V c) +5 V d) +10 V
[GATE – 2008 IE]

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51
 Rathi classes Analog Electronics
Q.49) In the circuit shown, the Zener diode has a) Remain constant at +1
ideal characteristics and a breakdown voltage b) Remain constant at -1
of 3.2 V. the output voltage Vo for an input c) Vary as (–Rf / 10,000)
voltage V1 = +1 V is closest to d) Vary as (1+ Rf/10,000)
[GATE – 2010 IE]
10kΩ
Q.52) An active filter is shown in the adjoining
figure. The dc gain and the 3 dB cut-off
frequency of the filter respectively, are nearly
1kΩ 10 kΩ
Vi - C1
Vo
R2
+
R1
Vi -
VO
+

a) -10 V b) -6.6 V c) -5 V d) -3.2 V

[GATE – 2009 IE] R1 = 15.9kΩ, R2 = 159kΩ, C1 = 1.0 nF

Q.50) The input resistance of the circuit shown a) 40 dB, 3.14 kHz b) 40 dB, 1.00 kHz
in the figure, assuming an ideal op-amp is c) 20 dB, 6.28 kHz d) 20 dB, 1.00 kHz
[GATE – 2010 IE]
2R
Common Data Questions (53 and 54) :
R 3R A differential amplifier is constructed using an
ideal op-amp as shown in the adjoining figure.
Vi The values of R1 and R2 and 47kΩ and 470kΩ
-
respectively.
Vo
+ R2
R1
V1 -
Vo
V2 +
R1
R2
𝑅 2𝑅 4𝑅
a) 3
b) 3
c) R d) 3
[GATE – 2009 IE]

Q.51) In the ideal op-amp circuit given in the Q.53) The input impedances seen looking into
adjoining figure, the value of Rf is varied from the terminals V1 and V2, with respect to ground,
1kΩ to 100kΩ. The gain G = (Vo / Vi) respectively are
a) 47 kΩ and 43 kΩ b) 47 kΩ and 47 kΩ
c) 47 kΩ and 517 kΩ d) 517 kΩ and 517 kΩ
Rf [GATE – 2010 IE]

10kΩ Q.54) V1 and V2 are connected to voltage

-
Vo sources having an open circuit output of +1 V
+ + each and internal resistances of 13kΩ and 3kΩ
+
Vi 10 kΩ Vo respectively. The output voltage VO is
a) 0V b) 0.15 V c) 1.5 V d) 10 V
[GATE – 2010 IE]

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52
 Rathi classes Analog Electronics
Q.55) The output voltage V0 of the given circuit Q.58) Assertion (A): In an op-amp circuit when
one input terminal of the op-amp is grounded,
the other terminal becomes a virtual ground.
Reason (R): Input impedance of the op-amp is
high.
a) Both A and R are true and R is the correct
explanation of A
b) Both A and R are true but R is NOT the
correct explanation of A
c) A is true but R is false
d) A is false but R is true
[IES – 2001 EC]
a) −100 𝑉 b) −100 𝑚𝑉
c) 10 𝑉 d) −10 𝑚𝑉 Q.59) In a 741 op-amp, there is 20 dB/decade
[IES – 1999 EC] fall-off staring at a relatively low frequency. this
is due to the
a) applied load
Q.56) The voltage gain versus frequency curve
of an Op-Amp is shown in the given figure b) internal compensation
c) impedance of the source
Voltage
d) power dissipation in the chip
gain 80 dB
[IES – 2001 EC]
+ 20 dB/decade
Q.60) Assertion (A): Operational amplifiers
should have a high slew rate for good transient
frequency response.
20 Hz Reason (R): Slew rate is the maximum rate of
The gain-bandwidth product of the Op-Amp is change of the output voltage of the operation
amplifier when a large amplitude step is applied
a) 200 Hz b) 200 MHz to its input.
c) 200 kHz d) 2 MHz a) Both A and R are true and R is the correct
[IES – 1999 EC] explanation of A
b) Both A and R are true but R is NOT the
Q.57) In the circuit shown in the given figure, V0 correct explanation of A
is given by c) A is true but R is false
d) A is false but R is true
[IES – 2002 EC]

Q.61) Assertion (A): An operational amplifier

should have a low input offset current.
+ Reason (R): Input impedance of op-amp should
be very high.
a) Both A and R are true and R is the correct
explanation of A
b) Both A and R are true but R is NOT the
a) sin(𝑡 − 𝜋/4) b) sin(𝑡 + 𝜋/4) correct explanation of A
c) A is true but R is false
c) sin 𝑡 d) cos 𝑡
d) A is false but R is true
[IES – 2001 EC]
[IES – 2002 EC]

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53
 Rathi classes Analog Electronics
Q.62) Assertion (A): An operational amplifier Q.65) The stage market X in the shown below
can amplify very low frequency including d.c. architecture of a two-stage op-amp is
signals.
Reason (R): op-amp uses very large coupling Differential Gain Emitter
capacitor for cascading the various stages. Input X Output
amplifier stage following
a) Both A and R are true and R is the correct
explanation of A
b) Both A and R are true but R is NOT the
correct explanation of A a) Direct coupled amplifier
c) A is true but R is false b) Buffer amplifier
d) A is false but R is true c) Level shifter
[IES – 2002 EC] d) Blocking oscillator
[IES – 2003 EC]

Q.66) Consider the following Op-Amp circuit:

Q.63) In a circuit, if the open loop gain is 106
and output voltage is 10 volt, the differential
voltage should be
a) 10 µV b) 0.1 V
c) 100 µV d) 1 µV

[IES – 2002 EC]

Q.64) A non-inverting op-amp is shown below What is the output voltage V0 in the above Op-
(assume ideal op-amp) Amp circuit?
a) +10 𝑉 b) −10 𝑉
c) +11 𝑉 d) −11 𝑉
[IES – 2004 EC]

Q.67) Consider the following circuit:

The output voltage V0 for an input 𝑉𝑖 =

[2 + sin(100𝑡)]𝑉

a) 3/2 sin(100𝑡)
b) 3 sin(100𝑡)
c) 2 sin(100𝑡)
d) 3 sin(100𝑡) + 1/2 What is the value of R4 in the above circuit if the
[IES – 2002 EC] voltage V- and V+ are to be amplified by the
same amplification factor?
a) 7 kΩ b) 22 kΩ
c) 33 kΩ d) 35 kΩ
[IES – 2004 EC]

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54
 Rathi classes Analog Electronics
Q.68) What is the load current IL in the circuit
below?

a) -11 V b) 6 V c) 11 V d) -6 V
[IES – 2007 EC]
a) −5 𝑚𝐴 b) −10 𝑚𝐴
c) +25 𝑚𝐴 d) +50 𝑚𝐴 Q.73) What is the output voltage V0 of the below
[IES – 2004 EC] circuit?
100 kΩ
Q.69) For a given o-amp, CMMR = 105 and 470 kΩ
22 kΩ
differential gain = 105. What is the common
-
mode gain of the op-amp? 10 kΩ -
a) 1010 b) 2×105 c) 105 d) 1 + 47 kΩ -
2.2 kΩ
[IES – 2005 EC] +
V0
+
1 mV
Q.70) In the circuit shown above, what is the
value of transfer function𝐼𝑜 /𝐼𝑖 ? a) -1.1 V b) +1.1 V
c) 1.0 V d) 10 V
[IES – 2007 EC]

Q.74) Which of the following are the non –

linear applications of OP amp?
1. Current – to – voltage converter
2. Comparator
3. Peak detector
4. Limiter
𝑍 𝑍
a) – 𝑍2 b) – 𝑍1 Select the correct answer from the codes given
1 2
𝑍 𝑍 below:
c) 1 + (𝑍2 ) d) 1 + (𝑍1 ) a) 1, 2 and 3 b) 2, 3 and 4
1 2
[IES – 2006 EC] c) 1, 3 and 4 d) 1, 2 and 4
[IES – 2008 EC]
Q.71) A differential amplifier has input, V1 =
1050 µV and V2 = 950 µV with CMRR = 1000. Q.75) The output of the below OP – amp circuit
What is the error in the differential output? is
a) 10% b) 1% 3R
c) 0.1% d) 0.01%
[IES – 2006 EC] R
-
Q.72) What is the output voltage V0 of the below
circuit? R Vx + Vout
-4V
R

(4 – 2 cos ωt) volts

a) -0.75 volts b) –4 cos ωt volts

c) -8 cos vots d) 16 volts
[IES – 2010 EC]
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55
 Rathi classes Analog Electronics
Q.76) In the circuit shown, the need of the (d) Ri = 50 kΩ, Rf = 200 kΩ
resistor RF is [GATE – 2014, IN]

RF Q.79) Assuming an ideal op-amp in linear range

of operation, the magnitude of the transfer
V0
impedance in MΩ of the current to voltage
i
Ri converter shown in the figure is ___________.
-
Vi
+ Vo

Ro

a) To increase the overall gain

b) To stabilize the circuit
c) To increase input impedance
d) To prevent saturation
[IES – 2012 EC] [GATE – 2014, IN]

Q.77) For the op-amp shown in the figure, the Q.80) In the low-pass filter shown in the figure,
bias currents are Ib1= 450 nA and Ib2=350 nA. for a cut-off frequency of 5 kHz , the value of R2
The values (in kΩ) is _____________.
of the input bias current (IB) and the input offset
current (If) are: R2

C
1 kΩ 10 nF
Vi -
R1 Vo
+
(a) IB = 800 nA, If =50 nA
(b) IB = 800 nA, If =100nA
(c) IB = 400 nA, If =50nA
(d) IB = 400 nA, If =100nA
[GATE - 2014 EC]
[GATE – 2014, IN]
Q.78) The amplifier in the figure has gain of −10 Q.81) In the circuit shown, the op-amp has finite
and input resistance of 50 kΩ. The values of Ri input impedance, infinite voltage gain and zero
and Rf are: input offset voltage. The output voltage Vout is
R2

R1 I1
-
Vout
+
I2

a) –I2(R1 + R2) b) I2R2

(a) Ri = 500 kΩ, Rf = 50 kΩ c) I1R2 d) –I1(R1 + R2)
(b) Ri = 50 kΩ, Rf = 500 kΩ [GATE – 2014, EC-01]
(c) Ri = 5 kΩ, Rf = 10 kΩ

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56
 Rathi classes Analog Electronics
Q.82) Assuming that the Op-amp in the circuit c)
shown is ideal, V0 is given by

3R
π/2
V1 - π/4
R Vo 0 10 2 0
2
10 10 10
3

+ 1 10
10 3
ω 1 ω
2R V2 R -10 -π/4
-20 -π/2
-30
5 5
a) 𝑉1 − 3𝑉2 b) 2V1 - 𝑉2
2 2
3 7 11
c) − 𝑉1 + 𝑉2 d) −3𝑉1 + 𝑉2
2 2 2
[GATE – 2014, EC-03] d)

Q.83) In the figure shown, assume the op-amp 

to be ideal. Which of the alternatives gives the π/2
π/4
correct Bode plots for the transfer function 0 0 10
𝑉0 (𝜔)
𝑉 (𝜔)
? -10
1 10 10 2
10 3 ω
-π/4
1 2
10 10
3 ω
𝑖

1 kΩ +VCC -20 -π/2

-30
Vi +
VO
1µF -
-VCC [GATE – 2014, EE-01]

Q.84) In the circuit shown, assume that the

Rf opamp is ideal. The bridge output voltage V0 (in
a) mV) for  = 0.05 is _______.

3
0 0 10 10 2 10
1 10
10 2 ω 1 ω
-10 -π/4
3
10
-20 -π/2
-30

[GATE-2015, EC-01, 2 MARKS]

b)
Q.85) In the circuit shown V0 = V0A for switch
SW in position A and V0 = V0B for SW in position
 B. Assume that the opamp is ideal. The value of
π/2
V0B
3 π/4 is ______.
0 10 0 10 3 V0A
1 10
10 2 ω 1 2 ω
-π/4 10 10
-10
-20 -π/2
-30

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57
 Rathi classes Analog Electronics
Q.89) In the circuit shown, assume that the
opamp is ideal. If the gain (v0/vm) is –12, the
value of R (in k ) is __________.

[GATE-2015, EC-02, 1 MARK]

Q.86) In the bistable circuit shown, the ideal

opamp has saturation levels of  5 V. The value [GATE-2015, EC-03, 2 MARKS]
of R1 (in k ) that gives a hysteresis width of Q.90) Consider the circuit shown in the figure.
500 mV is______.
In this circuit R = 1 k , and C = 1 F. The input
voltage is sinusoidal with a frequency of 50 Hz,
represented as a phasor with magnitude Vi and
phase angle 0 radian as shown in the figure.
The output voltage is represented as a phasor
with magnitude V0 and phase angle  radian.
What is the value of the output phase angle 
(in radian) relative to the phase angle of the
input voltage?
[GATE-2015, EC-02, 1 MARK]

Q.87) Assuming that the opamp in the circuit

shown below is ideal, the output voltage V0 (in
volts) is ________.

a) 0 b) 
 
c) d) −
2 2
[GATE-2015, EE-01, 1 MARK]

Q.91) The op-amp shown in the figure has a

finite gain A = 1000 and an infinite input
resistance. A step-voltage Vi = 1 mV is applied
[GATE-2015, EC-02, 2 MARKS] at the input at time t = 0 as shown. Assuming
that the operational amplifier is not saturated,
Q.88) In the circuit shown using an ideal the time constant (in millisecond) of the output
opamp, the 3-dB cut-off frequency (in Hz) is voltage V0 is
________.

[GATE-2015, EC-03, 1 MARKS]

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58
 Rathi classes Analog Electronics
a) 1001 Q.94) In the figure shown, RT represents a
b) 101 resistance temperature device (RTD), whose
c) 11 characteristic is given by RT = R0 (1 + T ) ,
d) 1
[GATE-2015, EE-01, 2 MARKS] where R0 R0 = 100 ,  = 0.0039 C −1 and T
denote the temperature in °C. Assuming the
Q.92) The operational amplifier shown in the opamp to be idea, the value of V0 in volts when
figure is ideal. The input voltage (in Volts) is T = 100 °C, is ________ V.
Vi = 2 sin ( 2  2000t ). The amplitude of the
output voltage V0 (in Volt) is _______.

[GATE-2015, IN, 2 MARKS]

[GATE-2015, EE-02, 1 MARK] Q.95) An op-amp has opamp has ideal

characteristics except that its open loop gain is
Q.93) The filter F1 and F2 having given by the expression Av(s) = 104/(1 + 10–3 s).
characteristics as shown in Figures (a) and (b) This op-amp is used is used circuit shown in the
are connected as shown in Figure (c). figure. The 3-dB bandwidth of the circuit, in
1. rad/s/ is

2.

a) 102 b) 103
c) 104 d) 106
[GATE-2015, IN, 2 MARKS]

3.

The cut-off frequencies of F1 and F2 are f1 and f2

respectively. If f1 < f2, the resultant circuit
exhibits the characteristic of a
a) Band-pass filter b) Band-stop filter
c) All pass filter d) High-Q filter
[GATE-2015, EE-02, 1 MARK]
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59
 Rathi classes Analog Electronics

Chapter – 11 a) b)
6 6
Waveform generators
V V

Q.1) If the input to the ideal comparator shown t3 t6 t3 t6

0 0
in the figure is a sinusoidal signal of 8V (peak to t
-3 -3
peak) without any DC component, then the
output of the comparator has a duty cycle of c) d)
6
Input + 6
Output
V
V
Vref =2V -
t6
0 t2 t4 t6
0 t2 t4 t
a) 1/2 b) 1/3 c) 1/6 d)1/12 t
-3 -3
[GATE - 2003 EC]
[GATE - 2009 EE]
Q.2) An ideal opamp circuit and its input
waveform are shown in the figures. The output
Q.3) Pulses of defined width can be obtained
waveform of this circuit will be
from irregular shaped pulses:
a) When it is given as input to a monostable
3 multivibrator
2 b) When it is given as triggering signal to a
1 t4 t5 t6
V 0 t1 t2 t3 t bistable multivibrator
-1 c) When it is used as input to a Schmitt trigger
-2 d) When it is used as input to a pulse
-3
transformer
[IES - 2005 EC]
6V Q.4) In the circuit of the figure , Vo is
1 kΩ - +15V
Vin
+ Vout
-
2 kΩ Vo
-3 V +1V +
R
-15V

1kΩ

R
a) – 1V b) 2V c) +1V d) +15V
[GATE – 2000 EC]

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60
 Rathi classes Analog Electronics
Q.5) Figure (a) shows a Schmitt trigger circuit a) -12 V and +12 V b) -7.5 and +7.5 V
and figure (b) the corresponding hysteresis c) -5 V and + 5 V d) 0 V and 5 V
characteristics. The values of VTL and V TH are [GATE - 2008 EC]

+10 Ω Q.7) A relaxation oscillator is made using

V OPAMP as shown in figure. The supply
- voltages of the OPAMP are ± 12V. the voltage
Vo waveform at point P will be
+
5kΩ -10 V
R1
10 k Ω
+
Vi
R2
(a) -
C
+10 V
+ 2kΩ

P 10kΩ

10kΩ
-10 V

V TL VTH
a) b)

(b) 5 10
a) VTL = -3.75 V, VTH = +3.75 V
-10 -5
b) VTL = -1 V, VTH = +5 V
c) VTL = -5 V, VTH = +1 V c) d)
d) VTL = -5 V, VTH = +5 V
[GATE – 2004 IE] 5 10

Q.6) Consider the Schmidt trigger circuit shown -10 -5

below. [GATE – 2006 EE]

+15 V Q.8) In the op- amp circuit shown below the

10 kΩ input voltage Vin gradually increased from -10 V
to +10 V. assuming that the output voltage Vout
saturates at -10 V and +10 V, Vout will change
-
Vi from
V0 Vin -
+
VO
+

10 kΩ 9k Ω
1kΩ
10kΩ
-15V a) -10 V to +10 V when Vin = -1 V
A triangular wave which goes from -12 V to 12 b) -10 V to +10 V when Vin = +1 V
V is applied to the inverting input of the c) +10 V to -10 V when Vin = -1 V
OP_Amp. Assume that the output of the OP- d) +10 V to -10 V when Vin = +1 V
Amp swings from +15 V to -15 V. the voltage at [GATE – 2008 IE]
the non – inverting input switches between
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61
 Rathi classes Analog Electronics
Q.9) The figure given below shows the circuit of a) Both A and R are true and R is the correct
which one of the following? explanation of A
+VDD b) Both A and R are true but R is NOT the
correct explanation of A
R c) A is true but R is false
V01 d) A is false but R is true
Vin V02 [IES - 1999 EC]
C
Q.14) Match List-I (Application of the circuit)
with List-II (Circuit Name) and select the correct
a) Bi – stable multi – vibrator answer using the codes given below the lists:
b) Schmitt trigger List-I
c) Monostable multi – vibrator A. Divider
d) Astable multi – vibrator B. Clips input voltage at two predetermined
[IES - 2008 EC] levels
C. Square wave generator
Q.10) Consider the following statements: D. Narrow current pulse generator
1. A Schmitt trigger circuit can be emitter- List-II
coupled bi – stable circuit. 1. Astable multivibrator
2. Schmitt trigger circuit exhibits hysteresis 2. Schmitt trigger
phenomenon. 3. Bistable multivibrator
3. The output of a Schmitt trigger will be 4. Blocking oscillator
triangular if the input is square wave. Codes:
Which of these statements are correct? A B C D
a) 1,2 and 3 b) 1 and 2 only a) 4 2 1 3
c) 2 and 3 only d) 1 and 3 only b) 3 2 1 4
[IES - 2011 EC] c) 4 1 2 3
d) 3 1 2 4
Q.11) In order to obtain repetitive pulses of [IES - 2004 EC]
unequal mark space one can use:
1. A voltage comparator fed with a triangular Q.15) In the following astable multivibrator
wave signal and dc voltage. circuit, which properties of v0(t) depend on R2?
2. An astable multi – vibrator.
3. A mono – stable multi – vibrator fed with a R1
square wave input.
Which of these statements are correct?
a) 1 and 3 only b) 1 and 3 only -
c) 2 and 3 only d) 1, 2 and 3 v0(t)
[IES - 2011 EC] +
C R3
Q.12) A 1 ms pulse can be stretched to 15 ms
pulse by using R2 R4
a) an astable multivibrator
b) a monostable multivibrator
c) a bistable multivibrator a) Only the frequency
d) a Schmitt trigger circuit b) Only the amplitude
[IES - 2000 EC] c) Both the amplitude and the frequency
d) Neither the amplitude nor the frequency
Q.13) Assertion (A): A monostable multivibrator [GATE - 2009 EC]
can be used to alter the pulse width of a
repetitive pulse train.
Reason (R): Monostable multivibrator has a
single stable state

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 Rathi classes Analog Electronics
Q.16) Consider the following two statements: a) Equal to zero because the input is zero
Statement 1: b) Dependent on element values hence nothing
A stable multivibrator can be used for can be predicted without a knowledge of
generating square wave. element values
Statement 2: c) A square wave varying between +𝑉𝐶𝐶 and
Bistable multivibrator can be used for storing −𝑉𝐶𝐶
binary information. d) A sinusoidal wave of amplifier VCC
a) Only statement 1 is correct [IES – 2002 EC]
b) Only statement 2 is correct
c) Both the statements 1 and 2 are correct Q.20) A 50 Hz symmetric square wave is
d) Both the statements 1 and 2 are incorrect applied to the RC-circuit shown in the diagram
[GATE - 2009 EC] given below:

Q.17) Consider the triangular wave generator

shown below:
CµF

10kΩ RkΩ ms ms

-
Input
-
+
1kΩ output
+ Which one of the following is the correct shape
of the output waveform?
a) b)

Assume that the op – amps are ideal and have

± 12 𝑉 power supply. If the input is a
± 5 𝑉 50 𝐻𝑧 square wave of duty cycle 50% , c) d)
the condition that results in a triangular wave of
peak to peak amplitude 5 V and frequency 50
Hz at the output is
𝑅 𝑅 𝐶
a) RC = 1 b) = 1 𝑐) = 5 𝑑) = 5
𝐶 𝐶 𝑅
[GATE – 2007 IE]

Q.18) A triangular-square wave generator uses [IES - 2003 EC]

a) A sine wave oscillation and a comparator
b) An integrator and a comparator Q.21) The function of the diode D in the timer
c) A differentiator and a comparator circuit shown above is to
d) A sine wave oscillator and a clipper
[IES - 2003 EC]

Q.19) An op-amp circuit is shown in the figure.

a) Increase the charging time of C

b) Decrease the charging time of C
c) Increase the discharging time of C
d) Decrease the discharging time of C
[IES - 2003 EC]
The output V0 will be (assume ideal op-amp)
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 Rathi classes Analog Electronics
Q.22) Consider the following circuit: voltage waveform are
VCC

RA

RB Th Vout
Tr
C R1
C 555
Timer
IC

What is the type of circuit given above?

a) Monostable b) Ramp generator a) RA = 3.62 kΩ, RB = 3.62 kΩ
c) VCO d) Bistable multivibrator b) RA = 3.62 kΩ, RB = 7.25 kΩ
[IES - 2004 EC] c) RA = 7.25 kΩ, RB = 3.62 kΩ
c) RA = 7.25 kΩ, RB = 7.25 kΩ
Q.23) a stable multi – vibrator circuit using IC [GATE - 2003 EE]
555 timer is shown below. Assume that the
circuit is oscillating steadily. Q.25) IC 555 in the figure is configured as an
9kΩ astable multivibrator. It is enabled to oscillate at
30 kΩ t=0 by applying a high input to pin 4. The pin
4 8
description is: 1 and 8 –supply; 2-trigger; 4-
(Reset) (Supply) reset; 6-threshold 7-discharge. The waveform
6 (Threshold) appearing across the capacitor starting from
t=0, as observed on a storage CRO is
10 kΩ (Output)3
+
2(Trigger) (Gnd)
(Discharge) 1
7
12kΩ 10 K
8
Vc 0.01µF
7

IC 555 3
The voltage VC across the capacitor varies 10 K
between 2,6
a) 3 V to 5 V b) 3 V to 6 V
c) 3.6 V to 6 V d)3.6 V to 5 V
[GATE - 2008 EC] 4 1

Q.24) The circuit of figure shown a 555 Timer

IC connected as an astable multivibrator. The a) b)
value of the capacitor C is 10 nF. The values of
the resistors RA and RB for a frequency of 10
KHz and a duty cycle of 0.75 for the output

c) d)

[GATE - 2007 EE]

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64
 Rathi classes Analog Electronics
Q.26) An Astable multivibrator circuit using a b) (td + tf) and (ts + tr)
555 IC is given in the following figure. The c) (tr + ts) and (td + tf)
frequency of oscillation is d) (td + tr) and (ts + tf)
[IES - 2012 EC]
V CC = 5 V

8 4 Q.29) In the given figure, if the input is a

sinusoidal signal, the output will appear as
shown in
I = 5 mA mA 3
output
6
Vth
555 Vin
2
Vtrig
7
Discharge t

C = 0. 1 µF
1

+V
a) 20 kHz b) 30 kHz c) 45 kHz d) 45 kHz R
[GATE – 2006 IE] -

Q.27) A 555 Astable multivibrator circuit is

shown in the figure below + +
5V
RL Vout
RA = 10 kΩ VCC reset -V
R
Discharge

RB = 10 kΩ Out
Trigger
VC Threshold a) b)
C Vout
1µF ground Vout
t t

If RB is shorted, the waveform at VC is

a) b) c) d)
VC
VC
2/3 VCC
2/3 V CC Vout
1/3 V CC
1/3 V CC
0 t 0 t t

b) d)
VC
VC
2/3 VCC
2/3 V CC

1/3 VCC
0 t
1/3 VCC
0 t *****
[GATE – 2007 IE]

Q.28) For a transistor used as a switch, td is

delay time, tr is rise time, ts is storage time and
tf is fall time. Then turn-on time tON and turn –
off time tOFF are respectively
a) (td + ts) and (tr + tf)

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