NCP1337

PWM Current-Mode
Controller for Free Running
Quasi-Resonant Operation
The NCP1337 combines a true current mode modulator and
a demagnetization detector which ensures full Borderline/Critical
Conduction Mode in any load/line conditions together with www.onsemi.com
minimum drain voltage switching (Quasi−Resonant operation).
The transformer core reset detection is done internally, without using
MARKING
any external signal, due to the Soxyless concept. The frequency is
DIAGRAM
internally limited to 130 kHz, preventing the controller to operate
above the 150 kHz CISPR−22 EMI starting limit. 7
By monitoring the feedback pin activity, the controller enters skip PDIP−7 NCP1337P
mode as soon as the power demand falls below a predetermined P SUFFIX AWL
level. As each restart is softened by an internal Soft−Skipt, and as CASE 626B YYWWG
the frequency cannot go below 25 kHz, no audible noise can be 1
heard.
The NCP1337 also features an efficient protective circuitry which, 8
in presence of an overcurrent condition, disables the output pulses P1337
SOIC−7
and enters a safe burst mode, trying to restart. Once the default has ALYWG
D SUFFIX G
gone, the device auto−recovers. Also included is a bulk voltage CASE 751U
monitoring function (known as brown−out protection), an adjustable 1
overpower compensation, and a VCC OVP. The controller
immediately restarts after any of these conditions, unless the fault A = Assembly Location
timer has timed out. Finally, an internal 4.0 ms soft−start eliminates WL, L = Wafer Lot
the traditional startup stress. YY, Y = Year
WW, W = Work Week
Features G, G = Pb−Free Package
• Free−Running Borderline/Critical Mode Quasi−Resonant Operation (Note: Microdot may be in either location)
• Current−Mode
• Soft−Skip Mode with Minimum Switching Frequency for Standby PIN CONNECTIONS
• Auto−Recovery Short−Circuit Protection Independent of Auxiliary BO
1 8
HV
Voltage 2
• Overvoltage Protection FB
3 6
• Brown−Out Protection CS VCC
• Two Externally Triggerable Fault Comparators (one for a disable GND
4 5
DRV
function, and the other for a permanent latch)
• Internal 4.0 ms Soft−Start (Top View)
• 500 mA Peak Current Drive Sink Capability
• 130 kHz Max Frequency ORDERING INFORMATION
• Internal Leading Edge Blanking Device Package Shipping†
• Internal Temperature Shutdown
NCP1337PG PDIP−7 50 Units/Rail
• Direct Optocoupler Connection (Pb−Free)
• Dynamic Self−Supply with Levels of 12 V (On) and 10 V (Off)
NCP1337DR2G SOIC−7 2500 Tape & Reel
• SPICE Models Available for TRANsient and AC Analysis (Pb−Free)
• These are Pb−Free Devices
†For information on tape and reel specifications,
Typical Applications including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
• AC−DC Adapters for Notebooks, etc. Brochure, BRD8011/D.
• Offline Battery Chargers
• Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.)
• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

December, 2014 − Rev. 6 NCP1337/D
 NCP1337

PIN FUNCTION DESCRIPTION

Pin No. Symbol Function Description
1 BO Brown−out and external • By connecting this pin to the input voltage through a resistor divider, the
triggering controller ensures operation at a safe mains level, thanks to a 500 mV
brown−out comparator.
• If an external event brings this pin above 3.0 V, the controller’s output is
disabled.
• If an external event brings this pin above 5.0 V, the controller is
permanently latched−off.
2 FB Sets the peak current • By connecting an optocoupler or an auxiliary winding to this pin, the peak
setpoint current setpoint is adjusted accordingly to the output power demand.
• When the requested peak current setpoint is below the internal standby
level, the device enters Soft−Skip mode.
3 CS Current sense input and • This pin senses the primary current and routes it to the internal comparator
overpower compensation via an L.E.B.
adjustment
• Inserting a resistor in series with the pin allows to control the overpower
compensation level.
4 GND IC ground
5 DRV Output driver • To be connected to an external MOSFET.

6 VCC IC supply • Connected to a tank capacitor (and possibly an auxiliary winding).

• When VCC reaches 18.6 V, an internal OVP stops the output pulses.

8 HV High−voltage pin • Connected to the high−voltage rail, this pin injects a constant current into
the VCC bulk capacitor and ensures a clean lossless startup sequence.

VOUT

+
NCP1337 VCC
BO
1 8

2 +
+C
bulk
3 6

4 5

VCC
Rcomp

Figure 1. Typical Application Schematic

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 NCP1337

-
+ S Q PERM. LATCH
5V
+ 8 ms 35 ms
R Vdd timeout max Toff
+ + DISABLE 5.5 ms
VCC < 4 V Toff
3V - blanking
Vdd TSD TSD
BO 10 mA S Ton
Startup VCC
Soxyless Clk
Q
7.5 ms min
VBO + BOK Ton D Q Inhib
period
- Toff
Soxyless
+ SStart R1 demag
500 mV R2 DRV
OVP detection

67 ms
Skip Ton
- max Ton
100 mV + SSkip
Vdd 130 mV +
FB Soxyless

3V Setpoint
12 V
20 kHz HV
- TSD 10 V
Low−pass +
5V +
filter +
CS -
comp. PERM. 9.5 mA or
500 mV LATCH 600 mA
FAULT FAULT
Vdd if Zener Management* VCC
activated 300 ms
SSkip
Soft−Skipt

VBO
70 mA x VBO − 35 mA 4 ms
SStart OVP -
soft−start
+
Ton +
CS 18.6 V
350 ns
LEB
4k FAULT
2p

(*If FAULT duration > 80 ms = > STOP

GND Restart when 2nd time VCC = VCCon)

Figure 2. Internal Circuit Architecture

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 NCP1337

MAXIMUM RATINGS
Rating Symbol Value Unit
Voltage on Pin 8 (HV) when Pin 6 (VCC) is Decoupled to Ground with 10 mF VHV −0.3 to 500 V
Maximum Current in Pin 8 (HV) − 20 mA
Power Supply Voltage, Pin 6 (VCC) and Pin 5 (DRV) VCCmax −0.3 to 20 V
Maximum Current in Pin 6 (VCC) − ±30 mA
Maximum VCC Slew Rate (dV/dt) dVCC/dt 9.0 V/ms
Maximum Voltage on all Pins except Pin 8 (HV), Pin 6 (VCC) and Pin 5 (DRV) − −0.3 to 10 V
Maximum Current into all Pins except Pin 8 (HV), Pin 6 (VCC) and Pin 5 (DRV) − ±10 mA
Maximum Current into Pin 6 (DRV) during ON Time and TBLANK − ±1.0 A
Maximum Current into Pin 6 (DRV) after TBLANK during OFF Time − ±15 mA
Thermal Resistance, Junction−to−Case RqJC 57 °C/W
Thermal Resistance, Junction−to−Air, SOIC Version RqJA 178 °C/W
Thermal Resistance, Junction−to−Air, DIP Version RqJA 100 °C/W
Maximum Junction Temperature TJMAX 150 °C
Operating Temperature Range − −40 to +125 °C
Storage Temperature Range − −60 to +150 °C
ESD Capability, HBM Model per JESD22, Method A114E (All Pins except HV) − 2.0 kV
ESD Capability, Machine Model per JESD22, Method A115A − 200 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains latchup protection and exceeds 100 mA per JEDEC standard JESD78.

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 NCP1337

ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C, VCC = 11 V, unless otherwise noted.)
Characteristic Pin Symbol Min Typ Max Unit

SUPPLY SECTION
VCC Increasing Level at which the Controller Starts 6 VCCON 11 12 13 V
VCC Decreasing Level at which the Controller Stops 6 VCCMIN 9.0 10 11 V
Protection Mode is Activated if VCC reaches this Level whereas the HV 6 VCCOFF − 9.0 − V
Current Source is ON

VCC Decreasing Level at which the Latch−Off Phase Ends 6 VCCLATCH 3.6 5.0 6.0 V
Margin between VCC Level at which Latch Fault is Released and − VMARGIN 0.3 − − V
VCCLATCH

VCC Increasing Level at which the Controller Enters Protection Mode 6 VCCOVP 17.6 18.6 19.6 V
VCC Level below which HV Current Source is Reduced 6 VCCINHIB − 1.5 − V
Internal IC Consumption, No Output Load on Pin 5, FSW = 60 kHz 6 ICC1 − 1.2 − mA
Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 60 kHz 6 ICC2 − 2.0 − mA
Internal IC Consumption, Latch−Off Phase, VCC = 8.0 V 6 ICC3 − 600 − mA
Internal IC Consumption in Skip 6 ICCLOW − 600 − mA

INTERNAL STARTUP CURRENT SOURCE

Minimum Guaranteed Startup Voltage on HV Pin 8 VHVmin − − 55 V
High−Voltage Current Source when VCC > VCCINHIB 8 IC1 5.5 9.5 15 mA
(VCC = 10.5 V, VHV = 60 V)

High−Voltage Current Source when VCC < VCCINHIB 8 IC2 0.3 0.6 1.1 mA
(VCC = 0 V, VHV = 60 V)

Leakage Current Flowing when the HV Current Source is OFF 8 IHVLeak − − 90 mA

(VCC = 17 V, VHV = 500 V)

DRIVE OUTPUT
Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of Output Signal 5 TR − 50 − ns
Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of Output Signal 5 TF − 20 − ns
Source Resistance 5 ROH − 20 − W
Sink Resistance 5 ROL − 8.0 − W

TEMPERATURE SHUTDOWN
Temperature Shutdown − TSD 130 − − °C
Hysteresis on Temperature Shutdown − − − 30 − °C

CURRENT COMPARATOR
Maximum Internal Current Setpoint (@ IFB = IFB100%) 3 VCSLimit 475 500 525 mV
Minimum Internal Current Setpoint (@ IFB = IFBrippleIN) 3 VCSrippleIN − 100 − mV
Internal Current Setpoint for IFB = IFBrippleOUT 3 VCSrippleOUT − 130 − mV
Propagation Delay from Current Detection to Gate OFF State 3 TDEL − 120 150 ns
Leading Edge Blanking Duration 3 TLEB − 350 − ns
Internal Current Offset Injected on the CS Pin during ON Time 3 IOPC mA
(Over Power Compensation)
@ 1.0 V on Pin 1 and Vpin3 = 0.5 V − 35 −
@ 2.0 V on Pin 1 and Vpin3 = 0.5 V − 105 −
Maximum ON Time 5 MaxTON 52 67 82 ms

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 NCP1337

ELECTRICAL CHARACTERISTICS (continued)

(For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C, VCC = 11 V, unless otherwise noted.)
Characteristic Pin Symbol Min Typ Max Unit

FEEDBACK SECTION
FB Current under which FAULT is Detected 2 IFBopen − 40 − mA
FB Current for which Internal Setpoint is 100% 2 IFB100% − 50 − mA
FB Current above which DRV Pulses are Stopped 2 IFBrippleIN − 220 − mA
FB Current under which DRV Pulses are Reauthorized after having 2 IFBrippleOUT − 205 − mA
reached IFBrippleIN

FB Current above which FB Pin Voltage is not Regulated anymore 2 IFBregMax − 500 − mA
FB Pin Voltage when IFBopen < IFB < IFBregMax 2 VFB 2.8 3.0 3.2 V
Duration before Entering Protection Mode after FAULT Detection − TFAULT − 80 − ms
Internal Soft−Start Duration (Up to VCSLimit) − TSS − 4.0 − ms
Internal Soft−Skip Duration (Up to VCSLimit) − TSSkip − 300 − ms

BROWN−OUT AND LATCH SECTION

Brown−Out Detection Level 1 VBO 460 500 540 mV
Current Flowing out of Pin 1 when Brown−Out Comparator has Toggled 1 IBO − 10 − mA
Vpin1 Threshold that Disables the Output 1 VDISABLE 2.8 3.0 3.3 V
Vpin1 Threshold that Activates the Permanent Latch 1 VLATCH 4.75 5.0 5.25 V

DEMAGNETIZATION DETECTION BLOCK

Current Threshold for Demagnetization Detection 5 ISOXYth − 210 − mA
Max Voltage on DRV Pin During OFF Time after TBLANK 5 VDRVlowMAX − − 1.5 V
(when Sinking 15 mA)

Min Voltage on DRV Pin During OFF Time after TBLANK 5 VDRVlowMIN −0.6 − − V
(when Sourcing 15 mA)

Propagation Delay from Demag Detection to Gate ON State 5 TDMG − 180 220 ns
(IGATE Slope of 500 A/s)

Blanking Window after Gate OFF State before Detecting 5 TBLANK − 5.5 − ms
Demagnetization

Timeout on Demag Signal 5 TOUT − 8.0 − ms

Maximum OFF Time 5 MaxTOFF − 35 42 ms
Minimum Switching Period 5 MinPeriod 6.8 7.7 8.5 ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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 NCP1337

APPLICATION INFORMATION

INTRODUCTION starts again. The soft−start, together with a minimum

frequency clamp, allow to reduce the noise generated
The NCP1337 implements a standard current mode
in the transformer in short−circuit conditions.
architecture where the switch−off time is dictated by the
peak current setpoint, whereas the core−reset detection • Overvoltage Protection (OVP): By continuously
triggers the turn−on event. This component represents monitoring the VCC voltage level, the NCP1337 stops
the ideal candidate where low part−count is the key switching whenever an overvoltage condition is
parameter, particularly in low−cost AC−DC adapters, detected.
consumer electronics, auxiliary supplies, etc. Due to • Brown−Out Detection (BO): By monitoring the level
its high−performance, high−voltage technology, the on Pin 1 during normal operation, the controller
NCP1337 incorporates all the necessary features needed to protects the SMPS against low mains condition. When
build a rugged and reliable Switch−Mode Power Supply Pin 1 level falls below 500 mV, the controller stops
(SMPS): switching until this level goes back and resumes
• Quasi−Resonant Operation: Valley−switching operation, unless the fault timer has timed out. By
operation is ensured whatever the operating conditions adjusting the resistor divider connected between the
are, due to the internal soxyless circuitry. As a result, high input voltage and this pin, start and stop levels
there are virtually no primary switch turn−on losses, are programmable.
and no secondary diode recovery losses, and EMI and • Over Power Compensation (OPC): An internal
video noise perturbations are reduced. The converter current source injects out of Pin 3 (CS pin) a current
also stays a first−order system and accordingly eases proportional to the voltage applied on Pin 1. As this
the feedback loop design. voltage is an image of the input voltage, by inserting a
• Dynamic Self−Supply (DSS): Due to its Very High resistor in series with Pin 3, it is possible to create an
Voltage Integrated Circuit (VHVIC) technology, offset on the current sense signal that will compensate
ON Semiconductor’s NCP1337 allows for a direct pin the effect of the input voltage variation.
connection to the high−voltage DC rail. A dynamic • External Latch Trip Point: By externally forcing a
current source charges up a capacitor and thus level on Pin 1 (e.g., with a signal coming from a
provides a fully independent VCC level. As a result, temperature sensor) greater than 3.0 V (but below
low power applications will not require any auxiliary 5.0 V), it is possible to disable the output of the
winding to supply the controller. In applications controller. If the voltage is forced over 5.0 V, the
where this winding is anyway required (see “Power controller is permanently latched−off: to resume
Dissipation” section in the application note), the DSS normal operation, the VCC voltage should go below
will simplify the VCC capacitor selection. 4.0 V, which implies to unplug the SMPS from the
• Overcurrent Protection (OCP): When the feedback mains.
current is below minimum value, a fault is detected. If • Standby Ability: Under low load conditions,
this fault is present for more than 80 ms, NCP1337 NCP1337 enters a Soft−Skip mode: when the CS
enters an auto−recovery soft burst mode. All pulses are setpoint becomes lower than 20% of the maximum
stopped and the VCC capacitor discharges down to peak current, output pulses are stopped, then switching
5.0 V. Then, by monitoring the VCC level, the startup is starting again when FB loop forces a setpoint higher
current source is activated ON and OFF to create a than 25%. As this occurs at low peak current, with
burst mode. After the current source being activated Soft−Skip activated, and as the TOFF is clamped,
twice, the controller tries to restart, with a 4.0 ms noise−free operation is guaranteed, even with a cheap
soft−start. If the fault has gone, the SMPS resumes transformer.
operation. If the fault is still there, the burst sequence

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 NCP1337

Timing Diagrams

VCC

VCCON

VCCMIN

At startup, a 4.0 ms soft−start is activated.

If the current Setpoint is above the fault
level, FAULT flag is raised.

CS
Setpoint

Fault

VCSstby

CS
VCSLimit

FAULT SS

TIMER When FAULT is activated,

the 80 ms timer starts.
80 ms

When the timer ends, if FAULT is not activated

anymore, the controller works normally.

Figure 3. Startup Sequence

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 NCP1337

VCC Restart on 2nd cycle

VCCON

VCCMIN

VCCLATCH

CS Overload Overload is removed here

Setpoint

Fault

When the current setpoint rises above

fault level, FAULT flag is activated.

CS
VCSLimit

Output pulses
are stopped.

FAULT
SS

TIMER When FAULT flag

is activated, timer
80 ms is restarted.

80 ms Fault Timer Normal Startup

Figure 4. Overload

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 NCP1337

VCC

VCCon

VCCmin

CS
Setpoint

VCSrippleOUT
VCSrippleIN

CS
(envelope)

Min TON

Soft−Skip on
each re−start

Figure 5. Soft−Skip Mode in Standby

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 NCP1337

Soxyless
The “Valley point detection” is based on the observation MOSFET (modelized by the Crss capacitance between
of the Power MOSFET Drain voltage variations. When the Gate and Drain): a negative current (flowing out of DRV
transformer is fully demagnetized, the Drain voltage pin) takes place during the decreasing part of the Drain
evolution from the plateau level down to the VIN asymptote oscillation, and a positive current (entering into the DRV
is governed by the resonating energy transfer between the pin) during the increasing part.
LP transformer inductor and the global capacitance present The Drain valley corresponds to the inversion of the
on the Drain. These voltage oscillations create current current (i.e., the zero crossing): by detecting this point, we
oscillation in the parasitic capacitor across the switching always ensure a true valley turn−on.

Lprim TSWING
Vswitch

Crss
Isoxy

DRV

Figure 6. Soxyless Concept

The current in the Power MOSFET gate is: Drain. This capacitance includes the snubber capacitor if
Igate = Vringing/Zc (with Zc the capacitance impedance) any, the transformer windings stray capacitance plus the
so parasitic MOSFET capacitances COSS and CRSS).
Igate = Vringing S (2 S p S Fres S Crss)
Internal Feedback Circuitry
The magnitude of this gate current depends on the To simplify the implementation of a primary regulation,
MOSFET, the resonating frequency and the voltage swing it is necessary to inject a current into the FB pin (instead of
present on the Drain at the end of the plateau voltage. sourcing it out). But to have a precise primary regulation,
The dead time TSWING is given by the equation: the voltage present on FB pin must be regulated. Figure 8
Tswing + 0.5ńFres + p * ǸLp * Cdrain (eq. 1) gives the FB pin internal implementation: the circuitry
combines the functions of a current to voltage converter
(where LP is the primary transformer inductance and and a voltage regulator.
CDRAIN the total capacitance present on the MOSFET

Vdd

FB
+

- Internal
+ Setpoint
3V

20 kHz
Low−pass Filter

Figure 7. Internal Implementation of FB Pin

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 NCP1337

The input information is the current injected in FB pin by activated. However, as the fault timer is still active, it can
the feedback loop. The range of current is from 40 mA for time out while the switching is stopped. As a result the
overload detection to 220 mA corresponding to VCSrippleIN. controller will go into protection mode, and won’t restart
In transients, currents from 0 to more than 400 mA may also instantaneously.
appear: the circuitry is able to sustain them. • Permanent Latch (Comparator activated by an external
To regulate the FB pin voltage, the operational amplifier signal): Activated when the voltage on BO pin is
needs to have a high gain and a wide bandwidth. But the above 5.0 V
feedback information used internally needs to be filtered,
When this comparator is activated, the DRV pulses are
because we don’t want the controller to be sensitive to the
stopped, and the DSS is deactivated (only the start−up
switching noise. For this purpose, a 20 kHz filter is added
current source is turned on each time VCC reaches
after the shunt regulator, and any reading of the feedback
VCCLATCH, maintaining VCC between 5.0 V and 12 V):
signal (for ripple mode, fault detection, or setpoint
the controller stays in this position until the VCC voltage is
elaboration) is done after.
decreased below 4.0 V, i.e., when the power supply is
Soft Burst Mode (Protection Mode) unplugged from the mains (in normal operation, as soon as
The NCP1337 features a fault timer to detect an overload a voltage is present on the HV pin, VCC is always kept
completely independently of the VCC voltage. As soon as above 5.0 V).
the feedback loop asks for the maximum power, a fault is
Soft−Skip Mode
detected, and an internal timer is started. When the fault
The soft ripple mode is a skip mode with a large
disappears the timer is reset, but if the timer reaches 80 ms,
hysteresis on the skip comparator in order to ensure a
the protection mode is activated.
noise−free and high−efficiency operation in low−load
Once this protection is toggled, output pulses are stopped
conditions (standby). When internal setpoint is reaching
and DSS is deactivated (HV current source turn−on
VCSrippleIN = 100 mV (corresponding to 20% of the
threshold changes from VCCMIN to VCCLATCH). VCC
maximum setpoint), the output pulses are stopped. Then
slowly decreases (the current consumption is ICC3), and
FB loop asks for more power and internal setpoint is
the HV current source is switched ON when VCC reaches
increasing: when it reaches VCSrippleOUT = 130 mV
VCCLATCH. As a result VCC increases until VCCON, but the
(corresponding to 25% of the maximum setpoint), the
controller does not start as the output is still forced low.
output starts switching again. Soft−Skip is activated in each
VCC decreases again down to VCCLATCH, and a new
activity following a stop period. See Figure 5 for detailed
start−up cycle occurs. On the second attempt, the output is
timing diagram.
released, and NCP1337 effectively starts, with the
soft−start activated. Figure 4 illustrates this behavior. HV Current Source
NCP1337 features a DSS, to allow operation without any
Safety Features
auxiliary voltage. But to protect the die in case of
The NCP1337 includes several safety features to help the
short−circuit on VCC pin, the current delivered by the HV
power supply designer to build a rugged design:
current source is lowered when VCC voltage is below 1.5 V.
• OVP (Overvoltage on VCC): Activated when voltage In the case the current consumed on the DRV pin is
on pin VCC is higher than 18.6 V higher than the DSS capability (high Qg MOSFET or
• Brown−Out (Undervoltage lockout on bulk voltage): failure), the HV current source is switched ON when VCC
Activated when voltage on pin BO is below 500 mV reaches VCCMIN, but the voltage on VCC pin keep on
• Disable (Comparator activated by an external signal): decreasing. If there is no UVLO threshold to stop the DRV
Activated when the voltage on BO pin is higher than pulses, the gate voltage will become too low and the risk is
3.0 V but below 5.0 V high to destroy the MOSFET. NCP1337 features an
• TSD (Temperature shutdown): Typically activated additional comparator, which threshold is 9.0 V: when VCC
when the die temperature is above 150°C, released at reaches this level whereas the HV current source is ON,
120°C DRV pulses are stopped and the protection mode is
activated.
All these events have the same consequence for the The maximum dV/dt that can be applied to the VCC pin
controller: the DRV pulses are stopped. When the condition is 9.0 V/ms. The supply capacitor is selected to ensure the
disappears, the controller restarts with the soft−start maximum dV/dt is not exceeded.

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 NCP1337

Brown−Out
The brown−out protection comparator has a fixed The BO pin also features two additional comparators: the
reference of 500 mV. When the comparator is activated first one (that toggles at 3.0 V) stops the DRV pulses,
(i.e., when the input voltage VIN is above the starting level), whereas the second one (that toggles at 5.0 V) permanently
a 10 mA internal current source is activated and creates an latches off the controller (the VCC should be forced below
offset across the bottom resistor of the external resistor 4.0 V to release the latch).
divider. It gives the minimum hysteresis of the brown−out Figure 8 gives the internal implementation of the BO
protection. By adding a series resistor between the divider pin.
and the BO pin, it is possible to adjust (increase) the
hysteresis.

+
Permanent Latch
-
+
5V

-
Enable
+
+
3V

Vin
Vdd

3.3 meg 10 mA current source activated

when VBOK is high

Rhyst BO
+
BOK
-
+
11 k 500 mV

Figure 8. Internal Implementation of BO Pin

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 NCP1337

PACKAGE DIMENSIONS

SOIC−7
D SUFFIX
CASE 751U
ISSUE E

−A− NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
8 5 3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
−B− S 0.25 (0.010) M B M 4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
1 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
4 PER SIDE.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
G A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C R X 45 _ C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
J H 0.10 0.25 0.004 0.010
−T− SEATING J 0.19 0.25 0.007 0.010
PLANE K 0.40 1.27 0.016 0.050
K M 0_ 8 _ 0_ 8_
H M
D 7 PL N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M T B S A S

SOLDERING FOOTPRINT*

1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 NCP1337

PACKAGE DIMENSIONS

PDIP−7 (PDIP−8 LESS PIN 7)

P SUFFIX
CASE 626B
ISSUE C

NOTES:
D A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
E 2. CONTROLLING DIMENSION: INCHES.
H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
8 5
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT
E1 TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
1 4 PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
NOTE 8 LEADS UNCONSTRAINED.
c 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
b2 B END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 5
INCHES MILLIMETERS
A2 DIM MIN MAX MIN MAX
e/2 A −−−− 0.210 −−− 5.33
A NOTE 3 A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
L b 0.014 0.022 0.35 0.56
b2 0.060 TYP 1.52 TYP
C 0.008 0.014 0.20 0.36
D 0.355 0.400 9.02 10.16
SEATING
PLANE D1 0.005 −−−− 0.13 −−−
A1 E 0.300 0.325 7.62 8.26
C M E1 0.240 0.280 6.10 7.11
D1 e 0.100 BSC 2.54 BSC
eB −−−− 0.430 −−− 10.92
e eB L 0.115 0.150 2.92 3.81
8X b END VIEW M −−−− 10 ° −−− 10 °
0.010 M C A M B M NOTE 6
SIDE VIEW

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