DATA SHEET

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Current-Mode PWM MARKING

DIAGRAM
Controller for Off-line TSOP−6
Power Supplies (SOT23−6)
SN SUFFIX
5xyAYWG
G
1 CASE 318G
1
NCP1251 STYLE 13

5xy = Specific Device Code

The NCP1251 is a highly integrated PWM controller capable of x = A or U
delivering a rugged and high performance offline power supply in a y = A, 2, C, D, or F
tiny TSOP−6 package. With a supply range up to 28 V, the controller A = Assembly Location
hosts a jittered 65 kHz or 100 kHz switching circuitry operated in peak Y = Year
W = Work Week
current mode control. When the power on the secondary side starts to
G = Pb−Free Package
decrease, the controller automatically folds back its switching
frequency down to a minimum level of 26 kHz. As the power further (Note: Microdot may be in either location)
goes down, the part enters skip cycle while limiting the peak current.
Over Power Protection (OPP) is a difficult exercise especially when PIN CONNECTIONS
no−load standby requirements drive the converter specifications. The
ON proprietary integrated OPP lets you harness the maximum GND 1 6 DRV
delivered power without affecting your standby performance simply
via two external resistors. A latched Over Voltage Protection (OVP) is FB 2 5 VCC
combined on the same pin. For ease of implementation, a latched OVP
OPP/Latch 3 4 CS
also monitors the VCC line. They offer an efficient protection in case
of optocoupler destruction or adverse open loop operation. (Top View)
Finally, a timer−based short−circuit protection offers the best
protection scheme, letting you precisely select the protection trip point
irrespective of a loose coupling between the auxiliary and the power ORDERING INFORMATION
windings. See detailed ordering, marking and shipping information on
page 2 of this data sheet.
Features
 Fixed−Frequency 65 or 100 kHz Current−Mode Control Operation
 Internal and Adjustable Over Power Protection (OPP) Circuit
 Frequency Foldback Down to 26 kHz and Skip−Cycle in Light Load
Conditions
 Internal Ramp Compensation
 Internal Fixed 4 ms Soft−Start
 100 ms Timer−Based Auto−Recovery Short−Circuit Protection
 Frequency Jittering in Normal and Frequency Foldback Modes
 Option for Auto−Recovery or Latched Short−Circuit Protection
 OVP Input for Improved Robustness
 Up to 28 V VCC Operation
 Latched or Auto−Recovery OVP Protection on VCC
 +300 mA / −500 mA Source/Sink Drive Capability
 Less than 100 mW Standby Power at High Line
 EPS 2.0 Compliant
 These are Pb−Free Devices

Typical Applications
 ac−dc Converters for TVs, Set−top Boxes and Printers
 Offline Adapters for Notebooks and Netbooks

 Semiconductor Components Industries, LLC, 2015 1 Publication Order Number:

January, 2024 − Rev. 15 NCP1251/D
 NCP1251

Vbulk
Vo u t
.

.
OVP

OPP
.

NCP1251
1 6

2 5

3 4
ramp
comp.

Figure 1. Typical Application Example

Pin N5 Pin Name Function Pin Description

1 GND − The controller ground.
2 FB Feedback pin Hooking an optocoupler collector to this pin will allow regulation.
3 OPP/OVP Adjust the Over Power Protection A resistive divider from the auxiliary winding to this pin sets the OPP
Latches off the part compensation level. When brought above 3 V, the part is fully latched off.
4 CS Current sense + ramp This pin monitors the primary peak current but also offers a means to
compensation introduce ramp compensation.
5 VCC Supplies the controller This pin is connected to an external auxiliary voltage and supplies the
controller. When the VCC exceeds a certain level, the part permanently
latches off.
6 DRV Driver output The driver’s output to an external MOSFET gate.

OPTIONS
Controller Frequency OCP VCC OVP OVP/OTP
NCP1251ASN65T1G 65 kHz Latched Latched Latched
NCP1251BSN65T1G 65 kHz Autorecovery Latched Latched
NCP1251CSN65T1G 65 kHz Autorecovery Autorecovery Latched
NCP1251FSN65T1G 65 kHz Autorecovery Latched Latched
NCP1251ASN100T1G 100 kHz Latched Latched Latched
NCP1251BSN100T1G 100 kHz Autorecovery Latched Latched
NOTE: F version has a different foldback scheme for improved efficiency.

ORDERING INFORMATION
Package VCC OVP Switching
Device Marking OCP Protection Protection Frequency Package Shipping†
NCP1251ASN65T1G 5AA Latch Latch 65 kHz
NCP1251BSN65T1G 5A2 Autorecovery Latch 65 kHz
NCP1251CSN65T1G 5AE Autorecovery Autorecovery 65 kHz TSOP−6 3000 /
NCP1251FSN65T1G 5AF Autorecovery Latch 65 kHz (Pb−Free) Tape & Reel

NCP1251ASN100T1G 5AC Latch Latch 100 kHz

NCP1251BSN100T1G 5AD Autorecovery Latch 100 kHz
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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 NCP1251
IpFlag BO
OPP
600−ns time
constant
Vcc logic
UVLO
management
and fault timer
Vlatch Up counter
vdd
OVP
RST
gone? 4
20us time
constant
power VOVP
on reset

S
Q
Q Rlimit
Vcc
Iscr
1−us
vdd R blanking

Power on
reset 65 kHz
100 kHz
clock Clamp
Frequency
modulation
S
Q
Q

Frequency
Drv
foldback

Vfold

Vskip

Rramp
4 ms
SS
vdd
The soft−start is activated during: IpFlag

RFB − the startup sequence

− the auto−recovery burst mode
/ 4.2
VFB < 1.05 V ? setpoint = 250 mV
FB

VOPP Vlimit + VOPP

250 mV +
peak current
freeze
CS LEB GND

Vlimit

Figure 2. Internal Circuit Architecture

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 NCP1251

MAXIMUM RATINGS TABLE

Symbol Rating Value Unit
VCC Power Supply voltage, VCC pin, continuous voltage 28 V
VDRVtran Maximum DRV pin voltage when DRV in H state, transient voltage (Note 1) VCC + 0.3 V
Maximum voltage on low power pins CS, FB and OPP −0.3 to 10 V
IOPP Maximum injected negative current into the OPP pin (pin 3) −2 mA
ISCR Maximum continuous current into the VCC pin while in latch mode 3 mA
RqJA Thermal Resistance Junction−to−Air 360 C/W
TJ,max Maximum Junction Temperature 150 C
Storage Temperature Range −60 to +150 C
ESD Capability, Human Body Model (HBM), all pins 2 kV
ESD Capability, Machine Model (MM) 200 V
ESD Capability, Charged Device Model (CDM) 1 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The transient voltage is a voltage spike injected to DRV pin being in high state. Maximum transient duration is 100 ns.
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JESD22, Method A114E.
Machine Model Method 200 V per JESD22, Method A115A. Charged Device Model per JEDEC Standard JESD22−C101D
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

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 NCP1251

ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25C, for min/max values TJ = −40C to +125C, Max TJ = 150C, VCC = 12 V unless otherwise noted)

Symbol Rating Pin Min Typ Max Unit

SUPPLY SECTION
VCCON VCC increasing level at which driving pulses are authorized 5 16 18 20 V
VCC(min) VCC decreasing level at which driving pulses are stopped 5 8.2 8.8 9.4 V
VCCHYST Hysteresis VCCON − VCC(min) 5 6.0 V
VZENER Clamped VCC when latched off / burst mode activation @ ICC = 500 mA 5 7.0 V
ICC1 Start−up current 5 15 mA
ICC2 Internal IC consumption with IFB = 50 mA, FSW = 65 kHz and CL = 0 nF 5 1.4 2.2 mA
ICC3 Internal IC consumption with IFB = 50 mA, FSW = 65 kHz and CL = 1 nF 5 2.1 3.0 mA
ICC2 Internal IC consumption with IFB = 50 mA, FSW = 100 kHz and CL = 0 nF 5 1.7 2.5 mA
ICC3 Internal IC consumption with IFB = 50 mA, FSW = 100 kHz and CL = 1 nF 5 3.1 4.0 mA
ICCstby Internal IC consumption while in skip cycle (VCC = 12 V, driving a typical 6 A/600 V 5 550 mA
MOSFET)

ICCLATCH Current flowing into VCC pin that keeps the controller latched (Note 4) 5 mA
TJ = −40C to +125C 40
TJ = 0C to +125C 32
Rlim Current−limit resistor in series with the latch SCR 5 4.0 kW
DRIVE OUTPUT
Tr Output voltage rise−time @ CL = 1 nF, 10−90% of output signal 6 40 ns
Tf Output voltage fall−time @ CL = 1 nF, 10−90% of output signal 6 30 ns
ROH Source resistance 6 13 W
ROL Sink resistance 6 6.0 W
Isource Peak source current, VGS = 0 V – (Note 5) 6 300 mA
Isink Peak sink current, VGS = 12 V – (Note 5) 6 500 mA
VDRVlow DRV pin level at VCC close to VCC(min) with a 33 kW resistor to GND 6 8.0 V
VDRVhigh DRV pin level at VCC = 28 V – DRV unloaded 6 10 12 14 V
CURRENT COMPARATOR
IIB Input Bias Current @ 0.8 V input level on pin 4 4 0.02 mA
VLimit1 Maximum internal current setpoint – TJ = 25C – pin 3 grounded 4 0.744 0.8 0.856 V
VLimit2 Maximum internal current setpoint – TJ = −40C to 125C – pin 3 grounded 4 0.72 0.8 0.88 V
Vfold Default internal voltage set point for frequency foldback trip point – 45% of Vlimit 3 357 mV
Vfreeze Internal peak current setpoint freeze ([31% of Vlimit) 3 250 mV
TDEL Propagation delay from current detection to gate off−state 4 100 150 ns
TLEB Leading Edge Blanking Duration 4 300 ns
TSS Internal soft−start duration activated upon startup, auto−recovery − 4 ms
IOPPo Setpoint decrease for pin 3 biased to –250 mV – (Note 6) 3 31.3 %
IOOPv Voltage setpoint for pin 3 biased to −250 mV – (Note 6), TJ = 25C 3 0.51 0.55 0.60 V
IOOPv Voltage setpoint for pin 3 biased to −250 mV – (Note 6), TJ = −40C to 125C 3 0.50 0.55 0.62 V
IOPPs Setpoint decrease for pin 3 grounded 3 0 %
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. For design robustness, we recommend to inject 60 mA as a minimum at the lowest input line voltage.
5. Guaranteed by design
6. See characterization table for linearity over negative bias voltage
7. A 1 MW resistor is connected from pin 3 to the ground for the measurement.

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 NCP1251

ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25C, for min/max values TJ = −40C to +125C, Max TJ = 150C, VCC = 12 V unless otherwise noted)

Symbol Rating Pin Min Typ Max Unit

INTERNAL OSCILLATOR
fOSC Oscillation frequency (65 kHz version) − 61 65 71 kHz
fOSC Oscillation frequency (100 kHz version) − 92 100 108 kHz
Dmax Maximum duty−cycle − 76 80 84 %
fjitter Frequency jittering in percentage of fOSC − 5 %
fswing Swing frequency − 240 Hz
FEEDBACK SECTION
Rup Internal pull−up resistor 2 20 kW
Req Equivalent ac resistor from FB to GND 2 16 kW
Iratio Pin 2 to current setpoint division ratio − 4.2
Vfreeze Feedback voltage below which the peak current is frozen 2 1.05 V
FREQUENCY FOLDBACK
Vfold Frequency foldback level on the feedback pin – [45% of maximum peak current − 1.5 V
VfoldF Frequency foldback level on the feedback pin – [59% of maximum peak current − 1.9 V
(F version only)

Ftrans Transition frequency below which skip−cycle occurs − 22 26 30 kHz

Vfold,end End of frequency foldback feedback level, Fsw = Fmin 350 mV
VfoldF,end End of frequency foldback feedback level, Fsw = Fmin 1.5 V
(F version only)

Vskip Skip−cycle level voltage on the feedback pin − 300 mV

Skip Hysteresis on the skip comparator – (Note 5) − 30 mV
hysteresis

INTERNAL SLOPE COMPENSATION

Vramp Internal ramp level @ 25C – (Note 7) 4 2.5 V
Rramp Internal ramp resistance to CS pin 4 20 kW
PROTECTIONS
Vlatch Latching level input 3 2.7 3 3.3 V
Tlatch−blank Blanking time after drive turn off 1 1.0 ms
Tlatch−count Number of clock cycles before latch confirmation − 4.0
Tlatch−del OVP detection time constant 1 600 ns
Timer Internal auto−recovery fault timer duration − 100 130 160 ms
VOVP Latched Over voltage protection on the VCC rail 5 24 25.5 27 V
TOVPdel Delay before OVP on VCC confirmation 5 20 ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. For design robustness, we recommend to inject 60 mA as a minimum at the lowest input line voltage.
5. Guaranteed by design
6. See characterization table for linearity over negative bias voltage
7. A 1 MW resistor is connected from pin 3 to the ground for the measurement.

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 NCP1251

TYPICAL CHARACTERISTICS

85 72
84
70
83
82
68
81

FSW (kHz)
Dmax (%)

80 66
79
64
78
77
62
76
75 60
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 3. Figure 4.

31
440
30
29 390
28
340
F_swing (Hz)

27
Ftrans (kHz)

26
290
25
24 240

23
190
22
21 140
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 5. Figure 6.

0.89
490
0.87 FSW = 65 kHz
440
0.85
0.83 390
VLskip (mV)
Vlimit (mV)

0.81 340
0.79
290
0.77
240
0.75

0.73 190

0.71 140
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 7. Figure 8.

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 NCP1251

TYPICAL CHARACTERISTICS

44
0.6
39
0.58

34
IOOPO (%)

IOOPV (V)
0.56

29
0.54

24 0.52

19 0.5
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 9. Figure 10.

9.5
19.9

19.4 9.3

18.9 9.1
VCC(min) (V)
VCC(ON) (V)

18.4 8.9
17.9
8.7
17.4
8.5
16.9

16.4 8.3

15.9 8.1
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 11. Figure 12.

14 16
13 14
12
12
11
10
VCC(Hyst) (V)

ICC1 (mA)

10
8
9
6
8
7 4

6 2

5 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 13. Figure 14.

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 NCP1251

TYPICAL CHARACTERISTICS

2 2.5
FSW = 65 kHz
FSW = 65 kHz
2
1.5

1.5
ICC2 (mA)

ICC3 (mA)
1
1

0.5
0.5

0 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125

TEMPERATURE (C) TEMPERATURE (C)

Figure 15. Figure 16.

30
10
25
8
20
ICCLatch (mA)
Vzener (V)

6
15

4
10

2 5

0 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125

TEMPERATURE (C) TEMPERATURE (C)

Figure 17. Figure 18.

160
390
140
340
120

290 100
Req (kW)
Tleb (V)

80
240
60
190
40
140
20

90 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125

TEMPERATURE (C) TEMPERATURE (C)

Figure 19. Figure 20.

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 NCP1251

TYPICAL CHARACTERISTICS

4.8 3.4

3.3
4.6
3.2
4.4
3.1

Vlatch (V)
Iratio (−)

4.2 3

2.9
4
2.8
3.8
2.7

3.6 2.6
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125

TEMPERATURE (C) TEMPERATURE (C)

Figure 21. Figure 22.

100 100

80 80
trise (ns)

tfall (ns)

60 60

40 40

20 20

0 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125

TEMPERATURE (C) TEMPERATURE (C)

Figure 23. Figure 24.

11
35
10
30
9
8 25
7
Roh (W)
Rol (W)

20
6

5 15
4
10
3
2 5
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125

TEMPERATURE (C) TEMPERATURE (C)

Figure 25. Figure 26.

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 NCP1251

TYPICAL CHARACTERISTICS

14
100
13

80 12
Vovp_del (ms)

Vdrv_low (V)
60 11

10
40
9
20
8

0 7
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 27. Figure 28.

12.9
4.9
12.4

11.9
4.4
Vdrv_high (V)

11.4
TSS (ms)

10.9 3.9
10.4

9.9 3.4
9.4

8.9 2.9
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 29. Figure 30.

1.9
360
1.8

1.7 358
1.6
Vfold(CS) (mV)
Vfold(FB) (V)

356
1.5

1.4 354

1.3
352
1.2

1.1 350
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 31. Figure 32.

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 NCP1251

TYPICAL CHARACTERISTICS

0.41
390
0.39

0.37 340
Vfold_end (V)

Vskip (mV)
0.35
290

0.33
240
0.31

0.29 190
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125

TEMPERATURE (C) TEMPERATURE (C)

Figure 33. Figure 34.

390 1.7

1.5
340
Vfreeze(FB) (V)
Vfreeze (mV)

1.3
290
1.1

240
0.9

190 0.7
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125

TEMPERATURE (C) TEMPERATURE (C)

Figure 35. Figure 36.

160 3.5

150 3

140 2.5
TIMER (ms)

130 2
ICC (mA)

120 1.5

110 1

100 0.5
FSW = 65 kHz
90 0
−50 −25 0 25 50 75 100 125 0 0.5 1 1.5 2 2.5 3 3.5

TEMPERATURE (C) ADAPTER OUTPUT CURRENT (A)

Figure 37. Figure 38. Controller Consumption vs.
Adapter Output Current

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 NCP1251

TYPICAL CHARACTERISTICS

26.9

26.4

25.9

VOVP (V)
25.4

24.9

24.4

23.9
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 39.

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 NCP1251

APPLICATION INFORMATION

Introduction 26 kHz (typical) reached for a feedback level of

The NCP1251 implements a standard current mode roughly 350 mV. At this point, if the power continues to
architecture where the switch−off event is dictated by the drop, the controller enters classical skip−cycle mode.
peak current setpoint. This component represents the ideal  Internal soft−start: A soft−start precludes the main
candidate where low part−count and cost effectiveness are power switch from being stressed upon start−up. In this
the key parameters, particularly in low−cost ac−dc adapters, controller, the soft−start is internally fixed to 4 ms. The
open−frame power supplies etc. Capitalizing on the soft−start is activated when a new startup sequence
NCP120X series success, the NCP1251 packs all the occurs or during an auto−recovery hiccup.
necessary components normally needed in today modern
 OVP input: The NCP1251 includes a latch input
power supply designs, bringing several enhancements such
(pin 3) that can be used to sense an overvoltage
as a non−dissipative OPP.
condition on the adapter. If this pin is brought higher
 Current−mode operation with internal ramp than the internal reference voltage Vlatch, then the
compensation: Implementing peak current mode circuit permanently latches off. The VCC pin is pulled
control at a fixed 65 kHz or 100 kHz, the NCP1251 down to a fixed level, keeping the controller latched.
offers an internal ramp compensation signal that can The latch reset occurs when the user disconnects the
easily by summed with the sensed current. Sub adapter from the mains and lets the VCC falls below the
harmonic oscillations are eliminated via the inclusion of VCC reset.
a single resistor in series with the current−sense
 Latched OVP on VCC: It is sometimes interesting to
information.
implement a circuit protection by sensing the VCC
 Internal OPP: By routing a portion of the negative level. This is what the NCP1251 does by monitoring its
voltage present during the on−time on the auxiliary VCC pin. When the voltage on this pin exceeds 25 V
winding to the dedicated OPP pin (pin 3), the user has a typical, the pulses are immediately stopped and the part
simple and non−dissipative means to alter the latches off. The Vcc is maintained to 7 V typical and
maximum peak current setpoint as the bulk voltage remains in this state until the user unplugs the power
increases. If the pin is grounded, no OPP compensation supply.
occurs. If the pin receives a negative voltage down to
 Short−circuit protection: Short−circuit and especially
–250 mV, then a peak current reduction down to 31.3%
over−load protections are difficult to implement for
typical can be achieved. For an improved performance,
transformers with high leakage inductance between
the maximum voltage excursion on the sense resistor is
auxiliary and power windings (the aux winding level
limited to 0.8 V.
does not properly collapse in presence of an output
 Low startup current: Achieving a low no−load short). Here, every time the internal 0.8 V maximum
standby power always represents a difficult exercise peak current limit is activated (or less when OPP is
when the controller draws a significant amount of used), an error flag is asserted and a time period starts,
current during start−up. Due to its proprietary thanks to an internal timer. If the timer reaches
architecture, the NCP1251 is guaranteed to draw less completion while the error flag is still present, the
than 15 mA typical, easing the design of low standby controller stops the pulses and goes into a latch−off
power adapters. phase, operating in a low−frequency burst−mode. When
 EMI jittering: An internal low−frequency modulation the fault is cleared, the SMPS resumes operation.
signal varies the pace at which the oscillator frequency Please note that some versions offer an auto−recovery
is modulated. This helps by spreading out energy in mode as described and some latch off in case of a short
conducted noise analysis. To improve the EMI circuit.
signature at low power levels, the jittering remains
active in frequency foldback mode. Start−up Sequence
 Frequency foldback capability: A continuous flow of The NCP1251 start−up voltage is made purposely high to
pulses is not compatible with no−load/light−load permit a large energy storage in a small VCC capacitor value.
standby power requirements. To excel in this domain, This helps to operate with a small start−up current which,
the controller observes the feedback pin and when it together with a small VCC capacitor, will not hamper the
reaches a level of 1.5 V, the oscillator then starts to start−up time. To further reduce the standby power, the
reduce its switching frequency as the feedback level start−up current of the controller is extremely low, below
continues to decrease. When the feedback pin reaches 15 mA maximum. The start−up resistor can therefore be
1.05 V, the peak current setpoint is internally frozen and connected to the bulk capacitor or directly to the mains input
the frequency continues to decrease. It can go down to voltage to further reduce the power dissipation.

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 NCP1251
R3
200k
3

10
R2
200k

5
D2 D1
1N4007 1N4007
11
12 R1
200k

Cbulk
1 D6 D5
input 22uF
1N4148 1N4935
mains
VCC 2 4

D4 D3
1N4007 1N4007 aux.
C1 C3
4.7uF 47uF

Figure 40. The Startup Resistor Can Be Connected to the Input Mains for Further Power Dissipation Reduction

The first step starts with the calculation of the VCC This calculation is purely theoretical, and assumes a
capacitor which will supply the controller when it operates constant charging current. In reality, the take over time can
until the auxiliary winding takes over. Experience shows be shorter (or longer!) and it can lead to a reduction of the
that this time t1 can be between 5 ms and 20 ms. If we VCC capacitor. Hence, a decrease in charging current and an
consider we need at least an energy reservoir for a t1 time of increase of the start−up resistor, thus reducing the standby
10 ms, the VCC capacitor must be larger than: power. Laboratory experiments on the prototype are thus
I CCt 1 mandatory to fine tune the converter. If we chose the 413 kW
3m 10m
CV CC w w w 3.3 mF resistor as suggested by Equation 4, the dissipated power at
VCC on * VCC min 9 (eq. 1) high line amounts to:
Let us select a 4.7 mF capacitor at first and experiments in 2
the laboratory will let us know if we were too optimistic for V ac,peak 2 ǒ230 Ǹ2Ǔ

the time t1. The VCC capacitor being known, we can now P Rstart*up + +
4R start*up 4 413k
evaluate the charging current we need to bring the VCC (eq. 5)
voltage from 0 to the VCCon of the IC, 18 V typical. This
230 2
current has to be selected to ensure a start−up at the lowest + + 64 mW
0.827Meg
mains (85 V rms) to be less than 3 s (2.5 s for design margin):
Now that the first VCC capacitor has been selected, we
VCC onC VCC 18 4.7m
I charge w w w 34 mA must ensure that the self−supply does not disappear when in
2.5 2.5 (eq. 2) no−load conditions. In this mode, the skip−cycle can be so
If we account for the 15 mA that will flow inside the deep that refreshing pulses are likely to be widely spaced,
controller, then the total charging current delivered by the inducing a large ripple on the VCC capacitor. If this ripple is
start−up resistor must be 49 mA. If we connect the start−up too large, chances exist to touch the VCCmin and reset the
network to the mains (half−wave connection then), we know controller into a new start−up sequence. A solution is to
that the average current flowing into this start−up resistor grow this capacitor but it will obviously be detrimental to the
will be the smallest when VCC reaches the VCCon of the start−up time. The option offered in Figure 40 elegantly
controller: solves this potential issue by adding an extra capacitor on the
auxiliary winding. However, this component is separated
V ac,rmsǸ2
p * VCC on from the VCC pin via a simple diode. You therefore have the
I CVCC,min + (eq. 3)
ability to grow this capacitor as you need to ensure the
R start*up
self−supply of the controller without jeopardizing the
To make sure this current is always greater than 49 mA, start−up time and standby power. A capacitor ranging from
then the minimum value for Rstart−up can be extracted: 22 to 47 mF is the typical value for this device.
V ac,rmsǸ2
85 1.414
One note on the start-up current. If reducing it helps to
p * VCC on p * 18 improve the standby power, its value cannot fall below a
R start*up v v v 413.5 kW
I CVCC,min 49m (eq. 4)
certain level at the minimum input voltage. Failure to inject

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15
 NCP1251

enough current (30 mA) at low line will turn a converter in the current−sense offset. A way to reduce the power
fault into an auto-recovery mode since the SCR won’t capability at high line is to capitalize on the negative voltage
remain latched. To build a sufficient design margin, we swing present on the auxiliary diode anode. During the
recommend to keep at least 60 mA flowing at the lowest input power switch on−time, this point dips to −NVin, N being the
line (80 V rms for 85 V minimum for instance). An excellent turns ratio between the primary winding and the auxiliary
solution is to actually combine X2 discharge and start-up winding. The negative plateau observed on Figure 42 will
networks as proposed in Figure 13 of application note have an amplitude dependant on the input voltage. The idea
AND8488/D. implemented in this chip is to sum a portion of this negative
swing with the 0.8 V internal reference level. For instance,
Internal Over Power Protection if the voltage swings down to −150 mV during the on time,
There are several known ways to implement Over Power then the internal peak current set point will be fixed to 0.8 −
Protection (OPP), all suffering from particular problems. 0.150 = 650 mV. The adopted principle appears in Figure 42
These problems range from the added consumption burden and shows how the final peak current set point is
on the converter or the skip−cycle disturbance brought by constructed.

1 v(24)

40.0

off−time

20.0 N1(Vout +Vf)

1
v(24) (V)

−20.0 −N2Vbulk

on−time
−40.0

464u 472u 480u 488u 496u

time (s)
Figure 41. The Signal Obtained on the Auxiliary Winding Swings Negative During the On−time

Let’s assume we need to reduce the peak current from level, then the negative voltage developed on the OPP pin
2.5 A at low line, to 2 A at high line. This corresponds to a must reach:
20% reduction or a set point voltage of 640 mV. To reach this V OPP + 640m * 800m + −160 mV (eq. 6)

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16
 NCP1251

RoppU

VCC swings to:

aux Vout during toff
−N V in during ton

This p oin t will

be adjusted to
reduce the ref
at hi line to the
desired level.
from FB
VDD reset

K1 SUM2 −
OPP ref CS
K2
+
Io p p
0.8 V
$5%
R oppL
ref = 0.8 V + VOPP

(V O P P is negativ e)

Figure 42. The OPP Circuitry Affects the Maximum Peak Current Set Point by Summing a Negative Voltage to the
Internal Voltage Reference

Let us assume that we have the following converter 0.16

Div + [ 2.4m (eq. 8)
characteristics: 67.5
Vout = 19 V If we arbitrarily fix the pull−down resistor ROPPL to 1 kW,
Vin = 85 to 265 Vrms then the upper resistor can be obtained by:
N1 = Np:Ns = 1:0.25 67.5 * 0.16
N2 = Np:Naux = 1:0.18 R OPPU + [ 421 kW (eq. 9)
0.16ń1k
Given the turns ratio between the primary and the auxiliary If we now plot the peak current set point obtained by
windings, the on−time voltage at high line (265 Vac) on the implementing the recommended resistor values, we obtain
auxiliary winding swings down to: the following curve (Figure 43):
V aux + −N 2V in,max + −0.18 375 + −67.5 V (eq. 7)

To obtain a level as imposed by Equation 6, we need to

install a divider featuring the following ratio:

Peak current
setpoint

100%

80%

Vbulk
375
Figure 43. The Peak Current Regularly Reduces Down to 20% at 375 Vdc

The OPP pin is surrounded by Zener diodes stacked to clamped slightly below –300 mV which means that if more
protect the pin against ESD pulses. These diodes accept current is injected before reaching the ESD forward drop,
some peak current in the avalanche mode and are designed then the maximum peak reduction is kept to 40%. If the
to sustain a certain amount of energy. On the other side, voltage finally forward biases the internal zener diode, then
negative injection into these diodes (or forward bias) can care must be taken to avoid injecting a current beyond
cause substrate injection which can lead to an erratic circuit –2 mA. Given the value of ROPPU, there is no risk in the
behavior. To avoid this problem, the pin is internally present example.

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17
 NCP1251

Finally, please note that another comparator internally to reduce the operating frequency down to 26 kHz. This
fixes the maximum peak current set point to 0.8 V even if the value is reached at a voltage feedback level of 350 mV
OPP pin is inadvertently biased above 0 V. typically. Below this point, if the output power continues to
decrease, the part enters skip cycle for the best noise−free
Frequency Foldback performance in no−load conditions. Figure 44 depicts the
The reduction of no−load standby power associated with adopted scheme for the part.
the need for improving the efficiency, requires a change to The NCP1251F version offers a means to improve
the traditional fixed−frequency type of operation. This light−load efficiency by folding the switching frequency
controller implements a switching frequency foldback when sooner compared to the other versions. With the 1251 A, B
the feedback voltage passes below a certain level, Vfold, set and C versions, the minimum frequency is reached for VFB
around 1.5 V. At this point, the oscillator enters frequency equals 350 mV. With the 1251F, this minimum frequency
foldback and reduces its switching frequency. The peak will be obtained at a feedback voltage equal to 1.5 V,
current setpoint follows the feedback pin until its level naturally offering a better efficiency for lighter load
reaches 1.05 V. Below this value, the peak current freezes to conditions. Figure 45 portrays the specific foldback scheme
Vfold/4.2 (250 mV or 31% of the maximum 0.8 V setpoint) implemented in the NCP1251F.
and the only way to further reduce the transmitted power is

Frequency Peak current setpoint

Fsw VCS

FB 65 kHz
max
max
0.8 V

[ 0.36 V
min
26 kHz min
[ 0.25 V
VFB VFB
350 mV 1.5 V 3.4 V Vfreeze Vfold 3.4 V
Vfold,end Vfold 1.05 V 1.5 V

Figure 44. By Observing the Voltage on the Feedback Pin, the Controller Reduces its Switching Frequency for an
Improved Performance at Light Load

Figure 45. with NCP1251F, the frequency foldback occurs sooner as the load gets lighter.

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18
 NCP1251

Auto−Recovery Short−Circuit Protection due to the resistive starting network. When VCC reaches
In case of output short−circuit or if the power supply VCCON, the controller attempts to re−start, checking for the
experiences a severe overloading situation, an internal error absence of the fault. If the fault is still there, the supply enters
flag is raised and starts a countdown timer. If the flag is another cycle of so−called hiccup mode. If the fault has
asserted longer than 100 ms, the driving pulses are stopped cleared, the power supply resumes normal operation. Please
and the VCC pin slowly goes down to around 7 V. At this note that the soft−start is activated during each of the re−start
point, the controller wakes−up and the VCC builds up again sequence.

1 vcc 2 vdrv 3 ilprim

23.6 15.9 4.32

Vcc (t)

14.8 9.90 3.35

VDRV (t)
ilprim in amperes
vdrv in volts

vcc in volts
Plot1

6.05 3.89 2.38

−2.72 −2.12 1.41

SS ILp (t)
−11.5 −8.13 445m

3
500u 1.50m 2.50m 3.50m 4.50m
time in seconds

Figure 46. An Auto−Recovery Hiccup Mode is Activated for Faults Longer than 100 ms

Slope Compensation converters. These oscillations take place at half the

The NCP1251 includes an internal ramp compensation switching frequency and occur only during CCM with a
signal. This is the buffered oscillator clock delivered only duty−cycle greater than 50%. To lower the current loop gain,
during the on time. Its amplitude is around 2.5 V at the one usually injects between 50% and 100% of the inductor
maximum duty−cycle. Ramp compensation is a known downslope. Figure 47 depicts how internally the ramp is
means used to cure sub harmonic oscillations in Continuous generated. Please note that the ramp signal will be
Conduction Mode (CCM) operated current−mode disconnected from the CS pin, during the off time.

2.5 V

0V

ON

latch
reset 20k
Rcomp
+ LEB
CS
− Rsense

from FB
setpoint
Figure 47. Inserting a Resistor in Series with the Current Sense Information Brings Ramp Compensation and
Stabilizes the Converter in CCM Operation.

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19
 NCP1251

In the NCP1251 controller, the oscillator ramp features a pin to the controller ground for an improved immunity to the
2.5 V swing reached at a 80% duty−ratio. If the clock noise. Please make sure both components are located very
operates at a 65 kHz frequency, then the available oscillator close to the controller.
slope corresponds to:
Latching Off the Controller
V ramp,peak 2.5 The OPP pin not only allows a reduction of the peak
S ramp + +
D maxT SW 0.8 15m (eq. 10) current set point in relationship to the line voltage, it also
offers a means to permanently latch−off the part. When the
+ 208 kVńs or 208 mVńms part is latched−off, the VCC pin is internally pulled down to
In our flyback design, let’s assume that our primary around 7 V and the part stays in this state until the user cycles
inductance Lp is 770 mH, and the SMPS delivers 19 V with the VCC down and up again, e.g. by un−plugging the
a Np :Ns ratio of 1:0.25. The off−time primary current slope converter from the mains outlet. It is important to note that
Sp is thus given by: the SCR maintains its latched state as long as the injected
N current stays above the minimum value of 30 mA. As the
ǒVout ) VfǓ Nps (19 ) 0.8) 4 SCR delatches for an injected current below this value, it is
Sp + + + 103 kAńs the designer duty to make sure the injected current is high
Lp 770m (eq. 11)
enough at the lowest input voltage. Failure to maintain a
Given a sense resistor of 330 mW, the above current ramp sufficiently high current would make the device auto
turns into a voltage ramp of the following amplitude:
recover. A good design practice is to ensure at least 60 mA
S sense + S pR sense + 103k 0.33 at the lowest input voltage. The latch detection is made by
(eq. 12)
+ 34 kVńs or 34 mVńms observing the OPP pin by a comparator featuring a 3 V
If we select 50% of the downslope as the required amount reference voltage. However, for noise reasons and in
of ramp compensation, then we shall inject a ramp whose particular to avoid the leakage inductance contribution at
slope is 17 mV/ms. Our internal compensation being of turn off, a 1 ms blanking delay is introduced before the
208 mV/ms, the divider ratio (divratio) between Rcomp and output of the OVP comparator is checked. Then, the OVP
comparator output is validated only if its high−state duration
the internal 20 kW resistor is:
lasts a minimum of 600 ns. Below this value, the event is
17m ignored. Then, a counter ensures that 4 successive OVP
divratio + + 0.082 (eq. 13)
208m events have occurred before actually latching the part. There
The series compensation resistor value is thus: are several possible implementations, depending on the
R comp + R ramp @ divratio + 20k 0.082 [ 1.6 kW needed precision and the parameters you want to control.
(eq. 14) The first and easiest solution is the additional resistive
A resistor of the above value will then be inserted from the divider on top of the OPP one. This solution is simple and
sense resistor to the current sense pin. We recommend inexpensive but requires the insertion of a diode to prevent
adding a small capacitor of 100 pF, from the current sense disturbing the OPP divider during the on time.

D2
R3
1N4148
5k

11

RoppU
421k

VCC
9 8
OP P
aux.
winding
10 4
1
ROPPL
C1 1k 5
100p
OVP OPP
Vlatch

Figure 48. A Simple Resistive Divider Brings the OPP Pin Above 3 V in Case of a VCC Voltage Runaway above
18 V

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20
 NCP1251

First, calculate the OPP network with the above equations. V latch * V VOP 18 * 3 15
Then, suppose we want to latch off our controller when Vout R OVP + + + + 5 kW (eq. 16)
V OVPńR OPPL 3ń1k 3m
exceeds 25 V. On the auxiliary winding, the plateau reflects
the output voltage by the turns ratio between the power and In nominal conditions, the plateau establishes to around
the auxiliary winding. In case of voltage runaway for our 14 V. Given the divide−by−6 ratio, the OPP pin will swing
19 V adapter, the plateau will go up to: to 14/6 = 2.3 V during normal conditions, leaving 700 mV
margin. A 100 pF capacitor can be added between the OPP
0.18
V aux,OVP + 25 + 18 V (eq. 15) pin and GND to improve noise immunity and avoid erratic
0.25 trips in presence of external surges. Do not increase this
Since our OVP comparator trips at a 3 V level, across the capacitor too much otherwise the OPP signal will be affected
1 kW selected OPP pulldown resistor, it implies a 3 mA by the integrating time constant.
current. From 3 V to go up to 18 V, we need an additional A second solution for the OVP detection alone, is to use
15 V. Under 3 mA and neglecting the series diode forward a Zener diode wired as recommended by.
drop, it requires a series resistor of:

D3 D2
15V 1N4148

11
ROPPU
421k

VCC
9 8
OPP aux.
winding
10 4

ROPPL 1
1k
C1 5
22pF
OVP OPP
Vlatch

Figure 49. A Zener Diode in Series with a Diode Helps to Improve the Noise Immunity of the System

For this configuration to maintain an 18 V level, we have probe connections!) and check that enough margin exists to
selected a 15 V Zener diode. In nominal conditions, the that respect.
voltage on the OPP pin is almost 0 V during the off time as
the Zener is fully blocked. This technique clearly improves Over Temperature Protection
the noise immunity of the system compared to that obtained In a lot of designs, the adapter must be protected against
from a resistive string as in Figure 48. Please note the thermal runaways, e.g. when the temperature inside the
reduction of the capacitor on the OPP pin to 10 pF − 22 pF. adapter box increases above a certain value. Figure 50
This capacitor is necessary because of the potential spike shows how to implement a simple OTP using an external
coupling through the Zener parasitic capacitance from the NTC and a series diode. The principle remains the same:
bias winding due to the leakage inductance. Despite the 1 ms make sure the OPP network is not affected by the additional
blanking delay at turn off. This spike is energetic enough to NTC hence the presence of this isolation diode. When the
charge the added capacitor C1 and given the time constant, NTC resistance decreases as the temperature increases, the
could make it discharge slower, potentially disturbing the voltage on the OPP pin during the off time will slowly
blanking circuit. When implementing the Zener option, it is increase and, once it passes 3 V for 4 consecutive clock
important to carefully observe the OPP pin voltage (short cycles, the controller will permanently latch off.

www.onsemi.com
21
 NCP1251

D2
NT C 1N4148

ROPPU
841k

VCC

OP P au x.
winding

ROPPL
2.5k

full−latch OPP
Vlatch

Figure 50. The Internal Circuitry Hooked to Pin 3 Can Be Used to Implement Over Temperature Protection (OTP)

Back to our 19 V adapter, we have found that the plateau limit at the chosen output power level. Suppose we need a
voltage on the auxiliary diode was 13 V in nominal 200 mV decrease from the 0.8 V set point and the on−time
conditions. We have selected an NTC which offers a swing on the auxiliary anode is −67.5 V, then we need to drop
resistance of 470 kW at 25C and drops to 8.8 kW at 110C. over ROPPU a voltage of:
If our auxiliary winding plateau is 14 V and we consider a V ROPPU + 67.5 * 0.2 + 67.3 V (eq. 20)
0.6 V forward drop for the diode, then the voltage across the
NTC in fault mode must be: The current flowing in the pulldown resistor ROPPL in this
V NTC + 14 * 3 * 0.6 + 10.4 V
condition will be:
(eq. 17)
200m
Based on the 8.8 kW NTC resistor at 110 C, the current I ROPPU + + 80 mA (eq. 21)
through the device must be: 2.5k

10.4 The ROPPU value is therefore easily derived:

I NTC + [ 1.2 mA (eq. 18)
8.8k 67.3
R OPPU + + 841 kW (eq. 22)
As such, the bottom resistor ROPPL, can easily be 80m
calculated:
Combining OVP and OTP
3
R OPPL + + 2.5 kW (eq. 19) The OTP and Zener−based OVP can be combined
1.2m together as illustrated by Figure 51.
Now that the pulldown OPP resistor is known, we can
calculate the upper resistor value ROPPU to adjust the power

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22
 NCP1251

D3
15V

D2
NT C 1N4148

11

ROPPU
841k

VCC
9 8
OPP au x.
winding
10 4

ROPPL 1
2.5k
5

OVP OPP
Vlatch

Figure 51. With the NTC Back in Place, the Circuit Nicely Combines OVP, OTP and OPP on the Same Pin

In nominal VCC / output conditions, when the Zener is not network. Typical values are those given in Figure 52 and
activated, the NTC can drive the OPP pin and trigger the must be selected to provide the adequate filtering function
adapter in case of an over temperature. During nominal without degrading the stand−by power by an excessive
temperature if the loop is broken, the voltage runaway will current circulation.
be detected and the controller will shut down the converter.
In case the OPP pin is not used for either OPP or OVP, it Latched OVP on VCC
can simply be grounded. The VCC pin is permanently monitored by a comparator.
When the VCC exceeds 25.5 V (typical), all pulses are
Filtering the Spikes immediately stopped and the VCC falls to the SCR
The auxiliary winding is the seat of spikes that can couple latched-level around 7 V typical. The controller remains in
to the OPP pin via the parasitic capacitances exhibited by the this state as long as a sufficient current flows in the SCR, at
Zener diode and the series diode. To prevent an adverse least 30 mA. We recommend to put a design margin there,
triggering of the Over Voltage Protection circuitry, it is with a minimum current around 60 mA at the lowest input
possible to install a small RC filter before the detection line. With the C version, the OVP on VCC is autorecovery.

D3 ad d ition al fil ter

15V

D2
NT C 1N4148

11 2
C1
ROPPU R3
330pF
841k 220

VCC
9 3
OP P aux.
winding
10 4
ROPPL 1
2.5k
5

OVP OPP
Vlatch

Figure 52. A Small RC Filter Avoids the Fast Rising Spikes from Reaching the Protection Pin of the NCP1251 in
Presence of Energetic Perturbations Superimposed on the Input Line

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23
 MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

TSOP−6 3.00x1.50x0.90, 0.95P

CASE 318G
ISSUE W
DATE 26 FEB 2024

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB14888C Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: TSOP−6 3.00x1.50x0.90, 0.95P PAGE 1 OF 2

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 TSOP−6 3.00x1.50x0.90, 0.95P
CASE 318G
ISSUE W
DATE 26 FEB 2024

GENERIC
MARKING DIAGRAM*

XXXAYWG XXX MG
G G
1 1
IC STANDARD
XXX = Specific Device Code XXX = Specific Device Code
A =Assembly Location M = Date Code
Y = Year G = Pb−Free Package
W = Work Week
G = Pb−Free Package
*This information is generic. Please refer to device data
sheet for actual part marking. Pb−Free indicator, “G”
or microdot “G”, may or may not be present. Some
products may not follow the Generic Marking.

STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: STYLE 6:

PIN 1. DRAIN PIN 1. EMITTER 2 PIN 1. ENABLE PIN 1. N/C PIN 1. EMITTER 2 PIN 1. COLLECTOR
2. DRAIN 2. BASE 1 2. N/C 2. V in 2. BASE 2 2. COLLECTOR
3. GATE 3. COLLECTOR 1 3. R BOOST 3. NOT USED 3. COLLECTOR 1 3. BASE
4. SOURCE 4. EMITTER 1 4. Vz 4. GROUND 4. EMITTER 1 4. EMITTER
5. DRAIN 5. BASE 2 5. V in 5. ENABLE 5. BASE 1 5. COLLECTOR
6. DRAIN 6. COLLECTOR 2 6. V out 6. LOAD 6. COLLECTOR 2 6. COLLECTOR

STYLE 7: STYLE 8: STYLE 9: STYLE 10: STYLE 11: STYLE 12:

PIN 1. COLLECTOR PIN 1. Vbus PIN 1. LOW VOLTAGE GATE PIN 1. D(OUT)+ PIN 1. SOURCE 1 PIN 1. I/O
2. COLLECTOR 2. D(in) 2. DRAIN 2. GND 2. DRAIN 2 2. GROUND
3. BASE 3. D(in)+ 3. SOURCE 3. D(OUT)− 3. DRAIN 2 3. I/O
4. N/C 4. D(out)+ 4. DRAIN 4. D(IN)− 4. SOURCE 2 4. I/O
5. COLLECTOR 5. D(out) 5. DRAIN 5. VBUS 5. GATE 1 5. VCC
6. EMITTER 6. GND 6. HIGH VOLTAGE GATE 6. D(IN)+ 6. DRAIN 1/GATE 2 6. I/O

STYLE 13: STYLE 14: STYLE 15: STYLE 16: STYLE 17:
PIN 1. GATE 1 PIN 1. ANODE PIN 1. ANODE PIN 1. ANODE/CATHODE PIN 1. EMITTER
2. SOURCE 2 2. SOURCE 2. SOURCE 2. BASE 2. BASE
3. GATE 2 3. GATE 3. GATE 3. EMITTER 3. ANODE/CATHODE
4. DRAIN 2 4. CATHODE/DRAIN 4. DRAIN 4. COLLECTOR 4. ANODE
5. SOURCE 1 5. CATHODE/DRAIN 5. N/C 5. ANODE 5. CATHODE
6. DRAIN 1 6. CATHODE/DRAIN 6. CATHODE 6. CATHODE 6. COLLECTOR

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB14888C Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: TSOP−6 3.00x1.50x0.90, 0.95P PAGE 2 OF 2

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com
2
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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