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Mux Ra1911004010178

This lab report documents the design of 4x1 and 8x1 multiplexers. The objectives were to design a 4x1 multiplexer using basic gates like AND, OR, and NOT. The procedure explained designing a 4x1 multiplexer by connecting 4 AND gates to 4 inputs, connecting 2 selection lines with NOT gates, and connecting the AND gates to an OR gate for the single output Y. Screenshots showed the 4x1 multiplexer design in Logisim. Pre-lab and post-lab questions covered multiplexer concepts like selecting data inputs, the relationship between multiplexers and demultiplexers, implementing multiplexers using other multiplexers, and applications of multiplexers and demultiplex

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Shivanshu Tripathi
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177 views10 pages

Mux Ra1911004010178

This lab report documents the design of 4x1 and 8x1 multiplexers. The objectives were to design a 4x1 multiplexer using basic gates like AND, OR, and NOT. The procedure explained designing a 4x1 multiplexer by connecting 4 AND gates to 4 inputs, connecting 2 selection lines with NOT gates, and connecting the AND gates to an OR gate for the single output Y. Screenshots showed the 4x1 multiplexer design in Logisim. Pre-lab and post-lab questions covered multiplexer concepts like selecting data inputs, the relationship between multiplexers and demultiplexers, implementing multiplexers using other multiplexers, and applications of multiplexers and demultiplex

Uploaded by

Shivanshu Tripathi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Course Code : 18ECC103J Course Title : Digital Electronic Principles

Reg. No. : Name : Shivanshu Tripathi


RA1911004010178
Semester : III Semester Year : II Year
Date of Expt. : 16-9-2020 Date of Submission : 24-10-2020
Name of the Lab Instructor : Saraswathy maam

Title of the Experiment


Design 4X1 and 8X1 Multiplexer .

Aim(s) / Objective(s) / Purpose

1. To design 4X1 Multiplexer using basic gates.

Materials / Equipment
.
1. AND gate , OR gate , NOT gate .
2. Wire
3. Plexer

Procedure

4X1-
1.Connect 4 AND gates to 4 inputs
2.Connect 2 selection lines along with NOT gates .
3.Now connect all four AND gates to and OR gate .
4.This gives the single out Y.

LOGISIM SCREENSHOT
.
4X1-

PRE LAB QUESTIONS

1. Multiplexer is also called a data selector. Why?


A) The multiplexer is sometimes called a data selector because it
selects which data input is to be sent to the data output.
2. Justify, Demultiplexer is a data distributor.
A) The word demultiplex means “one into many” and distributor. A
demultiplexer sends a single input to multiple outputs, depending on
the select lines. It is clear from the diagram:

3. A certain multiplexer can switch one of 32 data inputs to its


output. How many select inputs does this MUX have?
A)2^n=32.This implies n=5
4. Implement a 4:1 using 2:1 MUX only.
5. Implement a 16:1 multiplexer using two 8:1 multiplexer
POSTLAB QUESTIONS
1. Implement the following Boolean expression using 8:1
multiplexers : F(A,B,C,D)= Σ(0,1,3,4,8,9,15)
2. Draw the block diagram of 1x4 DeMUX . Draw its truth table.

3. Implement a Full Adder using two 8-to-1 MUX.


4. Implement a Full Adder using two 4-to-1 MUX and one
inverter.

5. Show how two 4-to-1 and one 2-to-1 MUX could be connected to
form an 8-to-1 MUX.
6. Show how two 2-to-1 MUX (with no added gates) could be
connected to form a 3-to 1 MUX. Input selection should be as
follows.
If AB=00, Select I0
If AB=01, Select I1
If AB=1X, Select I2

7. How can a decoder be used as a demultiplexer?


A) A decoder with an enable input can function as a Demultiplexer. A demultiplexer is a
circuit that receives information on a single line and transmits this information on one of 2n
possible output lines. Selection of a specific output line is controlled by the bit values of n
selection lines.

8. What are the applications of MUX and DEMUX?


A)i)Communication system
ii)Arithmetic logic unit
iii)parallel and Series conversion

Results and Conclusion


Therefore the designing of 4X1 mux is understood using basic gates and in built
function and required output are derived as in the given truth table.

References
1. https://www.tutorialspoint.com/digital_circuits/digital_circuits_multiplexers.htm

DO NOT USE PERSONAL PRONOUNS!


(This includes: me, my, I, our, us, they, her, she, he, them, etc.)

THIS LAB REPORT MUST BE TYPED IN ORDER TO RECEIVE CREDIT

-RA1911004010178

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