DL129/D

Rev. 7, Mar-2000

High-Speed CMOS Data

ON Semiconductor
ON Semiconductor

High-Speed CMOS Data

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further
notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC
products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of
the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

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EUROPE: LDC for ON Semiconductor - European Support JAPAN: ON Semiconductor, Japan Customer Focus Center
German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549
Email: ONlit-german@hibbertco.com Phone: 81-3-5740-2745
French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: r14525@onsemi.com
Email: ONlit-french@hibbertco.com
English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) ON Semiconductor Website: http://onsemi.com
Email: ONlit@hibbertco.com

EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 For additional information, please contact your local Sales
*Available from Germany, France, Italy, England, Ireland Representative

DL129/D 03/00
DL129
REV 7
 High–Speed CMOS Data

DL129/D
Rev. 7, Mar–2000

 SCILLC, 2000
Previous Edition  1996
“All Rights reserved”
 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment: CENTRAL/SOUTH AMERICA:
Literature Distribution Center for ON Semiconductor Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
P.O. Box 5163, Denver, Colorado 80217 USA Email: ONlit–spanish@hibbertco.com
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Email: ONlit@hibbertco.com Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada Toll Free from Hong Kong & Singapore:
001–800–4422–3781
N. American Technical Support: 800–282–9855 Toll Free USA/Canada Email: ONlit–asia@hibbertco.com

EUROPE: LDC for ON Semiconductor – European Support JAPAN: ON Semiconductor, Japan Customer Focus Center
German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time) 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549
Email: ONlit–german@hibbertco.com Phone: 81–3–5740–2745
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time) Email: r14525@onsemi.com
Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time) ON Semiconductor Website: http://onsemi.com
Email: ONlit@hibbertco.com

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 For additional information, please contact your local
*Available from Germany, France, Italy, England, Ireland Sales Representative.

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 Table of Contents
Chapter 1. Function Selector Guide Thermal Management . . . . . . . . . . . . . . . . . . . . . . . 41
Capacitive Loading Effects on
Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . 6 Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Buffers/Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Temperature Effects on DC and AC
Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Schmitt Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Supply Voltage Effects on Drive Current
Bus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 and Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . 44
Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . 45
Flip–Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Digital Data Selectors/Multiplexers . . . . . . . . . . . . . 16 Typical Parametric Values . . . . . . . . . . . . . . . . . . . . 48
Decoders/Demultiplexers/Display Drivers . . . . . . . 17 Reduction of Electromagnetic
Analog Switches/Multiplexers/ Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Hybrid Circuit Guidelines . . . . . . . . . . . . . . . . . . . . . 49
Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Schmitt–Trigger Devices . . . . . . . . . . . . . . . . . . . . . 50
Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Oscillator Design with High–Speed CMOS . . . . . . 51
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 51
Chapter 2. Design Considerations Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . 52
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Definitions and Glossary of Terms . . . . . . . . . . . 53
HC vs. HCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Handling Precautions . . . . . . . . . . . . . . . . . . . . . . . . 24
Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . 53
Power Supply Sizing . . . . . . . . . . . . . . . . . . . . . . . . . 28
Applications Assistance Form . . . . . . . . . . . . . . 56
Battery Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CPD Power Calculation . . . . . . . . . . . . . . . . . . . 29 Chapter 3. Device Datasheets
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3–State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Open–Drain Outputs . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 4. Application Notes
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Bus Termination . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Transmission Line Termination . . . . . . . . . . . . . 37 Chapter 5. Ordering Information
CMOS Latch Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 398
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . 40 Case Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
HC Quiescent Power Dissipation . . . . . . . . . . . 40 ON Semiconductor Major Worldwide
HCT Quiescent Power Dissipation . . . . . . . . . . 40 Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
HC and HCT Dynamic Power Dissipation . . . . 40 Document Definitions . . . . . . . . . . . . . . . . . . . . . . 406

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 CHAPTER 1
Function Selector Guide

Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . 6
Buffers/Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Schmitt Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . 12
Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flip–Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Digital Data Selectors/Multiplexers . . . . . . . . . . 16
Decoders/Demultiplexers/Display Drivers . . . . 17
Analog Switches/Multiplexers/
Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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 ALPHANUMERIC INDEX
Page
Device Number Function Number

MC74HC00A Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

MC74HC02A Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
MC74HC03A Quad 2–Input NAND Gate With Open–Drain Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
MC74HC04A Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
MC74HCT04A Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
MC74HCU04A Hex Unbuffered Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
MC74HC08A Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
MC74HC14A Hex Schmitt Trigger Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MC74HCT14A Hex Schmitt Trigger Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MC74HC32A Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
MC74HC74A Dual D Flip–Flop With Set and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
MC74HCT74A Dual D Flip–Flop With Set and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MC74HC86A Quad 2–Input Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
MC74HC125A Quad With 3–State Outputs Non–Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
MC74HC126A Quad With 3–State Outputs Non–Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
MC74HC132A Quad 2–Input NAND Gate With Schmitt Trigger Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
MC74HC138A 1–of–8 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MC74HCT138A 1–of–8 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MC74HC139A Dual 1–of–4 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
MC74HC157A Quad 2–Input Data Selector/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
MC74HC161A Presettable Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
MC74HC163A Presettable Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
MC74HC164A 8–Bit Serial–Input/Parallel–Output Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
MC74HC165A 8–Bit Serial or Parallel–Input/Serial–Output Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
MC74HC174A Hex D Flip–Flop With Common Clock & Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
MC74HC175A Quad D Flip–Flop With Common Clock & Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
MC74HC240A Octal With 3–State Outputs Inverting Buffer/Line Driver/line Receiver . . . . . . . . . . . . . . . . . 175
MC74HC244A Octal With 3–State Outputs Non–Inverting Buffer/Line Driver/Line Receiver . . . . . . . . . . . 180
MC74HCT244A Octal With 3–State Outputs Non–Inverting Buffer/Line Driver/Line Receiver . . . . . . . . . . . 185
MC74HC245A Octal With 3–State Outputs Non–Inverting Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 189
MC74HCT245A Octal With 3–State Outputs Non–Inverting Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 194
MC74HC273A Octal D Flip–Flop With Common Clock & Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
MC74HCT273A Octal D Flip–Flop With Common Clock & Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
MC74HC373A Octal With 3–State Outputs Non–Inverting Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . 208
MC74HCT373A Octal With 3–State Outputs Non–Inverting Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . 214
MC74HC374A Octal With 3–State Outputs Non–Inverting D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
MC74HCT374A Octal With 3–State Outputs Non–Inverting D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
MC74HC390A Dual 4–Stage Binary Ripple Counter W ÷2, ÷5 Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
MC74HC393A Dual 4–Stage Binary Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
MC74HC540A Octal With 3–State Outputs Inverting Buffer/Line Driver/Line Receiver . . . . . . . . . . . . . . . . 242
MC74HC541A Octal With 3–State Outputs Non–Inverting Buffer/Line Driver/Line Receiver . . . . . . . . . . . 246
MC74HCT541A Octal With 3–State Outputs Non–Inverting Buffer/Line Driver/Line Receiver . . . . . . . . . . . 250
MC74HC573A Octal With 3–State Outputs Non–Inverting Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . 254
MC74HCT573A Octal With 3–State Outputs Non–Inverting Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . 260
MC74HC574A Octal With 3–State Outputs Non–Inverting D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
MC74HCT574A Octal With 3–State Outputs Non–Inverting D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
MC74HC589A 8–Bit Serial or Parallel–Input/Serial–Output Shift Register With 3–State Outputs . . . . . . . 276
MC74HC595A 8–Bit Serial–Input/Serial or Parallel–Output Shift Register With Latched 3–State Outputs 285
MC74HC4020A 14–Stage Binary Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
MC74HC4040A 12–Stage Binary Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
MC74HC4046A Phase–Locked–Loop With VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

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 ALPHANUMERIC INDEX
Page
Device Number Function Number

MC74HC4051A 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

MC74HC4052A Dual 4–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
MC74HC4053A Triple 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
MC74HC4060A 14–Stage Binary Ripple Counter With Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
MC74HC4066A Quad Analog Switch/Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
MC74HC4316A Quad Analog Switch/Multiplexer/Demultiplexer With Separate Analog/
Digital Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
MC74HC4538A Dual Precision Monostable Multivibrator Retriggerable, Resettable) . . . . . . . . . . . . . . . . . . 360
MC74HC4851A Analog Multiplexer/Demultiplexer with Injection Current Effect Control . . . . . . . . . . . . . . . . 371
MC74HC4852A Analog Multiplexer/Demultiplexer with Injection Current Effect Control . . . . . . . . . . . . . . . . 371

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 BUFFERS/INVERTERS
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Functional
Functional
Equivalent

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Equivalent CMOS
Device LSTTL Device Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Number

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC74 ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Function
Device
74
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
of
Pins

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC04A Hex Inverter LS04 *4069 LS/CMOS 14

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HCT04A Hex Inverter with LSTTL–Compatible Inputs LS04 *4069 LS/CMOS 14
HCU04A Hex Unbuffered Inverter LS04 4069 LS/CMOS 14

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HC14A

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HCT14A ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Hex Schmitt–Trigger Inverter

ÎÎÎÎÎ
ÎÎÎ
Hex Schmitt–Trigger Inverter with LSTTL–Compatible
LS14
LS14
4584
4584
LS/CMOS
LS/CMOS
14
14

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Inputs

ÎÎÎÎÎ
HC125A
HC126A ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Quad 3–State Noninverting Buffer
Quad 3–State Noninverting Buffer
LS125,LS125A
LS126,LS126A
LS
LS
14
14

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC240A Octal 3–State Inverting Buffer/Line Driver/Line Receiver LS240 LS 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HC244A

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HCT244A
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
Receiver
ÎÎÎ
Octal 3–State Noninverting Buffer/Line Driver/Line

ÎÎÎÎÎ
ÎÎÎ
Octal 3–State Noninverting Buffer/Line Driver/Line
LS244

LS244
LS

LS
20

20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
HC245A ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Receiver with LSTTL–Compatible Inputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
Octal 3–State Noninverting Bus Transceiver LS245 LS 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HCT245A Octal 3–State Noninverting Bus Transceiver with LS245 LS 20
LSTTL–Compatible Inputs

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HC540A
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Octal 3–State Inverting Buffer/Line Driver/Line Receiver 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HC541A

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
Receiver ÎÎÎ
Octal 3–State Noninverting Buffer/Line Driver/Line

ÎÎÎÎÎ
ÎÎÎ
LS541 LS 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HCT541A Octal 3–State Noninverting Buffer/Line Driver/Line LS541 LS 20
Receiver with LSTTL–Compatible Inputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
HC Devices Have CMOS–Compatible Inputs. HCT Devices Have LSTTL–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
HC HC HC
HCT HCU HC HC HC HC HCT HCT

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
# Pins ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
Device

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
04A
14
04A
14
14A
14
125A
14
126A
14
240A
20
244A
20
245A
20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quad Device
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hex Device
Octal Device
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
D D D
D D
D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Nine–Wide Device

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Noninverting Outputs ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ D D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Inverting Outputs D D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Single Stage (unbuffered) D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Schmitt Trigger D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
3–State Outputs D D D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Open–Drain Outputs
Common Output Enables D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Active–Low Output Enables D D D D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Active–High Output Enables
D D
Separate 4–Bit Sections

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Separate 2–Bit and 4–Bit Sections

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Transceiver
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Direction Control
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Logic–Level Down Converter

http://onsemi.com
8
 BUFFERS/INVERTERS (Continued)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
HC Devices Have CMOS–Compatible Inputs. HCT Devices Have LSTTL–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
HC
HC HCT

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
# Pins ÎÎÎ
ÎÎÎ
ÎÎÎ
Device 540A
20
541A
20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quad Device
Hex Device
Octal Device
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Nine–Wide Device
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Noninverting Outputs ÎÎÎ
ÎÎÎ
ÎÎÎ D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Inverting Outputs D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Single Stage (unbuffered)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Schmitt Trigger

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
3–State Outputs D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Open–Drain Outputs
Common Output Enables D D
D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Active–Low Output Enables

http://onsemi.com
9
 GATES
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Functional
Functional
Equivalent

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Equivalent CMOS
Device LSTTL Device Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Number

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC74 ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Function
Device
74
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
of
Pins

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC00A Quad 2–Input NAND Gate LS00 4011 LS 14

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC02A Quad 2–Input NOR Gate 4001 14
HC03A Quad 2–Input NAND Gate with Open–Drain Outputs *4011 14

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HC08A

ÎÎÎÎÎ
HC32A
HC86A
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Quad 2–Input AND Gate

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
Quad 2–Input OR Gate
Quad 2–Input Exclusive OR Gate
LS08
LS32
LS86
4081
4071
4070
LS
LS
14
14

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
LS

ÎÎÎ
14
HC132A Quad 2–Input NAND Gate with Schmitt–Trigger Inputs LS132 4093 LS 14

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
HC Devices Have CMOS–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ Device
HC
00A
HC
02A
HC
03A
HC
08A
HC
32A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
# Pins
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ 14 14 14 14 14

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Single Device
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Dual Device ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Triple Device
Quad Device D D D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
NAND
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
NOR ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
D
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
AND
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
OR

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Exclusive OR
Exclusive NOR

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
AND–NOR

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
AND–OR

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
2–Input D D D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
3–Input
4–Input

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
8–Input

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
13–Input

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Schmitt–Trigger Inputs
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Open–Drain Outputs

http://onsemi.com
10
 GATES (Continued)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
HC Devices Have CMOS–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
HC HC
Device 86A 132A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
# Pins
ÎÎÎÎ
ÎÎÎ 14 14

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Single Device
Dual Device ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Triple Device
D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Quad Device
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
NAND
NOR

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AND
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
OR ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Exclusive OR D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Exclusive NOR
AND–NOR

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
AND–OR

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
2–Input
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–Input
4–Input
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
8–Input
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
13–Input ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Schmitt–Trigger Inputs D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Open–Drain Outputs

http://onsemi.com
11
 SCHMITT TRIGGERS
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Functional
Functional
Equivalent

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Equivalent CMOS
Device LSTTL Device Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC74 ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Function
Device
74
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
of
Pins

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC14A Hex Schmitt–Trigger Inverter LS14 4584 LS/CMOS 14

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HCT14A Hex Schmitt–Trigger Inverter with LSTTL–Compatible LS14 4584 LS 14
Inputs

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC132A Quad 2–Input NAND Gate with Schmitt–Trigger Inputs LS132 4093 LS 14

BUS TRANSCEIVERS
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Functional
Functional
Equivalent

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Equivalent CMOS
Device LSTTL Device Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC74 ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Function
Device
74
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
of
Pins

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC245A Octal 3–State Noninverting Bus Transceiver LS245 LS 20
HCT245A Octal 3–State Noninverting Bus Transceiver with LS245 LS 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
LSTTL–Compatible Inputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
HC Devices Have CMOS–Compatible Inputs. HCT Devices Have LSTTL–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
HC
HCT

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Device 245A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
# Pins 20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Quad Device
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Octal Device
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Buffer
Storage Capability

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Inverting Outputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Noninverting Outputs ÎÎÎ
ÎÎÎ D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Common Output Enable

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Active–Low Output Enable ÎÎÎ
ÎÎÎ
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Active–High Output Enable
Direction Control D

http://onsemi.com
12
 LATCHES
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Functional
Functional
Equivalent

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Equivalent CMOS
Device LSTTL Device Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Number

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC74 ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Function
Device
74
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
of
Pins

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC373A Octal 3–State Noninverting Transparent Latch LS373 LS373 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HCT373A Octal 3–State Noninverting Transparent Latch with LS373 LS373 20
LSTTL–Compatible Inputs

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HC573A

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HCT573A ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Octal 3–State Noninverting Transparent Latch

ÎÎÎÎÎ
ÎÎÎ
Octal 3–State Noninverting Transparent Latch with
LS373
LS373
LS573
LS573
20
20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
LSTTL–Compatible Inputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
HC Devices Have CMOS–Compatible Inputs. HCT Devices Have LSTTL–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
HC
HCT
HC
HCT

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Device 373A 573A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
# Pins 20 20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Single Device
Dual Device

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Octal Device
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Number of Bits Controlled by Latch Enable:
D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
2
D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
8
D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Transparent
Addressable

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Readback Capability

Noninverting Outputs ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Inverting Outputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Common Latch Enable, Active–Low D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
3–State Outputs D D
Common Output Enable, Active–Low D D
These devices are identical in function and are different in pinout only: HC/HCT373A and HC/HCT573A

http://onsemi.com
13
 FLIP–FLOPS
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Functional
Functional
Equivalent

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Equivalent CMOS
Device LSTTL Device Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Number

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC74 ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Function
Device
74
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
of
Pins

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC74A Dual D Flip–Flop with Set and Reset LS74,LS74A *4013 LS 14

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HCT74A Dual D Flip–Flop with Set and Reset with LS74,LS74A 4013 LS 14
LSTTL–Compatible Inputs

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HC174A

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HC175A ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Hex D Flip–Flop with Common Clock and Reset

ÎÎÎÎÎ
ÎÎÎ
Quad D Flip–Flop with Common Clock and Reset
LS174
LS175
4174
4175
LS/CMOS
LS/CMOS
16
16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HC273A

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HCT273A ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Octal D Flip–Flop with Common Clock and Reset

ÎÎÎÎÎ
ÎÎÎ
Octal D Flip–Flop with Common Clock and Reset with
LS273
LS273
LS
LS
20
20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
LSTTL–Compatible Inputs
HC374A Octal 3–State Noninverting D Flip–Flop LS374 LS374 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HCT374A

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Octal 3–State Noninverting D Flip–Flop with

ÎÎÎÎÎ
ÎÎÎ
LSTTL–Compatible Inputs
LS374 LS374 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC574A Octal 3–State Noninverting D Flip–Flop LS374 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HCT574A Octal 3–State Noninverting D Flip–Flop with LS374 20
LSTTL–Compatible Inputs
*Suggested alternative

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
HC Devices Have CMOS–Compatible Inputs. HCT Devices Have LSTTL–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
HC
HCT HC HC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Device 74A 174A 175/A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
# Pins 14 16 16

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Type D D D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Dual Device
Quad Device D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Hex Device D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Octal Device
D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Common Clock
Negative–Transition Clocking

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Positive–Transition Clocking D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Common, Active–Low Data Enables

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Noninverting Outputs D D D
Inverting Outputs D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–State Outputs
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Common, Active–Low Output Enables

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Common Reset
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Active–Low Reset
Active–High Reset
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
D
D
D
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Active–Low Set
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Transceiver
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Direction Control ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ

http://onsemi.com
14
 FLIP–FLOPS (Continued)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
HC Devices Have CMOS–Compatible Inputs. HCT Devices Have LSTTL–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
HC
HCT
HC
HCT
HC
HCT

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Device 273A 374A 574A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
# Pins 20 20 20
Type D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Dual Device
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quad Device ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Hex Device
Octal Device D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Common Clock
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
Negative–Transition Clocking
ÎÎÎ
D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Positive–Transition Clocking D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Common, Active–Low Data Enables
D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Noninverting Outputs
Inverting Outputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–State Outputs
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Common, Active–Low Output Enables
D
D
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Common Reset D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Active–Low Reset
Active–High Reset

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Active–Low Set
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Transceiver
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Direction Control ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
These devices are identical in function and are different in pinout only: HC374A and HC574A

http://onsemi.com
15
 DIGITAL DATA SELECTORS/MULTIPLEXERS
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Functional
Functional
Equivalent

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Equivalent CMOS
Device LSTTL Device Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Number
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC74 ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Function
Device
74
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
of
Pins

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC157A Quad 2–Input Noninverting Data Selector/Multiplexer LS157 LS 16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC251 8–Input Data Selector/Multiplexer with 3–State Outputs LS251 *4512 LS 16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC253 Dual 4–Input Data Selector/Multiplexer with 3–State LS253 LS 16
Outputs

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
HC257
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Quad 2–Input Data Selector/Multiplexer with 3–State

ÎÎÎÎÎ
Outputs
*Suggested alternative
ÎÎÎ
LS257B LS 16

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
HC Devices Have CMOS–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Device
HC
157A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
# Pins 16

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Description One of

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
two 4–bit
words is

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
selected

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Single Device

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Dual Device
Quad Device D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Data Latch with Active–Low Latch Enable

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Common Address
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1–Bit Binary Address
ÎÎÎ
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
2–Bit Binary Address
3–Bit Binary Address

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Address Latch (Transparent)
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Address Latch (Non–transparent)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Active–Low Address Latch Enable
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Noninverting Output
Inverting Output

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–State Outputs
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Common Output Enable
Active–High Output Enable
ÎÎÎ
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Active–Low Output Enable D

http://onsemi.com
16
 DECODERS/DEMULTIPLEXERS/DISPLAY DRIVERS
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Functional
Functional
Equivalent

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Equivalent CMOS
Device LSTTL Device Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Number
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC74 ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Function
Device
74
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
of
Pins

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
HC138A 1–of–8 Decoder/Demultiplexer LS138 *4028 LS 16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
HCT138A 1–of–8 Decoder/Demultiplexer with LSTTL–Compatible LS138 *4028 LS 16
Inputs

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
HC139A Dual 1–of–4 Decoder/Demultiplexer LS139 4556 LS/CMOS 16
*Suggested alternative

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
HC Devices Have CMOS–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
HC
HCT HC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Device 138A 139A
# Pins 16 16

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Description
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
3–Bit Binary
Address
2–Bit Binary
Address

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Description
ÎÎÎÎÎÎÎÎÎ One of 8 One of 4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Single Device D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Dual Device

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Address Input Latch
Active–High Latch Enable

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Active–Low Latch Enable

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Active–Low Inputs

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Active–Low Outputs D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Active–High Outputs
DD D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Active–Low Output Enable
Active–High Output Enable D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Active–Low Reset
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Active–Low Blanking Input

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Active–High Blanking Input ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Active–Low Lamp–Test Input

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Phase Input (for LCD’s)
DD Implies the device has two such enables

http://onsemi.com
17
 ANALOG SWITCHES/MULTIPLEXERS/DEMULTIPLEXERS
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Functional
Functional
Equivalent

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Equivalent CMOS
Device LSTTL Device Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Number

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC74 ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Function
Device
74
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
of
Pins

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC4051A 8–Channel Analog Multiplexer/Demultiplexer 4051 CMOS 16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC4052A Dual 4–Channel Analog Multiplexer/Demultiplexer 4052 CMOS 16
HC4053A Triple 2–Channel Analog Multiplexer/Demultiplexer 4053 CMOS 16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC4066A Quad Analog Switch/Multiplexer/Demultiplexer 4066,4016 CMOS 14

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
KHC4316/A

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
KHC4851A
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Quad Analog Switch/Multiplexer/Demultiplexer with

ÎÎÎÎÎ
ÎÎÎ
Separate Analog and Digital Power Supplies
Analog Multiplexer/Demultiplexer with Injection Current
*4016 16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
*4051 20
Effect Control

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
KHC4852A Analog Multiplexer/Demultiplexer with Injection Current *4052 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Effect Control
*Suggested alternative
K High–Speed CMOS design only

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
HC Devices Have CMOS–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Device
HC
4051A
HC
4052A
HC
4053A
HC
4066A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
# Pins 16 16 16 14

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Description A 3–Bit Address A 2–Bit Address A 3–Bit Address 4 Independently

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Selects One of 8 Selects One of 4 Selects Varying Controlled
Switches Switches Combinations of Switches

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
the 6 Switches

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Single Device D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Dual Device
Triple Device D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Quad Device D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
1–to–1 Multiplexing D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
2–to–1 Multiplexing D
4–to–1 Multiplexing D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
8–to–1 Multiplexing

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
Active–High ON/OFF Control
ÎÎÎÎÎ
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Common Address Inputs D D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
2–Bit Binary Address
3–Bit Binary Address D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Address Latch with Active–Low Latch

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Enable
D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Common Switch Enable
Active–Low Enable D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Active–High Enable

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Separate Analog and Control Reference D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Power Supplies
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Switched Tubs (for RON and Prop. Delay
Improvement)

http://onsemi.com
18
 ANALOG SWITCHES/MULTIPLEXERS/DEMULTIPLEXERS (Continued)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
HC Devices Have CMOS–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
HC HC HC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Device 4316A 4851A 4852A
# Pins 16 20 20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Description
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
4 Independently
Controlled Switches
A 3–Bit Address
Selects One of 8
A 3–Bit Address
Selects Varying

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
(Has a Separate Switches Combinations of
Analog Lower (Has Injection Current the 6 Switches

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Power Supply) Protection)

D
(Has Injection Current
Protection)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Single Device
Dual Device D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Triple Device
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quad Device ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
1–to–1 Multiplexing D
2–to–1 Multiplexing

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
4–to–1 Multiplexing

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
8–to–1 Multiplexing ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Active–High ON/OFF Control D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Common Address Inputs D
2–Bit Binary Address D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
3–Bit Binary Address

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Common Switch Enable
ÎÎÎÎÎÎÎ D
D
D
D
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Active–Low Enable D D
Active–High Enable

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Separate Analog and Control Reference Power Supplies

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Switched Tubs (for RON and Prop. Delay Improvement)
D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
njection Current Protection D D

http://onsemi.com
19
 SHIFT REGISTERS
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Functional
Functional
Equivalent

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Equivalent CMOS
Device LSTTL Device Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Number

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC74 ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Function
Device
74
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
of
Pins

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC164A 8–Bit Serial–Input/Parallel–Output Shift Register LS164 LS 14

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC165A 8–Bit Serial– or Parallel–Input/Serial–Output Shift Register LS165 *4021 LS 16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC589A 8–Bit Serial– or Parallel–Input/Serial–Output Shift Register 16
with 3–State Output

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HC595A

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
8–Bit Serial–Input/Serial– or Parallel–Output Shift Register

ÎÎÎÎÎ
ÎÎÎ
with Latched 3–State Outputs
*Suggested alternative
16

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
HC Devices Have CMOS–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Device
HC
164A
HC
165A
HC
589A
HC
595A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
# Pins 14 16 16 16

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
4–Bit Register
8–Bit Register D D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Serial Data Input
Parallel Data Inputs ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
D D
D
D
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Serial Output Only
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Parallel Outputs ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
D
D

D
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Inverting Output
Noninverting Output D D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Shifts One Direction Only ÎÎÎ
Serial Shift/Parallel Load Control

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ D
D
D
D
D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Shifts Both Directions
D D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Positive–Transition Clocking
Active–High Clock Enable D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Data Enable
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Data Latch with Active–High Latch Clock
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Latch with Active–High Latch Clock D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–State Outputs
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Active–Low Output Enable ÎÎÎ
ÎÎÎÎ
ÎÎÎ
D
D
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Active–Low Reset
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ D D

http://onsemi.com
20
 COUNTERS
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Functional
Functional
Equivalent

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Equivalent CMOS
Device LSTTL Device Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Number

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC74 ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Function
Device
74
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
of
Pins

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC161A Presettable 4–Bit Binary Counter with Asynchronous LS161,LS161A LS 16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Reset
HC163A Presettable 4–Bit Binary Counter with Synchronous Reset LS161,LS161A LS 16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC390A Dual 4–Stage Binary Ripple Counter with ÷ 2 and ÷ 5 16
Sections 16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
HC393A
HC4020A ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Dual 4–Stage Binary Ripple Counter
14–Stage Binary Ripple Counter
LS393 *4520
4020
LS
CMOS
14
16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC4040A 12–Stage Binary Ripple Counter 4040 CMOS 16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
HC4060A 14–Stage Binary Ripple Counter with Oscillator 4060 CMOS 16
*Suggested alternative

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
HC Devices Have CMOS–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
HC HC HC HC HC HC HC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Device 161A 163A 390A 393A 4020A 4040A 4060A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
# Pins 16 16 16 14 16 16 16
D D D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Single Device
Dual Device D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Ripple Counter
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Number of Ripple Counter Internal Stages
D
4
D
4
D
14
D
12
D
14

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Number of Stages with Available Outputs 4 4 12 12 10

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Count Up D D D D D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
4–Bit Binary Counter D D D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
BCD Counter
Decimal Counter

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Separate ÷ 2 Section

ÎÎÎ ÎÎÎ
ÎÎÎ
Separate ÷ 5 Section ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
On–Chip Oscillator Capability

ÎÎÎÎ ÎÎÎ
ÎÎÎ
Positive–Transition Clocking
ÎÎÎ D D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Negative–Transition Clocking D D D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Active–High Clock Enable
Active–Low Clock Enable

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Active–High Reset ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
Active–High Count Enable

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
DD
D
DD
D D D D D D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
BCD Preset Data Inputs ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
4–Bit Binary Preset Data Inputs

ÎÎÎ
ÎÎÎ
D

D
D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Active–Low Load Preset

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Carry Output D D
DD implies the device has two such enables

http://onsemi.com
21
 MISCELLANEOUS DEVICES
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
Functional
Functional
Equivalent

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
Equivalent CMOS
Device LSTTL Device Number

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Number

ÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC74 ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
Function
Device
74
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
of
Pins

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
HC4046A Phase–Locked Loop 4046 CMOS 16

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
HC4538A Dual Precision Monostable Multivibrator 4538,4528 CMOS 16
(Retriggerable, Resettable)

http://onsemi.com
22
 CHAPTER 2
Design Considerations

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Handling Precautions . . . . . . . . . . . . . . . . . . . . . . . . 24
Power Supply Sizing . . . . . . . . . . . . . . . . . . . . . . . . . 28
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CMOS Latch Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . 40
Thermal Management . . . . . . . . . . . . . . . . . . . . . . . 41
Capacitive Loading Effects on
Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Temperature Effects on DC and AC
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Supply Voltage Effects on Drive Current
and Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . 44
Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . 45
Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical Parametric Values . . . . . . . . . . . . . . . . . . . . 48
Reduction of Electromagnetic
Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Hybrid Circuit Guidelines . . . . . . . . . . . . . . . . . . . . . 49
Schmitt–Trigger Devices . . . . . . . . . . . . . . . . . . . . . 50
Oscillator Design with High–Speed CMOS . . . . . . 51
Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . 52
Definitions and Glossary of Terms . . . . . . . . . . . . . 53
Applications Assistance Form . . . . . . . . . . . . . . . . . 56

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 INTRODUCTION

CMOS devices have been used for many years in due to the self–aligning gate feature. This process uses the
applications where the primary concerns were low power gate to define the channel during processing, eliminating
consumption, wide power–supply range, and high noise registration errors and, therefore, the need for gate overlaps.
immunity. However, metal–gate CMOS (MC14000 series) The elimination of the gate overlap significantly lowers the
is too slow for many applications. Applications requiring gate capacitance, resulting in higher speed capability. The
high–speed devices, such as microprocessor memory smaller gate length also results in higher drive capability per
decoding, had to go to the faster families such as LSTTL. unit gate width, ensuring more efficient use of chip area.
This meant sacrificing the best qualities of CMOS. The next Immunity enhancements to electrostatic discharge (ESD)
step in the logic evolution was to introduce a family of damage and latch up are ongoing. Precautions should still be
devices that were fast enough for such applications, while taken, however, to guard against electrostatic discharge and
retaining the advantages of CMOS. The results of this latch up.
change can be seen in 1 where HSCMOS devices are ON Semiconductors’s High–Speed CMOS family has a
compared to standard (metal–gate) CMOS, LSTTL, and broad range of functions from basic gates, flip–flops, and
ALS. counters to bus–compatible devices. The family is made up
The ON Semiconductor CMOS evolutionary process of devices that are identical in pinout and are functionally
shown in Figure 1 indicates that one advantage of the equivalent to LSTTL devices, as well as the most popular
silicon–gate process is device size. The High–Speed CMOS metal–gate devices not available in TTL. Thus, the designer
(HSCMOS) device is about half the size of the metal–gate has an excellent alternative to existing families without
predecessor, yielding significant chip area savings. The having to become familiar with a new set of device numbers.
silicon–gate process allows smaller gate or channel lengths
METAL GATE CMOS
METAL
OXIDE
P+ N+ N+ P+ N+ P+ P+ N+
P– N–

120 µm
POLY
METAL
PSG
OXIDE
HIGH–SPEED
SILICON–GATE N+ P– N+
P+ P+
HSCMOS P N N–
65 µm

Figure 1. CMOS Evolution

HANDLING PRECAUTIONS
High–Speed CMOS devices, like all MOS devices, have VCC
SILICON–GATE
an insulated gate that is subject to voltage breakdown. The
gate oxide for HSCMOS devices breaks down at a D1
CMOS ∼ 150 Ω ∼ 50 Ω
gate–source potential of about 100 volts. Some device inputs INPUT TO CIRCUIT
POLY D2
are protected by a resistor–diode network (Figure 2). New
input protection structure deletes the poly resistor (Figure 3)
Using the test setup shown in Figure 4, the inputs typically GND
withstand a > 2 kV discharge. Figure 2. Input Protection Network

SILICON–GATE
VCC VCC 10 M W W
1.5 k TO INPUT
UNDER TEST
CMOS ∼ 190 Ω HIGH VOLTAGE
INPUT TO CIRCUIT 100 pF VZAP
DC SOURCE
Diffused
VCC
OR
GROUND

Figure 3. New Input Protection Network Figure 4. Electrostatic Discharge Test Circuit

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Table 1. Logic Family Comparisons

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
General Characteristics (1) (All Maximum Ratings)

ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TTL CMOS

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Characteristic Symbol LS ALS MC14000 Hi–Speed Unit

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
Operating Voltage Range

ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
Operating Temperature Range
ÎÎÎ
VCC/EE/DD
TA
5 ± 5%
0 to + 70
5 ± 5%
0 to + 70
3.0 to 18
– 40 to + 85
2.0 to 6.0
– 55 to + 125
V
_C

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Voltage (limits) VIH min 2.0 2.0 3.54 3.54 V

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIL max 0.8 0.8 1.54 1.04 V

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Output Voltage (limits) VOH min 2.7 2.7 VDD – 0.05 VCC – 0.1 V

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VOL max 0.5 0.5 0.05 0.1 V

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Current IINH 20 20 µA
± 0.3
03 ± 1.0
10

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
IINL – 400 – 200

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Output Current @ VO (limit) IOH – 0.4 – 0.4 – 2.1 @ 2.5 V – 4.0 @ mA
unless otherwise specified VCC – 0.8 V

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
DC Noise Margin Low/High ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
IOL
DCM
8.0
0.3/0.7
8.0
0.3/0.7
0.44 @ 0.4 V
1.454
4.0 @ 0.4 V
0.90/1.354
mA
V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
DC Fanout — 20 20 50(1)2 50(10)2 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Speed/Power Characteristics (1) (All Typical Ratings)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TTL CMOS

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Characteristic Symbol LS ALS MC14000 Hi–Speed Unit

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Quiescent Supply Current/Gate IG 0.4 0.2 0.0001 0.0005 mA

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Power/Gate (Quiescent) PG 2.0 1.0 0.0006 0.001 mW

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Propagation Delay tp 9.0 7.0 125 8.0 ns

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Speed Power Product — 18 7.0 0.075 0.01 pJ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Clock Frequency (D–F/F) fmax 33 35 4.0 40 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Frequency (Counter) fmax 40 45 5.0 40 MHz

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Propagation Delay (1)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TTL CMOS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Characteristic LS ALS MC14000 Hi–Speed Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Gate, NOR or NAND: Product No. SN74LS00 SN74ALS00 MC14001B 74HC00 —
tPLH/tPHL(5) (10)3 (5)3 (8)3 10

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Typical 25 ns
Maximum (15)3 10 250 (15)3 20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Flip–Flop, D–type:

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
tPLH/tPHL(5) (Clock to Q)
ÎÎÎ
Product No.
Typical
SN74LS74
(25)3
SN74ALS74
(12)3
MC14013B
175
74HC74
(23)2 25
—
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Counter:
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Maximum
Product No.
(40)3
SN74LS163
20
SN74ALS163
350
MC14163B
(30)3 32
74HC163 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
tPLH/tPHL(5) (Clock to Q)
ÎÎÎ Typical (18)3 (10)3 350 (20)3 22 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
NOTES: ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ Maximum

1. Specifications are shown for the following conditions:

(27)3 24 700 (27)3 29

a) VDD (CMOS) = 5.0 V ± 10% for dc tests, 5.0 V for ac tests; VCC (TTL) = 5.0 V ± 5% for dc tests, 5.0 V for ac tests
b) Basic Gates: LS00 or equivalent
c) TA = 25_C
d) CL = 50 pF (ALS, HC), 15 pF (LS, 14000 and Hi–Speed)
e) Commercial grade product
2. ( ) fanout to LSTTL
3. ( ) CL = 15 pF
4. DC input voltage specifications are proportional to supply voltage over operating range.
5. The number specified is the larger of tPLH and tPHL for each device.

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 The input protection network consists of large ESD 1. Wrist straps and equipment logs should be maintained
protection diodes, a diffused resistor, and two small and audited on a regular basis. Wrist straps
“dummy” transistors. Outputs have a similar ESD malfunction and may go unnoticed. Also, equipment
protection network except for the series resistor. Although gets moved from time to time and grounds may not be
the on–chip protection circuitry guards against ESD reconnected properly.
damage, additional protection may be necessary once the 2. Do not exceed the Maximum Ratings specified by the
chip is placed in circuit. Both an external series resistor and data sheet.
ground and VCC diodes, similar to the input protection 3. All unused device inputs should be connected to VCC
structure, are recommended if there is a potential of ESD, or GND.
voltage transients, etc. Several monolithic diode arrays are 4. All low impedance equipment (pulse generators, etc.)
available from ON Semiconductor, such as the MAD130 should be connected to CMOS inputs only after the
(dual 10 diode array) or the MAD1104 (dual 8 diode array). CMOS device is powered up. Similarly, this type of
These diodes, in chip form, not only provide the necessary equipment should be disconnected before power is
protection, but also save board space as opposed to using turned off.
discrete diodes. 5. Circuit boards containing CMOS devices are merely
Static damaged devices behave in various ways, extensions of the devices, and the same handling
depending on the severity of the damage. The most severely precautions apply. Contacting edge connectors wired
damaged pins are the easiest to detect. An ESD–damaged directly to device inputs can cause damage. Plastic
pin that has been completely destroyed may exhibit a wrapping should be avoided. When external
low–impedance path to VCC or GND. Another common connectors to a PC board are connected to an input or
failure mode is a fused or open circuit. The effect of both output of a CMOS device, a resistor should be used in
failure modes is that the device no longer properly responds series with the input or output. This resistor helps limit
to input signals. Less severe cases are more difficult to detect accidental damage if the PC board is removed and
because they show up as intermittent failures or as degraded brought into contact with static generating materials.
performance. Generally, another effect of static damage is The limiting factor for the series resistor is the added
increased chip leakage currents (ICC). delay. The delay is caused by the time constant formed
Although the input network does offer significant by the series resistor and input capacitance. Note that
protection, these devices are not immune to large static the maximum input rise and fall times should not be
voltage discharges that can be generated while handling. For exceeded. In Figure 5, two possible networks are
example, static voltages generated by a person walking shown using a series resistor to reduce ESD damage.
across a waxed floor have been measured in the 4 to 15 kV For convenience, an equation is given for added
range (depending on humidity, surface conditions, etc.). propagation delay and rise time effects due to series
Therefore, the following precautions should be observed. resistance size.
VCC

CMOS D1 CMOS
TO OFF–BOARD R1 INPUT TO OFF–BOARD R2 INPUT
CONNECTION OR CONNECTION OR
OUTPUT D2 OUTPUT
GND
Advantage: Requires minimal area Advantage: R2 < R1 for the same level of
protection. Impact on ac and dc
Disadvantage: R1 > R2 for the same level of characteristics is minimized.
protection; therefore, rise and
fall times, propagation delays, Disadvantage: More board area, higher initial
and output drives are severely cost.
affected. NOTE: These networks are useful for protecting the following:
A digital inputs and outputs C 3–state outputs
B analog inputs and outputs D bidirectional (I/O) ports
Propagation Delay and Rise Time vs. Series Resistance
R [ t
C·k
where:
R=the maximum allowable series resistance in ohms
t= the maximum tolerable propagation delay or rise time in
t= seconds
C= the board capacitance plus the driven input
C= capacitance in farads
k= 0.7 for propagation delay calculations
k= 2.3 for rise time calculations
Figure 5. Networks for Minimizing ESD and Reducing CMOS Latch Up Susceptibility

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 6. All CMOS devices should be stored or transported in b. Brush or spray cleaning should not be used.
materials that are antistatic or conductive. CMOS c. Assemblies should be placed into the vapor
devices must not be inserted into conventional plastic degreaser immediately upon removal from the
“snow”, Styrofoam, or plastic trays, but should be left antistatic or conductive container.
in their original container until ready for use. d. Cleaned assemblies should be placed in antistatic
7. All CMOS devices should be placed on a grounded or conductive containers immediately after
bench surface and operators should ground removal from the cleaning basket.
themselves prior to handling devices, because a e. High velocity air movement or application of
worker can be statically charged with respect to the solvents and coatings should be employed only
bench surface. Wrist straps in contact with skin are when a static eliminator using ionized air is
essential and should be tested daily. See Figure 6 for directed at the printed circuit board.
an example of a typical work station. 14. The use of static detection meters for production line
8. Nylon or other static generating materials should not surveillance is highly recommended.
come in contact with CMOS devices. 15. Equipment specifications should alert users to the
9. If automatic handlers are being used, high levels of presence of CMOS devices and require
static electricity may be generated by the movement familiarization with this specification prior to
of the device, the belts, or the boards. Reduce static performing any kind of maintenance or replacement
buildup by using ionized air blowers, anti–static of devices or modules.
sprays, and room humidifiers. All conductive parts of 16. Do not insert or remove CMOS devices from test
machines which come into contact with the top, sockets with power applied. Check all power supplies
bottom, or sides of IC packages must be grounded to to be used for testing devices to be certain there are no
earth ground. voltage transients present.
10. Cold chambers using CO2 for cooling should be 17. Double check test equipment setup for proper polarity
equipped with baffles, and the CMOS devices must be of VCC and GND before conducting parametric or
contained on or in conductive material. functional testing.
11. When lead straightening or hand soldering is 18. Do not recycle shipping rails. Repeated use causes
necessary, provide ground straps for the apparatus deterioration of their antistatic coating. Exception:
used and be sure that soldering iron tips are grounded. carbon rails (black color) may be recycled to some
12. The following steps should be observed during wave extent. This type of rail is conductive and antistatic.
solder operations:
a. The solder pot and conductive conveyor system of RECOMMENDED READING
the wave soldering machine must be grounded to
“Requirements for Handling Electrostatic–Discharge
earth ground.
Sensitive (ESDS) Devices” EIA Standard EIA–625
b. The loading and unloading work benches should
Available by writing to:
have conductive tops grounded to earth ground.
Global Engineering Documents
c. Operators must comply with precautions
15 Inverness Way East
previously explained.
Englewood, Colorado 80112
d. Completed assemblies should be placed in
Or by calling:
antistatic or conductive containers prior to being
1–800–854–7179 in the USA or CANADA or
moved to subsequent stations.
(303) 397–7956 International
13. The following steps should be observed during
S. Cherniak, “A Review of Transients and Their Means of
board–cleaning operations:
Suppression”, Application Note–843, ON Semiconductor
a. Vapor degreasers and baskets must be grounded to
Products Inc., 1982.
earth ground.

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 4

NOTES:
1. 1/16 inch conductive sheet stock covering bench-top work
1 area.
2. Ground strap.
3. Wrist strap In contact with skin.
2 4. Static neutralizer. (ionized air blower directed at work.
5 Primarily for use in areas where direct grounding is
impractical.
5. Room humidifier. Primarily for use in areas where the
3 relative humidity is less than 45%. Caution: building
heating and cooling systems usually dry the air causing
the relative humidity inside a building to be less than
outside humidity.
R=1M W

Figure 6. Typical Manufacturing Work Station

POWER SUPPLY SIZING

CMOS devices have low power requirements and the operation of all devices. The obvious benefit of this type of
ability to operate over a wide range of supply voltages. design is cost savings.
These two characteristics allow CMOS designs to be
implemented using inexpensive power supplies without BATTERY SYSTEMS
cooling fans. In addition, batteries may be used as either a HSCMOS devices can be used with battery or battery
primary power source or as a backup. backup systems. A few precautions should be taken when
The maximum recommended power supply voltage for designing battery–operated systems.
HC devices is 6.0 V and 5.5 V for HCT devices. Figure 7 1. The recommended power supply voltages should be
offers some insight as to how this specification was derived. observed. For battery backup systems such as the one
In the figure, VS is the maximum power supply voltage and in Figure 8, the battery voltage must be at least
IS is the sustaining current for the latch–up mode. The value 2.7 volts (2 volts for the minimum power supply
of VS was chosen so that the secondary breakdown effect voltage and 0.7 volts to account for the voltage drop
may be avoided. The low–current junction avalanche region across the series diode).
is between 10 and 14 volts at TA = 25_C. 2. Inputs that might go above the battery backup voltage
should use the HC4049 or HC4050 buffers (Figure 8).
If line power is interrupted, CMOS System A and
ICC Buffer A lose power. However, CMOS System B and
Buffer B remain active due to the battery backup.
Buffer A protects System A from System B by
LATCH blocking active inputs while the circuit is not powered
UP MODE up. Also, if the power supply voltage drops below the
SECONDARY battery voltage, Buffer A acts as a level translator for
BREAKDOWN
the outputs from System B. Buffer B acts to protect
LOW CURRENT System B from any overvoltages which might exist.
JUNCTION Both buffers may be replaced with current–limiting
IS
AVALANCHE resistors, however power consumption is increased
and propagation delays are lengthened.
VS VCC 3. Outputs that are subject to voltage levels above VCC
DATA SHEET MAXIMUM SUPPLY RATING or below GND should be protected with a series
resistor and/or clamping diodes to limit the current to
Figure 7. Secondary Breakdown Characteristics an acceptable level.
In an ideal system design, the power supply should be
designed to deliver only enough current to ensure proper

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 POWER SUPPLY

BATTERY TRICKLE
RECHARGE

CMOS
SYSTEM

Figure 8. Battery Backup System

POWER SUPPLY

BATTERY TRICKLE
LINE POWER ONLY BATTERY BACKUP RECHARGE
SYSTEM SYSTEM

HC4049
CMOS CMOS
HC4050
SYSTEM SYSTEM

HC4049
HC4050

A B

Figure 9. Battery Backup Interface

CPD POWER CALCULATION 1 MHz and the following formula is used to determine the
Power consumption for HSCMOS is dependent on the device’s CPD value:
power–supply voltage, frequency of operation, internal ICC (dynamic)
capacitance, and load. The power consumption may be CPD = – CL
VCC • f
calculated for each package by summing the quiescent
power consumption, ICC • VCC, and the switching power The resulting power dissipation is calculated using CPD as
required by each device within the package. For large follows under no–load conditions.
systems, the most timely method is to bread–board the (HC) PD = CPDVCC2f + VCCICC
circuit and measure the current required under a variety of (HCT) PD = CPDVCC2f + VCCICC + ∆ICCVCC
conditions.
(δ1 + δ2 + … + δn)
The device dynamic power requirements can be
calculated by the equation: where the previously undefined variable, δn is the duty cycle
PD = (CL + CPD) VCC2f
of each input applied at TTL/NMOS levels.
The power dissipation for analog switches switching
where: PD = power dissipated in µW
digital signals is the following:
CL = total load capacitance present at the output
in pF (HC) PD = CPDVCC2fin + (CS + CL)VCC2fout + VCCICC
CPD = a measure of internal capacitances, called where: CS = digital switch capacitance, and
power dissipation capacitance, given in pF fout = output frequency
VCC = supply voltage in volts In order to determine the CPD of a single section of a device
f = frequency in MHz (i.e., one of four gates, or one of two flip–flops in a package),
If the devices are tested at a sufficiently high frequency, ON Semiconductor uses the following procedures as
the dc supply current contributes a negligible amount to the defined by JEDEC. Note: “biased” as used below means
overall power consumption and can therefore be ignored. “tied to VCC or GND.”
For this reason, the power consumption is measured at

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Gates: Switch one input while the remaining PD = (CPD + CL)VCC2f + VCCICC
input(s) are biased so that the output(s) PD1 = (22 pF + 50 pF)(5 V)2(1 kHz) 1.8 µW
switch.
PD2 = (22 pF + 50 pF)(5 V)2(1 MHz) 1800 µW
Latches: Switch the enable and data inputs such that
PD3 = (22 pF) (5 V)2(0 Hz) = 0 µW
the latch toggles.
PD4 = (22 pF)(5 V)2(0 Hz) = 0 µW
Flip–Flops: Switch the clock pin while changing the
data pin(s) such that the output(s) change PD(total) = VCCICC + PD1 + PD2 + PD3 + PD4
with each clock cycle. = 10 µW + 1.8 µW + 1800 µW + 0 µW
Decoders/ Switch one address pin which changes two = 1812 µW
Demultiplexers: outputs.
Data Selectors/ Switch one address input with the corre- VCC = 5 V
Multiplexers: sponding data inputs at opposite logic
levels so that the output switches.
1 3
Analog Switch one address/select pin which f = 1 kHz 50 pF
Switches: changes two switches. The switch
inputs/outputs should be left open. For
digital applications where the switch
inputs/outputs change between VCC and
2 4
GND, the respective switch capacitance
f = 1 MHz 50 pF
should be added to the load capacitance.
Counters: Switch the clock pin with the other inputs
biased so that the device counts.
Figure 10. Power Consumption Calculation Example
Shift Switch the clock while alternating the
input As seen by this example, the power dissipated by CMOS
Registers: so that the device shifts alternating 1s and devices is dependent on frequency. When operating at very
0s through the register. high frequencies, HSCMOS devices can consume as much
Transceivers: Switch only one data input. Place power as LSTTL devices, as shown in Figure 11. The power
transceivers in a single direction. savings of HSCMOS is realized when used in a system
where only a few of the devices are actually switching at the
Monostables: The pulse obtained with a resistor and no
system frequency. The power consumption savings comes
external capacitor is repeatedly switched.
from the fact that for CMOS, only the devices that are
Parity Switch one input. switching consume significant power.
Generators:
Encoders: Switch the lowest priority output. 100 m
5 MC7400
Display Switch one input so that approximately
2
one– SN74LS00
10 m
Drivers: half of the outputs change state. 5
POWER (WATTS)

SN74ALS00
ALUs/Adders: Switch the least significant bit. The 2
remaining inputs are biased so that the 1m
device is alternately adding 0000 (binary) 5
or 0001 (binary) to 1111 (binary). 2 VCC = 5 Vdc
On HSCMOS data sheets, CPD is a typical value and is 100 µ MC74HC00
given either for the package or for the individual device (i.e., 5
gates, flip–flops, etc.) within the package. An example of 2
calculating the package power requirement is given using 10 µ
2 57 2 5 7 2 5 7 2 5 7 2 5 7
the 74HC00, as shown in Figure 10. 10 k 100 k 1M 10 M 100 M 1G
From the data sheet: FREQUENCY @ 50% DUTY CYCLE (Hz)
ICC = 2 µA at room temperature (per package)
Figure 11. Power Consumption Vs. Input Frequency
CPD = 22 pF per gate for TTL, LSTTL, ALs, and HSCMOS

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 INPUTS this chapter, for series resistor consideration). The resistors
should be configured as in Figure 14.
A basic knowledge of input and output structures is FROM RS
HSCMOS
essential to the HSCMOS designer. This section deals with EDGE
DEVICE
CONNECTOR
the various input characteristics and application rules 100 k W
regarding their use. Output characteristics are discussed in
the section titled Outputs.

v v
All standard HC, HCU and HCT inputs, while in the
recommended operating range (GND Vin VCC), can be Figure 14. External Protection
modeled as shown in Figure 12. For input voltages in this For inputs outside of the recommended operating range,
range, diodes D1 and D2 are modeled as resistors the CMOS input is modeled as in Figure 15 and Figure 16.
representing the high–impedance of reverse biased diodes. Current flows through diode D1 or D2 whenever the input
The maximum input current is 1 µA, worst case over voltage exceeds VCC or drops below GND enough to
temperature, when the inputs are at VCC or GND, and VCC forward bias either D1 or D2. The device inputs are
= 6 V. guaranteed to withstand from GND – 0.5 V to VCC + 0.5 V
and a maximum current of 20 mA. If this maximum rating
VCC
is exceeded, the device could go into a latch–up condition.
R1 = R2 = HIGH Z
(See CMOS Latch Up, this chapter.) Voltage should never
R1 be applied to any input or output pin before power has been
applied to the device’s power pins. Bias on input or output
pins should be removed before removing the power.
10 pF However, if the input current is limited to less than 20 mA,
R2
and this current only lasts for a brief period of time (< 100
ms), no damage to the device occurs.
Figure 12. Input Model for GND v Vin v VCC Another specification that should be noted is the
maximum input rise (tr) and fall (tf) times. Figure 17 shows
When CMOS inputs are left open–circuited, the inputs the results of exceeding the maximum rise and fall times
may be biased at or near the typical CMOS switchpoint of recommended by ON Semiconductor or contained in
0.45 VCC for HC devices or 1.3 V for HCT devices. At this JEDEC Standard No. 7A. The reason for the oscillation on
switchpoint, both the P–channel and the N–channel the output is that as the voltage passes through the switching
transistors are conducting, causing excess current drain. Due threshold region with a slow rise time, any noise that is on
to the high gain of the buffered devices (see Figure 13), the the input line is amplified, and is passed through to the
device can go into oscillation from any noise in the system, output. This oscillation may have a low enough frequency
resulting in even higher current drain. to cause succeeding stages to switch, giving unexpected
5 results. If input rise or fall times are expected to exceed the
maximum specified rise or fall times, Schmitt–triggered
4
devices such as ON Semiconductor’s HC14A and HC132A
Vout , OUTPUT VOLTAGE (V)

are recommended.

3 HCT HC OUTPUTS

All HSCMOS outputs, with the exception of the

2
HCU04A, are buffered to ensure consistent output voltage
and current specifications across the family. All buffered
1
v v
outputs have guaranteed output voltages of VOL = 0.1 V and
VOH = VCC – 0.1 V for Iout 20 µA ( 20 HSCMOS
loads).
0 1 2 3 4 5 The output drives for standard drive devices are such

v w
Vin, INPUT VOLTAGE (V) that 74HC/HCT devices can drive ten LSTTL loads and
maintain a VOL 0.4 V and VOH VCC – 0.8 V across the
Figure 13. Typical Transfer Characteristics
full temperature range; bus–driver devices can drive fifteen
for Buffered Devices
LSTTL loads under the same conditions.
For these reasons, all unused HC/HCT inputs should be
v v
The outputs of all HSCMOS devices are limited to
connected either to VCC or GND. For applications with externally forced output voltages of – 0.5 Vout VCC
inputs going to edge connectors, a 100 kΩ resistor to GND + 0.5 V. For externally forced voltages outside this range a
should be used, as well as a series resistor (RS) for static
protection and current limiting (see Handling Precautions,

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latch up condition could be triggered. (See CMOS Latch paralleled. Paralleling devices in different packages may
Up, this chapter.) result in devices switching at different points on the input
The maximum rated output current given on the voltage waveform, creating output short circuits and
individual data sheets is 25 mA for standard outputs and 35 yielding undesirable output voltage waveforms.
mA for bus drivers. The output short circuit currents of these As a design aid, output characteristic curves are given
devices typically exceed these limits. The outputs can, for both P–channel source and N–channel sink currents.
however, be shorted for short periods of time for logic The curves given include expected minimum curves for
testing, if the maximum package power dissipation is not TA = 25_C, 85_C, and 125_C, as well as typical values for
violated. (See individual data sheets for maximum power TA = 25_C. For temperatures < 25_C, use the 25_C curves.
dissipation ratings.) These curves, Figure 18 through Figure 29, are intended as
For applications that require driving high capacitive loads design aids, not as guarantees. Unused output pins should be
where fast propagation delays are needed (e.g., driving open–circuited (floating).
power MOSFETS), devices within the same package may be

 150 W D1

3 pF D2 2 pF Vin

Figure 15. Input Model for Vin > VCC or Vin < GND

Vout
D1

3 pF D2 2 pF

Figure 17. Maximum Rise Time Violation

Figure 16. Input Model for New ESD Enhanced Circuits

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 STANDARD OUTPUT CHARACTERISTICS

N–CHANNEL SINK CURRENT P–CHANNEL SOURCE CURRENT

25 – 25

Iout, OUTPUT SOURCE CURRENT (mA)

Iout, OUTPUT SINK CURRENT (mA)

20 – 20

15 –15

10 –10
TYPICAL TYPICAL
TA = 25_C TA = 25_C
5 –5
EXPECTED MINIMUM *, TA = 25–125_C EXPECTED MINIMUM *, TA = 25–125_C

0 0
0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0
Vout, OUTPUT VOLTAGE (V) Vout, OUTPUT VOLTAGE (V)

Figure 18. VGS = 2.0 V Figure 19. VGS = – 2.0 V

25 – 25
Iout, OUTPUT SOURCE CURRENT (mA)
TYPICAL
Iout, OUTPUT SINK CURRENT (mA)

TYPICAL TA = 25_C
20 – 20 TA = 25_C
TA = 25_C TA = 25_C

TA = 85_C TA = 85_C
15 –15

TA = 125_C TA = 125_C
10 –10

5 EXPECTED MINIMUM CURVES* –5 EXPECTED MINIMUM CURVES*

0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
Vout, OUTPUT VOLTAGE (V) Vout, OUTPUT VOLTAGE (V)

Figure 20. VGS = 4.5 V Figure 21. VGS = – 4.5 V

25 – 25
TA = 85_C TA = 85_C
TYPICAL TA = 25_C TYPICAL TA = 25_C
Iout, OUTPUT SOURCE CURRENT (mA)

TA = 25_C TA = 25_C
Iout, OUTPUT SINK CURRENT (mA)

TA = 125_C TA = 125_C
20 – 20

15 –15

EXPECTED MINIMUM CURVES*

10 –10 EXPECTED MINIMUM CURVES*

5 –5

0 0
0 1.0 2.0 3.0 4.0 5.0 6.0 6.0 5.0 4.0 3.0 2.0 1.0 0
Vout, OUTPUT VOLTAGE (V) Vout, OUTPUT VOLTAGE (V)

Figure 22. VGS = 6.0 V Figure 23. VGS = – 6.0 V

*The expected minimum curves are not guarantees, but are design aids.

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 BUS–DRIVER OUTPUT CHARACTERISTICS

N–CHANNEL SINK CURRENT P–CHANNEL SOURCE CURRENT

35 – 35
Iout, OUTPUT SOURCE CURRENT (mA)

Iout, OUTPUT SINK CURRENT (mA)

30 – 30

25 – 25

20 – 20

15 TYPICAL –15 TYPICAL

TA = 25_C TA = 25_C
10 –10

5 EXPECTED MINIMUM *, TA = 25–125_C –5 EXPECTED MINIMUM *, TA = 25–125_C

0 0
0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0
Vout, OUTPUT VOLTAGE (V) Vout, OUTPUT VOLTAGE (V)

Figure 24. VGS = 2.0 V Figure 25. VGS = – 2.0 V

35 – 35
TA = 25_C
Iout, OUTPUT SOURCE CURRENT (mA)

TYPICAL TYPICAL TA = 85_C

Iout, OUTPUT SINK CURRENT (mA)
30 – 30
TA = 25_C TA = 25_C TA = 25_C
25 – 25 TA = 125_C
TA = 85_C
20 – 20
TA = 125_C
15 –15
EXPECTED MINIMUMS*

10 EXPECTED MINIMUMS* –10

5 –5

0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
Vout, OUTPUT VOLTAGE (V) Vout, OUTPUT VOLTAGE (V)

Figure 26. VGS = 4.5 V Figure 27. VGS = – 4.5 V

35 – 35
TYPICAL
Iout, OUTPUT SOURCE CURRENT (mA)

TYPICAL
Iout, OUTPUT SINK CURRENT (mA)

30 TA = 25_C – 30 TA = 25_C
TA = 25_C TA = 25_C
25 – 25
TA = 85_C
TA = 85_C
20 – 20
TA = 125_C
TA = 125_C
15 –15
EXPECTED MINIMUMS*
10 –10
EXPECTED MINIMUMS*
5 –5

0 0
0 1.0 2.0 3.0 4.0 5.0 6.0 6.0 5.0 4.0 3.0 2.0 1.0 0
Vout, OUTPUT VOLTAGE (V) Vout, OUTPUT VOLTAGE (V)

Figure 28. VGS = 6.0 V Figure 29. VGS = – 6.0 V

*The expected minimum curves are not guarantees, but are design aids.

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3–STATE OUTPUTS VCC
Some HC/HCT devices have outputs that can be placed
into a high–impedance state. These 3–state output devices
are very useful for gang connecting to a common line or bus. HIGH Z
When enabled, these output pins can be considered as
ordinary output pins; as such, all specifications and
OUTPUT
precautions of standard output pins should be followed.
When disabled (high–impedance state), these outputs can be
modeled as in Figure 30. Output leakage current (10 µA
worst case over temperature) as well as 3–state output 10 pF
capacitance must be considered in any bus design. LOW Z HIGH Z
When power is interrupted to a 3–state device, the bus
voltage is forced to between GND and VCC + 0.7 V
regardless of the previous output state.
VCC Figure 32. Model of Open–Drain Output

R1 = R2 = HIGH Z INPUT/OUTPUT PINS

Some HC/HCT devices contain pins that serve both as
R1
inputs and outputs of digital logic. These pins are referred to
as digital I/O pins. The logic level applied to a control pin
INTERNAL
OUTPUT determines whether these I/O pins are selected as inputs or
CIRCUITRY
outputs.
R2 15 pF When I/O pins are selected as outputs, these pins may be
considered as standard CMOS outputs. When selected as
inputs, except for an increase in input leakage current and
input capacitance, these pins should be considered as
Figure 30. Model for Disabled Outputs standard CMOS inputs. These increases come from the fact
that a digital I/O pin is actually a combination of an input and
OPEN–DRAIN OUTPUTS
a 3–state output tied together (see Figure 33).
ON Semiconductor provides several devices that are As stated earlier, all HC/HCT inputs must be connected to
designed only to sink current to GND. These open–drain an appropriate logic level. This could pose a problem if an
output devices are fabricated using only an N–channel I/O pin is selected as an input while connected to an
transistor and a diode to VCC (Figure 31). The purpose of the improperly terminated bus.
diode is to provide ESD protection. Open–drain outputs can ON Semiconductor recommends terminating
be modeled as shown in Figure 32. HC/HCT–type buses with resistors to VCC or GND of
VCC between 1 kΩ to 1 MΩ in value. The choice of resistor value
is a trade–off between speed and power consumption (see
Bus Termination, this chapter).
Some ON Semiconductor devices have analog I/O pins.
These analog I/O pins should not be confused with digital
OUTPUT I/O pins. Analog I/O pins may be modeled as in Figure 34.
These devices can be used to pass analog signals, as well as
INTERNAL digital signals, in the same manner as mechanical switches.
CIRCUITRY

Figure 31. Open–Drain Output

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 not be able to drive the low value of termination used by
I/O
some buses. (This is another reason why an HCT device may
not be a drop in replacement for an LSTTL device.)
INTERNAL However, because low power operation is one of the main
CIRCUITRY reasons for using CMOS, an optimized CMOS bus
termination is usually advantageous.
BUS

Figure 33. Typical Digital I/O Pin

VCC VCC

HIGH Z
ENABLE INPUT
ANALOG Ron ANALOG (HIGH = 3–STATE)
I/O O/I

HIGH Z

GND OR VEE GND OR VEE

ENABLE INPUT
Figure 34. Analog I/O Pin (LOW = 3–STATE)

BUS TERMINATION Figure 35. Typical Bus Line with 3–State Bus Drivers
Because buses tend to operate in harsh, noisy
environments, most bus lines are terminated via a resistor to The choice of termination resistances is a trade–off
VCC or ground. This low impedance to VCC or ground between speed and power consumption. The speed of the
(depending on preference of a pull–up or pull–down logic bus is a function of the RC time constant of the termination
level) reduces bus noise pickup. In certain cases a bus line resistor and the parasitic capacitance associated with the
may be released (put in a high–impedance state) by disabling bus. Power consumption is a function of whether a pull–up
all the 3–state bus drivers (see Figure 35). In this condition or pull–down resistor is used and the output state of the
all HC/HCT inputs on the bus would be allowed to float. A device that has control of the bus (see Figure 36). The lower
CMOS input or 1/0 pin (when selected as an input) should the termination resistor the faster the bus operates, but more
never be allowed to float. (This is one reason why an HCT power is consumed. A large value resistor wastes less power,
device may not be a drop–in replacement of an LSTTL but slows the bus down. ON Semiconductor recommends a
device.) A floating CMOS input can put the device into the termination resistor value between 1 kΩ and 1 MΩ. An
linear region of operation. In this region excessive current alternative to a passive resistor termination would be an
can flow and the possibility of logic errors due to oscillation active–type termination (see Figure 37). This type
may occur (see Inputs, this chapter). Note that when a bus termination holds the last logic level on the bus until a driver
is properly terminated with pull–up resistors, HC devices, can once again take control of the bus. An active termination
instead of HCT devices, can be driven by an NMOS or has the advantage of consuming a minimal amount of power.
LSTTL bus driver. HC devices are preferred over HCT Most HC/HCT bus drivers do not have built–in hysteresis.
devices in bus applications because of their higher low level Therefore, heavily loaded buses can slow down rise and fall
input noise margin. (With a 5 V supply the typical HC switch signals and exceed the input rise/fall time defined in JEDEC
point is 2.3 V while the switch point of HCT is only 1.3 V.) Standard No. 7A. In this event, devices with
Some popular LSTTL bus termination designs may not Schmitt–triggered inputs should be used to condition these
work for HSCMOS devices. The outputs of HSCMOS may slow signals.

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 VCC

BUS
VCC VCC
I R I

(L) (H)

BUS
(a) USING A PULL-UP RESISTOR (b) USING A PULL-DOWN RESISTOR

Figure 36.
Transmission line distance becomes more critical as data
rates increase. As data rates increase, incident (and
reflective) waves begin to resemble that of RF transmission
line theory. However, due to the nonlinearity of CMOS
digital logic, conventional RF transmission theory is not
applicable.
HC devices are preferred over HCT devices due to the fact
that HC devices have higher switch points than HCT
devices. This higher switch point allows HC devices to
achieve better incident wave switching on lower impedance
lines.
HC/HCT may not have enough drive capability to
interface with some of the more popular LSTTL
transmission lines. (Possible reason why an HCT device
may not be a drop–in replacement of an equivalent TTL
device.) This does not pose a major problem since having
BUS LINES ENABLE
larger value termination resistors is desirable for CMOS
Figure 37. Using Active Termination (HC125) type transmission lines.
By increasing the termination resistance value, the CMOS
TRANSMISSION LINE TERMINATION advantage of low power consumption can be realized. ON
When data is transmitted over long distances, the line on Semiconductor recommends a minimum termination
which the data travels can be considered a transmission line. resistor value as shown in Figure 38. The termination
(Long distance is relative to the data rate being transmitted.) resistor should be as close to the receiving unit as possible.
Examples of transmission lines include high–speed buses, Another method of terminating the line driver, as well as the
long PCB lines, coaxial and ribbon cables. All transmission receiving unit, is shown in Figure 39. Note that the resistor
lines should be properly terminated into a low–impedance values in Figure 39 are twice the resistor value of Figure 38;
termination. A low–impedance termination helps eliminate this gives a net equivalent termination value of Figure 38.
noise, ringing, overshoot, and crosstalk problems. Also a Even higher values of resistors may be used for either
low–impedance termination reduces signal degradation termination method. This reduces power consumption, but
because the small values of parasitic line capacitance and at the expense of speed and possible signal degradation.
inductance have lesser effect on a low–impedance line.
The value of the termination resistor becomes a trade–off
between power consumption, data rate speeds, and
transmission line distance. The lower the resistor value, the
faster data can be presented to the receiving device, but the
more power the resistor consumes. The higher the resistor
value, the longer it will take to charge and discharge the
transmission line through the termination resistor (T = R •
C).

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 VCC V and have sufficient current to trigger the SCR. The
latch–up mechanism is similar for the inputs.
R1 Once a CMOS device is latched up, if the supply current
HSCMOS HSCMOS is not limited, the device can be destroyed or its reliability
(LINE DRIVER) (RECEIVER) can be degraded. Ways to prevent such an occurrence are
listed below.
R2 W
R1 = 1.5 k 1. Industrial controllers driving relays or motors is an
W
R1 = 1.0 k environment in which latch up is a potential problem.
Also, the ringing due to inductance of long
Figure 38. Termination Resistors at the Receiver
transmission lines in an industrial setting could
provide enough energy to latch up CMOS devices.
VCC VCC Opto–isolators, such as ON Semiconductor’s
MOC3011, are recommended to reduce chances of
R1 R3 latch up. See the ON Semiconductor Master Selection
Guide for a complete listing of ON Semiconductor
HSCMOS HSCMOS opto–isolators.
R2 R4
2. Ensure that inputs and outputs are limited to the
W maximum rated values.
v Vin v VCC +1.5 V referenced to GND or
R1 = R3 = 3.0 k
R2 = R4 = 2 kW – 1.5
– 0.5 v Vin v VCC +0.5 V referenced to GND
– 0.5 v Vout v VCC +0.5 V referenced to GND
Figure 39. Termination Resistors at

|Iin| v 20 mA
Both the Line Driver and Receiver

|Iout| v 25 mA for standard outputs

CMOS LATCH UP |Iout| v 35 mA for bus–driver outputs

Typically, HSCMOS devices do not latch up with currents 3. If voltage transients of sufficient energy to latch up the
of 75 mA forced into or out of the inputs or 300 mA for the device are expected on the inputs or outputs, external
outputs under worst case conditions (TA = 125_C and VCC protection diodes can be used to clamp the voltage.
= 6 V). Under dc conditions for the inputs, the input Another method of protection is to use a series resistor
protection network typically fails, due to grossly exceeding to limit the expected worst case current to the
the maximum input voltage rating of – 0.5 to VCC + 0.5 V maximum ratings value. See Handling Precautions
before latch–up currents are reached. For most designs, latch for other possible protection circuits and a discussion
up will not be a problem, but the designer should be aware of ESD prevention.
of it, what causes it, and how it can be prevented. 4. Sequence power supplies so that the inputs or outputs
Figure 40 shows the layout of a typical CMOS inverter of HSCMOS devices are not active before the supply
and Figure 41 shows the parasitic bipolar devices that are pins are powered up (e.g., recessed edge connectors
formed. The circuit formed by the parasitic transistors and and/or series resistors may be used in plug–in board
resistors is the basic configuration of a silicon controlled applications).
rectifier, or SCR. In the latch–up condition, transistors Q1 5. Voltage regulating and filtering should be used in
and Q2 are turned on, each providing the base current board design and layout to ensure that power supply
necessary for the other to remain in saturation, thereby lines are free of excessive noise.
latching the device on. Unlike a conventional SCR, where 6. Limit the available power supply current to the
the device is turned on by applying a voltage to the base of devices that are subject to latch–up conditions. This
the NPN transistor, the parasitic SCR is turned on by can be accomplished with the power–supply filtering
applying a voltage to the emitter of either transistor. The two network or with a current–limiting regulator.
emitters that trigger the SCR are the same point, the CMOS RECOMMENDED READING
output. Therefore, to latch up the CMOS device, the output Paul Mannone, “Careful Design Methods Prevent CMOS
voltage must be greater than VCC + 0.5 V or less than – 0.5 Latch–Up”, EDN, January 26, 1984.

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 P–CHANNEL N–CHANNEL
INPUT

VCC VCC P–CHANNEL N–CHANNEL GND

OUTPUT
OUTPUT OUTPUT

N+
FIELD OXIDE ÇÇÇ
P+ P+
FIELD OXIDE
N+
ÇÇ N+ P+
FIELD OXIDE

N – SUBSTRATE P – WELL

Figure 40. CMOS Wafer Cross Section

P–CHANNEL OUTPUT P – WELL RESISTANCE

Q1
P+
VCC
P+ P– GND
N–
P–
VCC
N– N+ N+ GND
Q2
N – SUBSTRATE RESISTANCE N–CHANNEL OUTPUT

Figure 41. Latch–Up Circuit Schematic

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 MAXIMUM POWER DISSIPATION Worst–case ICC occurs at VCC = 6.0 V. The value of ICC
at VCC = 6.0 V, as specified in the data sheets, is used for all
The maximum power dissipation for ON Semiconductor power supply voltages from 2 to 6 V.
HSCMOS packages is 750 mW for both ceramic and plastic
DIPs and 500 mW for SOIC packages. The deratings are – HCT QUIESCENT POWER DISSIPATION
10 mW/_C from 65_C for plastic DIPs, and – 7 mW/_C from Although HCT devices belong to the CMOS family, their
65_C for SOIC packages. This is illustrated in Figure 42. input voltage specifications are identical to those of LSTTL.
HCT parts can therefore be either judiciously substituted for
PD, MAXIMUM PACKAGE POWER DISSIPATION (mW)

800 or mixed with LS devices in a system.

TTL output voltages are VOL = 0.4 V (max) and
700
SOIC PLASTIC
VOH = 2.4 to 2.7 V (min).
600 PACKAGE DIP Slightly higher ICC current exists when an HCT device is
driven with VOL = 0.4 V (max) because this voltage is high
500
enough to partially turn on the N–channel transistor.
400 However, when being driven with a TTL VOH, HCT devices
exhibit large additional current flow (∆ICC) as specified on
300 TSSOP
PACKAGE
HCT device data sheets. ∆ICC current is caused by the
200 off–rail input voltage turning on both the P and N channels
of the input buffer. This condition offers a relatively low
100
impedance path from VCC to GND. Therefore, the HCT
quiescent power dissipation is dependent on the number of
– 40 0 40 80 120
inputs applied at the TTL VIH logic voltage level.
TA, AMBIENT TEMPERATURE (°C)
The equation for HCT quiescent power dissipation is
Figure 42. Maximum Package Power given by:
Dissipation versus Temperature PD = ICCVCC + η∆ICCVCC
where η = the number of inputs at the TTL VIH level.
Internal heat generation in HSCMOS devices comes from
two sources, namely, the quiescent power and dynamic HC AND HCT DYNAMIC POWER DISSIPATION
power consumption. Dynamic power dissipation is calculated in the same way
In the quiescent state, either the P–channel or N–channel for both HC and HCT devices. The three major factors
transistor in each complementary pair is off except for small which directly affect the magnitude of dynamic power
source–to–drain leakage due to the inputs being either at dissipation are load capacitance, internal capacitance, and
VCC or ground. Also, there are the small leakage currents switching transient currents.
flowing in the reverse–biased input protection diodes and The dynamic power dissipation due to capacitive loads is
the parasitic diodes on the chip. The specification which given by the following equation:
takes all leakage into account is called Maximum Quiescent PD = CLVCC2f
Supply Current (per package), or ICC, and is shown on all
data sheets. where PD = power in µW, CL = capacitive load in pF,
The three factors which directly affect the value of V CC = supply voltage in volts, and f = output frequency
quiescent power dissipation are supply voltage, device driving the load capacitor in MHz.
complexity, and temperature. On the data sheets, ICC is All CMOS devices have internal parasitic capacitances
specified only at VCC = 6.0 V because this is the worst–case that have the same effect as external load capacitors. The
supply voltage condition. Also, larger or more complex magnitude of this internal no–load power dissipation
devices consume more quiescent power because these capacitance, CPD, is specified as a typical value.
devices contain a proportionally greater reverse–biased Finally, switching transient currents affect the dynamic
diode junction area and more off (leaky) FETs. power dissipation. As each gate switches, there is a short
Finally, as can be seen from the data sheets, temperature period of time in which both N– and P–channel transistors
increases cause ICC increases. This is because at higher are partially on, creating a low–impedance path from VCC
temperatures, leakage currents increase. to ground. As switching frequency increases, the power
dissipation due to this effect also increases.
HC QUIESCENT POWER DISSIPATION The dynamic power dissipation due to CPD and switching
When HC device inputs are virtually at VCC or GND transient currents is given by the following equation:
potential (as in a totally CMOS system), quiescent power
PD = CPDVCC2f
dissipation is minimized. The equation for HC quiescent
power dissipation is given by: Therefore, the total dynamic power dissipation is given
by:
PD = VCCICC

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 PD = (CL + CPD)VCC2f TJ = TA + PD(θJA) (2)
Total power dissipation for HC and HCT devices is merely where
a summation of the dynamic and quiescent power TJ = maximum junction temperature
dissipation elements. When being driven by CMOS logic
TA = maximum ambient temperature
voltage levels (rail to rail), the total power dissipation for
both HC and HCT devices is given by the equation: PD = calculated maximum power dissipation
including effects of external loads (see Power
PD = VCCICC + (CL + CPD)VCC2f Dissipation on page 40).
When being driven by LSTTL logic voltage levels, the θJC = average thermal resistance, junction to case
total power dissipation for HCT devices is given by the θCA = average thermal resistance, case to ambient
equation:
θJA = average thermal resistance, junction to ambient
PD = VCCICC + VCC∆ICC(δ, + δ2 + … + δn)
This ON Semiconductor recommended formula has been
+ (CL + CPD)VCC2f approved by RADC and DESC for calculating a “practical”
where δn = duty cycle of LSTTL output applied to each input maximum operating junction temperature for
of an HCT device. MIL-M-38510 (JAN) devices.
Only two terms on the right side of equation ( 1 ) can be
THERMAL MANAGEMENT varied by the user — the ambient temperature, and the
Circuit performance and long-term circuit reliability are device case-to-ambient thermal resistance, θCA. (To some
affected by die temperature. Normally, both are improved by extent the device power dissipation can also be controlled,
keeping the IC junction temperatures low. but under recommended use the VCC supply and loading
Electrical power dissipated in any integrated circuit is a dictate a fixed power dissipation.) Both system air flow and
source of heat. This heat source increases the temperature of the package mounting technique affect the θCA thermal
the die relative to some reference point, normally the resistance term. θJC is essentially independent of air flow
ambient temperature of 25°C in still air. The temperature and external mounting method, but is sensitive to package
increase, then, depends on the amount of power dissipated material, die bonding method, and die area.
in the circuit and on the net thermal resistance between the For applications where the case is held at essentially a
heat source and the reference point. See page 29 for the fixed temperature by mounting on a large or temperature-
calculation of CMOS power consumption. controlled heat sink, the estimated junction temperature is
The temperature at the junction is a function of the calculated by:
packaging and mounting system’s ability to remove heat TJ = TC + PD(θJC) (3)
generated in the circuit — from the junction region to the where TC = maximum case temperature and the other
ambient environment. The basic formula for converting parameters are as previously defined.
power dissipation to estimated junction temperature is: The maximum and average θJC resistance values for
TJ = TA + PD(θJC + θCA) (1) standard IC packages are given in 2.
or

Table 2. Thermal Resistance Values for Standard I/C Packages

Thermal Resistance In Still Air
Package Description
θJC (°C/Watt)
No. Body Body Body Die Die Area Flag Area
Leads Style Material W×L Bonds (Sq. Mils) (Sg. Mils) Avg. Max.
14 DIL Epoxy 1/4″ × 3/4″ Epoxy 4096 6,400 38 61
16 DIL Epoxy 1/4″ × 3/4″ Epoxy 4096 12,100 34 54
20 DIL Epoxy 0.35″ × 0.35″ Epoxy 4096 14,400 N/A N/A
NOTES:
1. All plastic packages use copper lead frames.
2. Body style DIL is “Dual-In-Line.”
3. Standard Mounting Method: Dual-In-Line Socket or P/C board with no contact between bottom of package and socket or P/C board.

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AIR FLOW device in the system should be evaluated for maximum
The effect of air flow over the packages on θJA (due to a junction temperature. Knowing the maximum junction
decrease in θCA) reduces the temperature rise of the temperature, refer to 4 or Equation ( 1 ) on page 41 to
package, therefore permitting a corresponding increase in determine the continuous operating time required to 0.1%
power dissipation without exceeding the maximum bond failures due to intermetallic formation. At this time,
permissible operating junction temperature. system reliability departs from the desired value as indicated
Even though different device types mounted on a printed in Figure 43.
circuit board may each have different power dissipations, all Air flow is one method of thermal management which
will have the same input and output levels provided that each should be considered for system longevity. Other commonly
is subject to identical air flow and the same ambient air used methods include heat sinks for higher powered devices,
temperature. This eases design, since the only change in refrigerated air flow and lower density board stuffing. Since
levels between devices is due to the increase in ambient θCA is entirely dependent on the application, it is the
temperatures as the air passes over the devices, or responsibility of the designer to determine its value. This can
differences in ambient temperature between two devices. be achieved by various techniques including simulation,
The majority of users employ some form of air-flow modeling, actual measurement, etc.
cooling. As air passes over each device on a printed circuit The material presented here emphasizes the need to
board, it absorbs heat from each package. This heat gradient consider thermal management as an integral part of system
from the first package to the last package is a function of the design and also the tools to determine if the management
air flow rate and individual package dissipations. 3 provides methods being considered are adequate to produce the
gradient data at power levels of 200 mW, 250 mW, 300 mW, desired system reliability.
and 400 mW with an air flow rate of 500 Ifpm. These figures
show the proportionate increase in the junction temperature 4. Device Junction Temperature versus
of each dual in-line package as the air passes over each Time to 0.1% Bond Failures
device. For higher rates of air flow the change in junction
temperature from package to package down the airstream Junction
Temperature °C Time, Hours Time, Years
will be lower due to greater cooling.
80 1,032,200 117.8
3. Thermal Gradient of Junction Temperature 90 419,300 47.9
(16-Pin Dual-In-Line Package)
100 178,700 20.4
Power Dissipation Junction Temperature Gradient 110 79,600 9.4
(mW) (°C/Package)
120 37,000 4.2
200 0.4
130 17,800 2.0
250 0.5
140 8,900 1.0
300 0.63
400 0.88
NORMALIZED FAILURE RATE

FAILURE RATE OF PLASTIC = CERAMIC

Devices mounted on 0.062″ PC board with Z axis spacing of 0.5″.
UNTIL INTERMETALLICS OCCUR
Air flow is 500 lfpm along the Z axis.
TJ = 130 ° C

TJ = 120° C

TJ = 110° C

TJ = 100 ° C

TJ = 80 ° C
TJ = 90 ° C

4 is graphically illustrated in Figure 43 which shows that

the reliability for plastic and ceramic devices is the same
until elevated junction temperatures induce intermetallic
1
failures in plastic devices. Early and mid-life failure rates of
plastic devices are not effected by this intermetallic
1 10 100 1000
mechanism.
TIME, YEARS
PROCEDURE
After the desired system failure rate has been established Figure 43. Failure Rate versus Time
Junction Temperature
for failure mechanisms other than intermetallics, each

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 CAPACITIVE LOADING EFFECTS tPT = tP + 0.5 VCC (CL – 50 pF) / IOS
ON PROPAGATION DELAY where tPT = total propagation delay
tp = specified propagation delay with 50 pF load
In addition to temperature and power–supply effects,
CL = actual load capacitance
capacitive loading effects should be taken into account. The
IOS = short circuit current (5)
additional propagation delay may be calculated if the short
circuit current for the device is known. Expected minimum An example is given here for tPHL of the 74HC00 driving a
numbers may be determined from 5. 150 pF load.
From the equation VCC = 4.5 V
Cdvc tPHL (50 pF) = 18 ns
i=
dt
CL = 150 pF
this approximation follows: IOS = 17.3 mA
C∆V
I= (0.5)(4.5 V)(150 pF – 50 pF)
∆t tPHL (150 pF) = 18 ns +
17.3 mA
so
= 18 ns + 13 ns
C∆V
∆t = = 31 ns
I
or Another example for CL = 0 pF and all other parameters the
same.
C(0.5 VCC)
∆t = (0.5)(4.5 V)(0 pF – 50 pF)
I tPHL (0 pF) = 18 ns +
17.3 mA
because the propagation delay is measured to the 50% point
of the output waveform (typically 0.5 VCC). = 18 ns + (– 6.5 ns)
This equation gives the general form of the additional
tPHL = 11.5 ns
propagation delay. To calculate the propagation delay of a
device for a particular load capacitance, CL, the following This method gives the expected propagation delay and is
equation may be used. intended as a design aid, not as a guarantee.

ÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Table 5. Expected Minimum Short Circuit Currents*

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ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
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Standard Drivers Bus Drivers

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Parameter VCC 25_C 85_C 125_C 25_C 85_C 125_C Unit

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ÎÎÎ
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ÎÎÎ
Output Short Circuit Source Current 2.0 1.89 1.83 1.80 3.75 3.64 3.60 mA
4.5 18.5 15.0 13.4 37.0 30.0 26.6

ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Short Circuit Sink Current
6.0
2.0
35.2
1.55
28.0
1.55
24.6
1.55
70.6
2.45
56.1
2.45
49.2
2.43 mA

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ÎÎÎÎ
ÎÎÎÎ
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4.5 17.3 14.0 12.5 27.2 22.1 19.6
6.0 33.4 26.5 23.2 52.6 41.7 36.5
*These values are intended as design aids, not as guarantees.

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 TEMPERATURE EFFECTS ON SUPPLY VOLTAGE EFFECTS ON DRIVE
DC AND AC PARAMETERS CURRENT AND PROPAGATION DELAY

One of the inherent advantages of CMOS devices is that The transconductive gain, lout/Vin, of MOSFETs is
characteristics of the N– and P–channel transistors, such as proportional to the gate voltage minus the threshold voltage,
drive current, channel resistance, propagation delay, and V G – V T. The gate voltage at the input of the final stage of
output transition time, track each other over a wide buffered devices is approximately the power supply voltage,
temperature range. Figure 44 shows the temperature V CC or GND. Because V G = V CC or GND, the output drive
relationships for these parameters. To illustrate the effects of current is proportional to the supply voltage. Propagation
temperature on noise margin, Figure 45 shows the typical delays for CMOS devices are also affected by the power
transfer characteristics for devices with buffered inputs and supply voltage, because most of the delay is due to charging
outputs. Note that the typical switch point is at 45% of the and discharging internal capacitances. Figure 46 and

v
supply voltage and is minimally affected by temperature. Figure 47 show the typical variation of current drive and

v
The graphs in this section are intended to be design aids, propagation delay, normalized to V CC = 4.5 V for 2.0
not guarantees. V CC 6.0 V. These curves may be used with the tables on
each data sheet to arrive at parametric values over the
1.5 voltage range.
TYPICAL IOH, t PLH, t PHL, t TLH, t THL, RC,

1.8

I OH, I OL, TYPICAL OUTPUT DRIVE CURRENT

NORMALIZED TO 25 °C VALUE

1.6

(NORMALIZED TO 4.5 V NUMBER)

1.4
1.0
1.2

1.0

IOH, IOL 0.8

RC, tPLH, tPHL, tTLH, tTHL 0.6
0.5
–50 0 50 100 150 0.4
TA, AMBIENT TEMPERATURE (°C)
0.2
2.0 3.0 4.0 5.0 6.0
Figure 44. Characteristics of Drive Current, VCC, POWER SUPPLY VOLTAGE (V)
Channel Resistance, and AC Parameters
Over Temperature Figure 46. Drive Current versus VCC

5.0
VCC = 5 Vdc
tPLH , t PHL, TYPICAL PROPAGATION DELAY

4.0
Vout , OUTPUT VOLTAGE (V)

CL = 50 pF
(NORMALIZED TO 4.5 V NUMBER)

TA = –55°C TA = 125°C 3.0

3.0

2.0
VIL VIH 2.0
TA = 25°C
1.0
1.0
0
0 1.0 2.0 3.0 4.0 5.0
Vin, INPUT VOLTAGE (V)
2.0 3.0 4.0 5.0 6.0
Figure 45. Temperature Effects on the HC VCC, POWER SUPPLY VOLTAGE (V)
Transfer Characteristics
Figure 47. Propagation Delay versus VCC

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 DECOUPLING CAPACITORS

V out
The switching waveforms shown in Figure 48 and
Figure 49 show the current spikes introduced to the power
supply and ground lines. This effect is shown for a load
capacitance of less than 5 pF and for 50 pF. For ideal power
supply lines with no series impedance, the spikes would

ICC
pose no problem. However, actual power supply and ground
lines do possess series impedance, giving rise to noise
problems. For this reason, care should be taken in board
layouts, ensuring low impedance paths to and from logic

IGND
devices.
To absorb switching spikes, the following HSCMOS
devices should be bypassed with good quality 0.022 µF to BUFFERED DEVICE: INPUT tr, tf ≤ 500 ns, CL < 5 pF
0.1 µF decoupling capacitors:
Figure 48. Switching Currents for CL < 5 pF
1. Bypass every device driving a bus with all outputs
switching simultaneously.

V out
2. Bypass all synchronous counters.
3. Bypass devices used as oscillator elements.
4. Bypass Schmitt–trigger devices with slow input rise
and fall times. The slower the rise and fall time, the

ICC
larger the bypass capacitor. Lab experimentation is
suggested.
Bypass capacitors should be distributed over the circuit
board. In addition, boards could be decoupled with a 1 µF
capacitor.
IGND

BUFFERED DEVICE: INPUT tr, tf ≤ 500 ns, CL < 5 pF

Figure 49. Switching Currents for CL = 50 pF

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 INTERFACING VCC

HSCMOS devices have a wide operating voltage range

(VCC = 2 to 6 V) and sufficient current drive to interface with
most other logic families available today. In this section,
various interface schemes are given to aid the designer (see
Figure 50 through Figure 55). The various types of CMOS GND
devices with their input/output levels and comments are LSTTL PULL-UP HC
given in 6. DEVICE RESISTOR DEVICE
ON Semiconductor presently has available several Figure 52. LSTTL to HC Interfacing
CMOS memories and microprocessors (see 7) which are
designed to directly interface with High–Speed CMOS. 5V 3V
With these devices now available, the designer has an
attractive alternative to LSTTL/NMOS, and a total
HSCMOS system is now possible. (See SG102, CMOS
System IC Selection Guide, for more information.)
Device designators are as follows:

HC This is a high–speed CMOS device with CMOS input switching GND GND
LSTTL HC4049 HC
levels and buffered CMOS outputs. The numbering of devices
DEVICE OR DEVICE
with this designator follows the LSTTL numbering sequence.
HC4050
These devices are functional and pinout equivalents of LSTTL
devices (e.g., HC00A, HC245A, etc.). Exceptions to this are Figure 53. LSTTL to Low–Voltage HSCMOS
devices that are functional and pinout equivalents to metal–gate
CMOS devices (e.g., HC4066, HC4538A, etc.).
VDD = 3 –15 V* VCC = 2 – 6 V
HCU This is an unbuffered high–speed CMOS device with only one
stage between the input and output. Because this is an unbuffered
device, input and output levels may differ from buffered devices.
At present, the family contains only one unbuffered device, the
HCU04A.
HCT This is a high–speed CMOS device with an LSTTL–to–CMOS
input buffer stage. These devices are designed to interface with
LSTTL outputs operating at VCC = 5 V ± 10%. HCT devices have GND
fully buffered CMOS outputs that directly drive HSCMOS or STANDARD MC14049UB/14050B HC
LSTTL devices. CMOS DEVICE
*VOH must be greater than VIH of low voltage Device;
VCC VDD = 3 – 18 V may be used if interfacing to 14049UB/14050B.
Figure 54. High Voltage CMOS to HSCMOS

VCC/VDD VDD/VCC

GND
HC OR HCT DIRECT LSTTL LEVEL
GND
DEVICE INTERFACE DEVICE SHIFTER
Figure 50. HC to LSTTL Interfacing

GND MC14504B
VCC HSCMOS/ STANDARD CMOS/
STANDARD CMOS HSCMOS
Figure 55. Up/Down Level Shifting Using
the MC14504B

GND
LSTTL DIRECT HCT
DEVICE INTERFACE DEVICE
Figure 51. LSTTL to HCT Interfacing

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46
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Table 6. Interfacing Guide

ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Device Input Level Output Level Comments

ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HCXXX CMOS CMOS LSTTL Functional and Pinout Equivalent Devices
HC4XXX CMOS CMOS CMOS Functional and Pinout Equivalent Devices

ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
HCUXX

ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CMOS CMOS Used in Linear Applications

v v ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
HCTXXX TTL CMOS HSCMOS Device with TTL–to–CMOS Input Buffering

ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
MC14049UB

ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
MC14050B ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
– 0.5

ÎÎÎÎÎ
Vin 18 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CMOS Metal–Gate CMOS High–to–Low Level Translators, CMOS Switching
Levels

ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14504B CMOS or TTL CMOS Metal–Gate CMOS High–to–Low or Low–to–High Level Translator

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Table 7. CMOS Memories and Microprocessors RECOMMENDED READING
S. Craig, “Using High–Speed CMOS Logic for

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
CMOS

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Memories CMOS Microprocessors
Microprocessor Interfacing”, Application Note–868, ON
Semiconductor Products Inc., 1982.

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
MCM6147 MC68HC01 MC146805G2
MCM61L47 MC68HC03 MC146805H2

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
MCM68HC34 MC68HC11A8 MC1468705F2

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC68HC11D4 MC1468705G2
MC68HC811A2 MC68HC05C4

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC68HC811D4 MC68HSC05C4

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC68HC04P3 MC68HC05C8
MC146805E2 MC68HC805C4

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC146805F2 MC68HC000

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47
 TYPICAL PARAMETRIC VALUES variation to the end user. However, this does not hold true for
the mean value of the total devices processed. The mean
Given a fixed voltage and temperature, the electrical value, commonly referred to as a typical value, shifts over
characteristics of High–Speed CMOS devices depend processing and therefore varies from lot to lot or even wafer
primarily on design, layout, and processing variations to wafer within a lot.
inherent in semiconductor fabrication. As with all processing or manufacturing, the total devices
A preliminary evaluation of each device type essentially being produced fit the normal distribution or bell curve of
guarantees that the design and layout of the device conforms Figure 56. In order to guarantee a valid typical value, a
to the criteria and standards set forth in the design goals. typical number plus a tolerance, would have to be specified
With very few exceptions, device electrical parameters, and tested (see Figure 57). However, this would greatly
once established, do not vary due to design and layout. increase processing costs which would have to be absorbed
Of much more concern is processing variation. A digital by the consumer.
processing line is allowed to deviate over a fairly broad In some cases, the device’s actual values are so small that
processing range. This allows the manufacturer to incur the resolution of the automatic test equipment determines
reduced processing costs. These reduced processing costs the guaranteed limit. An example of this is quiescent supply
are passed on to the consumer in the form of lower device current and input leakage current.
prices. Most manufacturers provide typical numbers by one of
Processing variation is the range from worst case to best two methods. The first method is to simply double or halve,
case processing and is defined as the process window. This depending on the parameter, the guaranteed limit to
window is established with the aid of statistical process determine a typical number. This would theoretically put all
control (SPC). With SPC, when a processing parameter processed lots in the middle of the process window. Another
approaches the process window limit, that parameter is approach to typical numbers is to use a typical value that is
adjusted toward the middle of the window. This keeps derived from the aforementioned experimental lots.
process variations within a predetermined tolerance. However, neither method accurately reflects the mean value
ON Semiconductor characterizes each device type over of devices any one consumer can expect to receive.
this process window. Each device type is characterized by Therefore, the use of typical parametric numbers for
allowing experimental lots to be processed using worst case design purposes does not constitute sound engineering
and best case processing. The worst case processed lots design practice. Worst case analysis dictates the use of
usually determine the minimum or maximum guaranteed guaranteed minimum or maximum values. The only
limit. (Whether the limit is a guaranteed minimum or possible exception would be when no guaranteed value is
maximum depends on the particular parameter being given. In this case a typical value may be used as a ballpark
measured.) figure.
In production, these limits are guaranteed by probe and
final test and therefore appear independent of process
MIN MAX
LIMIT LIMIT
REJECT REJECT
REGION REGION

(a) (b)
Figure 56.

MEAN (TYP)
VALUE

MIN MAX
REJECT VALUE VALUE REJECT
REGION REGION

Figure 57.

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48
 REDUCTION OF ELECTROMAGNETIC stainless steel fiber–filled polycarbonate, aluminum
INTERFERENCE (EMI) flake–filled polycarbonate/ABS coated with nickel and
copper electrolysis plating or cathode sputtering, nickel
Electromagnetic interference (EMI) and radio frequency coated graphite fiber, and polyester SMC with carbon–fiber
interference (RFI) are phenomena inherent in all electrical veil. Several manufacturers who make conductive
systems covering the entire frequency spectrum. Although compounds and additives are listed below.
the characteristics have been well documented, EMI
remains difficult to deal with due to numerous variables. SHIELDING MANUFACTURERS
EMI should be considered at the beginning of a design, and General Electric Co., Plastics Group, Pittsfield, MA
taken into account during all stages, including production Mobay Chemical Corp., Pittsburgh, PA
and beyond. Wilson–Fiberfil International, Evansville, IN
These entities must be present for EMI to be a factor: (1) American Cyanamid Co., Wayne, NJ
a source of EMI, (2) a transmission medium for EMI, and (3)
Fillite U.S.A., Inc., Huntington, WV
a receiver of EMI. Several sources include relays, FM
transmitters, local oscillators in receivers, power lines, Transnet Corp., Columbus, OH
engine ignitions, arc welders, and lighting. EMI ON Semiconductor does not recommend, or in any way
transmission paths include ground connections, cables, and warrant the manufacturers listed here. Additionally, no
the space between conductors. Some receivers of EMI are claim is made that this list is by any means complete.
radar receivers, computers, and television receivers.
RECOMMENDED READING
For microprocessor based equipment, the source of
emissions is usually a current loop on a PC board. The chips D. White, K. Atkinson, and J. Osburn, “Taming EMI in
and their associated loop areas also function as receivers of Microprocessor Systems”, IEEE Spectrum, Vol. 22,
EMI. The fact is that PC boards which radiate high levels of Number 12, Dec. 1985.
EMI are also more likely to act as receivers of EMI. D. White and M. Mardiguian, EMI Control Methodology
All logic gates are potential transmitters and receivers of and Procedures, 1985.
emissions. Noise immunity and noise margin are two H. Denny, Grounding for the Control of EMI.
criterion which measure a gate’s immunity to noise which M. Mardiguian, How to Control Electrical Noise.
could be caused by EMI. CMOS technology, as opposed to D. White, Shielding Design Methodology and Procedures.
the other commonly used logic families, offers the best value For more information on this subject, contact:
Interference Control Technologies
for noise margin, and is therefore an excellent choice when
Don White Consultants, Inc., Subsidiary
considering EMI. State Route 625
The electric and magnetic fields associated with ICs are P.O. Box D
proportional to the current used, the current loop area, and Gainesville, VA 22065
the switching transition times. CMOS technology is
preferred due to smaller currents. Also, the current loop area HYBRID CIRCUIT GUIDELINES
can be reduced by the use of surface mount packages.
In a system where several pieces of equipment are High–Speed CMOS devices, when purchased in chip
connected by cables, at least five coupling paths should be (die) form, are useful in hybrid circuits. Most high–speed
taken into account to reduce EMI. They are: (1) common devices are fabricated with P wells and N substrates.
ground impedance coupling (a common impedance is Therefore, the substrates should be tied to VCC (+ supply).
shared between an EMI source and receiver), (2) Several devices however, are fabricated with N wells and
common–mode, field–to–cable coupling (electromagnetic P substrates. In this case, the substrates should be tied to
fields enter the loop found by two pieces of equipment, the GND. The best solution to alleviate confusion about the
cable connecting them, and the ground plane), (3) substrate is the use of nonconductive or insulative
differential–mode, field–to–cable coupling substrates. This averts the necessity of tying the substrate off
(electromagnetic fields enter the loop formed by two pieces to either VCC or GND.
of equipment and the cable connecting them), (4) crosstalk For more information on hybrid technology, contact:
coupling (signals in one transmission line are coupled into International Society for Hybrid Microelectronics
another transmission line), and (5) a conductive path P.O. Box 3255
through power lines. Montgomery, AL 36109
Shielding is a means of reducing EMI. Some of the more
commonly used shields against EMI and RFI contain

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 SCHMITT–TRIGGER DEVICES up signals with long rise and fall times. Positive–going input
noise excursions must rise above the VT+ threshold before
Schmitt–trigger devices exhibit the effect of hysteresis. they affect the output. Similarly, negative–going input noise
Hysteresis is characterized by two different switching excursions must drop below the VT– threshold before they
threshold levels, one for positive–going input transitions affect the output.
and the other for negative–going input transitions. The HC132A can be used as a direct replacement for the
Schmitt triggers offer superior noise immunity when HC00A NAND gate, which does not have Schmitt–trigger
compared to standard gates and inverters. Applications for capability. The HC132A has the same pin assignment as the
Schmitt triggers include line receivers, sine to square wave HC00A. Schmitt–trigger logic elements act as standard
converters, noise filters, and oscillators. ON Semiconductor logic elements in the absence of noise or slow rise and fall
offers six versatile Schmitt–trigger devices in the times, making direct substitution possible.
High–Speed CMOS logic family (see 8). Versatility and low cost are attractive features of CMOS
The typical voltage transfer characteristics of a standard Schmitt triggers. With six Schmitt triggers per HC14A
CMOS inverter and a CMOS Schmitt–trigger inverter are package, one trigger can be used for a noise elimination
compared in Figure 58 and Figure 59. The singular transfer application while the other five function as standard
threshold of the standard inverter is replaced by two distinct inverters. Similarly, each of the four triggers in the HC132A
thresholds in a Schmitt–trigger inverter. During a can be used as either Schmitt triggers or NAND gates or
positive–going transition of Vin, the output begins to go low some combination of both.
after the VT+ threshold is reached. During a negative–going

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin transition, Vout begins to go high after the VT– threshold Table 8. Schmitt–Trigger Devices
is reached. The difference between VT+ and VT– is defined

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
HC14A Hex Schmitt–Trigger Inverter
as VH, the hysteresis voltage.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
HCT14A Hex Schmitt–Trigger Inverter with LSTTL Inputs
As a direct result of hysteresis, Schmitt–trigger circuits HC132A Quad 2–Input NAND Gate with Schmitt–Trigger

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
provide excellent noise immunity and the ability to square Inputs

VCC

Vout

0 Vin VCC

Figure 58. Standard Inverter Transfer Characteristic

VCC

VT– VT+
Vout

VH

0 Vin VCC

Figure 59. Schmitt–Trigger Inverter Transfer Characteristic

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OSCILLATOR DESIGN WITH HIGH–SPEED CMOS Certain constraints must be met while designing this type
of oscillator. Stray capacitance and inductance must be kept
Oscillator design is a fundamental requirement of many to a minimum by placing the passive components as close to
systems and several types are discussed in this section. In the chip as possible. Also, at higher frequencies, the
general, an oscillator is comprised of two parts: an active HCU04A’s propagation delay becomes a dominant effect
network and a feedback network. The active network is and affects the cycle time. A polystyrene capacitor is
usually in the form of an amplifier, or an unbuffered inverter, recommended for optimum performance.
such as the HCU04. The feedback network is mainly
comprised of resistors, capacitors, and depending upon the CRYSTAL OSCILLATORS
application, a quartz crystal or ceramic resonator. Crystal oscillators provide the required stability and
Buffered inverters are never recommended in oscillator accuracy which is necessary in many applications. The
applications due to their high gain and added propagation crystal can be modeled as shown in Figure 62.
delay. For this reason ON Semiconductor manufactures the The power dissipated in a crystal is referred to as the drive
HCU04A, which is an unbuffered hex inverter. level and is specified in mW. At low drive levels, the
Oscillators for use in digital systems fall into two general resonant resistance of the crystal can be so large as to cause
categories, RC oscillators and crystal or ceramic resonator start–up problems. To overcome this problem, the amplifier
oscillators. Crystal oscillators have the best performance, (inverter) should provide enough amplification, but not too
but are more costly, especially for nonstandard frequencies. much as to overdrive the crystal.
RC oscillators are more useful in applications where Figure 61 shows a Pierce crystal oscillator circuit, which
stability and accuracy are not of prime importance. Where is a popular configuration with CMOS.
high performance at low frequencies is desired, ceramic
resonators are sometimes used. 1/6 HCU04A 1/6 HCU04A
OSCin OSCout1 OSCout2
RC OSCILLATORS
The circuit in Figure 60 shows a basic RC oscillator using
Rf BUFFER
the HCU04A. When the input voltage of the first inverter
reaches the threshold voltage, the outputs of the two
inverters change state, and the charging current of the
capacitor changes direction. The frequency at which this R1
circuit oscillates depends upon R1 and C. The equation to
calculate these component values is given in Figure 60. C1 C2

1/6 HCU04A 1/6 HCU04A BUFFER

Figure 61. Pierce Crystal Oscillator Circuit
Vout

Choosing R1
R2 R1  
C 2R1 R2 10 R1 Power is dissipated in the effective series resistance of the

C 100 pF crystal. The drive level specified by the crystal manufacturer
1kW  W R1 1 M is the maximum stress that a crystal can withstand without
+
f OSC 1
2.3 R1•C damage or excessive shift in frequency. R1 limits the drive
level.
Figure 60. RC Oscillator

Rs Ls Cs

1 2 1 2 1 Re Xe 2

Co

Values are supplied by the crystal manufacturer

(parallel resonant crystal)

Figure 62. Equivalent Crystal Networks

To verify that the maximum dc supply voltage does not supply voltage is increased. An overdriven crystal decreases
overdrive the crystal, monitor the output frequency at OSC in frequency or becomes unstable with an increase in supply
Out 2. The frequency should increase very slightly as the dc voltage. The operating supply voltage must be reduced or RI

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must be increased in value if the overdriven condition exists. A good power distribution network is essential before
The user should note that the oscillator start–up time is decoupling can provide any noise reduction. Avoid using
proportional to the value of R1. jumpers for ground and power connections; the inductance
they introduce into the lines permits coupling between
Selecting Rf outputs. Therefore, use of PC boards with premanufactured
The feedback resistor (Rf) typically ranges up to 20 MD. ground connections is advised to connect the device pins to
Rf determines the gain and bandwidth of the amplifier. ground.
Proper bandwidth ensures oscillation at the correct However, the optimum solution is to use multi–layer PC
frequency plus roll–off to minimize gain at undesirable boards where different layers are used for the supply rails
frequencies, such as the first overtone. Rf must be large and interconnections. Even with double–sided boards,
enough so as not to affect the phase of the feedback network placing the power and ground lines on opposite sides of the
in an appreciable manner. board whenever possible is recommended. The multi–wire
RECOMMENDED READING board is a less expensive approach than the multi–layer PC
D. Babin, “Designing Crystal Oscillators”, Machine board, while retaining the same noise reduction
Design, March 7, 1985. characteristics. As a rule of thumb, there should be several
D. Babin, “Guidelines for Crystal Oscillator Design”, ground pins per connector to give good ground distribution.
Machine Design, April 25, 1985. The precautions for ground lines also apply to VCC lines:
1) separate power stabilization for each board; 2) isolate
PRINTED CIRCUIT BOARD LAYOUT noise sources; and 3) avoid the use of large, single voltage
regulators.
Noise generators on the power supply lines should be After all of these precautions, decoupling is an added
decoupled. The two major sources of noise on the power measure to reduce supply noise. See the Decoupling
supply lines are peak current in output stages during Capacitors section.
switching and the charging and discharging of parasitic
capacitances.

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 Definitions and Glossary of Terms
HC vs. HCT VCC Positive Supply Voltage — + dc supply voltage
(referenced to GND). The voltage range over which
ON Semiconductor’s High–Speed CMOS is intended to ICs are functional.
give the designer an alternative to LSTTL. HSCMOS, with Vin Input Voltage — DC input voltage (referenced to
the faster speed advantage over metal–gate CMOS GND).
(MC14000 series) and the lower power consumption Vout Output Voltage — DC output voltage (referenced to
advantage over LSTTL, is an optimum choice for new GND).
midrange designs. With the advent of high–speed CMOS
microprocessors and memories, the ability to design a 100% VIH Minimum High Level Input Voltage — The worst
CMOS system is now possible. case voltage that is recognized by a device as the
HCT devices offer a short–term solution to the HIGH state.
TTL/NMOS–to–CMOS interface problem. To achieve this VIL Maximum Low Level Input Voltage — The worst
interface capability, some CMOS advantages had to be case voltage that is recognized by a device as the LOW
compromised. These compromises include power state.
consumption, operating voltage range, and noise immunity. VOH Minimum High Level Output Voltage — The worst
In most cases HCT devices are drop–in replacements of case high–level voltage at an output for a given output
TTL devices with significant advantages over the TTL current (lout) and supply voltage (VCC).
devices. However, in some cases, an equivalent HCT device VOL Maximum Low Level Output Voltage — The worst
may not replace a TTL device without some form of circuit case low–level voltage at an output for a given output
modification. current (lout) and supply voltage (VCC).
The wise designer uses HCT devices to perform logic VT+ Positive–Going Input Threshold Voltage — The
level conversions only. In new designs, the designer wants minimum input voltage of a device with hysteresis
all the advantages of a true CMOS system and designs using which is recognized as a high level. (Assumes ramp up
only HC devices. from previous low level.)
GLOSSARY OF TERMS VT– Negative–Going Input Threshold Voltage — The
maximum input voltage of a device with hysteresis
Cin Input Capacitance — The parasitic capacitance which is recognized as a low level. (Assumes ramp
associated with a given input pin. down from previous high level).
CL Load Capacitance — The capacitor value which VH Hysteresis Voltage — The difference between VT+
loads each output during testing and/or evaluation. and VT– of a given device with hysteresis. A measure
This capacitance is assumed to be attached to each of noise rejection.
output in a system. This includes all wiring and stray ICC IC Quiescent Supply Current — The current into
capacitance. the VCC pin when the device inputs are static at VCC or
Cout Output Capacitance — The capacitance associated GND and outputs are not connected.
with a three–state output in the high–impedance state. ∆ICCAdditional Quiescent Supply Current — The
CPD Power Dissipation Capacitance — Used to current into the VCC pin when one of the device inputs
determine device dynamic power dissipation, i.e., PD is at 2.4 V with respect to GND and the other inputs are
= C PD V CC 2 f + V CC I CC. See POWER SUPPLY static at VCC or GND. The outputs are not connected.
SIZING for a discussion of CPD. Iin Input Current — The current into an input pin with
fmax Maximum Clock Frequency — The maximum the respective input forced to VCC or GND. A negative
clocking frequency attainable with the following sign indicates current is flowing out of the pin
input and output conditions being met: (source). A positive sign or no sign indicates current is
flowing into the pin (sink).
Input Conditions — (HC) t r = t f = 6 ns, voltage
swing from GND to V CC with 50% duty cycle. (HCT) lout Output Current — The current out of an output pin.
t r = t f = 6 ns, voltage swing from GND to 3.0 V with A negative sign indicates current is flowing out of the
50% duty cycle. pin (source). A positive sign or no sign indicates
current is flowing into the pin (sink).
Output Conditions — (HC and HCT) waveform
must swing from 10% of (V OH – V OL) to 90% of IIH Input Current (High) — The input current when the
(V OH – V OL) and be functionally correct under the input voltage is forced to a high level.
given load condition: C L = 50 pF, all outputs.

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IIL Input Current (Low) — The input current when the tPZHHigh–Impedance to High–Level Propagation
input voltage is forced to a low level. Delay (Enable Time) — The time interval between
IOH Output Current (High) — The output current when the 0.5 V CC level (HC) or 1.3 V level with respect
the output voltage is at a high level. to GND (HCT) of the controlling input waveform and
IOL Output Current (Low) — The output current when the 50% level (HC) or 1.3 V level with respect to GND
the output voltage is at a low level. (HCT) of the output waveform, with the output
changing from the high–impedance (off) state to a
IOZ Three–State Leakage Current — The current into or high level.
out of a three–state output in the high–impedance state
with that respective output forced to VCC or GND. tTLHOutput Low–to–High Transition Time — The time
interval between the 10% and 90% voltage levels of
tPLHLow–to–High Propagation Delay (HC) — The time the rising edge of a switching output.
interval between the 0.5 VCC level of the controlling
input waveform and the 50% level of the output tTHLOutput High–to–Low Transition Time — The time
waveform, with the output changing from low level to interval between the 90% and 10% voltage levels of
high level. (HCT) — The time interval between the the falling edge of a switching output.
1.3 V level (with respect to GND) of the controlling tsu Setup Time — The time interval immediately
input waveform and the 1.3 V level (with respect to preceeding the active transition of a clock or latch
GND) of the output waveform, with the output enable input, during which the data to be recognized
changing from low level to high level. must be maintained (valid) at the input to ensure
tPHLHigh–to–Low Propagation Delay (HC) — The time proper recognition. A negative setup time indicates
interval between the 0.5 VCC level of the controlling that the data at the input may be applied sometime
input waveform and the 50% level of the output after the active clock or latch transition and still be
waveform, with the output changing from high level recognized. For HC devices, the setup time is
to low level. (HCT) — The time interval between the measured from the 50% level of the data waveform to
1.3 V level (with respect to GND) of the controlling the 50% level of the clock or latch input waveform.
input waveform and the 1.3 V level (with respect to For HCT devices, the setup time is measured from the
GND) of the output waveform, with the output 1.3 V level (with respect to GND) of the data
changing from high level to low level. waveform to the 1.3 V level (with respect to GND) of
the clock or latch input waveform.
tPLZ Low–Level to High–Impedance Propagation
Delay (Disable Time) — The time interval between th Hold Time — The time interval immediately
the 0.5 V CC level for HC devices (1.3 V with respect to following the active transition of a clock or latch
GND for HCT devices) of the controlling input enable input, during which the data to be recognized
waveform and the 10% level of the output waveform, must be maintained (valid) at the input to ensure
with the output changing from the low level to proper recognition. A negative hold time indicates
high–impedance (off) state. that the data at the input may be changed prior to the
active clock or latch transition and still be recognized.
tPHZHigh–Level to High–impedance Propagation For HC devices, the hold time is measured from the
Delay (Disable Time) — The time interval between 50% level of the clock or latch input waveform to the
the 0.5 V CC level for HC devices (1.3 V with respect to 50% level of the data waveform. For HCT devices, the
GND for HCT devices) of the controlling input hold time is measured from the 1.3 V level (with
waveform and the 90% level of the output waveform, respect to GND) of the clock or latch input waveform
with the output changing from the high level to to the 1.3 V level (with respect to GND) of the data
high–impedance (off) state. waveform.
tPZL High–Impedance to Low–Level Propagation
Delay (Enable Time) — The time interval between
0.5 V CC level (HC) or 1.3 V level with respect to
GND (HCT) of the controlling input waveform and
the 50% level (HC) or 1.3 V level with respect to GND
(HCT) of the output waveform, with the output
changing from the high–impedance (off) state to a low
level.

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trec Recovery Time (HC) — The time interval between tr Input Rise Time (HC) — The time interval between
the 50% level of the transition from active to inactive the 10% and 90% voltage levels on the rising edge of
state of an asynchronous control input and the 50% an input signal. (HCT) — The time interval between
level of the active clock or latch enable edge required the 0.3 V level and 2.7 V level (with respect to GND)
to guarantee proper operation of a device. (HCT) — on the rising edge of an input signal.
The time interval between the 1.3 V level (with respect tf Input Fall Time (HC) — The time interval between
to GND) of the transition from active to inactive state the 90% and 10% voltage levels on the falling edge of
of an asynchronous control input and the 1.3 V level an input signal. (HCT) — The time interval between
(with respect to GND) of the active clock or latch edge the 2.7 V level and 0.3 V level (with respect to GND)
required to guarantee proper operation of a logic on the falling edge of an input signal.
device.
tw Pulse Width (HC) — The time interval between 50%
levels of an input pulse required to guarantee proper
operation of a logic device. (HCT) — The time
interval between 1.3 V levels (with respect to GND) of
an input pulse required to guarantee proper operation
of a logic device.

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 APPLICATIONS ASSISTANCE FORM
In the event that you have any questions or concerns about the performance of any ON Semiconductor device listed in this
catalog, please contact your local ON Semiconductor sales office or the ON Semiconductor Help line for assistance. If further
information is required, you can request direct factory assistance.
Please fill out as much of the form as is possible if you are contacting ON Semiconductor for assistance or are sending devices
back to ON Semiconductor for analysis. Your information can greatly improve the accuracy of analysis and can dramatically
improve the correlation response and resolution time.
Items 4 thru 8 of the following form contains important questions that can be invaluable in analyzing application or device
problems. It can be used as a self-help diagnostic guideline or for a baseline of information gathering to begin a dialog with ON
Semiconductor representatives.
ON Semiconductor Device Correlation/Component Analysis Request Form
— Please fill out entire form and return with devices to ON Semiconductor, R&QA Dept., 5005 E. McDowell, Phoenix, AZ 85008.
1) Name of Person Requesting Correlation:
Phone No: Job Title: Company:
2) Alternate Contact: Phone/Position:
3) Device Type (user part number):
4) Industry Generic Device Type:
5) # of devices tested/sampled:
# of devices in question*:
# returned for correlation:
* In the event of 100% failure, does Customer have other date codes of ON Semiconductor devices that pass inspection?
Yes No Please specify passing date code(s) if applicable
If none, does customer have viable alternate vendor(s) for device type?
Yes No Alternate vendor’s name
6) Date code(s) and Serial Number(s) of devices returned for correlation — If possible, please provide one or two “good” units
(ON Semiconductor’s and/or other vendor) for comparison:
7) Describe USER process that device(s) are questionable in:
Incoming component inspection {test system = ?}:
Design prototyping:
Board test/burn-in:
Other (please describe):

8) Please describe the device correlation operating parameters as completely as possible for device(s) in question:
> Describe all pin conditions (e.g. floating, high, low, under test, stimulated but not under test, whatever ...), including any input
or output loading conditions (resistors, caps, clamps, driving devices or devices being driven ...). Potentially critical
information includes:
Input waveform timing relationships
Input edge rates
Input Overshoot or Undershoot — Magnitude and Duration
Output Overshoot or Undershoot — Magnitude and Duration
> Photographs, plots or sketches of relevent inputs and outputs with voltages and time divisions clearly identified for all
waveforms are greatly desirable.
> VCC and Ground waveforms should be carefully described as these characteristics vary greatly between applications and
test systems. Dynamic characteristics of Ground and VCC during device switching can dramatically effect input and internal
operating levels. Ground & VCC measurements should be made as physically close to the device in question as possible.
> Are there specific circumstances that seem to make the questionable unit(s) worse? Better?
Temperature
VCC
Input rise/fall time
Output loading (current/capacitance)
Others
> ATE functional data should include pattern with decoding key and critical parameters such as VCC, input voltages, Func step
rate, voltage expected, time to measure.

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 CHAPTER 3
Data Sheets

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MC74HC00A

Quad 2-Input NAND Gate

High–Performance Silicon–Gate CMOS
The MC74HC00A is identical in pinout to the LS00. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
• Output Drive Capability: 10 LSTTL Loads http://onsemi.com
• Outputs Directly Interface to CMOS, NMOS and TTL MARKING
• Operating Voltage Range: 2 to 6V DIAGRAMS
• Low Input Current: 1µA 14
PDIP–14
• High Noise Immunity Characteristic of CMOS Devices N SUFFIX MC74HC00AN
• In Compliance With the JEDEC Standard No. 7A Requirements CASE 646 AWLYYWW

• Chip Complexity: 32 FETs or 8 Equivalent Gates 1

14
SOIC–14
LOGIC DIAGRAM HC00A
D SUFFIX
AWLYWW
1 CASE 751A
A1 3
2 Y1 1
B1 14

4 TSSOP–14 HC
A2 6 00A
Y2 DT SUFFIX
5 ALYW
B2 CASE 948G
Y = AB 1
9
A3 8 A = Assembly Location
10 Y3
B3 WL or L = Wafer Lot
YY or Y = Year
12 WW or W = Work Week
A4 11
13 Y4
B4
FUNCTION TABLE
PIN 14 = VCC
PIN 7 = GND Inputs Output

A B Y
Pinout: 14–Lead Packages (Top View)
L L H
VCC B4 A4 Y4 B3 A3 Y3
L H H
14 13 12 11 10 9 8 H L H
H H L

1 2 3 4 5 6 7
ORDERING INFORMATION
A1 B1 Y1 A2 B2 Y2 GND
Device Package Shipping
MC74HC00AN PDIP–14 2000 / Box
MC74HC00AD SOIC–14 55 / Rail
MC74HC00ADR2 SOIC–14 2500 / Reel
MC74HC00ADT TSSOP–14 96 / Rail
MC74HC00ADTR2 TSSOP–14 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 58 Publication Order Number:

March, 2000 – Rev. 8 MC74HC00A/D
 MC74HC00A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ VCC = 6.0 V 0 400

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 MC74HC00A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Vout = 0.1V or VCC –0.1V 2.0 1.50 1.50 1.50 V
Voltage |Iout| ≤ 20µA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Vout = 0.1V or VCC – 0.1V 2.0 0.50 0.50 0.50 V
Voltage |Iout| ≤ 20µA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin =VIH or VIL |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
Current
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 1.0 10 40 µA
Current (per Package) Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A or B to Output Y 2.0 75 95 110 ns
tPHL (Figures 1 and 2) 3.0 30 40 55
4.5 15 19 22
6.0 13 16 19
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 2) 3.0 27 32 36
4.5 15 19 22
6.0 13 16 19
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

CPD Power Dissipation Capacitance (Per Buffer)* 22 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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60
 MC74HC00A

tf tr
VCC
90%
INPUT 50%
A OR B
10% GND
tPLH tPHL

90%
OUTPUT Y 50%
10%

tTLH tTHL

Figure 1. Switching Waveforms

TEST
POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

A
Y
B

Figure 3. Expanded Logic Diagram

(1/4 of the Device)

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61
MC74HC02A

Quad 2-Input NOR Gate

High–Performance Silicon–Gate CMOS
The MC74HC02A is identical in pinout to the LS02. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
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• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL MARKING
• Operating Voltage Range: 2.0 to 6.0 V
14
DIAGRAMS

• Low Input Current: 1.0 µA PDIP–14

• High Noise Immunity Characteristic of CMOS Devices N SUFFIX MC74HC02AN
AWLYYWW
CASE 646
• In Compliance with the Requirements Defined by JEDEC Standard
1
No. 7A 14
• Chip Complexity: 40 FETs or 10 Equivalent Gates SOIC–14
HC02A
D SUFFIX
AWLYWW
LOGIC DIAGRAM CASE 751A
1
2 14
A1 1
3 Y1
B1 TSSOP–14 HC
DT SUFFIX 02A
5 CASE 948G ALYW
A2 4
6 Y2
B2 1
Y=A+B A = Assembly Location
8 WL or L = Wafer Lot
A3 10
Y3 YY or Y = Year
9
B3 WW or W = Work Week

11
A4 13
12 Y4 FUNCTION TABLE
B4
PIN 14 = VCC Inputs Output
PIN 7 = GND A B Y
L L H
PIN ASSIGNMENT L H L
H L L
H H L
Y1 1 14 VCC
A1 2 13 Y4
B1 3 12 B4
Y2 4 11 A4
A2 5 10 Y3
B2 6 9 B3 ORDERING INFORMATION
GND 7 8 A3 Device Package Shipping
MC74HC02AN PDIP–14 2000 / Box
MC74HC02AD SOIC–14 55 / Rail
MC74HC02ADR2 SOIC–14 2500 / Reel
MC74HC02ADT TSSOP–14 96 / Rail
MC74HC02ADTR2 TSSOP–14 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 62 Publication Order Number:

March, 2000 – Rev. 8 MC74HC02A/D
 MC74HC02A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter Test Conditions V 25_C 85_C 125°C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIH
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0
3.0
1.5
2.1
1.5
2.1
1.5
2.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0
3.0
0.5
0.9
0.5
0.9
0.5
0.9
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
2.0
4.5
1.9
4.4
1.9
4.4
1.9
4.4
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 2.48 2.34 2.20
|Iout| 4.0 mA 4.5 3.98 3.84 3.7
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 5.2 mA 6.0 5.48 5.34 5.2

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63
 MC74HC02A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC – 55 to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125°C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
v
Voltage |Iout| 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ 6.0 0.1 0.1 0.1

v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ Vin = VIH or VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.4
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
|Iout| 4.0 mA 4.5 0.26 0.33 0.4
|Iout| 5.2 mA 6.0 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Quiescent Supply

ÎÎÎÎ
ÎÎÎ
Current (per Package)
Vin = VCC or GND
|Iout| = 0 µA
6.0 1.0 10 40

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
µA

(DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VCC – 55 to
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Propagation Delay, Input A or B to Output Y

ÎÎÎÎ
(Figures 1 and 2)
ÎÎÎ
2.0
3.0
75
30
95
40
110
55
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎÎ
(Figures 1 and 2)
ÎÎÎ
2.0
3.0
75
30
95
40
110
55
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Input Capacitance — 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Gate)* 22 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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64
 MC74HC02A

tf tr TEST POINT

INPUT 90% VCC

50% OUTPUT
A OR B
10% GND DEVICE
UNDER
tPLH tPHL CL*
TEST
90%
OUTPUT Y 50%
10%
tTLH tTHL
*Includes all probe and jig capacitance

Figure 1. Switching Waveforms Figure 2. Test Circuit

EXPANDED LOGIC DIAGRAM

(1/4 OF THE DEVICE)

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65
MC74HC03A

Quad 2-Input NAND Gate

with Open-Drain Outputs
High–Performance Silicon–Gate CMOS
The MC74HC03A is identical in pinout to the LS03. The device
inputs are compatible with Standard CMOS outputs; with pullup
http://onsemi.com
resistors, they are compatible with LSTTL outputs.
The HC03A NAND gate has, as its outputs, a high–performance MARKING
MOS N–Channel transistor. This NAND gate can, therefore, with a DIAGRAMS
suitable pullup resistor, be used in wired–AND applications. Having 14
the output characteristic curves given in this data sheet, this device can PDIP–14
N SUFFIX MC74HC03AN
be used as an LED driver or in any other application that only requires CASE 646 AWLYYWW
a sinking current.
• Output Drive Capability: 10 LSTTL Loads With Suitable Pullup
1
14
Resistor SOIC–14
HC03A
• Outputs Directly Interface to CMOS, NMOS and TTL D SUFFIX
AWLYWW
CASE 751A
• High Noise Immunity Characteristic of CMOS Devices
1
• Operating Voltage Range: 2 to 6V 14
• Low Input Current: 1µA TSSOP–14 HC
• In Compliance With the JEDEC Standard No. 7A Requirements DT SUFFIX 03A
• Chip Complexity: 28 FETs or 7 Equivalent Gates CASE 948G ALYW

DESIGN GUIDE 1
A = Assembly Location
Criteria Value Unit WL or L = Wafer Lot
Internal Gate Count* 7.0 ea YY or Y = Year
Internal Gate Propagation Delay 1.5 ns WW or W = Work Week

Internal Gate Power Dissipation 5.0 µW

FUNCTION TABLE
Speed Power Product 0.0075 pJ
* Equivalent to a two–input NAND gate Inputs Output
LOGIC DIAGRAM A B Y
VCC
L L Z
OUTPUT L H Z
PIN 14 = VCC PROTECTION
PIN 7 = GND H L Z
DIODE
* Denotes open–drain outputs 3,6,8,11 H H L
Y*
Z = High Impedance
1,4,9,12
A
2,5,10,13
B

ORDERING INFORMATION
Pinout: 14–Lead Packages (Top View)
Device Package Shipping
VCC B4 A4 Y4 B3 A3 Y3
14 13 12 11 10 9 8 MC74HC03AN PDIP–14 2000 / Box
MC74HC03AD SOIC–14 55 / Rail
MC74HC03ADR2 SOIC–14 2500 / Reel
MC74HC03ADT TSSOP–14 96 / Rail
1 2 3 4 5 6 7 MC74HC03ADTR2 TSSOP–14 2500 / Reel
A1 B1 Y1 A2 B2 Y2 GND

 Semiconductor Components Industries, LLC, 2000 66 Publication Order Number:

March, 2000 – Rev. 8 MC74HC03A/D
 MC74HC03A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 25 mA cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500
level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage (Referenced to GND)

ÎÎ
ÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
2.0
0
6.0
VCC
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
Input Rise and Fall Time

ÎÎÎÎÎ
ÎÎÎ
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns

DC CHARACTERISTICS (Voltages Referenced to GND)

VCC Guaranteed Limit
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Vout = 0.1V or VCC –0.1V 2.0 1.50 1.50 1.50 V
Voltage |Iout| ≤ 20µA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Vout = 0.1V or VCC – 0.1V 2.0 0.50 0.50 0.50 V
Voltage |Iout| ≤ 20µA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOL Maximum Low–Level Output Vout = 0.1V or VCC – 0.1V 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 1.0 10 40 µA
Current (per Package) Iout = 0µA
IOZ Maximum Three–State Leakage Output in High–Impedance State 6.0 ±0.5 ±5.0 ±10 µA
Current Vin = VIL or VIH
Vout = VCC or GND
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

http://onsemi.com
67
 MC74HC03A

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tPLZ, Maximum Propagation Delay, Input A or B to Output Y 2.0 120 150 180 ns
tPZL (Figures 1 and 2) 3.0 45 60 75
4.5 24 30 36
6.0 20 26 31
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 2) 3.0 27 32 36
4.5 15 19 22
6.0 13 16 19
Cin Maximum Input Capacitance 10 10 10 pF
Cout Maximum Three–State Output Capacitance 10 10 10 pF
(Output in High–Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

CPD Power Dissipation Capacitance (Per Buffer)* 8.0 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

http://onsemi.com
68
 MC74HC03A

VCC

tr tf
1kΩ Rpd
VCC
90%
INPUT A 50% OUTPUT TEST
10% GND DEVICE POINT
tPZL tPLZ UNDER
HIGH TEST CL*
90% IMPEDANCE
OUTPUT Y 50%
10% 10%
VOL
tTHL *Includes all probe and jig capacitance

Figure 1. Switching Waveforms Figure 2. Test Circuit

25
VCC=5V
TYPICAL
T=25°C
20
I D, SINK CURRENT (mA)

T=25°C
15
T=85°C

10 T=125°C

EXPECTED MINIMUM*
5

0
0 1 2 3 4 5
VO, OUTPUT VOLTAGE (VOLTS)

*The expected minimum curves are not guarantees, but are design aids.

Figure 3. Open–Drain Output Characteristics

VCC VCC
VCC +
VR
–
PULLUP +
RESISTOR VF
A1 –
1/4 Y1
OUTPUT 1/4 1/4
HC03
B1 LED1 HC03 HC03

^
A2 DESIGN EXAMPLE
1/4 Y2
CONDITIONS: ID 10mA
B2 HC03 LED2
^
USING FIGURE NO TAG TYPICAL
CURVE, at ID=10mA, VDS 0.4V
LED
An
1/4 Yn
ENABLE
NR + VCC *IVDF * VO
+ 5V * 1.7V * 0.4V
HC03
Bn

OUTPUT = Y1 • Y2 • . . . • Yn 10mA
= A1B1 • A2B2 • . . . • AnBn + 290W
USE R = 270Ω

Figure 4. Wired AND Figure 5. LED Driver With Blanking

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69
MC74HC04A
Hex Inverter
High–Performance Silicon–Gate CMOS
The MC74HC04A is identical in pinout to the LS04 and the
MC14069. The device inputs are compatible with Standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs. http://onsemi.com
The device consists of six three–stage inverters. MARKING
• Output Drive Capability: 10 LSTTL Loads DIAGRAMS
14
• Outputs Directly Interface to CMOS, NMOS and TTL PDIP–14
• Operating Voltage Range: 2 to 6V N SUFFIX MC74HC04AN
AWLYYWW
• Low Input Current: 1µA
CASE 646

• High Noise Immunity Characteristic of CMOS Devices

1
14
• In Compliance With the JEDEC Standard No. 7A Requirements SOIC–14
HC04A
• Chip Complexity: 36 FETs or 9 Equivalent Gates D SUFFIX
CASE 751A
AWLYWW

1
LOGIC DIAGRAM 14

TSSOP–14 HC
1 2
A1 Y1 DT SUFFIX 04A
CASE 948G ALYW
3 4 1
A2 Y2
A = Assembly Location
WL or L = Wafer Lot
5 6 YY or Y = Year
A3 Y3
WW or W = Work Week
Y=A
9 8
A4 Y4 FUNCTION TABLE
Inputs Outputs
11 10
A5 Y5 A Y
L H
13 12 H L
A6 Y6

Pinout: 14–Lead Packages (Top View)

VCC A6 Y6 A5 Y5 A4 Y4
14 13 12 11 10 9 8 ORDERING INFORMATION
Device Package Shipping
MC74HC04AN PDIP–14 2000 / Box
MC74HC04AD SOIC–14 55 / Rail
MC74HC04ADR2 SOIC–14 2500 / Reel

1 2 3 4 5 6 7 MC74HC04ADT TSSOP–14 96 / Rail

MC74HC04ADTR2 TSSOP–14 2500 / Reel
A1 Y1 A2 Y2 A3 Y3 GND

 Semiconductor Components Industries, LLC, 2000 70 Publication Order Number:

March, 2000 – Rev. 8 MC74HC04A/D
 MC74HC04A

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MAXIMUM RATINGS*

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Symbol
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Parameter Value Unit This device contains protection

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VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

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Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

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be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

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Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

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cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
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ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

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Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
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ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

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Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

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TL

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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RECOMMENDED OPERATING CONDITIONS

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Symbol Parameter Min Max Unit

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VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

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Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

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TA Operating Temperature, All Package Types – 55 + 125 _C

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tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

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ÎÎÎ VCC = 6.0 V 0 400

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71
 MC74HC04A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Vout = 0.1V or VCC –0.1V 2.0 1.50 1.50 1.50 V
Voltage |Iout| ≤ 20µA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Vout = 0.1V or VCC – 0.1V 2.0 0.50 0.50 0.50 V
Voltage |Iout| ≤ 20µA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin =VIH or VIL |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA
Current
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 1.0 10 40 µA
Current (per Package) Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A or B to Output Y 2.0 75 95 110 ns
tPHL (Figures 1 and 2) 3.0 30 40 55
4.5 15 19 22
6.0 13 16 19
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 2) 3.0 27 32 36
4.5 15 19 22
6.0 13 16 19
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Inverter)* 20 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

http://onsemi.com
72
 MC74HC04A

tf tr
VCC
90%
INPUT A 50%
10% GND
tPLH tPHL

90%
OUTPUT Y 50%
10%

tTLH tTHL

Figure 1. Switching Waveforms

TEST
POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

A Y

Figure 3. Expanded Logic Diagram

(1/6 of the Device Shown)

http://onsemi.com
73
MC74HCT04A
Hex Inverter
With LSTTL–Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT04A may be used as a level converter for interfacing
TTL or NMOS outputs to High–Speed CMOS inputs.
http://onsemi.com
The HCT04A is identical in pinout to the LS04.
MARKING
• Output Drive Capability: 10 LSTTL Loads DIAGRAMS
• TTL/NMOS–Compatible Input Levels 14
• Outputs Directly Interface to CMOS, NMOS and TTL PDIP–14
N SUFFIX MC74HCT04AN
• Operating Voltage Range: 4.5 to 5.5V CASE 646 AWLYYWW
• Low Input Current: 1µA 1
• In Compliance With the JEDEC Standard No. 7A Requirements 14
SOIC–14
• Chip Complexity: 48 FETs or 12 Equivalent Gates D SUFFIX
HCT04A
AWLYWW
CASE 751A
LOGIC DIAGRAM 1
14
1 2 TSSOP–14 HCT
A1 Y1
DT SUFFIX 04A
CASE 948G ALYW
3 4
A2 Y2 1
A = Assembly Location
WL or L = Wafer Lot
5 6
A3 Y3 YY or Y = Year
WW or W = Work Week
Y=A
9 8 Pin 14 = VCC
A4 Y4
Pin 7 = GND FUNCTION TABLE
Inputs Outputs
11 10
A5 Y5
A Y
L H
13 12
A6 Y6 H L

Pinout: 14–Lead Packages (Top View)

VCC A6 Y6 A5 Y5 A4 Y4
14 13 12 11 10 9 8
ORDERING INFORMATION
Device Package Shipping
MC74HCT04AN PDIP–14 2000 / Box
MC74HCT04AD SOIC–14 55 / Rail
MC74HCT04ADR2 SOIC–14 2500 / Reel
1 2 3 4 5 6 7 MC74HCT04ADT TSSOP–14 96 / Rail

A1 Y1 A2 Y2 A3 Y3 GND MC74HCT04ADTR2 TSSOP–14 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 74 Publication Order Number:

March, 2000 – Rev. 7 MC74HCT04A/D
 MC74HCT04A

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ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
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MAXIMUM RATINGS*

ÎÎÎÎ
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Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
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ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature Range – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

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ÎÎ
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Symbol Parameter Min Max Unit

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ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V

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ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
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TA Operating Temperature Range, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise/Fall Time (Figure 1) 0 500 ns

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75
 MC74HCT04A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Vout = 0.1V 4.5 2.0 2.0 2.0 V
Voltage |Iout| ≤ 20µA 5.5 2.0 2.0 2.0
VIL Maximum Low–Level Input Vout = VCC – 0.1V 4.5 0.8 0.8 0.8 V
Voltage |Iout| ≤ 20µA 5.5 0.8 0.8 0.8
VOH Minimum High–Level Output Vin = VIL 4.5 4.4 4.4 4.4 V
Voltage |Iout| ≤ 20µA 5.5 5.4 5.4 5.4
Vin = VIL |Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
VOL Maximum Low–Level Output Vin = VIH 4.5 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 5.5 0.1 0.1 0.1
Vin = VIH |Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
Iin Maximum Input Leakage Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA
Current
ICC Maximum Quiescent Supply Vin = VCC or GND 5.5 1 10 40 µA
Current (per Package) Iout = 0µA

∆ICC Additional Quiescent Supply Vin = 2.4V, Any One Input ≥ –55°C 25 to 125°C
Current Vin
i = VCC or GND,
GND Other Inputs
Iout = 0µA 5.5 2.9 2.4 mA
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + Σ∆ICC.

AC CHARACTERISTICS (VCC = 5.0V ±10%, CL = 50pF, Input tr = tf = 6ns)

Guaranteed Limit
Symbol Parameter –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A to Output Y 15 19 22 ns
tPHL (Figures 1 and 2) 17 21 26
tTLH, Maximum Output Transition Time, Any Output 15 19 22 ns
tTHL (Figures 1 and 2)
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Inverter)* 22 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

http://onsemi.com
76
 MC74HCT04A

tf tr
3.0V
2.7V
INPUT A 1.3V
0.3V GND
tPLH tPHL

90%
OUTPUT Y 1.3V
10%

tTLH tTHL

Figure 1. Switching Waveforms

TEST
POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

A Y

Figure 3. Expanded Logic Diagram

(1/6 of the Device Shown)

http://onsemi.com
77
MC74HCU04A
Hex Unbuffered Inverter
High–Performance Silicon–Gate CMOS
The MC74HCU04A is identical in pinout to the LS04 and the
MC14069UB. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs. http://onsemi.com
This device consists of six single–stage inverters. These inverters MARKING
are well suited for use as oscillators, pulse shapers, and in many other DIAGRAMS
applications requiring a high–input impedance amplifier. For digital 14
applications, the HC04A is recommended. PDIP–14
MC74HCU04AN
• Output Drive Capability: 10 LSTTL Loads N SUFFIX
CASE 646 AWLYYWW
• Outputs Directly Interface to CMOS, NMOS, and TTL 1
• Operating Voltage Range: 2 to 6 V; 2.5 to 6 V in Oscillator 14
Configurations SOIC–14
HCU04A
• Low Input Current: 1 µA D SUFFIX
CASE 751A
AWLYWW
• High Noise Immunity Characteristic of CMOS Devices 1
• In Compliance with the Requirements Defined by JEDEC Standard 14
No. 7A HCU
TSSOP–14
• Chip Complexity: 12 FETs or 3 Equivalent Gates DT SUFFIX 04A
CASE 948G ALYW
LOGIC DIAGRAM
1
1 2 A = Assembly Location
A1 Y1
WL or L = Wafer Lot
YY or Y = Year
3 4 WW or W = Work Week
A2 Y2

5 6 PIN ASSIGNMENT
A3 Y3
Y=A A1 1 14 VCC
9 8 Y1 2 13 A6
A4 Y4
A2 3 12 Y6
11 10 Y2 4 11 A5
A5 Y5
A3 5 10 Y5
PIN 14 = VCC
13 12 PIN 7 = GND Y3 6 9 A4
A6 Y6
GND 7 8 Y4

FUNCTION TABLE

Inputs Outputs
A Y
ORDERING INFORMATION
L H
H L Device Package Shipping
MC74HCU04AN PDIP–14 2000 / Box
MC74HCU04AD SOIC–14 55 / Rail
MC74HCU04ADR2 SOIC–14 2500 / Reel
MC74HCU04ADT TSSOP–14 96 / Rail
MC74HCU04ADTR2 TSSOP–14 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 78 Publication Order Number:

March, 2000 – Rev. 2 MC74HCU04A/D
 MC74HCU04A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: –10mW/_C from 65_ to 125_C
SOIC Package: –7mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time (Figure 1) — No ns
Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
v
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
v
ÎÎÎÎÎÎÎ
ÎÎÎ
Parameter Test Conditions
VCC
V
– 55 to
25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.5 V* 2.0 1.7 1.7 l.7 V
v Voltage |Iout| 20 µA 3.0 2.5 2.5 2.5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
3.6
4.8
3.6
4.8
3.6
4.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = VCC – 0.5 V* 2.0 0.3 0.3 0.3 V
v Voltage |Iout| 20 µA 3.0 0.5 0.5 0.5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 0.8 0.8 0.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 1.1 1.1 1.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = GND 2.0 1.8 1.8 1.8 V
v Voltage |Iout| 20 µA 4.5 4.0 4.0 4.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.5 5.5 5.5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = GND |Iout| 2.4 mA 3.0 2.36 2.26 2.20
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 3.86 3.76 3.70
|Iout| 5.2 mA 6.0 5.36 5.26 5.20

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VCC
|Iout| 20 µA
2.0
4.5
0.2
0.5
0.2
0.5
0.2
0.5
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.5 0.5 0.5
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC |Iout| 2.4 mA 3.0 0.32 0.32 0.32
|Iout| 4.0 mA 4.5 0.32 0.37 0.40
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 5.2 mA 6.0 0.32 0.37 0.40

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79
 MC74HCU04A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
25_C

ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA
Current

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 1 10 40 µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
*For VCC = 2.0 V, Vout = 0.2 V or VCC – 0.2 V.

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC – 55 to
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Input A to Output Y 2.0 70 90 105 ns
tPHL (Figures 1 and 2) 3.0 40 45 50

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
14
12
18
15
21
18

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 2) 3.0 27 32 36

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
15
13
19
16
22
19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Cin Maximum Input Capacitance — 10 10 10 pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Inverter)* 15 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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80
 MC74HCU04A

TEST POINT
tr tf
VCC OUTPUT
90% DEVICE
INPUT A 50%
10% GND UNDER
TEST CL*
tPHL tPLH
90%
OUTPUT Y 50%
10%
tTHL tTLH *Includes all probe and jig capacitance

Figure 1. Switching Waveforms Figure 2. Test Circuit

LOGIC DETAIL
(1/6 of Device Shown)

VCC

A Y

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81
 MC74HCU04A

TYPICAL APPLICATIONS

Crystal Oscillator Stable RC Oscillator

R2 1/6 HCU04A 1/6 HCU04A 1/6 HCU04A

Vout
R2 > > R1
C1 < C2
1/6 HCU04A C
R1

R2 R1

C1 C2

Vout

Schmitt Trigger High Input Impedance Single–Stage Amplifier

with a 2 to 6 V Supply Range

R2 VCC

R2 > 6R1 1 M 1/6 HCU04A

1/6 HCU04A 1/6 HCU04A
R1 INPUT OUTPUT
Vin Vout

1M

Multi–Stage Amplifier LED Driver

VCC +V

1/6 HCU04A 1/6 HCU04A 1/6 HCU04A 1/6 HCU04A

INPUT OUTPUT

For reduced power supply current, use high–efficiency LEDs

such as the Hewlett–Packard HLMP series or equivalent.

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82
MC74HC08A

Quad 2-Input AND Gate

High–Performance Silicon–Gate CMOS
The MC74HC08A is identical in pinout to the LS08. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
http://onsemi.com
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL MARKING
DIAGRAMS
• Operating Voltage Range: 2 to 6V 14
• Low Input Current: 1µA PDIP–14
MC74HC08AN
• High Noise Immunity Characteristic of CMOS Devices N SUFFIX
CASE 646 AWLYYWW
• In Compliance With the JEDEC Standard No. 7A Requirements 1
• Chip Complexity: 24 FETs or 6 Equivalent Gates 14
SOIC–14
HC08A
LOGIC DIAGRAM D SUFFIX
AWLYWW
CASE 751A
1 1
A1 3 14
2 Y1
B1 HC
TSSOP–14
4 DT SUFFIX 08A
A2 6 CASE 948G ALYW
5 Y2
B2 1
Y = AB
9 A = Assembly Location
A3 8 WL or L = Wafer Lot
10 Y3
B3 YY or Y = Year
WW or W = Work Week
12
A4 11
13 Y4 FUNCTION TABLE
B4
Inputs Output
PIN 14 = VCC
PIN 7 = GND A B Y
L L L
Pinout: 14–Lead Packages (Top View) L H L
H L L
VCC B4 A4 Y4 B3 A3 Y3
H H H
14 13 12 11 10 9 8

ORDERING INFORMATION
Device Package Shipping
1 2 3 4 5 6 7
MC74HC08AN PDIP–14 2000 / Box
A1 B1 Y1 A2 B2 Y2 GND
MC74HC08AD SOIC–14 55 / Rail
MC74HC08ADR2 SOIC–14 2500 / Reel
MC74HC08ADT TSSOP–14 96 / Rail
MC74HC08ADTR2 TSSOP–14 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 83 Publication Order Number:

March, 2000 – Rev. 8 MC74HC08A/D
 MC74HC08A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ VCC = 6.0 V 0 400

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84
 MC74HC08A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Vout = 0.1V or VCC –0.1V 2.0 1.50 1.50 1.50 V
Voltage |Iout| ≤ 20µA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Vout = 0.1V or VCC – 0.1V 2.0 0.50 0.50 0.50 V
Voltage |Iout| ≤ 20µA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin =VIH or VIL |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
Current
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 1.0 10 40 µA
Current (per Package) Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A or B to Output Y 2.0 75 95 110 ns
tPHL (Figures 1 and 2) 3.0 30 40 55
4.5 15 19 22
6.0 13 16 19
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 2) 3.0 27 32 36
4.5 15 19 22
6.0 13 16 19
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

CPD Power Dissipation Capacitance (Per Buffer)* 20 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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85
 MC74HC08A

tr tf
VCC
90%
INPUT 50%
A OR B
10% GND

tPLH tPHL

90%
OUTPUT Y 50%
10%

tTLH tTHL

Figure 1. Switching Waveforms

TEST
POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

A
Y
B

Figure 3. Expanded Logic Diagram

(1/4 of the Device)

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86
MC74HC14A

Hex Schmitt-Trigger
Inverter
High–Performance Silicon–Gate CMOS
The MC74HC14A is identical in pinout to the LS14, LS04 and the
HC04. The device inputs are compatible with Standard CMOS http://onsemi.com
outputs; with pullup resistors, they are compatible with LSTTL
outputs. MARKING
The HC14A is useful to “square up” slow input rise and fall times. DIAGRAMS
14
Due to hysteresis voltage of the Schmitt trigger, the HC14A finds
PDIP–14
applications in noisy environments. N SUFFIX MC74HC14AN
• Output Drive Capability: 10 LSTTL Loads CASE 646 AWLYYWW

• Outputs Directly Interface to CMOS, NMOS and TTL 1

• Operating Voltage Range: 2 to 6V 14

• Low Input Current: 1µA SOIC–14

D SUFFIX
HC14A
• High Noise Immunity Characteristic of CMOS Devices CASE 751A
AWLYWW

• In Compliance With the JEDEC Standard No. 7A Requirements 1

• Chip Complexity: 60 FETs or 15 Equivalent Gates
14

TSSOP–14 HC
LOGIC DIAGRAM DT SUFFIX 14A
CASE 948G ALYW
1 2
A1 Y1 1
A = Assembly Location
3 4 WL or L = Wafer Lot
A2 Y2 YY or Y = Year
WW or W = Work Week
5 6
A3 Y3 FUNCTION TABLE
Y=A
Inputs Outputs
9 8
A4 Y4 Pin 14 = VCC A Y
Pin 7 = GND
L H
11 10 H L
A5 Y5

13 12
A6 Y6

Pinout: 14–Lead Packages (Top View)

ORDERING INFORMATION
VCC A6 Y6 A5 Y5 A4 Y4
Device Package Shipping
14 13 12 11 10 9 8
MC74HC14AN PDIP–14 2000 / Box
MC74HC14AD SOIC–14 55 / Rail
MC74HC14ADR2 SOIC–14 2500 / Reel
MC74HC14ADT TSSOP–14 96 / Rail
MC74HC14ADTR2 TSSOP–14 2500 / Reel

1 2 3 4 5 6 7
A1 Y1 A2 Y2 A3 Y3 GND

 Semiconductor Components Industries, LLC, 2000 87 Publication Order Number:

March, 2000 – Rev. 8 MC74HC14A/D
 MC74HC14A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature Range – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to 0 VCC V
GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎ
ÎÎÎ
ÎÎÎ
Operating Temperature Range, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Input Rise/Fall Time

ÎÎÎ
ÎÎÎ
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
0
0
No Limit*
No Limit*
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VCC = 6.0 V 0 No Limit*
*When Vin = 50% VCC, ICC > 1mA

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 MC74HC14A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VT+ max Maximum Positive–Going Input Vout = 0.1V 2.0 1.50 1.50 1.50 V
Threshold Voltage |Iout| ≤ 20µA 3.0 2.15 2.15 2.15
(Figure 3) 4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VT+ min Minimum Positive–Going Input Vout = 0.1V 2.0 1.0 0.95 0.95 V
Threshold Voltage |Iout| ≤ 20µA 3.0 1.5 1.45 1.45
(Figure 3) 4.5 2.3 2.25 2.25
6.0 3.0 2.95 2.95
VT– max Maximum Negative–Going Input Vout = VCC – 0.1V 2.0 0.9 0.95 0.95 V
Threshold Voltage |Iout| ≤ 20µA 3.0 1.4 1.45 1.45
(Figure 3) 4.5 2.0 2.05 2.05
6.0 2.6 2.65 2.65
VT– min Minimum Negative–Going Input Vout = VCC – 0.1V 2.0 0.3 0.3 0.3 V
Threshold Voltage |Iout| ≤ 20µA 3.0 0.5 0.5 0.5
(Figure 3) 4.5 0.9 0.9 0.9
6.0 1.2 1.2 1.2
VHmax Maximum Hysteresis Voltage Vout = 0.1V or VCC – 0.1V 2.0 1.20 1.20 1.20 V
Note 2 (Figure 3) |Iout| ≤ 20µA 3.0 1.65 1.65 1.65
4.5 2.25 2.25 2.25
6.0 3.00 3.00 3.00
VHmin Minimum Hysteresis Voltage Vout = 0.1V or VCC – 0.1V 2.0 0.20 0.20 0.20 V
Note 2 (Figure 3) |Iout| ≤ 20µA 3.0 0.25 0.25 0.25
4.5 0.40 0.40 0.40
6.0 0.50 0.50 0.50
VOH Minimum High–Level Output Vin ≤ VT– min 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin ≤ VT– min |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20
VOL Maximum Low–Level Output Vin ≥ VT+ max 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin ≥ VT+ max |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
Current
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 1.0 10 40 µA
Current (per Package) Iout = 0µA
1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
2. VHmin > (VT+ min) – (VT– max); VHmax = (VT+ max) – (VT– min).

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89
 MC74HC14A

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A or B to Output Y 2.0 75 95 110 ns
tPHL (Figures 1 and 2) 3.0 30 40 55
4.5 15 19 22
6.0 13 16 19
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 2) 3.0 27 32 36
4.5 15 19 22
6.0 13 16 19
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Inverter)* 22 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

tf tr
VCC
90%
INPUT A 50%
10% GND
tPLH tPHL

90%
OUTPUT Y 50%
10%

tTLH tTHL

Figure 1. Switching Waveforms

TEST
POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

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90
 MC74HC14A

VT , TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS

4

3
(VT+) VHtyp

2
(VT–)

2 3 4 5 6
VCC, POWER SUPPLY VOLTAGE (VOLTS)

VHtyp = (VT+ typ) – (VT– typ)

Figure 3. Typical Input Threshold, VT+, VT– versus Power Supply Voltage

A Y

(a) A Schmitt–Trigger Squares Up Inputs With Slow Rise and Fall Times (b) A Schmitt–Trigger Offers Maximum Noise Immunity

VCC VCC
VH VH
VT+ VT+
Vin Vin
VT– VT–

GND GND

VOH VOH

Vout Vout

VOL VOL

Figure 4. Typical Schmitt–Trigger Applications

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91
MC74HCT14A

Hex Schmitt-Trigger
Inverter with LSTTL
Compatible Inputs
High–Performance Silicon–Gate CMOS
http://onsemi.com
The MC74HCT14A may be used as a level converter for interfacing
TTL or NMOS outputs to high–speed CMOS inputs. MARKING
The HCT14A is identical in pinout to the LS14. DIAGRAMS
The HCT14A is useful to “square up” slow input rise and fall times. 14
Due to the hysteresis voltage of the Schmitt trigger, the HCT14A finds PDIP–14
N SUFFIX MC74HCT14AN
applications in noisy environments. CASE 646 AWLYYWW
• Output Drive Capability: 10 LSTTL Loads 1
• TTL/NMOS–Compatible Input Levels
14
• Outputs Directly Interface to CMOS, NMOS and TTL SOIC–14
HCT14A
• Operating Voltage Range: 4.5 to 5.5 V D SUFFIX
AWLYWW
CASE 751A
• Low Input Current: 1.0 µA
1
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A A = Assembly Location
• Chip Complexity: 72 FETs or 18 Equivalent Gates
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
LOGIC DIAGRAM

1 2 PIN ASSIGNMENT
A1 Y1

A1 1 14 VCC
3 4 Y1 2 13 A6
A2 Y2
A2 3 12 Y6
5 6 Y2 4 11 A5
A3 Y3
A3 5 10 Y5
Y=A
Y3 6 9 A4
9 8
A4 Y4
GND 7 8 Y4
PIN 14 = VCC
PIN 7 = GND
11 10
A5 Y5

13 12
A6 Y6
ORDERING INFORMATION
Device Package Shipping
FUNCTION TABLE
MC74HCT14AN PDIP–14 2000 / Box
Input Output MC74HCT14AD SOIC–14 55 / Rail
A Y
MC74HCT14ADR2 SOIC–14 2500 / Reel
L H
H L

 Semiconductor Components Industries, LLC, 2000 92 Publication Order Number:

March, 2000 – Rev. 7 MC74HCT14A/D
 MC74HCT14A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 25 mA cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500
level (e.g., either GND or VCC).
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 Unused outputs must be left open.
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 _C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
Î ÎÎ
Symbol

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
Parameter
DC Supply Voltage (Referenced to GND)
Min
4.5
Max
5.5
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA ÎÎ
ÎÎÎÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎ
ÎÎÎ
Operating Temperature, All Package Types
0
– 55
VCC
+ 125
V
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf
[ ÎÎÎ
ÎÎ
ÎÎÎ
Input Rise and Fall Time (Figure 1)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
*No Limit when Vin 50% VCC, ICC > 1 mA.
— * ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎ
v ÎÎ – 55 to
Temperature Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎ
VCC 25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Symbol Parameter Test Conditions Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
VT+ max Maximum Positive–Going Vout = 0.1 V or VCC – 0.1 V 4.5 1.9 1.9 1.9 V
v Input Threshold Voltage |Iout| 20 µA 5.5 2.1 2.1 2.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
VT+ min

ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
v ÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
Minimum Positive–Going

ÎÎ
Input Threshold Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
4.5
5.5
1.2
1.4
1.2
1.4
1.2
1.4
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
VT– max Maximum Positive–Going Vout = 0.1 V or VCC – 0.1 V 4.5 1.2 1.2 1.2
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Input Threshold Voltage |Iout| 5.5 1.4 1.4 1.4
VT– min Minimum Positive–Going Vout = 0.1 V or VCC – 0.1 V 4.5 0.5 0.5 0.5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
v
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Input Threshold Voltage |Iout| 20 µA 5.5 0.6 0.6 0.6

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
VH max

ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
v ÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Voltage
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Maximum Hysteresis

ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
4.5
5.5
1.4
1.5
1.4
1.5
1.4
1.5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
VH min Minimum Hysteresis Vout = 0.1 V or VCC – 0.1 V 4.5 0.4 0.4 0.4
v Voltage |Iout| 20 µA 5.5 0.4 0.4 04

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOH
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
v ÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Minimum High–Level

ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎ
Vin < VT–min
|Iout| 20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Vin < VT–min 4.5 3.98 3.84 3.7
v |Iout| 4.0 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
(continued)

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 MC74HCT14A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC CHARACTERISTICS (Voltages Referenced to GND) – continued

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Temperature Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
– 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎ
25_C 85_C 125_C
VCC

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Symbol Parameter Test Conditions Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
VOL Maximum Low–Level Vin ≥ VT+max 4.5 0.1 0.1 0.1 V
v Output Voltage |Iout| 20 µA 5.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎ
Vin ≥ VT+max
|Iout| 4.0 mA
4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Maximum Input

ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Leakage Current
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ICC Maximum Quiescent Vin = VCC or GND 5.5 1.0 10 40 µA
Supply Current Iout = 0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(per package)
ÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎ
≥ – 55_C
25_C to
125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ
∆ICC Additional Quiescent Vin = 2.4 V, Any One Input 5.5 2.9 2.4 mA
Supply Current Vin = VCC or GND, Other Inputs

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎ
lout = 0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎ
– 55 to
v v 25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Parameter
ÎÎÎÎÎ Test Conditions Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
tPHL ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Maximum Propagation

ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎ
Delay, Input A to Output Y
VCC = 5.0 V ± 10%
CL = 50 pF, Input tr = tf = 6.0 ns
Fig.
1&2
32 40 48 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
(L to H)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
tTLH, Maximum Output VCC = 5.0 V ± 10% Fig. 15 19 22 ns
tTHL Transition Time. CL = 50 pF, Input tr = tf = 6.0 ns 1&2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Any Output
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Inverter)* 32 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

tf tr TEST POINT
3V
2.7 V
INPUT A 1.3 V OUTPUT
0.3 V GND
tPLH tPHL DEVICE
UNDER
90% TEST CL*
OUTPUT Y 1.3 V
10%

tTLH tTHL
*Includes all probe and jig capacitance

Figure 1. Switching Waveforms Figure 2. Test Circuit

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94
MC74HC32A

Quad 2-Input OR Gate

High–Performance Silicon–Gate CMOS
The MC74HC32A is identical in pinout to the LS32. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
http://onsemi.com
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL MARKING
DIAGRAMS
• Operating Voltage Range: 2 to 6V 14
• Low Input Current: 1µA PDIP–14
MC74HC32AN
• High Noise Immunity Characteristic of CMOS Devices N SUFFIX
CASE 646 AWLYYWW
• In Compliance With the JEDEC Standard No. 7A Requirements 1
• Chip Complexity: 48 FETs or 12 Equivalent Gates
14
SOIC–14
LOGIC DIAGRAM HC32A
D SUFFIX
AWLYWW
1 CASE 751A
A1 3 1
2 Y1
B1 14

4 TSSOP–14 HC
A2 6 DT SUFFIX 32A
5 Y2
B2 CASE 948G ALYW
Y = A+B
9 1
A3 8
10 Y3 A = Assembly Location
B3 WL or L = Wafer Lot
YY or Y = Year
12
A4 11 WW or W = Work Week
13 Y4
B4
FUNCTION TABLE
PIN 14 = VCC
PIN 7 = GND Inputs Output

A B Y
Pinout: 14–Lead Packages (Top View)
L L L
VCC B4 A4 Y4 B3 A3 Y3 L H H
14 13 12 11 10 9 8 H L H
H H H

1 2 3 4 5 6 7
ORDERING INFORMATION
Device Package Shipping
A1 B1 Y1 A2 B2 Y2 GND
MC74HC32AN PDIP–14 2000 / Box
MC74HC32AD SOIC–14 55 / Rail
MC74HC32ADR2 SOIC–14 2500 / Reel
MC74HC32ADT TSSOP–14 96 / Rail
MC74HC32ADTR2 TSSOP–14 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 95 Publication Order Number:

March, 2000 – Rev. 7 MC74HC32A/D
 MC74HC32A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ VCC = 6.0 V 0 400

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96
 MC74HC32A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Vout = 0.1V or VCC –0.1V 2.0 1.50 1.50 1.50 V
Voltage |Iout| ≤ 20µA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Vout = 0.1V or VCC – 0.1V 2.0 0.50 0.50 0.50 V
Voltage |Iout| ≤ 20µA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin =VIH or VIL |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
Current
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 1.0 10 40 µA
Current (per Package) Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A or B to Output Y 2.0 75 95 110 ns
tPHL (Figures 1 and 2) 3.0 30 40 55
4.5 15 19 22
6.0 13 16 19
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 2) 3.0 27 32 36
4.5 15 19 22
6.0 13 16 19
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

CPD Power Dissipation Capacitance (Per Buffer)* 20 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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97
 MC74HC32A

tr tf
VCC
90%
INPUT 50%
A OR B
10% GND

tPLH tPHL

90%
OUTPUT Y 50%
10%

tTLH tTHL

Figure 1. Switching Waveforms

TEST
POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

A
Y
B

Figure 3. Expanded Logic Diagram

(1/4 of the Device)

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98
MC74HC74A

Dual D Flip-Flop with Set

and Reset
High–Performance Silicon–Gate CMOS
The MC74HC74A is identical in pinout to the LS74. The device
inputs are compatible with standard CMOS outputs; with pullup http://onsemi.com
resistors, they are compatible with LSTTL outputs.
This device consists of two D flip–flops with individual Set, Reset, MARKING
and Clock inputs. Information at a D–input is transferred to the DIAGRAMS
14
corresponding Q output on the next positive going edge of the clock
PDIP–14
input. Both Q and Q outputs are available from each flip–flop. The Set N SUFFIX MC74HC74AN
and Reset inputs are asynchronous. CASE 646 AWLYYWW

• Output Drive Capability: 10 LSTTL Loads 1

• Outputs Directly Interface to CMOS, NMOS, and TTL 14

• Operating Voltage Range: 2.0 to 6.0 V SOIC–14
HC74A
D SUFFIX
• Low Input Current: 1.0 µA CASE 751A
AWLYWW

• High Noise Immunity Characteristic of CMOS Devices 1

• In Compliance with the Requirements Defined by JEDEC Standard 14
No. 7A TSSOP–14 HC
• Chip Complexity: 128 FETs or 32 Equivalent Gates DT SUFFIX 74A
CASE 948G ALYW
LOGIC DIAGRAM
1
1
RESET 1 A = Assembly Location
WL or L = Wafer Lot
2 5
DATA 1 Q1 YY or Y = Year
6 WW or W = Work Week
3
CLOCK 1 Q1
PIN ASSIGNMENT
4
SET 1
PIN 14 = VCC
RESET 1 1 14 VCC
PIN 7 = GND
13
RESET 2 DATA 1 2 13 RESET 2

12 9 CLOCK 1 3 12 DATA 2
DATA 2 Q2
8 SET 1 4 11 CLOCK 2
11
CLOCK 2 Q2
Q1 5 10 SET 2
10 Q1 6 9 Q2
SET 2
GND 7 8 Q2
FUNCTION TABLE
Inputs Outputs
Set Reset Clock Data Q Q
L H X X H L
H L X X L H ORDERING INFORMATION
L L X X H* H* Device Package Shipping
H H H H L
H H L L H MC74HC74AN PDIP–14 2000 / Box
H H L X No Change MC74HC74AD SOIC–14 55 / Rail
H H H X No Change
H H X No Change MC74HC74ADR2 SOIC–14 2500 / Reel
MC74HC74ADT TSSOP–14 96 / Rail
*Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously. MC74HC74ADTR2 TSSOP–14 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 99 Publication Order Number:

March, 2000 – Rev. 8 MC74HC74A/D
 MC74HC74A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 25 mA cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, Plastic DIP† 750 mW Unused inputs must always be
SOIC Package† 500 tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ TSSOP Package† 450 level (e.g., either GND or VCC).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC or TSSOP Package) 260
300
_C

*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage (Referenced to GND)

ÎÎ
ÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
2.0
0
6.0
VCC
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Rise and Fall Time

ÎÎÎ
VCC = 2.0 V 0 1000 ns

ÎÎ
(Figures 1, 2, 3) VCC = 3.0 V 0 600
VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
– 55 to
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIH
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0
3.0
4.5
1.5
2.1
3.15
1.5
2.1
1.5
2.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
3.15 3.15
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0
3.0
0.5
0.9
0.5
0.9
0.5
0.9
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
2.0
4.5
1.9
4.4
1.9
4.4
1.9
4.4
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 2.48 2.34 2.2
|Iout| 4.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ |Iout| 5.2 mA 6.0 5.48 5.34 5.2

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100
 MC74HC74A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
2.0
4.5
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.4
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 0.26 0.33 0.4
|Iout| 5.2 mA 6.0 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 2.0 20 80 µA
Current (per Package) Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
ÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 6.0 4.8 4.0 MHz
(Figures 1 and 4) 3.0 15 10 8.0

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
30
35
24
28
20
24

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Clock to Q or Q 2.0 100 125 150 ns
tPHL (Figures 1 and 4) 3.0 75 90 120

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
20
17
25
21
30
26

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Set or Reset to Q or Q 2.0 105 130 160 ns
tPHL (Figures 2 and 4) 3.0 80 95 130

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 21 26 32

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 18 22 27

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 4) 3.0 30 40 55

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 19 22

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 13 16 19
Cin Maximum Input Capacitance — 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Flip–Flop)* 32 pF
2
* Used to determine the no–load dynamic power consumption: P D = C PD V CC f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

http://onsemi.com
101
 MC74HC74A

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v V 25_C 85_C 125_C

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Unit
tsu Minimum Setup Time, Data to Clock 2.0 80 100 120 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
(Figure 3)

ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
3.0
4.5
6.0
35
16
14
45
20
17
55
24
20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
th
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(Figure 3)

ÎÎÎÎÎÎÎ
Minimum Hold Time, Clock to Data

ÎÎÎ
2.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3.0 3.0 3.0
6.0 3.0 3.0 3.0

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
trec
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(Figure 2)

ÎÎÎÎÎÎÎ
Minimum Recovery Time, Set or Reset Inactive to Clock

ÎÎÎ
2.0
3.0
8.0
8.0
8.0
8.0
8.0
8.0
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 8.0 8.0 8.0
6.0 8.0 8.0 8.0

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tw
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(Figure 1)

ÎÎÎÎÎÎÎ
Minimum Pulse Width, Clock

ÎÎÎ
2.0
3.0
4.5
60
25
12
75
30
15
90
40
18
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Minimum Pulse Width, Set or Reset
6.0
2.0
10
60
13
75
15
90 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figure 2) 3.0 25 30 40
4.5 12 15 18

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 10 13 15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figures 1, 2, 3) 3.0 800 800 800
4.5 500 500 500

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 400 400 400

http://onsemi.com
102
 MC74HC74A

SWITCHING WAVEFORMS

tw
tf tr VCC
VCC SET OR 50%
90%
CLOCK 50% RESET GND
10% GND tPHL
tw
1/fmax Q OR Q 50%

tPLH tPHL tPLH

90%
50%
10% Q OR Q 50%
Q or Q
tTLH tTHL trec
VCC
Figure 1. CLOCK 50%
GND

Figure 2.

TEST POINT
VALID
VCC
DATA 50% OUTPUT
GND DEVICE
tsu th UNDER
VCC TEST CL*
50%
CLOCK GND

Figure 3. *Includes all probe and jig capacitance

Figure 4.

EXPANDED LOGIC DIAGRAM

4, 10
SET

2, 12 5, 9
DATA Q

3, 11
CLOCK

6, 8
Q

1, 13
RESET

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103
MC74HCT74A

Dual D Flip-Flop with Set

and Reset with LSTTL
Compatible Inputs
High–Performance Silicon–Gate CMOS
http://onsemi.com
The MC74HCT74A is identical in pinout to the LS74. This device
may be used as a level converter for interfacing TTL or NMOS outputs MARKING
to High Speed CMOS inputs. DIAGRAMS
This device consists of two D flip–flops with individual Set, Reset, 14
and Clock inputs. Information at a D–input is transferred to the PDIP–14
N SUFFIX MC74HCT74AN
corresponding Q output on the next positive going edge of the clock CASE 646 AWLYYWW
input. Both Q and Q outputs are available from each flip–flop. The Set
1
and Reset inputs are asynchronous. 14
• Output Drive Capability: 10 LSTTL Loads SOIC–14
HCT74A
• TTL NMOS Compatible Input Levels D SUFFIX
CASE 751A
AWLYWW
• Outputs Directly Interface to CMOS, NMOS, and TTL 1
• Operating Voltage Range: 4.5 to 5.5 V A = Assembly Location
• Low Input Current: 1.0 µA WL or L = Wafer Lot
YY or Y = Year
• In Compliance with the Requirements Defined by JEDEC Standard WW or W = Work Week
No. 7A PIN ASSIGNMENT
• Chip Complexity: 136 FETs or 34 Equivalent Gates
RESET 1 1 14 VCC
LOGIC DIAGRAM DATA 1 2 13 RESET 2
1 CLOCK 1 3 12 DATA 2
RESET 1
SET 1 4 11 CLOCK 2
2 5
DATA 1 Q1 Q1 5 10 SET 2
3 6 Q1 6 9 Q2
CLOCK 1 Q1
GND 7 8 Q2
4
SET 1
PIN 14 = VCC FUNCTION TABLE
13 PIN 7 = GND Inputs Outputs
RESET 2
Set Reset Clock Data Q Q
12 9
DATA 2 Q2 L H X X H L
8 H L X X L H
11
CLOCK 2 Q2 L L X X H* H*
H H H H L
10 H H L L H

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
SET 2
H H L X No Change

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
H H H X No Change
Design Criteria Value Units
H H X No Change

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Internal Gate Count*

ÎÎÎÎ
ÎÎÎ
34 ea. *Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredict-

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Propagation Delay 1.5 ns able if Set and Reset go high simultaneously.

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Power Dissipation 5.0 µW

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ORDERING INFORMATION
Speed Power Product .0075 pJ
Device Package Shipping
*Equivalent to a two–input NAND gate.
MC74HCT74AN PDIP–14 2000 / Box
MC74HCT74AD SOIC–14 55 / Rail
MC74HCT74ADR2 SOIC–14 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 104 Publication Order Number:

March, 2000 – Rev. 8 MC74HCT74A/D
 MC74HCT74A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C Unused outputs must be left open.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
(Plastic DIP or SOIC Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: –10mW/_C from 65_ to 125_C
SOIC Package: –7mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 4.5 4.4 4.4 4.4 V
v 20 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 5.5 5.4 5.4 5.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = VIH or VIL

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
VOL
v
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Low–Level Output
|Iout| 4.0 mA
Vin = VIH or VIL
4.5
4.5
3.98
0.1
3.84
0.1
3.7
0.1 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 20 µA 5.5 0.1 0.1 0.1

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL
v
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 0.26 0.33 0.4
± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Vin = VCC or GND 5.5
Current

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
5.5 2.0 20 80 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
∆ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Current ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Additional Quiescent Supply Vin = 2.4 V, Any One Input
Vin = VCC or GND,
GND Other InInputs
uts
≥ – 55_C 25_C to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
lout = 0 µA 5.5 2.9 2.4 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

http://onsemi.com
105
 MC74HCT74A

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit
– 55 to
v 85_C v 125_C
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Symbol Parameter 25_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
fmax Maximum Clock Frequency (50% Duty Cycle) 30 24 20 MHz
(Figures 1 and 4)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tPLH,
tPHL ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Maximum Propagation Delay, Clock to Q or Q

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figures 1 and 4)
24 30 36 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tPLH,
tPHL ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Maximum Propagation Delay, Set or Reset to Q or Q

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figures 2 and 4)
24 30 36 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 15 19 22 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL (Figures 1 and 4)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)* 32 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎ
– 55 to
v v 25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tsu
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
Parameter

ÎÎ
Minimum Setup Time, Data to Clock
Fig.
3
Min
15
Max Min
19
Max Min
22
Max Units
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
th
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
trec
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
Minimum Hold Time, Clock to Data

ÎÎÎ
ÎÎ
Minimum Recovery Time, Set or Reset Inactive to Clock
3
2
3
6
3
8
3
9
ns
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tw
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
Minimum Pulse Width, Clock

ÎÎÎ
ÎÎ
Minimum Pulse Width, Set or Reset
1
2
15
15
19
19
22
22
ns
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
Maximum Input Rise and Fall Times 1 500 500 500 ns

http://onsemi.com
106
 MC74HCT74A

SWITCHING WAVEFORMS

tw
tr tf 3V
SET OR 1.3 V
2.7 V 3V GND
CLOCK RESET
1.3 V tPHL
0.3 V GND
tw Q OR Q 1.3 V

1/fmax tPLH

tPLH tPHL 1.3 V

Q OR Q
90% trec
Q OR Q 1.3 V
10% 3V
CLOCK 1.3 V
tTLH tTHL GND

Figure 1. Figure 2.

VALID
3V TEST POINT

DATA 1.3 V
OUTPUT
GND
DEVICE
tsu th UNDER
TEST CL*
3V
1.3 V GND
CLOCK

*Includes all probe and jig capacitance

Figure 3. Figure 4.

EXPANDED LOGIC DIAGRAM

4, 10
SET

2, 12 5, 9
DATA Q

3, 11
CLOCK

6, 8
Q

1, 13
RESET

http://onsemi.com
107
MC74HC86A

Quad 2-Input Exclusive

OR Gate
High–Performance Silicon–Gate CMOS
The MC74HC86A is identical in pinout to the LS86. The device
inputs are compatible with standard CMOS outputs; with pullup http://onsemi.com
resistors, they are compatible with LSTTL outputs.
MARKING
• Output Drive Capability: 10 LSTTL Loads DIAGRAMS
• Outputs Directly Interface to CMOS, NMOS, and TTL
14
• Operating Voltage Range: 2 to 6 V PDIP–14
• Low Input Current: 1 µA N SUFFIX MC74HC86AN
AWLYYWW
CASE 646
• High Noise Immunity Characteristic of CMOS Devices
1
• In Compliance with the Requirements Defined by JEDEC Standard
14
No. 7A
SOIC–14
• Chip Complexity: 56 FETs or 14 Equivalent Gates D SUFFIX
HC86A
AWLYWW
CASE 751A
LOGIC DIAGRAM 1
1 14
A1 3
2 Y1 HC
B1 TSSOP–14
DT SUFFIX 86A
4 CASE 948G ALYW
A2 6
5 Y2 1
B2
Y= A⊕B A = Assembly Location
9 = AB + AB WL or L = Wafer Lot
A3 8 YY or Y = Year
10 Y3 WW or W = Work Week
B3 PIN 14 = VCC
PIN 7 = GND
12 FUNCTION TABLE
A4 11
13 Y4
B4 Inputs Output
A B Y
PIN ASSIGNMENT L L L
L H H
A1 1 14 VCC H L H
B1 2 13 B4 H H L

Y1 3 12 A4
A2 4 11 Y4
B2 5 10 B3
Y2 6 9 A3
ORDERING INFORMATION
GND 7 8 Y3
Device Package Shipping
MC74HC86AN PDIP–14 2000 / Box
MC74HC86AD SOIC–14 55 / Rail
MC74HC86ADR2 SOIC–14 2500 / Reel
MC74HC86ADT TSSOP–14 96 / Rail
MC74HC86ADTR2 TSSOP–14 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 108 Publication Order Number:

March, 2000 – Rev. 2 MC74HC86A/D
 MC74HC86A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIH
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0
3.0
1.5
2.1
1.5
2.1
1.5
2.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0
3.0
0.5
0.9
0.5
0.9
0.5
0.9
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL |Iout|
|Iout|
2.4 mA
4.0 mA
3.0
4.5
2.48
3.98
2.34
3.84
2.20
3.70

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 5.2 mA 6.0 5.48 5.34 5.20

http://onsemi.com
109
 MC74HC86A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
vVoltage |Iout| 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.40
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 0.26 0.33 0.40
|Iout| 5.2 mA 6.0 0.26 0.33 0.40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 1.0 10 40 µA
Iout = 0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current (per Package)
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input t, = tf = 6 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Input A or B to Output Y

ÎÎÎ
(Figures 1 and 2)
2.0
3.0
100
80
125
90
150
110
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 20 25 31
6.0 17 21 26

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
(Figures 1 and 2)
2.0
3.0
75
30
95
40
110
55
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
NOTES: ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Capacitance — 10 10 10

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
pF

2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Gate)* 33 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

http://onsemi.com
110
 MC74HC86A

tr tf
VCC
90%
INPUT 50% TEST POINT
A OR B 10% GND
OUTPUT
tPLH tPHL DEVICE
UNDER
90% TEST CL*
OUTPUT Y 50%
10%

tTLH tTHL
*Includes all probe and jig capacitance

Figure 1. Switching Waveforms Figure 2. Test Circuit

EXPANDED LOGIC DIAGRAM

(1/4 of Device)

http://onsemi.com
111
MC74HC125A,
MC74HC126A

Quad 3-State Noninverting

Buffers
High–Performance Silicon–Gate CMOS
The MC74HC125A and MC74HC126A are identical in pinout to http://onsemi.com
the LS125 and LS126. The device inputs are compatible with standard MARKING
CMOS outputs; with pullup resistors, they are compatible with DIAGRAMS
LSTTL outputs. 14
The HC125A and HC126A noninverting buffers are designed to be PDIP–14
used with 3–state memory address drivers, clock drivers, and other N SUFFIX MC74HC12xAN
bus–oriented systems. The devices have four separate output enables CASE 646 AWLYYWW
that are active–low (HC125A) or active–high (HC126A). 1

• Output Drive Capability: 15 LSTTL Loads 14

• Outputs Directly Interface to CMOS, NMOS, and TTL SOIC–14

D SUFFIX
HC12xA
• Operating Voltage Range: 2.0 to 6.0 V CASE 751A
AWLYWW

• Low Input Current: 1.0 µA 1

• High Noise Immunity Characteristic of CMOS Devices
14

• In Compliance with the Requirements Defined by JEDEC Standard TSSOP–14 HC

DT SUFFIX 12xA
No. 7A ALYW
CASE 948G
• Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM 1
HC125A HC126A A = Assembly Location
WL or L = Wafer Lot
Active–Low Output Enables Active–High Output Enables
YY or Y = Year
2 3 2 3 WW or W = Work Week
A1 Y1 A1 Y1
PIN ASSIGNMENT
1 1
OE1 OE1
OE1 1 14 VCC
5 6 5 6
A2 Y2 A2 Y2 A1 2 13 OE4

4 4 Y1 3 12 A4
OE2 OE2
OE2 4 11 Y4
9 8 Y3 9 8 Y3
A3 A3 A2 5 10 OE3
Y2 6 9 A3
10 10
OE3 OE3 GND 7 8 Y3
12 11 12 11
A4 Y4 A4 Y4

13 13
OE4 OE4

PIN 14 = VCC
PIN 7 = GND ORDERING INFORMATION
FUNCTION TABLE Device Package Shipping
HC125A HC126A MC74HC12xAN PDIP–14 2000 / Box
Inputs Output Inputs Output MC74HC12xAD SOIC–14 55 / Rail
A OE Y A OE Y
MC74HC12xADR2 SOIC–14 2500 / Reel
H L H H H H
L L L L H L MC74HC12xADT TSSOP–14 96 / Rail
X H Z X L Z MC74HC12xADTR2 TSSOP–14 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 112 Publication Order Number:

March, 2000 – Rev. 9 MC74HC125A/D
 MC74HC125A, MC74HC126A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
± 20 voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin mA
voltages to this high–impedance cir-
± 35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin mA cuit. For proper operation, Vin and
± 75 Vout should be constrained to the
ICC DC Supply Current, VCC and GND Pins mA
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
range GND (Vin or Vout) VCC.
PD Power Dissipation in Still Air Plastic DIP† 750 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
SOIC Package† 500 tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TSSOP Package† 450 level (e.g., either GND or VCC).
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 Unused outputs must be left open.
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
DC Input Voltage, Output Voltage

ÎÎÎ
0 VCC V

ÎÎ
(Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIH
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Input

ÎÎÎ
Vout = VCC – 0.1 V
|Iout| 20 µA
2.0
3.0
4.5
1.5
2.1
3.15
1.5
2.1
3.15
1.5
2.1
3.15
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V 2.0 0.5 0.5 0.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH 2.0 1.9 1.9 1.9 V
v Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH |Iout| 3.6 mA 3.0 2.48 2.34 2.2
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 6.0 mA 4.5 3.98 3.84 3.7
|Iout| 7.8 mA 6.0 5.48 5.34 5.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VIL
|Iout| 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL |Iout|
|Iout|
|Iout|
3.6 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4

http://onsemi.com
113
 MC74HC125A, MC74HC126A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Leakage Current Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 4.0 40

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
160 µA

(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v 25_C 85_C 125_C

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Input A to Output Y 2.0 90 115 135 ns
tPHL (Figures 1 and 3) 3.0 36 45 60

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 18 23 27

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 15 20 23

ÎÎÎÎÎ
tPLZ,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Propagation Delay, Output Enable to Y

ÎÎÎÎ
2.0

ÎÎÎÎ
120

ÎÎÎ
150

ÎÎÎÎ
180

ÎÎÎ
ns
tPHZ (Figures 2 and 4) 3.0 45 60 80

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 24 30 36
6.0 20 26 31

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZL,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZH ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Output Enable to Y

ÎÎÎ
(Figures 2 and 4)
2.0
3.0
90
36
115
45
135
60
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 18 23 27
6.0 15 20 23

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
(Figures 1 and 3)
2.0
3.0
60
22
75
28
90
34
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 12 15 18
6.0 10 13 15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Capacitance — 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cout

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Three–State Output Capacitance

ÎÎÎ
(Output in High–Impedance State)
— 15 15 15

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
pF

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Buffer)* 30 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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114
 MC74HC125A, MC74HC126A

SWITCHING WAVEFORMS

VCC
OE (HC125A) 50%
tr tf GND
VCC
90% VCC
INPUT A 50%
10% OE (HC126A) 50%
GND
tPHL GND
tPLH
OUTPUT Y 90% tPZL tPLZ
HIGH
50%
10% IMPEDANCE
OUTPUT Y 50%
10% VOL
tTLH tTHL tPZH tPHZ
90% VOH
OUTPUT Y 50% HIGH
Figure 1.
IMPEDANCE
Figure 2.

TEST POINT TEST POINT

CONNECT TO VCC WHEN
1 kΩ
OUTPUT OUTPUT TESTING tPLZ AND tPZL.
DEVICE CONNECT TO GND WHEN
DEVICE UNDER
UNDER TESTING tPHZ and tPZH.
CL* TEST CL *
TEST

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 3. Test Circuit Figure 4. Test Circuit

VCC

OE

A Y

HC125A
(1/4 OF THE DEVICE)
VCC

OE

A Y

HC126A
(1/4 OF THE DEVICE)

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115
MC74HC132A

Quad 2-Input NAND Gate

with Schmitt-Trigger Inputs
High–Performance Silicon–Gate CMOS
The MC74HC132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pullup http://onsemi.com
resistors, they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up MARKING
slowly changing waveforms. DIAGRAMS

•
14
Output Drive Capability: 10 LSTTL Loads PDIP–14
• Outputs Directly Interface to CMOS, NMOS, and TTL N SUFFIX MC74HC132AN
AWLYYWW
• Operating Voltage Range: 2.0 to 6.0 V CASE 646

• Low Input Current: 1.0 µA 1

• High Noise Immunity Characteristic of CMOS Devices 14

•
SOIC–14
In Compliance with the Requirements Defined by JEDEC Standard HC132A
D SUFFIX
AWLYWW
No. 7A CASE 751A
• Chip Complexity: 72 FETs or 18 Equivalent Gates 1
LOGIC DIAGRAM A = Assembly Location
WL or L = Wafer Lot
1
A1 YY or Y = Year
WW or W = Work Week
3
Y1
2 PIN ASSIGNMENT
B1

A1 1 14 VCC
A2 4
B1 2 13 B4
6
Y2 Y1 3 12 A4
5 A2 4 11 Y4
B2
Y = AB B2 5 10 B3
9 Y2 6 9 A3
A3
8 GND 7 8 Y3
Y3
10
B3

A4 12
11
Y4 ORDERING INFORMATION
13 Device Package Shipping
B4
MC74HC132AN PDIP–14 2000 / Box
PIN 14 = VCC
PIN 7 = GND MC74HC132AD SOIC–14 55 / Rail

FUNCTION TABLE MC74HC132ADR2 SOIC–14 2500 / Reel

Inputs Output
A B Y
L L H
L H H
H L H
H H L

 Semiconductor Components Industries, LLC, 2000 116 Publication Order Number:

March, 2000 – Rev. 7 MC74HC132A/D
 MC74HC132A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V
fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA
voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 25 mA cuit. For proper operation, Vin and
Vout should be constrained to the
± 50
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins mA
range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, Plastic DIP† 750 mW Unused inputs must always be
SOIC Package† 500 tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
level (e.g., either GND or VCC).
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
TL Lead Temperature, 1 mm from Case for 10 Seconds _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP or SOIC Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
DC Input Voltage, Output Voltage

ÎÎÎ
0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎÎÎ
(Referenced to GND)

ÎÎ
ÎÎÎ
Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
X
*When Vin
ÎÎ
ÎÎÎ
Input Rise and Fall Time (Figure 1)

ÎÎÎÎÎ
ÎÎÎ
0.5 VCC, ICC >> quiescent current.
— no
limit*
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VCC – 40_C to – 55_C to
Symbol Parameter Test Conditions V 25_C + 85_C + 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VT+ max

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Positive–Going

ÎÎÎÎ
ÎÎÎ
Input Threshold Voltage
Vout = 0.1 V
|Iout| 20 µA
2.0
4.5
1.5
3.15
1.5
3.15
1.5
3.15
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 3) 6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VT+ min Minimum Positive–Going Vout = 0.1 V 2.0 1.0 0.95 0.95 V
v Input Threshold Voltage |Iout| 20 µA 4.5 2.3 2.25 2.25

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 3) 6.0 3.0 2.95 2.95

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VT– max Maximum Negative–Going Vout = VCC – 0.1 V 2.0 0.9 0.95 0.95 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Threshold Voltage |Iout| 4.5 2.0 2.05 2.05
(Figure 3) 6.0 2.6 2.65 2.65

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VT– min

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
(Figure 3)
ÎÎÎ
Minimum Negative–Going

ÎÎÎÎ
ÎÎÎ
Input Threshold Voltage
Vout = VCC – 0.1 V
|Iout| 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VHmax

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Note 2 v
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
(Figure 3) ÎÎÎ
Maximum Hysteresis Voltage

ÎÎÎÎ
ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0
4.5
1.2
2.25
1.2
2.25
1.2
2.25
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
6.0 3.0 3.0 3.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VHmin Minimum Hysteresis Voltage Vout = 0.1 V or VCC – 0.1 V 2.0 0.2 0.2 0.2 V
Note 2 v (Figure 3) |Iout| 20 µA 4.5 0.4 0.4 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
6.0 0.5 0.5 0.5
NOTE: 1. VHmin > (VT+ min) – (VT– max); VHmax = (VT+ max) + (VT– min).
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

http://onsemi.com
117
 MC74HC132A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin VT– min or VT+ max 2.0 1.9 1.9 1.9 V
v
Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin –VT– min or VT+ max
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 3.98 3.84 3.7
|Iout| 5.2 mA 6.0 5.48 5.34 5.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin ≥VT+ max
|Iout| 20 µA
2.0
4.5
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1
v Vin≥VT+ max

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 0.26 0.33 0.4
|Iout| 5.2 mA 6.0 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 1.0 10 40 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current (per Package) Iout = 0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Input A or B to Output Y 2.0 125 155 190 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL (Figures 1 and 2) 4.5 25 31 38
6.0 21 26 32

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
(Figures 1 and 2)
2.0
4.5
75
15
95
19
110
22
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 13 16 19
Cin Maximum Input Capacitance — 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Gate)* 24 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

tr tf TEST POINT
VCC
90%
INPUT 50% OUTPUT
A OR B 10% GND
DEVICE
tPHL tPLH
UNDER
90% TEST CL*
Y 50%
10%
tTHL tTLH

*Includes all probe and jig capacitance

Figure 1. Switching Waveforms Figure 2. Test Circuit

http://onsemi.com
118
 MC74HC132A

VT , TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS

4

3
VHtyp

2 3 4 5 6
VCC, POWER SUPPLY VOLTAGE (VOLTS)
VHtyp = (VT + typ) – (VT – typ)

Figure 3. Typical Input Threshold, VT+, VT–

Versus Power Supply Voltage

VCC

Vout
Vin

(a) A SCHMITT TRIGGER SQUARES UP INPUTS (b) A SCHMITT TRIGGER OFFERS MAXIMUM NOISE
(a) WITH SLOW RISE AND FALL TIMES (b) IMMUNITY
VCC VCC
VH VH
VT + Vin VT +
Vin VT –
VT –

GND GND

VOH VOH

Vout Vout

VOL VOL

Figure 4. Typical Schmitt–Trigger Applications

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119
MC74HC138A

1-of-8 Decoder/
Demultiplexer
High–Performance Silicon–Gate CMOS
The MC74HC138A is identical in pinout to the LS138. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs. http://onsemi.com
The HC138A decodes a three–bit Address to one–of–eight
MARKING
active–low outputs. This device features three Chip Select inputs, two
DIAGRAMS
active–low and one active–high to facilitate the demultiplexing,
16
cascading, and chip–selecting functions. The demultiplexing function
PDIP–16
is accomplished by using the Address inputs to select the desired N SUFFIX MC74HC138AN
16 AWLYYWW
device output; one of the Chip Selects is used as a data input while the CASE 648
other Chip Selects are held in their active states. 1
1
• Output Drive Capability: 10 LSTTL Loads 16
• Outputs Directly Interface to CMOS, NMOS and TTL SO–16
HC138A
• Operating Voltage Range: 2.0 to 6.0 V 16
D SUFFIX
CASE 751B
AWLYWW
• Low Input Current: 1.0 µA 1
1
• High Noise Immunity Characteristic of CMOS Devices 16
• In Compliance with the Requirements Defined by JEDEC Standard TSSOP–16 HC
No. 7A 16 DT SUFFIX 138A
• Chip Complexity: 100 FETs or 29 Equivalent Gates 1
CASE 948F ALYW

LOGIC DIAGRAM 1
1 15 A = Assembly Location
A0 Y0 WL = Wafer Lot
ADDRESS 14
2 Y1 YY = Year
INPUTS A1 13
Y2 WW = Work Week
3 12
A2 Y3 ACTIVE–LOW
11 OUTPUTS
Y4 PIN ASSIGNMENT
10
Y5
9 A0 1 16 VCC
Y6
7
Y7 A1 2 15 Y0
A2 3 14 Y1
6
CS1
CHIP– PIN 16 = VCC CS2 4 13 Y2
4
SELECT CS2 PIN 8 = GND
CS3 5 12 Y3
INPUTS 5
CS3 CS1 6 11 Y4
FUNCTION TABLE Y7 7 10 Y5
Inputs Outputs GND 8 9 Y6
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H X X X H H H H H H H H
X H X X X X H H H H H H H H
L X X X X X H H H H H H H H
H L L L L L L H H H H H H H ORDERING INFORMATION
H L L L L H H L H H H H H H
Device Package Shipping
H L L L H L H H L H H H H H
H L L L H H H H H L H H H H MC74HC138AN PDIP–16 2000 / Box
H L L H L L H H H H L H H H MC74HC138AD SOIC–16 48 / Rail
H L L H L H H H H H H L H H
MC74HC138ADR2 SOIC–16 2500 / Reel
H L L H H L H H H H H H L H
H L L H H H H H H H H H H L MC74HC138ADT TSSOP–16 96 / Rail
H = high level (steady state); L = low level (steady state); X = don’t care MC74HC138ADTR2 TSSOP–16 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 120 Publication Order Number:

March, 2000 – Rev. 7 MC74HC138A/D
 MC74HC138A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 25 mA cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500
level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 .W/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 2) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC –55_C to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
v Voltage |Iout| 20 µA 3.0 0.9 0.9 0.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
1.35
1.8
1.35
1.8
1.35
1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
v Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 2.48 2.34 2.20
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 3.98 3.84 3.70
|Iout| 5.2 mA 6.0 5.48 5.34 5.20

http://onsemi.com
121
 MC74HC138A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC –55_C to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
2.0
4.5
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.40
|Iout| 4.0 mA 4.5 0.26 0.33 0.40
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 5.2 mA 6.0 0.26 0.33 0.40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current
µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160
Current (per Package) Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC –55_C to
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Input A to Output Y 2.0 135 170 205 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL (Figures 1 and 4) 3.0 90 125 165
4.5 27 34 41

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 23 29 35

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, CS1 to Output Y 2.0 110 140 165 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL (Figures 2 and 4) 3.0 85 100 125
4.5 22 28 33

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 19 24 28

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, CS2 or CS3 to Output Y 2.0 120 150 180 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL (Figures 3 and 4) 3.0 90 120 150
4.5 24 30 36

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 20 26 31

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 2 and 4) 3.0 30 40 55

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
15
13
19
16
22
19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Cin Maximum Input Capacitance — 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 55 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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122
 MC74HC138A

SWITCHING WAVEFORMS
tr tf
VALID VALID
VCC
VCC INPUT CS1 90%
INPUT A 50% 50%
10% GND
GND
tPHL tPLH
tPLH tPHL
90%
50%
OUTPUT Y 50% OUTPUT Y 10%
tTHL tTLH

Figure 1. Figure 2.

TEST POINT
tf tr
VCC OUTPUT
90%
INPUT 50% DEVICE
CS2, CS3 10% GND UNDER
tPHL tPLH TEST CL*
90%
50%
OUTPUT Y 10%
tTHL tTLH
*Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit

PIN DESCRIPTIONS

ADDRESS INPUTS Address inputs. For any other combination of CS1, CS2, and
A0, A1, A2 (Pins 1, 2, 3) CS3, the outputs are at a logic high.
Address inputs. These inputs, when the chip is selected,
OUTPUTS
determine which of the eight outputs is active–low.
Y0 – Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)
CONTROL INPUTS Active–low Decoded outputs. These outputs assume a
CS1, CS2, CS3 (Pins 6, 4, 5) low level when addressed and the chip is selected. These
Chip select inputs. For CS1 at a high level and CS2, CS3 outputs remain high when not addressed or the chip is not
at a low level, the chip is selected and the outputs follow the selected.

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 MC74HC138A

EXPANDED LOGIC DIAGRAM

15
Y0

14
Y1

13
1 Y2
A0

12
2 Y3
A1

11
Y4
3
A2

10
Y5
5
CS3
4 9
CS2 Y6

7
Y7

6
CS1

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124
MC74HCT138A

1-of-8 Decoder/
Demultiplexer with LSTTL
Compatible Inputs
High–Performance Silicon–Gate CMOS
http://onsemi.com
The MC74HCT138A is identical in pinout to the LS138. The
HCT138A may be used as a level converter for interfacing TTL or MARKING
NMOS outputs to High Speed CMOS inputs. DIAGRAMS
The HCT138A decodes a three–bit Address to one–of–eight 16
active–lot outputs. This device features three Chip Select inputs, two PDIP–16
MC74HCT138AN
active–low and one active–high to facilitate the demultiplexing, 16
N SUFFIX
AWLYYWW
cascading, and chip–selecting functions. The demultiplexing function CASE 648
1
is accomplished by using the Address inputs to select the desired 1
device output; one of the Chip Selects is used as a data input while the 16
other Chip Selects are held in their active states. SO–16
HCT138A
D SUFFIX
• Output Drive Capability: 10 LSTTL Loads 16
CASE 751B
AWLYWW

•
1
TTL/NMOS Compatible Input Levels 1
• Outputs Directly Interface to CMOS, NMOS, and TTL 16

• Operating Voltage Range: 4.5 to 5.5 V TSSOP–16 HCT

• Low Input Current: 1.0 µA 16 DT SUFFIX 138A
ALYW
CASE 948F
• In Compliance with the Requirements Defined by JEDEC Standard 1
1
No. 7A
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates A
WL
= Assembly Location
= Wafer Lot
YY = Year
WW = Work Week

ORDERING INFORMATION
Device Package Shipping
MC74HCT138AN PDIP–16 2000 / Box
MC74HCT138AD SOIC–16 48 / Rail
MC74HCT138ADR2 SOIC–16 2500 / Reel
MC74HCT138ADT TSSOP–16 96 / Rail
MC74HCT138ADTR2 TSSOP–16 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 125 Publication Order Number:

March, 2000 – Rev. 7 MC74HCT138A/D
 MC74HCT138A

LOGIC DIAGRAM FUNCTION TABLE

Inputs Outputs
1 15
A0 Y0 CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
ADDRESS 2 14 X X H X X X H H H H H H H H
A1 Y1
INPUTS X H X X X X H H H H H H H H
3 13
A2 Y2 L X X X X X H H H H H H H H
12 H L L L L L L H H H H H H H
Y3 ACTIVE–LOW H L L L L H H L H H H H H H
11 OUTPUTS
Y4 H L L L H L H H L H H H H H
10 H L L L H H H H H L H H H H
Y5
H L L H L L H H H H L H H H
9 H L L H L H H H H H H L H H
Y6
7 H L L H H L H H H H H H L H
Y7 H L L H H H H H H H H H H L
H = high level (steady state)
6 L = low level (steady state)
CS1 X = don’t care
CHIP–
SELECT 4 PIN 16 = VCC
CS2
INPUTS PIN 8 = GND
5
CS3
PIN ASSIGNMENT

A0 1 16 VCC
A1 2 15 Y0
A2 3 14 Y1
CS2 4 13 Y2
CS3 5 12 Y3
CS1 6 11 Y4
Y7 7 10 Y5

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
GND 8 9 Y6

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Design Criteria Value Units

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Count* 30.5 ea.

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Internal Gate Propagation Delay

ÎÎÎÎ
ÎÎÎ
Internal Gate Power Dissipation
1.5

5.0
ns

µW

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Speed Power Product

*Equivalent to a two–input NAND gate.

.0075 pJ

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126
 MC74HCT138A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 25 mA cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500
level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, TSSOP or SOIC Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
Î ÎÎ
Symbol

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
Parameter
DC Supply Voltage (Referenced to GND)
Min
4.5
Max
5.5
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIH
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 4.5 4.4 4.4 4.4 V
v Voltage |Iout| 20 µA 5.5 5.4 5.4 5.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout| 4.0 µA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA
Current

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
5.5 4.0 40 160 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
∆ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Additional Quiescent Supply Vin = 2.4 V, Any One Input ≥ – 55_C 25_C to 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Current Vin
i = VCC or GND,
GND Other In
Inputs
uts
lout = 0 µA 5.5 2.9 2.4 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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127
 MC74HCT138A

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
– 55 to
v v
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Symbol Parameter 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, Maximum Propagation Delay, Input A to Output Y 30 38 45 ns
tPHL (Figures 1 and 4)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Propagation Delay, CS1 to Output Y

ÎÎÎÎ
ÎÎÎ
(Figures 2 and 4)
27 34 41 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Output Transition Time, CS2 or CS3 to Output Y

ÎÎÎÎ
ÎÎÎ
(Figures 3 and 4)
30 38 45 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 15 19 22 ns
tTHL (Figures 2 and 4)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Maximum Input Rise and Fall Time 500 500 500 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Maximum Input Capacitance 10 10 10
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
pF

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)* 51 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

EXPANDED LOGIC DIAGRAM

15
Y0

14
Y1

13
1 Y2
A0

12
2 Y3
A1

11
Y4
3
A2

10
Y5
5
CS3
4 9
CS2 Y6

7
Y7

6
CS1

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128
 MC74HCT138A

SWITCHING WAVEFORMS

tr tf
VALID VALID
3V
3V 2.7 V
INPUT CS1 1.3 V
INPUT A 1.3 V 0.3 V GND
GND
tPHL tPLH
tPLH tPHL
90%
OUTPUT Y 1.3 V
1.3 V 10%
OUTPUT Y
tTHL tTLH

Figure 1. Figure 2.

tr tf
3V
2.7 V
INPUT 1.3 V
CS2, CS3 0.3 V GND
tPHL tPLH

90%
OUTPUT Y 1.3 V
10%

tTHL tTLH

Figure 3.

TEST CIRCUIT

TEST POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 4.

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129
MC74HC139A

Dual 1-of-4 Decoder/

Demultiplexer
High–Performance Silicon–Gate CMOS
The MC74HC139A is identical in pinout to the LS139. The device
inputs are compatible with standard CMOS outputs; with pullup http://onsemi.com
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 1–of–4 decoders, each of MARKING
which decodes a two–bit Address to one–of–four active–low outputs. DIAGRAMS
Active–low Selects are provided to facilitate the demultiplexing and 16
cascading functions. The demultiplexing function is accomplished by PDIP–16
N SUFFIX MC74HC139AN
using the Address inputs to select the desired device output, and 16
CASE 648
AWLYYWW
utilizing the Select as a data input. 1
1
• Output Drive Capability: 10 LSTTL Loads 16
• Outputs Directly Interface to CMOS, NMOS and TTL SO–16
HC139A
• Operating Voltage Range: 2.0 to 6.0 V 16
D SUFFIX
CASE 751B
AWLYWW
• Low Input Current: 1.0 µA 1
1
• High Noise Immunity Characteristic of CMOS Devices
A = Assembly Location
• In Compliance with the Requirements Defined by JEDEC Standard WL = Wafer Lot
No. 7A YY = Year
• Chip Complexity: 100 FETs or 25 Equivalent Gates
WW = Work Week

LOGIC DIAGRAM PIN ASSIGNMENT

2 4 SELECTa 1 16 VCC
ADDRESS A0a Y0a
INPUTS 3 5 A0a 2 15 SELECTb
A1a Y1a ACTIVE–LOW
6 OUTPUTS A1a 3 14 A0b
Y2a
7 Y0a 4 13 A1b
Y3a
Y1a 5 12 Y0b

1 PIN 16 = VCC Y2a 6 11 Y1b

SELECTa PIN 8 = GND
Y3a 7 10 Y2b
14 12 GND 8 9 Y3b
ADDRESS A0b Y0b
INPUTS 13 11
A1b Y1b ACTIVE–LOW
10 OUTPUTS
Y2b
9
Y3b
ORDERING INFORMATION
Device Package Shipping
15
SELECTb
MC74HC139AN PDIP–16 2000 / Box
FUNCTION TABLE
MC74HC139AD SOIC–16 48 / Rail
Inputs Outputs MC74HC139ADR2 SOIC–16 2500 / Reel
Select A1 A0 Y0 Y1 Y2 Y3
H X X H H H H
L L L L H H H
L L H H L H H
L H L H H L H
L H H H H H L
X = don’t care

 Semiconductor Components Industries, LLC, 2000 130 Publication Order Number:

March, 2000 – Rev. 7 MC74HC139A/D
 MC74HC139A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 25 mA cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500
level (e.g., either GND or VCC).
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 Unused outputs must be left open.
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
Î ÎÎ
Symbol

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
Max
6.0
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC – 55 to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ 25_C 85_C 125_C
Symbol Parameter Test Conditions V Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0
4.5
0.5
1.35
0.5
1.35
0.5
1.35
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 1.8 1.8 1.8
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
Voltage

ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
|Iout| 20 µA 4.5
6.0
4.4
5.9
4.4
5.9
4.4
5.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 4.0 mA 4.5 3.98 3.84 3.70
v |Iout| 5.2 mA 6.0 5.48 5.34 5.20

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
2.0
4.5
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 4.0 mA 4.5 0.26 0.33 0.40
|Iout| 5.2 mA 6.0 0.26 0.33 0.40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 µA
Current (per Package) Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

http://onsemi.com
131
 MC74HC139A

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Select to Output Y 2.0 115 145 175 ns
tPHL (Figures 1 and 3) 4.5 23 29 35

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 20 25 30

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Input A to Output Y 2.0 115 145 175 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL (Figures 2 and 3) 4.5 23 29 35
6.0 20 25 30

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
(Figures 1 and 3)
2.0
4.5
75
15
95
19
110
22
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 13 16 19
Cin Maximum Input Capacitance — 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Decoder)* 55 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS

tf tr
VCC VALID VALID
90% VCC
50%
SELECT 10% GND INPUT A 50%
tPHL tPLH GND
90% tPLH tPHL
50%
OUTPUT Y 10% OUTPUT Y 50%
tTHL tTLH

Figure 1. Figure 2.

TEST POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 3. Test Circuit

http://onsemi.com
132
 MC74HC139A

PIN DESCRIPTIONS

ADDRESS INPUTS inputs. A high level on this input forces all outputs to a high
A0a, A1a, A0b, A1b (Pins 2, 3, 14, 13) level.
Address inputs. These inputs, when the respective 1–of–4
OUTPUTS
decoder is enabled, determine which of its four active–low Y0a – Y3a, Y0b – Y3b (Pins 4 – 7, 12, 11, 10, 9)
outputs is selected.
Active–low outputs. These outputs assume a low level
CONTROL INPUTS when addressed and the appropriate Select input is active.
Selecta, Selectb (Pins 1, 15) These outputs remain high when not addressed or the
Active–low select inputs. For a low level on this input, the appropriate Select input is inactive.
outputs for that particular decoder follow the Address

EXPANDED LOGIC DIAGRAM

(1/2 OF DEVICE)

SELECT
Y0

Y1
A0

Y2

Y3
A1

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133
MC74HC157A

Quad 2-Input Data

Selectors / Multiplexers
High–Performance Silicon–Gate CMOS
The MC74HC157A is identical in pinout to the LS157. The device
inputs are compatible with standard CMOS outputs; with pullup http://onsemi.com
resistors, they are compatible with LSTTL outputs.
This device routes 2 nibbles (A or B) to a single port (Y) as MARKING
determined by the Select input. The data is presented at the outputs in DIAGRAMS
noninverted form. A high level on the Output Enable input sets all four 16
Y outputs to a low level. PDIP–16
N SUFFIX MC74HC157AN
• Output Drive Capability: 10 LSTTL Loads
16
CASE 648
AWLYYWW

• Outputs Directly Interface to CMOS, NMOS, and TTL

1
1
• Operating Voltage Range: 2.0 to 6.0 V 16

• Low Input Current: 1.0 µA

SO–16
D SUFFIX
HC157A
• High Noise Immunity Characteristic of CMOS Devices 16
CASE 751B
AWLYWW

•
1
In Compliance with the Requirements Defined by JEDEC Standard 1
No. 7A 16

• Chip Complexity: 82 FETs or 20.5 Equivalent Gates TSSOP–16 HC

16 DT SUFFIX 157A
LOGIC DIAGRAM CASE 948F ALYW
1
2 1
A0
5 A = Assembly Location
NIBBLE A1 WL = Wafer Lot
11 YY = Year
A INPUTS A2 4
Y0
14 WW = Work Week
A3 7
Y1
9 DATA
3 Y2 OUTPUTS PIN ASSIGNMENT
B0 12
6 Y3
B1 SELECT 1 16 VCC
NIBBLE
10 OUTPUT
B INPUTS B2 A0 2 15
13 ENABLE
B3 PIN 16 = VCC
PIN 8 = GND B0 3 14 A3
Y0 4 13 B3
1
SELECT A1 5 12 Y3
OUTPUT 15
ENABLE B1 6 11 A2
Y1 7 10 B2
FUNCTION TABLE
GND 8 9 Y2
Inputs
Output Outputs
Enable Select Y0 – Y3
H X L
L L A0 – A3
L H B0 – B3 ORDERING INFORMATION
Device Package Shipping
X = don’t care
A0 – A3, B0 – B3 = the levels of the MC74HC157AN PDIP–16 2000 / Box
respective Data–Word Inputs.
MC74HC157AD SOIC–16 48 / Rail
MC74HC157ADR2 SOIC–16 2500 / Reel
MC74HC157ADT TSSOP–16 96 / Rail
MC74HC157ADTR2 TSSOP–16 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 134 Publication Order Number:

March, 2000 – Rev. 8 MC74HC157A/D
 MC74HC157A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage 0 VCC V
(Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Rise and Fall Time

ÎÎÎ
VCC = 2.0 V 0 1000 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
(Figure 1)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
VCC = 4.5 V
VCC = 6.0 V
0
0
500
400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v Voltage |Iout| 20 µA 3.0 2.1 2.1 2.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2
VIL Maximum Low–Level Input Vout = 0.1 V 2.0 0.5 0.5 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
Voltage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
|Iout| 20 µA 3.0
4.5
6.0
0.9
1.35
1.8
0.9
1.35
1.8
0.9
1.35
1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎÎÎÎÎÎÎ
Vin = VIH 2.0 1.9 1.9 1.9 V

v ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9
Vin = VIH |Iout| 2.4 mA 3.0 2.48 2.34 2.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
|Iout|
|Iout|
6.0 mA
7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIL 2.0 0.1 0.1 0.1 V
v Voltage |Iout| 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.4
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 6.0 mA 4.5 0.26 0.33 0.4
|Iout| 7.8 mA 6.0 0.26 0.33 0.4

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135
 MC74HC157A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Leakage Current Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 4.0 40

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
160 µA

(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v 25_C 85_C 125_C

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Input A or B to Output Y 2.0 105 130 160 ns
tPHL (Figures 1 and 4) 3.0 65 85 115

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 21 26 32

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 18 22 27

ÎÎÎÎÎ
tPLH,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Propagation Delay, Select to Output Y

ÎÎÎÎ
2.0

ÎÎÎÎ
110

ÎÎÎ
140

ÎÎÎÎ
165

ÎÎÎ
ns
tPHL (Figures 2 and 4) 3.0 70 90 115

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 22 28 33
6.0 19 24 28

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Output Enable to Output Y

ÎÎÎ
(Figures 3 and 4)
2.0
3.0
100
60
125
80
150
110
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 20 25 30
6.0 17 21 26

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
(Figures 1 and 4)
2.0
3.0
75
27
95
32
110
36
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Capacitance — 10 10 10
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
pF

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 33 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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136
 MC74HC157A

PIN DESCRIPTIONS

INPUTS The data present on these pins is in its noninverted form. For
A0, A1, A2, A3 (Pins 2, 5, 11, 14) the Output Enable input at a high level, the outputs are at a
Nibble A inputs. The data present on these pins is low level.
transferred to the outputs when the Select input is at a low
CONTROL INPUTS
level and the Output Enable input is at a low level. The data Select (Pin 1)
is presented to the outputs in noninverted form.
Nibble select. This input determines the data word to be
B0, B1, B2, B3 (Pins 3, 6, 10, 13) transferred to the outputs. A low level on this input selects
Nibble B inputs. The data present on these pins is the A inputs and a high level selects the B inputs.
transferred to the outputs when the Select input is at a high Output Enable (Pin 15)
level and the Output Enable input is at a low level. The data
is presented to the outputs in noninverted form. Output Enable input. A low level on this input allows the
selected input data to be presented at the outputs. A high
OUTPUTS level on this input sets all outputs to a low level.
Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)
Data outputs. The selected input Nibble is presented at
these outputs when the Output Enable input is at a low level.

SWITCHING WAVEFORMS

tr tf tr tf
VCC VCC
90% SELECT 90%
INPUT A OR B 50% 50%
10% GND 10% GND
tPLH tPHL tPLH tPHL
90% OUTPUT Y 90%
OUTPUT Y 50% 50%
10% 10%
tTLH tTHL tTLH tTHL

Figure 1. HC157A Figure 2. Y versus Select, Noninverted

tr tf
VCC
OUTPUT 90%
50%
ENABLE 10% GND
tPHL tPLH
90%
OUTPUT Y 50%
10%
tTHL tTLH

Figure 3. HC157A

TEST POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 4. Test Circuit

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137
 MC74HC157A

EXPANDED LOGIC DIAGRAM

2
A0
4
3 Y0
B0
5
A1
7
6 Y1
B1
NIBBLE
11 DATA
OUTPUTS A2 OUTPUTS
10 9 Y2
B2
14
A3
12 Y3
13
B3
15
OUTPUT ENABLE
1
SELECT

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138
MC74HC161A,
MC74HC163A

Presettable Counters
High–Performance Silicon–Gate CMOS
The MC74HC161A and HC163A are identical in pinout to the
LS161 and LS163. The device inputs are compatible with standard
http://onsemi.com
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs. MARKING
The HC161A and HC163A are programmable 4–bit binary counters DIAGRAMS
with asynchronous and synchronous reset, respectively. 16
PDIP–16
• Output Drive Capability: 10 LSTTL Loads N SUFFIX MC74HC16xAN
•
16 AWLYYWW
Outputs Directly Interface to CMOS, NMOS, and TTL CASE 648
•
1
Operating Voltage Range: 2.0 to 6.0 V 1

• Low Input Current: 1.0 µA

16
SO–16
• High Noise Immunity Characteristic of CMOS Devices D SUFFIX
HC16xA
AWLYWW
•
16
In Compliance with the Requirements Defined by JEDEC Standard CASE 751B
1
No. 7A 1

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
• Chip Complexity: 192 FETs or 48 Equivalent Gates
A
WL
= Assembly Location
= Wafer Lot

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ Count YY = Year

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
Device Mode Reset Mode WW = Work Week

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
HC161A Binary Asynchronous
ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
HC163A Binary Synchronous
Device Package Shipping
MC74HC16xAN PDIP–16 2000 / Box
LOGIC DIAGRAM
MC74HC16xAD SOIC–16 48 / Rail
MC74HC16xADR2 SOIC–16 2500 / Reel
3 14
P0 Q0 PIN ASSIGNMENT
PRESET 4 13 BCD OR
P1 Q1
DATA BINARY RESET 1 16 VCC
5 12
INPUTS P2 Q2 OUTPUT CLOCK 2 15 RIPPLE
CARRY OUT
6 11
P3 Q3 P0 3 14 Q0
P1 4 13 Q1
RIPPLE
2 15
CLOCK CARRY P2 5 12 Q2
OUT
P3 6 11 Q3
1 ENABLE P 7 10 ENABLE T
RESET
9 PIN 16 = VCC GND 8 9 LOAD
LOAD
PIN 8 = GND
7 FUNCTION TABLE
COUNT ENABLE P
ENABLES 10 Inputs Output
ENABLE T
Clock Reset* Load Enable P Enable T Q
L X X X Reset
H L X X Load Preset Data
H H H H Count
H H L X No Count
H H X L No Count

*HC163A only. HC161A is an Asynchronous Reset Device

H = high level, L = low level, X = don’t care

 Semiconductor Components Industries, LLC, 2000 139 Publication Order Number:

March, 2000 – Rev. 8 MC74HC161A/D
 MC74HC161A, MC74HC163A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 25 mA cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500
level (e.g., either GND or VCC).
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 Unused outputs must be left open.

_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
Î ÎÎ
Symbol

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
Max
6.0
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V 0 1000 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
VCC = 3.0 V 0 600
VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC = 6.0 V 0 400

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140
 MC74HC161A, MC74HC163A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v V 25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions Unit
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
Voltage
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
|Iout| 20 µA 3.0
4.5
2.1
3.15
2.1
3.15
2.1
3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
v
Voltage |Iout| 20 µA 3.0 0.9 0.9 0.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 1.35 1.35 1.35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
v
Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ 6.0 5.9 5.9 5.9

v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ Vin = VIH or VIL |Iout| 3.6 mA 3.0 2.48 2.34 2.2
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 5.2 mA 6.0 5.48 5.34 5.2
VOL Maximum Low–Level Output V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL 2.0 0.1 0.1 0.1
v
Voltage |Iout| 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 3.6 mA 3.0 0.26 0.33 0.4
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 0.26 0.33 0.4
|Iout| 5.2 mA 6.0 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4.0 40 160 µA
Current (per Package) Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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141
 MC74HC161A, MC74HC163A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Fig. V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
fmax Maximum Clock Frequency (50% Duty Cycle)* 1, 7 2.0 6 5 4 MHz
3.0 15 12 10

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 30 24 20

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 35 28 24

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH Maximum Propagation Delay, Clock to Q 1, 7 2.0 120 160 200 ns
3.0 75 120 150

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 20 23 28

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 16 20 22

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL 1, 7 2.0 145 185 220 ns
3.0 100 135 150

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 22 25 30

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 18 20 23

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL Maximum Propagation Delay, Reset to Q (HC161A Only) 2, 7 2.0 145 185 220 ns
3.0 100 135 150

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 20 22 25
6.0 17 19 21

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Enable T to Ripple Carry Out

ÎÎÎ
3, 7 2.0
3.0
110
60
150
115
190
140
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 16 18 20
6.0 14 15 17

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
3, 7 2.0
3.0
135
100
175
130
210
160
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 18 20 22
6.0 15 16 20

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Clock to Ripple Carry Out

ÎÎÎ
1, 7 2.0
3.0
120
75
160
135
200
150
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 22 27 30
6.0 18 22 25

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
1, 7 2.0
3.0
145
100
185
135
220
150
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 22 28 35
6.0 20 24 28

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
(HC161A Only) ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Reset to Ripple Carry Out

ÎÎÎ
2, 7 2.0
3.0
155
120
190
140
230
155
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
4.5

ÎÎÎÎ
22

ÎÎÎ
26

ÎÎÎÎ
30

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Output Transition Time, Any Output 2, 7
6.0
2.0
18
75
22
95
25
110 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTHL 3.0 30 40 55
4.5 15 19 22

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Cin ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Input Capacitance 1, 7
6.0
—
13
10
16
10
19
10
*Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out
pF

propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable.
See Applications information in this data sheet.
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Gate)* 45 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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142
 MC74HC161A, MC74HC163A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Fig. V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tsu Minimum Setup Time, 5 2.0 40 60 80 ns
Preset Data Inputs to Clock 3.0 20 30 40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 20 30

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 12 18 20

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tsu Minimum Setup Time, 5 2.0 60 75 90 ns
Load to Clock 3.0 25 30 40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 20 30

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 12 18 20

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tsu Minimum Setup Time, 4 2.0 60 75 90 ns
Reset to Clock (HC163A Only) 3.0 25 30 40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 20 25 35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 17 23 25

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tsu Minimum Setup Time, 6 2.0 80 95 110 ns
Enable T or Enable P to Clock 3.0 35 40 50

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 20 25 35
6.0 17 23 25

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
th
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Minimum Hold Time,

ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Clock to Load or Preset Data Inputs
5 2.0
3.0
3
3
3
3
3
3
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3 3 3
6.0 3 3 3

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
th
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Minimum Hold Time,

ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Clock to Reset (HC163A Only)
4 2.0
3.0
3
3
3
3
3
3
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3 3 3
6.0 3 3 3

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
th
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Minimum Hold Time,

ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Clock to Enable T or Enable P
6 2.0
3.0
3
3
3
3
3
3
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3 3 3
6.0 3 3 3

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
trec

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum Recovery Time,

ÎÎÎ
Reset Inactive to Clock (HC161A Only)
2 2.0
3.0
80
35
95
40
110
50
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 20 26
6.0 12 17 23

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
trec

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum Recovery Time,

ÎÎÎ
Load Inactive to Clock
5 2.0
3.0
4.5
80
35
15
95
40
20
110
50
26
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎtw ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Minimum Pulse Width, 1
6.0
2.0
12
60
17
75
23
90 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Clock 3.0 25 30 40
4.5 12 15 18

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎtw ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Minimum Pulse Width, 2
6.0
2.0
10
60
13
75
15
90 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Reset (HC161A Only) 3.0 25 30 40
4.5 12 15 18

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
3.0 800 800 800
4.5 500 500 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 400 400 400

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143
 MC74HC161A, MC74HC163A

FUNCTION DESCRIPTION

The HC161A/163A are programmable 4–bit synchronous level. The HC161A resets asynchronously, and the HC163A
counters that feature parallel Load, synchronous or resets with the rising edge of the Clock input (synchronous
asynchronous Reset, a Carry Output for cascading and reset).
count–enable controls. Loading
The HC161A and HC163A are binary counters with With the rising edge of the Clock, a low level on Load (Pin
asynchronous Reset and synchronous Reset, respectively. 9) loads the data from the Preset Data input pins (P0, P1, P2,
INPUTS P3) into the internal flip–flops and onto the output pins, Q0
Clock (Pin 2)
through Q3. The count function is disabled as long as Load
is low.
The internal flip–flops toggle and the output count
advances with the rising edge of the Clock input. In addition, Count Enable/Disable
control functions, such as resetting and loading occur with These devices have two count–enable control pins:
the rising edge of the Clock input. Enable P (Pin 7) and Enable T (Pin 10). The devices count
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
when these two pins and the Load pin are high. The logic
equation is:
These are the data inputs for programmable counting.
Data on these pins may be synchronously loaded into the Count Enable = Enable P • Enable T • Load
internal flip–flops and appear at the counter outputs. P0 (Pin The count is either enabled or disabled by the control
3) is the least–significant bit and P3 (Pin 6) is the inputs according to Table 1. In general, Enable P is a
most–significant bit. count–enable control: Enable T is both a count–enable and
a Ripple–Carry Output control.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11) Table 1. Count Enable/Disable
These are the counter outputs. Q0 (Pin 14) is the Control Inputs Result at Outputs
least–significant bit and Q3 (Pin 11) is the most–significant
Load Enable P Enable T Q0 – Q3 Ripple Carry Out
bit.
H H H Count
Ripple Carry Out (Pin 15) High when Q0–Q3
When the counter is in its maximum state 1111, this output L H H No are maximum*
Count
goes high, providing an external look–ahead carry pulse that
may be used to enable successive cascaded counters. Ripple X L H No High when Q0–Q3
Carry Out remains high only during the maximum count Count are maximum*
state. The logic equation for this output is: X X L No
L
Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3 Count

CONTROL FUNCTIONS *Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111.

Resetting
A low level on the Reset pin (Pin 1) resets the internal
flip–flops and sets the outputs (Q0 through Q3) to a low
OUTPUT STATE DIAGRAMS

0 1 2 3 4

15 5

14 6

13 7

12 11 10 9 8

Binary Counters

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144
 MC74HC161A, MC74HC163A

SWITCHING WAVEFORMS

tr tf tw
VCC VCC
CLOCK 90%
50% RESET 50%
10% GND GND
tw tPHL
1/fmax
ANY 50%
tPLH tPHL
OUTPUT
ANY 90% trec
50%
OUTPUT 10% VCC
CLOCK 50%
tTLH tTHL GND

Figure 1. Figure 2.

tr tf
VCC 50%
ENABLE T 90% RESET
50%
10% GND
tPLH tPHL tsu th
RIPPLE 90%
50% VCC
CARRY 10% CLOCK 50%
OUT
tTLH tTHL GND

Figure 3. Figure 4. HC163A Only

VALID

INPUTS VCC
P0, P1, 50%
P2, P3 GND

tsu th
VALID
VCC
LOAD 50% ENABLE T VCC
GND OR 50%
ENABLE P GND
tsu th trec tsu th
VCC
VCC 50%
CLOCK
CLOCK 50% GND
GND
Figure 5. Figure 6.

TEST CIRCUIT

TEST POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 7.

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145
 T0 14
R Q0 Q0
C
C
LOAD
3 LOAD Q0
P0 P0

T1 13
R Q1 Q1
C
Figure 8. 4–Bit Binary Counter with Asynchronous Reset

C
LOAD
LOAD Q1
P1 4 P1

MC74HC161A, MC74HC163A
T2 12
R Q2 Q2
C
C
LOAD
http://onsemi.com

(MC74HC161A)

5 LOAD Q2
P2 P2
146

T3 11
R Q3 Q3
C
C
LOAD
6 LOAD
P3 P3
15 RIPPLE
CARRY
OUT
7
ENABLE P

VCC = PIN 16
10 GND = PIN 8
ENABLE T

1
RESET R
The flip–flops shown in the circuit diagrams are Toggle–Enable flip–flops. A Toggle–
Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data from
9 LOAD
LOAD Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
LOAD the flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flop
2 on the next rising edge of the clock.
CLOCK C A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
C output of the flip–flop low.
 MC74HC161A, MC74HC163A

Sequence illustrated in waveforms:

1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one and two.
4. Inhibit.

RESET (HC161A)
(ASYNCHRONOUS)
RESET (HC163A)
(SYNCHRONOUS)
LOAD

P0

PRESET P1
DATA
INPUTS P2

P3
CLOCK (HC161A)

CLOCK (HC163A)

ENABLE P
COUNT
ENABLES
ENABLE T

Q0

Q1
OUTPUTS
Q2

Q3
RIPPLE
CARRY
OUT 12 13 14 15 0 1 2
COUNT INHIBIT
RESET LOAD

Figure 9. Timing Diagram

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147
 T0 14
R Q0 Q0
C
C
LOAD
3 LOAD Q0
P0 P0

T1 13
R Q1 Q1
C
Figure 10. 4–Bit Binary Counter with Synchronous Reset

C
LOAD
4 LOAD Q1
P1 P1

MC74HC161A, MC74HC163A
T2 12
R Q2 Q2
C
C
LOAD
http://onsemi.com

(MC74HC163A)

5 LOAD Q2
P2 P2
148

T3 11
R Q3 Q3
C
C
LOAD
6 LOAD
P3 P3
15 RIPPLE
CARRY
OUT
7
ENABLE P

VCC = PIN 16
10 GND = PIN 8
ENABLE T

1
RESET R
The flip–flops shown in the circuit diagrams are Toggle–Enable flip–flops. A Toggle–
Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data from
9 LOAD
LOAD Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
LOAD the flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flop
2 on the next rising edge of the clock.
CLOCK C A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
C output of the flip–flop low.
 MC74HC161A, MC74HC163A

TYPICAL APPLICATIONS CASCADING

LOAD

INPUTS INPUTS INPUTS

LOAD P0 P1 P2 P3 LOAD P0 P1 P2 P3 LOAD P0 P1 P2 P3

H = COUNT
ENABLE P ENABLE P ENABLE P
L = DISABLE
RIPPLE RIPPLE RIPPLE TO
H = COUNT
ENABLE T CARRY ENABLE T CARRY ENABLE T CARRY MORE
L = DISABLE
OUT OUT OUT SIGNIFICANT
CLOCK CLOCK CLOCK STAGES

R Q0 Q1 Q2 Q3 R Q0 Q1 Q2 Q3 R Q0 Q1 Q2 Q3

RESET

OUTPUTS OUTPUTS OUTPUTS

CLOCK

NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on
number of stages. This limitation is due to set up times between Enable (Port) and Clock.

Figure 11. N–Bit Synchronous Counters

INPUTS INPUTS INPUTS

LOAD
ENABLE P
ENABLE T

LOAD P0 P1 P2 P3 LOAD P0 P1 P2 P3 LOAD P0 P1 P2 P3

ENABLE P ENABLE P ENABLE P

RIPPLE RIPPLE RIPPLE TO
ENABLE T CARRY ENABLE T CARRY ENABLE T CARRY MORE
OUT OUT OUT SIGNIFICANT
CLOCK CLOCK CLOCK CLOCK STAGES

R Q0 Q1 Q2 Q3 R Q0 Q1 Q2 Q3 R Q0 Q1 Q2 Q3

RESET

OUTPUTS OUTPUTS OUTPUTS

Figure 12. Nibble Ripple Counter

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149
 MC74HC161A, MC74HC163A

TYPICAL APPLICATIONS VARYING THE MODULUS

HC163A HC163A
OTHER OTHER
Q0 OPTIONAL BUFFER Q0 OPTIONAL BUFFER
INPUTS INPUTS
Q1 FOR NOISE REJECTION Q1 FOR NOISE REJECTION

Q2 OUTPUT Q2 OUTPUT

Q3 Q3

RESET RESET

Figure 13. Modulo–5 Counter Figure 14. Modulo–11 Counter

The HC163A facilitates designing counters of any modulus with minimal external logic. The output is glitch–free due to
the synchronous Reset.

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150
MC74HC164A

8-Bit Serial-Input/
Parallel-Output Shift
Register
High–Performance Silicon–Gate CMOS
The MC74HC164A is identical in pinout to the LS164. The device http://onsemi.com
inputs are compatible with standard CMOS outputs; with pullup MARKING
resistors, they are compatible with LSTTL outputs. DIAGRAMS
The MC74HC164A is an 8–bit, serial–input to parallel–output shift 14
register. Two serial data inputs, A1 and A2, are provided so that one PDIP–14
N SUFFIX MC74HC164AN
input may be used as a data enable. Data is entered on each rising edge
CASE 646 AWLYYWW
of the clock. The active–low asynchronous Reset overrides the Clock
and Serial Data inputs. 1
14
• Output Drive Capability: 10 LSTTL Loads SOIC–14
HC164A
• Outputs Directly Interface to CMOS, NMOS, and TTL D SUFFIX
AWLYWW
CASE 751A
• Operating Voltage Range: 2 to 6 V
1
• Low Input Current: 1 µA 14
• High Noise Immunity Characteristic of CMOS Devices TSSOP–14 HC
• In Compliance with the Requirements Defined by JEDEC Standard DT SUFFIX 164A
CASE 948G ALYW
No. 7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates 1
A = Assembly Location
LOGIC DIAGRAM WL or L = Wafer Lot
YY or Y = Year
3 WW or W = Work Week
SERIAL 1 QA
A1
DATA DATA 4 PIN ASSIGNMENT
2 QB
INPUTS A2 5
QC
6 A1 1 14 VCC
QD PARALLEL
10 DATA A2 2 13 QH
QE OUTPUTS
11 QA 3 12 QG
QF
8 12 QB 4 11 QF
CLOCK QG
13 QC 5 10 QE
QH
QD 6 9 RESET
9
RESET PIN 14 = VCC GND 7 8 CLOCK
PIN 7 = GND

FUNCTION TABLE
Inputs Outputs
ORDERING INFORMATION
Reset Clock A1 A2 QA QB … QH Device Package Shipping
L X X X L L … L MC74HC164AN PDIP–14 2000 / Box
H X X No Change MC74HC164AD SOIC–14 55 / Rail
H H D D QAn … QGn
H D H D QAn … QGn MC74HC164ADR2 SOIC–14 2500 / Reel
MC74HC164ADT TSSOP–14 96 / Rail
D = data input
QAn – QGn = data shifted from the preceding MC74HC164ADTR2 TSSOP–14 2500 / Reel
stage on a rising edge at the clock input.

 Semiconductor Components Industries, LLC, 2000 151 Publication Order Number:

March, 2000 – Rev. 1 MC74HC164A/D
 MC74HC164A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Guaranteed Limit

v ÎÎÎÎ
v ÎÎÎ
VCC –55_C to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIH ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Parameter

ÎÎÎ
Minimum High–Level Input
Test Conditions
Vout = 0.1 V or VCC – 0.1 V
V
2.0
25_C
1.5
85_C
1.5
125_C
1.5
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 20 µA 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL |Iout|
|Iout|
|Iout|
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20

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152
 MC74HC164A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC –55_C to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
vVoltage |Iout| 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.40
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 0.26 0.33 0.40
|Iout| 5.2 mA 6.0 0.26 0.33 0.40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 µA
Current (per Package) Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
–55_C to

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fmax

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Clock Frequency (50% Duty Cycle)

ÎÎÎ
(Figures 1 and 4)
2.0
3.0
10
20
10
20
10
20
MHz

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 40 35 30
6.0 50 45 40

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Clock to Q

ÎÎÎ
(Figures 1 and 4)
2.0
3.0
4.5
160
100
32
200
150
40
250
200
48
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Propagation Delay, Reset to Q
6.0
2.0
27
175
34
220
42
260 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figures 2 and 4) 3.0 100 150 200
4.5 35 44 53

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Output Transition Time, Any Output
6.0
2.0
30
75
37
95
45
110 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTHL (Figures 1 and 4) 3.0 27 32 36
4.5 15 19 22

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 13 16 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Cin Maximum Input Capacitance — 10 10 10 pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 180 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC164A

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6 ns)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC –55_C to
v v
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tsu Minimum Setup Time, A1 or A2 to Clock 2.0 25 35 40 ns
(Figure 3) 3.0 15 20 25

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 7 8 9

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5 6 6

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
th Minimum Hold Time, Clock to A1 or A2 2.0 3 3 3 ns
(Figure 3) 3.0 3 3 3

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3 3 3

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 3 3 3

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
trec Minimum Recovery Time, Reset Inactive to Clock 2.0 3 3 3 ns
(Figure 2) 3.0 3 3 3

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3 3 3

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 3 3 3

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Clock 2.0 50 60 75 ns
(Figure 1) 3.0 26 35 45

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 12 15 20
6.0 10 12 15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tw
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(Figure 2)
ÎÎÎÎÎÎÎ
Minimum Pulse Width, Reset

ÎÎÎ
2.0
3.0
50
26
60
35
75
45
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 12 15 20
6.0 10 12 15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tr, tf
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
(Figure 1) ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Rise and Fall Times

ÎÎÎ
2.0
3.0
1000
800
1000
800
1000
800
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 500 500 500
6.0 400 400 400
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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 MC74HC164A

PIN DESCRIPTIONS

INPUTS register is completely static, allowing clock rates down to

DC in a continuous or intermittent mode.
A1, A2 (Pins 1, 2)
Serial Data Inputs. Data at these inputs determine the data OUTPUTS
to be entered into the first stage of the shift register. For a QA – QH (Pins 3, 4, 5, 6, 10, 11, 12, 13)
high level to be entered into the shift register, both A1 and
Parallel Shift Register Outputs. The shifted data is
A2 inputs must be high, thereby allowing one input to be
presented at these outputs in true, or noninverted, form.
used as a data–enable input. When only one serial input is
used, the other must be connected to VCC. CONTROL INPUT
Clock (Pin 8) Reset (Pin 9)
Shift Register Clock. A positive–going transition on this Active–Low, Asynchronous Reset Input. A low voltage
pin shifts the data at each stage to the next stage. The shift applied to this input resets all internal flip–flops and sets
Outputs QA – QH to the low level state.

SWITCHING WAVEFORMS

tr tf tw
VCC VCC
90% RESET 50%
CLOCK 50%
10% GND GND
tw tPHL
1/fmax
Q 50%
tPLH tPHL
90% trec
Q 50% VCC
10%
CLOCK 50%
tTLH tTHL GND

Figure 1. Figure 2.

TEST POINT

VALID OUTPUT
VCC DEVICE
A1 OR A2 50% UNDER
GND TEST CL*
tsu th
VCC
CLOCK 50%
GND
*Includes all probe and jig capacitance

Figure 3. Figure 4. Test Circuit

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 MC74HC164A

EXPANDED LOGIC DIAGRAM

8
CLOCK

1
A1
2 D Q D Q D Q D Q D Q D Q D Q D Q
A2
R R R R R R R R
9
RESET

3 4 5 6 10 11 12 13

QA QB QC QD QE QF QG QH

TIMING DIAGRAM

CLOCK
A1
A2

RESET
QA

QB

QC

QD

QE

QF

QG

QH

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MC74HC165A

8-Bit Serial or
Parallel-Input/
Serial-Output Shift Register
High–Performance Silicon–Gate CMOS
The MC74HC165A is identical in pinout to the LS165. The device http://onsemi.com
inputs are compatible with standard CMOS outputs; with pullup MARKING
resistors, they are compatible with LSTTL outputs. DIAGRAMS
This device is an 8–bit shift register with complementary outputs 14
from the last stage. Data may be loaded into the register either in PDIP–14
N SUFFIX MC74HC165AN
parallel or in serial form. When the Serial Shift/Parallel Load input is
CASE 646 AWLYYWW
low, the data is loaded asynchronously in parallel. When the Serial
Shift/Parallel Load input is high, the data is loaded serially on the 1
14
rising edge of either Clock or Clock Inhibit (see the Function Table).
SOIC–14
The 2–input NOR clock may be used either by combining two HC165A
D SUFFIX
independent clock sources or by designating one of the clock inputs to AWLYWW
CASE 751A
act as a clock inhibit. 1
• Output Drive Capability: 10 LSTTL Loads 14

• Outputs Directly Interface to CMOS, NMOS, and TTL TSSOP–14 HC

165A
• Operating Voltage Range: 2 to 6 V DT SUFFIX
CASE 948G ALYW
• Low Input Current: 1 µA
1
• High Noise Immunity Characteristic of CMOS Devices A = Assembly Location
• In Compliance with the Requirements Defined by JEDEC Standard WL or L = Wafer Lot
No. 7A YY or Y = Year
WW or W = Work Week
• Chip Complexity: 286 FETs or 71.5 Equivalent Gates

ORDERING INFORMATION
Device Package Shipping
MC74HC165AN PDIP–14 2000 / Box
MC74HC165AD SOIC–14 55 / Rail
MC74HC165ADR2 SOIC–14 2500 / Reel
MC74HC165ADT TSSOP–14 96 / Rail
MC74HC165ADTR2 TSSOP–14 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 157 Publication Order Number:

March, 2000 – Rev. 2 MC74HC165A/D
 MC74HC165A

LOGIC DIAGRAM PIN ASSIGNMENT

11 SERIAL SHIFT/ 1 16 VCC
A PARALLEL LOAD
12
B CLOCK 2 15 CLOCK INHIBIT
13 9 QH
C SERIAL E 3 14 D
PARALLEL DATA
D 14 7 F 4 13 C
DATA QH OUTPUTS
INPUTS E 3
G 5 12 B
F 4
H 6 11 A
G 5
QH 7 10 SA
H 6 PIN 16 = VCC
SERIAL
GND 8 9 QH
DATA SA 10 PIN 8 = GND
INPUT
SERIAL SHIFT/ 1
PARALLEL LOAD
CLOCK 2
15
CLOCK INHIBIT
FUNCTION TABLE
Inputs Internal Stages Output
Serial Shift/ Clock
Parallel Load Clock Inhibit SA A–H QA QB QH Operation
L X X X a…h a b h Asynchronous Parallel Load
H L L X L QAn QGn
Serial Shift via Clock
H L H X H QAn QGn
H L L X L QAn QGn
Serial Shift via Clock Inhibit
H L H X H QAn QGn
H X H X X
No Change Inhibited Clock
H H X X X
H L L X X No Change No Clock
X = don’t care QAn – QGn = Data shifted from the preceding stage

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158
 MC74HC165A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 3.0 V 0 600

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC = 4.5 V 0 500
VCC = 6.0 V 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
v Voltage |Iout| 20 µA 3.0 0.9 0.9 0.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
1.35
1.80
1.35
1.80
1.35
1.80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
v Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 2.48 2.34 2.20 V
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 3.98 3.84 3.70
|Iout| 5.2 mA 6.0 5.48 5.34 5.20

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 MC74HC165A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
vVoltage |Iout| 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.40
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 0.26 0.33 0.40
|Iout| 5.2 mA 6.0 0.26 0.33 0.40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 µA
Current (per Package) Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fmax

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Clock Frequency (50% Duty Cycle)

ÎÎÎ
(Figures 1 and 8)
2.0
3.0
6
18
4.8
17
4
15
MHz

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 30 24 20
6.0 35 28 24

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH

ÎÎÎ
(Figures 1 and 8)
2.0
3.0
4.5
150
52
30
190
63
38
225
65
45
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Propagation Delay, Serial Shift/Parallel Load to QH or
6.0
2.0
26
175
33
220
38
265 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL QH (Figures 2 and 8) 3.0 58 70 72
4.5 35 44 53

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Propagation Delay, Input H to QH or QH
6.0
2.0
30
150
37
190
45
225 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL (Figures 3 and 8) 3.0 52 63 65
4.5 30 38 45

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 26 33 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTHL (Figures 1 and 8) 3.0 27 32 36
4.5 15 19 22

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 13 16 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Cin Maximum Input Capacitance — 10 10 10 pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 40 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC165A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6 ns)

ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VCC – 55 to
v v V 25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Symbol Parameter Unit
tsu Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load 2.0 75 95 110 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
(Figure 4)

ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
3.0
4.5
6.0
30
15
13
40
19
16
55
22
19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tsu

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
(Figure 5) ÎÎÎ
ÎÎÎÎ ÎÎÎ
Minimum Setup Time, Input SA to Clock (or Clock Inhibit)

ÎÎÎ
ÎÎÎ
2.0
3.0
75
30
95
40
110
55
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tsu

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Inhibit) ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock

ÎÎÎ
ÎÎÎ
2.0
3.0
75
30
95
40
110
55
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Figure 6) 4.5 15 19 22
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tsu

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
(Figure 7)
ÎÎÎ
ÎÎÎÎ ÎÎÎ
Minimum Setup Time, Clock to Clock Inhibit

ÎÎÎ
ÎÎÎ
2.0
3.0
4.5
75
30
15
95
40
19
110
55
22
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
th ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs
6.0
2.0
13
5
16
5
19
5 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Figure 4) 3.0 5 5 5
4.5 5 5 5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
6.0 5 5 5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
th Minimum Hold Time, Clock (or Clock Inhibit) to Input SA 2.0 5 5 5 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Figure 5) 3.0 5 5 5
4.5 5 5 5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
6.0 5 5 5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
th Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel 2.0 5 5 5 ns
Load 3.0 5 5 5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
(Figure 6)

ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
4.5
6.0
5
5
5
5
5
5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
trec Minimum Recovery Time, Clock to Clock Inhibit 2.0 75 95 110 ns
(Figure 7) 3.0 30 40 55

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
4.5 15 19 22

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
tw Minimum Pulse Width, Clock (or Clock Inhibit) 2.0 70 90 100 ns
(Figure 1) 3.0 27 32 36

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tw
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
(Figure 2) ÎÎÎ
ÎÎÎÎ ÎÎÎ
Minimum Pulse width, Serial Shift/Parallel Load

ÎÎÎ
ÎÎÎ
2.0
3.0
70
27
90
32
100
36
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
(Figure 1) ÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Input Rise and Fall Times

ÎÎÎ
ÎÎÎ
2.0
3.0
1000
800
1000
800
1000
800
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
4.5 500 500 500
6.0 400 400 400
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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 MC74HC165A

PIN DESCRIPTIONS

INPUTS is applied to this pin, data at the Parallel Data inputs are
A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6) asynchronously loaded into each of the eight internal stages.
Parallel Data inputs. Data on these inputs are Clock, Clock Inhibit (Pins 2, 15)
asynchronously entered in parallel into the internal Clock inputs. These two clock inputs function identically.
flip–flops when the Serial Shift/Parallel Load input is low. Either may be used as an active–high clock inhibit.
SA (Pin 10) However, to avoid double clocking, the inhibit input should
go high only while the clock input is high.
Serial Data input. When the Serial Shift/Parallel Load The shift register is completely static, allowing Clock
input is high, data on this pin is serially entered into the first rates down to DC in a continuous or intermittent mode.
stage of the shift register with the rising edge of the Clock.
OUTPUTS
CONTROL INPUTS
QH, QH (Pins 9, 7)
Serial Shift/Parallel Load (Pin 1)
Complementary Shift Register outputs. These pins are the
Data–entry control input. When a high level is applied to noninverted and inverted outputs of the eighth stage of the
this pin, data at the Serial Data input (SA) are shifted into the shift register.
register with the rising edge of the Clock. When a low level

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 MC74HC165A

SWITCHING WAVEFORMS

tr tf
CLOCK VCC
90%
OR CLOCK INHIBIT 50% tw
10% GND VCC
tw SERIAL SHIFT/ 50% 50%
PARALLEL LOAD GND
1/fmax
tPLH tPHL
tPLH tPHL
90% QH OR QH 50%
QH OR QH 50%
10%
tTLH tTHL

Figure 1. Serial–Shift Mode Figure 2. Parallel–Load Mode

VALID
tr tf VCC
VCC INPUTS A–H 50%
INPUT H 90% GND
50%
10% GND
tsu th
tPLH tPHL
90% VCC
QH OR QH 50% SERIAL SHIFT/
10% PARALLEL LOAD GND
tTLH tTHL ASYNCHRONOUS PARALLEL
LOAD
(LEVEL SENSITIVE)

Figure 3. Parallel–Load Mode Figure 4. Parallel–Load Mode

VALID SERIAL SHIFT/ VCC

VCC 50%
PARALLEL LOAD
INPUT SA 50% GND
GND tsu th
tsu th VCC
CLOCK
CLOCK VCC 50%
OR CLOCK INHIBIT
50% GND
OR CLOCK INHIBIT
GND

Figure 5. Serial–Shift Mode Figure 6. Serial–Shift Mode

TEST POINT

CLOCK 2 INHIBITED OUTPUT

VCC
CLOCK INHIBIT DEVICE
50%
GND UNDER
TEST CL*

tsu trec
VCC
CLOCK 50%
GND *Includes all probe and jig capacitance

Figure 7. Serial–Shift, Clock–Inhibit Mode Figure 8. Test Circuit

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 MC74HC165A

EXPANDED LOGIC DIAGRAM

A B C F G H
11 12 13 4 5 6

SERIAL SHIFT/
1 9 Q
PARALLEL LOAD H

SERIAL DATA 10 D QA D QB D QC D QF D QG D QH 7 Q
H
INPUT SA

C C C C C C C C C C C C

CLOCK 2

CLOCK 15
INHIBIT

TIMING DIAGRAM

CLOCK
CLOCK INHIBIT

SA
SERIAL SHIFT/
PARALLEL LOAD
A H

B L

C H
PARALLEL D L
DATA
INPUTS E H

F L

G H

H H

QH H H L H L H L H
QH L L L L L
H H H
CLOCK
INHIBIT SERIAL–SHIFT MODE
MODE

PARALLEL LOAD

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MC74HC174A

Hex D Flip-Flop with

Common Clock and Reset
High–Performance Silicon–Gate CMOS
The MC74HC174A is identical in pinout to the LS174. The device
inputs are compatible with standard CMOS outputs; with pullup
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resistors, they are compatible with LSTTL outputs.
This device consists of six D flip–flops with common Clock and MARKING
Reset inputs. Each flip–flop is loaded with a low–to–high transition of DIAGRAMS
the Clock input. Reset is asynchronous and active–low. 16

• Output Drive Capability: 10 LSTTL Loads

PDIP–16
N SUFFIX MC74HC174AN
• TTL NMOS Compatible Input Levels 16
CASE 648
AWLYYWW

• Outputs Directly Interface to CMOS, NMOS, and TTL 1

1
• Operating Voltage Range: 4.5 to 5.5 V 16

• Low Input Current: 1.0 µA SO–16

D SUFFIX
HC174A
• In Compliance with the Requirements Defined by JEDEC Standard 16
CASE 751B
AWLYWW
1
No. 7A 1
• Chip Complexity: 162 FETs or 40.5 Equivalent Gates A = Assembly Location
LOGIC DIAGRAM WL = Wafer Lot
YY = Year
D0 3 2 Q0 WW = Work Week
D1 4 5
Q1
PIN ASSIGNMENT
DATA D2 6 7 Q2
NONINVERTING
INPUTS D3 11 10 Q3 OUTPUTS
RESET 1 16 VCC
D4 13 12 Q4
Q0 2 15 Q5
14 15
D5 Q5
D0 3 14 D5

CLOCK 9 D1 4 13 D4
PIN 16 = VCC Q1 5 12 Q4
PIN 8 = GND
D2 6 11 D3
RESET 1
FUNCTION TABLE Q2 7 10 Q3

Inputs Output GND 8 9 CLOCK

Reset Clock D Q
L X X L
H H H
H L L
H L X No Change ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
H X No Change Device Package Shipping

ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ MC74HC174AN PDIP–16 2000 / Box

ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Design Criteria Value Units
MC74HC174AD SOIC–16 48 / Rail

ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Internal Gate Count* 40.5 ea. MC74HC174ADR2 SOIC–16 2500 / Reel

ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Internal Gate Propagation Delay 1.5 ns

ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Internal Gate Power Dissipation 5.0 µW

ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Speed Power Product
*Equivalent to a two–input NAND gate.
.0075 pJ

 Semiconductor Components Industries, LLC, 2000 165 Publication Order Number:

March, 2000 – Rev. 7 MC74HC174A/D
 MC74HC174A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 25 mA cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500
level (e.g., either GND or VCC).
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 Unused outputs must be left open.
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage (Referenced to GND)

ÎÎ
ÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
2.0
0
6.0
VCC
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
Input Rise and Fall Time (Figure 1)

ÎÎÎÎÎ
ÎÎÎ
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
vVoltage |Iout| 20 µA 4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
2.0
4.5
1.9
4.4
1.9
4.4
1.9
4.4
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL
v |Iout| 4.0 mA 4.5 3.98 3.84 3.7
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 5.2 mA 6.0 5.48 5.34 5.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout|
|Iout|
4.0 mA
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4

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166
 MC74HC174A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v 25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V Unit
± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0
µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4.0 40 160
Current (per Package) Iout = 0 µA
NOTES:
1. Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + S∆ICC.

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC – 55 to
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 6.0 4.8 4.0 MHz
(Figures 1 and 4) 4.5 30 24 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 35 28 24

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH Maximum Propagation Delay, Clock to Q 2.0 110 140 165 ns
tPHL (Figures 1 and 4) 4.5 22 28 33

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 19 24 28

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH Maximum Propagation Delay, Reset to Q 2.0 110 140 160 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL (Figures 2 and 4) 4.5 21 28 32
6.0 19 24 27

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Capacitance 10 10
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
10 pF

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)* 62 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
v ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
v
ÎÎÎ
ÎÎÎ
ÎÎÎ
Parameter Fig.
VCC
V
– 55 to 25_C
Min Max Min
85_C
Max Min
125_C
Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
tsu
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Minimum Setup Time, Data to Clock 3 2.0 50 65 75 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
4.5 10 13 15
6.0 9.0 11 13

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
th
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Minimum Hold Time, Clock to Data 3 2.0 5.0 5.0 5.0 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
4.5 5.0 5.0 5.0
6.0 5.0 5.0 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
trec
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Minimum Recovery Time, Reset Inactive to 2 2.0 5.0 5.0 5.0 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Clock 4.5 5.0 5.0 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
6.0 5.0 5.0 5.0
tw Minimum Pulse Width, Clock 1 2.0 75 95 110 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ 4.5 15 19 22

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
tw Minimum Pulse Width, Reset 2 2.0 75 95 110 ns
4.5 15 19 22

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
tr, tf Maximum Input Rise and Fall Times 1 2.0 1000 1000 1000 ns
4.5 500 500 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
6.0 400 400 400

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167
 MC74HC174A

EXPANDED LOGIC DIAGRAM

CLOCK 9 C
Q 2
3 Q0
D0 D
R
RESET 1

C 5 Q1
4 Q
D1 D
R

C 7
6 Q Q2
D2 D
R

C 10
Q Q3
D3 11 D
R

C 12
13 Q Q4
D4 D
R

C 15 Q5
Q
D5 14 D
R

SWITCHING WAVEFORMS

tr tf
VCC tw
90%
CLOCK RESET VCC
50%
50%
10% GND GND
tw
tPHL
1/fmax

tPLH tPHL Q

90% trec
Q 50% VCC
10% 50%
CLOCK GND
tTLH tTHL

Figure 1. Figure 2.

TEST POINT

VALID OUTPUT
VCC DEVICE
DATA 50% UNDER
TEST CL*
GND
tsu th
VCC
CLOCK 50%
*Includes all probe and jig capacitance
GND
Figure 3. Figure 4. Test Circuit

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168
MC74HC175A

Quad D Flip-Flop with

Common Clock and Reset
High–Performance Silicon–Gate CMOS
The MC74HC175A is identical in pinout to the LS175. The device
inputs are compatible with standard CMOS outputs; with pullup
http://onsemi.com
resistors, they are compatible with LSTTL outputs.
This device consists of four D flip–flops with common Reset and MARKING
Clock inputs, and separate D inputs. Reset (active–low) is DIAGRAMS
asynchronous and occurs when a low level is applied to the Reset 16
input. Information at a D input is transferred to the corresponding Q PDIP–16
N SUFFIX MC74HC175AN
output on the next positive going edge of the Clock input. 16 AWLYYWW
CASE 648
• Output Drive Capability: 10 LSTTL Loads 1
1
• Outputs Directly Interface to CMOS, NMOS, and TTL 16
• Operating Voltage Range: 2 to 6 V SO–16
HC175A
• Low Input Current: 1 µA 16
D SUFFIX
CASE 751B
AWLYWW
• High Noise Immunity Characteristic of CMOS Devices 1
1
• In Compliance with the Requirements Defined by JEDEC Standard 16
No. 7A HC
TSSOP–16
• Chip Complexity 166 FETs or 41.5 Equivalent Gates 16 DT SUFFIX 175A
CASE 948F ALYW
1
LOGIC DIAGRAM
1
A = Assembly Location
CLOCK 9 2 Q0 WL = Wafer Lot
3 Q0 YY = Year
7 WW = Work Week
Q1 INVERTING
D0 4 6 Q1 AND
5 10 Q2
D1 NONINVERTING
DATA 11 PIN ASSIGNMENT
Q2 OUTPUTS
INPUTS D2 12 15 Q3 RESET 1 16 VCC
D3 13 14 Q3
Q0 2 15 Q3
RESET 1
Q0 3 14 Q3

PIN 16 = VCC D0 4 13 D3
PIN 8 = GND D1 5 12 D2
Q1 6 11 Q2
FUNCTION TABLE
Q1 7 10 Q2
Inputs Outputs
GND 8 9 CLOCK
Reset Clock D Q Q
L X X L H
H H H L
H L L H
H L X No Change ORDERING INFORMATION
Device Package Shipping
MC74HC175AN PDIP–16 2000 / Box
MC74HC175AD SOIC–16 48 / Rail
MC74HC175ADR2 SOIC–16 2500 / Reel
MC74HC175ADT TSSOP–16 96 / Rail
MC74HC175ADTR2 TSSOP–16 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 169 Publication Order Number:

March, 2000 – Rev. 2 MC74HC175A/D
 MC74HC175A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 3.0 V 0 600

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC = 4.5 V 0 500
VCC = 6.0 V 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 42

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 1.80 1.80 1.80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
v Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ 6.0 5.9 5.9 5.9

v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ Vin = VIH or VIL |Iout| 2.4 mA 3.0 2.48 2.34 2.20
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 3.98 3.84 3.70
|Iout| 5.2 mA 6.0 5.48 5.34 5.20

http://onsemi.com
170
 MC74HC175A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
vVoltage |Iout| 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.40
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 0.26 0.33 0.40
|Iout| 5.2 mA 6.0 0.26 0.33 0.40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 µA
Iout = 0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current (per Package)
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fmax

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Clock Frequency (50% Duty Cycle)

ÎÎÎ
(Figures 1 and 4)
2.0
3.0
6
10
4.8
8.0
4
6
MHz

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 30 24 20
6.0 35 28 24

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Clock to Q or Q

ÎÎÎ
(Figures 1 and 4)
2.0
3.0
150
75
190
90
225
110
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 26 32 38
6.0 22 28 33

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Reset to Q or Q

ÎÎÎ
(Figures 2 and 4)
2.0
3.0
125
70
155
85
190
110
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 22 27 34
6.0 19 24 30

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
(Figures 1 and 4)
2.0
3.0
75
27
95
32
110
36
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
NOTES: ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Capacitance — 10 10 10

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
pF

2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Flip–Flop)* 35 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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171
 MC74HC175A

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6 ns)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tsu Minimum Setup Time, Data to Clock 2.0 100 125 150 ns
(Figure 3) 3.0 45 65 85

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 20 25 30

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 17 21 26

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
th Minimum Hold Time, Clock to Data 2.0 5 5 5 ns
(Figure 3) 3.0 3 3 3

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3 3 3

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 3 3 3

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
trec Minimum Recovery Time, Reset Inactive to Clock 2.0 100 125 150 ns
(Figure 2) 3.0 45 65 85

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 20 25 30

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 17 21 26

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Clock 2.0 80 100 120 ns
(Figure 1) 3.0 45 65 85

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 16 20 24
6.0 14 17 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tw
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(Figure 2)
ÎÎÎÎÎÎÎ
Minimum Pulse Width, Reset

ÎÎÎ
2.0
3.0
80
45
100
65
120
85
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 16 20 24
6.0 14 17 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tr, tf
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
(Figure 1) ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Rise and Fall Times

ÎÎÎ
2.0
3.0
1000
800
1000
800
1000
800
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 500 500 500
6.0 400 400 400
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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172
 MC74HC175A

SWITCHING WAVEFORMS

tw
VCC
50%
RESET
GND
tf tr tPHL
VCC
90%
CLOCK 50% 50%
GND Q
10%
tw tPLH
1/fmax
Q 50%
tPLH tPHL
90% trec
Q or Q 50%
10% VCC
CLOCK
50%
tTLH tTHL
GND

Figure 1. Figure 2.

VALID
VCC
DATA
GND
tsu th
VCC
CLOCK 50%
GND

Figure 3.

TEST CIRCUIT

TEST POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 4.

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173
 MC74HC175A

EXPANDED LOGIC DIAGRAM

D0 4 D Q 2 Q0
C
9 3 Q0
CLOCK C
R

D1 5 D Q 7 Q1
C
6 Q1
C
R

D2 12 D Q 10 Q2
C
11 Q2
C
R

D3 13 D Q 15 Q3
C
14 Q3
C
R
RESET 1

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174
MC74HC240A
Octal 3-State Inverting
Buffer/Line Driver/Line
Receiver
High–Performance Silicon–Gate CMOS
The MC74HC240A is identical in pinout to the LS240. The device
inputs are compatible with standard CMOS outputs; with pullup http://onsemi.com
resistors, they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed MARKING
to be used with 3–state memory address drivers, clock drivers, and DIAGRAMS
other sub–oriented systems. The device has inverting outputs and two 20
active–low output enables. PDIP–20
MC74HC240AN
P SUFFIX
The HC240A is similar in function to the HC244A. AWLYYWW
20 CASE 738
• Output Drive Capability: 15 LSTTL Loads 1 1
• Outputs Directly Interface to CMOS, NMOS, and TTL 20
• Operating Voltage Range: 2 to 6 V
20
SOIC WIDE–20
DW SUFFIX HC240A
• Low Input Current: 1 µA 1 CASE 751D AWLYYWW

• High Noise Immunity Characteristic of CMOS Devices 1

20
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A TSSOP–20 HC
20 240A
• Chip Complexity: 120 FETs or 30 Equivalent Gates 1
DT SUFFIX
CASE 948G ALYW
LOGIC DIAGRAM
1
2 18
A1 YA1 A = Assembly Location
WL = Wafer Lot
4 16 YY = Year
A2 YA2
WW = Work Week
6 14
A3 YA3
PIN ASSIGNMENT
8 12
A4 YA4 ENABLE A 1 20 VCC
DATA INVERTING
INPUTS OUTPUTS A1 2 19 ENABLE B
11 9
B1 YB1
YB4 3 18 YA1
13 7 A2 4 17 B4
B2 YB2
YB3 5 16 YA2
15 5
B3 YB3 A3 6 15 B3
YB2 7 14 YA3
17 3
B4 YB4
A4 8 13 B2
YB1 9 12 YA4
PIN 20 = VCC GND 10 11 B1
1
OUTPUT ENABLE A PIN 10 = GND
ENABLES 19
ENABLE B
FUNCTION TABLE ORDERING INFORMATION
Inputs Outputs Device Package Shipping
Enable A,
MC74HC240AN PDIP–20 1440 / Box
Enable B A, B YA, YB
MC74HC240ADW SOIC–WIDE 38 / Rail
L L H
L H L MC74HC240ADWR2 SOIC–WIDE 1000 / Reel
H X Z
MC74HC240ADT TSSOP–20 75 / Rail
Z = high impedance
MC74HC240ADTR2 TSSOP–20 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 175 Publication Order Number:

March, 2000 – Rev. 8 MC74HC240A/D
 MC74HC240A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC – 55 to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIH ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Parameter

ÎÎÎ
Minimum High–Level Input
Test Conditions
Vout = VCC – 0.1 V
20 µA
V
2.0
25_C
1.5
85_C
1.5
125_C
1.5
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V 2.0 0.5 0.5 0.5 V
v Voltage |Iout| 20 µA 3.0 0.9 0.9 0.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
1.35
1.8
1.35
1.8
1.35
1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH 2.0 1.9 1.9 1.9 V
v Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH |Iout| 2.4 mA 3.0 2.48 2.34 2.2
|Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Low–Level Output Vin = VIL
20 µA
|Iout| 7.8 mA 6.0
2.0
5.48
0.1
5.34
0.1
5.2
0.1 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL |Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4

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176
 MC74HC240A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Leakage Current Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 4.0 40

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
160 µA

(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v 25_C 85_C 125_C

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, A to YA or B to YB 2.0 80 100 120 ns
tPHL (Figures 1 and 3) 3.0 40 50 60

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 16 20 24

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 14 17 20

ÎÎÎÎÎ
tPLZ,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Propagation Delay, Output Enable to YA or YB

ÎÎÎÎ
2.0

ÎÎÎÎ
110

ÎÎÎ
140

ÎÎÎÎ
165

ÎÎÎ
ns
tPHZ (Figures 2 and 4) 3.0 60 70 80

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 22 28 33
6.0 19 24 28

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZL,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZH ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Output Enable to YA or YB

ÎÎÎ
(Figures 2 and 4)
2.0
3.0
110
60
140
70
165
80
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 22 28 33
6.0 19 24 28

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
(Figures 1 and 3)
2.0
3.0
60
23
75
27
90
32
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 12 15 18
6.0 10 13 15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Capacitance — 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cout

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Three–State Output Capacitance (Output in

ÎÎÎ
High–Impedance State)
— 15 15 15

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
pF

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Transceiver Channel)* 32 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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177
 MC74HC240A

SWITCHING WAVEFORMS

VCC
tr tf ENABLE 50%
DATA INPUT VCC GND
90% tPZL tPLZ
A OR B 50% HIGH
10% GND
50% IMPEDANCE
tPHL tPLH OUTPUT Y
90% 10% VOL
50% tPZH tPHZ
OUTPUT 90% VOH
10%
YA OR YB OUTPUT Y 50%
HIGH
tTHL tTLH
IMPEDANCE

Figure 1. Figure 2.

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 3. Test Circuit Figure 4. Test Circuit

PIN DESCRIPTIONS

INPUTS function as inverters. When a high level is applied, the

outputs assume the high–impedance state.
A1, A2, A3, A4, B1, B2, B3, B4
(Pins 2, 4, 6, 8, 11, 13, 15, 17) OUTPUTS
Data input pins. Data on these pins appear in inverted form
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
on the corresponding Y outputs, when the outputs are (Pins 18, 16, 14, 12, 9, 7, 5, 3)
enabled.
Device outputs. Depending upon the state of the
CONTROLS output–enable pins, these outputs are either inverting
outputs or high–impedance outputs.
Enable A, Enable B (Pins 1, 19)
Output enables (active–low). When a low level is applied
to these pins, the outputs are enabled and the devices

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178
 MC74HC240A

LOGIC DETAIL

TO THREE OTHER
A OR B INVERTERS

ONE OF 8
INVERTERS

VCC
DATA
INPUT
A OR B
YA
OR
YB

ENABLE A
OR ENABLE B

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179
MC74HC244A
Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver
High–Performance Silicon–Gate CMOS
The MC74HC244A is identical in pinout to the LS244. The device
inputs are compatible with standard CMOS outputs; with pullup http://onsemi.com
resistors, they are compatible with LSTTL outputs. MARKING
This octal noninverting buffer/line driver/line receiver is designed DIAGRAMS
to be used with 3–state memory address drivers, clock drivers, and 20
other bus–oriented systems. The device has noninverting outputs and PDIP–20
MC74HC244AN
two active–low output enables. P SUFFIX
AWLYYWW
The HC244A is similar in function to the HC240A. 20 CASE 738
1
• Output Drive Capability: 15 LSTTL Loads 1
20
• Outputs Directly Interface to CMOS, NMOS, and TTL SOIC WIDE–20
• Operating Voltage Range: 2 to 6 V 20
1
DW SUFFIX HC244A
AWLYYWW
CASE 751D
• Low Input Current: 1 µA
1
• High Noise Immunity Characteristic of CMOS Devices 20
• In Compliance with the Requirements Defined by JEDEC Standard TSSOP–20 HC
No. 7A 20 DT SUFFIX 244A
• Chip Complexity: 136 FETs or 34 Equivalent Gates 1 CASE 948G ALYW

1
LOGIC DIAGRAM
A = Assembly Location
2 18 WL = Wafer Lot
A1 YA1
YY = Year
4 16 WW = Work Week
A2 YA2
PIN ASSIGNMENT
6 14
A3 YA3
ENABLE A 1 20 VCC
8 12
A4 YA4 A1 2 19 ENABLE B
DATA NONINVERTING
YB4 3 18 YA1
INPUTS 11 9 OUTPUTS
B1 YB1 A2 4 17 B4
13 7 YB3 5 16 YA2
B2 YB2
A3 6 15 B3
15 5 YB2 7 14 YA3
B3 YB3
A4 8 13 B2
17 3
B4 YB4
YB1 9 12 YA4
GND 10 11 B1

1 PIN 20 = VCC
OUTPUT ENABLE A PIN 10 = GND
ENABLES 19
ENABLE B
ORDERING INFORMATION
FUNCTION TABLE
Device Package Shipping
Inputs Outputs
Enable A, MC74HC244AN PDIP–20 1440 / Box
Enable B A, B YA, YB MC74HC244ADW SOIC–WIDE 38 / Rail
L L L MC74HC244ADWR2 SOIC–WIDE 1000 / Reel
L H H
H X Z MC74HC244ADT TSSOP–20 75 / Rail
Z = high impedance MC74HC244ADTR2 TSSOP–20 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 180 Publication Order Number:

March, 2000 – Rev. 8 MC74HC244A/D
 MC74HC244A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC, SSOP or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC – 55 to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIH ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Parameter

ÎÎÎ
Minimum High–Level Input
Test Conditions
Vout = VCC – 0.1 V
20 µA
V
2.0
25_C
1.5
85_C
1.5
125_C
1.5
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V 2.0 0.5 0.5 0.5 V
v Voltage |Iout| 20 µA 3.0 0.9 0.9 0.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
1.35
1.8
1.35
1.8
1.35
1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH 2.0 1.9 1.9 1.9 V
v Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH |Iout| 2.4 mA 3.0 2.48 2.34 2.2
|Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Low–Level Output Vin = VIL
20 µA
|Iout| 7.8 mA 6.0
2.0
5.48
0.1
5.34
0.1
5.2
0.1 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL |Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4

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181
 MC74HC244A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Leakage Current Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Quiescent Supply

ÎÎÎÎ
ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 4.0 40 160

NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the ON
µA

Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VCC – 55 to
v v 25_C 85_C 125_C

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter V Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
tPLH, Maximum Propagation Delay, A to YA or B to YB 2.0 96 115 135 ns
tPHL (Figures 1 and 3) 3.0 50 60 70

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5 18 23 27

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
6.0 15 20 23

ÎÎÎÎÎ
tPLZ,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Propagation Delay, Output Enable to YA or YB

ÎÎÎÎ
2.0

ÎÎÎÎ
110

ÎÎÎ
140

ÎÎÎÎ
165

ÎÎÎ
ns
tPHZ (Figures 2 and 4) 3.0 60 70 80

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5 22 28 33
6.0 19 24 28

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZL,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZH ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Propagation Delay, Output Enable to YA or YB

ÎÎÎÎ
ÎÎÎ
(Figures 2 and 4)
2.0
3.0
110
60
140
70
165
80
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5 22 28 33
6.0 19 24 28

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎÎ
ÎÎÎ
(Figures 1 and 3)
2.0
3.0
60
23
75
27
90
32
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5 12 15 18
6.0 10 13 15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Input Capacitance — 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cout

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Three–State Output Capacitance (Output in

ÎÎÎÎ
ÎÎÎ
High–Impedance State)
— 15 15 15

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
pF

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Buffer)* 34 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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182
 MC74HC244A

SWITCHING WAVEFORMS

tr tf VCC
DATA INPUT VCC ENABLE 50%
90%
A OR B 50% A OR B GND
10% GND tPZL tPLZ
tPLH tPHL HIGH
OUTPUT 90% 50% IMPEDANCE
50% OUTPUT Y
YA OR YB 10% VOL
10% tPZH tPHZ
tTLH tTHL 90% VOH
OUTPUT Y 50%
HIGH
IMPEDANCE

Figure 1. Figure 2.

TEST CIRCUITS

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 3. Test Circuit Figure 4. Test Circuit

PIN DESCRIPTIONS

INPUTS function as noninverting buffers. When a high level is

applied, the outputs assume the high impedance state.
A1, A2, A3, A4, B1, B2, B3, B4
(Pins 2, 4, 6, 8, 11, 13, 15, 17) OUTPUTS
Data input pins. Data on these pins appear in noninverted
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
form on the corresponding Y outputs, when the outputs are
(Pins 18, 16, 14, 12, 9, 7, 5, 3)
enabled.
Device outputs. Depending upon the state of the
CONTROLS output–enable pins, these outputs are either noninverting
Enable A, Enable B (Pins 1, 19) outputs or high–impedance outputs.
Output enables (active–low). When a low level is applied
to these pins, the outputs are enabled and the devices

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183
 MC74HC244A

LOGIC DETAIL

TO THREE OTHER
A OR B INVERTERS

ONE OF 8
INVERTERS

VCC
DATA
INPUT
A OR B
YA
OR
YB

ENABLE A OR
ENABLE B

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184
MC74HCT244A
Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS http://onsemi.com
The MC74HCT244A is identical in pinout to the LS244. This
device may be used as a level converter for interfacing TTL or NMOS MARKING
outputs to High–Speed CMOS inputs. The HCT244A is an octal DIAGRAMS
noninverting buffer line driver line receiver designed to be used with 20
3–state memory address drivers, clock drivers, and other bus–oriented PDIP–20
MC74HCT244AN
P SUFFIX
systems. The device has non–inverted outputs and two active–low CASE 738
AWLYYWW
20
output enables.
1 1
The HCT244A is the noninverting version of the HCT240. See also 20
HCT241. SOIC WIDE–20
• 20 DW SUFFIX HCT244A
Output Drive Capability: 15 LSTTL Loads 1 AWLYYWW
CASE 751D
• TTL NMOS–Compatible Input Levels
1
• Outputs Directly Interface to CMOS, NMOS, and TTL 20

• Operating Voltage Range: 4.5 to 5.5 V TSSOP–20 HCT

• Low Input Current: 1 µA 20 DT SUFFIX 244A
ALYW
1
•
CASE 948G
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A 1

•
A = Assembly Location
Chip Complexity: 112 FETs or 28 Equivalent Gates WL = Wafer Lot
LOGIC DIAGRAM YY = Year
WW = Work Week
2 18
A1 YA1
PIN ASSIGNMENT
4 16
A2 YA2 ENABLE A 1 20 VCC
6 14 A1 2 19 ENABLE B
A3 YA3
YB4 3 18 YA1
8 12
A4 YA4 A2 4 17 B4
DATA INPUTS NONINVERTING
11 9 OUTPUTS YB3 5 16 YA2
B1 YB1
A3 6 15 B3
13 7
B2 YB2 YB2 7 14 YA3

15 5 A4 8 13 B2
B3 YB3
YB1 9 12 YA4
17 3 GND 10 11 B1
B4 YB4

1 PIN 20 = VCC
OUTPUT ENABLE A
ENABLES ENABLE B 19 PIN 10 = GND
ORDERING INFORMATION
FUNCTION TABLE
Device Package Shipping
Inputs Outputs
Enable A, MC74HCT244AN PDIP–20 1440 / Box
Enable B A, B YA, YB MC74HCT244ADW SOIC–WIDE 38 / Rail
L L L MC74HCT244ADWR2 SOIC–WIDE 1000 / Reel
L H H
H X Z MC74HCT244ADT TSSOP–20 75 / Rail
Z = high impedance, X = don’t care MC74HCT244ADTR2 TSSOP–20 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 185 Publication Order Number:

March, 2000 – Rev. 8 MC74HCT244A/D
 MC74HCT244A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC, SSOP or TSSOP Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
ÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 2 2 2 V
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 20 µA 5.5 2 2 2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 0.8 0.8 0.8 V
v Voltage |Iout| 20 µA 5.5 0.8 0.8 0.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout| 6 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 4.5 0.1 0.1 0.1 V
v Voltage |Iout| 20 µA 5.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout| 6 mA 4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 5.5 ± 0.5 ± 5.0 ± 10 µA
Leakage Current Vin = VIL or VIH

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎICC ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Quiescent Supply
Vout = VCC or GND
Vin = VCC or GND 5.5 4 40 160 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current (per Package) Iout = 0 µA

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186
 MC74HCT244A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
∆ICC ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Additional Quiescent Supply Vin = 2.4 V, Any One Input ≥ –55_C 25_C to 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Current Vin = VCC or GND,
GND Other In
Inputs
uts
lout = 0 µA 5.5 2.9 2.4 mA
NOTES:
1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + Σ∆ICC.

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
– 55 to
v v 25_C

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Symbol Parameter 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, Maximum Propagation Delay, A to YA or B to YB 20 25 30 ns
tPHL (Figures 1 and 3)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Propagation Delay, Output Enable to YA or YB

ÎÎÎÎ
ÎÎÎ
(Figures 2 and 4)
26 33 39 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZL,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZH
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Propagation Delay, Output Enable to YA or YB

ÎÎÎÎ
ÎÎÎ
(Figures 2 and 4)
22 28 33 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 12 15 18 ns
tTHL (Figures 1 and 3)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Maximum Input Capacitance 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Cout
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Three–State Output Capacitance (Output in

ÎÎÎÎ
ÎÎÎ
High–Impedance State)
15 15 15

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
pF

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)* 55 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS

3V
tr tf ENABLE 1.3 V
INPUT 3V A OR B GND
2.7 V tPZL tPLZ
A OR B 1.3 V
0.3 V HIGH
GND
1.3 V IMPEDANCE
tPLH tPHL OUTPUT Y
OUTPUT 90% 10% VOL
1.3 V tPZH tPHZ
YA OR YB 90% VOH
10%
OUTPUT Y 1.3 V
tTLH tTHL HIGH
IMPEDANCE

Figure 1. Figure 2.

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187
 MC74HCT244A

TEST CIRCUITS

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 3. Figure 4.

LOGIC DETAIL

TO THREE OTHER
A OR B INVERTERS

ONE OF 8
BUFFERS

VCC
DATA INPUT
A OR B

YA
OR
YB

ENABLE A OR ENABLE B

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188
MC74HC245A

Octal 3-State Noninverting

Bus Transceiver
High–Performance Silicon–Gate CMOS
The MC74HC245A is identical in pinout to the LS245. The device
inputs are compatible with standard CMOS outputs; with pullup
http://onsemi.com
resistors, they are compatible with LSTTL outputs.
The HC245A is a 3–state noninverting transceiver that is used for MARKING
2–way asynchronous communication between data buses. The device DIAGRAMS
has an active–low Output Enable pin, which is used to place the I/O 20
ports into high–impedance states. The Direction control determines PDIP–20
MC74HC245AN
whether data flows from A to B or from B to A. P SUFFIX
AWLYYWW
CASE 738
•
20
Output Drive Capability: 15 LSTTL Loads 1
1
• Outputs Directly Interface to CMOS, NMOS, and TTL 20
• Operating Voltage Range: 2 to 6 V SOIC WIDE–20
HC245A
20 DW SUFFIX
• Low Input Current: 1 µA 1 CASE 751D AWLYYWW
• High Noise Immunity Characteristic of CMOS Devices 1
• In Compliance with the Requirements Defined by JEDEC Standard A = Assembly Location
No. 7A WL = Wafer Lot
• Chip Complexity: 308 FETs or 77 Equivalent Gates YY = Year
WW = Work Week

LOGIC DIAGRAM PIN ASSIGNMENT

2 18
A1 B1 DIRECTION 1 20 VCC
3 17
A2 B2
4 16 A1 2 19 OUTPUT ENABLE
A3 B3
A 5 15 B A2 3 18 B1
A4 B4
DATA 6 14 DATA A3 4 17 B2
PORT A5 B5 PORT
7 13 A4 5 16 B3
A6 B6
8 12 A5 6 15 B4
A7 B7
9 11 A6 7 14 B5
A8 B8
A7 8 13 B6
1
DIRECTION
19 A8 9 12 B7
OUTPUT ENABLE
GND 10 11 B8
PIN 10 = GND
PIN 20 = VCC

FUNCTION TABLE
ORDERING INFORMATION
Control Inputs
Device Package Shipping
Output
MC74HC245AN PDIP–20 1440 / Box
Enable Direction Operation
MC74HC245ADW SOIC–WIDE 38 / Rail
L L Data Transmitted from Bus B to Bus A
MC74HC245ADWR2 SOIC–WIDE 1000 / Reel
L H Data Transmitted from Bus A to Bus B
H X Buses Isolated (High–Impedance State)
X = don’t care

 Semiconductor Components Industries, LLC, 2000 189 Publication Order Number:

March, 2000 – Rev. 8 MC74HC245A/D
 MC74HC245A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VI/O DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
± 20 voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin mA
voltages to this high–impedance cir-
± 35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
II/O DC Output Current, per Pin mA cuit. For proper operation, Vin and
± 75 Vout should be constrained to the
ICC DC Supply Current, VCC and GND Pins mA
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
range GND (Vin or Vout) VCC.
PD Power Dissipation in Still Air, Plastic DIP† 750 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
SOIC Package† 500 tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C level (e.g., either GND or VCC).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
(Plastic DIP or SOIC Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
Î ÎÎ
Symbol

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
Max
6.0
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC – 55 to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIH ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Parameter

ÎÎÎ
Minimum High–Level Input
Test Conditions
Vout = VCC – 0.1 V
20 µA
V
2.0
25_C
1.5
85_C
1.5
125_C
1.5
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V 2.0 0.5 0.5 0.5 V
v Voltage |Iout| 20 µA 3.0 0.9 0.9 0.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
1.35
1.8
1.35
1.8
1.35
1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH 2.0 1.9 1.9 1.9 V
v Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH |Iout| 2.4 mA 3.0 2.48 2.34 2.2
v |Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Low–Level Output Vin = VIL
20 µA
|Iout| 7.8 mA 6.0
2.0
5.48
0.1
5.34
0.1
5.2
0.1 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL |Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4

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190
 MC74HC245A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Leakage Current Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 4.0 40 160

NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the ON
µA

Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC – 55 to
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, A to B, B to A 2.0 75 95 110 ns
tPHL (Figures 1 and 3) 3.0 55 70 80

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
15
13
19
16
22
19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLZ, Maximum Propagation Delay, Direction or Output Enable to A or B 2.0 110 140 165 ns
tPHZ (Figures 2 and 4) 3.0 90 110 130

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 22 28 33

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 19 24 28

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPZL, Maximum Propagation Delay, Output Enable to A or B 2.0 110 140 165 ns
tPZH (Figures 2 and 4) 3.0 90 110 130

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 22 28 33

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 19 24 28

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 2.0 60 75 90 ns
tTHL (Figures 1 and 3) 3.0 23 27 32

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 12 15 18

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 10 13 15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Cin Maximum Input Capacitance (Pin 1 or Pin 19) — 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Cout Maximum Three–State I/O Capacitance — 15 15 15 pF
(I/O in High–Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Transceiver Channel)* 40 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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191
 MC74HC245A

SWITCHING WAVEFORMS

VCC
DIRECTION 50%
GND
VCC
tr tf OUTPUT 50%
VCC ENABLE GND
INPUT 90% tPZL tPLZ
A OR B 50% HIGH
10% GND
50% IMPEDANCE
tPLH tPHL A OR B
10% VOL
OUTPUT 90% tPZH tPHZ
B OR A 50% VOH
10% 90%
A OR B 50%
HIGH
tTLH tTHL
IMPEDANCE

Figure 1. Figure 2.

TEST CIRCUITS

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 3. Figure 4.

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192
 MC74HC245A

EXPANDED LOGIC DIAGRAM

2
A1
18
B1

3
A2
17
B2

4
A3
16
B3

5
A4
A
15
DATA B4 B
PORT DATA
6 PORT
A5
14
B5

7
A6
13
B6

8
A7
12
B7

9
A8
11
B8

1
DIRECTION

19
OUTPUT ENABLE

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193
MC74HCT245A
Octal 3-State Noninverting
Bus Transceiver with LSTTL
Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT245A is identical in pinout to the LS245. This
device may be used as a level converter for interfacing TTL or NMOS
http://onsemi.com
outputs to High Speed CMOS inputs.
The MC74HCT245A is a 3–state noninverting transceiver that is MARKING
used for 2–way asynchronous communication between data buses. DIAGRAMS
The device has an active–low Output Enable pin, which is used to 20
place the I/O ports into high–impedance states. The Direction control PDIP–20
MC74HCT245AN
determines whether data flows from A to B or from B to A. P SUFFIX
AWLYYWW
• Output Drive Capability: 15 LSTTL Loads 20 CASE 738
1
• TTL/NMOS Compatible Input Levels 1
20
• Outputs Directly Interface to CMOS, NMOS and TTL SOIC WIDE–20
• Operating Voltage Range: 4.5 to 5.5 V 20
1
DW SUFFIX HCT245A
AWLYYWW
CASE 751D
• Low Input Current: 1.0 µA
1
• In Compliance with the Requirements Defined by JEDEC Standard 20
No. 7A TSSOP–20 HCT
• Chip Complexity: 304 FETs or 76 Equivalent Gates 20 DT SUFFIX 245A
1 CASE 948G ALYW
LOGIC DIAGRAM
2 18 1
A1 B1
3 17 A = Assembly Location
A2 B2
WL = Wafer Lot
4 16
A3 B3 YY = Year
A 5 15 B WW = Work Week
A4 B4
DATA 6 14 DATA
PORT A5 B5 PORT
7 13 PIN ASSIGNMENT
A6 B6
8 12
A7 B7 DIRECTION 1 20 VCC
9 11
A8 B8 A1 2 19 OUTPUT ENABLE

1 A2 3 18 B1
DIRECTION PIN 20 = VCC
19 A3 4 17 B2

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
OUTPUT ENABLE PIN 10 = GND
A4 5 16 B3

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Design Criteria Value Units
A5 6 15 B4

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Internal Gate Count*

ÎÎÎ
ÎÎÎ
Internal Gate Propagation Delay
76

1.0
ea

ns
A6
A7
7
8
14
13
B5
B6

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Internal Gate Power Dissipation 5.0 µW A8 9 12 B7

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Speed Power Product
*Equivalent to a two–input NAND gate.
0.005 pJ GND 10 11 B8

FUNCTION TABLE
ORDERING INFORMATION
Control Inputs
Output Device Package Shipping
Enable Direction Operation MC74HCT245AN PDIP–20 1440 / Box
L L Data Transmitted from Bus B to Bus A MC74HCT245ADW SOIC–WIDE 38 / Rail
L H Data Transmitted from Bus A to Bus B MC74HCT245ADWR2 SOIC–WIDE 1000 / Reel

H X Buses Isolated (High–Impedance State) MC74HCT245ADT TSSOP–20 75 / Rail

X = Don’t Care MC74HCT245ADTR2 TSSOP–20 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 194 Publication Order Number:

March, 2000 – Rev. 8 MC74HCT245A/D
 MC74HCT245A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC, SSOP or TSSOP Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
Î ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 0.8 0.8 0.8 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 5.5 0.8 0.8 0.8
VOH Minimum High–Level Output Vin = VIH or VIL 4.5 4.4 4.4 4.4 V
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
Voltage

ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
|Iout| 20 µA
Vin = VIH or VIL
5.5 5.4 5.4 5.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 6.0 mA 4.5 3.98 3.84 3.7
VOL Maximum Low–Level Output Vin = VIH or VIL 4.5 0.1 0.1 0.1 V
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
Voltage

ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
|Iout| 20 µA
Vin = VIH or VIL
5.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 6.0 mA 4.5 0.26 0.33 0.4
Iin Maximum Input Leakage Current Vin = VCC or GND, Pins 1 or 19 5.5 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ICC

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
5.5 4.0 40 160 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 5.5 ± 0.5 ± 5.0 ± 10 µA
Leakage Current Vin = VIL or VIH

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
∆ICC ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Additional Quiescent Supply
Vout = VCC or GND, I/O Pins
Vin = 2.4 V, Any One Input ≥ –55_C 25_C to 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Current Vin = VCC or GND,
GND Other In
Inputs
uts
lout = 0 µA 5.5 2.9 2.4 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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195
 MC74HCT245A

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
– 55 to
v v
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Symbol Parameter 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, Maximum Propagation Delay, A to B or B to A 22 28 33 ns
tPHL (Figures 1 and 3)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Propagation Delay, Direction or Output Enable to A or B

ÎÎÎÎ
ÎÎÎ
(Figures 2 and 4)
30 36 42 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZL,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZH
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Propagation Delay, Output Enable to A or 8

ÎÎÎÎ
ÎÎÎ
(Figures 2 and 4)
30 36 42 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, Maximum Output Transition Time. any Output 12 15 18 ns
tTHL (Figures 1 and 3)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Maximum Input Capacitance (Pin 1 or 19) 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Cout
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
State) ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Three–State I/O Capacitance, (I/O in High–Impedance

ÎÎÎÎ
ÎÎÎ
15 15 15 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)* 97 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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196
 MC74HCT245A

SWITCHING WAVEFORMS

3.0 V
DIRECTION 1.3 V 1.3 V
GND
3.0 V
tr tf OUTPUT 1.3 V
INPUT 3.0 V ENABLE GND
2.7 V
A OR B 1.3 V tPZL tPLZ
0.3 V GND HIGH
tPLH tPHL 1.3 V IMPEDANCE
A OR B
OUTPUT 90% 10% VOL
1.3 V tPZH tPHZ
B OR A VOH
10% 90%
A OR B 1.3 V
tTLH tTHL HIGH
IMPEDANCE
Figure 1. Figure 2.

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 3. Figure 4. Test Circuit

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197
 MC74HCT245A

EXPANDED LOGIC DIAGRAM

2
A1
18
B1

3
A2
17
B2

4
A3
16
B3

5
A4
A
DATA 15
B4
PORT B
6 DATA
A5 PORT
14
B5

7
A6
13
B6

8
A7
12
B7

9
A8
11
B8

1
DIRECTION

19
OUTPUT ENABLE

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198
MC74HC273A

Octal D Flip-Flop with

Common Clock and Reset
High–Performance Silicon–Gate CMOS
The MC74HC273A is identical in pinout to the LS273. The device
inputs are compatible with standard CMOS outputs; with pullup
http://onsemi.com
resistors, they are compatible with LSTTL outputs.
This device consists of eight D flip–flops with common Clock and MARKING
Reset inputs. Each flip–flop is loaded with a low–to–high transition of DIAGRAMS
the Clock input. Reset is asynchronous and active low. 20

• Output Drive Capability: 10 LSTTL Loads

PDIP–20
P SUFFIX
MC74HC273AN
• Outputs Directly Interface to CMOS, NMOS and TTL 20 CASE 738
AWLYYWW

• Operating Voltage Range: 2.0 to 6.0 V 1 1

• Low Input Current: 1.0 µA 20
SOIC WIDE–20
• High Noise Immunity Characteristic of CMOS Devices 20 DW SUFFIX HC273A
• In Compliance with the Requirements Defined by JEDEC Standard 1 CASE 751D AWLYYWW

No. 7A 1
20
• Chip Complexity: 264 FETs or 66 Equivalent Gates
TSSOP–20 HC
LOGIC DIAGRAM 20 273A
DT SUFFIX
2 1 CASE 948G ALYW
3 Q0
D0
4 5 1
D1 Q1
7 6 A = Assembly Location
D2 Q2 WL = Wafer Lot
8 9 YY = Year
DATA D3 Q3 NONINVERTING WW = Work Week
INPUTS 13 12
D4 Q4 OUTPUTS
14
D5 15 PIN ASSIGNMENT
Q5
17
D6 16
18 Q6 RESET 1 20 VCC
D7 19
Q7 Q0 2 19 Q7
11
CLOCK
D0 3 18 D7
PIN 20 = VCC D1 4 17 D6
1 PIN 10 = GND
RESET
Q1 5 16 Q6
FUNCTION TABLE Q2 6 15 Q5
Inputs Output D2 7 14 D5
Reset Clock D Q
D3 8 13 D4
L X X L
H H H Q3 9 12 Q4
H L L GND 10 11 CLOCK
H L X No Change

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
H X No Change

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ORDERING INFORMATION
Design Criteria Value Units

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Device Package Shipping
Internal Gate Count* 66 ea

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
MC74HC273AN PDIP–20 1440 / Box
Internal Gate Propagation Delay 1.5 ns

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
MC74HC273ADW SOIC–WIDE 38 / Rail
Internal Gate Power Dissipation 5.0 µW

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
MC74HC273ADWR2 SOIC–WIDE 1000 / Reel
Speed Power Product .0075 pJ MC74HC273ADT TSSOP–20 75 / Rail
*Equivalent to a two–input NAND gate. MC74HC273ADTR2 TSSOP–20 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 199 Publication Order Number:

March, 2000 – Rev. 8 MC74HC273A/D
 MC74HC273A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC – 55 to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIH ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Parameter

ÎÎÎ
Minimum High–Level Input
Test Conditions
Vout = VCC – 0.1 V
20 µA
V
2.0
25_C
1.5
85_C
1.5
125_C
1.5
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V 2.0 0.5 0.5 0.5 V
v Voltage |Iout| 20 µA 3.0 0.9 0.9 0.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
1.35
1.8
1.35
1.8
1.35
1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH 2.0 1.9 1.9 1.9 V
v Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH |Iout| 2.4 mA 3.0 2.48 2.34 2.2
|Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Low–Level Output Vin = VIL
20 µA
|Iout| 7.8 mA 6.0
2.0
5.48
0.1
5.34
0.1
5.2
0.1 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL |Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4

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200
 MC74HC273A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Leakage Current Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 4.0 40

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
160 µA

(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v 25_C 85_C 125_C

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 6.0 5.0 4.0 MHz
(Figures 1 and 4) 3.0 15 10 8.0

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 30 24 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 35 28 24

ÎÎÎÎÎ
tPLH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Propagation Delay, Clock to Q

ÎÎÎÎ
2.0

ÎÎÎÎ
145

ÎÎÎ
180

ÎÎÎÎ
220

ÎÎÎ
ns
tPHL (Figures 1 and 4) 3.0 90 120 140

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 29 36 44
6.0 25 31 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Reset to Q

ÎÎÎ
(Figures 2 and 4)
2.0
3.0
145
90
180
120
220
140
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 29 36 44
6.0 25 31 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
(Figures 1 and 4)
2.0
3.0
75
27
95
32
110
36
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Capacitance 10 10 10
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
pF

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)* 48 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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201
 MC74HC273A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
v v ÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎ
– 55 to 25_C 85_C 125_C
VCC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Fig. Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tsu Minimum Setup Time, Data to Clock 3 2.0 60 75 90 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
3.0 23 27 32
4.5 12 15 18

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
6.0 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
th Minimum Hold Time, Clock to Data 3 2.0 3.0 3.0 3.0 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
3.0 3.0 3.0 3.0
4.5 3.0 3.0 3.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
6.0 3.0 3.0 3.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
trec Minimum Recovery Time, Reset Inactive to 2 2.0 5.0 5.0 5.0 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Clock 3.0 5.0 5.0 5.0
4.5 5.0 5.0 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
6.0 5.0 5.0 5.0

ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Clock 1 2.0 60 75 90 ns
3.0 23 27 32

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎ
4.5 12 15 18

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
6.0 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Reset 2 2.0 60 75 90 ns
3.0 23 27 32

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎ
4.5 12 15 18

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
6.0 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf Maximum Input Rise and Fall Times 1 2.0 1000 1000 1000 ns
3.0 800 800 800

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
4.5 500 500 500
6.0 400 400 400

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202
 MC74HC273A

SWITCHING WAVEFORMS

tr tf tw
VCC VCC
90% RESET 50%
CLOCK 50%
10% GND GND
tw tPHL

1/fmax 50%
Q
tPLH tPHL
90% trec
Q 50% VCC
10% CLOCK 50%
tTLH tTHL GND

Figure 1. Figure 2.

VALID
VCC
DATA 50%
GND
tsu th
VCC
CLOCK 50% EXPANDED LOGIC DIAGRAM
GND

Figure 3. C 2
3 Q Q0
D0 DR

C 5
4 Q Q1
D1 DR

C 6
7 Q Q2
TEST POINT D2 DR

C 9
OUTPUT 8 Q Q3
D3 DR NONINVERTING
DEVICE DATA
UNDER OUTPUTS
CL* INPUTS C
TEST 12
13 Q Q4
D4 DR

C 15
14 Q Q5
D5 DR
*Includes all probe and jig capacitance

Figure 4. Test Circuit C 16

17 Q Q6
D6 DR

C 19
18 Q Q7
D7 DR

11

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MC74HCT273A

Octal D Flip-Flop with

Common Clock and Reset
with LSTTL-Compatible
Inputs
High–Performance Silicon–Gate CMOS http://onsemi.com

The MC74HCT273A may be used as a level converter for MARKING

interfacing TTL or NMOS outputs to High–Speed CMOS inputs. DIAGRAMS
20
The HCT273A is identical in pinout to the LS273.
PDIP–20
This device consists of eight D flip–flops with common Clock and MC74HCT273AN
P SUFFIX
Reset inputs. Each flip–flop is loaded with a low–to–high transition of AWLYYWW
20 CASE 738
the Clock input. Reset is asynchronous and active low. 1
1
• Output Drive Capability: 10 LSTTL Loads 20
• TTL/NMOS Compatible Input Levels 20
SOIC WIDE–20
DW SUFFIX HCT273A
• Outputs Directly Interface to CMOS, NMOS and TTL 1 CASE 751D AWLYYWW

• Operating Voltage Range: 4.5 to 5.5 V 1

• Low Input Current: 1.0 µA A = Assembly Location
• In Compliance with the Requirements Defined by JEDEC Standard WL = Wafer Lot
YY = Year
No. 7A WW = Work Week
• Chip Complexity: 284 FETs or 71 Equivalent Gates
LOGIC DIAGRAM PIN ASSIGNMENT

3 2 RESET 1 20 VCC
D0 Q0
4 5 Q0 2 19 Q7
D1 Q1
7 6 D0 3 18 D7
D2 Q2
8 9 D1 4 17 D6
DATA D3 Q3 NONINVERTING
INPUTS 13 12 Q1 5 16 Q6
D4 Q4 OUTPUTS
14 Q2 6 15 Q5
D5 15
Q5 D2 7 14 D5
17
D6 16
18 Q6 D3 8 13 D4
D7 19
11 Q7 Q3 9 12 Q4
CLOCK
GND 10 11 CLOCK

PIN 20 = VCC
1 PIN 10 = GND
RESET
FUNCTION TABLE ORDERING INFORMATION
Inputs Output Device Package Shipping
Reset Clock D Q MC74HCT273AN PDIP–20 1440 / Box
L X X L MC74HCT273ADW SOIC–WIDE 38 / Rail
H H H
H L L MC74HCT273ADWR2 SOIC–WIDE 1000 / Reel
H L X No Change
H X No Change

X = Don’t Care
Z = High Impedance

 Semiconductor Components Industries, LLC, 2000 204 Publication Order Number:

March, 2000 – Rev. 8 MC74HCT273A/D
 MC74HCT273A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C Unused outputs must be left open.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
(SOIC or Plastic DIP) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎ
ÎÎÎÎÎÎ
DC Supply Voltage (Referenced to GND)

ÎÎ
ÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
4.5
0
5.5
VCC
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎ
ÎÎ
ÎÎÎ
Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎ
ÎÎÎ
Input Rise and Fall Time (Figure 1) 0 500 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 2.0 2.0 2.0 V
v Voltage |Iout| 20 µA 5.5 2.0 2.0 2.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL
v |Iout| 4.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout| 4.0 mA 4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current
µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 5.5 4.0 40 160
Current (per Package) Iout = 0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
∆ICC

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Current ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Additional Quiescent Supply

ÎÎÎ
Vin = 2.4 V, Any One Input
Vin = VCC or GND,
GND Other In
Inputs
uts
≥ –55_C 25_C to 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
lout = 0 µA 5.5 2.9 2.4 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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205
 MC74HCT273A

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
– 55 to
v v
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Fig. 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
fmax Maximum Clock Frequency (50% Duty Cycle) 1, 4 30 24 20 MHz

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Clock to Q 1, 4 25 28 35 ns
tPHL

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Reset to Q 2, 4 25 28 35 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
1, 5 18 20

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
22 ns

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Gate)* 30 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
v ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
Î ÎÎÎ
ÎÎ
ÎÎÎ
– 55 to 25_C 85_C 125_C
Symbol

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tsu
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
Parameter

ÎÎÎ
Minimum Setup Time, Data to Clock
Fig.
3
Min
10
Max Min
12
Max Min
15
Max Unit
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
th
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎ
Î ÎÎÎ
Minimum Hold Time, Clock to Data

ÎÎ
ÎÎÎ
3 3.0 3.0 3.0 ns
trec

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
Minimum Recovery Time, Set or Reset Inactive to Clock

ÎÎ
Î ÎÎ
ÎÎÎÎÎÎ
Minimum Pulse Width, Clock
2
1
5.0
12
5.0
15
5.0
18
ns
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
Minimum Pulse Width, Set or Reset 2 12 15 18 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
Maximum Input Rise and Fall Times 1 500 500 500 ns

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206
 MC74HCT273A

SWITCHING WAVEFORMS

tr tf tw
3.0 V 3.0 V
2.7 V RESET 1.3 V
CLOCK 1.3 V
0.3 V GND GND
tw tPHL

1/fmax 1.3 V
Q
tPLH tPHL
90% trec
Q 1.3 V 3.0 V
10% CLOCK 1.3 V
tTLH tTHL GND

Figure 1. Figure 2.

TEST POINT

VALID OUTPUT
3.0 V DEVICE
DATA 1.3 V UNDER
GND TEST CL*
tsu th
3.0 V
1.3 V
CLOCK GND
*Includes all probe and jig capacitance
Figure 3. Figure 4. Test Circuit

EXPANDED LOGIC DIAGRAM

C 2
3 Q Q0
D0 DR

C 5
4 Q Q1
D1 DR

C 6
7 Q Q2
D2 DR

C 9
8 Q Q3
D3 DR NONINVERTING
DATA
OUTPUTS
INPUTS C 12
13 Q Q4
D4 DR

C 15
14 Q Q5
D5 DR

C 16
17 Q Q6
D6 DR

C 19
18 Q Q7
D7 DR

11
CLOCK

1
RESET

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MC74HC373A

Octal 3-State Non-Inverting

Transparent Latch
High–Performance Silicon–Gate CMOS
The MC74HC373A is identical in pinout to the LS373. The device
inputs are compatible with standard CMOS outputs; with pullup
http://onsemi.com
resistors, they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change MARKING
asynchronously) when Latch Enable is high. When Latch Enable goes DIAGRAMS
low, data meeting the setup and hold time becomes latched. 20
The Output Enable input does not affect the state of the latches, but PDIP–20
MC74HC373AN
when Output Enable is high, all device outputs are forced to the P SUFFIX
AWLYYWW
CASE 738
high–impedance state. Thus, data may be latched even when the 20
1
outputs are not enabled. 1
20
The HC373A is identical in function to the HC573A which has the
SOIC WIDE–20
data inputs on the opposite side of the package from the outputs to 20 DW SUFFIX HC373A
facilitate PC board layout. 1 CASE 751D AWLYYWW
The HC373A is the non–inverting version of the HC533A. 1
20
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL 20
TSSOP–20 HC
373A
DT SUFFIX
• Operating Voltage Range: 2.0 to 6.0 V 1 CASE 948G ALYW
• Low Input Current: 1.0 µA 1
• High Noise Immunity Characteristic of CMOS Devices A = Assembly Location
• In Compliance with the Requirements Defined by JEDEC Standard WL = Wafer Lot
No. 7A YY = Year
WW = Work Week
• Chip Complexity: 186 FETs or 46.5 Equivalent Gates

ORDERING INFORMATION
Device Package Shipping
MC74HC373AN PDIP–20 1440 / Box
MC74HC373ADW SOIC–WIDE 38 / Rail
MC74HC373ADWR2 SOIC–WIDE 1000 / Reel
MC74HC373ADT TSSOP–20 75 / Rail
MC74HC373ADTR2 TSSOP–20 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 208 Publication Order Number:

March, 2000 – Rev. 8 MC74HC373A/D
 MC74HC373A

PIN ASSIGNMENT
OUTPUT 1 20 VCC
ENABLE
Q0 2 19 Q7
LOGIC DIAGRAM
D0 3 18 D7
3 2 D1 4 17 D6
D0 Q0
4 5 Q1 5 16 Q6
D1 Q1
7 6 Q2 6 15 Q5
D2 Q2
D2 7 14 D5
DATA 8 9
D3 Q3 NONINVERTING
INPUTS D3 8 13 D4
13 12 OUTPUTS
D4 Q4 Q3 9 12 Q4
14 15 LATCH
D5 Q5 GND 10 11
ENABLE
17 16
D6 Q6
18 19 FUNCTION TABLE
D7 Q7
Inputs Output
Output Latch
11 PIN 20 = VCC Enable Enable D Q
LATCH ENABLE
1 PIN 10 = GND
OUTPUT ENABLE L H H H
L H L L
L L X No Change
H X X Z
X = Don’t Care

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Z = High Impedance

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Design Criteria

ÎÎÎÎ
ÎÎÎ
Internal Gate Count*
Value
46.5
Units
ea

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Internal Gate Propagation Delay

ÎÎÎÎ
ÎÎÎ
Internal Gate Power Dissipation
1.5
5.0
ns
µW

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Speed Power Product 0.0075 pJ
*Equivalent to a two–input NAND gate.

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209
 MC74HC373A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC, SSOP or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC – 55 to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIH ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Parameter

ÎÎÎ
Minimum High–Level Input
Test Conditions
Vout = VCC – 0.1 V
20 µA
V
2.0
25_C
1.5
85_C
1.5
125_C
1.5
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V 2.0 0.5 0.5 0.5 V
v Voltage |Iout| 20 µA 3.0 0.9 0.9 0.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
1.35
1.8
1.35
1.8
1.35
1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH 2.0 1.9 1.9 1.9 V
v Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH |Iout| 2.4 mA 3.0 2.48 2.34 2.2
|Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Low–Level Output Vin = VIL
20 µA
|Iout| 7.8 mA 6.0
2.0
5.48
0.1
5.34
0.1
5.2
0.1 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL |Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4

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 MC74HC373A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Leakage Current Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 4.0 40

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
160 µA

(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v 25_C 85_C 125_C

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH Maximum Propagation Delay, Input D to Q 2.0 125 155 190 ns
tPHL (Figures 1 and 5) 3.0 80 110 130

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 25 31 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 21 26 32

ÎÎÎÎÎ
tPLH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Propagation Delay, Latch Enable to Q

ÎÎÎÎ
2.0

ÎÎÎÎ
140

ÎÎÎ
175

ÎÎÎÎ
210

ÎÎÎ
ns
tPHL (Figures 2 and 5) 3.0 90 120 140

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 28 35 42
6.0 24 30 36

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Output Enable to Q

ÎÎÎ
(Figures 3 and 6)
2.0
3.0
150
100
190
125
225
150
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 30 38 45
6.0 26 33 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZL

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZH ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Output Enable to Q

ÎÎÎ
(Figures 3 and 6)
2.0
3.0
150
100
190
125
225
150
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 30 38 45
6.0 26 33 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
(Figures 1 and 5)
2.0
3.0
60
23
75
27
90
32
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 12 15 18
6.0 10 13 15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Capacitance 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cout

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Three–State Output Capacitance

ÎÎÎ
(Output in High–Impedance State)
15 15 15

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
pF

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)* 36 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

http://onsemi.com
211
 MC74HC373A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
v v ÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎ
– 55 to 25_C 85_C 125_C
VCC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Symbol Parameter Fig. Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
tsu Minimum Setup Time, Input D to Latch Enable 4 2.0 25 30 40 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
3.0 20 25 30
4.5 5.0 6.0 8.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
6.0 5.0 6.0 7.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
th Minimum Hold Time, Latch Enable to Input D 4 2.0 5.0 5.0 5.0 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
3.0 5.0 5.0 5.0
4.5 5.0 50 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
6.0 5.0 5.0 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
tw Minimum Pulse Width, Latch Enable 2 2.0 60 75 90 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
3.0 23 27 32
4.5 12 15 18

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
6.0 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
tr, tf Maximum Input Rise and Fall Times 1 2.0 1000 1000 1000 ns
3.0 800 800 800

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
4.5
6.0
500
400
500
400
500
400

SWITCHING WAVEFORMS

tr tf tw
VCC VCC
90%
INPUT D 50% LATCH ENABLE 50%
10% GND GND
tPLH tPHL tPLH tPHL
90%
Q 50%
10%
Q 50%
tTLH tTHL

Figure 1. Figure 2.

VCC
OUTPUT
50%
ENABLE
GND VALID
tPZL tPLZ VCC
HIGH
INPUT D 50%
IMPEDANCE
Q 50% GND
10% VOL tsu th
tPZH tPHZ VCC
VOH LATCH ENABLE 50%
90%
Q 1.3 V GND
HIGH
IMPEDANCE

Figure 3. Figure 4.

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212
 MC74HC373A

TEST CIRCUITS

TEST POINT
TEST POINT

OUTPUT CONNECT TO VCC WHEN

OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE
DEVICE CONNECT TO GND WHEN
UNDER
CL* UNDER TESTING tPHZ AND tPZH.
TEST CL*
TEST

*Includes all probe and jig capacitance

*Includes all probe and jig capacitance

Figure 5. Figure 6.

EXPANDED LOGIC DIAGRAM

D0 D1 D2 D3 D4 D5 D6 D7
3 4 7 8 13 14 17 18
D Q D Q D Q D Q D Q D Q D Q D Q

LE LE LE LE LE LE LE LE

11

2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

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MC74HCT373A

Octal 3-State Noninverting

Transparent Latch with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT373A may be used as a level converter for http://onsemi.com
interfacing TTL or NMOS outputs to High–Speed CMOS inputs. MARKING
The HCT373A is identical in pinout to the LS373. DIAGRAMS
The eight latches of the HCT373A are transparent D–type latches. 20
While the Latch Enable is high the Q outputs follow the Data Inputs. PDIP–20
When Latch Enable is taken low, data meeting the setup and hold MC74HCT373AN
P SUFFIX
AWLYYWW
times becomes latched. 20 CASE 738
The Output Enable does not affect the state of the latch, but when 1 1
Output Enable is high, all outputs are forced to the high–impedance 20
state. Thus, data may be latched even when the outputs are not SOIC WIDE–20
20 DW SUFFIX HCT373A
enabled. 1 AWLYYWW
CASE 751D
The HCT373A is identical in function to the HCT573A, which has
1
the input pins on the opposite side of the package from the output pins. 20
This device is similar in function to the HCT533A, which has
TSSOP–20 HCT
inverting outputs. 20 373A
DT SUFFIX
• Output Drive Capability: 15 LSTTL Loads 1 CASE 948G ALYW

• TTL/NMOS–Compatible Input Levels 1

• Outputs Directly Interface to CMOS, NMOS, and TTL A = Assembly Location
• Operating Voltage Range: 4.5 to 5.5 V WL = Wafer Lot
YY = Year
• Low Input Current: 1.0 µA WW = Work Week
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A PIN ASSIGNMENT
• Chip Complexity: 196 FETs or 49 Equivalent Gates
ENABLE A 1 20 VCC
A1 2 19 ENABLE B
YB4 3 18 YA1
A2 4 17 B4
YB3 5 16 YA2
A3 6 15 B3
YB2 7 14 YA3
A4 8 13 B2
YB1 9 12 YA4
GND 10 11 B1

ORDERING INFORMATION
Device Package Shipping
MC74HCT373AN PDIP–20 1440 / Box
MC74HCT373ADW SOIC–WIDE 38 / Rail
MC74HCT373ADWR2 SOIC–WIDE 1000 / Reel
MC74HCT373ADT TSSOP–20 75 / Rail
MC74HCT373ADTR2 TSSOP–20 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 214 Publication Order Number:

March, 2000 – Rev. 8 MC74HCT373A/D
 MC74HCT373A

PIN ASSIGNMENT
OUTPUT 1 20 VCC
ENABLE
Q0 2 19 Q7
LOGIC DIAGRAM
D0 3 18 D7
D1 4 17 D6
3 2
D0 Q0 Q1 5 16 Q6
4 5
D1 Q1 Q2 6 15 Q5
7 6
D2 Q2 D2 7 14 D5
DATA 8 9 D3 8 13 D4
D3 Q3 NONINVERTING
INPUTS 13 12
D4 Q4 OUTPUTS Q3 9 12 Q4
14 15 GND 10 11 LATCH
D5 Q5 ENABLE
17 16
D6 Q6
18 19
FUNCTION TABLE
D7 Q7
Inputs Output
Output Latch
11 PIN 20 = VCC Enable Enable D Q
LATCH ENABLE
1 PIN 10 = GND
OUTPUT ENABLE L H H H
L H L L
L L X No Change
H X X Z

X = don’t care

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Z = high impedance

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Design Criteria Value Units

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Internal Gate Count*

ÎÎÎÎ
ÎÎÎ
Internal Gate Propagation Delay
49

1.5
ea.

ns

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Power Dissipation 5.0 µW

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Speed Power Product .0075 pJ

*Equivalent to a two–input NAND gate.

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 MC74HCT373A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC, SSOP or TSSOP Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
ÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 2.0 2.0 2.0 V
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 20 µA 5.5 2.0 2.0 2.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 0.8 0.8 0.8 V
v Voltage |Iout| 20 µA 5.5 0.8 0.8 0.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 4.5 0.1 0.1 0.1 V
v Voltage |Iout| 20 µA 5.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout| 6.0 mA 4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 5.5 ± 0.5 ± 5.0 ± 10 µA
Leakage Current Vin = VIL or VIH

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎICC ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Quiescent Supply
Vout = VCC or GND
Vin = VCC or GND 5.5 4.0 40 160 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current (per Package) Iout = 0 µA

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 MC74HCT373A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
∆ICC ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Additional Quiescent Supply Vin = 2.4 V, Any One Input 5.5 ≥ –55_C 25_C to 125_C mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Current Vin = VCC or GND,
GND Other In
Inputs
uts
lout = 0 µA 2.9 2.4

NOTE: 1. Total Supply Current = ICC + Σ∆ICC.

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ – 55 to
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Symbol Parameter 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, Maximum Propagation Delay, Input D to Q 28 35 42 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL (Figures 1 and 5)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, Maximum Propagation Delay, Latch Enable to Q 32 40 48 ns
tPHL (Figures 2 and 5)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Propagation Delay, Output Enable to Q

ÎÎÎÎ
ÎÎÎ
(Figures 3 and 6)
30 38 45 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPZL, Maximum Propagation Delay, Output Enable to Q 35 44 53 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPZH (Figures 3 and 6)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 12 15 18 ns
tTHL (Figures 1 and 5)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Maximum Input Capacitance 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Cout
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Three–State Output Capacitance

ÎÎÎÎ
ÎÎÎ
(Output in High–Impedance State)
15 15 15

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
pF

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Latch)* 65 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ – 55 to
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Symbol Parameter 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tsu Minimum Setup Time, Input D to Latch Enable 10 13 15 ns
(Figure 4)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
th
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Minimum Hold Time, Latch Enable to Input D

ÎÎÎÎ
(Figure 4)
ÎÎÎ
10 13 15 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tw
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Minimum Pulse Width, Latch Enable

ÎÎÎÎ
(Figure 2)

ÎÎÎ
12 15 18 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tr, tf Maximum Input Rise and Fall Times 500 500 500 ns
(Figure 1)

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 MC74HCT373A

EXPANDED LOGIC DIAGRAM

D0 D1 D2 D3 D4 D5 D6 D7
3 4 7 8 13 14 17 18
D Q D Q D Q D Q D Q D Q D Q D Q

LE LE LE LE LE LE LE LE

LATCH 11
ENABLE

OUTPUT 1
ENABLE
2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

SWITCHING WAVEFORMS

tr tf tw
3V 3V
2.7 V
INPUT D 1.3 V LATCH ENABLE 1.3 V 1.3 V
0.3 V GND GND
tPLH tPHL tPLH tPHL
90%
Q 1.3 V
10%
Q 1.3 V
tTLH tTHL

Figure 1. Figure 2.

3V
OUTPUT
1.3 V
ENABLE
GND VALID
tPZL tPLZ 3V
HIGH
INPUT D 1.3 V
IMPEDANCE
Q 1.3 V GND
10% VOL tsu th
tPZH tPHZ 3V
VOH LATCH ENABLE 1.3 V
90%
Q 1.3 V GND
HIGH
IMPEDANCE

Figure 3. Figure 4.

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 MC74HCT373A

TEST CIRCUITS

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT 1 kΩ
OUTPUT TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
CL* TEST CL*
TEST

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 5. Figure 6.

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MC74HC374A

Octal 3-State Non-Inverting

D Flip-Flop
High–Performance Silicon–Gate CMOS
The MC74HC374A is identical in pinout to the LS374. The device
inputs are compatible with standard CMOS outputs; with pullup
http://onsemi.com
resistors, they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising MARKING
edge of the clock. The Output Enable input does not affect the states of DIAGRAMS
the flip–flops, but when Output Enable is high, the outputs are forced 20
to the high–impedance state; thus, data may be stored even when the PDIP–20
MC74HC374AN
outputs are not enabled. P SUFFIX
AWLYYWW
CASE 738
The HC374A is identical in function to the HC574A which has the 20
1
input pins on the opposite side of the package from the output. This 1
20
device is similar in function to the HC534A which has inverting
SOIC WIDE–20
outputs. 20 DW SUFFIX HC374A
AWLYYWW
• Output Drive Capability: 15 LSTTL Loads
1 CASE 751D

• Outputs Directly Interface to CMOS, NMOS, and TTL 1

20
• Operating Voltage Range: 2.0 to 6.0 V HC
TSSOP–20
• Low Input Current: 1.0 µA 20 DT SUFFIX 374A
• High Noise Immunity Characteristic of CMOS Devices 1 CASE 948G ALYW

• In Compliance with the Requirements Defined by JEDEC Standard 1

No. 7A A = Assembly Location
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates WL = Wafer Lot
YY = Year
LOGIC DIAGRAM WW = Work Week
3 2
D0 Q0 PIN ASSIGNMENT
4 5
D1 Q1 OUTPUT 1 20 VCC
7 6 ENABLE
D2 Q2
Q0 2 19 Q7
8 9
DATA D3 Q3 NONINVERTING D0 3 18 D7
INPUTS 13 12
D4 Q4 OUTPUTS
D1 4 17 D6
14
D5 15
Q5 Q1 5 16 Q6
17
D6 16
Q6 Q2 6 15 Q5
18
D7 19
Q7 D2 7 14 D5
11
CLOCK D3 8 13 D4
Q3 9 12 Q4
PIN 20 = VCC
1 PIN 10 = GND GND 10 11 CLOCK
OUTPUT ENABLE
FUNCTION TABLE
Inputs Output
ORDERING INFORMATION
Output
Enable Clock D Q Device Package Shipping
L H H MC74HC374AN PDIP–20 1440 / Box
L L L
MC74HC374ADW SOIC–WIDE 38 / Rail
L L,H, X No Change
H X X Z MC74HC374ADWR2 SOIC–WIDE 1000 / Reel

X = don’t care MC74HC374ADT TSSOP–20 75 / Rail

Z = high impedance MC74HC374ADTR2 TSSOP–20 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 220 Publication Order Number:

March, 2000 – Rev. 8 MC74HC374A/D
 MC74HC374A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC, SSOP or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIH
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0
3.0
1.50
2.10
1.50
2.10
1.50
2.10
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0
3.0
0.50
0.90
0.50
0.90
0.50
0.90
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
2.0
4.5
6.0
1.90
4.40
5.90
1.90
4.40
5.90
1.90
4.40
5.90
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL |Iout|
|Iout|
2.4 mA
6.0 mA
3.0
4.5
2.48
2.98
2.34
3.84
2.20
3.70 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 7.8 mA 6.0 5.48 5.34 5.20

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221
 MC74HC374A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.10 0.10 0.10 V
vVoltage |Iout| 20 µA 4.5 0.10 0.10 0.10

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.10 0.10 0.10

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.40
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 6.0 mA 4.5 0.26 0.33 0.40 V
|Iout| 7.8 mA 6.0 0.26 0.33 0.40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Leakage Current Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 4 40

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
160 µA

(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC – 55 to
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 6 5 4 MHz
3.0 15 10 8

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
30
35
24
28
20
24

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH Maximum Propagation Delay, Input Clock to Q 2.0 125 155 190 ns
tPHL (Figures 1 and 5) 3.0 80 110 130

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 25 31 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 21 26 32

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLZ Maximum Propagation Delay, Output Enable to Q 2.0 150 190 225 ns
tPHZ (Figures 3 and 6) 3.0 100 125 150

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 30 38 45

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 26 33 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLZ Maximum Propagation Delay, Output Enable to Q 2.0 150 190 225 ns
tPHZ (Figures 3 and 6) 3.0 100 125 150

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 30 38 45

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 26 33 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTLH Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 5) 3.0 27 32 36

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Capacitance 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cout

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Three–State Output Capacitance

ÎÎÎ
(Output in High–Impedance State)
15 15 15 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)* 34 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC374A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
v v ÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎ
– 55 to 25_C 85_C 125_C
VCC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Symbol Parameter Fig. Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
tsu Minimum Setup Time, Data to Clock 3 2.0 50 65 75 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
3.0 40 50 60
4.5 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
6.0 9 11 13

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
th Minimum Hold Time, Clock to Data 3 2.0 5.0 5.0 5.0 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
3.0 5.0 50 5.0
4.5 5.0 5.0 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
6.0 5.0 5.0 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
tw Minimum Pulse Width, Clock 1 2.0 60 75 90 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
3.0 23 27 32
4.5 12 15 18

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
6.0 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
tr, tf Maximum Input Rise and Fall Times 1 2.0 1000 1000 1000 ns
3.0 800 800 800

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
4.5
6.0
500
400
500
400
500
400

SWITCHING WAVEFORMS

tr tf VCC
VCC OUTPUT
90% 50%
ENABLE
50% GND
CLOCK
10% GND tPZL tPLZ
HIGH
tW IMPEDANCE
1/fmax Q 50%
10% VOL
tPLH tPHL
tPZH tPHZ
90%
Q 90% VOH
50% Q
10% 50%
HIGH
tTLH tTHL IMPEDANCE

Figure 1. Figure 2.

VALID
VCC

DATA 50%

GND

tsu th

VCC
CLOCK 50%

GND

Figure 3.

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223
 MC74HC374A

TEST CIRCUITS

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 4. Figure 5.

EXPANDED LOGIC DIAGRAM

D0 D1 D2 D3 D4 D5 D6 D7
3 4 7 8 13 14 17 18
D Q D Q D Q D Q D Q D Q D Q D Q

C C C C C C C C

11
Clock

Output 1
Enable
2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

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MC74HCT374A

Octal 3-State Noninverting

D Flip-Flop with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT374A may be used as a level converter for http://onsemi.com
interfacing TTL or NMOS outputs to High–Speed CMOS inputs. MARKING
The HCT374A is identical in pinout to the LS374. DIAGRAMS
Data meeting the setup and hold time is clocked to the outputs with 20
the rising edge of Clock. The Output Enable does not affect the state of PDIP–20
the flip–flops, but when Output Enable is high, the outputs are forced MC74HCT374AN
P SUFFIX
AWLYYWW
to the high–impedance state. Thus, data may be stored even when the 20 CASE 738
outputs are not enabled. 1 1
The HCT374A is identical in function to the HCT574A, which has 20
the input pins on the opposite side of the package from the output pins. SOIC WIDE–20
20 DW SUFFIX HCT374A
This device is similar in function to the HCT534A, which has 1 AWLYYWW
CASE 751D
inverting outputs.
1
• Output Drive Capability: 15 LSTTL Loads 20

• TTL/NMOS–Compatible Input Levels TSSOP–20 HCT

• Outputs Directly Interface to CMOS, NMOS, and TTL
20
1
DT SUFFIX 374A
ALYW
CASE 948G
• Operating Voltage Range: 4.5 to 5.5 V
•
1
Low Input Current: 1.0 µA
•
A = Assembly Location
In Compliance with the Requirements Defined by JEDEC Standard WL = Wafer Lot
No. 7A YY = Year
• Chip Complexity: 276 FETs or 69 Equivalent Gates WW = Work Week

• Improvements over HCT374

— Improved Propagation Delays ORDERING INFORMATION
— 50% Lower Quiescent Power
Device Package Shipping
— Improved Input Noise and Latchup Immunity
MC74HCT374AN PDIP–20 1440 / Box
MC74HCT374ADW SOIC–WIDE 38 / Rail
MC74HCT374ADWR2 SOIC–WIDE 1000 / Reel
MC74HCT374ADT TSSOP–20 75 / Rail
MC74HCT374ADTR2 TSSOP–20 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 225 Publication Order Number:

March, 2000 – Rev. 8 MC74HCT374A/D
 MC74HCT374A

PIN ASSIGNMENT
OUTPUT
1 20 VCC
ENABLE
Q0 2 19 Q7
LOGIC DIAGRAM D0 3 18 D7
D1 4 17 D6
3 2
D0 Q0
Q1 5 16 Q6
4 5
D1 Q1
Q2 6 15 Q5
7 6
D2 Q2
D2 7 14 D5
8 9
DATA D3 Q3
NONINVERTING D3 8 13 D4
INPUTS 13 12
D4 Q4 OUTPUTS
Q3 9 12 Q4
14 15
D5 Q5
GND 10 11 CLOCK
17 16
D6 Q6
18 19
D7 Q7

CLOCK
11 FUNCTION TABLE
Inputs Output
Output
PIN 20 = VCC
1 Enable Clock D Q
PIN 10 = GND
OUTPUT ENABLE
L H H
L L L
L L,H, X No Change
H X X Z

X = don’t care

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Z = high impedance

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Design Criteria Value Units

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Count* 69 ea.

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Propagation Delay 1.5 ns
µW

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Power Dissipation 5.0
Speed Power Product .0075 pJ
*Equivalent to a two–input NAND gate.

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226
 MC74HCT374A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC, SSOP or TSSOP Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
ÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 2.0 2.0 2.0 V
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 20 µA 5.5 2.0 2.0 2.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 0.8 0.8 0.8 V
v Voltage |Iout| 20 µA 5.5 0.8 0.8 0.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 4.5 0.1 0.1 0.1 V
v Voltage |Iout| 20 µA 5.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout| 6.0 mA 4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 5.5 ± 0.5 ± 5.0 ± 10 µA
Leakage Current Vin = VIL or VIH

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎICC ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Quiescent Supply
Vout = VCC or GND
Vin = VCC or GND 5.5 4.0 40 160 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current (per Package) Iout = 0 µA

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227
 MC74HCT374A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
∆ICC ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Additional Quiescent Supply Vin = 2.4 V, Any One Input ≥ –55_C 25_C to 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Current Vin = VCC or GND, Other In
Inputs
uts
lout = 0 µA 5.5 2.9 2.4 mA
NOTE: 1. Total Supply Current = ICC + Σ∆ICC.
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ – 55 to
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Symbol Parameter 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
fmax Maximum Clock Frequency (50% Duty Cycle) 30 24 20 MHz

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figures 1 and 4)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, Maximum Propagation Delay, Clock to Q 31 39 47 ns
tPHL (Figures 1 and 4)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Propagation Delay, Output Enable to Q

ÎÎÎÎ
ÎÎÎ
(Figures 2 and 5)
30 38 45 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPZL, Maximum Propagation Delay, Output Enable to Q 30 38 45 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPZH (Figures 2 and 5)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 12 15 18 ns
tTHL (Figures 1 and 4)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Maximum Input Capacitance 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Cout
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Three–State Output Capacitance

ÎÎÎÎ
ÎÎÎ
(Output in High–Impedance State)
15 15 15

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
pF

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Flip–Flop)* 65 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ – 55 to
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Symbol Parameter 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tsu Minimum Setup Time, Data to Clock 12 15 18 ns
(Figure 3)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
th
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Minimum Hold Time, Clock to Data

ÎÎÎÎ
(Figure 3)
ÎÎÎ
5.0 5.0 5.0 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tw
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Minimum Pulse Width, Clock

ÎÎÎÎ
(Figure 1)

ÎÎÎ
12 15 18 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tr, tf Maximum Input Rise and Fall Times 500 500 500 ns
(Figure 1)

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228
 MC74HCT374A

SWITCHING WAVEFORMS

tr tf 3V
VCC OUTPUT 1.3 V
CLOCK 2.7 V
1.3 V ENABLE GND
0.3 V GND tPZL tPLZ
tw HIGH
IMPEDANCE
1/fmax Q 1.3 V
10% VOL
tPLH tPHL tPZH tPHZ
90% VOH
1.3 V 90%
Q 10% Q 1.3 V HIGH
tTLH tTHL IMPEDANCE

Figure 1. Figure 2.

VALID
DATA 3V
1.3 V
GND
tsu th
3V
CLOCK 1.3 V
GND

Figure 3.

TEST CIRCUITS

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kΩ
TESTING tPLZ AND tPZL
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 4. Figure 5.

EXPANDED LOGIC DIAGRAM

D0 D1 D2 D3 D4 D5 D6 D7
3 4 7 8 13 14 17 18
D Q D Q D Q D Q D Q D Q D Q D Q

C C C C C C C C

11
CLOCK

OUTPUT 1
ENABLE 2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

http://onsemi.com
229
MC74HC390A

Dual 4-Stage Binary Ripple

Counter with ÷ 2 and ÷ 5
Sections
High–Performance Silicon–Gate CMOS
The MC74HC390A is identical in pinout to the LS390. The device http://onsemi.com
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs. MARKING
This device consists of two independent 4–bit counters, each DIAGRAMS
composed of a divide–by–two and a divide–by–five section. The 16
divide–by–two and divide–by–five counters have separate clock PDIP–16
N SUFFIX MC74HC390AN
inputs, and can be cascaded to implement various combinations of ÷ 2 16
CASE 648
AWLYYWW
and/or ÷ 5 up to a ÷ 100 counter. 1
1
Flip–flops internal to the counters are triggered by high–to–low
16
transitions of the clock input. A separate, asynchronous reset is SO–16
provided for each 4–bit counter. State changes of the Q outputs do not HC390A
D SUFFIX
occur simultaneously because of internal ripple delays. Therefore, 16 AWLYWW
CASE 751B
1
decoded output signals are subject to decoding spikes and should not 1
be used as clocks or strobes except when gated with the Clock of the 16
HC390A.
HC
• Output Drive Capability: 10 LSTTL Loads 16
TSSOP–16
DT SUFFIX 390A
• Outputs Directly Interface to CMOS, NMOS, and TTL 1
CASE 948F ALYW

• Operating Voltage Range: 2 to 6 V 1

• Low Input Current: 1 µA A = Assembly Location
• High Noise Immunity Characteristic of CMOS Devices WL = Wafer Lot
YY = Year
• In Compliance with the Requirements Defined by JEDEC Standard WW = Work Week
No 7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates PIN ASSIGNMENT
LOGIC DIAGRAM
CLOCK Aa 1 16 VCC
RESET a 2 15 CLOCK Ab
1, 15 ÷2 3, 13
CLOCK A QA QAa 3 14 RESET b
COUNTER
CLOCK Ba 4 13 QAb
QBa 5 12 CLOCK Bb
5, 11 QCa 6 11 QBb
QB
4, 12 ÷5 6, 10
CLOCK B QC QDa 7 10 QCb
COUNTER 7, 9
QD
GND 8 9 QDb

PIN 16 = VCC
2, 14 PIN 8 = GND
RESET
FUNCTION TABLE
Clock
ORDERING INFORMATION
A B Reset Action Device Package Shipping
X X H Reset MC74HC390AN PDIP–16 2000 / Box
÷ 2 and ÷ 5
MC74HC390AD SOIC–16 48 / Rail
X L Increment
÷2 MC74HC390ADR2 SOIC–16 2500 / Reel
X L Increment MC74HC390ADT TSSOP–16 96 / Rail
÷5 MC74HC390ADTR2 TSSOP–16 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 230 Publication Order Number:

March, 2000 – Rev. 2 MC74HC390A/D
 MC74HC390A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
Î ÎÎ
Symbol

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
Max
6.0
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA ÎÎ
ÎÎÎÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎ
ÎÎÎ
Operating Temperature, All Package Types
0
– 55
VCC
+ 125
V
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
Input Rise and Fall Time

ÎÎÎ
VCC = 2.0 V 0 1000 ns

ÎÎ
(Figure 1) VCC = 3.0 V 0 600
VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
v
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
v
ÎÎÎÎÎÎÎ
ÎÎÎ
Parameter Test Conditions
VCC
V
– 55 to
25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v Voltage |Iout| 20 µA 3.0 2.1 2.1 2.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
3.15
4.2
3.15
4.2
3.15
4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
v Voltage |Iout| 20 µA 3.0 0.9 0.9 0.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 1.35 1.35 1.35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
v Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 2.48 2.34 2.20
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 3.98 3.84 3.70
|Iout| 5.2 mA 6.0 5.48 5.34 5.20

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
2.0
4.5
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.40
|Iout| 4.0 mA 4.5 0.26 0.33 0.40
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 5.2 mA 6.0 0.26 0.33 0.40

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231
 MC74HC390A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA
Current

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 4 40

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
160 µA

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
– 55 to

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fmax

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Clock Frequency (50% Duty Cycle)

ÎÎÎ
(Figures 1 and 3)
2.0
3.0
4.5
10
15
30
9
14
28
8
12
25
MHz

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 50 45 40

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Clock A to QA 2.0 70 80 90 ns
tPHL (Figures 1 and 3) 3.0 40 45 50

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
24
20
30
26
36
31

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Clock A to QC 2.0 200 250 300 ns
tPHL (QA connected to Clock B) 3.0 160 185 210

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figures 1 and 3) 4.5 58 65 70
6.0 49 62 68

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Clock B to QB

ÎÎÎ
(Figures 1 and 3)
2.0
3.0
70
40
80
45
90
50
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 26 33 39
6.0 22 28 33

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Clock B to QC

ÎÎÎ
(Figures 1 and 3)
2.0
3.0
4.5
90
56
37
105
70
46
180
100
56
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 31 39 48

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Clock B to QD 2.0 70 80 90 ns
tPHL (Figures 1 and 3) 3.0 40 45 50

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
26
22
33
28
39
33

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL Maximum Propagation Delay, Reset to any Q 2.0 80 95 110 ns
(Figures 2 and 3) 3.0 48 65 75

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 30 38 44
6.0 26 33 39

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
(Figures 1 and 3)
2.0
3.0
75
27
95
32
110
36
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 19 22
6.0 13 15 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Cin Maximum Input Capacitance — 10 10 10 pF
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Counter)* 35 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC390A

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6 ns)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
trec Minimum Recovery Time, Reset Inactive to Clock A or Clock B 2.0 25 30 40 ns
(Figure 2) 3.0 15 20 30

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 10 13 15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 9 11 13

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Clock A, Clock B 2.0 75 95 110 ns
(Figure 1) 3.0 27 32 36

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 19 22

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 13 15 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Reset 2.0 75 95 110 ns
(Figure 2) 3.0 27 32 36

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 20 24 30

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 18 22 28

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tf, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns
(Figure 1) 3.0 800 800 800

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 500 500 500
6.0 400 400 400
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

PIN DESCRIPTIONS
INPUTS OUTPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15) QA (Pins 3, 13)
Clock A is the clock input to the ÷ 2 counter; Clock B is Output of the ÷ 2 counter.
the clock input to the ÷ 5 counter. The internal flip–flops are
toggled by high–to–low transitions of the clock input. QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)
Outputs of the ÷ 5 counter. QD is the most significant bit.
CONTROL INPUTS QA is the least significant bit when the counter is connected
Reset (Pins 2, 14) for BCD output as in Figure 4. QB is the least significant bit
Asynchronous reset. A high at the Reset input prevents when the counter is operating in the bi–quinary mode as in
counting, resets the internal flip–flops, and forces QA Figure 5.
through QD low.
SWITCHING WAVEFORMS
tf tr tw
90% VCC VCC
CLOCK 50% 50%
RESET
10% 10% GND GND
tw tPHL
1/fmax
tPLH tPHL Q 50%

90%
Q 50% trec
10% VCC
CLOCK 50%
tTLH tTHL
GND
Figure 1. Figure 2.

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233
 MC74HC390A

TEST CIRCUIT
TEST POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 3.

EXPANDED LOGIC DIAGRAM

1, 15 Q
CLOCK A C
3, 13
D Q QA
R

4, 12
CLOCK B C Q
5, 11
D Q QB
R

C Q
6, 10 Q
D Q C
R

C
7, 9 Q
D Q D
R
2, 14
RESET

TIMING DIAGRAM
(QA Connected to Clock B)

0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6
CLOCK A

RESET

QA

QB

QC

QD

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234
 MC74HC390A

APPLICATIONS INFORMATION

Each half of the MC54/74HC390A has independent ÷ 2 To obtain a bi–quinary count sequence, the input signals
and ÷ 5 sections (except for the Reset function). The ÷ 2 and connected to the Clock B input, and output QD is connected
÷ 5 counters can be connected to give BCD or bi–quinary to the Clock A input (Figure 5). QA provides a 50% duty
(2–5) count sequences. If Output QA is connected to the cycle output. The bi–quinary count sequence function table
Clock B input (Figure 4), a decade divider with BCD output is given in Table 2.
is obtained. The function table for the BCD count sequence
is given in Table 1.

Table 1. BCD Count Sequence* Table 2. Bi–Quinary Count Sequence**

Output Output
Count QD QC QB QA Count QA QD QC QB
0 L L L L 0 L L L L
1 L L L H 1 L L L H
2 L L H L 2 L L H L
3 L L H H 3 L L H H
4 L H L L 4 L H L L
5 L H L H 8 H L L L
6 L H H L 9 H L L H
7 L H H H 10 H L H L
8 H L L L 11 H L H H
9 H L L H 12 H H L L
*QA connected to Clock B input. ** QD connected to Clock A input.

CONNECTION DIAGRAMS

1, 15 3, 13 1, 15 3, 13
÷2 QA ÷2 QA
CLOCK A CLOCK A
COUNTER COUNTER

5, 11 5, 11 QB
QB 4, 12
CLOCK B 4, 12 CLOCK B ÷5 6, 10
÷5 6, 10
QC COUNTER QC
COUNTER 7, 9 7, 9
QD QD

2, 14 2, 14
RESET RESET

Figure 4. BCD Count Figure 5. Bi-Quinary Count

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235
MC74HC393A

Dual 4-Stage Binary Ripple

Counter
High–Performance Silicon–Gate CMOS
The MC74HC393A is identical in pinout to the LS393. The device
inputs are compatible with standard CMOS outputs; with pullup
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resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4–bit binary ripple counters MARKING
with parallel outputs from each counter stage. A ÷ 256 counter can be DIAGRAMS
obtained by cascading the two binary counters. 14
Internal flip–flops are triggered by high–to–low transitions of the PDIP–14
N SUFFIX MC74HC393AN
clock input. Reset for the counters is asynchronous and active–high. CASE 646 AWLYYWW
State changes of the Q outputs do not occur simultaneously because of
1
internal ripple delays. Therefore, decoded output signals are subject to 14
decoding spikes and should not be used as clocks or as strobes except SOIC–14
HC393A
when gated with the Clock of the HC393A. D SUFFIX
AWLYWW
CASE 751A
• Output Drive Capability: 10 LSTTL Loads
1
• Outputs Directly Interface to CMOS, NMOS, and TTL 14
• Operating Voltage Range: 2 to 6 V TSSOP–14 HC
• Low Input Current: 1 µA DT SUFFIX 393A

• CASE 948G ALYW

High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard 1
A = Assembly Location
No. 7A
WL or L = Wafer Lot
• Chip Complexity: 236 FETs or 59 Equivalent Gates YY or Y = Year
WW or W = Work Week
LOGIC DIAGRAM
PIN ASSIGNMENT
3, 11
Q1
4, 10 CLOCK a 1 14 VCC
1, 13 BINARY Q2
CLOCK 5, 9 RESET a 2 13 CLOCK b
COUNTER Q3
6, 8 Q1a 3 12 RESET b
Q4
Q2a 4 11 Q1b
2, 12 Q3a
RESET 5 10 Q2b
Q4a 6 9 Q3b
PIN 14 = VCC
PIN 7 = GND GND 7 8 Q4b

FUNCTION TABLE
Inputs
Clock Reset Outputs
ORDERING INFORMATION
X H L
H L No Change Device Package Shipping
L L No Change MC74HC393AN PDIP–14 2000 / Box
L No Change
L Advance to MC74HC393AD SOIC–14 55 / Rail
Next State MC74HC393ADR2 SOIC–14 2500 / Reel
MC74HC393ADT TSSOP–14 96 / Rail
MC74HC393ADTR2 TSSOP–14 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 236 Publication Order Number:

March, 2000 – Rev. 2 MC74HC393A/D
 MC74HC393A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
VCC = 3.0 V 0 600

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Figure 1) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 1.80 1.80 1.80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
v Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ 6.0 5.9 5.9 5.9

v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ Vin = VIH or VIL |Iout| 2.4 mA 3.0 2.48 2.34 2.20
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 3.98 3.84 3.70
|Iout| 5.2 mA 6.0 5.48 5.34 5.20

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 MC74HC393A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
v
Voltage |Iout| 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.40
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.0 mA 4.5 0.26 0.33 0.40
|Iout| 5.2 mA 6.0 0.26 0.33 0.40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 µA
Iout = 0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current (per Package)
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fmax

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Clock Frequency (50% Duty Cycle)

ÎÎÎ
(Figures 1 and 3)
2.0
3.0
10
15
9
14
8
12
MHz

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 30 28 25
6.0 50 45 40

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Clock to Q1

ÎÎÎ
(Figures 1 and 3)
2.0
3.0
70
40
80
45
90
50
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 24 30 36
6.0 20 26 31

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Clock to Q2

ÎÎÎ
(Figures 1 and 3)
2.0
3.0
100
56
105
70
180
100
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 34 45 55
6.0 20 38 48

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Clock to Q3

ÎÎÎ
(Figures 1 and 3)
2.0
3.0
130
80
150
105
180
130
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 44 55 70
6.0 37 47 58

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Clock to Q4

ÎÎÎ
(Figures 1 and 3)
2.0
3.0
160
110
250
185
300
210
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 52 65 82
6.0 44 55 65

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Reset to any Q

ÎÎÎ
(Figures 2 and 3)
2.0
3.0
4.5
80
48
30
95
65
38
110
75
50
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Output Transition Time, Any Output
6.0
2.0
26
75
33
95
43
110 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTHL (Figures 1 and 3) 3.0 27 32 36
4.5 15 19 22

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎCin
NOTES:
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Input Capacitance
6.0
—
13
10
16
10
19
10 pF

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC393A

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Counter)* 35 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6 ns)

ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC – 55 to
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
trec Minimum Recovery Time, Reset Inactive to Clock 2.0 25 30 40 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figure 2) 3.0 15 20 30
4.5 10 13 15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 9 11 13

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Clock 2.0 75 95 110 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figure 1) 3.0 27 32 36
4.5 15 19 22

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 13 15 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Reset 2.0 75 95 110 ns
(Figure 2) 3.0 27 32 36

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
15
13
19
15
22
19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns
(Figure 1) 3.0 800 800 800

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
500
400
500
400
500
400
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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 MC74HC393A

PIN DESCRIPTIONS

INPUTS OUTPUTS
Clock (Pins 1, 13) Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)
Clock input. The internal flip–flops are toggled and the Parallel binary outputs Q4 is the most significant bit.
counter state advances on high–to–low transitions of the
clock input.

CONTROL INPUTS
Reset (Pins 2, 12)
Active–high, asynchronous reset. A separate reset is
provided for each counter. A high at the Reset input prevents
counting and forces all four outputs low.

SWITCHING WAVEFORMS
tf tr tw
90% VCC
VCC
CLOCK 50% RESET 50%
10%
GND GND
tw tPHL
1/fmax
tPLH tPHL 50%
Q
90%
Q 50% trec
10% VCC
CLOCK 50%
GND
tTLH tTHL

Figure 1. Figure 2.

TEST EXPANDED LOGIC DIAGRAM

POINT
1, 13
OUTPUT CLOCK C Q
DEVICE 3, 11
D Q Q1
UNDER
TEST CL*

C Q
4, 10
D Q Q2
*Includes all probe and jig capacitance

Figure 3. Test Circuit

C Q
5, 9
D Q Q3

C Q
6, 8
D Q Q4

2, 12
RESET

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 MC74HC393A

TIMING DIAGRAM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0

CLOCK

RESET

Q1

Q2

Q3

Q4

COUNT SEQUENCE

Outputs
Count Q4 Q3 Q2 Q1
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
9 H L L H
10 H L H L
11 H L H H
12 H H L L
13 H H L H
14 H H H L
15 H H H H

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MC74HC540A

Octal 3-State Inverting

Buffer/Line Driver/Line
Receiver
High–Performance Silicon–Gate CMOS
The MC74HC540A is identical in pinout to the LS540. The device http://onsemi.com
inputs are compatible with Standard CMOS outputs. External pullup
resistors make them compatible with LSTTL outputs. MARKING
The HC540A is an octal inverting buffer/line driver/line receiver DIAGRAMS
designed to be used with 3–state memory address drivers, clock 20
drivers, and other bus–oriented systems. This device features inputs PDIP–20
MC74HC540AN
and outputs on opposite sides of the package and two ANDed P SUFFIX
AWLYYWW
20 CASE 738
active–low output enables.
1
The HC540A is similar in function to the HC541A, which has 1
20
non–inverting outputs.
SOIC WIDE–20
• Output Drive Capability: 15 LSTTL Loads 20
1
DW SUFFIX HC540A
AWLYYWW
• Outputs Directly Interface to CMOS, NMOS and TTL
CASE 751D
1
• Operating Voltage Range: 2 to 6V
A = Assembly Location
• Low Input Current: 1µA WL = Wafer Lot
• High Noise Immunity Characteristic of CMOS Devices YY = Year
• In Compliance With the JEDEC Standard No. 7A Requirements
WW = Work Week

• Chip Complexity: 124 FETs or 31 Equivalent Gates

LOGIC DIAGRAM ORDERING INFORMATION
Device Package Shipping
2 18
A1 Y1 MC74HC540AN PDIP–20 1440 / Box
3 17 MC74HC540ADW SOIC–WIDE 38 / Rail
A2 Y2
MC74HC540ADWR2 SOIC–WIDE 1000 / Reel
4 16
A3 Y3

5 15
Data A4 Y4 Inverting
Inputs 6 14 Outputs
A5 Y5

7 13
A6 Y6

8 12
A7 Y7

9 11
A8 Y8

1
Output OE1
OE2 PIN 20 = VCC Pinout: 20–Lead Packages (Top View)
Enables 19 PIN 10 = GND
VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
FUNCTION TABLE
20 19 18 17 16 15 14 13 12 11
Inputs
Output Y
OE1 OE2 A
L L L H
L L H L
H X X Z
X H X Z
1 2 3 4 5 6 7 8 9 10
Z = High Impedance
X = Don’t Care OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND

 Semiconductor Components Industries, LLC, 2000 242 Publication Order Number:

March, 2000 – Rev. 7 MC74HC540A/D
 MC74HC540A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature Range – 65 to + 150 _C Unused outputs must be left open.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
Plastic DIP or SOIC Package 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
_C

ÎÎÎÎ
TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Operating Temperature Range, All Package Types

ÎÎÎ
– 55

ÎÎ
+ 125
tr, tf

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
Input Rise/Fall Time

ÎÎÎ
VCC = 2.0 V 0 1000 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
(Figure 1)

ÎÎÎÎÎ
ÎÎÎ
VCC = 4.5 V
VCC = 6.0 V
0
0
500
400

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Vout = 0.1V 2.0 1.50 1.50 1.50 V
Voltage |Iout| ≤ 20µA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Vout = VCC – 0.1V 2.0 0.50 0.50 0.50 V
Voltage |Iout| ≤ 20µA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum High–Level Output Vin = VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin = VIL |Iout| ≤ 3.6mA 3.0 2.48 2.34 2.20
|Iout| ≤ 6.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 7.8mA 6.0 5.48 5.34 5.20
VOL Maximum Low–Level Output Vin = VIH 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH |Iout| ≤ 3.6mA 3.0 0.26 0.33 0.40
|Iout| ≤ 6.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 7.8mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

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 MC74HC540A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
IOZ Maximum Three–State Leakage Output in High Impedance State 6.0 ±0.5 ±5.0 ±10.0 µA
Current Vin = VIL or VIH
Vout = VCC or GND
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 µA
Current (per Package) Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A to Output Y 2.0 80 100 120 ns
tPHL (Figures 1 and 3) 3.0 30 40 55
4.5 18 23 28
6.0 15 20 25
tPLZ, Maximum Propagation Delay, Output Enable to Output Y 2.0 110 140 165 ns
tPHZ (Figures 2 and 4) 3.0 45 60 75
4.5 25 31 38
6.0 21 26 31
tPZL, Maximum Propagation Delay, Output Enable to Output Y 2.0 110 140 165 ns
tPZH (Figures 2 and 4) 3.0 45 60 75
4.5 25 31 38
6.0 21 26 31
tTLH, Maximum Output Transition Time, Any Output 2.0 60 75 90 ns
tTHL (Figures 1 and 3) 3.0 22 28 34
4.5 12 15 18
6.0 10 13 15
Cin Maximum Input Capacitance 10 10 10 pF
Cout Maximum Three–State Output Capacitance (Output in High 15 15 15 pF
Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

CPD Power Dissipation Capacitance (Per Buffer)* 35 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS

tr tf VCC
OE1 or OE2 50% 50%
90% VCC
GND
INPUT A 50% tPZL tPLZ
HIGH
10% GND IMPEDANCE
tPHL tPLH OUTPUT Y 50%
90% 10%
VOL
50% tPZH tPHZ
OUTPUT Y
10% VOH
90%
OUTPUT Y
tTLH 50%
tTHL
HIGH
IMPEDANCE
Figure 1. Figure 2.

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244
 MC74HC540A

TEST CIRCUITS

TEST TEST
POINT POINT
CONNECT TO VCC WHEN
OUTPUT OUTPUT 1kΩ
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ and tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 3. Figure 4.

PIN DESCRIPTIONS

INPUTS outputs are enabled and the device functions as an inverter.

A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, When a hgih voltage is applied to either input, the outputs
9) — Data input pins. Data on these pins appear in inverted assume the high impedance state.
form on the corresponding Y outputs, when the outputs are
enabled. OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
CONTROLS 13, 12, 11) — Device outputs. Depending upon the state of
OE1, OE2 (PINS 1, 19) — Output enables (active–low). the output enable pins, these outputs are either inverting
When a low voltage is applied to both of these pins, the outputs or high–impedance outputs.

LOGIC DETAIL

To 7 Other
Inverters

VCC
One of Eight
Inverters

INPUT A
OUTPUT Y

OE1

OE2

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245
MC74HC541A

Octal 3-State Non-Inverting

Buffer/Line Driver/
Line Receiver
High–Performance Silicon–Gate CMOS
The MC74HC541A is identical in pinout to the LS541. The device http://onsemi.com
inputs are compatible with Standard CMOS outputs. External pullup MARKING
resistors make them compatible with LSTTL outputs. DIAGRAMS
The HC541A is an octal non–inverting buffer/line driver/line 20
receiver designed to be used with 3–state memory address drivers, PDIP–20
clock drivers, and other bus–oriented systems. This device features MC74HC541AN
P SUFFIX
AWLYYWW
inputs and outputs on opposite sides of the package and two ANDed 20 CASE 738
active–low output enables. 1 1
The HC541A is similar in function to the HC540A, which has 20
inverting outputs. SOIC WIDE–20
20 DW SUFFIX HC541A
• Output Drive Capability: 15 LSTTL Loads 1 CASE 751D AWLYYWW

• Outputs Directly Interface to CMOS, NMOS and TTL 1

• Operating Voltage Range: 2 to 6V A = Assembly Location
• Low Input Current: 1µA WL = Wafer Lot
YY = Year
• High Noise Immunity Characteristic of CMOS Devices WW = Work Week
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates FUNCTION TABLE
LOGIC DIAGRAM Inputs
Output Y
2 18 OE1 OE2 A
A1 Y1
L L L L
3 17 L L H H
A2 Y2
H X X Z
4 16
A3 Y3 X H X Z
5 15 Z = High Impedance
Data A4 Y4 Non–Inverting X = Don’t Care
Inputs 6 14 Outputs
A5 Y5

7 13
A6 Y6
ORDERING INFORMATION
8 12
A7 Y7 Device Package Shipping
9 11 MC74HC541AN PDIP–20 1440 / Box
A8 Y8
MC74HC541ADW SOIC–WIDE 38 / Rail
1 PIN 20 = VCC
Output OE1 MC74HC541ADWR2 SOIC–WIDE 1000 / Reel
Enables OE2 PIN 10 = GND
19

Pinout: 20–Lead Packages (Top View)

VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND

 Semiconductor Components Industries, LLC, 2000 246 Publication Order Number:

March, 2000 – Rev. 2 MC74HC541A/D
 MC74HC541A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
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MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature Range – 65 to + 150 _C Unused outputs must be left open.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
Plastic DIP or SOIC Package 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
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Symbol Parameter Min Max Unit

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
_C

ÎÎÎÎ
TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Operating Temperature Range, All Package Types

ÎÎÎ
– 55

ÎÎ
+ 125
tr, tf

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
Input Rise/Fall Time

ÎÎÎ
VCC = 2.0 V 0 1000 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
(Figure 1)

ÎÎÎÎÎ
ÎÎÎ
VCC = 4.5 V
VCC = 6.0 V
0
0
500
400

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Vout = 0.1V 2.0 1.50 1.50 1.50 V
Voltage |Iout| ≤ 20µA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Vout = VCC – 0.1V 2.0 0.50 0.50 0.50 V
Voltage |Iout| ≤ 20µA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum High–Level Output Vin = VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin = VIL |Iout| ≤ 3.6mA 3.0 2.48 2.34 2.20
|Iout| ≤ 6.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 7.8mA 6.0 5.48 5.34 5.20
VOL Maximum Low–Level Output Vin = VIH 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH |Iout| ≤ 3.6mA 3.0 0.26 0.33 0.40
|Iout| ≤ 6.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 7.8mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

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 MC74HC541A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
IOZ Maximum Three–State Leakage Output in High Impedance State 6.0 ±0.5 ±5.0 ±10.0 µA
Current Vin = VIL or VIH
Vout = VCC or GND
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 µA
Current (per Package) Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A to Output Y 2.0 80 100 120 ns
tPHL (Figures 1 and 3) 3.0 30 40 55
4.5 18 23 28
6.0 15 20 25
tPLZ, Maximum Propagation Delay, Output Enable to Output Y 2.0 110 140 165 ns
tPHZ (Figures 2 and 4) 3.0 45 60 75
4.5 25 31 38
6.0 21 26 31
tPZL, Maximum Propagation Delay, Output Enable to Output Y 2.0 110 140 165 ns
tPZH (Figures 2 and 4) 3.0 45 60 75
4.5 25 31 38
6.0 21 26 31
tTLH, Maximum Output Transition Time, Any Output 2.0 60 75 90 ns
tTHL (Figures 1 and 3) 3.0 22 28 34
4.5 12 15 18
6.0 10 13 15
Cin Maximum Input Capacitance 10 10 10 pF
Cout Maximum Three–State Output Capacitance (Output in High 15 15 15 pF
Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

CPD Power Dissipation Capacitance (Per Buffer)* 35 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS
VCC
tr tf
OE1 or OE2 50% 50%
VCC
90%
GND
INPUT A 50% tPZL tPLZ
HIGH
10% GND IMPEDANCE
tPLH tPHL OUTPUT Y 50%
10% VOL
90%
50% tPZH tPHZ
OUTPUT Y
10% VOH
90%
OUTPUT Y
tTHL 50%
tTLH
HIGH
IMPEDANCE
Figure 1. Figure 2.

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248
 MC74HC541A

TEST CIRCUITS
TEST TEST
POINT POINT
CONNECT TO VCC WHEN
OUTPUT OUTPUT 1kΩ
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ and tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 3. Figure 4.

PIN DESCRIPTIONS

INPUTS outputs are enabled and the device functions as an

A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, non–inverting buffer. When a high voltage is applied to
9) — Data input pins. Data on these pins appear in either input, the outputs assume the high impedance state.
non–inverted form on the corresponding Y outputs, when
the outputs are enabled. OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
CONTROLS 13, 12, 11) — Device outputs. Depending upon the state of
OE1, OE2 (PINS 1, 19) — Output enables (active–low). the output enable pins, these outputs are either
When a low voltage is applied to both of these pins, the non–inverting outputs or high–impedance outputs.

LOGIC DETAIL
To 7 Other
Buffers

VCC
One of Eight
Buffers

INPUT A
OUTPUT Y

OE1

OE2

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249
MC74HCT541A

Octal 3-State Non-Inverting

Buffer/Line Driver/
Line Receiver With
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS http://onsemi.com

The MC74HCT541A is identical in pinout to the LS541. This MARKING

device may be used as a level converter for interfacing TTL or NMOS DIAGRAMS
20
outputs to high speed CMOS inputs.
PDIP–20
The HCT541A is an octal non–inverting buffer/line driver/line MC74HCT541AN
P SUFFIX
receiver designed to be used with 3–state memory address drivers, AWLYYWW
20 CASE 738
clock drivers, and other bus–oriented systems. This device features 1
1
inputs and outputs on opposite sides of the package and two ANDed 20
active–low output enables. SOIC WIDE–20
HCT541A
• Output Drive Capability: 15 LSTTL Loads
20
1
DW SUFFIX
CASE 751D AWLYYWW
• TTL/NMOS–Compatible Input Levels 1
• Outputs Directly Interface to CMOS, NMOS and TTL A = Assembly Location
• Operating Voltage Range: 4.5 to 5.5V WL = Wafer Lot
• Low Input Current: 1µA YY = Year
WW = Work Week
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates
ORDERING INFORMATION
LOGIC DIAGRAM Device Package Shipping
MC74HCT541AN PDIP–20 1440 / Box
2 18
A1 Y1 MC74HCT541ADW SOIC–WIDE 38 / Rail
3 17 MC74HCT541ADWR2 SOIC–WIDE 1000 / Reel
A2 Y2

4 16 FUNCTION TABLE
A3 Y3
Inputs
Output Y
5 15 OE1 OE2 A
Data A4 Y4 Non–Inverting
Inputs Outputs L L L L
6 14
A5 Y5 L L H H
H X X Z
7 13
A6 Y6 X H X Z
Z = High Impedance
8 12 X = Don’t Care
A7 Y7

9 11
Pinout: 20–Lead Packages (Top View)
A8 Y8
VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
1 20 19 18 17 16 15 14 13 12 11
Output OE1
OE2 PIN 20 = VCC
Enables
19 PIN 10 = GND

1 2 3 4 5 6 7 8 9 10
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND

 Semiconductor Components Industries, LLC, 2000 250 Publication Order Number:

March, 2000 – Rev. 2 MC74HCT541A/D
 MC74HCT541A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature Range – 65 to + 150 _C Unused outputs must be left open.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
Plastic DIP or SOIC Package 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
_C

ÎÎÎÎ
TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Operating Temperature Range, All Package Types

ÎÎÎ
– 55

ÎÎ
+ 125
tr, tf
ÎÎÎ
Input Rise/Fall Time (Figure 1) 0 500 ns

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Vout = 0.1V or VCC – 0.1V 4.5 2.0 2.0 2.0 V
Voltage |Iout| ≤ 20µA 5.5 2.0 2.0 2.0
VIL Maximum Low–Level Input Vout = 0.1V or VCC – 0.1V 4.5 0.8 0.8 0.8 V
Voltage |Iout| ≤ 20µA 5.5 0.8 0.8 0.8
VOH Minimum High–Level Output Vin = VIH or VIL 4.5 4.4 4.4 4.4 V
Voltage |Iout| ≤ 20µA 5.5 5.4 5.4 5.4
Vin = VIH or VIL |Iout| ≤ 6.0mA 4.5 3.98 3.84 3.70
VOL Maximum Low–Level Output Vin = VIH or VIL 4.5 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 5.5 0.1 0.1 0.1
Vin = VIH or VIL |Iout| ≤ 6.0mA 4.5 0.26 0.33 0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA
IOZ Maximum Three–State Leakage Output in High Impedance State 5.5 ±0.5 ±5.0 ±10.0 µA
Current Vin = VIL or VIH
Vout = VCC or GND
ICC Maximum Quiescent Supply Vin = VCC or GND 5.5 4 40 160 µA
Current (per Package) Iout = 0µA

∆ICC Additional Quiescent Supply Vin = 2.4V, Any One Input ≥ –55°C 25 to 125°C
Current Vin
i = VCC or GND,
GND Other Inputs
Iout = 0µA 5.5 2.9 2.4 mA
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + Σ∆ICC.

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251
 MC74HCT541A

AC CHARACTERISTICS (VCC = 5.0V, CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
Symbol Parameter –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A to Output Y 23 28 32 ns
tPHL (Figures 1 and 3)
tPLZ, Maximum Propagation Delay, Output Enable to Output Y 30 34 38 ns
tPHZ (Figures 2 and 4)
tPZL, Maximum Propagation Delay, Output Enable to Output Y 30 34 38 ns
tPZH (Figures 2 and 4)
tTLH, Maximum Output Transition Time, Any Output 12 15 18 ns
tTHL (Figures 1 and 3)
Cin Maximum Input Capacitance 10 10 10 pF
Cout Maximum Three–State Output Capacitance (Output in High Impedance 15 15 15 pF
State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Buffer)* 55 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS

tr tf 3.0V
OE1 or OE2 1.3V 1.3V
90% 3.0V
GND
INPUT A 1.3V tPZL tPLZ
HIGH
10% GND IMPEDANCE
tPLH tPHL OUTPUT Y 1.3V
10%
90% VOL
1.3V tPZH tPHZ
OUTPUT Y
10% 90% VOH
OUTPUT Y
tTHL 1.3V
tTLH
HIGH
IMPEDANCE
Figure 1. Figure 2.

TEST CIRCUITS

TEST TEST
POINT POINT
CONNECT TO VCC WHEN
OUTPUT OUTPUT 1kΩ
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ and tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 3. Figure 4.

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 MC74HCT541A

PIN DESCRIPTIONS

INPUTS outputs are enabled and the device functions as a

A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, non–inverting buffer. When a high voltage is applied to
9) — Data input pins. Data on these pins appear in either input, the outputs assume the high impedance state.
non–inverted form on the corresponding Y outputs, when
the outputs are enabled. OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
CONTROLS 13, 12, 11) — Device outputs. Depending upon the state of
OE1, OE2 (PINS 1, 19) — Output enables (active–low). the output enable pins, these outputs are either
When a low voltage is applied to both of these pins, the non–inverting outputs or high–impedance outputs.

LOGIC DETAIL

To 7 Other
Buffers

VCC
One of Eight
Buffers

INPUT A
OUTPUT Y

OE1

OE2

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253
MC74HC573A

Octal 3-State Noninverting

Transparent Latch
High–Performance Silicon–Gate CMOS
The MC74HC573A is identical in pinout to the LS573. The devices
are compatible with standard CMOS outputs; with pullup resistors,
http://onsemi.com
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change MARKING
asynchronously) when Latch Enable is high. When Latch Enable goes DIAGRAMS
low, data meeting the setup and hold time becomes latched. 20
The HC573A is identical in function to the HC373A but has the data PDIP–20
MC74HC573AN
inputs on the opposite side of the package from the outputs to facilitate P SUFFIX
AWLYYWW
CASE 738
PC board layout. 20
1
•
1
Output Drive Capability: 15 LSTTL Loads 20
• Outputs Directly Interface to CMOS, NMOS and TTL SOIC WIDE–20
HC573A
• Operating Voltage Range: 2.0 to 6.0 V
20
1
DW SUFFIX
CASE 751D AWLYYWW
• Low Input Current: 1.0 µA 1
• In Compliance with the Requirements Defined by JEDEC Standard 20

No. 7A TSSOP–20 HC
• Chip Complexity: 218 FETs or 54.5 Equivalent Gates 20 DT SUFFIX 573A
ALYW
1 CASE 948G
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

ORDERING INFORMATION
Device Package Shipping
MC74HC573AN PDIP–20 1440 / Box
MC74HC573ADW SOIC–WIDE 38 / Rail
MC74HC573ADWR2 SOIC–WIDE 1000 / Reel
MC74HC573ADT TSSOP–20 75 / Rail
MC74HC573ADTR2 TSSOP–20 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 254 Publication Order Number:

March, 2000 – Rev. 8 MC74HC573A/D
 MC74HC573A

LOGIC DIAGRAM PIN ASSIGNMENT

OUTPUT
2 19 1 20 VCC
D0 Q0 ENABLE
3 18 D0 2 19 Q0
D1 Q1
4 17 D1 3 18 Q1
D2 Q2
DATA 5 16 NONINVERTING D2 4 17 Q2
D3 Q3
INPUTS 6 15 OUTPUTS
D4 Q4 D3 5 16 Q3
7 14
D5 Q5 D4 6 15 Q4
8 13
D6 Q6 D5 7 14 Q5
9 12
D7 Q7 D6 8 13 Q6
11 D7 9 12 Q7
LATCH ENABLE
PIN 20 = VCC GND 10 11 LATCH
1 ENABLE
OUTPUT ENABLE PIN 10 = GND

FUNCTION TABLE
Inputs Output
Output Latch
Enable Enable D Q
L H H H
L H L L
L L X No Change
H X X Z
X = Don’t Care

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Z = High Impedance

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Design Criteria Value Units

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Count* 54.5 ea.

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Internal Gate Propagation Delay

ÎÎÎÎ
ÎÎÎ
Internal Gate Power Dissipation
1.5

5.0
ns

µW

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Speed Power Product

*Equivalent to a two–input NAND gate.

0.0075 pJ

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255
 MC74HC573A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 35 mA cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, Plastic DIP† 750 mW Unused inputs must always be
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500
TSSOP Package† 450 level (e.g., either GND or VCC).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, TSSOP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: –6.1 mW/°C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage (Referenced to GND)

ÎÎ
ÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
2.0
0
6.0
VCC
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
Input Rise and Fall Time

ÎÎÎÎÎ
ÎÎÎ
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIH
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0
3.0
4.5
1.5
2.1
3.15
1.5
2.1
3.15
1.5
2.1
3.15
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 1.8 18 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.2
|Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 7.8 mA 6.0 5.48 5.34 5.2
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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256
 MC74HC573A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vout = 0.1 V or VCC – 0.1 V 2.0 0.1 0.1 0.1 V
Voltage |Iout| 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.4
|Iout| 6.0 mA 4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ |Iout| 7.8 mA 6.0 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 6.0 – 0.5 – 5.0 – 10 µA
Leakage Current Vin = VIL or VIH

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4.0 40 160 µA
Current (per Package) IIoutI = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC – 55 to

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Parameter
Maximum Propagation Delay, Input D to Q
V
2.0
25_C
150
85_C
190
125_C
225
Unit
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL (Figures 1 and 5) 3.0 100 140 180
4.5 30 38 45

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 26 33 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Latch Enable to Q 2.0 160 200 240 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL (Figures 2 and 5) 3.0 105 145 190
4.5 32 40 48

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 27 34 41

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLZ, Maximum Propagation Delay, Output Enable to Q 2.0 150 190 225 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHZ (Figures 3 and 6) 3.0 100 125 150
4.5 30 38 45

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 26 33 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPZL, Maximum Propagation Delay, Output Enable to Q 2.0 150 190 225 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPZH (Figures 3 and 6) 3.0 100 125 150
4.5 30 38 45

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 26 33 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 2.0 60 75 90 ns
tTHL (Figures 1 and 5) 3.0 27 32 36

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
12
10
15
13
18
15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Cin Maximum Input Capacitance 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Cout Maximum Three–State Output Capacitance (Output in High–Impedance 15 15 15 pF
State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)* 23 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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257
 MC74HC573A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
v v ÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎ VCC – 55 to 25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
Symbol Parameter Fig. Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
tsu Minimum Setup Time, Input D to Latch Enable 4 2.0 50 65 75 ns
3.0 40 50 60

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
4.5 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
6.0 9.0 11 13

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
th Minimum Hold Time, Latch Enable to Input D 4 2.0 5.0 5.0 5.0 ns
3.0 5.0 5.0 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
4.5 5.0 5.0 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
6.0 5.0 5.0 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Latch Enable 2 2.0 75 95 110 ns
3.0 60 80 90

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
Maximum Input Rise and Fall Times 1 2.0 1000 1000 1000 ns

ÎÎÎÎÎ
3.0 800 800 800

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎ
4.5 500 500 500
6.0 400 400 400

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258
 MC74HC573A

SWITCHING WAVEFORMS

VCC
LATCH
tr tf 50%
ENABLE
VCC
90% GND
INPUT D 50%
10% GND tw
tPLH tPHL
90% tPLH tPHL
Q 50%
10%
tTLH tTHL Q 50%

Figure 1. Figure 2.

OUTPUT 3.0 V
ENABLE 50% VALID
GND VCC
tPZL tPLZ INPUT D 50%
HIGH GND
Q 50% IMPEDANCE tSU th
10% VOL VCC
tPZH tPHZ LATCH 50%
90% VOH GND
ENABLE
Q 1.3 V
HIGH
IMPEDANCE
Figure 3. Figure 4.

TEST POINT EXPANDED LOGIC DIAGRAM

2
OUTPUT D0 D 19
Q Q0
DEVICE LE
UNDER 3
CL* D1 D 18
TEST Q Q1
LE
4
D2 D 17
Q Q2
LE
*Includes all probe and jig capacitance 5
D3 D 16
Q Q3
Figure 5. Test Circuit LE
6
D4 D 15
Q Q4
LE
7
TEST POINT D5 D 14
Q Q5
LE
CONNECT TO VCC WHEN
OUTPUT 1 kΩ 8
TESTING tPLZ AND tPZL. D6 D 13
DEVICE CONNECT TO GND WHEN Q Q6
LE
UNDER TESTING tPHZ AND tPZH.
TEST CL* 9
D7 D 12
Q Q7
LE

11
*Includes all probe and jig capacitance LATCH ENABLE

1
Figure 6. Test Circuit OUTPUT ENABLE

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259
MC74HCT573A

Octal 3-State Noninverting

Transparent Latch with
LSTTL Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT573A is identical in pinout to the LS573. This http://onsemi.com
device may be used as a level converter for interfacing TTL or NMOS MARKING
outputs to High–Speed CMOS inputs. DIAGRAMS
These latches appear transparent to data (i.e., the outputs change 20
asynchronously) when Latch Enable is high. When Latch Enable goes PDIP–20
low, data meeting the setup and hold times becomes latched. MC74HCT573AN
P SUFFIX
AWLYYWW
The Output Enable input does not affect the state of the latches, but 20 CASE 738
when Output Enable is high, all device outputs are forced to the 1 1
high–impedance state. Thus, data may be latched even when the 20
outputs are not enabled. SOIC WIDE–20
20 DW SUFFIX HCT573A
The HCT573A is identical in function to the HCT373A but has the 1 AWLYYWW
CASE 751D
Data Inputs on the opposite side of the package from the outputs to
1
facilitate PC board layout. 20
• Output Drive Capability: 15 LSTTL Loads TSSOP–20 HCT
• TTL/NMOS–Compatible Input Levels 20 DT SUFFIX 573A
ALYW
•
1 CASE 948G
Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V 1

• Low Input Current: 10 µA A = Assembly Location

WL = Wafer Lot
• In Compliance with the Requirements Defined by JEDEC Standard YY = Year
No. 7A WW = Work Week
• Chip Complexity: 234 FETs or 58.5 Equivalent Gates
— Improved Propagation Delays
— 50% Lower Quiescent Power ORDERING INFORMATION
Device Package Shipping
MC74HCT573AN PDIP–20 1440 / Box
MC74HCT573ADW SOIC–WIDE 38 / Rail
MC74HCT573ADWR2 SOIC–WIDE 1000 / Reel
MC74HCT573ADT TSSOP–20 75 / Rail
MC74HCT573ADTR2 TSSOP–20 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 260 Publication Order Number:

March, 2000 – Rev. 8 MC74HCT573A/D
 MC74HCT573A

LOGIC DIAGRAM PIN ASSIGNMENT

2 19 OUTPUT
D0 Q0 1 20 VCC
ENABLE
3 18 D0 2 19 Q0
D1 Q1
4 17
D2 Q2 D1 3 18 Q1
DATA 5 16 NONINVERTING
D3 Q3 D2 4 17 Q2
INPUTS 6 15 OUTPUTS
D4 Q4 D3 5 16 Q3
7 14
D5 Q5 D4 6 15 Q4
8 13
D6 Q6
9 12 D5 7 14 Q5
D7 Q7
D6 8 13 Q6
11
LATCH ENABLE D7 9 12 Q7
PIN 20 = VCC LATCH
1 GND 10 11
OUTPUT ENABLE PIN 10 = GND ENABLE

FUNCTION TABLE
Inputs Output
Output Latch
Enable Enable D Q
L H H H
L H L L
L L X No Change
H X X Z

X = Don’t Care

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Z = High Impedance

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Design Criteria Value Units

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Count* 58.5 ea

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Propagation Delay 1.5 ns

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Power Dissipation 5.0 µW

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Speed Power Product
*Equivalent to a two–input NAND gate.
0.0075 pJ

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261
 MC74HCT573A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, TSSOP or SOIC Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: –6.1 mW/°C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
Î ÎÎ
Symbol

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
Parameter
DC Supply Voltage (Referenced to GND)
Min
4.5
Max
5.5
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
v
ÎÎÎ
ÎÎÎÎ
v ÎÎÎ VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 2.0 2.0 2.0 V
Voltage |Iout| 20 µA 5.5 2.0 2.0 2.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Low–Level Input

ÎÎÎÎ
ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 4.5 4.4 4.4 4.4 V
Voltage |Iout| 20 µA 5.5 5.4 5.4 5.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 4.5 0.1 0.1 0.1 V
20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Voltage |Iout| 5.5 0.1 0.1 0.1

v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout| 6.0 mA 4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
IOZ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Input Leakage Current

ÎÎÎÎ
ÎÎÎ
Maximum Three–State
Vin = VCC or GND
Output in High–Impedance State
5.5
5.5
± 0.1
± 0.5
± 1.0
± 5.0
± 1.0
± 10
µA
µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Leakage Current Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Quiescent Supply

ÎÎÎÎ
ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout 0 µA
5.5 4.0 40 160 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
∆ICC Additional Quiescent Supply Vin = 2.4 V, Any One Input ≥ – 55_C 25_C to 125_C
Current Vin = VCC or GND,
GND Other InInputs
uts

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
lout = 0 µA 5.5 2.9 2.4 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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262
 MC74HCT573A

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
– 55 to
v v
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Symbol Parameter 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, Maximum Propagation Delay, Input D to Output Q 30 38 45 ns
tPHL (Figures 1 and 5)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tPLH
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Propagation Delay, Latch Enable to Q

ÎÎÎÎ
ÎÎÎ
(Figures 2 and 5)
30 38 45 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TPLZ,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TPHZ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Propagation Delay, Output Enable to Q

ÎÎÎÎ
ÎÎÎ
(Figures 3 and 6)
28 35 42 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTZL, Maximum Propagation Delay, Output Enable to Q 28 35 42 ns
tTZH (Figures 3 and 6)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tTLH,
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Output Transition Time, any Output

ÎÎÎÎ
ÎÎÎ
(Figures 1 and 5)
12 15 18 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Maximum Input Capacitance 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Cout
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Maximum Three–State Output Capacitance

ÎÎÎÎ
ÎÎÎ
(Output in High–Impedance State)
15 15 15

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
pF

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)* 48 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Guaranteed Limit
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
– 55 to 25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
Symbol Parameter Fig. Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
tsu Minimum Setup Time, Input D to Latch Enable 4 10 13 15 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
th Minimum Hold Time, Latch Enable to Input D 4 5.0 5.0 5.0 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
tw Minimum Pulse Width, Latch Enable 2 15 19 22 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
tr, tf Maximum Input Rise and Fall Times 1 500 500 500 ns

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263
 MC74HCT573A

SWITCHING WAVEFORMS

3.0 V
LATCH
tr tf 1.3 V
ENABLE
3.0 V
2.7 V GND
INPUT D 1.3 V
0.3 V GND tw
tPLH tPHL
90% tPLH tPHL
Q 1.3 V
10%
tTLH tTHL Q 1.3 V

Figure 1. Figure 2.

OUTPUT 3.0 V
ENABLE 1.3 V VALID
GND 3.0 V
tPZL tPLZ INPUT D 1.3 V
HIGH GND
Q 1.3 V IMPEDANCE tSU th
10% VOL 3.0 V
tPZH tPHZ LATCH 1.3 V
90% VOH GND
ENABLE
Q 1.3 V
HIGH
IMPEDANCE
Figure 3. Figure 4.

TEST POINT EXPANDED LOGIC DIAGRAM

2
OUTPUT D0 D 19
Q Q0
DEVICE LE
UNDER 3
CL* D1 D 18
TEST Q Q1
LE
4
D2 D 17
Q Q2
LE
*Includes all probe and jig capacitance 5
D3 D 16
Q Q3
Figure 5. Test Circuit LE
6
D4 D 15
Q Q4
LE
7
D5 D 14
TEST POINT Q Q5
LE
CONNECT TO VCC WHEN 8
OUTPUT 1 kΩ D6
TESTING tPLZ AND tPZL. D 13
Q Q6
DEVICE CONNECT TO GND WHEN LE
UNDER TESTING tPHZ AND tPZH. 9
TEST CL* D7 D 12
Q Q7
LE

11
LATCH ENABLE
*Includes all probe and jig capacitance

1
OUTPUT ENABLE
Figure 6. Test Circuit

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264
MC74HC574A

Octal 3-State Noninverting

D Flip-Flop
High–Performance Silicon–Gate CMOS
The MC74HC574A is identical in pinout to the LS574. The device
inputs are compatible with standard CMOS outputs; with pullup
http://onsemi.com
resistors, they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising MARKING
edge of the Clock. The Output Enable input does not affect the states DIAGRAMS
of the flip–flops, but when Output Enable is high, all device outputs 20
are forced to the high–impedance state. Thus, data may be stored even PDIP–20
MC74HC574AN
when the outputs are not enabled. P SUFFIX
AWLYYWW
CASE 738
The HC574A is identical in function to the HC374A but has the 20
1
flip–flop inputs on the opposite side of the package from the outputs to 1
20
facilitate PC board layout.
SOIC WIDE–20
• Output Drive Capability: 15 LSTTL Loads 20 DW SUFFIX HC574A
AWLYYWW
1
• Outputs Directly Interface to CMOS, NMOS and TTL
CASE 751D

• Operating Voltage Range: 2.0 to 6.0 V

1

• Low Input Current: 1.0 µA A = Assembly Location

WL = Wafer Lot
• In Compliance with the Requirements Defined by JEDEC Standard YY = Year
No. 7A WW = Work Week
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates
ORDERING INFORMATION
Device Package Shipping
MC74HC574AN PDIP–20 1440 / Box
MC74HC574ADW SOIC–WIDE 38 / Rail
MC74HC574ADWR2 SOIC–WIDE 1000 / Reel

 Semiconductor Components Industries, LLC, 2000 265 Publication Order Number:

March, 2000 – Rev. 8 MC74HC574A/D
 MC74HC574A

LOGIC DIAGRAM PIN ASSIGNMENT

2 19 OUTPUT
D0 Q0 1 20 VCC
3 18 ENABLE
D1 Q1 D0 2 19 Q0
4 17
D2 Q2
D1 3 18 Q1
DATA 5 16 NON–
D3 Q3
INPUTS 6 15 INVERTING D2 4 17 Q2
D4 Q4 OUTPUTS
7 14 D3 5 16 Q3
D5 Q5
8 13 D4 6 15 Q4
D6 Q6
9 12 D5 7 14 Q5
D7 Q7
11 D6 8 13 Q6
CLOCK
PIN 20 = VCC D7 9 12 Q7
1 PIN 10 = GND
OUTPUT ENABLE GND 10 11 CLOCK

FUNCTION TABLE
Inputs Output
OE Clock D Q
L H H
L L L
L L,H, X No Change
H X X Z
X = Don’t Care

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Z = High Impedance

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Design Criteria Value Units

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Count* 66.5 ea

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Internal Gate Propagation Delay

ÎÎÎÎ
ÎÎÎ
Internal Gate Power Dissipation
1.5

5.0
ns

µW

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Speed Power Product 0.0075

*Equivalent to a two–input NAND gate.

pJ

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266
 MC74HC574A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 35 mA cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500
level (e.g., either GND or VCC).
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 Unused outputs must be left open.
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ
Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
(Figure 1) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V 2.0 0.5 0.5 0.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH 2.0 1.9 1.9 1.9 V
v Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ 6.0 5.9 5.9 5.9

v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ Vin = VIH |Iout| 2.4 mA 3.0 2.48 2.34 2.2
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 6.0 mA 4.5 3.98 3.84 3.7
|Iout| 7.8 mA 6.0 5.48 5.34 5.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VIL
|Iout| 20 µA
2.0
4.5
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.4
v |Iout| 6.0 mA 4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Iin ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Input Leakage Vin = VCC or GND
|Iout| 7.8 mA 6.0
6.0
0.26
± 0.1
0.33
± 1.0
0.4
± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current

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 MC74HC574A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
IOZ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Three–State

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Leakage Current
ÎÎÎ
Output in High–Impedance State
Vin = VIL or VIH
6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4.0 40 160 µA
Current (per Package) Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ v ÎÎÎ
ÎÎÎÎÎÎÎ
Parameter Test Conditions
VCC
V
– 55 to
25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IOZ Maximum Three–State Output in High–Impedance State 6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Leakage Current Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
|Iout| = 0 µA
6.0 4.0 40 160 µA

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC – 55 to

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fmax ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Parameter
Maximum Clock Frequency (50% Duty Cycle)
V
2.0
25_C
6.0
85_C
4.8
125_C
4.0
Unit
MHz

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figures 1 and 4) 3.0 15 10 8.0
4.5 30 24 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 35 28 24

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Clock to Q 2.0 160 200 240 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL (Figures 1 and 4) 3.0 105 145 190
4.5 32 40 48

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 27 34 41

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLZ, Maximum Propagation Delay, Output Enable to Q 2.0 150 190 225 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHZ (Figures 2 and 5) 3.0 100 125 150
4.5 30 38 45

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 26 33 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPZL, Maximum Propagation Delay, Output Enable to Q 2.0 140 175 210 ns
tPZH (Figures 2 and 5) 3.0 90 120 140

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
60
28
24
35
30
42
36

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, any Output 2.0 60 75 90 ns
tTHL (Figures 1 and 4) 3.0 27 32 36

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
12
10
15
13
18
15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Cin Maximum Input Capacitance 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Cout Maximum Three–State Output Capacitance, Output in High–Impedance 15 15 15 pF
State
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)* 24 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
v v ÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎ VCC – 55 to 25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
Symbol Parameter Fig. Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
tsu Minimum Setup Time, Data to Clock 3 2.0 50 65 75 ns
3.0 40 50 60

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
4.6 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
6.0 9.0 11 13

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
th Minimum Hold Time, Clock to Data 3 2.0 5.0 5.0 5.0 ns
3.0 5.0 5.0 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
4.5 5.0 5.0 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
6.0 5.0 5.0 5.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Clock 1 2.0 75 95 110 ns
3.0 60 80 90

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
Maximum Input Rise and Fall Times 1 2.0 1000 1000 1000 ns

ÎÎÎÎÎ
3.0 800 800 800

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎ
4.5 500 500 500
6.0 400 400 400

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 MC74HC574A

SWITCHING WAVEFORMS

tr tf
VCC 3.0 V
90%
CLOCK 50% 1.3 V
10% GND GND
tw tPZL tPLZ
HIGH
1/fmax
1.3 V IMPEDANCE
tPLH tPHL Q
10% VOL
90% tPZH tPHZ
Q 50% 90% VOH
10% Q
HIGH
tTLH tTHL IMPEDANCE

Figure 1. Figure 2.

VALID EXPANDED LOGIC DIAGRAM

VCC
DATA 50%
GND C 19
2 Q Q0
tsu th D0 D
VCC
CLOCK 50% C 18
GND 3 Q Q1
D1 D

Figure 3. C 17
4 Q Q2
D2 D

TEST POINT C 16
5 Q Q3
D3 D
OUTPUT
DEVICE C 15
6 Q Q4
UNDER D4 D
TEST CL*

C 14
7 Q Q5
D5 D

*Includes all probe and jig capacitance C 13

8 Q Q6
D6 D
Figure 4.
C 12
9 Q Q7
D7 D
TEST POINT
CONNECT TO VCC WHEN
OUTPUT 1 kΩ 11
TESTING tPLZ AND tPZL. CLOCK
DEVICE CONNECT TO GND WHEN
UNDER TESTING tPHZ AND tPZH.
CL* 1
TEST OUTPUT ENABLE

*Includes all probe and jig capacitance

Figure 5. Test Circuit

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MC74HCT574A

Octal 3-State Noninverting

D Flip-Flop with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT574A is identical in pinout to the LS574. This http://onsemi.com
device may be used as a level converter for interfacing TTL or NMOS MARKING
outputs to High Speed CMOS inputs. DIAGRAMS
Data meeting the setup time is clocked to the outputs with the rising 20
edge of the Clock. The Output Enable input does not affect the states PDIP–20
of the flip–flops, but when Output Enable is high, all device outputs MC74HCT574AN
P SUFFIX
AWLYYWW
are forced to the high–impedance state. Thus, data may be stored even 20 CASE 738
when the outputs are not enabled. 1 1
The HCT574A is identical in function to the HCT374A but has the 20
flip–flop inputs on the opposite side of the package from the outputs to SOIC WIDE–20
20 DW SUFFIX HCT574A
facilitate PC board layout. 1 AWLYYWW
CASE 751D
• Output Drive Capability: 15 LSTTL Loads 1
• TTL NMOS Compatible Input Levels A = Assembly Location
• Outputs Directly Interface to CMOS, NMOS and TTL WL = Wafer Lot
• Operating Voltage Range: 4.5 to 5.5 V
YY
WW
= Year
= Work Week
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A ORDERING INFORMATION
• Chip Complexity: 286 FETs or 71.5 Equivalent Gates Device Package Shipping
MC74HCT574AN PDIP–20 1440 / Box
MC74HCT574ADW SOIC–WIDE 38 / Rail
MC74HCT574ADWR2 SOIC–WIDE 1000 / Reel

 Semiconductor Components Industries, LLC, 2000 271 Publication Order Number:

March, 2000 – Rev. 8 MC74HCT574A/D
 MC74HCT574A

LOGIC DIAGRAM PIN ASSIGNMENT

2 19 OUTPUT 1 20 VCC
D0 Q0
ENABLE
3 18
D1 Q1 D0 2 19 Q0
4 17
D2 Q2 D1 3 18 Q1
DATA 5 16 NON–
D3 Q3 D2 4 17 Q2
INPUTS 6 15 INVERTING
D4 Q4 OUTPUTS
7 14 D3 5 16 Q3
D5 Q5
8 13 D4 6 15 Q4
D6 Q6
9 12 D5 7 14 Q5
D7 Q7
D6 8 13 Q6
11
CLOCK
D7 9 12 Q7
PIN 20 = VCC
1 PIN 10 = GND GND 10 11 CLOCK
OUTPUT ENABLE

FUNCTION TABLE
Inputs Output
OE Clock D Q
L H H
L L L
L L,H, X No Change
H X X Z
X = don’t care

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Z = high impedance

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Design Criteria Value Units

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Internal Gate Count*

ÎÎÎÎ
ÎÎÎ
Internal Gate Propagation Delay
71.5

1.5
ea

ns

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Internal Gate Power Dissipation 5.0 µW

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Speed Power Product 0.0075 pJ

*Equivalent to a two–input NAND gate.

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 MC74HCT574A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C Unused outputs must be left open.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
(Plastic DIP or SOIC Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎ
ÎÎÎÎÎÎ
DC Supply Voltage (Referenced to GND)

ÎÎ
ÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
4.5
0
5.5
VCC
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎ
ÎÎ
ÎÎÎ
Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎ
ÎÎÎ
Input Rise and Fall Time (Figure 1) 0 500 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 2.0 2.0 2.0 V
v Voltage |Iout| 20 µA 5.5 2.0 2.0 2.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL V
v |Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout| 6.0 mA 4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND
Current (per Package) Iout = 0 µA 5.5 4.0 40 160 µA
1. Output in high–impedance state.
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

http://onsemi.com
273
 MC74HCT574A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
IOZ Maximum Three–State Vin = VIL or VIH (Note 1) 5.5 – 0.5 – 5.0 – 10 µA
Leakage Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Current

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
∆ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
Additional Quiescent Supply Vin = 2.4 V, Any One Input ≥ – 55_C 25_C to 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
Current Vin = VCC or GND,
GND Other In
Inputs
uts
lout = 0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
5.5 2.9 2.4 mA
1. Output in high–impedance state.

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
– 55 to
v v
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
Symbol Parameter 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
fMAX Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 30 24 20 MHz

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
tPLH, Maximum Propagation Delay, Clock to Q 30 38 45 ns
tPHL (Figures 1 and 4)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tPLZ,
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
Maximum Propagation Delay, Output Enable to Q

ÎÎÎÎ
ÎÎÎ
(Figures 2 and 5)
28 35 42 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
tPZH, Maximum Propagation Delay Time, Output Enable to Q 28 35 42 ns
tPZL (Figures 2 and 5)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tTLH,
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎÎ
ÎÎÎ
(Figures 1, 2 and 4)
12 15 18 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
tTHL

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Flip–Flop)* 58 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
v ÎÎÎÎÎÎ
ÎÎÎÎÎ
v ÎÎ – 55 to 25_C
Guaranteed Limit
85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol
tsu
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
ÎÎ
Parameter
Minimum Setup Time, Data to Clock
Fig.
3
Min
10
Max Min
13
Max Min
15
Max Unit
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
th
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
Minimum Hold Time, Clock to Data

ÎÎÎ
ÎÎ
Minimum Pulse Width, Clock
3
1
5.0
15
5.0
19
5.0
22
ns
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, If
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
Maximum Input Rise and Fall Times 1 500 500 500 ns

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274
 MC74HCT574A

EXPANDED LOGIC DIAGRAM

D0 D1 D2 D3 D4 D5 D6 D7
2 3 4 5 6 7 8 9

11
CLOCK

D D D D D D D D
C C C C C C C C
Q Q Q Q Q Q Q Q

ENABLE 1
OUTPUT

19 18 17 16 15 14 13 12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

SWITCHING WAVEFORMS
tr tf
3.0 V 3.0 V
2.7 V OUTPUT
CLOCK 1.3 V 1.3 V
0.3 V GND ENABLE GND
tw tPZL tPLZ
HIGH
1/fmax
1.3 V IMPEDANCE
tPLH tPHL Q
10% VOL
90% tPZH tPHZ
Q 1.3 V 90% VOH
10% Q 1.3 V HIGH
tTLH tTHL IMPEDANCE

Figure 1. Figure 2.

TEST POINT

VALID OUTPUT
3.0 V DEVICE
1.3 V UNDER
DATA GND TEST CL*
tsu th
3.0 V
1.3 V
CLOCK GND
*Includes all probe and jig capacitance

Figure 3. Figure 4. Test Circuit

TEST POINT
CONNECT TO VCC WHEN
OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE CONNECT TO GND WHEN
UNDER TESTING tPHZ AND tPZH.
TEST CL*

*Includes all probe and jig capacitance

Figure 5. Test Circuit

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275
MC74HC589A

8-Bit Serial or
Parallel-Input/Serial-Output
Shift Register with 3-State
Output
High–Performance Silicon–Gate CMOS http://onsemi.com

The MC74HC589A device consists of an 8–bit storage latch which MARKING

feeds parallel data to an 8–bit shift register. Data can also be loaded DIAGRAMS
serially (see Function Table). The shift register output, QH, is a 16
PDIP–16
three–state output, allowing this device to be used in bus–oriented MC74HC589AN
N SUFFIX
systems. 16
CASE 648
AWLYYWW
The HC589A directly interfaces with the SPI serial data port on 1
1
CMOS MPUs and MCUs.
16
• Output Drive Capability: 15 LSTTL Loads SO–16
HC589A
• Outputs Directly Interface to CMOS, NMOS, and TTL 16
D SUFFIX
CASE 751B
AWLYWW
• Operating Voltage Range: 2 to 6 V 1
1
• Low Input Current: 1 µA 16
• High Noise Immunity Characteristic of CMOS Devices
TSSOP–16 HC
• In Compliance with the Requirements Defined by JEDEC Standard 16 DT SUFFIX 589A
No. 7A CASE 948F ALYW
1
• Chip Complexity: 526 FETs or 131.5 Equivalent Gates 1
A = Assembly Location
LOGIC DIAGRAM WL = Wafer Lot
SERIAL YY = Year
DATA 14 WW = Work Week
SA
INPUT
PIN ASSIGNMENT
15
A B 1 16 VCC
1
B C 2 15 A
2
C VCC = PIN 16
PARALLEL 3 D 3 14 SA
D GND = PIN 8 SERIAL SHIFT/
DATA E 4 13
4 DATA SHIFT PARALLEL LOAD
INPUTS E
5 LATCH REGISTER F 5 12 LATCH CLOCK
F
6 G 6 11 SHIFT CLOCK
G SERIAL
7 9 H 7 10 OUTPUT ENABLE
H QH DATA
OUTPUT
12 GND 8 9 QH
LATCH CLOCK

11
SHIFT CLOCK
SERIAL SHIFT/ 13
PARALLEL LOAD ORDERING INFORMATION
10
OUTPUT ENABLE Device Package Shipping
MC74HC589AN PDIP–16 2000 / Box
MC74HC589AD SOIC–16 48 / Rail
MC74HC589ADR2 SOIC–16 2500 / Reel
MC74HC589ADT TSSOP–16 96 / Rail
MC74HC589ADTR2 TSSOP–16 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 276 Publication Order Number:

March, 2000 – Rev. 1 MC74HC589A/D
 MC74HC589A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 35 mA cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500
TSSOP Package† 450 level (e.g., either GND or VCC).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
Î ÎÎ
Symbol

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
Max
6.0
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
VCC = 3.0 V 0 TBD
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
VCC = 6.0 V 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to
25_C
Guaranteed Limit

85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V Unit

v
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 20 µA 3.0 2.1 2.1 2.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0
3.0
4.5
0.5
0.9
1.35
0.5
0.9
1.35
0.5
0.9
1.35
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output V
v
Vin = VIH or VIL 2.0 1.9 1.9 1.9
Voltage 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL |Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VIH
|Iout| 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL |Iout|
|Iout|
2.4 mA
6.0 mA
3.0
4.5
0.26
0.26
0.33
0.33
0.40
0.40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 7.8 mA 6.0 0.26 0.33 0.40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA
Current

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 MC74HC589A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
IOZ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Three–State

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Leakage Current

ÎÎÎ
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 4 40 160

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
µA

(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v v Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fmax

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Clock Frequency (50% Duty Cycle)

ÎÎÎ
(Figures 2 and 8)
2.0
3.0
6.0
TBD
4.8
TBD
4.0
TBD
MHz

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 30 24 20
6.0 35 28 24

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Latch Clock to QH

ÎÎÎ
(Figures 1 and 8)
2.0
3.0
4.5
175
100
40
225
110
50
275
125
60
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 30 40 50

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Shift Clock to QH 2.0 160 200 240 ns
tPHL (Figures 2 and 8) 3.0 90 130 160

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
30
25
40
30
48
40

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Serial Shift/Parallel Load to QH 2.0 160 200 240 ns
tPHL (Figures 4 and 8) 3.0 90 130 160

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 30 40 48
6.0 25 30 40

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Output Enable to QH

ÎÎÎ
(Figures 3 and 9)
2.0
3.0
4.5
150
80
27
170
100
30
200
130
40
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZL, ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Propagation Delay, Output Enable to QH
6.0
2.0
23
150
25
170
30
200 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPZH (Figures 3 and 9) 3.0 80 100 130
4.5 27 30 40

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 23 25 30

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 2.0 60 75 90 ns
tTHL (Figures 1 and 8) 3.0 TBD TBD TBD

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 12 15 18

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 10 13 15
Cin Maximum Input Capacitance — 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cout

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
NOTES:
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Three–State Output Capacitance (Output in

ÎÎÎ
High–Impedance State)
— 15 15 15 pF

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 50 pF
2
* Used to determine the no–load dynamic power consumption: P D = C PD V CC f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC589A

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6 ns)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v 25_C 85_C 125_C

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tsu Minimum Setup Time, A–H to Latch Clock 2.0 100 125 150 ns
(Figure 5) 3.0 TBD TBD TBD

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 20 25 30
6.0 17 21 26

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tsu
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(Figure 6)

ÎÎÎÎÎÎÎ
Minimum Setup Time, Serial Data Input SA to Shift Clock

ÎÎÎ
2.0
3.0
4.5
100
TBD
20
125
TBD
25
150
TBD
30
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 17 21 26

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tsu Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock 2.0 100 125 150 ns
(Figure 7) 3.0 TBD TBD TBD

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
20
17
25
21
30
26

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
th Minimum Hold Time, Latch Clock to A–H 2.0 25 30 40 ns
(Figure 5) 3.0 TBD TBD TBD

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 5 6 8
6.0 5 6 7

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
th
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(Figure 6)

ÎÎÎÎÎÎÎ
Minimum Hold Time, Shift Clock to Serial Data Input SA

ÎÎÎ
2.0
3.0
4.5
5
5
5
5
5
5
5
5
5
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Minimum Pulse Width, Shift Clock
6.0
2.0
5
75
5
95
5
110 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figure 2) 3.0 TBD TBD TBD
4.5 15 19 23

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 13 16 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Latch Clock 2.0 80 100 120 ns
(Figure 1) 3.0 TBD TBD TBD

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 16 20 24
6.0 14 17 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tw
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(Figure 4)

ÎÎÎÎÎÎÎ
Minimum Pulse Width, Serial Shift/Parallel Load

ÎÎÎ
2.0
3.0
80
TBD
100
TBD
120
TBD
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 16 20 24
6.0 14 17 20

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figure 1) 3.0 TBD TBD TBD
4.5 500 500 500

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 400 400 400
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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 MC74HC589A

FUNCTION TABLE
Inputs Resulting Function
Serial Parallel Data Shift
Output Serial Shift/ Latch Shift Input Inputs Latch Register Output
Operation Enable Parallel Load Clock Clock SA A–H Contents Contents QH
Force output into high H X X X X X X X Z
impedance state
Load parallel data into L H L, H, X a–h a–h U U
data latch
Transfer latch contents to L L L, H, X X X U LRN SRN LRH
shift register
Contents of input latch L H L, H, L, H, X X U U U
and shift register are
unchanged
Load parallel data into L L X X a–h a–h a–h h
data latch and shift
register
Shift serial data into shift L H X D X * SRA = D, SRG SRH
register SRN SRN+1
Load parallel data in data L H D a–h a–h SRA = D, SRG SRH
latch and shift serial data SRN SRN+1
into shift register
LR = latch register contents U = remains unchanged
SR = shift register contents X = don’t care
a–h = data at parallel data inputs A–H Z = high impedance
D = data (L, H) at serial data input SA * = depends on Latch Clock input

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 MC74HC589A

SWITCHING WAVEFORMS

tr tf
1/fmax
VCC
90% tw
LATCH CLOCK 50% VCC
10% GND SHIFT CLOCK
tw 50%
GND

tPLH tPHL
tPLH tPHL
90%
QH 50%
10% QH 50%
tTLH tTHL

Figure 1. (Serial Shift/Parallel Load = L) Figure 2. (Serial Shift/Parallel Load = H)

VCC
OUTPUT 50%
ENABLE GND tw
tPZL tPLZ VCC
HIGH SERIAL SHIFT/ 50% 50%
50% IMPEDANCE PARALLEL LOAD GND
QH
10% VOL tPLH tPHL
tPZH tPHZ
90% VOH QH 50%
QH 50% HIGH
IMPEDANCE

Figure 3. Figure 4.

DATA VALID DATA VALID

VCC VCC
A–H 50% SA 50%
GND GND
tsu th tsu th

LATCH CLOCK 50% SHIFT CLOCK 50%

Figure 5. Figure 6.

TEST POINT

VCC OUTPUT
SERIAL SHIFT/ 50% DEVICE
PARALLEL LOAD GND UNDER
TEST CL*
tsu

SHIFT CLOCK 50%

*Includes all probe and jig capacitance

Figure 7. Figure 8. Test Circuit

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 MC74HC589A

TEST CIRCUIT

TEST POINT
CONNECT TO VCC WHEN
OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE CONNECT TO GND WHEN
UNDER TESTING tPHZ AND tPZH.
TEST CL*

*Includes all probe and jig capacitance

Figure 9.

PIN DESCRIPTIONS

DATA INPUTS data in stage H is shifted out QH, being replaced by the data
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7) previously stored in stage G.
Parallel data inputs. Data on these inputs are stored in the
Latch Clock (Pin 12)
data latch on the rising edge of the Latch Clock input.
Data latch clock. A low–to–high transition on this input
SA (Pin 14)
loads the parallel data on inputs A–H into the data latch.
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input if Serial Output Enable (Pin 10)
Shift/Parallel Load is high. Data on this input is ignored Active–low output enable A high level applied to this pin
when Serial Shift/Parallel Load is low. forces the QH output into the high impedance state. A low
level enables the output. This control does not affect the state
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)
of the input latch or the shift register.
Shift register mode control. When a high level is applied OUTPUT
to this pin, the shift register is allowed to serially shift data. QH (Pin 9)
When a low level is applied to this pin, the shift register Serial data output. This pin is the output from the last stage
accepts parallel data from the data latch. of the shift register. This is a 3–state output.
Shift Clock (Pin 11)
Serial shift clock. A low–to–high transition on this input
shifts data on the serial data input into the shift register and

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 MC74HC589A

TIMING DIAGRAM

SHIFT CLOCK

SERIAL DATA
INPUT, SA

OUTPUT ENABLE

SERIAL SHIFT/
PARALLEL LOAD

LATCH CLOCK

A L H L L

B L L L L

C L H L L

PARALLEL D L L L L
DATA
INPUTS
E L H L H

F L H L H

G L L L L

H L H H H

ÉÉÉÉÉ
ÉÉÉÉÉ
QH HIGH IMPEDANCE H L H H L H L H L H L L L H L H H
SERIAL SHIFT SERIAL SHIFT SERIAL SHIFT SERIAL
SHIFT

RESET LATCH LOAD LATCH PARALLEL LOAD LOAD LATCH PARALLEL LOAD PARALLEL LOAD, LATCH
AND SHIFT REGISTER SHIFT REGISTER SHIFT REGISTER AND SHIFT REGISTER

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 MC74HC589A

LOGIC DETAIL

10
OUTPUT ENABLE
14
SA

11
SHIFT CLOCK
SERIAL SHIFT/ 13
PARALLEL LOAD
12
LATCH CLOCK STAGE A

15
A D Q
C S
D
C Q
R

STAGE B

1
B D Q
C S
D
C Q
R

PARALLEL
DATA 2
INPUTS C STAGE C*

3
D STAGE D*

4
E STAGE E*

5
F STAGE F*

6
G STAGE G*

STAGE H
VCC
7
H D Q
C S
D 9
C Q QH
R

*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.

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MC74HC595A

8-Bit Serial-Input/Serial or
Parallel-Output Shift
Register with Latched
3-State Outputs
High–Performance Silicon–Gate CMOS http://onsemi.com

The MC74HC595A consists of an 8–bit shift register and an 8–bit MARKING

D–type latch with three–state parallel outputs. The shift register DIAGRAMS
accepts serial data and provides a serial output. The shift register also 16
PDIP–16
provides parallel data to the 8–bit latch. The shift register and latch MC74HC595AN
N SUFFIX
have independent clock inputs. This device also has an asynchronous 16
CASE 648
AWLYYWW
reset for the shift register. 1
1
The HC595A directly interfaces with the SPI serial data port on
16
CMOS MPUs and MCUs. SO–16
HC595A
• Output Drive Capability: 15 LSTTL Loads 16
D SUFFIX
AWLYWW
CASE 751B
• Outputs Directly Interface to CMOS, NMOS, and TTL 1
1
• Operating Voltage Range: 2.0 to 6.0 V 16
• Low Input Current: 1.0 µA
HC
•
TSSOP–16
High Noise Immunity Characteristic of CMOS Devices 16 DT SUFFIX 595A
• In Compliance with the Requirements Defined by JEDEC Standard 1
CASE 948F ALYW
No. 7A 1
• Chip Complexity: 328 FETs or 82 Equivalent Gates A = Assembly Location
• Improvements over HC595 WL = Wafer Lot
YY = Year
— Improved Propagation Delays
WW = Work Week
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
PIN ASSIGNMENT
LOGIC DIAGRAM QB 1 16 VCC
SERIAL
DATA 14 15 QC 2 15 QA
A QA
INPUT 1
QB QD 3 14 A
2
QC QE 4 13 OUTPUT ENABLE
3 PARALLEL
QD QF 5 12 LATCH CLOCK
4 DATA
SHIFT QE OUTPUTS
LATCH QG 6 11 SHIFT CLOCK
REGISTER 5
QF
6 QH 7 10 RESET
QG
7 GND 8 9 SQH
QH
SHIFT 11
CLOCK
10 9 SERIAL
RESET SQH DATA
OUTPUT ORDERING INFORMATION
LATCH 12
CLOCK Device Package Shipping
VCC = PIN 16
OUTPUT 13 MC74HC595AN PDIP–16 2000 / Box
GND = PIN 8
ENABLE
MC74HC595AD SOIC–16 48 / Rail
MC74HC595ADR2 SOIC–16 2500 / Reel
MC74HC595ADT TSSOP–16 96 / Rail
MC74HC595ADTR2 TSSOP–16 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 285 Publication Order Number:

March, 2000 – Rev. 8 MC74HC595A/D
 MC74HC595A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 35 mA cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500
level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC
ÎÎÎ
ÎÎ
ÎÎÎ
DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
DC Input Voltage, Output Voltage

ÎÎÎ
0 VCC V

ÎÎ
(Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
(Figure 1) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ v ÎÎÎ
ÎÎÎÎÎÎÎ
Parameter Test Conditions
VCC
V
– 55 to
25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage |Iout| 3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
v Voltage, QA – QH 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|Iout| 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
v
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL |Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Voltage, QA – QHÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
2.0
4.5
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.4
|Iout| 6.0 mA 4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ |Iout| 7.8 mA 6.0 0.26 0.33 0.4

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286
 MC74HC595A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOH
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Voltage, SQH ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎ
Vin = VIH or VIL
IIoutI 20 µA
2.0
4.5
1.9
4.4
1.9
4.4
1.9
4.4
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
vv ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 2.4 mA 3.0 2.98 2.34 2.2
IIoutI 4.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IIoutI 5.2 mA 6.0 5.48 5.34 5.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Voltage, SQH IIoutI 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
vv ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL |Iout|
IIoutI
IIoutI
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
Current
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
IOZ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Leakage
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Maximum Three–State

ÎÎÎ
Current, QA – QH
ÎÎÎÎÎÎÎ
ÎÎÎ
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Current (per Package)ÎÎÎ
Maximum Quiescent Supply

ÎÎÎ
Vin = VCC or GND
lout = 0 µA
6.0 4.0 40 160 µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fmax

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Figures 1 and 7)
ÎÎÎ
Maximum Clock Frequency (50% Duty Cycle)

ÎÎÎ
2.0
3.0
4.5
6.0
15
30
4.8
10
24
4.0
8.0
20
MHz

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 35 28 24

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Shift Clock to SQH 2.0 140 175 210 ns

ÎÎÎÎÎ
tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figures 1 and 7)

ÎÎÎÎ
3.0

ÎÎÎÎ
100

ÎÎÎ
125

ÎÎÎÎ
150

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
28
24
35
30
42
36

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHL Maximum Propagation Delay, Reset to SQH 2.0 145 180 220 ns
(Figures 2 and 7) 3.0 100 125 150

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 29 36 44
6.0 25 31 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Figures 3 and 7) ÎÎÎ
Maximum Propagation Delay, Latch Clock to QA – QH

ÎÎÎ
2.0
3.0
140
100
175
125
210
150
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 28 35 42
6.0 24 30 36

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ,

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Figures 4 and 8)
ÎÎÎ
Maximum Propagation Delay, Output Enable to QA – QH

ÎÎÎ
2.0
3.0
4.5
150
100
30
190
125
38
225
150
45
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 26 33 38

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPZL, Maximum Propagation Delay, Output Enable to QA – QH 2.0 135 170 205 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPZH (Figures 4 and 8) 3.0 90 110 130
4.5 27 34 41

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 23 29 35

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, QA – QH 2.0 60 75 90 ns
tTHL (Figures 3 and 7) 3.0 23 27 31

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 12 15 18
6.0 10 13 15

http://onsemi.com
287
 MC74HC595A

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol v Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, SQH

ÎÎÎ
(Figures 1 and 7)
2.0
3.0
75
27
95
32
110
36
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 19 22
6.0 13 16 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Capacitance — 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cout
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Three–State Output Capacitance (Output in
High–Impedance State), QA – QH
— 15 15 15

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
pF

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 300 pF
2
* Used to determine the no–load dynamic power consumption: P D = C PD V CC f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)

ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC 25_C to
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter V – 55_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tsu Minimum Setup Time, Serial Data Input A to Shift Clock 2.0 50 65 75 ns
(Figure 5) 3.0 40 50 60

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
6.0
10
9.0
13
11
15
13

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tsu Minimum Setup Time, Shift Clock to Latch Clock 2.0 75 95 110 ns
(Figure 6) 3.0 60 70 80

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 15 19 22

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 13 16 19

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
th Minimum Hold Time, Shift Clock to Serial Data Input A 2.0 5.0 5.0 5.0 ns
(Figure 5) 3.0 5.0 5.0 5.0

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 5.0 5.0 5.0
6.0 5.0 5.0 5.0

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
trec
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(Figure 2)
ÎÎÎÎÎÎÎ
Minimum Recovery Time, Reset Inactive to Shift Clock

ÎÎÎ
2.0
3.0
50
40
65
50
75
60
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 10 13 15
6.0 9.0 11 13

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tw
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(Figure 2)

ÎÎÎÎÎÎÎ
Minimum Pulse Width, Reset

ÎÎÎ
2.0
3.0
60
45
75
60
90
70
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 12 15 18
6.0 10 13 15

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tw
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(Figure 1)

ÎÎÎÎÎÎÎ
Minimum Pulse Width, Shift Clock

ÎÎÎ
2.0
3.0
4.5
50
40
10
65
50
13
75
60
15
ns

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tw ÎÎÎÎ
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ÎÎÎ
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Minimum Pulse Width, Latch Clock
6.0
2.0
9.0
50
11
65
13
75 ns

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(Figure 6) 3.0 40 50 60
4.5 10 13 15

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6.0 9.0 11 13

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tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figure 1) 3.0 800 800 800
4.5 500 500 500

ÎÎÎÎÎ
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ÎÎÎÎ
ÎÎÎÎ
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ÎÎÎÎÎÎÎ
6.0 400 400 400

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 MC74HC595A

FUNCTION TABLE
Inputs Resulting Function
Serial Shift Latch Serial Parallel
Input Shift Latch Output Register Register Output Outputs
Operation Reset A Clock Clock Enable Contents Contents SQH QA – QH
Reset shift register L X X L, H, ↓ L L U L U
Shift data into shift H D ↑ L, H, ↓ L D SRA; U SRG SRH U
register SRN SRN+1
Shift register remains H X L, H, ↓ L, H, ↓ L U U U U
unchanged
Transfer shift register H X L, H, ↓ ↑ L U SRN LRN U SRN
contents to latch
register
Latch register remains X X X L, H, ↓ L * U * U
unchanged
Enable parallel outputs X X X X L * ** * Enabled
Force outputs into high X X X X H * ** * Z
impedance state
SR = shift register contents D = data (L, H) logic level ↑ = Low–to–High * = depends on Reset and Shift Clock inputs
LR = latch register contents U = remains unchanged ↓ = High–to–Low ** = depends on Latch Clock input

PIN DESCRIPTIONS

INPUTS Output Enable (Pin 13)

A (Pin 14) Active–low Output Enable. A low on this input allows the
Serial Data Input. The data on this pin is shifted into the data from the latches to be presented at the outputs. A high
8–bit serial shift register. on this input forces the outputs (QA–QH) into the
CONTROL INPUTS high–impedance state. The serial output is not affected by
Shift Clock (Pin 11) this control unit.
Shift Register Clock Input. A low– to–high transition on OUTPUTS
this input causes the data at the Serial Input pin to be shifted QA – QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)
into the 8–bit shift register. Noninverted, 3–state, latch outputs.
Reset (Pin 10) SQH (Pin 9)
Active–low, Asynchronous, Shift Register Reset Input. A Noninverted, Serial Data Output. This is the output of the
low on this pin resets the shift register portion of this device eighth stage of the 8–bit shift register. This output does not
only. The 8–bit latch is not affected. have three–state capability.
Latch Clock (Pin 12)
Storage Latch Clock Input. A low–to–high transition on
this input latches the shift register data.

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 MC74HC595A

SWITCHING WAVEFORMS

tr tf tw
VCC VCC
SHIFT 90% 50%
50% RESET
CLOCK GND
10% GND
tw tPHL

1/fmax 50%
OUTPUT
tPLH tPHL SQH
90% trec
OUTPUT
SQH 50% SHIFT VCC
10% 50%
CLOCK
tTLH tTHL GND

Figure 1. Figure 2.

VCC
LATCH VCC OUTPUT 50%
50% ENABLE GND
CLOCK
GND tPZL tPLZ
HIGH
50% IMPEDANCE
tPLH tPHL OUTPUT Q
10% VOL
90%
QA–QH 50% tPZH tPHZ
90% VOH
OUTPUTS 10%
OUTPUT Q 50% HIGH
tTLH tTHL
IMPEDANCE

Figure 3. Figure 4.

VCC
SHIFT
VALID 50%
CLOCK
VCC GND
SERIAL
50% tsu
INPUT A
GND VCC
tsu th LATCH
50%
VCC CLOCK
SWITCH GND
50% tw
CLOCK
GND

Figure 5. Figure 6.

TEST CIRCUITS

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance
Figure 7. Figure 8.

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 MC74HC595A

EXPANDED LOGIC DIAGRAM

OUTPUT 13
ENABLE

LATCH 12
CLOCK

SERIAL 14 15
D Q D Q QA
DATA
INPUT A SRA LRA
R

1
D Q D Q QB
SRB LRB
R

2
D Q D Q QC
SRC LRC
R

3
D Q D Q QD
SRD LRD PARALLEL
R DATA
OUTPUTS
4
D Q D Q QE
SRE LRE
R

5
D Q D Q QF
SRF LRF
R

6
D Q D Q QG
SRG LRG
R

7
D Q D Q QH
SHIFT
11
CLOCK SRH LRH
R

10 SERIAL
RESET 9 DATA
OUTPUT SQH

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 MC74HC595A

TIMING DIAGRAM

SHIFT
CLOCK
SERIAL DATA
INPUT A

RESET

LATCH
CLOCK

OUTPUT
ENABLE

QA

QB

QC

QD

QE

QF

QG

QH

SERIAL DATA
OUTPUT SQH
NOTE: implies that the output is in a high–impedance
state.

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MC74HC4020A

14-Stage Binary Ripple

Counter
High–Performance Silicon–Gate CMOS
The MC74C4020A is identical in pinout to the standard CMOS
MC14020B. The device inputs are compatible with standard CMOS
http://onsemi.com
outputs; with pullup resistors, they are compatible with LSTTL
outputs. MARKING
This device consists of 14 master–slave flip–flops with 12 stages DIAGRAMS
brought out to pins. The output of each flip–flop feeds the next and the 16
frequency at each output is half of that of the preceding one. Reset is PDIP–16
N SUFFIX MC74HC4020AN
asynchronous and active–high. 16 AWLYYWW
CASE 648
State changes of the Q outputs do not occur simultaneously because 1
of internal ripple delays. Therefore, decoded output signals are subject 1
to decoding spikes and may have to be gated with the Clock of the 16
HC4020A for some designs. SO–16
HC4020A
D SUFFIX
• Output Drive Capability: 10 LSTTL Loads
16
CASE 751B
AWLYWW
1
• Outputs Directly Interface to CMOS, NMOS, and TTL 1

• Operating Voltage Range: 2 to 6 V 16

• Low Input Current: 1 µA TSSOP–16 HC40

• 16 DT SUFFIX 20A
High Noise Immunity Characteristic of CMOS Devices ALYW
CASE 948F
• In Compliance With JEDEC Standard No. 7A Requirements 1
1
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
A = Assembly Location
WL = Wafer Lot
LOGIC DIAGRAM YY = Year
9 WW = Work Week
Q1
7
Q4
5 FUNCTION TABLE
Q5
4
Q6 Clock Reset Output State
10 6
Clock Q7
13 L No Charge
Q8
12 L Advance to Next State
Q9
14 X H All Outputs Are Low
Q10
15
Q11
1
Q12
2
Q13
3
Q14
ORDERING INFORMATION
11 Pin 16 = VCC
Reset Device Package Shipping
Pin 8 = GND
MC74HC4020AN PDIP–16 2000 / Box
VCC Q11 Q10 Q8 Q9 Reset Clock Q1
MC74HC4020AD SOIC–16 48 / Rail
16 15 14 13 12 11 10 9
MC74HC4020ADR2 SOIC–16 2500 / Reel
MC74HC4020ADT TSSOP–16 96 / Rail
Pinout: 16–Lead Plastic Package
MC74HC4020ADTR2 TSSOP–16 2500 / Reel
(Top View)

1 2 3 4 5 6 7 8
Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND

 Semiconductor Components Industries, LLC, 2000 293 Publication Order Number:

March, 2000 – Rev. 2 MC74HC4020A/D
 MC74HC4020A

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MAXIMUM RATINGS*

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Symbol
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Parameter Value Unit This device contains protection

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VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

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Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

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be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

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Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

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cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
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ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

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Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW tied to an appropriate logic voltage

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ÎÎÎÎÎ
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SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

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Unused outputs must be left open.
Tstg Storage Temperature Range – 65 to + 150 _C

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TL

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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Symbol
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RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ Parameter Min Max Unit

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VCC

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Vin, Vout
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DC Supply Voltage (Referenced to GND)

ÎÎ
ÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
2.0
0
6.0
VCC
V
V

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
Operating Temperature Range, All Package Types – 55 + 125 _C

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tr, tf

ÎÎÎÎ ÎÎÎ
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ÎÎÎ
Input Rise/Fall Time

ÎÎÎ
VCC = 2.0 V 0 1000 ns

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(Figure 1)

ÎÎÎÎÎ
ÎÎÎ
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
600
500
400

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Vout = 0.1V or VCC –0.1V 2.0 1.50 1.50 1.50 V
Voltage |Iout| ≤ 20µA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Vout = 0.1V or VCC – 0.1V 2.0 0.50 0.50 0.50 V
Voltage |Iout| ≤ 20µA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin =VIH or VIL |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40

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 MC74HC4020A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 µA
Current (per Package) Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 10 9.0 8.0 MHz
(Figures 1 and 4) 3.0 15 14 12
4.5 30 28 25
6.0 50 50 40
tPLH, Maximum Propagation Delay, Clock to Q1* 2.0 96 106 115 ns
tPHL (Figures 1 and 4) 3.0 63 71 88
4.5 31 36 40
6.0 25 30 35
tPHL Maximum Propagation Delay, Reset to Any Q 2.0 45 52 65 ns
(Figures 2 and 4) 3.0 30 36 40
4.5 30 35 40
6.0 26 32 35
tPLH, Maximum Propagation Delay, Qn to Qn+1 2.0 69 80 90 ns
tPHL (Figures 3 and 4) 3.0 40 45 50
4.5 17 21 28
6.0 14 15 22
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 4) 3.0 27 32 36
4.5 15 19 22
6.0 13 15 19
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] ns
VCC = 3.0 V: tP = [61.5 + 34.4 (n–1)] ns VCC = 6.0 V: tP = [24.4 + 12 (n–1)] ns

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 38 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC4020A

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
trec Minimum Recovery Time, Reset Inactive to Clock 2.0 30 40 50 ns
(Figure 2) 3.0 20 25 30
4.5 5 8 12
6.0 4 6 9
tw Minimum Pulse Width, Clock 2.0 70 80 90 ns
(Figure 1) 3.0 40 45 50
4.5 15 19 24
6.0 13 16 20
tw Minimum Pulse Width, Reset 2.0 70 80 90 ns
(Figure 2) 3.0 40 45 50
4.5 15 19 24
6.0 13 16 20
tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns
(Figure 1) 3.0 800 800 800
4.5 500 500 500
6.0 400 400 400
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

PIN DESCRIPTIONS

INPUTS OUTPUTS
Clock (Pin 10) Q1, Q4—Q14 (Pins 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3)
Negative–edge triggering clock input. A high–to–low Active–high outputs. Each Qn output divides the Clock
transition on this input advances the state of the counter. input frequency by 2N.
Reset (Pin 11)
Active–high reset. A high level applied to this input
asynchronously resets the counter to its zero state, thus
forcing all Q outputs low.

SWITCHING WAVEFORMS

tf tr VCC
VCC Clock 50%
90%
Clock 50% GND
10% trec
GND
tw tw
VCC
1/fMAX
tPLH tPHL Reset 50%
GND
90% tPHL
Q1 50%
10%
Any Q 50%
tTLH tTHL

Figure 1. Figure 2.

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 MC74HC4020A

SWITCHING WAVEFORMS (continued)

TEST
POINT

VCC
Qn OUTPUT
50%
DEVICE
GND UNDER
tPLH tPHL TEST CL*

Qn+1 50%

*Includes all probe and jig capacitance

Figure 3. Figure 4. Test Circuit

Q1 Q4 Q5 Q12 Q13 Q14

9 7 5 1 2 3

10
Clock C Q C Q C Q C Q C Q C Q

C Q C Q C Q C Q C Q C

R R

11
Reset
Q6 = Pin 4 Q9 = Pin 12 VCC = Pin 16
Q7 = Pin 6 Q10 = Pin 14 GND = Pin 8
Q8 = Pin 13 Q11 = Pin 15

Figure 5. Expanded Logic Diagram

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297
 MC74HC4020A

1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384

Clock
Reset

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q12

Q13

Q14

Figure 6. Timing Diagram

APPLICATIONS INFORMATION

Time–Base Generator feeds the HC4020A. Selecting outputs Q5, Q10, Q11, and
A 60Hz sinewave obtained through a 1.0 Megohm resistor Q12 causes a reset every 3600 clocks. The HC20 decodes the
connected directly to a standard 120 Vac power line is counter outputs, produces a single (narrow) output pulse,
applied to the input of the MC54/74HC14A, Schmitt-trigger and resets the binary counter. The resulting output frequency
inverter. The HC14A squares–up the input waveform and is 1.0 pulse/minute.

VCC VCC

1/6 of HC14A
1.0M HC4020A
13
Clock Q5
12 1.0 Pulse/Minute
1
≥20pF Q10 8 2 6 Output
120Vac 1/2 1/2
4
60Hz 10 HC20 HC20
5
Q11
9
Q12

Figure 7. Time–Base Generator

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298
MC74HC4040A

12-Stage Binary Ripple

Counter
High–Performance Silicon–Gate CMOS
The MC74C4040A is identical in pinout to the standard CMOS
MC14040. The device inputs are compatible with standard CMOS
http://onsemi.com
outputs; with pullup resistors, they are compatible with LSTTL
outputs. MARKING
This device consists of 12 master–slave flip–flops. The output of DIAGRAMS
each flip–flop feeds the next and the frequency at each output is half of 16
that of the preceding one. The state counter advances on the PDIP–16
N SUFFIX MC74HC4040AN
negative–going edge of the Clock input. Reset is asynchronous and 16 AWLYYWW
CASE 648
active–high. 1
State changes of the Q outputs do not occur simultaneously because 1
of internal ripple delays. Therefore, decoded output signals are subject 16
to decoding spikes and may have to be gated with the Clock of the SO–16
HC4040A
D SUFFIX
HC4040A for some designs. 16
CASE 751B
AWLYWW

• Output Drive Capability: 10 LSTTL Loads 1

1
• Outputs Directly Interface to CMOS, NMOS, and TTL 16

• Operating Voltage Range: 2 to 6 V TSSOP–16 HC40

• Low Input Current: 1 µA 16 DT SUFFIX 40A
ALYW
CASE 948F
• High Noise Immunity Characteristic of CMOS Devices 1

• In Compliance With JEDEC Standard No. 7A Requirements 1

• Chip Complexity: 398 FETs or 99.5 Equivalent Gates

A
WL
= Assembly Location
= Wafer Lot
YY = Year
LOGIC DIAGRAM WW = Work Week
9
Q1
7 FUNCTION TABLE
Q2
6
Q3 Clock Reset Output State
5
Q4
3 L No Charge
10 Q5
Clock 2 L Advance to Next State
Q6
4 X H All Outputs Are Low
Q7
13
Q8
12
Q9
14
Q10
15
Q11 ORDERING INFORMATION
1
Q12
Device Package Shipping
11 Pin 16 = VCC
Reset MC74HC4040AN PDIP–16 2000 / Box
Pin 8 = GND
MC74HC4040AD SOIC–16 48 / Rail
VCC Q11 Q10 Q8 Q9 Reset Clock Q1 MC74HC4040ADR2 SOIC–16 2500 / Reel
16 15 14 13 12 11 10 9 MC74HC4040ADT TSSOP–16 96 / Rail
MC74HC4040ADTR2 TSSOP–16 2500 / Reel
Pinout: 16–Lead Plastic Package
(Top View)

1 2 3 4 5 6 7 8
Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND

 Semiconductor Components Industries, LLC, 2000 299 Publication Order Number:

March, 2000 – Rev. 2 MC74HC4040A/D
 MC74HC4040A

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MAXIMUM RATINGS*

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Symbol
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ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
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ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

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ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

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ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
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cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
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ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

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Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
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ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature Range – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
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Lead Temperature, 1 mm from Case for 10 Seconds

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Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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RECOMMENDED OPERATING CONDITIONS

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Symbol Parameter Min Max Unit

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VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

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Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

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TA Operating Temperature Range, All Package Types – 55 + 125 _C

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tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 3.0 V 0 600

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VCC = 4.5 V
VCC = 6.0 V
0
0
500
400

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Vout = 0.1V or VCC –0.1V 2.0 1.50 1.50 1.50 V
Voltage |Iout| ≤ 20µA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Vout = 0.1V or VCC – 0.1V 2.0 0.50 0.50 0.50 V
Voltage |Iout| ≤ 20µA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin =VIH or VIL |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1

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 MC74HC4040A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 µA
Current (per Package) Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 10 9.0 8.0 MHz
(Figures 1 and 4) 3.0 15 14 12
4.5 30 28 25
6.0 50 45 40
tPLH, Maximum Propagation Delay, Clock to Q1* 2.0 96 106 115 ns
tPHL (Figures 1 and 4) 3.0 63 71 88
4.5 31 36 40
6.0 25 30 35
tPHL Maximum Propagation Delay, Reset to Any Q 2.0 45 52 65 ns
(Figures 2 and 4) 3.0 30 36 40
4.5 30 35 40
6.0 26 32 35
tPLH, Maximum Propagation Delay, Qn to Qn+1 2.0 69 80 90 ns
tPHL (Figures 3 and 4) 3.0 40 45 50
4.5 17 21 28
6.0 14 15 22
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 4) 3.0 27 32 36
4.5 15 19 22
6.0 13 15 19
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] ns
VCC = 3.0 V: tP = [61.5 + 34.4 (n–1)] ns VCC = 6.0V: tP = [24.4 + 12 (n–1)] ns

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 31 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC4040A

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
trec Minimum Recovery Time, Reset Inactive to Clock 2.0 30 40 50 ns
(Figure 2) 3.0 20 25 30
4.5 5 8 12
6.0 4 6 9
tw Minimum Pulse Width, Clock 2.0 70 80 90 ns
(Figure 1) 3.0 40 45 50
4.5 15 19 24
6.0 13 16 20
tw Minimum Pulse Width, Reset 2.0 70 80 90 ns
(Figure 2) 3.0 40 45 50
4.5 15 19 24
6.0 13 16 20
tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns
(Figure 1) 3.0 800 800 800
4.5 500 500 500
6.0 400 400 400
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

PIN DESCRIPTIONS

INPUTS OUTPUTS
Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)
Clock (Pin 10)
Negative–edge triggering clock input. A high–to–low Active–high outputs. Each Qn output divides the Clock
transition on this input advances the state of the counter. input frequency by 2N.

Reset (Pin 11)

Active–high reset. A high level applied to this input
asynchronously resets the counter to its zero state, thus
forcing all Q outputs low.

SWITCHING WAVEFORMS

tf tr VCC
VCC Clock 50%
90%
Clock 50% GND
10% trec
GND
tw tw
VCC
1/fMAX
tPLH tPHL Reset 50%
GND
90% tPHL
Q1 50%
10%
Any Q 50%
tTLH tTHL

Figure 1. Figure 2.

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 MC74HC4040A

SWITCHING WAVEFORMS (continued)

TEST
POINT

VCC
Qn OUTPUT
50%
DEVICE
GND UNDER
tPLH tPHL TEST CL*

Qn+1 50%

*Includes all probe and jig capacitance

Figure 3. Figure 4. Test Circuit

Q1 Q2 Q3 Q10 Q11 Q12

9 7 6 14 15 1

10
Clock C Q C Q C Q C Q C Q C Q

C Q C Q C Q C Q C Q C

R R

11
Reset
Q4 = Pin 5 Q7 = Pin 4 VCC = Pin 16
Q5 = Pin 3 Q8 = Pin 13 GND = Pin 8
Q6 = Pin 2 Q9 = Pin 12

Figure 5. Expanded Logic Diagram

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 MC74HC4040A

1 2 4 8 16 32 64 128 256 512 1024 2048 4096

Clock
Reset

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Figure 6. Timing Diagram

APPLICATIONS INFORMATION

Time–Base Generator feeds the HC4040A. Selecting outputs Q5, Q10, Q11, and
A 60Hz sinewave obtained through a 1.0 Megohm resistor Q12 causes a reset every 3600 clocks. The HC20 decodes the
connected directly to a standard 120 Vac power line is counter outputs, produces a single (narrow) output pulse,
applied to the input of the MC54/74HC14A, Schmitt-trigger and resets the binary counter. The resulting output frequency
inverter. The HC14A squares–up the input waveform and is 1.0 pulse/minute.

VCC VCC

1/6 of HC14A
1.0M HC4040A
13
Clock Q5
12 1.0 Pulse/Minute
1
≥20pF Q10 8 2 6 Output
120Vac 1/2 1/2
4
60Hz 10 HC20 HC20
5
Q11
9
Q12

Figure 7. Time–Base Generator

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MC74HC4046A

Phase-Locked Loop
High–Performance Silicon–Gate CMOS
The MC74HC4046A is similar in function to the MC14046 Metal
gate CMOS device. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs. http://onsemi.com
The HC4046A phase–locked loop contains three phase
comparators, a voltage–controlled oscillator (VCO) and unity gain MARKING
op–amp DEMOUT. The comparators have two common signal inputs, DIAGRAMS
COMP IN, and SIG IN. Input SIG IN and COMP IN can be used directly 16
PDIP–16
coupled to large voltage signals, or indirectly coupled (with a series MC74HC4046AN
N SUFFIX
capacitor to small voltage signals). The self–bias circuit adjusts small 16
CASE 648
AWLYYWW
voltage signals in the linear region of the amplifier. Phase comparator 1
1
1 (an exclusive OR gate) provides a digital error signal PC1 OUT and 16
maintains 90 degrees phase shift at the center frequency between SO–16
SIG IN and COMP IN signals (both at 50% duty cycle). Phase HC4046A
D SUFFIX
16 AWLYWW
comparator 2 (with leading–edge sensing logic) provides digital error CASE 751B
1
signals PC2 OUT and PCP OUT and maintains a 0 degree phase shift 1
between SIG IN and COMP IN signals (duty cycle is immaterial). The 16
linear VCO produces an output signal VCOOUT whose frequency is HC40
TSSOP–16
determined by the voltage of input VCO IN signal and the capacitor 16 DT SUFFIX 46A
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain CASE 948F ALYW
1
op–amp output DEMOUT with an external resistor is used where the
1
VCO IN signal is needed but no loading can be tolerated. The inhibit 16
input, when high, disables the VCO and all op–amps to minimize
SOEIAJ–16
standby power consumption. F SUFFIX 74HC4046B
Applications include FM and FSK modulation and demodulation, 16 AWLYWW
CASE 966
frequency synthesis and multiplication, frequency discrimination, 1
1
tone decoding, data synchronization and conditioning,
voltage–to–frequency conversion and motor speed control. A = Assembly Location
WL = Wafer Lot
• Output Drive Capability: 10 LSTTL Loads YY = Year
• Low Power Consumption Characteristic of CMOS Devices WW = Work Week
• Operating Speeds Similar to LSTTL
• Wide Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 µA Maximum (except SIGIN and COMPIN) ORDERING INFORMATION
• In Compliance with the Requirements Defined by JEDEC Standard Device Package Shipping
No. 7A
MC74HC4046AN PDIP–16 2000 / Box
• Low Quiescent Current: 80 µA Maximum (VCO disabled)
MC74HC4046AD SOIC–16 48 / Rail
• High Noise Immunity Characteristic of CMOS Devices
MC74HC4046ADR2 SOIC–16 2500 / Reel
• Diode Protection on all Inputs
MC74HC4046AF SOIC–EIAJ See Note 1.
• Chip Complexity: 279 FETs or 70 Equivalent Gates
MC74HC4046AFEL SOIC–EIAJ See Note 1.
1. For ordering information on the EIAJ version of the
SOIC packages, please contact your local ON
Semiconductor representative.

 Semiconductor Components Industries, LLC, 2000 305 Publication Order Number:

March, 2000 – Rev. 7 MC74HC4046A/D
 MC74HC4046A

Pin No. Symbol Name and Function

1 PCPOUT Phase Comparator Pulse Output PIN ASSIGNMENT
2 PC1OUT Phase Comparator 1 Output
3 COMPIN Comparator Input PCPout 1 16 VCC
4 VCOOUT VCO Output PC1out 2 15 PC3out
5 INH Inhibit Input
6 C1A Capacitor C1 Connection A COMPin 3 14 SIGin
7 C1B Capacitor C1 Connection B VCOout 4 13 PC2out
8 GND Ground (0 V) VSS
9 VCOIN VCO Input INH 5 12 R2
10 DEMOUT Demodulator Output C1A 6 11 R1
11 R1 Resistor R1 Connection
12 R2 Resistor R2 Connection C1B 7 10 DEMout
13 PC2OUT Phase Comparator 2 Output
GND 8 9 VCOin
14 SIGIN Signal Input
15 PC3OUT Phase Comparator 3 Output
16 VCC Positive Supply Voltage

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MAXIMUM RATINGS*

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Symbol Parameter Value Unit This device contains protection
circuitry to guard against damage

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VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
due to high static voltages or electric

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Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V fields. However, precautions must
be taken to avoid applications of any

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Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated
± 20

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Iin DC Input Current, per Pin mA voltages to this high–impedance cir-
cuit. For proper operation, Vin and
± 25

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Iout DC Output Current, per Pin mA
Vout should be constrained to the
± 50 v
range GND (Vin or Vout) VCC. v
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ICC DC Supply Current, VCC and GND Pins mA
Unused inputs must always be

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PD Power Dissipation in Still Air Plastic DIP† 750 mW tied to an appropriate logic voltage
SOIC Package† 500 level (e.g., either GND or VCC).

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Tstg

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TL ÎÎÎ
Storage Temperature

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Lead Temperature, 1 mm from Case for 10 Seconds
– 65 to + 150 _C
_C
Unused outputs must be left open.

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Plastic DIP and SOIC Package† 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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RECOMMENDED OPERATING CONDITIONS

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Symbol Parameter Min Max Unit

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VCC DC Supply Voltage (Referenced to GND) 3.0 6.0 V

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VCC DC Supply Voltage (Referenced to GND) NON–VCO 2.0 6.0 V

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Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

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TA Operating Temperature, All Package Types – 55 + 125 _C

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tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Pin 5) VCC = 4.5 V 0 500

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ÎÎÎ VCC = 6.0 V 0 400

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[Phase Comparator Section]

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC – 55 to
Symbol Parameter Test Conditions Volts 25_C ≤ 85°C ≤ 125°C Unit
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
Voltage DC Coupled |Iout| ≤ 20 µA 4.5 3.15 3.15 3.15
SIGIN, COMPIN 6.0 4.2 4.2 4.2
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
Voltage DC Coupled |Iout| ≤ 20 µA 4.5 1.35 1.35 1.35
SIGIN, COMPIN 6.0 1.8 1.8 1.8
VOH Minimum High–Level Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Output Voltage |Iout| ≤ 20 µA 4.5 4.4 4.4 4.4
PCPOUT, PCnOUT 6.0 5.9 5.9 5.9
Vin = VIH or VIL
|Iout| ≤ 4.0 mA 4.5 3.98 3.84 3.7
|Iout| ≤ 5.2 mA 6.0 5.48 5.34 5.2
(continued)

[Phase Comparator Section]

DC ELECTRICAL CHARACTERISTICS – continued (Voltages Referenced to GND)
Guaranteed Limit
VCC – 55 to
Symbol Parameter Test Conditions Volts 25_C ≤ 85°C ≤ 125°C Unit
VOL Maximum Low–Level Vout = 0.1 V or VCC – 0.1 V 2.0 0.1 0.1 0.1 V
Output Voltage Qa–Qh |Iout| ≤ 20 µA 4.5 0.1 0.1 0.1
PCPOUT, PCnOUT 6.0 0.1 0.1 0.1
Vin = VIH or VIL
|Iout| ≤ 4.0 mA 4.5 0.26 0.33 0.4
|Iout| ≤ 5.2 mA 6.0 0.26 0.33 0.4
Iin Maximum Input Leakage Cur- Vin = VCC or GND 2.0 ± 3.0 ± 4.0 ± 5.0 µA
rent 3.0 ± 7.0 ± 9.0 ± 11.0
SIGIN, COMPIN 4.5 ± 18.0 ± 23.0 ± 27.0
6.0 ± 30.0 ± 38.0 ± 45.0

IOZ Maximum Three–State Output in High–Impedance State 6.0 ± 0.5 ± 5.0 ± 10 µA

Leakage Current Vin = VIH or VIL
PC2OUT Vout = VCC or GND
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4.0 40 160 µA
Current (per Package) |Iout| = 0 µA
(VCO disabled)
Pins 3, 5 and 14 at VCC
Pin 9 at GND; Input Leakage
at
Pins 3 and 14 to be excluded
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
[Phase Comparator Section]
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC
Symbol Parameter Volts – 55 to 25_C ≤ 85°C ≤ 125°C Unit
tPLH, Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT 2.0 175 220 265 ns
tPHL (Figure 1) 4.5 35 44 53
6.0 30 37 45
tPLH, Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT 2.0 340 425 510 ns
tPHL (Figure 1) 4.5 68 85 102
6.0 58 72 87

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 MC74HC4046A

[Phase Comparator Section]

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
tPLH, Maximum Propagation Delay, SIGIN/COMPIN to PC3OUT 2.0 270 340 405 ns
tPHL (Figure 1) 4.5 54 68 81
6.0 46 58 69
tPLZ, Maximum Propagation Delay, SIGIN/COMPIN Output 2.0 200 250 300 ns
tPHZ Disable Time to PC2OUT (Figures 2 and 3) 4.5 40 50 60
6.0 34 43 51
tPZH, Maximum Propagation Delay, SIGIN/COMPIN Output 2.0 230 290 345 ns
tPZL Enable Time to PC2OUT (Figures 2 and 3) 4.5 46 58 69
6.0 39 49 59
tTLH, Maximum Output Transition Time 2.0 75 95 110 ns
tTHL (Figure 1) 4.5 15 19 22
6.0 13 16 19
[VCO Section]
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC – 55 to
Symbol Parameter Test Conditions Volts 25_C ≤ 85°C ≤ 125°C Unit
VIH Minimum High–Level Vout = 0.1 V or VCC – 0.1 V 3.0 2.1 2.1 2.1 V
Input Voltage |Iout| ≤ 20 µA 4.5 3.15 3.15 3.15
INH 6.0 4.2 4.2 4.2
VIL Maximum Low–Level Vout = 0.1 V or VCC – 0.1 V 3.0 0.90 0.9 0.9 V
Input Voltage |Iout| ≤ 20 µA 4.5 1.35 1.35 1.35
INH 6.0 1.8 1.8 1.8
VOH Minimum High–Level Vin = VIH or VIL 3.0 1.9 1.9 1.9 V
Output Voltage |Iout| ≤ 20 µA 4.5 4.4 4.4 4.4
VCOOUT 6.0 5.9 5.9 5.9
Vin = VIH or VIL
|Iout| ≤ 4.0 mA 4.5 3.98 3.84 3.7
|Iout| ≤ 5.2 mA 6.0 5.48 5.34 5.2
VOL Maximum Low–Level Vout = 0.1 V or VCC – 0.1 V 3.0 0.1 0.1 0.1 V
Output Voltage |Iout| ≤ 20 µA 4.5 0.1 0.1 0.1
VCOOUT 6.0 0.1 0.1 0.1
Vin = VIH or VIL
|Iout| ≤ 4.0 mA 4.5 0.26 0.33 0.4
|Iout| ≤ 5.2 mA 6.0 0.26 0.33 0.4
Iin Maximum Input Vin = VCC or GND 6.0 0.1 1.0 1.0 µA
Leakage Current
INH, VCOIN
Min Max Min Max Min Max

VVCOIN Operating Voltage Range at INH = VIL 3.0 0.1 1.0 0.1 1.0 0.1 1.0 V
VCOIN over the range 4.5 0.1 2.5 0.1 2.5 0.1 2.5
specified for R1; For 6.0 0.1 4.0 0.1 4.0 0.1 4.0
linearity see Fig. 15A,
Parallel value of R1 and R2
should be > 2.7 kΩ
R1 Resistor Range 3.0 3.0 300 3.0 300 3.0 300 kΩ
4.5 3.0 300 3.0 300 3.0 300
6.0 3.0 300 3.0 300 3.0 300
R2 3.0 3.0 300 3.0 300 3.0 300
4.5 3.0 300 3.0 300 3.0 300
6.0 3.0 300 3.0 300 3.0 300
C1 Capacitor Range 3.0 40 No pF
4.5 40 Limit
6.0 40

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 MC74HC4046A

[VCO Section]
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit

– 55 to 25_C ≤ 85°C ≤ 125°C

VCC
Symbol Parameter Volts Min Max Min Max Min Max Unit
∆f/T Frequency Stability with 3.0 %/K
Temperature Changes 4.5
(Figure 13A, B, C) 6.0
fo VCO Center Frequency 3.0 3 MHz
(Duty Factor = 50%) 4.5 11
(Figure 14A, B, C, D) 6.0 13
∆fVCO VCO Frequency Linearity 3.0 See Figures 15A, B, C %
4.5
6.0
∂ VCO Duty Factor at VCOOUT 3.0 Typical 50% %
4.5
6.0

[Demodulator Section]
DC ELECTRICAL CHARACTERISTICS
Guaranteed Limit

– 55 to 25_C ≤ 85°C ≤ 125°C

VCC
Symbol Parameter Test Conditions Volts Min Max Min Max Min Max Unit
RS Resistor Range At RS > 300 kΩ the 3.0 50 300 kΩ
Leakage Current can 4.5 50 300
Influence VDEMOUT 6.0 50 300
VOFF Offset Voltage Vi = VVCOIN = 1/2 VCC; 3.0 See Figure 12 mV
VCOIN to VDEMOUT Values taken over RS 4.5
Range. 6.0
RD Dynamic Output VDEMOUT = 1/2 VCC 3.0 Typical 25 Ω Ω
Resistance at DEMOUT 4.5
6.0

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 MC74HC4046A

SWITCHING WAVEFORMS

VCC
VCC SIGIN
SIGIN, COMPIN INPUT 50%
INPUTS 50% GND
GND VCC
tPHL tPLH COMPIN
50%
INPUT
90% GND
PCPOUT, PC1OUT tPHZ
50% tPZH
PC3OUT VOH
OUTPUTS PC2OUT 90%
10% 50%
OUTPUT HIGH
tTHL tTLH IMPEDANCE

Figure 1. Figure 2.

VCC
SIGIN
INPUT 50% TEST POINT
GND
OUTPUT
VCC DEVICE
COMPIN UNDER
50% TEST CL*
INPUT
GND
tPLZ
tPZL
HIGH
IMPEDANCE
PC2OUT 50%
*INCLUDES ALL PROBE AND JIG CAPACITANCE
OUTPUT 10% VOL

Figure 3. Figure 4. Test Circuit

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 MC74HC4046A

DETAILED CIRCUIT DESCRIPTION up to Vref of the comparators, the oscillator logic flips the
capacitor which causes the mirror to charge the opposite side
Voltage Controlled Oscillator/Demodulator Output of the capacitor. The output from the internal logic is then
The VCO requires two or three external components to taken to VCO output (Pin 4).
operate. These are R1, R2, C1. Resistor R1 and Capacitor C1 The input to the VCO is a very high impedance CMOS
are selected to determine the center frequency of the VCO input and thus will not load down the loop filter, easing the
(see typical performance curves Figure 14). R2 can be used filters design. In order to make signals at the VCO input
to set the offset frequency with 0 volts at VCO input. For accessible without degrading the loop performance, the
example, if R2 is decreased, the offset frequency is VCO input voltage is buffered through a unity gain Op–amp
increased. If R2 is omitted the VCO range is from 0 Hz. The to Demod Output. This Op–amp can drive loads of 50K
effect of R2 is shown in Figure 24, typical performance ohms or more and provides no loading effects to the VCO
curves. By increasing the value of R2 the lock range of the input voltage (see Figure 12).
PLL is increased and the gain (volts/Hz) is decreased. Thus, An inhibit input is provided to allow disabling of the VCO
for a narrow lock range, large swings on the VCO input will and all Op–amps (see Figure 5). This is useful if the internal
cause less frequency variation. VCO is not being used. A logic high on inhibit disables the
Internally, the resistors set a current in a current mirror, as VCO and all Op–amps, minimizing standby power
shown in Figure 5. The mirrored current drives one side of consumption.
the capacitor. Once the voltage across the capacitor charges

VREF
+ I1
_
12

R2 CURRENT
MIRROR
I1 + I2 = I3

I2 4 VCOOUT
VCOIN 9 +
_
11

R1 I3

DEMODOUT 10 +
_

C1
(EXTERNAL)
6 7

Vref

+ +
–

INH 5

Figure 5. Logic Diagram for VCO

The output of the VCO is a standard high speed CMOS feed external prescalers (counters) to enable frequency
output with an equivalent LS–TTL fan out of 10. The VCO synthesis.
output is approximately a square wave. This output can
either directly feed the COMPIN of the phase comparators or

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 MC74HC4046A

Phase Comparators outputs of these comparators are essentially standard 74HC

All three phase comparators have two inputs, SIGIN and outputs (comparator 2 is TRI–STATEABLE). In normal
COMPIN. The SIGIN and COMPIN have a special DC bias operation VCC and ground voltage levels are fed to the loop
network that enables AC coupling of input signals. If the filter. This differs from some phase detectors which supply
signals are not AC coupled, standard 74HC input levels are a current to the loop filter and should be considered in the
required. Both input structures are shown in Figure 6. The design. (The MC14046 also provides a voltage).

VCC
VCC

SIGIN
14 PC2OUT
13

VCC

COMPIN
3 PCPOUT
1

PC3OUT
15

PC1OUT
2

Figure 6. Logic Diagram for Phase Comparators

Phase Comparator 1 two input signals must be in phase. When the input
This comparator is a simple XOR gate similar to the frequency is fmax, the VCO input must be VCC and the phase
74HC86. Its operation is similar to an overdriven balanced detector inputs must be 180 degrees out of phase.
modulator. To maximize lock range the input frequencies
must have a 50% duty cycle. Typical input and output
waveforms are shown in Figure 7. The output of the phase SIGIN
detector feeds the loop filter which averages the output
COMPIN
voltage. The frequency range upon which the PLL will lock
onto if initially out of lock is defined as the capture range. PC1OUT
The capture range for phase detector 1 is dependent on the VCC
VCOIN
loop filter design. The capture range can be as large as the GND
lock range, which is equal to the VCO frequency range.
To see how the detector operates, refer to Figure 7. When
Figure 7. Typical Waveforms for PLL Using
two square wave signals are applied to this comparator, an
Phase Comparator 1
output waveform (whose duty cycle is dependent on the
phase difference between the two signals) results. As the The XOR is more susceptible to locking onto harmonics
phase difference increases, the output duty cycle increases of the SIGIN than the digital phase detector 2. For instance,
and the voltage after the loop filter increases. In order to a signal 2 times the VCO frequency results in the same
achieve lock when the PLL input frequency increases, the output duty cycle as a signal equal to the VCO frequency.
VCO input voltage must increase and the phase difference The difference is that the output frequency of the 2f example
between COMPIN and SIGIN will increase. At an input is twice that of the other example. The loop filter and VCO
frequency equal to fmin, the VCO input is at 0 V. This range should be designed to prevent locking on to
requires the phase detector output to be grounded; hence, the harmonics.

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Phase Comparator 2 and will cause the output to go high until the VCO leading
This detector is a digital memory network. It consists of edge is seen, potentially for an entire SIGIN period. This
four flip–flops and some gating logic, a three state output would cause the VCO to speed up during that time. When
and a phase pulse output as shown in Figure 6. This using PC1, the output of that phase detector would be
comparator acts only on the positive edges of the input disturbed for only the short duration of the noise spike and
signals and is independent of duty cycle. would cause less upset.
Phase comparator 2 operates in such a way as to force the
PLL into lock with 0 phase difference between the VCO Phase Comparator 3
output and the signal input positive waveform edges. Figure This is a positive edge–triggered sequential phase
8 shows some typical loop waveforms. First assume that detector using an RS flip–flop as shown in Figure 6. When
SIGIN is leading the COMPIN. This means that the VCO’s the PLL is using this comparator, the loop is controlled by
frequency must be increased to bring its leading edge into positive signal transitions and the duty factors of SIGIN and
proper phase alignment. Thus the phase detector 2 output is COMP IN
set high. This will cause the loop filter to charge up the VCO are not important. It has some similar characteristics to the
input, increasing the VCO frequency. Once the leading edge edge sensitive comparator. To see how this detector works,
of the COMPIN is detected, the output goes TRI–STATE assume input pulses are applied to the SIG IN and
holding the VCO input at the loop filter voltage. If the VCO COMP IN ’s as shown in Figure 9. When the SIGIN leads the
still lags the SIGIN then the phase detector will again charge COMPIN, the flop is set. This will charge the loop filter and
up the VCO input for the time between the leading edges of cause the VCO to speed up, bringing the comparator into
both waveforms. phase with the SIG IN. The phase angle between SIGIN and
If the VCO leads the SIGIN then when the leading edge of COMP IN varies from 0° to 360° and is 180° at fo. The
the VCO is seen; the output of the phase comparator goes voltage swing for PC3 is greater than for PC2 but
low. This discharges the loop filter until the leading edge of consequently has more ripple in the signal to the VCO.
the SIGIN is detected at which time the output disables itself When no SIG IN is present the VCO will be forced to fmax as
again. This has the effect of slowing down the VCO to again opposed to fmin when PC2 is used.
make the rising edges of both waveforms coincidental. The operating characteristics of all three phase
When the PLL is out of lock, the VCO will be running comparators should be compared to the requirements of the
either slower or faster than the SIGIN. If it is running slower system design and the appropriate one should be used.
the phase detector will see more SIGIN rising edges and so
the output of the phase comparator will be high a majority SIGIN
of the time, raising the VCO’s frequency. Conversely, if the
VCO is running faster than the SIGIN, the output of the COMPIN
VCC
PC2OUT
detector will be low most of the time and the VCO’s output
GND
frequency will be decreased. HIGH IMPEDANCE OFF–STATE
As one can see, when the PLL is locked, the output of VCOIN
phase comparator 2 will be disabled except for minor PCPOUT
corrections at the leading edge of the waveforms. When PC2
is TRI–STATED, the PCP output is high. This output can be
Figure 8. Typical Waveforms for PLL Using
used to determine when the PLL is in the locked condition. Phase Comparator 2
This detector has several interesting characteristics. Over
the entire VCO frequency range there is no phase difference
between the COMPIN and the SIGIN. The lock range of the SIGIN
PLL is the same as the capture range. Minimal power was COMPIN
consumed in the loop filter since in lock the detector output
is a high impedance. When no SIGIN is present, the detector PC3OUT
VCC
VCOIN
will see only VCO leading edges, so the comparator output
GND
will stay low, forcing the VCO to fmin.
Phase comparator 2 is more susceptible to noise, causing
the PLL to unlock. If a noise pulse is seen on the SIGIN, the Figure 9. Typical Waveform for PLL Using
comparator treats it as another positive edge of the SIGIN Phase Comparator 3

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 MC74HC4046A

800 VCC=6.0 V
VCC=3.0 V
4.0
VCC=4.5 V

VCC=3.0 V
R I = (k Ω )

I I ( µ A)
400
VCC=4.5 V 0

VCC=6.0 V

0
1/2 VCC–1.0 V 1/2 VCC 1/2 VCC+1.0 V –4.0
1/2VCC – 500 mV 1/2 VCC 1/2 VCC + 500 mV
VI (V)
VI (V)

Figure 10. Input Resistance at SIGIN, COMPIN with Figure 11. Input Current at SIGIN, COMPIN with
∆VI = 1.0 V at Self–Bias Point ∆VI = 500 mV at Self–Bias Point

DEMOD OUT
15
6.0
R1=3.0 kΩ
10
FREQUENCY STABILITY (%)
R1=100 kΩ
5.0 R1=300 kΩ
VCC=6.0 V RS=300 k
OUT

VCC=6.0 V RS=50 k 0 R1=100 kΩ

VDEM

VCC=4.5 V RS=300 k R1=300 kΩ

–5.0
VCC=4.5 V RS=50 k

–10 VCC = 3.0 V

VCC=3.0 V RS=300 k
R1=3.0 kΩ C1 = 100 pF; R2 = ∞; VVCOIN=1/3 VCC
VCC=3.0 V RS=50 k
–15
–100 –50 0 50 100 150
0
0 3.0 6.0 AMBIENT TEMPERATURE (°C)
VCOIN (V)
Figure 12. Offset Voltage at Demodulator Output as Figure 13A. Frequency Stability versus Ambient
a Function of VCOIN and RS Temperature: VCC = 3.0 V

15 R1=3.0 kΩ
10
R1=3.0 kΩ
R1=300 kΩ 8.0 R1=300 kΩ
FREQUENCY STABILITY (%)

10
FREQUENCY STABILITY (%)

R1=100 kΩ 6.0 R1=100 kΩ

5.0 4.0
2.0
0 0
–2.0
–5.0
–4.0
–6.0
–10 VCC = 4.5 V VCC = 6.0 V
C1 = 100 pF; R2 = ∞; VVCOIN = 1/2 VCC –8.0 C1 = 100 pF; R2 = ∞; VVCOIN=1/2 VCC
–15 –10
–100 –50 0 50 100 150 –100 –50 0 50 100 150
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)

Figure 13B. Frequency Stability versus Ambient Figure 13C. Frequency Stability versus Ambient
Temperature: VCC = 4.5 V Temperature: VCC = 6.0 V

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23 70
VCC = 4.5 V VCC = 6.0 V
21 VCC = 6.0 V 60
19
50 VCC = 3.0 V
f VCO(MHz)

17 VCC = 4.5 V

f VCO (KHz)
40
15
30
13
VCC = 3.0 V 20
11
R1 = 3.0 kΩ R1 = 3.0 kΩ
9 10
C1 = 39 pF C1 = 0.1 µF
7.0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VVCOIN (V) VVCOIN (V)

Figure 14A. VCO Frequency (fVCO) as a Function Figure 14B. VCO Frequency (fVCO) as a Function
of the VCO Input Voltage (VVCOIN) of the VCO Input Voltage (VVCOIN)

2.0 1.0
VCC = 6.0 V
VCC = 4.5 V 0.9
0.8 VCC = 4.5 V
VCC = 6.0 V
VCC = 3.0 V 0.7
VCC = 3.0 V
f VCO (KHz)
f VCO(MHz)

0.6
1.0 0.5
0.4
0.3

R1 = 300 kΩ 0.2
R1 = 300 kΩ
C1 = 39 pF 0.1 C1 = 0.1 µF
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VVCOIN (V) VVCOIN (V)

Figure 14C. VCO Frequency (fVCO) as a Function Figure 14D. VCO Frequency (fVCO) as a Function
of the VCO Input Voltage (VVCOIN) of the VCO Input Voltage (VVCOIN)

2.0
VCC=
C1 = 1.0 µF
4.5 V
1.0 f2
6.0 V
∆ f VCO (%)

f0
3.0 V f0′
0
4.5 V f1

6.0 V
–1.0

R2 = ∞; ∆V = 0.5 V
3.0 V C1 = 39 pF
–2.0
MIN 1/2 VCC MAX
100 101 102 103
R1 (kΩ) ∆V = 0.5 V OVER THE VCC RANGE:
FOR VCO LINEARITY
f0′ = (f1 + f2) / 2
LINEARITY = (f0′ – f0) / f0′) x 100%

Figure 15A. Frequency Linearity versus Figure 15B. Definition of VCO Frequency Linearity
R1, C1 and VCC

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 MC74HC4046A

106 CL = 50 pF; R2 = ∞; VVCOIN = 1/2 VCC FOR VCC = 4.5 V AND 6.0 V;
106 CL = 50 pF; R1 = ∞; VVCOIN = 0 V; Tamb = 25°C
VVCOIN = 1/3 VCC FOR VCC = 3.0 V; Tamb = 25°C

105 105
PR1 ( µW)

PR2 ( µW)
VCC = 6.0 V, C1 = 40 pF

VCC = 6.0 V, C1 = 1.0 µF VCC = 6.0 V, C1 = 40 pF

VCC = 6.0 V, C1 = 1.0 µF

104 VCC = 4.5 V, C1 = 40 pF 104
VCC = 4.5 V, C1 = 1.0 µF
VCC = 4.5 V, C1 = 40 pF
VCC = 3.0 V, C1 = 40 pF VCC = 4.5 V, C1 = 1.0 µF

VCC = 3.0 V, C1 = 1.0 µF VCC = 3.0 V, C1 = 1.0 µF

VCC = 3.0 V, C1 = 40 pF
103 103
100 101 102 103 100 101 102 103
R1 (kΩ) R2 (kΩ)

Figure 16. Power Dissipation versus R1 Figure 17. Power Dissipation versus R2

108 VCC = INH = GND; Tamb = 25°C; R2 = ∞; VVCOIN = 1/3 VCC

103 6.0 V
R1 = R2 = ∞; Tamb = 25°C
4.5 V
107 3.0 V
6.0 V
4.5 V
106 3.0 V
PDEM ( µ W)

102 6.0 V
(Hz)

4.5 V
3.0 V
105
VCO

VCC=6.0 V
R1=3.0 kΩ
f

VCC=4.5 V
101 104

VCC=3.0 V R1=100 kΩ
103
R1=300 kΩ
100 102
101 102 103 101 102 103 104 105 106
RS (kΩ) C1 (pF)

Figure 18. DC Power Dissipation of Figure 19. VCO Center Frequency versus C1
Demodulator versus RS

108 108
VCC = R1 = ∞; VVCOIN = 1/2 VCC FOR VCC = 4.5 V AND 6.0 V;
6.0 V VVCOIN = 1/3 VCC FOR VCC = 3.0 V; INH = GND; Tamb = 25°C
107 4.5 V VCC = 4.5 V; R2 = ∞
3.0 V 107
6.0 V
106 4.5 V
3.0 V
106
2 fL (Hz)
off (Hz)

6.0 V
105 4.5 V
3.0 V
105
f

104 R2=3.0 kΩ

103 104
R2=100 kΩ

102 R2=300 kΩ 103

101 102
101 102 103 104 105 106 10–7 10–6 10–5 10–4 10–3 10–2 10–1
C1 (pF) R1C1
Figure 20. Frequency Offset versus C1 Figure 21. Typical Frequency Lock Range (2fL)
versus R1C1

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20 14
R1=3.0 kΩ
C1=39 pF
R1=10 kΩ 12
15
10
R1=20 kΩ
FREQ. (MHz)

FREQ. (MHz)
R1=30 kΩ
8.0
10 6.0
R1=3 kΩ
R1=40 kΩ
R1=10 kΩ
R1=20 kΩ
R1=50 kΩ
4.0 R1=30 kΩ
R1=40 kΩ
5.0 2.0 R1=50 kΩ
R1=100 kΩ
R1=100 kΩ
0 R1=300 kΩ
C1=39 pF R1=300 kΩ
0 –2.0
1.0 101 102 103 104 105 100 101 102 103 104 105 106
R2 ( kΩ) R2 ( kΩ)
Figure 22. R2 versus fmax Figure 23. R2 versus fmin

20
C1=39 pF

R1=10 kΩ
2f L (MHz)

R1=3.0 kΩ
R1=20 kΩ

10 R1=30 kΩ

R1=40 kΩ
R1=50 kΩ

R1=100 kΩ

R1=300 kΩ

0
1.0 101 102 103 104 105
R2 ( kΩ)

Figure 24. R2 versus Frequency Lock Range (2fL)

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APPLICATION INFORMATION
The following information is a guide for approximate values of R1, R2, and C1. Figures 19, 20, and 21 should be used as
references as indicated below, also the values of R1, R2, and C1 should not violate the Maximum values indicated in the DC
ELECTRICAL CHARACTERISTICS tables.

Phase Comparator 1 Phase Comparator 2 Phase Comparator 3

R2 = ∞ R2 0R R2 = ∞ R2 0R R2 = ∞ R2 0R
• Given f0 • Given f0 and fL • Given fmax and f0 • Given f0 and fL • Given fmax and f0 • Given f0 and fL
• Use f0 with • Calculate fmin • Determine the • Calculate fmin • Determine the • Calculate fmin:
Figure 19 to fmin = f0–fL value of R1 and fmin = f0–fL value of R1 and fmin = f0–fL
determine R1 and • Determine values C1 using Figure • Determine values C1 using Figure • Determine values
C1. of C1 and R2 from 19 and use Figure of C1 and R2 from 19 and Figure 21 of C1 and R2 from
(see Figure 23 for Figure 20. 21 to obtain 2fL Figure 20. to obtain 2fL and Figure 20.
characteristics of and then use this then use this to
• Determine R1–C1 to calculate fmin. • Determine R1–C1 calculate fmin. • Determine R1–C1
the VCO operation) from Figure 21. from Figure 21. from Figure 21.
• Calculate value of • Calculate value of • Calculate value of
R1 from the value R1 from the value R1 from the value
of C1 and the of C1 and the of C1 and the
product of R1C1 product of R1C1 product of R1C1
from Figure 21. from Figure 21. from Figure 21.
(see Figure 24 for (see Figure 24 for (see Figure 24 for
characteristics of characteristics of characteristics of
the VCO operation) the VCO operation) the VCO operation)

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MC74HC4051A,
MC74HC4052A,
MC74HC4053A

Analog Multiplexers /
Demultiplexers
High–Performance Silicon–Gate CMOS http://onsemi.com

MARKING
The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize DIAGRAMS
silicon–gate CMOS technology to achieve fast propagation delays,
16
low ON resistances, and low OFF leakage currents. These analog
PDIP–16
multiplexers/demultiplexers control analog voltages that may vary N SUFFIX HC405xAN
across the complete power supply range (from VCC to VEE). 16 AWLYYWW
CASE 648
The HC4051A, HC4052A and HC4053A are identical in pinout to 1
1
the metal–gate MC14051AB, MC14052AB and MC14053AB. The 16
Channel–Select inputs determine which one of the Analog SO–16
Inputs/Outputs is to be connected, by means of an analog switch, to the HC405xAD
D SUFFIX
16 AWLYYWW
Common Output/Input. When the Enable pin is HIGH, all analog CASE 751B
1
switches are turned off. 1
The Channel–Select and Enable inputs are compatible with standard 16
CMOS outputs; with pullup resistors they are compatible with LSTTL SO–16 WIDE
outputs. HC405xA
16 DW SUFFIX
AWLYWW
These devices have been designed so that the ON resistance (Ron) is CASE 751G
more linear over input voltage than Ron of metal–gate CMOS analog 1 1
switches. 16
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HC4852A. TSSOP–16 HC40
5xA
• Fast Switching and Propagation Speeds 16 DT SUFFIX
CASE 948F ALYW
• Low Crosstalk Between Switches 1
1
• Diode Protection on All Inputs/Outputs 16
• Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V SOEIAJ–16
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V 16
F SUFFIX 74HC405xA
ALYW
• Improved Linearity and Lower ON Resistance Than Metal–Gate 1
CASE 966

Counterparts 1
• Low Noise A = Assembly Location
• In Compliance With the Requirements of JEDEC Standard No. 7A WL = Wafer Lot
YY = Year
• Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates WW = Work Week
HC4052A — 168 FETs or 42 Equivalent Gates
HC4053A — 156 FETs or 39 Equivalent Gates
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 331 of this data sheet.

 Semiconductor Components Industries, LLC, 2000 319 Publication Order Number:

March, 2000 – Rev. 1 MC74HC4051A/D
 MC74HC4051A, MC74HC4052A, MC74HC4053A

FUNCTION TABLE – MC74HC4051A

LOGIC DIAGRAM Control Inputs
MC74HC4051A Select
Single–Pole, 8–Position Plus Common Off Enable C B A ON Channels

13
L L L L X0
X0 L L L H X1
14
X1 L L H L X2
15 3 COMMON L L H H X3
X2 X
ANALOG 12 OUTPUT/ L H L L X4
INPUTS/ X3 MULTIPLEXER/ INPUT L H L H X5
OUTPUTS X4 1 DEMULTIPLEXER
L H H L X6
5
X5 L H H H X7
2 H X X X NONE
X6
4
X7 X = Don’t Care
11
A
CHANNEL 10
SELECT B Pinout: MC74HC4051A (Top View)
INPUTS 9 VCC X2 X1 X0 X3 A B C
C
6
ENABLE 16 15 14 13 12 11 10 9
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND

1 2 3 4 5 6 7 8
X4 X6 X X7 X5 Enable VEE GND

FUNCTION TABLE – MC74HC4052A

LOGIC DIAGRAM Control Inputs
MC74HC4052A
Select
Double–Pole, 4–Position Plus Common Off
Enable B A ON Channels
12
X0 L L L Y0 X0
14
X1 13 L L H Y1 X1
15 X SWITCH X
X2 L H L Y2 X2
11 L H H Y3 X3
X3
ANALOG COMMON H X X NONE
INPUTS/OUTPUTS 1 OUTPUTS/INPUTS
Y0 X = Don’t Care
5 3
Y1 Y SWITCH Y
2
Y2
4
Y3 Pinout: MC74HC4052A (Top View)
10
CHANNEL-SELECT A VCC X2 X1 X X0 X3 A B
9 PIN 16 = VCC
INPUTS B
PIN 7 = VEE 16 15 14 13 12 11 10 9
PIN 8 = GND
6
ENABLE

1 2 3 4 5 6 7 8
Y0 Y2 Y Y3 Y1 Enable VEE GND

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 MC74HC4051A, MC74HC4052A, MC74HC4053A

FUNCTION TABLE – MC74HC4053A

Control Inputs
LOGIC DIAGRAM
MC74HC4053A Select
Triple Single–Pole, Double–Position Plus Common Off Enable C B A ON Channels
L L L L Z0 Y0 X0
12 L L L H Z0 Y0 X1
X0 14
13 X SWITCH X L L H L Z0 Y1 X0
X1 L L H H Z0 Y1 X1
L H L L Z1 Y0 X0
2 L H L H Z1 Y0 X1
Y0 15 COMMON
ANALOG 1 Y SWITCH Y L H H L Z1 Y1 X0
INPUTS/OUTPUTS Y1 OUTPUTS/INPUTS
L H H H Z1 Y1 X1
H X X X NONE
5
Z0 4
3 Z SWITCH Z X = Don’t Care
Z1
11
A
CHANNEL-SELECT 10 PIN 16 = VCC
INPUTS B
9 PIN 7 = VEE Pinout: MC74HC4053A (Top View)
C PIN 8 = GND
6 VCC Y X X1 X0 A B C
ENABLE
16 15 14 13 12 11 10 9
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls
the Y–Switch and Input C controls the Z–Switch

1 2 3 4 5 6 7 8
Y1 Y0 Z1 Z Z0 Enable VEE GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit This device contains protection
circuitry to guard against damage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
(Referenced to VEE) – 0.5 to + 14.0 due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
fields. However, precautions must
VEE Negative DC Supply Voltage (Referenced to GND) – 7.0 to + 5.0 V be taken to avoid applications of any

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
voltage higher than maximum rated
VIS Analog Input Voltage VEE – 0.5 to V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
voltages to this high–impedance cir-
VCC + 0.5
cuit. For proper operation, Vin and

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout should be constrained to the
v v
Vin Digital Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
range GND (Vin or Vout) VCC.
I DC Current, Into or Out of Any Pin ± 25 mA Unused inputs must always be

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
EIAJ/SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450 Unused outputs must be left open.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎÎÎ
ÎÎÎ
Storage Temperature Range – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
EIAJ/SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ
Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Referenced to VEE) 2.0 12.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VEE Negative DC Supply Voltage, Output (Referenced to – 6.0 GND V
GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin
ÎÎÎÎÎ
ÎÎÎ
Analog Input Voltage

ÎÎ
ÎÎÎ
Digital Input Voltage (Referenced to GND)
VEE
GND
VCC
VCC
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIO*

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
Static or Dynamic Voltage Across Switch

ÎÎ
ÎÎÎ
Operating Temperature Range, All Package Types – 55
1.2
+ 125
V
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Rise/Fall Time

ÎÎÎ
VCC = 2.0 V 0 1000 ns

ÎÎ
(Channel Select or Enable Inputs) VCC = 3.0 V 0 600

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC = 4.5 V 0 500
VCC = 6.0 V 0 400
*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Ron = Per Spec 2.0 1.50 1.50 1.50 V
Voltage, Channel–Select or 3.0 2.10 2.10 2.10
Enable Inputs 4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Ron = Per Spec 2.0 0.5 0.5 0.5 V
Voltage, Channel–Select or 3.0 0.9 0.9 0.9
Enable Inputs 4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
Iin Maximum Input Leakage Current, Vin = VCC or GND, 6.0 ± 0.1 ± 1.0 ± 1.0 µA
Channel–Select or Enable Inputs VEE = – 6.0 V
ICC Maximum Quiescent Supply Channel Select, Enable and µA
Current (per Package) VIS = VCC or GND; VEE = GND 6.0 1 10 20
VIO = 0 V VEE = – 6.0 6.0 4 40 80
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC4051A, MC74HC4052A, MC74HC4053A

DC CHARACTERISTICS — Analog Section

Guaranteed Limit
Symbol Parameter Condition VCC VEE –55 to 25°C ≤85°C ≤125°C Unit
Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to 4.5 0.0 190 240 280 Ω
VEE; IS ≤ 2.0 mA 4.5 – 4.5 120 150 170
(Figures 1, 2) 6.0 – 6.0 100 125 140
Vin = VIL or VIH; VIS = VCC or 4.5 0.0 150 190 230
VEE (Endpoints); IS ≤ 2.0 mA 4.5 – 4.5 100 125 140
(Figures 1, 2) 6.0 – 6.0 80 100 115
∆Ron Maximum Difference in “ON” Vin = VIL or VIH; 4.5 0.0 30 35 40 Ω
Resistance Between Any Two VIS = 1/2 (VCC – VEE); 4.5 – 4.5 12 15 18
Channels in the Same Package IS ≤ 2.0 mA 6.0 – 6.0 10 12 14
Ioff Maximum Off–Channel Leakage Vin = VIL or VIH; µA
Current, Any One Channel VIO = VCC – VEE; 6.0 – 6.0 0.1 0.5 1.0
Switch Off (Figure 3)
Maximum Off–Channel HC4051A Vin = VIL or VIH; 6.0 – 6.0 0.2 2.0 4.0
Leakage Current, HC4052A VIO = VCC – VEE; 6.0 – 6.0 0.1 1.0 2.0
Common Channel HC4053A Switch Off (Figure 4) 6.0 – 6.0 0.1 1.0 2.0
Ion Maximum On–Channel HC4051A Vin = VIL or VIH; 6.0 – 6.0 0.2 2.0 4.0 µA
Leakage Current, HC4052A Switch–to–Switch = 6.0 – 6.0 0.1 1.0 2.0
Channel–to–Channel HC4053A VCC – VEE; (Figure 5) 6.0 – 6.0 0.1 1.0 2.0

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Channel–Select to Analog Output 2.0 270 320 350 ns
tPHL (Figure 9) 3.0 90 110 125
4.5 59 79 85
6.0 45 65 75
tPLH, Maximum Propagation Delay, Analog Input to Analog Output 2.0 40 60 70 ns
tPHL (Figure 10) 3.0 25 30 32
4.5 12 15 18
6.0 10 13 15
tPLZ, Maximum Propagation Delay, Enable to Analog Output 2.0 160 200 220 ns
tPHZ (Figure 11) 3.0 70 95 110
4.5 48 63 76
6.0 39 55 63
tPZL, Maximum Propagation Delay, Enable to Analog Output 2.0 245 315 345 ns
tPZH (Figure 11) 3.0 115 145 155
4.5 49 69 83
6.0 39 58 67
Cin Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF
CI/O Maximum Capacitance Analog I/O 35 35 35 pF
(All Switches Off) Common O/I: HC4051A 130 130 130
HC4052A 80 80 80
HC4053A 50 50 50
Feedthrough 1.0 1.0 1.0
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D)
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Figure 13)* HC4051A 45 pF
HC4052A 80
HC4053A 45
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC4051A, MC74HC4052A, MC74HC4053A

ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

Limit*
VCC VEE
Symbol Parameter Condition V V 25°C Unit
BW Maximum On–Channel Bandwidth fin = 1MHz Sine Wave; Adjust fin Voltage to ‘51 ‘52 ‘53 MHz
or Minimum
Mi i Frequency
F Response
R Obt i 0dBm
Obtain 0dB att VOS; Increase
I fin
2.25 –2.25 80 95 120
(Figure 6) Frequency Until dB Meter Reads –3dB;
4.50 –4.50 80 95 120
RL = 50Ω, CL = 10pF
6.00 –6.00 80 95 120
— Off–Channel Feedthrough Isolation fin = Sine Wave; Adjust fin Voltage to 2.25 –2.25 –50 dB
(Figure 7) Obtain 0dBm at VIS 4.50 –4.50 –50
fin = 10kHz, RL = 600Ω, CL = 50pF 6.00 –6.00 –50
2.25 –2.25 –40
4.50 –4.50 –40
fin = 1.0MHz, RL = 50Ω, CL = 10pF 6.00 –6.00 –40
— Feedthrough Noise. Vin ≤ 1MHz Square Wave (tr = tf = 6ns); 2.25 –2.25 25 mVPP
Channel–Select Input to Common Adjust RL at Setup so that IS = 0A; 4.50 –4.50 105
I/O (Figure 8) Enable = GND RL = 600Ω, CL = 50pF 6.00 –6.00 135
2.25 –2.25 35
4.50 –4.50 145
RL = 10kΩ, CL = 10pF 6.00 –6.00 190
— Crosstalk Between Any Two fin = Sine Wave; Adjust fin Voltage to 2.25 –2.25 –50 dB
Switches (Figure 12) Obtain 0dBm at VIS 4.50 –4.50 –50
(Test does not apply to HC4051A) fin = 10kHz, RL = 600Ω, CL = 50pF 6.00 –6.00 –50
2.25 –2.25 –60
4.50 –4.50 –60
fin = 1.0MHz, RL = 50Ω, CL = 10pF 6.00 –6.00 –60
THD Total Harmonic Distortion fin = 1kHz, RL = 10kΩ, CL = 50pF %
(Figure 14) THD = THDmeasured – THDsource
VIS = 4.0VPP sine wave 2.25 –2.25 0.10
VIS = 8.0VPP sine wave 4.50 –4.50 0.08
VIS = 11.0VPP sine wave 6.00 –6.00 0.05
*Limits not tested. Determined by design and verified by qualification.

300 180
160
250
Ron , ON RESISTANCE (OHMS)

Ron , ON RESISTANCE (OHMS)

140
200 120
125°C 125°C
100
150
25°C 80
25°C
– 55°C
100 60
40 – 55°C
50
20
0 0
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1a. Typical On Resistance, VCC – VEE = 2.0 V Figure 1b. Typical On Resistance, VCC – VEE = 3.0 V

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 MC74HC4051A, MC74HC4052A, MC74HC4053A

120 105

100 90
Ron , ON RESISTANCE (OHMS)

Ron , ON RESISTANCE (OHMS)

75 125°C
80
125°C
60
60 25°C
25°C 45
– 55°C
40
– 55°C 30

20 15

0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1c. Typical On Resistance, VCC – VEE = 4.5 V Figure 1d. Typical On Resistance, VCC – VEE = 6.0 V

80 60

70
50
Ron , ON RESISTANCE (OHMS)

60 Ron , ON RESISTANCE (OHMS) 125°C

40
50 25°C
125°C
40 30
– 55°C
30 25°C
20
20 – 55°C
10
10
0 0
–4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 –6.0 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 6.0
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1e. Typical On Resistance, VCC – VEE = 9.0 V Figure 1f. Typical On Resistance, VCC – VEE = 12.0 V

PLOTTER

PROGRAMMABLE
POWER MINI COMPUTER DC ANALYZER
SUPPLY
– + VCC
DEVICE
UNDER TEST

ANALOG IN COMMON OUT

GND VEE

Figure 2. On Resistance Test Set–Up

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 MC74HC4051A, MC74HC4052A, MC74HC4053A

VCC VCC

VCC VCC
VEE 16 VEE 16
ANALOG I/O
OFF OFF
VCC A VCC
NC OFF COMMON O/I OFF COMMON O/I

VIH 6 VIH 6
7 7
8 8
VEE VEE

Figure 3. Maximum Off Channel Leakage Current, Figure 4. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up Common Channel, Test Set–Up

VCC VOS
VCC VCC
A 16 0.1µF 16 dB
ON fin ON METER
VEE N/C CL* RL
OFF COMMON O/I
VCC ANALOG I/O

VIL 6 6
7 7
8 8
VEE VEE
*Includes all probe and jig capacitance

Figure 5. Maximum On Channel Leakage Current, Figure 6. Maximum On Channel Bandwidth,

Channel to Channel, Test Set–Up Test Set–Up

VIS VCC VOS VCC

0.1µF 16 dB 16
RL
fin OFF METER ON/OFF COMMON O/I
TEST
RL CL* RL ANALOG I/O
POINT
OFF/ON RL CL*
RL

6 6
7 7 VCC
8 Vin ≤ 1 MHz 8 11
tr = tf = 6 ns
VEE VCC VEE
CHANNEL SELECT CHANNEL SELECT
VIL or VIH GND
*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 7. Off Channel Feedthrough Isolation, Figure 8. Feedthrough Noise, Channel Select to
Test Set–Up Common Out, Test Set–Up

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 MC74HC4051A, MC74HC4052A, MC74HC4053A

VCC
VCC
16
VCC
CHANNEL ON/OFF COMMON O/I
50% TEST
SELECT ANALOG I/O
POINT
OFF/ON CL*
GND
tPLH tPHL

6
ANALOG 7
OUT 50%
8

CHANNEL SELECT

*Includes all probe and jig capacitance

Figure 9a. Propagation Delays, Channel Select Figure 9b. Propagation Delay, Test Set–Up Channel
to Analog Out Select to Analog Out

VCC
16
ANALOG I/O COMMON O/I
VCC TEST
ON
ANALOG POINT
IN 50% CL*
GND
tPLH tPHL
6
7
ANALOG 8
OUT 50%

*Includes all probe and jig capacitance

Figure 10a. Propagation Delays, Analog In Figure 10b. Propagation Delay, Test Set–Up
to Analog Out Analog In to Analog Out

tf tr POSITION 1 WHEN TESTING tPHZ AND tPZH

VCC 1 POSITION 2 WHEN TESTING tPLZ AND tPZL
90%
ENABLE 50% 2
VCC
10%
GND VCC 1kΩ
tPZL tPLZ 16
HIGH 1 ANALOG I/O
IMPEDANCE TEST
ANALOG 2 ON/OFF
50% POINT
OUT 10% CL*
VOL
tPZH tPHZ
ENABLE
VOH 6
90%
ANALOG 7
OUT 50% 8
HIGH
IMPEDANCE

Figure 11a. Propagation Delays, Enable to Figure 11b. Propagation Delay, Test Set–Up
Analog Out Enable to Analog Out

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 MC74HC4051A, MC74HC4052A, MC74HC4053A

VCC
VIS A
VCC
16 16
RL VOS
fin ON ON/OFF COMMON O/I
ANALOG I/O NC
0.1µF OFF/ON

OFF
VEE RL CL* RL CL* VCC
RL 6
7
6 VEE 8 11
7
8 CHANNEL SELECT

*Includes all probe and jig capacitance

Figure 12. Crosstalk Between Any Two Figure 13. Power Dissipation Capacitance,
Switches, Test Set–Up Test Set–Up

0
VIS
VCC VOS – 10 FUNDAMENTAL FREQUENCY
0.1µF 16 – 20
TO
fin ON DISTORTION – 30
RL METER
CL* – 40
dB

– 50
DEVICE
– 60
6 SOURCE
– 70
7
8 – 80
VEE – 90
*Includes all probe and jig capacitance
– 100
1.0 2.0 3.125
FREQUENCY (kHz)

Figure 14a. Total Harmonic Distortion, Test Set–Up Figure 14b. Plot, Harmonic Distortion

APPLICATIONS INFORMATION

The Channel Select and Enable control pins should be at outputs to VCC or GND through a low value resistor helps
VCC or GND logic levels. VCC being recognized as a logic minimize crosstalk and feedthrough noise that may be
high and GND being recognized as a logic low. In this picked up by an unused switch.
example: Although used here, balanced supplies are not a
VCC = +5V = logic high requirement. The only constraints on the power supplies are
GND = 0V = logic low that:
The maximum analog voltage swings are determined by VCC – GND = 2 to 6 volts
the supply voltages VCC and VEE. The positive peak analog VEE – GND = 0 to –6 volts
voltage should not exceed VCC. Similarly, the negative peak VCC – VEE = 2 to 12 volts
analog voltage should not go below VEE. In this example, and VEE ≤ GND
the difference between VCC and VEE is ten volts. Therefore, When voltage transients above VCC and/or below VEE are
using the configuration of Figure 15, a maximum analog anticipated on the analog channels, external Germanium or
signal of ten volts peak–to–peak can be controlled. Unused Schottky diodes (Dx) are recommended as shown in Figure
analog inputs/outputs may be left floating (i.e., not 16. These diodes should be able to absorb the maximum
connected). However, tying unused analog inputs and anticipated current surges during clipping.

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 MC74HC4051A, MC74HC4052A, MC74HC4053A

VCC VCC
+5V VCC
16 Dx 16 Dx
+5V +5V
ANALOG ANALOG
ON ON/OFF
–5V SIGNAL SIGNAL –5V
Dx Dx

VEE VEE

6 11 TO EXTERNAL CMOS
7 10 CIRCUITRY 0 to 5V 7
8 9 DIGITAL SIGNALS 8
–5V VEE

Figure 15. Application Example Figure 16. External Germanium or

Schottky Clipping Diodes

+5V +5V

+5V 16 +5V +5V 16 +5V

ANALOG ANALOG ANALOG ANALOG
ON/OFF ON/OFF
VEE SIGNAL SIGNAL VEE VEE SIGNAL SIGNAL VEE
+5V
*
R R R +5V
6 11 6 11
LSTTL/NMOS LSTTL/NMOS
7 10 7 10
CIRCUITRY CIRCUITRY
8 9 8 9
VEE VEE
* 2K ≤ R ≤ 10K HCT
BUFFER
a. Using Pull–Up Resistors b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs

11 LEVEL 13
A X0
SHIFTER

14
X1

10 LEVEL 15
B X2
SHIFTER

12
X3

9 LEVEL 1
C X4
SHIFTER

5
X5

6 LEVEL 2
ENABLE X6
SHIFTER

4
X7

3
X
Figure 18. Function Diagram, HC4051A

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 MC74HC4051A, MC74HC4052A, MC74HC4053A

10 LEVEL 12
A X0
SHIFTER

14
X1

9 LEVEL 15
B X2
SHIFTER

11
X3
13
X
6 LEVEL 1
ENABLE Y0
SHIFTER

5
Y1

2
Y2

4
Y3

3
Y

Figure 19. Function Diagram, HC4052A

11 LEVEL 13
A X1
SHIFTER

12
X0
14
X
10 LEVEL 1
B Y1
SHIFTER

2
Y0
15
Y
9 LEVEL 3
C Z1
SHIFTER

5
Z0
4
Z
6 LEVEL
ENABLE
SHIFTER

Figure 20. Function Diagram, HC4053A

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ORDERING & SHIPPING INFORMATION

Device Package Shipping
MC74HC4051AN PDIP–16 500 Units / Unit Pak
MC74HC4051AD SOIC–16 48 Units / Rail
MC74HC4051ADR2 SOIC–16 2500 Units / Tape & Reel
MC74HC4051ADT TSSOP–16 96 Units / Rail
MC74HC4051ADTR2 TSSOP–16 2500 Units / Tape & Reel
MC74HC4051ADW SOIC WIDE 48 Units / Rail
MC74HC4051ADWR2 SOIC WIDE 1000 Units / Tape & Reel
MC74HC4051AF SOEIAJ–16 See Note 1.
MC74HC4051AFEL SOEIAJ–16 See Note 1.
MC74HC4052AN PDIP–16 500 Units / Unit Pak
MC74HC4052AD SOIC–16 48 Units / Rail
MC74HC4052ADR2 SOIC–16 2500 Units / Tape & Reel
MC74HC4052ADT TSSOP–16 96 Units / Rail
MC74HC4052ADTR2 TSSOP–16 2500 Units / Tape & Reel
MC74HC4052ADW SOIC WIDE 48 Units / Rail
MC74HC4052ADWR2 SOIC WIDE 1000 Units / Tape & Reel
MC74HC4052AF SOEIAJ–16 See Note 1.
MC74HC4052AFEL SOEIAJ–16 See Note 1.
MC74HC4053AN PDIP–16 500 Units / Unit Pak
MC74HC4053AD SOIC–16 48 Units / Rail
MC74HC4053ADR2 SOIC–16 2500 Units / Tape & Reel
MC74HC4053ADT TSSOP–16 96 Units / Rail
MC74HC4053ADTR2 TSSOP–16 2500 Units / Tape & Reel
MC74HC4053ADW SOIC WIDE 48 Units / Rail
MC74HC4053ADWR2 SOIC WIDE 1000 Units / Tape & Reel
MC74HC4053AF SOEIAJ–16 See Note 1.
MC74HC4053AFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

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MC74HC4060A

14-Stage Binary Ripple

Counter With Oscillator
High–Performance Silicon–Gate CMOS
The MC74C4060A is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS
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outputs; with pullup resistors, they are compatible with LSTTL
outputs. MARKING
This device consists of 14 master–slave flip–flops and an oscillator DIAGRAMS
with a frequency that is controlled either by a crystal or by an RC 16
circuit connected externally. The output of each flip–flop feeds the PDIP–16
N SUFFIX MC74HC4060AN
next and the frequency at each output is half of that of the preceding 16 AWLYYWW
CASE 648
one. The state of the counter advances on the negative–going edge of 1
the Osc In. The active–high Reset is asynchronous and disables the 1
16
oscillator to allow very low power consumption during stand–by
SO–16
operation. HC4060A
D SUFFIX
State changes of the Q outputs do not occur simultaneously because 16
CASE 751B
AWLYWW
of internal ripple delays. Therefore, decoded output signals are subject 1
1
to decoding spikes and may have to be gated with Osc Out 2 of the 16
HC4060A.
TSSOP–16 HC40
• Output Drive Capability: 10 LSTTL Loads 16 DT SUFFIX 60A
• Outputs Directly Interface to CMOS, NMOS, and TTL 1
CASE 948F ALYW

• Operating Voltage Range: 2 to 6 V 1

• Low Input Current: 1 µA
A
WL
= Assembly Location
= Wafer Lot
• High Noise Immunity Characteristic of CMOS Devices YY = Year
• In Compliance With JEDEC Standard No. 7A Requirements WW = Work Week

• Chip Complexity: 390 FETs or 97.5 Equivalent Gates LOGIC DIAGRAM

Osc Out 1 Osc Out 2
Pinout: 16–Lead Plastic Package (Top View) 10 9
Osc Osc
7
VCC Q10 Q8 Q9 Reset Osc In Out 1 Out 2 Q4
5
16 15 14 13 12 11 10 9 Q5
11 4
Osc In Q6
6
Q7
14
Q8
13
Q9
15
Q10
1
Q12
1 2 3 4 5 6 7 8 2
Q13
Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND 3
Q14
12 Pin 16 = VCC
FUNCTION TABLE Reset
Pin 8 = GND
Clock Reset Output State
L No Charge
ORDERING INFORMATION
L Advance to Next State
Device Package Shipping
X H All Outputs Are Low
MC74HC4060AN PDIP–16 2000 / Box
MC74HC4060AD SOIC–16 48 / Rail
MC74HC4060ADR2 SOIC–16 2500 / Reel
MC74HC4060ADT TSSOP–16 96 / Rail
MC74HC4060ADTR2 TSSOP–16 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 332 Publication Order Number:

March, 2000 – Rev. 2 MC74HC4060A/D
 MC74HC4060A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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MAXIMUM RATINGS*

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Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
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ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

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ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

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ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

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Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

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cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
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ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

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Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

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ÎÎÎÎÎ
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SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

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Unused outputs must be left open.
Tstg Storage Temperature Range – 65 to + 150 _C

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TL

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Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
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Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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RECOMMENDED OPERATING CONDITIONS

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Symbol Parameter Min Max Unit

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VCC DC Supply Voltage (Referenced to GND) 2.5* 6.0 V

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Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

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TA Operating Temperature Range, All Package Types – 55 + 125 _C

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tr, tf Input Rise/Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500

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ÎÎÎÎÎ
ÎÎÎ VCC = 6.0 V 0 400
*The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested
at 2.0 V by driving Pin 11 with an external clock source.

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Vout = 0.1V or VCC –0.1V 2.0 1.50 1.50 1.50 V
Voltage |Iout| ≤ 20µA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Vout = 0.1V or VCC – 0.1V 2.0 0.50 0.50 0.50 V
Voltage |Iout| ≤ 20µA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Voltage (Q4–Q10, Q12–Q14) |Iout| ≤ 20µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin =VIH or VIL |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20

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 MC74HC4060A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
Voltage (Q4–Q10, Q12–Q14) |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
VOH Minimum High–Level Output Vin = VCC or GND 2.0 1.9 1.9 1.9 V
Voltage (Osc Out 1, Osc Out 2) |Iout| ≤ 20µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin =VCC or GND |Iout| ≤ 0.7mA 3.0 2.48 2.34 2.20
|Iout| ≤ 1.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 1.3mA 6.0 5.48 5.34 5.20
VOL Maximum Low–Level Output Vin = VCC or GND 2.0 0.1 0.1 0.1 V
Voltage (Osc Out 1, Osc Out 2) |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin =VCC or GND |Iout| ≤ 0.7mA 3.0 0.26 0.33 0.40
|Iout| ≤ 1.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 1.3mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 µA
Current (per Package) Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 6.0 9.0 8.0 MHz
(Figures 1 and 4) 3.0 10 14 12
4.5 30 28 25
6.0 50 45 40
tPLH, Maximum Propagation Delay, Osc In to Q4* 2.0 300 375 450 ns
tPHL (Figures 1 and 4) 3.0 180 200 250
4.5 60 75 90
6.0 51 64 75
tPLH, Maximum Propagation Delay, Osc In to Q14* 2.0 500 750 1000 ns
tPHL (Figures 1 and 4) 3.0 350 450 600
4.5 250 275 300
6.0 200 220 250
tPHL Maximum Propagation Delay, Reset to Any Q 2.0 195 245 300 ns
(Figures 2 and 4) 3.0 75 100 125
4.5 39 49 61
6.0 33 42 53
tPLH, Maximum Propagation Delay, Qn to Qn+1 2.0 75 95 125 ns
tPHL (Figures 3 and 4) 3.0 60 75 95
4.5 15 19 24
6.0 13 16 20

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 MC74HC4060A

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) – continued

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 4) 3.0 27 32 36
4.5 15 19 22
6.0 13 16 19
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] ns
VCC = 3.0 V: tP = [61.5+ 34.4 (n–1)] ns VCC = 6.0 V: tP = [24.4 + 12 (n–1)] ns

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 35 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
trec Minimum Recovery Time, Reset Inactive to Clock 2.0 100 125 150 ns
(Figure 2) 3.0 75 100 120
4.5 20 25 30
6.0 17 21 25
tw Minimum Pulse Width, Clock 2.0 75 95 110 ns
(Figure 1) 3.0 27 32 36
4.5 15 19 23
6.0 13 16 19
tw Minimum Pulse Width, Reset 2.0 75 95 110 ns
(Figure 2) 3.0 27 32 36
4.5 15 19 23
6.0 13 16 19
tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns
(Figure 1) 3.0 800 800 800
4.5 500 500 500
6.0 400 400 400
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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 MC74HC4060A

PIN DESCRIPTIONS

INPUTS Osc Out 1, Osc Out 2 (Pins 9, 10)

Osc In (Pin 11) Oscillator outputs. These pins are used in conjunction
Negative–edge triggering clock input. A high–to–low with Osc In and the external components to form an
transition on this input advances the state of the counter. Osc oscillator. When Osc In is being driven with an external
In may be driven by an external clock source. clock source, Osc Out 1 and Osc Out 2 must be left open
circuited. With the crystal oscillator configuration in Figure
Reset (Pin 12)
6, Osc Out 2 must be left open circuited.
Active–high reset. A high level applied to this input
asynchronously resets the counter to its zero state (forcing
all Q outputs low) and disables the oscillator.

OUTPUTS
Q4—Q10, Q12–Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)
Active–high outputs. Each Qn output divides the Clock
input frequency by 2N. The user should note the Q1, Q2, Q3
and Q11 are not available as outputs.

SWITCHING WAVEFORMS

tw
tf tr VCC
VCC Reset 50%
90%
Osc In 50% GND
10% GND tPHL
tw
1/fMAX
tPLH tPHL Q 50%

90% trec
Q 50% VCC
10%
Osc In 50%
tTLH tTHL GND

Figure 1. Figure 2.

TEST
POINT

VCC
Qn OUTPUT
50%
DEVICE
GND UNDER
tPLH tPHL TEST CL*

Qn+1 50%

*Includes all probe and jig capacitance

Figure 3. Figure 4. Test Circuit

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 MC74HC4060A

Q4 Q5 Q12 Q13 Q14

7 5 1 2 3

C Q C Q C Q C Q C Q C Q

C Q C Q C Q C Q C Q C

R R
9
Osc Out 2

Q6 = Pin 4 Q10 = Pin 15

10 Q7 = Pin 6 VCC = Pin 16
Osc Out 1 Q8 = Pin 14 GND = Pin 8
Q9 = Pin 13

11
Osc In
12
Reset

Figure 5. Expanded Logic Diagram

12 For 2.0V ≤ VCC ≤ 6.0V

Reset 10Rtc > RS > 2Rtc
400Hz ≤ f ≤ 400Khz:
Osc In 11 Osc Out 1 10 Osc Out 2 9
f [ 3 R1tcCtc (f in Hz, Rtc in ohms, Ctc in farads)
Rtc
RS Ctc
The formula may vary for other frequencies.

Figure 6. Oscillator Circuit Using RC Configuration

12
Reset

Osc In 11 Osc Out 1 10 9 Osc Out 2

Rf

R1

C1 C2

Figure 7. Pierce Crystal Oscillator Circuit

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 MC74HC4060A

TABLE 1. CRYSTAL OSCILLATOR AMPLIFIER SPECIFICATIONS (TA = 25°C; Input = Pin 11, Output = Pin 10)
Type Positive Reactance (Pierce)
Input Resistance, Rin 60MΩ Minimum
Output Impedance, Zout (4.5V Supply) 200Ω (See Text)
Input Capacitance, Cin 5pF Typical
Output Capacitance, Cout 7pF Typical
Series Capacitance, Ca 5pF Typical
Open Loop Voltage Gain with Output at Full Swing, α 3Vdc Supply 5.0 Expected Minimum
4Vdc Supply 4.0 Expected Minimum
5Vdc Supply 3.3 Expected Minimum
6Vdc Supply 3.1 Expected Minimum

PIERCE CRYSTAL OSCILLATOR DESIGN

RS LS CS

1 2 1 2 1 Re Xe 2
CO

Value are supplied by crystal manufacturer (parallel resonant crystal).

Figure 8. Equivalent Crystal Networks

RS –jXC2 R
Rload
Ca
–jXCo
jXLs
Zload Xload
–jXCs –jXC Cin Cout

NOTE: C = C1 + Cin and R = R1 + Rout. Co is considered as part of

the load. Ca and Rf typically have minimal effect below 2MHz. Values are listed in Table 1.

Figure 9. Series Equivalent Crystal Load Figure 10. Parasitic Capacitances of the Amplifier

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 MC74HC4060A

DESIGN PROCEDURES

The following procedure applies for oscillators operating below 2MHz where Z is a resistor R1. Above 2MHz, additional
impedance elements should be considered: Cout and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from
180°C.
Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation.

Ze + **jXjXCCo)(RRs s))jXjXLsL**jXjXCCs) + Re ) jXe

o s s
Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency.
The maximum Rs for the crystal should be used in the equation.
Step 2: Determine β, the attenuation, of the feedback network. For a closed-loop gain of 2,Aνβ = 2,β = 2/Aν where Aν is
the gain of the HC4060A amplifier.
Step 3: Determine the manufacturer’s loading capacitance. For example: A manufacturer may specify an external load
capacitance of 32pF at the required frequency.
Step 4: Determine the required Q of the system, and calculate Rload, For example, a manufacturer specifies a crystal Q of
100,000. In-circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then Rload = (2πfoLS/Q) – Rs where Ls and Rs are
crystal parameters.
Step 5: Simultaneously solve, using a computer,
@ XC2
+ R @ Re )XCXC2 (Xe * XC)
b (with feedback phase shift = 180°) ( Eq 1 )

Xe + XC2 ) XC ) ReRXC2 + XCload (where the loading capacitor is an external load, not including Co) ( Eq 2 )

RXCoXC2 [(XC ) XC2)(XC ) XCo) * XC(XC ) XCo ) XC2)]

Rload +
X2C2(XC ) XCo)2 ) R2(XC ) XCo ) XC2)2
( Eq 3 )

Here R = Rout + R1. Rout is amp output resistance, R1 is Z. The C corresponding to XC is given by C = C1 + Cin.
Alternately, pick a value for R1 (i.e, let R1 = RS). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that
Q = 2πfoLs/(Rs + Rload) to find in-circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure.
CHOOSING R1 the first overtone. Rf must be large enough so as to not affect
Power is dissipated in the effective series resistance of the the phase of the feedback network in an appreciable manner.
crystal. The drive level specified by the crystal manufacturer ACKNOWLEDGEMENTS AND RECOMMENDED
is the maximum stress that a crystal can withstand without REFERENCES
damage or excessive shift in frequency. R1 limits the drive The following publications were used in preparing this
level. data sheet and are hereby acknowledged and recommended
To verify that the maximum dc supply voltage does not for reading:
overdrive the crystal, monitor the output frequency as a Technical Note TN-24, Statek Corp.
function of voltage at Osc Out 2 (Pin 9). The frequency Technical Note TN-7, Statek Corp.
should increase very slightly as the dc supply voltage is D. Babin, “Designing Crystal Oscillators”, Machine
increased. An overdriven crystal will decrease in frequency Design, March 7, 1985.
or become unstable with an increase in supply voltage. The D. Babin, “Guidelines for Crystal Oscillator Design”,
operating supply voltage must be reduced or R1 must be Machine Design, April 25, 1985.
increased in value if the overdriven condition exists. The
user should note that the oscillator start-up time is ALSO RECOMMENDED FOR READING:
proportional to the value of R1. E. Hafner, “The Piezoelectric Crystal Unit-Definitions
and Method of Measurement”, Proc. IEEE, Vol. 57, No. 2,
SELECTING Rf Feb., 1969.
The feedback resistor, Rf, typically ranges up to 20MΩ. Rf D. Kemper, L. Rosine, “Quartz Crystals for Frequency
determines the gain and bandwidth of the amplifier. Proper Control”, Electro-Technology, June, 1969.
bandwidth insures oscillation at the correct frequency plus P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
roll-off to minimize gain at undesirable frequencies, such as Design, May, 1966.

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 MC74HC4060A

1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384

Clock
Reset

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q12

Q13

Q14

Figure 11. Timing Diagram

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MC74HC4066A

Advance Information
Quad Analog Switch/
Multiplexer/Demultiplexer
High–Performance Silicon–Gate CMOS
The MC74HC4066A utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low
http://onsemi.com
OFF–channel leakage current. This bilateral switch/
multiplexer/demultiplexer controls analog and digital voltages that MARKING
may vary across the full power–supply range (from VCC to GND). DIAGRAMS
The HC4066A is identical in pinout to the metal–gate CMOS 14
MC14016 and MC14066. Each device has four independent switches. PDIP–14
N SUFFIX HC4066AN
The device has been designed so that the ON resistances (RON) are CASE 646 AWLYYWW
much more linear over input voltage than RON of metal–gate CMOS
1
analog switches. 14
The ON/OFF control inputs are compatible with standard CMOS SOIC–14
HC4066AD
outputs; with pullup resistors, they are compatible with LSTTL outputs. D SUFFIX
AWLYWW
For analog switches with voltage–level translators, see the HC4316A. CASE 751A

• Fast Switching and Propagation Speeds 1

14
• High ON/OFF Output Voltage Ratio HC40
TSSOP–14
• Low Crosstalk Between Switches DT SUFFIX 66A
• Diode Protection on All Inputs/Outputs CASE 948G ALYW

• Wide Power–Supply Voltage Range (VCC – GND) = 2.0 to 12.0 Volts 1

14
• Analog Input Voltage Range (VCC – GND) = 2.0 to 12.0 Volts
SOEIAJ–14
• Improved Linearity and Lower ON Resistance over Input Voltage F SUFFIX 74HC4066A
than the MC14016 or MC14066 CASE 965 AWLYWW

• Low Noise 1
• Chip Complexity: 44 FETs or 11 Equivalent Gates A = Assembly Location
LOGIC DIAGRAM WL or L = Wafer Lot
YY or Y = Year
XA 1 2 Y WW or W = Work Week
A
PIN ASSIGNMENT
A ON/OFF CONTROL 13
XA 1 14 VCC
4 3 Y A ON/OFF
XB B YA 2 13 CONTROL
YB 3 12 D ON/OFF
B ON/OFF CONTROL 5 CONTROL
ANALOG XB 4 11 XD
XC 8 9 Y OUTPUTS/INPUTS B ON/OFF
C CONTROL 5 10 YD
6 C ON/OFF 6 9 YC
C ON/OFF CONTROL CONTROL
GND 7 8 XC
XD 11 10 Y
D

D ON/OFF CONTROL 12 ORDERING INFORMATION

ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD Device Package Shipping
PIN 14 = VCC
MC74HC4066AN PDIP–14 2000 / Box
PIN 7 = GND
MC74HC4066AD SOIC–14 55 / Rail
FUNCTION TABLE MC74HC4066ADR2 SOIC–14 2500 / Reel
On/Off Control State of MC74HC4066ADT TSSOP–14 96 / Rail
Input Analog Switch
MC74HC4066ADTR2 TSSOP–14 2500 / Reel
L Off
MC74HC4066AF SOEIAJ–14 See Note 1.
H On
1. For ordering information on the EIAJ version of the
This document contains information on a new product. Specifications and information
SOIC packages, please contact your local ON
herein are subject to change without notice.
Semiconductor representative.

 Semiconductor Components Industries, LLC, 2000 341 Publication Order Number:

March, 2000 – Rev. 1 MC74HC4066A/D
 MC74HC4066A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) – 0.5 to + 14.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIS Analog Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin Digital Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
I DC Current Into or Out of Any Pin ± 25 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, Plastic DIP† 750 mW cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
EIAJ/SOIC Package† 500
TSSOP Package† 450 range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
Tstg Storage Temperature – 65 to + 150 _C tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
level (e.g., either GND or VCC).
TL Lead Temperature, 1 mm from Case for 10 Seconds _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
(Plastic DIP, SOIC or TSSOP Package) 260
I/O pins must be connected to a
*Maximum Ratings are those values beyond which damage to the device may occur. properly terminated line or bus.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
EIAJ/SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ
Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) 2.0 12.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIS Analog Input Voltage (Referenced to GND) GND VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin Digital Input Voltage (Referenced to GND) GND VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIO* Static or Dynamic Voltage Across Switch — 1.2 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
tr, tf Input Rise and Fall Time, ON/OFF Control ns
Inputs (Figure 10) VCC = 2.0 V 0 1000

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
VCC = 3.0 V 0 600

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
VCC = 4.5 V 0 500
VCC = 9.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC = 12.0 V 0 250
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input
components. The reliability of the device will be unaffected unless the Maximum Ratings are

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
exceeded.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC – 55 to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
VIH ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Parameter

ÎÎÎ
Minimum High–Level Voltage
Test Conditions
Ron = Per Spec
V
2.0
25_C
1.5
85_C
1.5
125_C
1.5
Unit
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ON/OFF Control Inputs 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
9.0 6.3 6.3 6.3

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
12.0 8.4 8.4 8.4
VIL Maximum Low–Level Voltage Ron = Per Spec 2.0 0.5 0.5 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ON/OFF Control Inputs

ÎÎÎ
3.0
4.5
9.0
0.9
1.35
2.7
0.9
1.35
2.7
0.9
1.35
2.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
12.0 3.6 3.6 3.6

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Current Vin = VCC or GND 12.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ON/OFF Control Inputs
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 2 20 40 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current (per Package) VIO = 0 V 12.0 4 40
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
160

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ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v V 25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions Unit
Ron Maximum “ON” Resistance Vin = VIH 2.0† — — — Ω

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VIS = VCC to GND
IS 2.0 mA (Figures 1, 2)
3.0†
4.5
9.0
—
120
70
—
160
85
—
200
100

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
12.0 70 85 100

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH 2.0 — — —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIS = VCC or GND (Endpoints) 3.0 — — —
v IS 2.0 mA (Figures 1, 2) 4.5 70 85 100

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
9.0 50 60 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
12.0 30 60 80
∆Ron Ω

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Difference in “ON” Vin = VIH 2.0 — — —
Resistance Between Any Two VIS = 1/2 (VCC – GND) 4.5 20 25 30
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Channels in the Same Package IS 2.0 mA 9.0 15 20 25
12.0 15 20 25

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Ioff
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Off–Channel Leakage

ÎÎÎ
Current, Any One Channel
Vin = VIL
VIO = VCC or GND
12.0 0.1 0.5 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Switch Off (Figure 3)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Ion Maximum On–Channel Leakage Vin = VIH 12.0 0.1 0.5 1.0 µA
Current, Any One Channel VIS = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figure 4)
†At supply voltage (VCC) approaching 3 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage
operation, it is recommended that these devices only be used to control digital signals.
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v V 25_C 85_C 125_C

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Unit
tPLH, Maximum Propagation Delay, Analog Input to Analog Output 2.0 40 50 60 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figures 8 and 9)

ÎÎÎ
3.0
4.5
9.0
30
5
5
40
7
7
50
8
8

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ, ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Propagation Delay, ON/OFF Control to Analog Output
12.0
2.0
5
80
7
90
8
110 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHZ (Figures 10 and 11) 3.0 60 70 80
4.5 20 25 35

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
9.0 20 25 35

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
12.0 20 25 35

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPZL, Maximum Propagation Delay, ON/OFF Control to Analog Output 2.0 80 90 100 ns
tPZH (Figures 10 and 1 1) 3.0 45 50 60

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 20 25 30
9.0 20 25 30

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ C ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Capacitance ON/OFF Control Input
12.0
—
20
10
25
10
30
10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Control Input = GND

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Analog I/O — 35 35 35
Feedthrough — 1.0 1.0 1.0
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* 15 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Limit*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
VCC 25_C
Symbol Parameter Test Conditions V 54/74HC Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
BW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
or ÎÎÎÎ
ÎÎÎ ÎÎÎ
Maximum On–Channel Bandwidth

ÎÎÎÎ
ÎÎÎ
fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
4.5
9.0
150
160
MHz

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Minimum Frequency Response Increase fin Frequency Until dB Meter Reads – 3 dB 12.0 160
(Figure 5) RL = 50 Ω, CL = 10 pF

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
—
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 6) ÎÎÎÎ
ÎÎÎ ÎÎÎ
Off–Channel Feedthrough Isolation

ÎÎÎÎ
ÎÎÎ
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 Ω, CL = 50 pF
4.5
9.0
– 50
– 50
dB

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
12.0 – 50
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
4.5 – 40
9.0 – 40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
12.0 – 40
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
— Feedthrough Noise, Control to Vin 1 MHz Square Wave (tr = tf = 6 ns) 4.5 60 mVPP

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Switch Adjust RL at Setup so that IS = 0 A 9.0 130
(Figure 7) RL = 600 Ω, CL = 50 pF 12.0 200

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
RL = 10 kΩ, CL = 10 pF 4.5
9.0
12.0
30
65
100

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
—
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ

Switches ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Crosstalk Between Any Two fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
4.5
9.0
– 70
– 70
dB

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 12) fin = 10 kHz, RL = 600 Ω, CL = 50 pF 12.0 – 70

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 4.5 – 80
9.0 – 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
THD ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Total Harmonic Distortion fin = 1 kHz, RL = 10 kΩ, CL = 50 pF
12.0 – 80
%

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 14) THD = THDMeasured – THDSource
VIS = 4.0 VPP sine wave 4.5 0.10

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
VIS = 8.0 VPP sine wave
VIS = 11.0 VPP sine wave
*Guaranteed limits not tested. Determined by design and verified by qualification.
9.0
12.0
0.06
0.04

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TBD TBD

Figure 1a. Typical On Resistance, VCC = 2.0 V Figure 1b. Typical On Resistance, VCC = 4.5 V

TBD TBD

Figure 1c. Typical On Resistance, VCC = 6.0 V Figure 1d. Typical On Resistance, VCC = 9.0 V

PLOTTER

PROGRAMMABLE
POWER MINI COMPUTER DC ANALYZER
TBD SUPPLY
– + VCC
DEVICE
UNDER TEST

ANALOG IN COMMON OUT

GND

Figure 1e. Typical On Resistance, VCC = 12 V Figure 2. On Resistance Test Set–Up

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 MC74HC4066A

VCC

VCC VCC
GND 14 VCC 14
A ON N/C
VCC A OFF GND

SELECTED VIL SELECTED VIH

CONTROL CONTROL
7 INPUT 7 INPUT

Figure 3. Maximum Off Channel Leakage Current, Figure 4. Maximum On Channel Leakage Current,
Any One Channel, Test Set–Up Test Set–Up

VCC VOS VIS VCC VOS

14 14
fin ON fin OFF
dB dB
0.1µF CL* 0.1µF CL*
METER RL METER

SELECTED
CONTROL
SELECTED VCC INPUT
CONTROL
7 INPUT 7

*Includes all probe and jig capacitance. *Includes all probe and jig capacitance.

Figure 5. Maximum On–Channel Bandwidth Figure 6. Off–Channel Feedthrough Isolation,

Test Set–Up Test Set–Up

VCC/2 VCC VCC/2

14

RL RL
VOS
OFF/ON IS
VCC
CL*
50%
SELECTED ANALOG IN
CONTROL GND
Vin ≤ 1 MHz 7 INPUT tPLH tPHL
tr = tf = 6 ns
VCC
GND CONTROL
50%
ANALOG OUT
*Includes all probe and jig capacitance.

Figure 7. Feedthrough Noise, ON/OFF Control to Figure 8. Propagation Delays, Analog In to

Analog Out, Test Set–Up Analog Out

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 MC74HC4066A

VCC tr tf
14 VCC
90%
ANALOG IN ANALOG OUT TEST CONTROL 50%
ON POINT 10% GND
CL*
tPZL tPLZ
HIGH
IMPEDANCE
SELECTED VCC 50%
10% VOL
CONTROL
7 ANALOG
INPUT tPZH tPHZ
OUT
90% VOH
50%
*Includes all probe and jig capacitance. HIGH
IMPEDANCE

Figure 9. Propagation Delay Test Set–Up Figure 10. Propagation Delay, ON/OFF Control
to Analog Out

POSITION 1 WHEN TESTING tPHZ AND tPZH VIS

POSITION 2 WHEN TESTING tPLZ AND tPZL VCC
1
14
RL VOS
2
VCC fin ON
VCC 14 1 kΩ 0.1 µF
1
TEST OFF
ON/OFF POINT
2 VCC OR GND
CL* RL CL* RL CL*
RL
SELECTED
SELECTED
CONTROL VCC/2 VCC/2
CONTROL
INPUT
INPUT
7
7
VCC/2
*Includes all probe and jig capacitance. *Includes all probe and jig capacitance.

Figure 11. Propagation Delay Test Set–Up Figure 12. Crosstalk Between Any Two Switches,
Test Set–Up

VCC

A
VIS
14 VCC VOS
0.1 µF TO
N/C OFF/ON N/C fin ON DISTORTION
CL* METER
RL

SELECTED VCC/2
7 CONTROL SELECTED VCC
INPUT CONTROL
7
INPUT
ON/OFF CONTROL

*Includes all probe and jig capacitance.

Figure 13. Power Dissipation Capacitance Figure 14. Total Harmonic Distortion, Test Set–Up
Test Set–Up

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0
– 10 FUNDAMENTAL FREQUENCY
– 20
– 30
– 40

dBm
– 50
DEVICE
– 60
SOURCE
– 70
– 80
– 90

1.0 2.0 3.0

FREQUENCY (kHz)
Figure 15. Plot, Harmonic Distortion

APPLICATION INFORMATION below, the difference between VCC and GND is twelve volts.
Therefore, using the configuration in Figure 16, a maximum
The ON/OFF Control pins should be at VCC or GND logic analog signal of twelve volts peak–to–peak can be
levels, VCC being recognized as logic high and GND being controlled.
recognized as a logic low. Unused analog inputs/outputs When voltage transients above VCC and/or below GND
may be left floating (not connected). However, it is are anticipated on the analog channels, external diodes (Dx)
advisable to tie unused analog inputs and outputs to VCC or are recommended as shown in Figure 17. These diodes
GND through a low value resistor. This minimizes crosstalk should be small signal, fast turn–on types able to absorb the
and feedthrough noise that may be picked–up by the unused maximum anticipated current surges during clipping. An
I/O pins. alternate method would be to replace the Dx diodes with
The maximum analog voltage swings are determined by Mosorbs (Mosorb is an acronym for high current surge
the supply voltages VCC and GND. The positive peak analog protectors). Mosorbs are fast turn–on devices ideally suited
voltage should not exceed VCC. Similarly, the negative peak for precise DC protection with no inherent wear out
analog voltage should not go below GND. In the example mechanism.

VCC VCC
VCC = 12 V
14 Dx 16 Dx
+ 12 V + 12 V
ANALOG I/O ANALOG O/I
ON ON
0V 0V
Dx Dx

SELECTED SELECTED
VCC
CONTROL CONTROL
OTHER CONTROL OTHER CONTROL
INPUT INPUT
INPUTS INPUTS
7 (VCC OR GND) 7 (VCC OR GND)

Figure 16. 12 V Application Figure 17. Transient Suppressor Application

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 MC74HC4066A

+5 V +5 V

ANALOG 14 ANALOG ANALOG 14 ANALOG

SIGNALS SIGNALS SIGNALS SIGNALS

R* R* R* R* HC4066A HCT HC4066A

LSTTL/ LSTTL/ BUFFER
NMOS 5 NMOS 5
6 CONTROL 6 CONTROL
14 INPUTS 14 INPUTS
15 15
7 7
R* = 2 TO 10 kΩ

a. Using Pull-Up Resistors b. Using HCT Buffer

Figure 18. LSTTL/NMOS to HCMOS Interface

VDD = 5 V VCC = 5 TO 12 V

13 1 16 ANALOG 14 ANALOG
3 SIGNALS SIGNALS
5 HC4066A
7 MC14504 2 5
9 4 6 CONTROL
11 6 14 INPUTS
14 8 10 15 7

Figure 19. TTL/NMOS–to–CMOS Level Converter

Analog Signal Peak–to–Peak Greater than 5 V
(Also see HC4316A)

1 OF 4
CHANNEL 4
SWITCHES

1 OF 4
CHANNEL 3
SWITCHES
COMMON I/O
1 OF 4
CHANNEL 2
SWITCHES

–
1 OF 4 OUTPUT
CHANNEL 1 1 OF 4
SWITCHES INPUT + LF356 OR
SWITCHES
EQUIVALENT
0.01 µF
1 2 3 4
CONTROL INPUTS

Figure 20. 4–Input Multiplexer Figure 21. Sample/Hold Amplifier

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MC74HC4316A

Product Preview
Quad Analog Switch/
Multiplexer/Demultiplexer
with Separate Analog and
http://onsemi.com
Digital Power Supplies
High–Performance Silicon–Gate CMOS MARKING
DIAGRAMS
The MC74HC4316A utilizes silicon–gate CMOS technology to 16
achieve fast propagation delays, low ON resistances, and low PDIP–16
OFF–channel leakage current. This bilateral switch/multiplexer/ P SUFFIX HC4316AN
CASE 648 AWLYYWW
demultiplexer controls analog and digital voltages that may vary
across the full analog power–supply range (from VCC to VEE). 1
The HC4316A is similar in function to the metal–gate CMOS 16
MC14016 and MC14066, and to the High–Speed CMOS HC4066A. SOIC–16
HC4316AD
Each device has four independent switches. The device control and D SUFFIX
AWLYWW
Enable inputs are compatible with standard CMOS outputs; with CASE 751B
pullup resistors, they are compatible with LSTTL outputs. The device 1
has been designed so that the ON resistances (RON) are much more 16
linear over input voltage than RON of metal–gate CMOS analog TSSOP–16 HC43
switches. Logic–level translators are provided so that the On/Off DT SUFFIX 16A
Control and Enable logic–level voltages need only be VCC and GND, CASE 948F ALYW
while the switch is passing signals ranging between VCC and VEE. 1
When the Enable pin (active–low) is high, all four analog switches are
16
turned off.
SOEIAJ–16
• Logic–Level Translator for On/Off Control and Enable Inputs F SUFFIX 74HC4316A
AWLYWW
• Fast Switching and Propagation Speeds CASE 966

• High ON/OFF Output Voltage Ratio 1

• Diode Protection on All Inputs/Outputs A = Assembly Location

• Analog Power–Supply Voltage Range (VCC – VEE) = 2.0 to 12.0
WL or L = Wafer Lot
YY or Y = Year
Volts WW or W = Work Week
• Digital (Control) Power–Supply Voltage Range (VCC – GND) = 2.0
to 6.0 Volts, Independent of VEE ORDERING INFORMATION
• Improved Linearity of ON Resistance Device Package Shipping
• Chip Complexity: 66 FETs or 16.5 Equivalent Gates MC74HC4316AN PDIP–16 2000 / Box
MC74HC4316AD SOIC–16 48 / Rail
PIN ASSIGNMENT
MC74HC4316ADR2 SOIC–16 2500 / Reel
XA 1 16 VCC
MC74HC4316ADT TSSOP–16 96 / Rail
YA 2 15 A ON/OFF
CONTROL MC74HC4316ADTR2 TSSOP–16 2500 / Reel
YB 3 14 D ON/OFF FUNCTION TABLE
CONTROL MC74HC4316AF SOEIAJ–14 See Note 1.
XD Inputs State of
XB 4 13 1. For ordering information on the EIAJ version of
B ON/OFF On/Off Analog
5 12 YD the SOIC packages, please contact your local
CONTROL Enable Control Switch ON Semiconductor representative.
C ON/OFF 6 11 YC L H On
CONTROL
L L Off
ENABLE 7 10 XC
H X Off
GND 8 9 VEE
X = don’t care
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.

 Semiconductor Components Industries, LLC, 2000 350 Publication Order Number:

March, 2000 – Rev. 1 MC74HC4316A/D
 MC74HC4316A

LOGIC DIAGRAM

1 ANALOG 2
XA YA
SWITCH
15
A ON/OFF CONTROL LEVEL
TRANSLATOR
4 ANALOG 3
XB YB
SWITCH
5 ANALOG
B ON/OFF CONTROL LEVEL
TRANSLATOR OUTPUTS/INPUTS
10 ANALOG 11
XC YC PIN 16 = VCC
SWITCH
6 PIN 8 = GND
C ON/OFF CONTROL LEVEL PIN 9 = VEE
TRANSLATOR GND ≥ VEE
13 ANALOG 12
XD YD
SWITCH
14
D ON/OFF CONTROL LEVEL
7 TRANSLATOR
ENABLE

ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Ref. to GND) – 0.5 to + 7.0 V circuitry to guard against damage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Ref. to VEE) – 0.5 to + 14.0 due to high static voltages or electric
fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VEE Negative DC Supply Voltage (Ref. to GND) – 7.0 to + 0.5 V
be taken to avoid applications of any

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIS Analog Input Voltage VEE – 0.5 V voltage higher than maximum rated
to VCC + 0.5 voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Vin DC Input Voltage (Ref. to GND) – 0.5 to VCC + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout should be constrained to the
I DC Current Into or Out of Any Pin ± 25 mA v
range GND (Vin or Vout) VCC. v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
EIAJ/SOIC Package† 500
TSSOP Package† 450 level (e.g., either GND or VCC).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C I/O pins must be connected to a

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC or TSSOP Package) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
_C properly terminated line or bus.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
EIAJ/SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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351
 MC74HC4316A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ
Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Ref. to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VEE Negative DC Supply Voltage (Ref. to GND) – 6.0 GND V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIS Analog Input Voltage VEE VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin Digital Input Voltage (Ref. to GND) GND VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIO* Static or Dynamic Voltage Across Switch — 1.2 V
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Control or Enable Inputs) VCC = 3.0 V 0 600

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Figure 10) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input
components. The reliability of the device will be unaffected unless the Maximum Ratings are
exceeded.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Voltage, Ron = Per Spec 2.0 1.5 1.5 1.5 V
Control or Enable Inputs 3.0 2.1 2.1 2.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Voltage,

ÎÎÎ
Control or Enable Inputs
Ron = Per Spec 2.0
3.0
0.5
0.9
0.5
0.9
0.5
0.9
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Inputs
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current, Control or Enable
Vin = VCC or GND
VEE = – 6.0 V
6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Current (per Package)
Vin = VCC or GND
VIO = 0 V VEE = GND
VEE = – 6.0
6.0
6.0
2
4
20
40
40
160
µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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352
 MC74HC4316A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
VCC VEE – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Test Conditions V V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Ron Maximum “ON” Resistance Vin = VIH 2.0* 0.0 — — — Ω
VIS = VCC to VEE 45 0.0 160 200 240
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
IS 2.0 mA (Figures 1, 2) 4.5 – 4.5 90 110 130

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 – 6.0 90 110 130

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH 2.0 0.0 — — —
VIS = VCC or VEE (Endpoints) 4.5 0.0 90 115 140
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
IS 2.0 mA (Figures 1, 2) 4.5 – 4.5 70 90 105

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 – 6.0 70 90 105
∆Ron Ω

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Difference in “ON” Vin = VIH 2.0 0.0 — — —
Resistance Between Any Two VIS = 1/2 (VCC – VEE) 4.5 0.0 20 25 30
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Channels in the Same Package IS 2.0 mA 4.5 – 4.5 15 20 25

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 – 6.0 15 20 25
µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Ioff Maximum Off–Channel Vin = VIL 6.0 – 6.0 0.1 0.5 1.0
Leakage Current, Any One VIO = VCC or VEE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Channel Switch Off (Figure 3)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Ion Maximum On–Channel Vin = VIH 6.0 – 6.0 0.1 0.5 1.0 µA
Leakage Current, Any One VIS = VCC or VEE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Channel
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ (Figure 4)
*At supply voltage (VCC – VEE) approaching 2 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage
operation, it is recommended that these devices only be used to control digital signals.
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND)

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Analog Input to Analog Output

ÎÎÎ
(Figures 8 and 9)
2.0
4.5
40
6
50
8
60
9
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5 7 8

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLZ, Maximum Propagation Delay, Control or Enable to Analog Output 2.0 130 160 200 ns
tPHZ (Figures 10 and 11) 4.5 40 50 60

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 30 40 50

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZL,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZH
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Control or Enable to Analog Output

ÎÎÎ
(Figures 10 and 11)
2.0
4.5
6.0
140
40
30
175
50
40
250
60
50
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
C
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Capacitance

ÎÎÎ
ON/OFF Control
and Enable Inputs
— 10 10 10 pF

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Control Input = GND
Analog I/O
Feedthrough
—
—
35
1.0
35
1.0
35
1.0
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* 15 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC4316A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VCC VEE Limit*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Symbol Parameter Test Conditions V V 25_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
BW Maximum On–Channel Bandwidth or fin = 1 MHz Sine Wave 2.25 – 2.25 150 MHz
Minimum Frequency Response Adjust fin Voltage to Obtain 0 dBm at VOS 4.50 – 4.50 160

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Figure 5) Increase fin Frequency Until dB Meter 6.00 – 6.00 160
RL = 50 Ω, CL = 10 pF

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Reads – 3 dB

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
— Off–Channel Feedthrough Isolation fin Sine Wave 2.25 – 2.25 – 50 dB
(Figure 6) Adjust fin Voltage to Obtain 0 dBm at VIS 4.50 – 4.50 – 50

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
fin = 10 kHz, RL = 600 Ω, CL = 50 pF 6.00 – 6.00 – 50

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 2.25 – 2.25 – 40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
4.50 – 4.50 – 40
6.00 – 6.00 – 40

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
—
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Switch ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Feedthrough Noise, Control to

ÎÎÎ
ÎÎÎ
Vin 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 Ω, CL = 50 pF
2.25
4.50
– 2.25
– 4.50
60
130
mVPP

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Figure 7) 6.00 – 6.00 200

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
RL = 10 kΩ, CL = 10 pF 2.25 – 2.25 30
4.50 – 4.50 65

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
6.00 – 6.00 100

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
— Crosstalk Between Any Two fin Sine Wave 2.25 – 2.25 – 70 dB

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Switches Adjust fin Voltage to Obtain 0 dBm at VIS 4.50 – 4.50 – 70
(Figure 12) fin = 10 kHz, RL = 600 Ω, CL = 50 pF 6.00 – 6.00 – 70

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 80
– 80
– 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
THD
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Total Harmonic Distortion
(Figure 14)
fin = 1 kHz, RL = 10 kΩ, CL = 50 pF
THD = THDMeasured – THDSource
%

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIS = 4.0 VPP sine wave 2.25 – 2.25 0.10
VIS = 8.0 VPP sine wave 4.50 – 4.50 0.06

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
*Limits not tested. Determined by design and verified by qualification.
VIS = 11.0 VPP sine wave 6.00 – 6.00 0.04

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 MC74HC4316A

TBD TBD

Figure 1a. Typical On Resistance, Figure 1b. Typical On Resistance,

VCC – VEE = 2.0 V VCC – VEE = 4.5 V

TBD TBD

Figure 1c. Typical On Resistance, Figure 1d. Typical On Resistance,

VCC – VEE = 6.0 V VCC – VEE = 9.0 V

PLOTTER

PROGRAMMABLE
POWER MINI COMPUTER DC ANALYZER
SUPPLY
TBD
– + VCC
DEVICE
UNDER TEST

ANALOG IN COMMON OUT

GND VEE

Figure 1e. Typical On Resistance, Figure 2. On Resistance Test Set–Up

VCC – VEE = 12.0 V

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 MC74HC4316A

VCC

VCC VCC
VEE 16 VCC 16
A ON N/C
VCC A OFF
O/I
VEE
VIL VIH
7 SELECTED 7 SELECTED
8 CONTROL 8 CONTROL
9 INPUT 9 INPUT
VEE VEE

Figure 3. Maximum Off Channel Leakage Current, Figure 4. Maximum On Channel Leakage Current,
Any One Channel, Test Set–Up Test Set–Up

VIS
VCC VCC VCC
16 RL 16
TO dB TO dB
fin ON fin OFF
METER METER
0.1 µF RL CL* 0.1 µF RL RL CL*

VCC
7 7
SELECTED SELECTED
8 8
CONTROL CONTROL
9 9
INPUT INPUT
VEE VEE

*Includes all probe and jig capacitance. *Includes all probe and jig capacitance.

Figure 5. Maximum On–Channel Bandwidth Figure 6. Off–Channel Feedthrough Isolation,

Test Set–Up Test Set–Up

VCC
16

TEST
ON/OFF POINT VCC
RL
RL CL*
7 50%
8 ANALOG IN
9 SELECTED GND
CONTROL tPLH tPHL
VEE INPUT

CONTROL 50%
ANALOG OUT
*Includes all probe and jig capacitance.

Figure 7. Feedthrough Noise, Control to Analog Out, Figure 8. Propagation Delays, Analog In to
Test Set–Up Analog Out

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 MC74HC4316A

VCC
16 tr tf
ANALOG I/O ANALOG O/I TEST ENABLE VCC
ON POINT 50%
50 pF* CONTROL GND
tPZL tPLZ
HIGH
7 SELECTED VCC IMPEDANCE
8 50%
CONTROL 10% VOL
9 ANALOG
INPUT tPZH tPHZ
OUT 90% VOH
50%
HIGH
*Includes all probe and jig capacitance. IMPEDANCE

Figure 9. Propagation Delay Test Set–Up Figure 10. Propagation Delay, ON/OFF Control
to Analog Out

VIS
POSITION 1 WHEN TESTING tPHZ AND tPZH
1 POSITION 2 WHEN TESTING tPLZ AND tPZL
VCC
RL
2 fin 16
VCC RL
VCC 1 kΩ 0.1 µF ON
16
1 CL*
TEST ANALOG I/O
ON/OFF POINT
2
50 pF* TEST
OFF POINT
CONTROL RL CL*
OR 7
8 VCC
ENABLE
9 SELECTED
8 CONTROL
9 VEE INPUT

*Includes all probe and jig capacitance. *Includes all probe and jig capacitance.

Figure 11. Propagation Delay Test Set–Up Figure 12. Crosstalk Between Any Two Switches,
Test Set–Up (Adjacent Channels Used)

VCC

A
VIS
16 VCC VOS
10 µF 16
TO
N/C ON/OFF N/C fin ON DISTORTION
RL CL* METER

7
8 SELECTED
7
9 CONTROL SELECTED
8 VCC
INPUT CONTROL
VEE 9
INPUT
VEE
CONTROL

*Includes all probe and jig capacitance.

Figure 13. Power Dissipation Capacitance Figure 14. Total Harmonic Distortion, Test Set–Up
Test Set–Up

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 MC74HC4316A

APPLICATIONS INFORMATION
0
– 10 FUNDAMENTAL FREQUENCY
– 20
– 30
– 40

dBm
– 50
DEVICE
– 60
SOURCE
– 70
– 80
– 90
– 100
1.0 2.0 3.0
FREQUENCY (kHz)

Figure 15. Plot, Harmonic Distortion

The Enable and Control pins should be at VCC or GND Therefore, using the configuration in Figure 16, a maximum
logic levels, VCC being recognized as logic high and GND analog signal of twelve volts peak–to–peak can be
being recognized as a logic low. Unused analog controlled.
inputs/outputs may be left floating (not connected). When voltage transients above VCC and/or below VEE are
However, it is advisable to tie unused analog inputs and anticipated on the analog channels, external diodes (Dx) are
outputs to VCC or VEE through a low value resistor. This recommended as shown in Figure 17. These diodes should
minimizes crosstalk and feedthrough noise that may be be small signal, fast turn–on types able to absorb the
picked up by the unused I/O pins. maximum anticipated current surges during clipping. An
The maximum analog voltage swings are determined by alternate method would be to replace the Dx diodes with
the supply voltages VCC and VEE. The positive peak analog Mosorbs (Mosorb is an acronym for high current surge
voltage should not exceed VCC. Similarly, the negative peak protectors). Mosorbs are fast turn–on devices ideally suited
analog voltage should not go below VEE. In the example for precise dc protection with no inherent wear out
below, the difference between VCC and VEE is twelve volts. mechanism.

VCC VCC
VCC = 6 V
16 Dx 16 Dx
+6V +6V
ANALOG I/O ANALOG O/I
ON ON
–6 V –6 V VCC
Dx SELECTED Dx
+6V SELECTED CONTROL VEE
CONTROL INPUT
VEE
INPUT
ENABLE CONTROL VEE ENABLE CONTROL
VEE INPUTS INPUTS
8 (VCC OR GND) (VCC OR GND)
–6 V

Figure 16. Figure 17. Transient Suppressor Application

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 MC74HC4316A

VCC = 5 V +5 V

ANALOG 16 ANALOG ANALOG 16 ANALOG

SIGNALS SIGNALS SIGNALS SIGNALS
R* R* R* R* R*
HC4316A HCT HC4016A
VEE = 0 VEE = 0
BUFFER
TO – 6 V TO – 6 V
7 5
TTL ENABLE LSTTL/
5 AND NMOS 6 CONTROL
6 CONTROL 9 14 INPUTS 9
14 INPUTS
15 15
8 7
R* = 2 TO 10 kΩ

a. Using Pull–Up Resistors b. Using HCT Buffer

Figure 18. LSTTL/NMOS to HCMOS Interface

VCC = 12 V
12 V R1
POWER GND = 6 V
SUPPLY
R2
VEE = 0 V

R1 = R2
VCC
ANALOG ANALOG
INPUT R3 OUTPUT
SIGNAL 1 OF 4 SIGNAL 12 V
12 VPP
SWITCHES 0
C R4
R1 = R2
R3 = R4
VEE

Figure 19. Switching a 0–to–12 V Signal Using a

Single Power Supply (GND ≠ 0 V)

1 OF 4
CHANNEL 4
SWITCHES

1 OF 4
CHANNEL 3
SWITCHES
COMMON I/O
1 OF 4
CHANNEL 2
SWITCHES

–
1 OF 4 OUTPUT
CHANNEL 1 1 OF 4
SWITCHES INPUT + LF356 OR
SWITCHES
EQUIVALENT
0.01 µF
1 2 3 4
CONTROL INPUTS

Figure 20. 4–Input Multiplexer Figure 21. Sample/Hold Amplifier

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MC74HC4538A

Dual Precision
Monostable Multivibrator
(Retriggerable, Resettable)
The MC74HC4538A is identical in pinout to the MC14538B. The
device inputs are compatible with standard CMOS outputs; with http://onsemi.com
pullup resistors, they are compatible with LSTTL outputs.
This dual monostable multivibrator may be triggered by either the MARKING
positive or the negative edge of an input pulse, and produces a DIAGRAMS
precision output pulse over a wide range of pulse widths. Because the 16
PDIP–16
device has conditioned trigger inputs, there are no trigger–input rise MC74HC4538AN
N SUFFIX
and fall time restrictions. The output pulse width is determined by the 16
CASE 648
AWLYYWW
external timing components, Rx and Cx. The device has a reset 1
1
function which forces the Q output low and the Q output high, 16
regardless of the state of the output pulse circuitry. SO–16
HC4538A
• Unlimited Rise and Fall Times Allowed on the Trigger Inputs 16
D SUFFIX
AWLYWW
CASE 751B
• Output Pulse is Independent of the Trigger Pulse Width 1
1
• ± 10% Guaranteed Pulse Width Variation from Part to Part (Using A = Assembly Location
the Same Test Jig) WL = Wafer Lot
• Output Drive Capability: 10 LSTTL Loads YY = Year
• Outputs Directly Interface to CMOS, NMOS and TTL
WW = Work Week

• Operating Voltage Range: 3.0 to 6.0 V PIN ASSIGNMENT

• Low Input Current: 1.0 µA GND 1 16 VCC
• High Noise Immunity Characteristic of CMOS Devices CX1/RX1 2 15 GND
• In Compliance with the Requirements Defined by JEDEC Standard RESET 1 3 14 CX2/RX2
No. 7A A1 4 13 RESET 2
• Chip Complexity: 145 FETs or 36 Equivalent Gates B1 5 12 A2
Q1 6 11 B2
LOGIC DIAGRAM Q1 7 10 Q2
CX1 RX1 GND 8 9 Q2
VCC
FUNCTION TABLE
1 2
Inputs Outputs
4 6 Reset A B Q Q
TRIGGER A1 Q1
INPUTS B1 5 7 H H
Q1
H L

3 H X L Not Triggered
RESET 1 H H X Not Triggered
CX2 RX2
VCC H L,H, H Not Triggered
H L L,H, Not Triggered
15 14 L X X L H
X X Not Triggered
12 10
TRIGGER A2 Q2
INPUTS 11 9
B2 Q2
ORDERING INFORMATION
PIN 16 = VCC 13
RESET 2 Device Package Shipping
PIN 8 = GND
RX AND CX ARE EXTERNAL COMPONENTS MC74HC4538AN PDIP–16 2000 / Box
PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND
MC74HC4538AD SOIC–16 48 / Rail
MC74HC4538ADR2 SOIC–16 2500 / Reel

 Semiconductor Components Industries, LLC, 2000 360 Publication Order Number:

March, 2000 – Rev. 7 MC74HC4538A/D
 MC74HC4538A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin A, B, Reset ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Cx, Rx ± 30 cuit. For proper operation, Vin and
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iout DC Output Current, per Pin ± 25 mA
range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA Unused inputs must always be
tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, Plastic DIP† 750 mW level (e.g., either GND or VCC).
SOIC Package† 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Symbol ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎÎÎ
ÎÎÎ Parameter Min Max Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
VCC
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ
ÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
3.0**
0
6.0
VCC
V
V

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
tr, tf
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Input Rise and Fall Time

ÎÎÎÎÎÎ
ÎÎÎ
(Figure 7)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Rx
ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
A or B (Figure 5)

ÎÎÎÎÎÎ
ÎÎÎ
External Timing Resistor VCC < 4.5 V
—
1.0
No Limit
* kΩ

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cx ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
External Timing Capacitor
VCC ≥ 4.5 V 2.0
0
*
* µF
* The maximum allowable values of Rx and Cx are a function of the leakage of capacitor Cx, the leakage of the HC4538A, and leakage due
to board layout and surface resistance. For most applications, Cx/Rx should be limited to a maximum value of 10 µF/1.0 MΩ. Values of Cx
> 1.0 µF may cause a problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals may
occur for Rx > 1.0 MΩ.
** The HC4538A will function at 2.0 V but for optimum pulse width stability, VCC should be above 3.0 V.
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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361
 MC74HC4538A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC CHARACTERISTICS FOR THE MC54/74HC4538A

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Guaranteed Limits

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ ÎÎ
– 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎ
25_C 85_C 125_C
VCC

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Symbol Parameter Test Conditions Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
VIH Minimum High–Level Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v
Input Voltage |Iout| 20 µA 4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
VIL Maximum Low–Level Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
v
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Input Voltage |Iout| 20 µA 4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Voltage ÎÎÎ
Minimum High–Level
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
Vin = VIH or VIL

ÎÎ
|Iout| 20 µA
2.0
4.5
1.9
4.4
1.9
4.4
1.9
4.4
V

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
6.0 5.9 5.9 5.9

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Vin = VIH or VIL
v |Iout| – 4.0 mA 4.5 3.98 3.84 3.7
v
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
|Iout| – 5.2 mA 6.0 5.48 5.34 5.2

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
VOL Maximum Low–Level Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
v 20 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Output Voltage |Iout| 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
Vin = VIH or VIL

ÎÎ
|Iout| 4.0 mA 4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
|Iout| 5.2 mA 6.0 0.26 0.33 0.4
± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Iin Maximum Input Vin = VCC or GND 6.0
Leakage Current

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
(A, B, Reset)

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Iin Maximum Input Vin = VCC or GND 6.0 ± 50 ± 500 ± 500 nA

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Leakage Current
(Rx, Cx)

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ICC

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Maximum Quiescent

ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Vin = VCC or GND

ÎÎÎ ÎÎÎ
6.0 130 220 350 µA

ÎÎ
Supply Current Q1 and Q2 = Low
Iout = 0 µA

ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ
(per package)

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Standby State

ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎ
ICC Maximum Supply Vin = VCC or GND – 45_C to – 55_C to
Current Q1 and Q2 = High 25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
((per
er package)
ackage) Iout = 0 µA
Active State Pins 2 and 14 = 0.5 VCC 6.0 400 600 800 µA

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 MC74HC4538A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC CHARACTERISTICS FOR THE MC54/74HC4538A (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Guaranteed Limits

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
v ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
v ÎÎ
– 55 to
25_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
85_C

ÎÎÎ
125_C

ÎÎÎÎÎ
VCC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Symbol Parameter Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
tPLH Maximum Propagation Delay 2.0 175 220 265 ns
Input A or B to Q 4.5 35 44 53

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
(Figures 6 and 8) 6.0 30 37 45

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
tPHL Maximum Propagation Delay 2.0 195 245 295 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Input A or B to NQ 4.5 39 49 59
(Figures 6 and 8) 6.0 33 42 50

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Reset to Q

ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
Maximum Propagation Delay

ÎÎ
2.0
4.5
175
35
220
44
265
53
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
(Figures 7 and 8) 6.0 30 37 45

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
tPLH Maximum Propagation Delay 2.0 175 220 265 ns
Reset to NQ 4.5 35 44 53

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
(Figures 7 and 8) 6.0 30 37 45

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
tTLH Maximum Output Transition Time, Any Output 2.0 75 95 110 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
tTHL (Figures 7 and 8) 4.5 15 19 22
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Cin
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Maximum Input Capacitance

ÎÎÎÎÎ
(A. B, Reset)
(Cx, Rx)
— 10
25
10
25
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
10
25
pF

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Multivibrator)* 150 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING CHARACTERISTICS FOR THE MC54/74HC4538A (Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Guaranteed Limits

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ v ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
v ÎÎÎ
ÎÎÎÎÎ ÎÎ
– 55 to
25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
VCC
Volts

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
Symbol Parameter Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
trec Minimum Recovery Time, Inactive to A or B 2.0 0 0 0 ns
(Figure 7) 4.5 0 0 0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎ
ÎÎÎ
6.0 0 0 0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
tw Minimum Pulse Width, Input A or B 2.0 60 75 90 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎ
ÎÎÎ
(Figure 6) 4.5 12 15 18
6.0 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tw
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
(Figure 7) ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
Minimum Pulse Width, Reset

ÎÎ
ÎÎÎ
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
Maximum Input Rise and Fall Times, Reset

ÎÎÎ
2.0 1000 1000 1000 ns

ÎÎÎÎ
(Figure 7)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎ
ÎÎ
ÎÎÎ
4.5
6.0
500
400
500
400
500
400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
A or B 2.0
(Figure 7) 4.5 No Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ 6.0

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 MC74HC4538A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
OUTPUT PULSE WIDTH CHARACTERISTICS (CL = 50 pF)t

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Conditions Guaranteed Limits

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ ÎÎ
– 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎ
25_C 85_C 125_C
VCC

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
Symbol Parameter Timing Components Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎ
ÎÎÎ
τ Output Pulse Width* Rx = 10 kΩ, Cx = 0.1 µF 5.0 0.63 0.77 0.6 0.8 0.59 0.81 ms
(Figures 6 and 8)

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ — Pulse Width Match — — ± 5.0 %

ÎÎ
Between Circuits in the

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
same Package

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
— Pulse Width Match — — ± 10 %
Variation (Part to Part)
*For output pulse widths greater than 100 µs, typically τ = kRxCx, where the value of k may be found in Figure 1.
k, OUTPUT PULSE WIDTH CONSTANT (TYPICAL)

0.8 10 s
TA = 25°C
1s VCC = 5 V, TA = 25°C
0.7

OUTPUT PULSE WIDTH (τ )

100 ms

0.6 10 ms

1 ms
0.5 100 µs 1 MΩ

10 µs 100 kΩ
0.4
1 µs 10 kΩ
1 kΩ
0.3 100 ns
1 2 3 4 5 6 7 0.00001 0.0001 0.001 0.01 0.1 1 10 100
VCC, POWER SUPPLY VOLTAGE (VOLTS) CAPACITANCE (µF)

Figure 1. Typical Output Pulse Width Constant, k, Figure 2. Output Pulse Width versus
versus Supply Voltage Timing Capacitance
(For output pulse widths > 100 µs: τ = kRxCx)

1.1
Rx = 100 kΩ TA = 25°C
1 Cx = 1000 pF
(NORMALIZED TO 5 V NUMBER)
OUTPUT PULSE WIDTH (t)

0.9

0.8
Rx = 1 MΩ
0.7 Cx = 0.1 µF

0.6

0.5
1 2 3 4 5 6 7
VCC, POWER SUPPLY VOLTAGE (VOLTS)

Figure 3. Normalized Output Pulse Width

versus Power Supply Voltage

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 MC74HC4538A

1.1

(NORMALIZED TO 25 °C NUMBER)
1.05

OUTPUT PULSE WIDTH (τ )

1
VCC = 6 V Rx = 10 kΩ
0.95 Cx = 0.1 µF

0.9

0.85
VCC = 3 V
0.8
– 75 – 50 – 25 0 25 50 75 100 125 150
TA, AMBIENT TEMPERATURE (°C)

Figure 4. Normalized Output Pulse Width

versus Power Supply Voltage

1.03

Rx = 10 kΩ
(NORMALIZED TO 25 °C NUMBER)

1.02
Cx = 0.1 µF
OUTPUT PULSE WIDTH (τ )

1.01

1
VCC = 5.5 V
0.99

0.98 VCC = 5 V
VCC = 4.5 V
0.97
– 75 – 50 – 25 0 25 50 75 100 125 150
TA, AMBIENT TEMPERATURE (°C)

Figure 5. Normalized Output Pulse Width

versus Power Supply Voltage

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 MC74HC4538A

SWITCHING WAVEFORMS

tw(H)
VCC
50%
A GND

tw(L)

B VCC
50%
GND

tPLH τ tPLH τ

50%
Q

tPHL τ tPHL τ
Q
50%

tr tf Figure 6.

VCC
90%
A 10% GND

trr
VCC
50%
B GND

tf tf
VCC
90%
RESET 50%
10% GND
tw(L) trec
tTLH τ + trr
tPHL
90% (RETRIGGERED PULSE)
50% 50%
Q 10%

tTHL tPLH
Q
90%
50%
10%
Figure 7.

TEST POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 8. Test Circuit

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 MC74HC4538A

PIN DESCRIPTIONS
INPUTS capacitors (see the Block Diagram). Polystyrene capacitors
A1, A2 (Pins 4, 12) are recommended for optimum pulse width control.
Positive–edge trigger inputs. A rising–edge signal on Electrolytic capacitors are not recommended due to high
either of these pins triggers the corresponding multivibrator leakages associated with these type capacitors.
when there is a high level on the B1 or B2 input. GND (Pins 1 and 15)
B1, B2 (Pins 5, 11) External ground. The external timing capacitors discharge
Negative–edge trigger inputs. A falling–edge signal on to ground through these pins.
either of these pins triggers the corresponding multivibrator
OUTPUTS
when there is a low level on the A1 or A2 input.
Q1, Q2 (Pins 6, 10)
Reset 1, Reset 2 (Pins 3, 13) Noninverted monostable outputs. These pins (normally
Reset inputs (active low). When a low level is applied to low) pulse high when the multivibrator is triggered at either
one of these pins, the Q output of the corresponding the A or the B input. The width of the pulse is determined by
multivibrator is reset to a low level and the Q output is set to the external timing components, RX and CX.
a high level.
Q1, Q2 (Pins 7, 9)
CX1/RX1 and CX2/RX2 (Pins 2 and 14) Inverted monostable outputs. These pins (normally high)
External timing components. These pins are tied to the pulse low when the multivibrator is triggered at either the A
common points of the external timing resistors and or the B input. These outputs are the inverse of Q1 and Q2.
LOGIC DETAIL
(1/2 THE DEVICE)
RxCx

UPPER
REFERENCE OUTPUT
CIRCUIT LATCH
–
VCC +
Vre, UPPER

M1 LOWER
VCC REFERENCE
CIRCUIT
2 kΩ –
M2 + Q
Vre, LOWER
M3

TRIGGER CONTROL
CIRCUIT
A
C Q
TRIGGER CONTROL
CB R RESET CIRCUIT
B

RESET

POWER
ON
RESET
RESET LATCH

Figure 9.

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 MC74HC4538A

CIRCUIT OPERATION

Figure 12 shows the HC4538A configured in the TRIGGER OPERATION

retriggerable mode. Briefly, the device operates as follows The HC4538A is triggered by either a rising–edge signal
(refer to Figure 10): In the quiescent state, the external at input A (#7) or a falling–edge signal at input B (#8), with
timing capacitor, Cx, is charged to V CC. When a trigger the unused trigger input and the Reset input held at the
voltage levels shown in the Function Table. Either trigger
[
occurs, the Q output goes high and Cx discharges quickly to
the lower reference voltage (Vref Lower 1/3 V CC). Cx signal will cause the output of the trigger–control circuit to
go high (#9).
[
then charges, through Rx, back up to the upper reference
voltage (Vref Upper 2/3 V CC), at which point the The trigger–control circuit going high simultaneously
one–shot has timed out and the Q output goes low. initiates two events. First, the output latch goes low, thus
The following, more detailed description of the circuit taking the Q output of the HC4538A to a high state (#10).
operation refers to both the logic detail (Figure 9) and the Second, transistor M3 is turned on, which allows the
timing diagram (Figure 10). external timing capacitor, Cx, to rapidly discharge toward
ground (#11). (Note that the voltage across Cx appears at the
QUIESCENT STATE
input of both the upper and lower reference circuit
In the quiescent state, before an input trigger appears, the
comparator).
output latch is high and the reset latch is high (#1 in
When Cx discharges to the reference voltage of the lower
Figure 10). Thus the Q output (pin 6 or 10) of the monostable
reference circuit (#12), the outputs of both reference circuits
multivibrator is low (#2, Figure 10).
will be high (#13). The trigger–control reset circuit goes
The output of the trigger–control circuit is low (#3), and
high, resetting the trigger–control circuit flip–flop to a low
transistors M1, M2, and M3 are turned off. The external
state (#14). This turns transistor M3 off again, allowing Cx
timing capacitor, Cx, is charged to VCC (#4), and both the
to begin to charge back up toward VCC, with a time constant
upper and lower reference circuit has a low output (#5).
t = RxCx (#15). Once the voltage across Cx charges to above
In addition, the output of the trigger–control reset circuit
the lower reference voltage, the lower reference circuit will
is low.
go low allowing the monostable multivibrator to be
retriggered.
QUIESCENT TRIGGER CYCLE TRIGGER CYCLE
STATE (A INPUT) (B INPUT) RESET RETRIGGER

7
trr
TRIGGER INPUT A
(PIN 4 OR 12)

TRIGGER INPUT B
(PIN 5 OR 11) 8
24
9

TRIGGER-CONTROL 3 14
CIRCUIT OUTPUT
4 11 21 23
15 17
RX/CX INPUT 12
(PIN 2 OR 14)
Vref UPPER 25
Vref LOWER 13

UPPER REFERENCE 5 18
CIRCUIT
13

LOWER REFERENCE 6 16
CIRCUIT

RESET INPUT 20
(PIN 3 OR 13)
1

RESET LATCH 22

10

Q OUTPUT 2 19
(PIN 6 OR 10)
τ τ τ + trr
Figure 10. Timing Diagram

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 MC74HC4538A

When Cx charges up to the reference voltage of the upper occurs, the output of the reset latch goes low (#22), turning
reference circuit (#17), the output of the upper reference on transistor M1. Thus Cx is allowed to quickly charge up to
circuit goes low (#18). This causes the output latch to toggle, VCC (#23) to await the next trigger signal.
taking the Q output of the HC4538A to a low state (#19), and On power up of the HC4538A the power–on reset circuit
completing the time–out cycle. will be high causing a reset condition. This will prevent the
trigger–control circuit from accepting a trigger input during
POWER–DOWN CONSIDERATIONS
this state. The HC4538A’s Q outputs are low and the Q not
Large values of Cx may cause problems when powering
outputs are high.
down the HC4538A because of the amount of energy stored
in the capacitor. When a system containing this device is RETRIGGER OPERATION
powered down, the capacitor may discharge from VCC When used in the retriggerable mode (Figure 12), the
through the input protection diodes at pin 2 or pin 14. HC4538A may be retriggered during timing out of the
Current through the protection diodes must be limited to 30 output pulse at any time after the trigger–control circuit
mA; therefore, the turn–off time of the VCC power supply flip–flop has been reset (#24), and the voltage across Cx is
must not be faster than t = V CCC x /(30 mA). For example, above the lower reference voltage. As long as the Cx voltage
if V CC = 5.0 V and Cx = 15 µF, the VCC supply must turn off is below the lower reference voltage, the reset of the
no faster than t = (5.0 V)(15 µF)/30 mA = 2.5 ms. This is flip–flop is high, disabling any trigger pulse. This prevents
usually not a problem because power supplies are heavily M3 from turning on during this period resulting in an output
filtered and cannot discharge at this rate. pulse width that is predictable.
When a more rapid decrease of VCC to zero volts occurs, The amount of undershoot voltage on RxCx during the
the HC4538A may sustain damage. To avoid this possibility, trigger mode is a function of loop delay, M3 conductivity,
use an external damping diode, Dx, connected as shown in and V DD. Minimum retrigger time, trr (Figure 7), is a
Figure 11. Best results can be achieved if diode Dx is chosen function of 1) time to discharge Rx C x from V DD to lower
to be a germanium or Schottky type diode able to withstand reference
large current surges. voltage(T discharge);2)loopdelay(T delay);3)timetocharge
R x C x from the undershoot voltage back to the lower
RESET AND POWER ON RESET OPERATION
reference voltage (Tcharge).
A low voltage applied to the Reset pin always forces the
Figure 13 shows the device configured in the
Q output of the HC4538A to a low state.
non–retriggerable mode.
The timing diagram illustrates the case in which reset
For additional information, please see Application Note
occurs (#20) while Cx is charging up toward the reference
(AN1558/D) titled Characterization of Retrigger Time in
voltage of the upper reference circuit (#21). When a reset
the HC4538A Dual Precision Monstable Multivibrator.

DX

CX VCC

RX

Q
A
B Q

RESET

Figure 11. Discharge Protection During Power Down

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 MC74HC4538A

TYPICAL APPLICATIONS

CX RX CX RX

RISING–EDGE RISING–EDGE
VCC VCC
TRIGGER TRIGGER

Q Q
A A
B B Q
Q

B = VCC

RESET = VCC RESET = VCC

CX RX CX RX

VCC VCC
A = GND
Q
Q
A
B Q B Q

FALLING–EDGE FALLING–EDGE
TRIGGER TRIGGER
RESET = VCC RESET = VCC

Figure 12. Retriggerable Monostable Circuitry Figure 13. Non–retriggerable Monostable Circuitry

GND N/C
A = GND
RXCX
Q N/C
VCC B
Q N/C
RESET

Figure 14. Connection of Unused Section

ONE–SHOT SELECTION GUIDE

100 ns 1 µs 10 µs 100 µs 1 ms 10 ms 100 ms 1s 10 s

MC14528B
MC14536B 23 HR
MC14538B
MC14541B 5 MIN
HC4538A*

*Limited operating voltage (2 – 6 V)

TOTAL OUTPUT PULSE WIDTH RANGE

RECOMMENDED PULSE WIDTH RANGE

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MC74HC4851A,
MC74HC4852A

Analog Multiplexers/
Demultiplexers with
Injection Current Effect
http://onsemi.com
Control
Automotive Customized MARKING
DIAGRAMS
These devices are pin compatible to standard HC405x and 16
MC1405xB analog mux/demux devices, but feature injection current PDIP–16
effect control. This makes them especially suited for usage in N SUFFIX HC485xAN
AWLYYWW
automotive applications where voltages in excess of normal logic CASE 648
voltage are common. 1
The injection current effect control allows signals at disabled analog 16
input channels to exceed the supply voltage range without affecting SOIC–16
HC485xAD
the signal of the enabled analog channel. This eliminates the need for D SUFFIX AWLYWW
external diode/ resistor networks typically used to keep the analog CASE 751B
channel signals within the supply voltage range. 1
The devices utilize low power silicon gate CMOS technology. The 16
Channel Select and Enable inputs are compatible with standard CMOS SOIC–16 WIDE
HC485xADW
outputs. DW SUFFIX AWLYWW
• Injection Current Cross–Coupling Less than 1mV/mA (See Figure 9) CASE 751G

• Pin Compatible to HC405X and MC1405XB Devices 1

• Power Supply Range (VCC – GND) = 2.0 to 6.0 V 16

• In Compliance With the Requirements of JEDEC Standard No. 7A TSSOP–16 HC48

DT SUFFIX
• Chip Complexity: 154 FETs or 36 Equivalent Gates CASE 948F
5xA
ALYW

1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 380 of this data sheet.

 Semiconductor Components Industries, LLC, 1999 371 Publication Order Number:

March, 2000 – Rev. 4 MC74HC4851A/D
 MC74HC4851A, MC74HC4852A

FUNCTION TABLE – MC74HC4851A

Control Inputs
Select
13
X0 Enable C B A ON Channels
14
X1 L L L L X0
15
X2 L L L H X1
ANALOG 12 L L H L X2
INPUTS/ X3 MULTIPLEXER/ 3 COMMON
OUTPUTS X4 1 DEMULTIPLEXER X L L H H X3
OUTPUT/
5 INPUT L H L L X4
X5 L H L H X5
2
X6 L H H L X6
4
X7 L H H H X7
11 H X X X NONE
A
CHANNEL 10
SELECT B
INPUTS 9
C VCC X2 X1 X0 X3 A B C
6
ENABLE 16 15 14 13 12 11 10 9
PIN 16 = VCC
PIN 8 = GND

Figure 1. MC74HC4851A Logic Diagram

Single–Pole, 8–Position Plus Common Off

1 2 3 4 5 6 7 8
X4 X6 X X7 X5 Enable NC GND
Figure 2. MC74HC4851A 16–Lead Pinout (Top View)

FUNCTION TABLE – MC74HC4852A

Control Inputs
Select
Enable B A ON Channels
12
X0 L L L Y0 X0
14
X1 13 L L H Y1 X1
15 X SWITCH X
X2 L H L Y2 X2
11 L H H Y3 X3
X3
ANALOG COMMON H X X NONE
INPUTS/OUTPUTS 1 OUTPUTS/INPUTS
Y0 X = Don’t Care
5 3
Y1 Y SWITCH Y
2
Y2
4
Y3 VCC X2 X1 X X0 X3 A B
10
CHANNEL-SELECT A 16 15 14 13 12 11 10 9
9 PIN 16 = VCC
INPUTS B
PIN 8 = GND
6
ENABLE

Figure 3. MC74HC4852A Logic Diagram

Double–Pole, 4–Position Plus Common Off
1 2 3 4 5 6 7 8
Y0 Y2 Y Y3 Y1 Enable NC GND
Figure 4. MC74HC4852A 16–Lead Pinout (Top View)

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 MC74HC4851A, MC74HC4852A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Any Pin) (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
I DC Current, Into or Out of Any Pin ± 25 mA
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, Plastic DIP† 750 mW voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 cuit. For proper operation, Vin and
TSSOP Package† 450 Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
range GND (Vin or Vout) VCC.
Tstg Storage Temperature Range – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
TL Lead Temperature, 1 mm from Case for 10 Seconds _C tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package 260 level (e.g., either GND or VCC).
Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Any Pin) (Referenced to GND) GND VCC V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIO* Static or Dynamic Voltage Across Switch 0.0 1.2 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature Range, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tr, tf Input Rise/Fall Time VCC = 2.0 V 0 1000 ns
(Channel Select or Enable Inputs) VCC = 4.5 V 0 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ VCC = 6.0 V 0 400
*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Ron = Per Spec 2.0 1.50 1.50 1.50 V
Voltage, Channel–Select or Enable 3.0 2.10 2.10 2.10
Inputs 4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Ron = Per Spec 2.0 0.50 0.50 0.50 V
Voltage, Channel–Select or Enable 3.0 0.90 0.90 0.90
Inputs 4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA
on Digital Pins (Enable/A/B/C)
ICC Maximum Quiescent Supply Vin(digital) = VCC or GND 6.0 2 20 40 µA
Current (per Package) Vin(analog) = GND
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC4851A, MC74HC4852A

DC CHARACTERISTICS — Analog Section

Guaranteed Limit
Symbol Parameter Condition VCC –55 to 25°C ≤85°C ≤125°C Unit
Ron Maximum “ON” Resistance Vin = VIL or VIH;VIS = VCC to 2.0 1700 1750 1800 Ω
GND; IS ≤ 2.0 mA 3.0 1100 1200 1300
4.5 550 650 750
6.0 400 500 600
∆Ron Delta “ON” Resistance Vin = VIL or VIH; VIS = VCC/2 2.0 300 400 500 Ω
IS ≤ 2.0 mA 3.0 160 200 240
4.5 80 100 120
6.0 60 80 100
Ioff Maximum Off–Channel Leakage Vin = VCC or GND µA
Current, 6.0 ±0.1 ±0.5 ±1.0
Any One Channel ±0.2 ±2.0 ±4.0
Common Channel
Ion Maximum On–Channel Leakage Vin = VCC or GND µA
Channel–to–Channel 6.0 ±0.2 ±2.0 ±4.0

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbol Parameter VCC –55 to 25°C ≤85°C ≤125°C Unit
tPHL, Maximum Propagation Delay, Analog Input to Analog Output 2.0 160 180 200 ns
tPLH 3.0 80 90 100
4.5 40 45 50
6.0 30 35 40
tPHL, tPHZ,PZH Maximum Propagation Delay, Enable or Channel–Select to 2.0 260 280 300 ns
tPLH, tPLZ,PZL Analog Output 3.0 160 180 200
4.5 80 90 100
6.0 60 70 80
Cin Maximum Input Capacitance Digital Pins 10 10 10 pF
(All Switches Off) Any Single Analog Pin 35 35 35
(All Switches Off) Common Analog Pin 130 130 130
CPD Power Dissipation Capacitance Typical 5.0 20 pF

INJECTION CURRENT COUPLING SPECIFICATIONS (VCC = 5V, TA = –55°C to +125°C)

Symbol Parameter Typ Max Unit Condition
V∆out Maximum Shift of Output Voltage of Enabled Analog 0.1 1.0 mV Iin* ≤ 1mA, RS ≤ 3,9kΩ
Channel 1.0 5.0 Iin* ≤ 10mA, RS ≤ 3,9kΩ
0.5 2.0 Iin* ≤ 1mA, RS ≤ 20kΩ
5.0 20 Iin* ≤ 10mA, RS ≤ 20kΩ
* Iin = Total current injected into all disabled channels.

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 MC74HC4851A, MC74HC4852A

1100 1100
1000 1000
900 900

R on , ON RESISTANCE (OHMS)
R on , ON RESISTANCE (OHMS)

–55°C
800 800
+25°C
700 700
+125°C
600 600
500 500
–55°C
400 400
+25°C
300 300 +125°C
200 200
100 100
0 0
0.0 0.4 0.8 1.2 1.6 2.0 0.0 0.6 1.2 1.8 2.4 3.0

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 5. Typical On Resistance VCC = 2V Figure 6. Typical On Resistance VCC = 3V

660 440
600 400
540 360
R on , ON RESISTANCE (OHMS)
R on , ON RESISTANCE (OHMS)

480 320
–55°C
420 280
+25°C
360 –55°C 240
+125°C
300 200
+25°C
240 +125°C 160
180 120
120 80
60 40
0 0
0.0 0.9 1.8 2.7 3.6 4.5 0.0 1.2 2.4 3.6 4.8 6.0

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 7. Typical On Resistance VCC = 4.5V Figure 8. Typical On Resistance VCC = 6V

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 MC74HC4851A, MC74HC4852A

VCC = 5V
Iin

Vin2 < VSS or VCC < Vin2

Any Disabled Channel

VSS < Vin1 < VCC

Enabled Channel Vout = Vin1 ±V∆out
RS

Figure 9. Injection Current Coupling Specification

5V 6V
5V VCC

VCC
HC4051A Microcontroller
Sensor
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
(8x Identical Circuitry) Common Out A/D – Input

Figure 10. Actual Technology

Requires 32 passive components and one extra 6V regulator
to suppress injection current into a standard HC4051 multiplexer

5V VCC

VCC
HC4851A Microcontroller
Sensor
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
(8x Identical Circuitry) Common Out A/D – Input

Figure 11. MC74HC4851A Solution

Solution by applying the HC4851A multiplexer

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 MC74HC4851A, MC74HC4852A

PLOTTER
VCC

PROGRAMMABLE
POWER MINI COMPUTER DC ANALYZER VCC
VEE 16
SUPPLY
OFF
– + VCC VCC A
NC OFF COMMON O/I
DEVICE
UNDER TEST
VIH 6
ANALOG IN COMMON OUT
8

GND

Figure 13. Maximum Off Channel Leakage Current,

Figure 12. On Resistance Test Any One Channel, Test Set–Up
Set–Up

VCC

VCC VCC VCC

VEE 16 A 16
ANALOG I/O
OFF ON
VCC VEE N/C
OFF OFF COMMON O/I
COMMON O/I
VCC ANALOG I/O

VIH 6 VIL 6

8 8

Figure 14. Maximum Off Channel Leakage Current, Figure 15. Maximum On Channel Leakage Current,
Common Channel, Test Set–Up Channel to Channel, Test Set–Up

VCC
VCC
16
VCC
CHANNEL ON/OFF COMMON O/I
50% TEST
SELECT ANALOG I/O
POINT
OFF/ON CL*
GND
tPLH tPHL

6
ANALOG
OUT 50%
8

CHANNEL SELECT

*Includes all probe and jig capacitance

Figure 16. Propagation Delays, Channel Select Figure 17. Propagation Delay, Test Set–Up Channel
to Analog Out Select to Analog Out

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 MC74HC4851A, MC74HC4852A

VCC
16
ANALOG I/O COMMON O/I
VCC TEST
ON
ANALOG POINT
IN 50% CL*
GND
tPLH tPHL
6
ANALOG 8
OUT 50%

*Includes all probe and jig capacitance

Figure 18. Propagation Delays, Analog In Figure 19. Propagation Delay, Test Set–Up
to Analog Out Analog In to Analog Out

tf tr POSITION 1 WHEN TESTING tPHZ AND tPZH

VCC 1 POSITION 2 WHEN TESTING tPLZ AND tPZL
90%
ENABLE 50% 2
VCC
10%
GND VCC 10kΩ
tPZL tPLZ 16
HIGH 1 ANALOG I/O
IMPEDANCE ON/OFF TEST
ANALOG 50% 2 POINT
OUT 10% CL*
VOL
tPZH tPHZ
ENABLE
VOH 6
90%
ANALOG
OUT 50% 8
HIGH
IMPEDANCE

Figure 20. Propagation Delays, Enable to Figure 21. Propagation Delay, Test Set–Up
Analog Out Enable to Analog Out

VCC
A
VCC
16
ON/OFF COMMON O/I
ANALOG I/O NC
OFF/ON

6 VCC

8 11

CHANNEL SELECT

Figure 22. Power Dissipation Capacitance,

Test Set–Up

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 MC74HC4851A, MC74HC4852A

Gate = VCC
Disabled Analog Mux Input (Disabled) Common Analog Output
Vin > VCC + 0.7V Vout > VCC

P+ P+

+
+
+

N – Substrate (on VCC potential)

Figure 23. Diagram of Bipolar Coupling Mechanism

Appears if Vin exceeds VCC, driving injection current into the substrate

INJECTION 13
11 CURRENT X0
A CONTROL

INJECTION 14
CURRENT X1
CONTROL

10 INJECTION
B 15
CURRENT X2
CONTROL

INJECTION 12
CURRENT X3
CONTROL

9 INJECTION
C 1
CURRENT X4
CONTROL

INJECTION 5
CURRENT X5
CONTROL

INJECTION 2
6 CURRENT X6
ENABLE CONTROL

INJECTION 4
CURRENT X7
CONTROL

INJECTION 3
CURRENT X
CONTROL

Figure 24. Function Diagram, HC4851A

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 MC74HC4851A, MC74HC4852A

INJECTION 13
10 CURRENT X0
A CONTROL

INJECTION 14
CURRENT X1
CONTROL

9 INJECTION 15
B
CURRENT X2
CONTROL

INJECTION 12
CURRENT X3
CONTROL

INJECTION 13
CURRENT X
CONTROL

6 INJECTION
ENABLE 1
CURRENT Y0
CONTROL

INJECTION 5
CURRENT Y1
CONTROL

INJECTION 2
CURRENT Y2
CONTROL

INJECTION 4
CURRENT Y3
CONTROL

INJECTION 3
CURRENT Y
CONTROL
Figure 25. Function Diagram, HC4852A

ORDERING & SHIPPING INFORMATION

Device Package Shipping
MC74HC4851AN PDIP–16 500 Units / Unit Pak
MC74HC4851AD SOIC–16 48 Units / Rail
MC74HC4851ADR2 SOIC–16 2500 Units / Tape & Reel
MC74HC4851ADW SOIC–16 WIDE 48 Units / Rail
MC74HC4851ADWR2 SOIC–16 WIDE 1000 Units / Tape & Reel
MC74HC4851ADT TSSOP–16 96 Units / Rail
MC74HC4851ADTR2 TSSOP–16 2500 Units / Tape & Reel
MC74HC4852AN PDIP–16 500 Units / Unit Pak
MC74HC4852AD SOIC–16 48 Units / Rail
MC74HC4852ADR2 SOIC–16 2500 Units / Tape & Reel
MC74HC4852ADW SOIC–16 WIDE 48 Units / Rail
MC74HC4852ADWR2 SOIC–16 WIDE 1000 Units / Tape & Reel
MC74HC4852ADT TSSOP–16 96 Units / Rail
MC74HC4852ADTR2 TSSOP–16 2500 Units / Tape & Reel

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 CHAPTER 4
Application Notes

AN1410/D, Configuring and Applying

the MC74HC4046A
Phase–Locked Loop . . . . . . . . . . . . . 382
AN1558/D, Characterization of Retrigger Time in the
MC74HC4538A Dual Precision
Monostable Multivibrator . . . . . . . . . . 388

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AN1410/D

Configuring and Applying

the MC74HC4046A
Phase-Locked Loop
A versatile device for 0.1 to 16MHz http://onsemi.com
frequency synchronization
APPLICATION NOTE
Prepared by: Cleon Petty, Gary Tharalson & Marten Smith
Logic Application Engineers
Abstract the following information is useful for approximating a
The MC74HC4046A (hereafter designated HC4046A) design but, because of process, layout and other variables,
phase–locked loop contains three phase comparators, a there can be substantial deviation between theory and actual
voltage–controlled oscillator (VCO) and an output results. Therefore, it is highly recommended that
amplifier. The user of this document should have a copy of prototypes be built and checked before committing a
the HC4046A data sheet in ON Semiconductor Data Book design to production.
DL129 available for details of device operation and Typical applications for the HC4046A usually involve a
operating specifications. The user should also be aware that configuration such as shown in Figure 1.

Ref Osc Phase Detector Low Pass Filter VCO fo

Feedback
÷N

Figure 1. Typical Phase–Locked Loop

VCO/OUTPUT FREQUENCY and reworking it to obtain a formula that incorporates all the
The output frequency, Fo, is calculated as a function of the detail to fit the HC4046A. First, the charge time of the device
Ref Osc input and the ÷N feedback counter: for half–cycle time is obtained as follows:

Fo = Ref Osc * N (1) dt + dV CI and Fo + 2dt1

The ability of the loop to emulate the above formula
+ + 2CdV
1
makes it ideal for multiplying an input frequency by any or, Fo 2CdV I (4)
I
number up to the maximum of the VCO. The HC4046A
VCO frequency is controlled by the equation: where I and dV must be obtained for the HC4046A.
There are two components that comprise the I charge for
VCO freq = f(I * C) (2) the HC4046A VCO, I1 and I2. I1 is the current that sets the
frequency associated with the VCO input and is a function
where I is controlled by the external resistors R1 and R2 and
of R1, VCOin, and an internal current mirror that is ratioed
C by external capacitor Cext .
at 120/5 ≈ 24, resulting in the equation:
Frequency of oscillation is calculated by starting with the
familiar equation: I1 + VCO
R1
in ǒ Ǔ
120
5
(5)

I + c dV
dt
(3)

 Semiconductor Components Industries, LLC, 1999 382 Publication Order Number:

March, 2000 – Rev. 0 AN1410/D
 AN1410/D

I2 is set by R2 and adds a constant current to limit the Fo min 1. Iconstant ratio versus R1
of the VCO and is a function of Vdd, R2, and an internal

ǒ Ǔǒ Ǔ
R1 (KΩ) Iconstant ratio
current mirror of ratio 23/5, resulting in the equation:
3.0 13.5
I2 + 2Vdd
3R2
23
5
(6) 5.1
9.1
17.5
21.5
12 23.0
The dV of Equation ( 4 ) is determined by design to be ≈ 1/3 15 24.0
Vdd. Substituting this and I = I1 + I2 into Equation ( 4 ) results 30 26.5
40 27.0
in:
ǒ Ǔ ) ǒ Ǔǒ Ǔ
51 28.5
VCOin 120 2Vdd
110 29.0

+
23
R1 5 3R2 5
300 31.0
Fo Vdd
2Cext 3 The VCO calculation [Equation ( 8 )] becomes a bit more

)ǒ Ǔ
VCOin 2Vdd
accurate by adjusting the VCOin and Iconstant ratio. For
+ R1
(24)
V
3R2
(4.6) example, with R1 = 300K, R2 = ∞, Cext = 0.1µF, VCOin =
1.0V, Vdd = 4.5V, and Iconstant ratio = 31, Equation ( 8 ) yields:
2Cext 3dd

+ 2(0.1 * 10-6)(4.5 ) 2.1)

(3)(1)(31)

+
3VCOin
R1
(24) ) 2Vdd
R2
(4.6)
(7)
Fo 300K

+ 235Hz
2Cext Vdd

It was found by experiment that when the Cext potential For comparison, from Chart 14D in the HC4046A data
reaches threshold (at Vdd/3), the inversion of the charging sheet, the Fo based on measurements is approximately 270
voltage of Cext is forced below ground due to charge Hz. Thus, the calculated and measured values are not too far
coupling. Therefore, the dV is not just Vdd/3 as expected and apart taking into consideration such variables as process
the charging time must start at a point below ground which variation, temperature, and breadboard inaccuracies. The
affects t and thus, Fo. An undershoot voltage must be added Cstray of a PCB layout will affect results if the Cext is not &
to the equation for better accuracy in calculating t and Fo. Cstray. So for Cext ≤ 1000pF, adding Cstray to the Cext fixed
This modifies Equation ( 7 ) as follows: capacitance will result in better accuracy.

+ 2C
3VCOin
R1
(24) ) 2Vdd
R2
(4.6)
The gain of a VCO is calculated by knowing fmax at
VCOin max and fmin at VCOinmin and calculating the
) 3 * undershoot)
Fo
ext (Vdd following equation:
max * f min
+ VCO f max
+ 2C (V R1
)
3VCOin(Iconstant ratio) 9.2(Vdd)
R2
VCO gain
* VCOin min (9)

ext dd ) 3 * undershoot)
(8) in
+ Dfreqńvolt
Equation ( 8 ) now contains all the factors to calculate an Fo
for the HC4046A VCO. The gain of the VCO is needed to calculate a suitable loop
filter for a PLL system.
It was determined by experiment that the undershoot of
the charging waveform is a function of Cext and an on–chip Fo is determined by VCOin and is clamped as a function
parasitic diode that clamps it at a maximum of –0.7V. The of a % of Vdd. The clamp voltage generally follows the slope
size of the Cext capacitor limits the voltage and was found to of 4%/V for Vdd changes from 3.5V ≤ Vdd ≤ 6V, starting at
be near zero volts for Cstray ≈17pF ≤ Cext ≤ 30pF; the voltage 56% at Vdd = 3.5V and going to 66% at Vdd = 6V. Knowing
increases at 6 mV/pF for a 30pF ≤ Cext ≤ 150pF range of Cext. this limit point allows picking a VCOin max point a few
The on–chip diode then takes over and limits the voltage to hundred mV below it and keeps Fo in the linear range of
–0.7V. operation. It also best to pick a VCOin min point at a level
of a few hundred mV above 0V for the same reason given
It was also found that the Iconstant ratio is a function of R1
above.
and increases as R1 becomes larger. The change is attributed
to saturation of the current mirror at lower value resistances, As an example, for a Cext =1100pF, R1 = 9.1K, R2 = ∞, Vdd
and to voltage divider problems at higher value resistances =5.0V, and VCOin min = 0.25V, VCOin max can be
combined with the resistance of the small FET in the current determined and a gain calculated as follows. VCOin limit =
mirror. Experimental data shows that Iconstant ratio follows (4%/V)(1.5V) + 56% = (62%)(Vdd ) = 3.1V. So, for sake of
Table 1 somewhat. The ratio goes to 25 somewhere between linearity, choose VCOin = 2.5V. Using Equation ( 8 ), VCOin
9.1KΩ and 51KΩ, and for those limits, 25 should give min and VCOin max can be used to calculate Fo min and Fo
reasonable results. In addition, these numbers seem to hold max as follows:
for a range of Vdd of 3.0V ≤ Vdd ≤ 6V.

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 AN1410/D

Now choose a Cext of 200pF. Then, from above result,

+ 2(1100 * 10-12)(5 ) 2.1) + 113.4KHz
(3)(0.25)(21.5)
9.1K
Fo min
R1 + 200
5.28 * 10-6 + 26K
* 10-12

+ 2(1100 * 10-12)(5 ) 2.1) + 1.3MHz

(3)(2.5)(21.5)
9.1K
This appears reasonable and there are standard values for
Fo max Cext = 200pF and R1 = 27K. Using these values, Equation (
8 ) can be adjusted according to the desired Fo min, Fo max,
Then, using Equation ( 9 ), the VCO gain is: and Fo center.

VCO gain + 1.3 * 102.5–0.25

6–0.11 * 106
+ 528.9KHzńV LOW PASS FILTER DESIGN

This gain factor will be known as Kvco in the loop filter The design of low pass filters is well known and the intent
equations. here is to simply show some typical examples. Reference
should be made to the HC4046A Data Sheet and to
R2 is used in applications where a minimum output
Application Note AN535/D — “Phase–Locked Loop
frequency is desired when VCOin is 0V. It is calculated at
Fundamentals” (available through ON Semiconductor
VCOin = 0V causing Equation ( 8 ) to become:
Literature Distribution).
Fo + 2C (R2) (V9.2 (Vdd)
dd ) 3 * undershoot)
Some simple types of low pass filters are shown in
Figure 2 and Figure 3.
The additional I2 current is a constant that adds to total R1
charge current for Cext and increases the VCOin versus Fo ∅det Charge Pump Output VCOin
curve by a theoretical constant amount. In reality, the C1
amount of increase actually decreases at a slight rate as
VCOin increases. The decrease is slight and the use of
Equation ( 8 ) will give adequate accuracy for most Figure 2. Simple Low Pass Filter A
applications.
The Fmax of the HC4046A VCO was determined to be
R1
about 16MHz. Beyond 16MHz, the output logic swing tends
∅det Charge Pump Output VCOin
to reduce and is therefore somewhat useless for driving a
CMOS input. The VCO will operate at ≈ 28MHz but the R2
output has a VOL≈ 2.0V and a VOH≈ 4.5V at Vdd = 5.0V.
C1
The following table was generated to make calculation of
R1 and Cext a function of Fo with Vdd = 5V, VCOin = 1V, and
room temperature. Use of the table allows a rough estimate Figure 3. Simple Low Pass Filter B
of (R1)(Cext) for a given Fo. The final values can be adjusted
by use of Equation ( 8 ), Table 1 for Iconstant ratio, rules for The equations for calculating loop natural frequency (wn)
undershoot voltage, Vdd variations, and VCOin variations. and damping factor (d) are as follows:

Ǹ
The example below shows a typical calculation. For Filter A (Figure 2):
2. (R1)(Cext) versus Fo
wn + KøKVCO
NC1R1
R1 (Ω) Cext (pF) (R1)(Cext)
3.0K ≤ R1 ≤ 9.0K 0 ≤ Cext ≤ 30 5.40/Fo
30 ≤ Cext ≤ 150
150 ≤ Cext ≤ ∞
4.15/Fo
3.80/Fo d + Kø0.5w
KVCO
n

9.1K ≤ R1 ≤ 50K 0 ≤ Cext ≤ 30 7.50/Fo

30 ≤ Cext ≤ 150 5.77/Fo
150 ≤ Cext ≤ ∞ 5.28/Fo where K∅ = phase detector gain, KVCO = VCO gain, and N =
divide counter.

Ǹ
50K ≤ R1 ≤ 900K 0 ≤ Cext ≤ 30 9.00/Fo
30 ≤ Cext ≤ 150 6.92/Fo For Filter B (Figure 3):
150 ≤ Cext ≤ ∞ 6.34/Fo

Assume a desired value of Fo of 1MHz. From 2, choose

wn + KøKVCO
NC1(R1 R2))
an R1 range of 9.1K ≤ R1 ≤ 50K and a Cext range of > 150pF;
this condition leads to (R1)(Cext) = 5.28/Fo. Thus,
d + 0.5wn(R2C1 ) KøKNVCO) ( 10 )
(R1) (Cext) + 15.28
* 106
+ 5.28 * 10-6

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 AN1410/D

Figure 4 shows an active filter using an op amp from

Ref Osc ∅det LP Filter
Application Note AN535/D. KVCO fo
Fref (K∅) wn
R1 C1
Feedback
÷N
R1
∅det Charge OP VCOin
Pump Output AMP Figure 5. Parametized PLL

To determine N, use equation (1) for Fo min = 200KHz,

Figure 4. Op Amp Filter and Fo max = 2MHz resulting in the following:

Ǹ
N min = 200/100 = 2, and
For Figure 4, the equations become:
N max = 2000/100 = 20
wn + KøKVCO
NC1R1
( 11 ) The results so far indicate the following starting parameters:
A. A VCO with a 10:1 range is required
B. wn = Fref/10 = 10KHz
d + Kø2wKVCO
nNR1
R2 ( 12 ) C. d = 0.707
D. R2 = ∞
E. Vdd = 5.0V
+ wnC21R2 , where Op Amp gain is large The Fo center frequency ≈

From the above equations, it is possible to design a

F max ) F min + 2.0 ) 0.2 + 1.1MHz
2 2
suitable filter to meet the needs of many PLL applications.
Recalling that the clamp voltage % at Vdd = 5V is about
The inclusion of R2 in the equations for Figure 3 and
62, then Fmax VCOin limit = (0.62)(5) = 3.1V, but as
Figure 4 permits the capability to change wn and d
described earlier, this needs to be reduced by a factor to bring
separately while Figure 2 equations do not. Normally, a
it into linearity (≈ 350mV) so the final Fmax VCOin limit =
design is easier if wn and d can be chosen independently.
2.75V.
Both factors affect the loop acquisition time and stability. A
good starting value for d is 0.707 and Fref/10 for wn. For the Fmin VCOin limit pick 0.25V. This results in a
center frequency VCOin of:
Manipulation of the equations allows calculation of R1,
R2, and C1 from the other measured, calculated, or picked
parameters. For example,
Center freq VCOin + 2.75 *2 0.25 + 1.25V
R1 ) R2 + KNCøKVCO
w 2
( 13 )
From 2, for picked values of 9.1K≤R1≤50K and 30≤Cext
≤150, obtain an estimate for (R1)(Cext) of 5.77/Fo. Thus, at
1 n
the Fo center frequency,
R2 + C2d * N
1wn C1(KøKVCO)
( 14 )
(R1)(Cext) + 1.15.77 + 5.245 * 10-6
* 106

C1 + Nw K2ø(RKVCO
)R , or alternatively,
Now, a reasonable starting point is established for setting the
values of the loop filter and the VCO range. Choosing R1 =
n 1 2)
9.1K, Cext becomes

C1 + R2d * N
2wn R2(KøKVCO)
Cext + 5.2459.1K* 10-6 + 576pF WHOOPS!
Usually, C1, wn, and d are picked and the remaining This value, 576pF, is outside of the original picked range for
parameters calculated. Cext; therefore, we need to go back and pick a larger value
of R1, e.g., 42K should be sufficient. Then Cext becomes
DESIGN EXAMPLE
Cext + 5.24542K* 10-6 + 125pF
The goal is to design a phase–locked loop that has an Fref
of 100KHz, an output Fo of 1MHz center frequency, and the and now both R1 and Cext are within selected ranges.
ability to move from 200KHz to 2MHz in 100KHz steps.

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 AN1410/D

Now calculate Fmax and Fmin using Equation ( 8 ) with R1 The final values used for the desired frequency range are
1
= 42kΩ, R2 = , Vdd = 5.0V, Iconstant ratio = 27 (from 1. and 1
R1 = 42kΩ, Cext = 175pF, R2 = , VCOin max = 2.75V, and
R1 = 42kΩ), Vundershoot = 0.57V (calculated from 6pF/mV VCOin min = 0.25V.
(125pF–30pF) = 0.57V), VCOin min = 0.25V, and VCOin The next step is to determine the loop filter. Choosing a
max = 2.75V: filter like the one in Figure 3, calculate the component as
0 follows:
) R
+ (2)(125 * 10-12f) [5.0V
(3)(0.25)(27) (9.2) (5.0)

Fo min 42K
) 3(0.57V)] Kø + V4ddp + 5.0
4p
+ 0.4Vńrad
+ 70.455
20.25 + 287.4KHz wn + 100KHz
10
+ 10KHz * 2p + 62.83 * 103radńsec
* 10-6
0
)
d = 0.707 (for starters), and
R
(3)(2.75)(27) (9.2) (5.0)

) 3(0.57V)]
42K
Fo max N = 2 to 20
(2)(125 * 10-12f) [5.0V
where
+ 222.75
70.455 * 10-6
+ 3.16MHz K∅ = phase detector gain
Vdd = output swing
Fmax is > the required 2.0MHz, but the Fmin is not low Choose C1 to be 0.01µF, N = 10 for approximate
enough for required application. It is necessary to adjust mid–range Fo, and calculate R1 and R2 using Equations ( 13
either Cext or R1 to achieve required specification of 0.2 to ) and ( 14 ):
2.0MHz Fo. Since R1 = 42kΩ is a standard resistor value, try
adjusting Cext to a higher value, such as 175pF. Because Cext R1 ) R2 + KNCøKVCO
w 2
+ (0.4)(4.86 * 106)
(10)(0.01 * 10-6)(62.83 * 103)2
is now > 150pF, the Vundershoot must be adjusted to 0.7V, as 1 n
per earlier explanation:
So, + 1.944 * 106 + 4924.5W
394.76
0
(3)(0.25)(27)
)
+ (2)(175 * 10-12f) [5.0VR) 3(0.7V)]
(9.2) (5.0)

Fo min 42K
R2 + C2d * N
1wn C1(KøKVCO)

+ 104.37
20.25
* 10-6
+ 194.02KHz + (0.01 (2)(0.707) – 10
* 10-6) (62830) (0.01 * 10-6)(0.4)(4.86 * 106)

and
+ 2250.52–514.4 + 1736W
0
(3)(2.75)(27)
) R
(9.2) (5.0)
Then, R1 = 4924.5 – 1736 = 3188.5Ω.
) 3(0.7V)]
42K
Fo max
(2)(175 * 10-12f) [5.0V Since N is changeable, it is a good idea to check min and
max on wn and d. For more information on why, see
+ 104.37
222.75
* 10-6
+ 2.13MHz Application Note AN535/D or the MC4044 Data Sheet in
the MECL Data Book DL122/D. The following examples
These values are adequate for the specified application. show sample calculations for N = 2 and 20.

Ǹ
The next item to determine is the VCO gain factor, KVCO, For N = 20, use Equation ( 10 ) to calculate wn and d:
using Equation ( 9 ):
* f min + KøKVCO
+ )
f max wn min
* VCOin min
Ǹ
KVCO NC1(R1 R2)
VCOin max

* 106 * 0.194 * 106 + 774.4KHzńV

+ 2.13 2.75V + (0.4)(4.86 * 106)
KVCO
* 0.25V (20)(0.01 * 10-6)(3188.5 ) 1736)
or in radians + 44.43 * 103radńsec, or
+ (2p) (774.4 * 103) + 4.86 * 106RadńsecńV + 44.43 * 103radńsec [ 7KHz
p
2

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 AN1410/D

and and

ƪ ƫ
ƪ ƫ
d min + (0.5)(wn) R2C1 ) KøKNVCO d max + (0.5)(140.49 * 103) *
(1736)(0.01 * 10-6) ) (0.4)(4.86
2

ƪ ƫ
+ (0.5)(44.43 * 103) *
* 106)

(1736)(0.01 * 10-6) ) (0.4)(4.86

20 + 1.292
* 106) This shows the effect of changing n on loop performance and
for this application is adequate.
+ 0.6144 If the components are not what is desired, choosing a
different wn and/or d allows them to be modified.

Ǹ
For N = 2: Alternatively, picking different C, R1 or R2 and
recalculating the other parameters can be done. If the filter
+ (0.4)(4.86 * 106) does not provide adequate performance, making wn smaller
)
wn max
(2)(0.01 * 10-6)(3188.5 1736) or d larger may improve stability.

+ 140.49 * 103radńsec, or
+ 140.49 * 103radńsec + 22.36KHz
2p

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AN1558/D

Characterization of
Retrigger Time in the
HC4538A Dual Precision
Monostable Multivibrator
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Prepared by: Douglas M. Buzard, Rodolfo E. Soto APPLICATION NOTE

Introduction resistance, and the contact resistance. The
The MC74HC4538A is a monostable multivibrator interconnection resistance is heavily process
commonly used as a one–shot, or in applications that require dependent, but fortunately it is small overall and
a pulse width of reliable dimensions. The pulse width and doesn’t vary significantly from lot to lot.

ǒ Ǔ@ @
the minimum retrigger time are usually well behaved over The discharge time can be computed from:
the suggested pulse–width range of 1µs to 1 second.
However, some customers have found that in using shorter Tdischarge + Ln 3
2
Ri Cx
than recommended pulse widths the retrigger time did not
(Equation 1)
behave as it had at longer pulse widths. ON Semiconductor
has done an overall characterization of the minimum
retrigger time in an investigation of this phenomenon. Typically the value of Ri would be near 300Ω.
The retrigger time is applicable when the device is 2) Loop delay (Tdelay = constant) ranges from 20–60ns,
triggered a second time within the period of the output pulse. and is strongly correlated to VCC. This is the time for
When this happens, the output pulse remains high for a the signal coming from the lower reference circuit to
period of τ + Trr. The earliest the part can be retriggered, or reset the flip–flop, and turn off M3. The amount of
the minimum retrigger time, is the focus of this the undershoot voltage is a function of the loop delay,
characterization. A trigger pulse on A or B inputs before this and for small values of capacitance the undershoot
minimum retrigger time would be ignored. voltage is well below the lower reference voltage.
Analysis and Data 3) The time to charge RxCx from the undershoot voltage
When used in the retriggerable mode (Figure 1), the back to the lower reference voltage (Vref lower). This

@ @ ǒ) @@ Ǔ
MC74HC4538A uses an external Rx & Cx to regulate the time is given by the RxCx transient equation:

+ Rx
output pulse width, and the minimum retrigger time (Trr). 3 Vundershoot
The minimum retrigger time depends on: Tcharge Cx Ln 1
2 VCC
(Equation 2)
1) Time to discharge RxCx from VCC to (Vref lower=1/3
VCC) Tdischarge. This discharge occurs quickly where Vundershoot = (Vref lower) – Gnd. Hence the
because external resistance, Rx, does not have any retrigger time is given by:
effect on the RC time constant. The resistance in the
discharge path, as seen in Figure 2, is the Trr = Tdischarge + Tdelay + Tcharge
on–resistance of M3, and the interconnect resistance.
(Equation 3)
The interconnection resistance is dependent on the
polysilicon sheet resistance, the metal sheet

 Semiconductor Components Industries, LLC, 1999 388 Publication Order Number:

February, 2000 – Rev. 1 AN1558/D
 AN1558/D

CX RX CX RX

RISING–EDGE
VCC VCC
TRIGGER A = GND

Q Q
A
B Q B Q

B = VCC FALLING–EDGE
TRIGGER
RESET = VCC RESET = VCC

Figure 1. Retriggerable Monostable Circuitry

LOGIC DETAIL
(1/2 THE DEVICE)

RxCx

UPPER
REFERENCE OUTPUT
CIRCUIT LATCH
–
VCC +
Vref UPPER

M1 LOWER
VCC REFERENCE
CIRCUIT
2 kΩ –
M2 + Q
Vref LOWER
M3

TRIGGER CONTROL
CIRCUIT
A
C Q
TRIGGER CONTROL
CB R RESET CIRCUIT
B

RESET

POWER
ON
RESET
RESET LATCH

Figure 2. MC74HC4538A Logic Circuit Detail

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 AN1558/D

QUIESCENT TRIGGER CYCLE TRIGGER CYCLE

STATE (A INPUT) (B INPUT) RESET RETRIGGER

trr
TRIGGER INPUT A
(PIN 4 OR 12)

TRIGGER INPUT B
(PIN 5 OR 11)
TRIGGER-CONTROL
CIRCUIT OUTPUT

RX/CX INPUT
(PIN 2 OR 14)

UPPER REFERENCE
CIRCUIT

LOWER REFERENCE
CIRCUIT

RESET INPUT
(PIN 3 OR 13)

RESET LATCH

Q OUTPUT
(PIN 6 OR 10)
τ τ τ + trr

Figure 3. Timing Diagram

Design and Applications Table 1. Test Matrix

The output pulse width of the HC4538A is determined by Cx/Rx 10pF 100pF 220pF 1000pF
the external timing components, Rx and Cx, and can be
2KΩ 4.5V 4.5V 4.5V 4.5V
represented linearly as shown in Figure 10.
The array in Table 1 was generated to make a concise 10KΩ 3.0V 3.0V 3.0V 3.0V
4.5V 4.5V 4.5V 4.5V
study of the behavior for the retrigger time for short pulse
widths. A sample of 10 pieces from each of 7 non–consec– 100KΩ 3.0V 3.0V 3.0V 3.0V
utive wafer lots were tested at each condition. 4.5V 4.5V 4.5V 4.5V
The retrigger time for external capacitance that ranges 1MΩ 3.0V 3.0V 3.0V 3.0V
from 3000pF < Cx < 4.7µF, Region 3 on the graphs, can be 4.5V 4.5V 4.5V 4.5V
computed by making use of the following linear equation
(Equation 4).

@ @ @
Trr = 10z,

+ ƪ –1062.41 – (0.1236764 ) (1.13509292 )

@ @ @ @ ) @
where z VCC) (Log Cx) 3 ) – (2.875 10 –17 Rx 3 )

10 *16 Rx) ) (5.9621 10 *12 )

@ @ @ @ƫ
(3.5256 (Log Cx) 2 (Log Cx) Rx 2 ) (4.03306325 (Log Cx) 2 )

10 *11 ) (5.1513 10* (Log Cx) Rx) ) (0.02312176 )

@ @ @
(7.9452 Rx 2 ) 5
Log Rx)

ƪ (1.8339 10 *4 Rx) * (171.91718 Log Cx) ) (4.64784302 10 Cx ) 8

Equation 4. Retrigger Time for 4.7µF > Cx > 3000pF

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 AN1558/D

1.0ms

100µs

1MΩ
10µs
T rr (sec)

100kΩ
1.0µs

10KΩ
0.1µs
2KΩ
Region 1 Region 2 Region 3
0.01µs
1.0pF 10pF 100pF 1000pF 0.01µF 0.1µF 1.0µF 10µF 100µF
Cx (Farad)

Figure 4. Retrigger Time versus Timing Capacitance at VCC = 4.5V

1.0ms

100µs
T rr (sec)

1MΩ
10µs

100kΩ
1.0µs

10KΩ
Region 2
Region 1 Region 3
0.1µs
1.0pF 10pF 100pF 1000pF 0.01µF 0.1µF 1.0µF 10µF
Cx (Farad)

Figure 5. Retrigger Time versus Timing Capacitance at VCC = 3.0V

For values of 1000pF < Cx < 3000pF, the non–linear It was determined from experiment and statistical analysis
portion of the curves are converging. In this region, Region of the data that the retrigger time for small values of external
2, the equation was represented by too few measurements to capacitance within the range of 10pF < Cx < 1000pF, Region
generate a reasonably accurate equation. Therefore, the 1, can be characterized with the following linear equation
equation in Region 2 will remain underived. A value may be (Equation 5).
approximated from the graphs in Figure 4 and Figure 5.

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 AN1558/D

@ @ ) @
Trr = 10z,

+ ƪ –315.29624–(0.082881
@ @ @ @ * @
where z VCC)–(0.3146338 (Log Cx) 3 ) 4.3277 10 –16 Rx 3 )–

10 *7 ) (3.0657 10 *12 *
@ @ ƫ@ * @
(3.984 (Log Cx) 2 R x) (Log Cx) Rx 2 ) (9.467093 (Log Cx) 2 )

10 *10 * (1.124 10* )

@ @
(4.575 Rx 2 ) 5
(Log Cx) Rx ) (94.092747 Log Cx)

ƪ (1.36599588 10 8 Cx) * (1.423 10 * 5

Rx )

Equation 5. Retrigger Time for 10pF < Cx < 1000pF

Here, the same components of: value of Cx increases for the same resistance, Trr increases
as it takes longer to charge the larger capacitor. For values
Trr = Tdischarge + Tdelay + Tcharge of Rx > 10kΩ, this increasing undershoot of Vreflower and
the resultant increase in Tcharge negates any improvement in
(Equation 3)
Trr.
are still represented, but have become combined by the At small values of Cx, the circuit capacitance will also
linear regression. The constant and VCC dependent term still come into play. The size of the undershoot of Vreflower can
derive from the loop delay, and serve to shift the components vary as a function of normal process variance. This will also
along the vertical axis. The major difference between this introduce an uncertainty into Trr for these smaller values.
and the larger values of Cx is twofold. The curves and regression equations here were derived
First, over all of Region 3 the undershoot is effectively 0 statistically and only represent the mean of the variance in
volts. This results in Tcharge not contributing to Trr and the 7 non–consecutive production lots.
predictable minimum Trr occurring in Region 2. This difference in the non–zero value of Tcharge in Region
Second, as we progress to smaller values of capacitance 1 can also be seen in Figure 6 and Figure 7 as the slope of Trr
in Region 1, Cx is too small to support Vreflower as the becomes zero as the undershoot becomes zero.
charge is drained through M3. This is why the resistance of Also, note that in Figure 8 through Figure 11, this effect
Rx now plays a role in Trr. This condition creates the has no influence on the Output Pulse Width as the Pulse
undershoot of Vreflower and the time of Tcharge is then Width is controlled by RxCx and Vrefupper.
controlled by the current through Rx. This is also why as the

@ @
τ = 10z,

+ ƪ –1.0059363–(7.6336 ) (0.87653815 )
@ @ @
where z 10 –3 VCC) Log Rx)

ƪ (0.8635535 Log Cx) * (9.3203 10 *3 Log Rx Log Cx) ƫ

Equation 6. Pulse Width

Equation 6 is a linear regression equation for calculating Also, as we have stated above, as the value of Cx decreases
the pulse width and is also made from the data means. From in the non–linear region, the total capacitance becomes more
the logarithmic plots in Figure 8 through Figure 11, it can be dependent upon internal circuit capacitance. Since the
seen that there is no cubic dependency similar to Trr, even at internal circuit capacitance is process dependent, it can vary
the small values of capacitance. The pulse width is from lot to lot, and from manufacturing site to
completely controlled by the relationship between RxCx and manufacturing site. It is for this reason that the device is not
Vrefupper. This predictability of the pulse width has tempted recommended to be used in this range, as doing so would
some customers into trying to use the part for very short potentially result in inconsistent performance over large
pulse widths. Unfortunately it has also resulted in production runs. The curves represented in this applications
inconsistent performance for Trr. note were made using linear regression on a number of lots
widely separated in time, but all from the same
Summary
manufacturing site. As a result, the curves can only be
While smaller pulse widths and Trr values can be regarded as statistical means, and may not represent the
achieved, selection of the external components must take performance of any particular device the customer may
into account the introduction of undershoot of Vreflower. encounter.

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 AN1558/D

1.0E–04

0.1µF
1.0E–05

0.01µF
T rr (sec)

1.0E–06
1000pF

200pF
100pF

1.0E–07
10pF

1.0E–08
1.0E+03 1.0E+04 1.0E+05 1.0E+06
RESISTANCE (Ω)
Figure 6. Retrigger Time vs Resistance at VCC = 4.5V

1.0E–03

1.0E–04
T rr (sec)

0.1µF

1.0E–05

1000pF 200pF

0.01µF
1.0E–06
100pF
10pF

1.0E–07
1.0E+04 1.0E+05 1.0E+06
RESISTANCE (Ω)
Figure 7. Retrigger Time vs Resistance at VCC = 3.0V

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 AN1558/D

1.0E–02

1.0E–03
PULSE WIDTH (sec)

1.0E–04
1MΩ

1.0E–05
100kΩ

1.0E–06
10kΩ

2kΩ
1.0E–07
1.0E–11 1.0E–10 1.0E–09 1.0E–08 1.0E–07
Cx (Farads)

Figure 8. Pulse Width vs Timing Capacitance at VCC = 4.5V

1.0E–02

1.0E–03
PULSE WIDTH (sec)

1.0E–04 1MΩ

1.0E–05
100kΩ

1.0E–06
10kΩ

1.0E–07
1.0E–11 1.0E–10 1.0E–09 1.0E–08 1.0E–07
Cx (Farads)

Figure 9. Pulse Width vs Timing Capacitance at VCC = 3.0V

10s

1s VCC = 5 V, TA = 25°C

100ms
OUTPUT PULSE WIDTH (τ )

10ms

1ms

100µs 1 MΩ

10µs 100 kΩ

1µs 10 kΩ
1 kΩ
100ns
0.00001 0.0001 0.001 0.01 0.1 1 10 100
CAPACITANCE (µF)

Figure 10. Output Pulse Width vs Timing Capacitance

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 AN1558/D

1.0E–02

10pF
1.0E–03

100pF
PULSE WIDTH (sec)

1.0E–04

200pF
1000pF
1.0E–05

0.01µF
0.1µF

1.0E–06

1.0E–07
1.0E+04 1.0E+05 1.0E+06
RESISTANCE (Ω)

Figure 11. Pulse Width versus Resistance at VCC = 3.0V

1.0E–02

1.0E–03

10pF
PULSE WIDTH (sec)

1.0E–04

100pF
1.0E–05

200pF

1.0E–06
1000pF

0.01µF
0.1µF
1.0E–07
1.0E+03 1.0E+04 1.0E+05 1.0E+06
RESISTANCE (Ω)

Figure 12. Pulse Width versus Resistance at VCC = 4.5V

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 CHAPTER 5
Case Outlines and Ordering Information

Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 398

Case Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
ON Semiconductor Distributor and Worldwide
Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Document Definitions . . . . . . . . . . . . . . . . . . . . . . 406

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 High–Speed CMOS Family
Device Nomenclature

MC VV WWW XXXX Y
Package Type
ON Semiconductor • D for 150 mil Plastic SOIC
Circuit Identifier • DT for TSSOP
• DW for 300 mil Plastic SOIC
Temperature Range • F for 200 mil EIAJ SOIC
• 74 Series (–55 to +125°C) • N for Plastic PDIP
Function Type
• XX(X) Same Function and Pin Configuration
High–Speed CMOS
as LSTTL
Specification Identifier
• HC = Buffered High–Speed CMOS • 4XXX Same Function and Pin Configuration
• HCU = Unbuffered High–Speed CMOS* as CMOS 14000
• HCT = High–Speed CMOS TTL Compatible • 7XX(X) Variation of LSTTL or CMOS 14000
Device
*Not Available On All Devices

Case Outlines
14-Pin Packages
PDIP–14
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.

INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
N F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
–T– J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING
PLANE L 0.290 0.310 7.37 7.87
K J M ––– 10_ ––– 10_
H G D 14 PL M N 0.015 0.039 0.38 1.01

0.13 (0.005) M

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 SO–14
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
14 8 MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
–B– P 7 PL PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G MILLIMETERS INCHES
R X 45° F
DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
SEATING K M J F 0.40 1.25 0.016 0.049
D 14 PL G 1.27 BSC 0.050 BSC
PLANE
J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S
K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

TSSOP–14
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O

14X K REF NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
0.10 (0.004) M T U S V S Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
N (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE INTERLEAD
2X L/2 FLASH OR PROTRUSION. INTERLEAD FLASH OR
M PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
–U– N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
IDENT. F EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1 7 6. TERMINAL NUMBERS ARE SHOWN FOR
DETAIL E REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
0.15 (0.006) T U S
A K

ÉÉ
ÇÇ
MILLIMETERS INCHES
–V– K1 DIM MIN MAX MIN MAX

ÇÇ
ÉÉ
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
J J1 C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N–N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C –W– K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
–T– SEATING D G H DETAIL E
PLANE

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399
 SO–14 EIAJ
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 965–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
14 8 LE MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
E HE M_ 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
1 7 L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DETAIL P DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
D BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P
A MILLIMETERS INCHES
e DIM MIN MAX MIN MAX
c A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
b A1 D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
0.13 (0.005) M 0.10 (0.004) e 1.27 BSC 0.050 BSC
HE 7.40 8.20 0.291 0.323
0.50 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 1.42 ––– 0.056

16-Pin Packages
PDIP–16
N SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R

NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

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 SO–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B– P 8 PL MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8 0.25 (0.010) M B M PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
G MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45° B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– G 1.27 BSC 0.050 BSC
SEATING M J J 0.19 0.25 0.008 0.009
PLANE K 0.10 0.25 0.004 0.009
D 16 PL
M 0° 7° 0° 7°
0.25 (0.010) M T B S A S P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

SO–16 WIDE
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–03
ISSUE B

D A
q
16 9 NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
M

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.
B

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD

H

h X 45 _
M

PROTRUSION.
E
8X

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

0.25

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
1 8 CONDITION.

MILLIMETERS
16X B B DIM MIN MAX
A 2.35 2.65
0.25 M T A S B S A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60
A

e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L

SEATING
14X e PLANE L 0.50 0.90
q 0_ 7_
A1

T C

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401
 TSSOP–16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF

0.10 (0.004) M T U S V S
NOTES:
0.15 (0.006) T U S 1. DIMENSIONING AND TOLERANCING PER ANSI

ÇÇÇ
K Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
K1

ÉÉ
ÇÇÇ
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
16 9

ÉÉ
ÇÇÇ
2X L/2 OR GATE BURRS SHALL NOT EXCEED 0.15
J1 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
B SECTION N–N PROTRUSION SHALL NOT EXCEED
L –U– 0.25 (0.010) PER SIDE.
J 5. DIMENSION K DOES NOT INCLUDE DAMBAR
PIN 1 PROTRUSION. ALLOWABLE DAMBAR
IDENT. PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
1 8
MATERIAL CONDITION.
N 6. TERMINAL NUMBERS ARE SHOWN FOR
0.25 (0.010) REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
0.15 (0.006) T U S AT DATUM PLANE –W–.
A M
–V– MILLIMETERS INCHES
DIM MIN MAX MIN MAX
N A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
F C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
DETAIL E F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C –W– K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
0.10 (0.004) M 0_ 8_ 0_ 8_
–T– SEATING H DETAIL E
PLANE D G

SO–16 EIAJ
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01 NOTES:
ISSUE O 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
16 9 LE MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
E HE M_ 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
1 8 L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DETAIL P DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DAMBAR CANNOT BE LOCATED ON THE LOWER
D RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P
e A MILLIMETERS INCHES
c DIM MIN MAX MIN MAX
A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
A1 D 9.90 10.50 0.390 0.413
b E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 0.78 ––– 0.031

http://onsemi.com
402
 20-Pin Packages
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
20 11 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B 3. DIMENSION L TO CENTER OF LEAD WHEN
1 10 FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
C L FLASH.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 1.010 1.070 25.66 27.17
B 0.240 0.260 6.10 6.60
-T- K C 0.150 0.180 3.81 4.57
SEATING D 0.015 0.022 0.39 0.55
PLANE M E 0.050 BSC 1.27 BSC
F 0.050 0.070 1.27 1.77
E N G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
G F J 20 PL 0.110 0.140 2.80 3.55
K
L 0.300 BSC 7.62 BSC
D 20 PL 0.25 (0.010) M T B M
0° 15° 0° 15°
M
0.25 (0.010) M T A M N 0.020 0.040 0.51 1.01

SO–20 WIDE
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F

D
A q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
20 11 2. INTERPRET DIMENSIONS AND TOLERANCES
M

PER ASME Y14.5M, 1994.

B

X 45 _

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

H
M

PROTRUSION.
E
10X

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

0.25

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
1 10 MAXIMUM MATERIAL CONDITION.

MILLIMETERS
DIM MIN MAX
20X B B A 2.35 2.65
A1 0.10 0.25
0.25 M T A S B S B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
A H 10.05 10.55
h 0.25 0.75
L

SEATING L 0.50 0.90

PLANE q 0_ 7_
18X e A1 T C

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403
 TSSOP–20
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
0.15 (0.006) T U S 0.10 (0.004) M T U S V S Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
K

ÍÍÍÍ
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
K1 PROTRUSIONS OR GATE BURRS. MOLD FLASH

ÍÍÍÍ
20 11 OR GATE BURRS SHALL NOT EXCEED 0.15
2X L/2 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD

ÍÍÍÍ
B J J1 FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
L –U– PER SIDE.
PIN 1 5. DIMENSION K DOES NOT INCLUDE DAMBAR
IDENT SECTION N–N PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
1 10 EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
N 0.25 (0.010) 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
0.15 (0.006) T U S 7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
A M
MILLIMETERS INCHES
–V– DIM MIN MAX MIN MAX
A 6.40 6.60 0.252 0.260
N B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
F D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
DETAIL E G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
–W– J1 0.09 0.16 0.004 0.006
C K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
G
D H M 0_ 8_ 0_ 8_
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE

SO–20 EIAJ
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 967–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
LE MOLD FLASH OR PROTRUSIONS AND ARE
20 11
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
M_
E HE 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
1 10 TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DETAIL P DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
D BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P MILLIMETERS INCHES
e A DIM MIN MAX MIN MAX
c A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
D 12.35 12.80 0.486 0.504
b A1 E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 0.81 ––– 0.032

http://onsemi.com
404
 ON SEMICONDUCTOR MAJOR WORLDWIDE SALES OFFICES
UNITED STATES CANADA INTERNATIONAL (continued)
ONTARIO KOREA
ALABAMA Ottawa . . . . . . . . . . . . . . . . . . . . (613)226–3491 Seoul . . . . . . . . . . . . . . . . . . . . 82–2–3440–7200
Huntsville . . . . . . . . . . . . . . . . . . (256)464–6800 QUEBEC MALAYSIA
CALIFORNIA Montreal . . . . . . . . . . . . . . . . . . . (514)333–3300 Penang . . . . . . . . . . . . . . . . . . . . 60(4)228–2514
Irvine . . . . . . . . . . . . . . . . . . . . . . (949)753–7360
MEXICO
San Jose . . . . . . . . . . . . . . . . . . (408)749–0510 INTERNATIONAL Guadalajara . . . . . . . . . . . . . . . . 52(36)78–0750
COLORADO BRAZIL PHILIPPINES
Littleton . . . . . . . . . . . . . . . . . . . . (303)256–5884 Sao Paulo . . . . . . . . . . . . . 55(011)3030–5244 Manila . . . . . . . . . . . . . . . . . . . . (63)2 807–8455
FLORIDA CHINA PUERTO RICO
Tampa . . . . . . . . . . . . . . . . . . . . . (813)286–6181 Beijing . . . . . . . . . . . . . . . . . . . 86–10–65642288 San Juan . . . . . . . . . . . . . . . . . . (787)641–4100
GEORGIA Guangzhou . . . . . . . . . . . . . . 86–20–87537888
SINGAPORE
Atlanta . . . . . . . . . . . . . . . . . . . . (770)338–3810 Shanghai . . . . . . . . . . . . . . . . 86–21–63747668 Singapore . . . . . . . . . . . . . . . . . . . . (65)4818188
ILLINOIS FRANCE SPAIN
Chicago . . . . . . . . . . . . . . . . . . . (847)413–2500 Paris . . . . . . . . . . . . . . . . . . . . . . 33134 635900 Madrid . . . . . . . . . . . . . . . . . . . . . 34(1)457–8204
MASSACHUSETTS GERMANY or . . . . . . . . . . . . . . . . . . . . . . . . . 34(1)457–8254
Boston . . . . . . . . . . . . . . . . . . . . (781)932–9700 Munich . . . . . . . . . . . . . . . . . . . . 49 89 92103–0
SWEDEN
MICHIGAN HONG KONG Stockholm . . . . . . . . . . . . . . . . . 46(8)734–8800
Detroit . . . . . . . . . . . . . . . . . . . . . (248)347–6800 Hong Kong . . . . . . . . . . . . . . . 852–2–610–6888
TAIWAN
MINNESOTA INDIA Taipei . . . . . . . . . . . . . . . . . . . 886(2)27058000
Plymouth . . . . . . . . . . . . . . . . . . (612)249–2360 Bangalore . . . . . . . . . . . . . . . . . 91–80–5598615
THAILAND
NORTH CAROLINA ISRAEL Bangkok . . . . . . . . . . . . . . . . . . . 66(2)254–4910
Raleigh . . . . . . . . . . . . . . . . . . . . (919)870–4355 Tel Aviv . . . . . . . . . . . . . . . . . . . 972–9–9522333
UNITED KINGDOM
PENNSYLVANIA ITALY Aylesbury . . . . . . . . . . . . . . . 44 1 (296)395252
Philadelphia/Horsham . . . . . . . (215)957–4100 Milan . . . . . . . . . . . . . . . . . . . . . . . . 39(02)82201
TEXAS JAPAN
Dallas . . . . . . . . . . . . . . . . . . . . . (972)516–5100 Tokyo . . . . . . . . . . . . . . . . . . . 81–3–5487–8345

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405
 ON SEMICONDUCTOR STANDARD DOCUMENT TYPE DEFINITIONS

REFERENCE MANUAL
A Reference Manual is a publication that contains a comprehensive system or device–specific description of the structure and function
(operation) of a particular part/system; used overwhelmingly to describe the functionality of a microprocessor, microcontroller, or some
other sub–micron sized device. Procedural information in a Reference Manual is limited to less than 40 percent (usually much less).
USER’S GUIDE
A User’s Guide contains procedural, task–oriented instructions for using or running a device or product. A User’s Guide differs from
a Reference Manual in the following respects:
* Majority of information (> 60%) is procedural, not functional, in nature
* Volume of information is typically less than for Reference Manuals
* Usually written more in active voice, using second–person singular (you) than is found in Reference Manuals
* May contain photographs and detailed line drawings rather than simple illustrations that are often found in Reference Manuals
POCKET GUIDE
A Pocket Guide is a pocket–sized document that contains technical reference information. Types of information commonly found in
pocket guides include block diagrams, pinouts, alphabetized instruction set, alphabetized registers, alphabetized third–party vendors and
their products, etc.
ADDENDUM
A documentation Addendum is a supplemental publication that contains missing information or replaces preliminary information in the
primary publication it supports. Individual addendum items are published cumulatively. Addendums end with the next revision of the
primary document.
APPLICATION NOTE
An Application Note is a document that contains real–world application information about how a specific ON Semiconductor
device/product is used with other ON Semiconductor or vendor parts/software to address a particular technical issue. Parts and/or software
must already exist and be available.
A document called “Application–Specific Information” is not the same as an Application Note.
SELECTOR GUIDE
A Selector Guide is a tri–fold (or larger) document published on a regular basis (usually quarterly) by many, if not all, divisions, that
contains key line–item, device–specific information for particular product families. Some Selector Guides are published in book format
and contain previously published information.
PRODUCT PREVIEW
A Product Preview is a summary document for a product/device under consideration or in the early stages of development. The Product
Preview exists only until an “Advance Information” document is published that replaces it. The Product Preview is often used as the first
section or chapter in a corresponding reference manual. The Product Preview displays the following disclaimer at the bottom of the first
page: “ON Semiconductor reserves the right to change or discontinue this product without notice.”
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The Advance Information document is for a device that is NOT fully MC–qualified. The Advance Information document is replaced
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High-Speed CMOS Data

ON Semiconductor
ON Semiconductor

High-Speed CMOS Data

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