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Add-On Sequential

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65 views3 pages

Add-On Sequential

Uploaded by

asd
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Bit Storage Summary

SR latch Level-sensitive SR latch D latch D flip-flop


S (set) S D S
S1 S1 D latch D latch
D Q′
Dm Qm Ds Qs′
C C Q
Cm Cs Qs
Q Q Q master servant
R
R1 R1 Clk
R (reset) R
Feature: S=1 Feature: S and R only Feature: SR can’t be 11. Feature: Only loads D value
sets Q to 1, R=1 have effect when C=1. Problem: C=1 for too long present at rising clock edge,
resets Q to 0. An external circuit can will propagate new values so values can't propagate to
Problem: prevent SR=11 when through too many latches; other flip-flops during same
SR=11 yields C=1. for too short may not clock cycle. Tradeoff: uses
undefined Q, Problem: avoiding result in the bit being more gates internally, and
other glitches SR=11 can be a burden. stored. requires more external gates
may set/reset than SR—but transistors today
inadvertently. are more plentiful and cheaper.

• We considered increasingly better bit storage until we arrived at the


robust D flip-flop bit storage
Digital Design 2e
Copyright © 2010 21
Frank Vahid
3.4

Controller Design Laser timer FSM


Inputs: b; Outputs: x
• Converting FSM to sequential circuit x=0
– Circuit called controller Off b’
– Standard controller architecture
• State register stores encoding of b
x=1 x=1 x=1
current state
– e.g., Off:00, On1:01, On2:10, On3:11 On1 On2 On3
• Combinational logic computes outputs
and next state from inputs and current
state Controller for laser timer FSM
• Rising clock edge takes controller to Laser timer controller
next state b x
FSM Combinational n1 FSM
Controller logic
I O inputs outputs
Combinational
n0
FSM logic FSM s1 s0
General inputs outputs
S clk State register
form m
m-bit m
a clk
state register

Digital Design 2e N
Copyright © 2010 40
Frank Vahid
Controller Design Process
Step Description
Step 1:
Capture the Create an FSM that describes the desired behavior
Capture
FSM of the controller.
behavior
Use state register of appropriate width and combinational
2A: Set up logic. The logic’s inputs are the state register bits and the
architecture FSM inputs; outputs are next state bits and the FSM outputs.

2B: Encode Assign unique binary number (encoding) to each state.


Usually use fewest bits, assign encoding to each state by
the states counting up in binary.
Step 2:
Convert Translate FSM to truth table for combinational logic such that
to circuit 2C: Fill in the logic will generate the outputs and next state signals for
the truth table the given FSM. Ordering the inputs with state bits first makes
the correspondence between the table and the FSM clear.
2D: Implement Implement the combinational logic using any method.
combinational
logic
Digital Design 2e
Copyright © 2010 41
Frank Vahid

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