CONTENTS

Module-3

 Latches
 Flip flops
 Flip flop conversions
 Finite State Machine – design using mealy and Moore state machines
 Sequence detectors and generators design
 Shift Registers
 Counters-synchronous and asynchronous counters
 Ring and Johnson counters

Sequential Logic Circuit Design 2

 CONTENTS

Lecture-7

 Sequential Circuit Design: FSM Design (Cont…)

Sequential Logic Circuit Design 3

 BOOKS

Textbooks

1. M.Morris Mano, Michael D Ciletti, Digital Design, 5th edition, Pearson Publishers, 2013.
2. R.P. Jain, “Modern Digital Electronics”, 4th edition, TMH.

References

1. M.Morris Mano, Charles R. Kime, Tom Martin, Logic and Computer Design Fundamentals, 4th edition,
Pearson Publishers.
2. C. H. Roth and L. L. Kinney, Fundamentals of Logic Design, 5th edition, Cengage Publishers.

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Sequential Logic Circuit Design 5
 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Example:

 Design a sequential circuit specified by the

following state table using JK flip-flop.

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Solution:
Step 1: (State table)
 As the state table has two states A & B,
hence, two JK flip-flops will be used. The state
table with the JK flip-flop inputs as described
earlier in JK flip-flop excitation table is shown

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 2: (State Equations)

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 2: (State Equations)

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 3: (Logic Diagram)

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Example:

Design a sequential circuit for the following state

diagram (3-bit counter) using T flip flop.

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Solution:
Step 1: (State table)
As the state diagram has a 3-bit
counter, hence, three T flip-flops
will be used. The state table with
the T flip-flop inputs as described
earlier in T flip-flop excitation table
is shown

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 2: (State Equations)

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 3: (Logic Diagram)

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Example: Odd Parity Checker

Assert output whenever input bit stream has odd number of 1’s using the following state diagram.

Re se t

Ev en 0
[0]

1 1

Odd
[1]
0

State Diagram

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Solution:

Step 1: (State table) Step 2: (State Assignment)

Even means 0
Present State Input Next State Output
Even 0 Even 0 Odd means 1
Even 1 Odd 0 PS PI NS PO
Odd 0 Odd 1 Present State Input Next State Output
Odd 1 Even 1 0 0 0 0
0 1 1 0
Symbolic State Transition Table 1 0 1 1
1 1 0 1

Encoded State Transition Table

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN
Step 3: (State Equation) Step 4: (Logic Diagram)
PI
PS
0 1 NS
1 Input
0 D Q
NS = PS xor PI CL K PS/Output
Q
1 R
1
\Reset

PI
0 1
PS Input 1 0 0 1 1 0 1 0 1 1 1 0
0
PO = PS Clk
1 1 1
Output 1 1 1 0 1 1 0 0 1 0 1 1

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Example: Vending Machine FSM

 Deliver package of gum after 15 rupees deposited

 Single coin slot for 10 rupees (D), 5 rupees (N)
 No change (change is optional)
 Design the FSM using combinational logic and flip flops

N
Coin Vending Gum
Sensor D Open
Machine Release
Reset FSM Mechanism

Clk

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Solution:

Step 1: (State Diagram) Reset

0₹
N

5₹ D
Reuse states
N
whenever possible
D 10₹
N,D
15₹
[open]

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 2: (State Table)

Present Inputs Next Output
State D N State Open
0₹ 0 0 0₹ 0
0 1 5₹ 0
1 0 10₹ 0
1 1 X X
5₹ 0 0 5₹ 0
0 1 10₹ 0
1 0 15₹ 0
1 1 X X
10₹ 0 0 10₹ 0
0 1 15₹ 0
1 0 15₹ 0
1 1 X X
15₹ X X 15₹ 1

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 3: (State Assignment)

Present State Inputs Nex t State Output
Q1 Q0 D N D1 D0 Open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 X X X
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 X X X
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1 X X X
1 1 0 0 1 1 1
0 1 1 1 1
1 0 1 1 1
1 1 X X X

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 4: (State Equations)

DN DN DN
Q1Q0 00 01 11 10 Q1Q0 00 01 11 10 Q1Q0 00 01 11 10

00 X 1 00 1 X 00 X

01 1 X 1 01 1 X 1 01 X

11 1 1 X 1 11 1 1 X 1 11 1 1 X 1

10 1 1 X 1 10 1 X 1 10 X

D1= Q1 + D + Q0N D0= Q1N + Q1D + Q0N’ + Q0’N OPEN= Q1Q0

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 5: (Logic Diagram)

Q1
D D1 Q1
D Q
Q0 CLK Q1
R Q
N Reset OPEN
N
Q0
Q0
D0 Q0
N D Q
CLK
Q1 R Q Q0
N
Reset
Q1
Vending machine FSM implementation based
D
on D flip-flops(Moore)

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