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Publication Annexure

The document lists research publications by Vikas Mahor and Manisha Pattanaik including 6 conference publications from 2011-2015 on topics related to low power dynamic logic design and FinFET technology. It also lists 3 journal publications from 2015-2016 and 1 book published in 2014 on process variation tolerant VLSI designs. The publications focus on novel techniques for wide fan-in domino logic gates with improved noise tolerance, power, and process variation handling.

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Vikas Mahor
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579 views1 page

Publication Annexure

The document lists research publications by Vikas Mahor and Manisha Pattanaik including 6 conference publications from 2011-2015 on topics related to low power dynamic logic design and FinFET technology. It also lists 3 journal publications from 2015-2016 and 1 book published in 2014 on process variation tolerant VLSI designs. The publications focus on novel techniques for wide fan-in domino logic gates with improved noise tolerance, power, and process variation handling.

Uploaded by

Vikas Mahor
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Research Publications

Conference Publications:

1 Vikas Mahor; Manisha Pattanaik; Parashar, S.; Kumar, C.I.; Chouhan,


A. “A Novel Low Power Noise Tolerant High Performance Dynamic
Feed through Logic Design Technique,” IEEE 2011 3rd International
Symposium on Electronic System Design (ISED), , pp.118,123, 19-
21 Dec. 2011.
2 Vikas Mahor; Chouhan, A.; Manisha Pattanaik,“A novel process
variation tolerant wide fan-in dynamic OR gate with reduced con-
tention,” IEEE 5th International Conference on Computers and De-
vices for Communication (CODEC), 2012 , pp.1,4, 17-19 Dec. 2012.
3 Vikas Mahor; Manisha Pattanaik, “Highly robust FinFET based wide
Fan-in dynamic OR gate with dynamic threshold voltage control,”
IEEE 8th International Conference on Circuits, Systems, Communi-
cation and Information Technology Applications (CSCITA), 2014 ,
pp.42,47, 4-5 April 2014.
4 Vikas Mahor; Manisha Pattanaik, “A novel delay minimization tech-
nique for low leakage wide fan-in domino logic gates,” IEEE 5th
International Conference on Computers and Devices for Communi-
cation (CODEC), 2012, pp.1,4, 17-19 Dec. 2012
5 Vikas Mahor; Manisha Pattanaik, “A Process Variation Tolerant Low
Contention Keeper Design for Wide Fan-In Dynamic OR Gate,” 4th IEEE
International Symposium on Electronic System Design (ISED), 2012,
pp.151,153, 19-22 Dec. 2012
6 Neetesh Bhardwaj; Vikas Mahor; Manisha Pattanaik, “Robust Fin-
FET Based Highly Noise Immune Power Gated SRAM Circuit De-
sign” IEEE 1st International Conference on Communication Net-
works (ICCN), pp.163,168, 19-21 Nov 2015

Journal Publications:

1 Vikas Mahor, and Manisha Pattanaik “Novel NBTI Aware Approach


for Low Power FinFET Based Wide Fan-In Domino Logic.” Journal
of Low Power Electronics, ASP, vol. 11, no. 2 (2015): 225-235.
2 Vikas Mahor, and Manisha Pattanaik “Low Leakage and Highly Noise
Immune FinFET-Based Wide Fan-In Dynamic Logic Design.” Jour-
nal of Circuits, Systems and Computers, WSP, Vol. 24, no. 05
(2015): 1550073.
3 Vikas Mahor, and Manisha Pattanaik “A State-of-The-Art Current
Mirror Based Reliable Wide Fan-In FinFET Domion OR Gate De-
sign” Journal of Circuits, Systems and Signal Processing, Springer
(2016). (Accepted - In-Press)

Books:

1 Vikas Mahor, Manisha Pattanaik, Balwinder Raj, Process Variation


Tolerant VLSI Designs,ISBN: 978-3-659-64894-6.LAP Lambert Aca-
demic Publishing, November 2014.

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