Telescopic Operational Amplifier Design

Analog Circuit Design-II

Report of Final Project
Sucharitha, 0860824
Department of EECS IGP
National Chiao Tung University
Hsinchu,Taiwan
tosucharithac@gmail.com

Abstract—In this project I designed a folded telescopic Differential to single ended conversion is called
cascode amplifier circuit using cadence tool and performed
simulation to obtain gain, phase margin, gain bandwidth, slew
‘Added gain’. The input stage which has a
rate, output voltage swing for FF, SS and TT corners and differential output, and the conversion to single
compared the obtained results.. ended signals is performed in a subsequent
I. INTRODUCTION stage.
Operational amplifiers (op-amps) play a very important c. Third block is called the output buffer, which
role in designing many analog and mixed-signal provides larger output current with lower
systems. Complexity in designing of op-amps varies impedance to drive the load of the op-amp. It
from one design to another design. We can realize doesn’t show any effect on the gain. If the op-
different functions varying from the generation of dc amp is an internal component of a switched-
bias and amplification with high speed. capacitor filter, then the output load is a
Op-Amp is similar to the DC-coupled differential input
capacitor, and the buffer need not provide very
voltage device with high gain. The output obtained from
the op-amp is very large (voltage difference is million large current or very lower output impedance.
times larger than difference across its two input However, if the op-amp is at the filter output,
terminals). Large voltage gain is controlled using a then it has to drive a large capacitor and/or
feedback circuit. Op-amp acts as a comparator when resistive load. This requires large current drive
negative feedback is not used. For regeneration of cap
certain applications op-amp can act as a positive
feedback.
II. DESIGNED CIRCUIT
A. Two Stage Op-amp
Fig01: Op-Amp general structure
Two-stage op-amp block diagram shown in fig 3
Basic structure of op-amp has 3 different stages:
consist of two differential inputs and the second
a. The first stage in op-amp is input differential
stage is a common-source stage. The given
amplifier, it produces very high input differential input provides initial gain and gain is
impedance, a large CMRR and PSRR, a low increased by the second stage and hence maximizes
offset voltage, low noise and high gain. Output the output swing. The first stage of a two-stage
is single ended; it is not compulsory that the amplifier having differential inputs whose function
first stage in op-amp should have symmetrical is to convert given input voltage to current. The
second stage is basically a CS amplifier whose work
stages. Since the transistor in the input region
is to convert current to voltage. The total DC gain of
should operate in saturation region so that there this two-stage structure can be expressed
is appreciable difference in the input and output Maintaining the Integrity of the Specifications
signal of the input stages. Av = Av1 * Av2 …. (1)
b. Second stage is to perform ‘level shifting’. where,
Level shifting is used to compensate for the DC Av1: gain of first stage.
voltage change that is occurring at the input Av2: gain of source follower
stage along with that it assures exact DC bias i.e. second stage. The DC gain can be expressed as:
for the next stage. The gain that is provided by AV = Gm * Rout …. (2)
where
the input stage is not sufficient and this the Gm: trans conductance of input network
additional amplification is required. Rout: effective output resistance

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 mode rejection and power-supply rejection of such a
circuit is greatly compromised.
Moreover, the performance parameters of the op-amp
with no tail or with a tail transistor in the linear region
is sensitive to input common-mode and supply voltage
variation which is undesired in most analog cases.

Fig 2: Block diagram of two stage op-amp

Advantages:
1. It has a high output voltage swing.
Disadvantages:
1. It has compromised frequency response.
2. High power consumption due to two stages in its
Fig: 03 TCO Designed Circuit
design. In order to achieve a high gain, the differential cascode
3. It has poor negative supply PSRR at higher topologies can be used. Low-frequency gain. Av = gmN
frequency. [(gmN roN2) || (gmP roP2)], but at the cost of output swing
and adding poles.
B. Telescopic Op-amp
C. Gain Boosting

The telescopic architecture is the simplest version of a As I used pmos throughout the design gain I obtained is
two staged OTA as shown in fig2. I used the double very low to compensate that I used gain boosting
stage OTA in my design. The input differential pair technique using two stage differential amplifier. Output
injects the signal current into common gate stages. of first stage is given as input of second stage. For
Then, the circuit achieves the differential to double example, if output of first stage is A1 and second stage
ended conversion with cascode current mirror. The is A2 overall gain would be A1*A2. Thus gain is
transistors are placed one on the top of the other to increased.
create a sort of Telescopic composition. This results in D.Millers Compensation
the structure in which MOSFETs on each branch are
As my phase gain is very low and negative to
connected along a straight line like the lenses of
compensate that I used Millers compensation
refracting telescopes. Hence, this configuration is also
technique by adding Millers capacitor at the output.
known as telescopic configuration.
Phase margin has been shifted by 900 after performing
All the transistors in the telescopic amplifier should be
millers compensation.
operated in the saturation region.
In the designed circuit overall voltage swing is only III. DESIGN PROCEDURE
little more than telescopic configuration, but for this
Specifications
there is always a trade-off among cost of higher power
● Gain at dc (Av)
consumption, lower voltage gains, lower pole
frequencies, and higher noise. ● Unity gain bandwidth (GB)
1. z Folded-cascode op amps are used quite ● Load capacitance (CL)
widely, even more than telescopic topologies, ● Slew rate (SR)
because the input and outputs can be shorted ● Power Dissipation (Pdiss)
together and the choice of the input common- Design Steps:
mode level is easier. STEP1: The first step of the design gives the estimation
2. In a telescopic op amp, three voltages must be of the bias current assuming the GBW established by
defined carefully: the input CM level and the the dominant node, we have
gate bias voltages of the PMOS and NMOS
cascode transistors, whereas in folded-cascode
configurations only the latter two are critical. where Iss is the tail current.
3. In folded-cascode op amps, the capability of STEP 2: Design Tail transistor and calculate W and L
of this transistor by using the transistor in saturation.
handling input CM levels are close to one of the
The equation used is
supply rails.
Although a telescopic op-amp without the tail current
source improves the differential swing, the common
STEP 3: Calculate the bias VB of transistor using the
equation is

STEP 4: Design the differential pair of the circuit, by

assuming both of them to be working in saturation
mode. Their aspect ratios could be calculated using bias
current Iss. The equation used is

STEP 5: Calculate the common mode voltage that

allows to be in Saturation Fig: 04 Schematic diagram of designed circuit
Schematic of Folded Telescopic Amplifier
STEP 6: Design the High Compliance Current mirror (bias- circuit)
and calculate the Bias voltage that is applied to both the In this work, in bias circuit the amplifier is implemented
gates by the following equation in 0.18μm TSMC CMOS process technology

where VB1 is the bias voltage that is applied to High

Compliance current mirror, V2 is the voltage at node 2
and VTH, n is the threshold voltage. The aspect ratios
of transistors M3 and M4can be calculated by assuming
both the transistors in saturation and both are matching.
The current equation is

Where
Fig: 05 Schematic diagram of bias circuit

STEP 7: Design the Cascode Current Mirror stage IV. SIMULATION RESULTS
where there are four PMOS transistors, which are Calculating results using TT Corner
identical, and the current passing through them is the Gain:
same as the drain and gate are tied to each other. They Voltage gain is defined as the ratio of the output
all are in saturation mode. The current flowing is the voltage to the input voltage in dB. When I plotted the
same that was in the High Compliance Current Mirror graph after simulation the result I obtained is as shown
stage. The aspect ratios can be calculated by the below.
following current equation

Where

Schematic diagram of designed circuit in

cadence
In this work, the amplifier is implemented in 0.18μm
TSMC CMOS process technology
Fig. 06 Gain plot
Gain obtained as shown in the graph is 97.75dB.
Gain Band Width:
Gain band width (GBW) is taken when the plot is at zero
value, in the first graph we can see at point zero phase
margin obtained is 7.1MHz
Phase Margin:
Phase margin from the first graph is 124.4degrees
Simulation Results
 TT Corner Results Units
Simulation

Gain 97.75 dB

Phase Margin 124.4 degree

GBW 7.1 MHz

Output Voltage Swing:

Most systems employing op amps require large voltage Fig. 09: Power Consumption
swings to accommodate a wide range of signal For the overall circuit designed power consumption is
amplitudes. 72uA
Fully differential topology, the output swing is given by
2[VDD − (VOD1 + VOD3 + VCSS + |VOD5| + |VOD7|)]
where VODj denotes the overdrive voltage of Mj.
Calculating results using FF Corner

Fig. 07: Voltage Swing

After simulation, the obtained output voltage is 1.42V.
Slew Rate: Fig. 10: Gain plot using FF corner
It is the response of a linear circuit to the input step. Gain obtained as shown in the graph is 95.1dB.
Gain Band Width:
Gain band width (GBW) is taken when the plot is at zero
value, in the first graph we can see at point zero phase
margin obtained is 6.41MHz
The response to sufficiently small inputs follows the Phase Margin:
exponential of the above equation, but with large input Phase margin from the first graph is 125 degrees
steps, the output displays a linear ramp having a Simulation Results
constant slope. Under this condition, we say the op amp
experiences slewing and call the slope of the ramp the TT Corner Results Units
“slew rate.” Simulation

Gain 95.1 dB

Phase Margin 125 degree

GBW 6.41 MHz

Output Voltage Swing:

Fig. 08: Slew Rate

From the above graph slew rate obtained is 5.06V/us.
Current consumption
The picture shown below describes the power
consumption
 Fig. 11: Voltage Swing After simulation, the obtained output voltage is 1.34 V.
After simulation, the obtained output voltage is 1.57 V. It is mentioned in the red box.
It is mentioned in the red box. Slew Rate:
Slew Rate:

Fig. 15: Voltage Swing

Fig.12: Slew Rate
Graph is plotted for voltage versus time. Graph is plotted for voltage versus time.
From the above graph slew rate obtained is 3.8 V/us. From the above graph slew rate obtained is 5.17 V/us.
Calculating results using SS Corner Current consumption
The picture shown below describes the power
consumption

Fig. 13: Gain plot using SS corner

Gain obtained as shown in the graph is 103.3 dB
Gain Band Width:
Gain band width (GBW) is taken when the plot is at zero Fig. 16: Power Consumption
value, in the first graph we can see at point zero phase For the overall circuit designed power consumption is
margin obtained is 6.53MHz 85uA
V. COMPARISON TABLE
Phase Margin:
Phase margin from the first graph is 121.5 degrees
Simulation Results
TT Corner Results Units
Simulation

Gain 103.3 dB

Phase Margin 121.5 degree

GBW 6.53 MHz

Output Voltage Swing:

VI. CONCLUSION
● In this design topology, based on the table of
comparison, a folded cascode amplifier is
designed and implemented using TSMC 180
nm CMOS technology and the simulation
results were presented.
● Several trade-off issues which have influences
on the design of this amplifier are observed.
Fig. 14: Voltage Swing
These trades-offs are very important and have
to be considered during the design in order to REFERENCES
obtain the comparison table. In order to achieve [1] Achala Shukla, Ankur Girolkar, and Jagveer Verma, “review of folded
cascode & telescopic op-amp,” May 2017, Volume 4, Issue 05 JETIR
high UGF in FF corner, a certain amount of (ISSN-2349-5162)
current is required, which results in a current [2] Operational Amplifiers., National Chung-Hsing University
Department of Electrical Engineering
consumption of 200µW.