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Digital Logic Design Course and LAB Outline

This 3 credit hour course introduces fundamental concepts of digital logic including number systems and logic gates. The objectives are to explain key digital logic concepts and design combinational and sequential logic circuits. Students will understand number systems, gates, and use simplification techniques to analyze and design circuits. They will also evaluate sequential components in digital systems through laboratory experiments implementing various logic circuits.

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562 views3 pages

Digital Logic Design Course and LAB Outline

This 3 credit hour course introduces fundamental concepts of digital logic including number systems and logic gates. The objectives are to explain key digital logic concepts and design combinational and sequential logic circuits. Students will understand number systems, gates, and use simplification techniques to analyze and design circuits. They will also evaluate sequential components in digital systems through laboratory experiments implementing various logic circuits.

Uploaded by

salman
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Digital Logic Design

Course Code EE-110


Credit Hours 03+01
Contact Hours 48+48
Prerequisite None
Course Objectives
The objective of this course is to explain some fundamental concepts related to Digital logic i.e. Number
systems, Logic gates etc., and make the students able to design combinational logic circuits using SOP/ POS/
K-Map, to analyze the operation of sequential circuits and their software implantation.
Course Learning Outcomes Theory
Sr. Taxonomy
CLO Domain PLO
No Level
Understand the Fundamental concepts
PLO-1: Engineering
1 related to Digital logic i.e. Number Cognitive C2
Knowledge
systems, Logic gates e.tc.
Applying basic sequential circuit and
PLO-3: Design/Development of
2 perform analysis of Sequential logic Cognitive C3
Solutions
circuits using SOP/ POS/ K-Map.
Evaluate and analyze sequential
3 components used in typical digital Cognitive C5 PLO-4: Investigation
Systems: Registers, counters, Adders etc
Course Learning Outcomes Laboratory
Sr. Taxonomy
CLO Domain PLO
No Level
Practically check the performance of Psychomot
1 P2 PLO-2: Problem Analysis
logic gate. or
To integrate the circuits to design high Psychomot PLO-3: Design/Development of
2 P4
performance systems or Solutions
Course Outline
 Number Systems and Logic Gates: Introductory digital concepts, Programming logic devices
 Number systems and their interconversions
CLO-
 Number system arithmetic, 1’s and 2’s complement, Signed number arithmetic, Single
1
precision floating point number
 Error detection and correction techniques
 Simplification techniques: Logic Gates, Laws and rules of Boolean algebra, DE Morgan’s
theorem, SOP and POS, K-MAP
 Combinational Logic: AND OR and AND OR inverter Logic, XOR and XNOR logic
 Combinational logic
 Universal properties of NAND and NOR gates
CLO-
 Logic circuit operation using pulse waveforms
2
 Functions of combinational logic: Adder, Subtractor
 Comparator, Encoder, Decoder
 Code converter
 Multiplexer, Demultiplexer
 Even and odd parity generator and checker.
 Sequential Circuits: Latches
 Edge triggered Flip-Flops
CLO-  Flip Flop Characteristics and applications
3  555 timer
 Asynchronous counter, Synchronous counter
 Cascade Counter, Shift registers, and ALU integrated circuits.  
Recommended Books
1 Digital Systems-Principles and Applications, by Ronald J. Tocci, Neal S. Widmer, latest Edition.
2 Digital Fundamentals, by Thomas L. Floyd, latest Edition.
3 Morris Mano and Charles R. Kime, “Logic and Computer Design Fundamentals”, Prentice Hall.

Lab Outline
Sr. No Experiments
1 Introduction to ETS-7000, IDL-400, Bread Board, IC, and Jumpers.
2 Analyzing the operation of AND gate and verifying the following expressions A.B, A.B.C, A.B.C.D
using Schematic, Truth Table, and Timing Diagram using ETS-7000 Trainer and Logicly Software
3 Analyzing the operation of OR and NOT gate and verifying the following expressions A+B,
A+B+C, A+B+C+D , A’’=A, A + A’=1, A+A=A, A’ + B+ C, A’ + B + C’ using Schematic, Truth
Table, and Timing Diagram using ETS-7000 Trainer and Logicly Software
4 Analyzing the operation of NAND, NOR gate and verifying the following expressions (AB)’,
((AB)’C)’, (A+B)’, ((A+B)’+C)’ Also Verify that NAND is equal to negative OR (Demorgan’s
theorem) and NOR is equal to negative AND (Demorgan’s Theorem)
5 Analyzing the Operation of XOR, XNOR gate using 74LS86 and 74LS04 ICs and Implement the
SOP ( A’ B+A B’, A B+A’ B’) and POS ((A+B) (A’+B’), (A’+B)(A+B’))standard Forms
6 Implementation of Logic Gates (AND, OR, NAND, NOR, OR, NOT, XOR, XNOR) using Multisim
and Xilinx Softwares.
7 Designing of Half adder and Half subtractor using ETS-7000, Multisim, and Xilinx.
8 Designing 2-bit and 4-bit full Adder using ETS-7000, Multisim, and Xilinx.
9 Designing 2-bit and 4-bit full Subtractor using ETS-7000, Multisim, and Xilinx. .
10 Designing of 4-bit Encoder and Decoder using ETS-7000, Multisim, and Xilinx.
11 Designing of 4-bit Multiplexer and Demultiplexer using ETS-7000, Multisim, and Xilinx.
12 Designing of S-R and D latch using ETS-7000, Multisim, and Xilinx.
13 Designing of S-R and D Flip Flop using ETS-7000, Multisim, and Xilinx.
14 Designing of J-K Flip Flop using ETS-7000, Multisim, and Xilinx.
15 Designing of Asynchronous Counter using ETS-7000, Multisim, and Xilinx.
16 Designing of Synchronous Counter using ETS-7000, Multisim, and Xilinx.

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