Freescale Semiconductor Document Number: MC33661

Technical Data Rev. 8.0, 4/2013

Local Interconnect Network

(LIN) Enhanced Physical 33661
Interface with Selectable Slew-
Rate
LIN PHYSICAL INTERFACE
Local interconnect network (LIN) is a serial communication protocol
designed to support automotive networks in conjunction with controller
area network (CAN). As the lowest level of a hierarchical network, LIN
enables cost-effective communication with sensors and actuators
when all the features of CAN are not required. This device is powered
by SMARTMOS technology.
The 33661 is a physical layer component dedicated to automotive
LIN sub-bus applications. It offers slew-rate selection for optimized
operation at 10 kbps and 20 kbps, fast baud rate (above 100 kbps) for
test and programming modes, excellent radiated emission
performance, and safe behavior in the event of LIN bus short-to-ground
or LIN bus leakage during low power mode. EF SUFFIX (PB-FREE)
The 33661 is compatible with LIN Protocol Specification 2.0. 98ASB42564B
8-PIN SOICN
Features
• Operational from VSUP 6.0 V to 18 V DC, functional up to 27 V DC,
and handles 40 V during load dump
ORDERING INFORMATION
• Active bus waveshaping offering excellent radiated emission
performance Device
• 5.0 kV ESD on LIN bus pin (For Tape and Temperature
Package
• 30 k internal pull-up resistor Reel, add an R2 Range (TA)
Suffix)
• LIN bus short-to-ground or high leakage in Sleep mode
• -18 V to +40 V DC voltage at LIN pin MC33661PEF - 40 to 125°C 8 SOICN
• 8.0 A in Sleep mode
• Local and remote wake-up capability reported by INH and RXD pins
• 5.0 V and 3.3 V compatible digital inputs without any external 
components required
VPWR

33661
WAKE VSUP
INH
VDD

Regulator
EN
12 V MCU RXD LIN Bus
5.0 V LIN
TXD GND

Figure 1. 33661 Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006 - 2013. All rights reserved.
INTERNAL BLOCK DIAGRAM

INTERNAL BLOCK DIAGRAM

VSUP

WAKE INH 20 A
Control
EN
INH
Control

RXD 30 k

Receiver LIN

TXD
Slope GND
Control

Figure 2. 33661 Simplified Internal Block Diagram

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 PIN CONNECTIONS

PIN CONNECTIONS

RXD 1 8 INH
EN 2 7 VSUP
WAKE 3 6 LIN
TXD 4 5 GND

Figure 3. 33661 8-SOICN Pin Connections

Table 1. 33661 8-SOICN Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page page 12.
Pin Pin Name Formal Name Definition

1 RXD Data Output MCU interface that reports the state of the LIN bus voltage.

2 EN Enable Control Controls the operation mode of the interface.

3 WAKE Wake Input High-voltage input used to wake-up the device from Sleep mode.

4 TXD Data Input MCU interface to control the state of the LIN output.

5 GND Ground Device ground pin.

6 LIN LIN Bus Bidirectional pin that represents the single-wire bus transmitter and receiver.

7 VSUP Power Supply Device power supply pin.

8 INH Inhibit Output This pin can have two main functions: controlling an external switchable voltage
regulator having an inhibit input or driving a bus external resistor in the master node
application.

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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings Symbol Value Unit

ELECTRICAL RATINGS

Power Supply Voltage VSUP V

Continuous Supply Voltage 27
Transient Voltage (Load Dump) 40
WAKE DC and Transient Voltage (Through a 33 k Serial Resistor) VWAKE -18 to 40 V
Logic Voltage (RXD, TXD, EN Pins) VLOG - 0.3 to 5.5 V
LIN Bus Voltage VBUS V
DC Voltage -18 to 40
Transient (Coupled Through 1.0 nF Capacitor) -150 to 100
INH Voltage / Current
DC Voltage VINH - 0.3 to VSUP + 0.3 V
DC Current IINH 40 mA

ESD Voltage (1) VESD1 V

Human Body Model
All Pins ± 2000
LIN Pin with Respect to Ground ± 5000
Machine Model VESD2 ± 200

THERMAL RATINGS

Operating Temperature C
Ambient TA - 40 to 125
Junction TJ - 40 to 150

Storage Temperature TSTG - 55 to 150 C

Thermal Resistance, Junction to Ambient RJA 150 °C/W
Peak Package Reflow Temperature During Reflow (2), (3) TPPRT Note 3 °C
Thermal Shutdown Temperature TSHUT 150 to 200 °C
Thermal Shutdown Hysteresis Temperature THYST 8.0 to 20 °C

Notes
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 220 pF, RZAP = 0 ).
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.

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 ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 7.0 V  VSUP  18 V, - 40C  TA  125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
VSUP PIN (DEVICE POWER SUPPLY)

Supply Voltage VSUP V

Nominal DC 7.0 13.5 18.0
Functional DC, TA  25 °C 6.0 — —
Supply Current in Sleep Mode A
VSUP  13.5 V, Recessive State IS1 — 8.0 12
13.5 V < VSUP < 1.0 V IS2 — — 200
VSUP  13.5 V, Dominant State or Shorted to GND IS3 — 300 —

Supply Current in Normal, Slow, or Fast Mode MA

Bus Recessive, Excluding INH Output Current IS(REC) — 4.0 6.0
Bus Dominant, Total Bus Load > 500 , Excluding INH Output IS(DOM) — 6.0 8.0
Current

RXD OUTPUT PIN (LOGIC)

Low Level Output Voltage VOL V

IIN  1.5 mA 0.0 — 0.9

High Level Output Voltage VOH V

VEN = 5.0 V, IOUT  250 A 4.25 — 5.25
VEN = 3.3 V, IOUT  250 A 3.0 — 3.5

TXD INPUT PIN (LOGIC)

Low Level Input Voltage VIL — — 1.2 V

High Level Input Voltage VIH 2.5 — — V
Input Threshold Voltage Hysteresis VINHYST 100 300 800 mV
Pull-up Current Source IPU A
VEN = 5.0 V, 1.0 V < VTXD < 3.5 V - 60 - 35 - 20

EN INPUT PIN (LOGIC)

Low Level Input Voltage VIL — — 1.2 V

High Level Input Voltage VIH 2.5 — — V
Input Voltage Threshold Hysteresis VINHYST 100 300 800 mV
Low Level Input Current IIL A
VIN = 1.0 V 5.0 20 30

High Level Input Current IIH A

VIN = 4.0 V — 20 40

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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 7.0 V  VSUP  18 V, - 40C  TA  125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
LIN PIN (VOLTAGE EXPRESSED VERSUS VSUP VOLTAGE)

Low Level Bus Voltage (Dominant State) VDOM V

External Bus Pull-up 500  — — 1.4
High Level Bus Voltage (Recessive State) VREC V
TXD HIGH, IOUT = 1.0 A VSUP - 1.0 — —

Internal Pull-up Resistor to VSUP (Normal mode) RPU 20 30 47 k

Internal Pull-up Current Source (Sleep mode) IPU — 20 — A
Overcurrent Shutdown Threshold IOV-CUR 50 75 150 mA
Leakage Current to GND ILEAK
Recessive State, 8.0 V  VSUP  18 V, 8.0 V  VLIN  18 V 0 3.0 20 A
GND Disconnected, VGND = VSUP, VLIN at - 18 V - 1.0 — 1.0 mA
VSUP Disconnected, VLIN at +18 V — 1.0 10 A

LIN Receiver, Low Level Input Voltage VLINL V

TXD HIGH, RXD LOW 0.0 VSUP — 0.4 VSUP
LIN Receiver, High Level Input Voltage VLINH V
TXD HIGH, RXD HIGH 0.6 VSUP — VSUP
LIN Receiver Threshold Center VLINTH V
(VLINH - VLINL) / 2 0.475 VSUP 0.5 VSUP 0.525 VSUP

LIN Receiver Input Voltage Hysteresis VLINHYST V

VLINH - VLINL — — 0.175 VSUP

LIN Wake-up Threshold Voltage VLINWU — 0.5 VSUP — V

INH OUTPUT PIN

Driver ON Resistance (Normal mode) INHON — 35 70 

Leakage Current (Sleep mode) ILEAK A
0.0 V < VINH < VSUP 0 — 5.0

WAKE INPUT PIN

Typical Wake-up Threshold Voltage (EN = 0 V, 7.0 V  VSUP  18 V) (5) VWUTH V

HIGH-to-LOW Transition 0.3 VSUP 0.43 VSUP 0.55 VSUP
LOW-to-HIGH Transition 0.4 VSUP 0.55 VSUP 0.65 VSUP
Wake-up Threshold Voltage Hysteresis VWUHYST 0.1 VSUP 0.16 VSUP 0.2 VSUP V
WAKE Input Current IWU A
VWAKE < 27 V — 1.0 5.0

Notes
4. This parameter is guaranteed by design; however, it is not production tested.
5. When VSUP > 18 V, the wake-up voltage thresholds remain identical to the wake-up thresholds at 18 V.

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 ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 7.0 V  VSUP  18 V, - 40C  TA  125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
LIN OUTPUT TIMING CHARACTERISTICS FOR NORMAL MODE

Dominant Propagation Delay Time TXD to LIN (6) s

Measurement Threshold (50% TXD to 58.1% VSUP) t DOM (MIN) — — 50
Measurement Threshold (50% TXD to 28.4% VSUP) t DOM (MAX) — — 50

Recessive Propagation Delay Time TXD to LIN (6) s

Measurement Threshold (50% TXD to 42.2% VSUP) t REC (MIN) — — 50
Measurement Threshold (50% TXD to 74.4% VSUP) t REC (MAX) — — 50

Propagation Delay Time Symmetry s

t DOM (MIN) to t REC (MAX) dt1 - 10.44 — 8.12
t DOM (MAX) to t REC (MIN) dt2 - 10.44 — 8.12

LIN OUTPUT TIMING CHARACTERISTICS FOR SLOW MODE

Dominant Propagation Delay Time TXD to LIN (6) s

Measurement Threshold (50% TXD to 61.6% VSUP) t DOM (MIN) — — 100
Measurement Threshold (50% TXD to 25.1% VSUP) t DOM (MAX) — — 100

Recessive Propagation Delay Time TXD to LIN (6) s

Measurement Threshold (50% TXD to 38.9% VSUP) t REC (MIN) — — 100
Measurement Threshold (50% TXD to 77.8% VSUP) t REC (MAX) — — 100

Propagation Delay Time Symmetry s

t DOM (MIN) to t REC (MAX) dt1S - 21.88 — 17.44
t DOM (MAX) to t REC (MIN) dt 2S - 21.88 — 17.44

LIN OUTPUT DRIVER FAST MODE

LIN Fast Slew Rate (Programming Mode) dv/dt fast V/s

Fast Slew Rate — 15 —

LIN PIN

Over-current Shutdown Delay Time (7) t OV-DELAY — 10 — s

LIN RECEIVER CHARACTERISTICS

Receiver Dominant Propagation Delay Time (8) t RL s
LIN LOW to RXD LOW — 3.5 6.0
Receiver Recessive Propagation Delay Time (8) t RH s
LIN HIGH to RXD HIGH — 3.5 6.0
Receiver Propagation Delay Time Symmetry t R-SYM s
t RL - t RH - 2.0 — 2.0

Notes
6. 7.0 V  VSUP  18 V. Bus load R0 and C0: 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 .
7. This parameter is guaranteed by design; however, it is not production tested.
8. Measured between LIN signal threshold VLINL or VLINH and 50% of RXD signal.

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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 7.0 V  VSUP  18 V, - 40C  TA  125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SLEEP MODE AND WAKE-UP TIMINGS

EN Pin Wake-up Time (9) t LWUE — 5.0 15 s

(10)
WAKE Pin Filter Time t WF 10 — 70 s
LIN Pin Wake-up Filter Time (LIN Bus Wake-Up) (11)
t WUF 40 70 120 s
Sleep Mode Delay Time (12)
t SD s
EN HIGH-to-LOW 50 — —
Delay for INH Turning off When Device Enters in Sleep Mode(16), (17) tSD_INH s
EN HIGH-to-LOW and INH HIGH-to-LOW — — 50
Delay Time Between EN and TXD for Mode Selection (13), (14) t D_MS 5.0 — — s
Delay Time Between First TXD after Device Mode Selection (13), (14) t D_COM 50 — — s

FAST BAUD RATE TIMING

Delay Entering Fast Baud Rate Using Toggle Function (15) t1 s

EN LOW to EN HIGH — — 35
Delay on EN Pin Resetting Fast Baud Rate to Previous Baud Rate (15) t2 s
EN LOW to EN HIGH — — 5.0

Notes
9. See Figures 7 and 8, 10.
10. See Figures 9 and 10, 10.
11. See Figures 11 and 12, 11.
12. See Figure 14a, 11.
13. See Figures 7 through 12, pp. 10–11.
14. This parameter is guaranteed by design; however, it is not production tested.
15. See Figure 13, 11.
16. No capacitor is connected to the INH pin. Measurement is done between the EN HIGH-to-LOW transition at 80% of INH voltage.
17. See Figure 14b, 11.

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 ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS

TIMING DIAGRAMS

TXD
Recessive State

VREC t REC(MAX)
LIN 74.4% VSUP
58.1% VSUP
t DOM(MIN)
40% VSUP 60% VSUP

42.2% VSUP
28.4% VSUP
t DOM(MAX) VDOM
Dominant State
t REC(MIN)
RXD

tRL tRH

Figure 4. Normal Mode Bus Timing Characteristics

TXD
Recessive State

VREC t REC(MAX)
LIN 77.8% VSUP
61.6% VSUP
t DOM(MIN)
40% VSUP 60% VSUP

38.9% VSUP
25.1% VSUP
t DOM(MAX) VDOM
Dominant State
t REC(MIN)
RXD

t RL t RH

Figure 5. Slow Mode Bus Timing Characteristics

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ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS

VSUP

VSUP
TXD R0

RXD LIN
GND C0

Note R0 and C0: 1.0 k/1.0 nF, 660 /6.8 nF, and 500 /10 nF.

Figure 6. Test Circuit for Timing Measurements

FUNCTIONAL DIAGRAMS

EN
WAKE
t WF
INH

t LWUE INH

TXD EN

t D_MS t D_COM TXD

t D_MS t D_COM

LIN
LIN

RXD (High Z)
RXD (High Z)

Figure 9. WAKE Pin Wake-up and

Figure 7. EN Pin Wake-up and Normal Baud Rate Selection (1.0 kbps to 20 kbps)
Normal Baud Rate Selection (1.0 kbps to 20 kbps)

EN WAKE
t WF
INH
INH
t LWUE
EN
TXD
TXD
t D_MS t D_COM
t D_MS t D_COM

LIN LIN

RXD (High Z)
RXD (High Z)
Figure 10. WAKE Pin Wake-up and
Figure 8. EN Pin Wake-up and Slow Baud Rate Selection (1.0 kbps to 10 kbps)
Slow Baud Rate Selection (1.0 kbps to 10 kbps)

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 ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS

Wake-up Frame Wake-Up Frame

LIN 0.4 VSUP LIN 0.4 VSUP
t WUF
tWUF
INH INH

EN
EN

TXD
TXD
t D_MS t D_COM
t D_MS t D_COM

RXD (High Z) RXD (High Z)

Figure 11. LIN Bus Wake-up and

Figure 12. LIN Bus Wake-up and
Normal Baud Rate Selection (1.0 kbps to 20 kbps)
Slow Baud Rate Selection (1.0 kbps to 10 kbps)

EN EN = HIGH and TXD = HIGH EN

TXD
t 2 (5.0 s)

EN = LOW and TXD = HIGH

Toggle Reset to Previous Baud Rate
t 1 (35 s)

Figure 13. Fast Baud Rate Selection (Toggle Function)

EN

TXD

Sleep Mode
Device in Communication Mode Preparation to Sleep Mode

t SD

Figure 14a

EN

Preparation to Sleep Mode

INH Normal or Slow Mode t SD_INH

Sleep Mode

Figure 14b

Figure 14. Sleep Mode Enter

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FUNCTIONAL DESCRIPTION
INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33661 is a Physical Layer component dedicated to performance, and safe behavior in case of LIN bus short-to-
automotive LIN sub-bus applications. ground or LIN bus leakage during low power mode.
The 33661 features include slew rate selection for Digital inputs are 5.0 V and 3.3 V compatible without any
optimized operation at 10 kbps and 20 kbps, fast baud rate external component required.
for test and programming modes, excellent radiated emission The INH output may be used to control an external voltage
regulator or to drive a LIN bus pull-up resistor.

FUNCTIONAL PIN DESCRIPTION

POWER SUPPLY PIN (VSUP) DATA INPUT PIN (TXD)

The VSUP supply pin is the power supply pin for the The TXD input pin is the MCU interface to control the state
33661. The pin is connected to a battery through a serial of the LIN output. When TXD is LOW, LIN output is LOW;
diode for reverse battery protection. The DC operating when TXD is HIGH, the LIN output transistor is turned OFF.
voltage is from 7.0 V to 27 V. This pin sustains standard The threshold is 3.3 V and 5.0 V compatible. The baud rate
automotive voltage conditions such as 27 V DC during jump- selection (normal or Slow mode) is done at device wake-up
start conditions and 40 V during load dump. Supply current in by the state of the TXD pin prior to a HIGH level at the EN pin
the Sleep mode is typically 8.0 A. (see Figures 7 through 12).

GROUND PIN (GND) DATA OUTPUT PIN (RXD)

In case of a ground disconnection at the module level, the The RXD output pin is the MCU interface, which reports
33661 does not have significant current consumption on the the state of the LIN bus voltage. LIN HIGH (recessive) is
LIN bus pin when in the recessive state. (Less than 100 µA is reported by a high-voltage on RXD; LIN LOW (dominant) is
sourced from LIN bus pin, which creates 100 mV drop reported by a low-voltage on RXD. The RXD output structure
voltage from the 1.0 k LIN bus pull-up resistor.) is a CMOS-type push-pull output stage.
The low level is fixed. The high level is dependant on the
LIN BUS PIN (LIN) EN voltage. If EN is set at 3.3 V, RXD VOH is 3.3 V. If EN is
This I/O pin represents the single-wire bus transmitter and set at 5.0 V, RXD VOH is 5.0 V.
receiver. In the Sleep mode, RXD is high impedance. When a wake-
up event is recognized from WAKE pin or from the LIN bus
Transmitter Characteristics pin, RXD is pulled LOW to report the wake-up event. An
The LIN driver is a low-side MOSFET with internal external pull-up resistor may be needed.
overcurrent thermal shutdown. An internal pullup resistor with
a serial diode structure is integrated so no external pullup ENABLE INPUT PIN (EN)
components are required for the application in a slave node. The EN input pin controls the operation mode of the
An additional pullup resistor of 1.0 k must be added when interface. If EN = 1, the interface is in Normal mode, with
the device is used in the master node. transmission path from TXD to LIN and from LIN to RXD both
Voltage can go from - 18 V to 40 V without current other active. The threshold is 3.3 V and 5.0 V compatible. The high
than the pull-up resistance. The LIN pin exhibits no reverse level at EN defines the VOH at RXD. The Sleep mode is
current from the LIN bus line to VSUP, even in the event of entered by setting EN LOW while TXD is HIGH. Sleep mode
GND shift or VPWR disconnection. is active after the t SD filter time (see Figure 14).
The transmitter has two slew rate selections: 20 kbps
(normal slew rate) and 10 kbps (slow slew rate). The slow INHIBIT OUTPUT PIN (INH)
slew rate can be used to improve radiated emissions. The INH output pin may have two main functions. It may
be used to control an external switchable voltage regulator
Receiver Characteristics having an inhibit input. The high drive capability also allows it
The receiver thresholds are ratiometric with the device to drive the bus external resistor in the master node
supply pin. application. This is illustrated in Figures 18 and 19.
In Sleep mode, INH is turned OFF. If a voltage regulator
inhibit input is connected to INH, the regulator will be
disabled. If the master node pull-up resistor is connected to
INH, the pull-up resistor will be disabled from the LIN bus.

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 FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION

WAKE INPUT PIN (WAKE) An internal filter is implemented (40 s typical filtering time
The WAKE pin is a high-voltage input used to wake-up the delay). WAKE pin input structure exhibits a high-impedance,
device from the Sleep mode. WAKE is usually connected to with extremely low input current when voltage at this pin is
an external switch in the application. The typical wake below 14 V. When voltage at the WAKE pin exceeds 14 V,
thresholds are VSUP / 2. input current starts to sink into the device. A serial resistor
should be inserted in order to limit the input current mainly
The WAKE pin has a special design structure and allows
during transient pulses. Recommended resistor value is
wake-up from both High-to-Low or Low-to-High transitions.
33 k.
When entering into Sleep mode, the LIN monitors the state of
the WAKE pin and stores it as a reference state. The opposite Important The WAKE pin should not be left open. If the
state of this reference state will be the wake-up event used wake-up function is not used, WAKE should be connected to
by the device to enter again into Normal mode. ground to avoid false wake-up.

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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

As described in the following, and as depicted in Figure 15 SLEEP MODE

and Table 5, the 33661 has two operational modes, Normal In the Sleep mode, the transmission path is disabled and
and Sleep. Normal mode may be adjusted to improve the 33661 is in Low Power mode. Supply current from VSUP
radiated emissions by changing the slew rate of the LIN bus is very low. Wake-up can occur from LIN bus activity from
output to Fast or Slow mode. In addition, there are two node internal wake-up through the EN pin and from the
transitional modes: Awake mode, which allows the device to WAKE input pin.
go in Normal or Slow mode, and Wait Slow mode, which is a
In the Sleep mode, the 33661 has an internal 20 A pull-
temporary state before the device enters the Slow mode.
up source to VSUP. This avoids the high current path from
the battery to ground in the event the bus is shorted to
NORMAL MODE ground. (Refer to succeeding paragraphs describing wake-
In the Normal mode, the 33661 has slew rate and timing up behavior.)
compatible with the LIN protocol specification, and operates
from 1.0 kbps to 20 kbps. This mode is selected after Sleep DEVICE POWER-UP (AWAKE TRANSITIONAL
mode by setting the TXD pin High prior to setting EN from MODE)
Low to High. Once Normal mode is selected, it is impossible
to select the Slow mode unless the 33661 is set into Sleep At power-up (VSUP rises from zero), the 33661
mode. automatically switches to the Awake transitional mode. It
switches the INH pin to High state and RXD to Low state. The
Slow Mode MCU of the application will then confirm Normal or Slow
mode by setting the TXD and EN pins appropriately.
In the Slow mode, the slew rate is around half the normal
slew rate, and bus speed operation ranges from 1.0 kbps to
DEVICE WAKE-UP EVENTS
10 kbps. The radiated emission is significantly reduced
compared to the already excellent emission level of the The 33661 can be awakened from Sleep mode by three
Normal mode. Slow mode is entered after Sleep mode by wake-up events:
setting the TXD pin Low prior to setting EN from Low to High. • Remote wake-up via LIN bus activity
Once the Slow mode is selected, it is impossible to select the • Internal node wake-up via the EN pin
Normal mode unless the device is set to Sleep mode. • Toggling the WAKE pin

Fast Mode Remote Wake from LIN Bus (Awake Transitional Mode)
In the Fast mode, the slew rate is around 10 times faster The LIN bus wake-up is recognized by a recessive-to-
than the Normal mode. This allows very fast data dominant transition, followed by a dominant level with a
transmission (> 100 kbps) — for instance, for electronic duration greater than 70 s, followed by a dominant-to-
control unit (ECU) tests and microcontroller program recessive transition. This is illustrated in Figures 11 and 12.
download. The bus pull-up resistor might be reduced to Once the wake-up is detected, the 33661 enters the Awake
ensure a correct RC time constant in line with the high baud Transitional mode, with INH High and RXD pulled Low.
rate used.
Fast mode can be selected from either Normal or Slow Wake-up from Internal Node Activity (Normal or Wait
mode. Fast mode is entered via a special sequence (called Slow Mode)
toggle function) as follows: TXD and EN pins set Low, then The 33661 can wake-up by internal node activity through
TXD pulled High, and at the EN pin Low-to-High transition, a Low-to-High transition of the EN pin. When EN is switched
the device enters into the Fast Baud rate. The duration of this from Low-to-High, the device is awakened and enters either
sequence must be less than 35 µs. The toggle function is the Normal or the Wait Slow transitional mode depending on
described in Figure 13. Once in the Fast mode, two different the level of TXD input. The MCU must set the TXD pin LOW
procedures will bring the device back to the previously or HIGH prior to waking up the device through the EN pin.
selected mode (Normal or Slow):
• The toggle function already described. Wake-up from WAKE Pin (Awake Transitional Mode)
• A glitch on EN where t 2 < 5.0 µs also resets the device to If the WAKE input pin is toggled, the 33661 enters the
the previously selected mode (Normal or Slow) Awake transitional mode, with INH High and RXD pulled Low.
(Figure 13).

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14 Freescale Semiconductor
 FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES

Power-up

TXD High and EN Low > t1 (35 s) Fast

(10 x)
TXD High and EN Low to
High Toggle Function EN Low for t 2 < 5.0 s,
then High

LIN Bus or WAKE Pin

Wake-up
TXD High and EN Low to High Normal
Sleep Awake 1.0 to 20 EN Low for t 2 < 5.0 s,
kbps then High

TXD Low and EN

Low to High TXD High Slow EN Low for t 2 < 5.0 s,
1.0 to 10 then High
TXD Low and EN Low to High Wait Slow
kbps
Toggle Function
TXD High and EN Low > t1 (35 s)

EN Low for t 2 < 5.0 s, then High

Fast
(10 x)
Note Refer to Table 5 for explanation.

Figure 15. Operational and Transitional Modes State Diagram

Table 5. Explanation of Operational and Transitional Modes State Diagram

Operational/
LIN INH EN TXD RXD
Transitional
Sleep Mode Recessive state, driver off. 20 A Low Low X High-impedance. High if external
pull-up current source. pull-up to VDD.

Awake Recessive state, driver off. 30 k High Low X Low. If external pull-up, High-to-
pull-up active. Low transition reports wake-up.

Normal Mode Driver active. 30 k pull-up High High High to enter Normal mode. Once Report LIN bus level:
active. Slew rate normal in Normal mode: Low to drive LIN • Low LIN bus dominant
(20 kbps). bus in dominant, High to drive • High LIN bus recessive
LIN bus in recessive.

Wait Slow Recessive state. Driver off. 30 k High High Low High
pull-up active.

Slow Driver active. 30 k pull-up High High Low to enter Slow mode. Once in Report LIN bus level:
active. Slew rate slow (10 kbps). Slow mode: Low to drive LIN bus • Low LIN bus dominant
in dominant, High to drive LIN • High LIN bus recessive
bus in recessive.

Fast Driver active. 30 k pull-up High High Low to drive LIN bus in dominant, Report LIN bus level:
active. Slew rate fast High to drive LIN bus in • Low LIN bus dominant
(>100 kbps). recessive. • High LIN bus recessive

X = Don’t care.

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Freescale Semiconductor 15
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES

ELECTROMAGNETIC COMPATIBILITY

RADIATED EMISSION IN NORMAL AND SLOW 1.5 meters, device loaded with 10 nF and 500  bus
MODES impedance.
The 33661 has been tested for radiated emission Figure 16 displays the results when the device is set in the
performances. Figures 16 and 17 show the results in the Normal mode, optimized for baud rate up to 20 kbps.
frequency range 100 kHz to 2.0 MHz. Test conditions are in Figure 17 displays the results when the device is set in the
accordance with CISPR25 recommendations, bus length of Slow mode, optimized for baud rate up to 10 kbps. The level
of emissions is significantly reduced compared to the already
excellent level of the Normal mode.

Figure 16. Radiated Emission in Normal Mode

Figure 17. Radiated Emission in Slow Mode

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16 Freescale Semiconductor
 TYPICAL APPLICATIONS

TYPICAL APPLICATIONS

The 33661 can be configured in several applications. An additional pull-up resistor of 1.0 k in series with a diode
Figures 18 and 19 show master and slave node applications. must be added when the device is used in the master node.

VPWR

33661 VSUP

> 33 k
WAKE
INH 20 A
Control Master Node
External EN Pull-up
Switch I/O INH
VDD
MCU Control

*
VDD RXD 1.0 k
Regulator RXD 30 k
12 V VDD LIN LIN Bus
Receiver
5.0 V

TXD
TXD
Slope GND
Control
* Optional

Figure 18. Master Node Typical Application

VPWR

33661 VSUP

> 33 k
WAKE
INH 20 A
Control
External EN
Switch I/O INH
VDD
MCU Control

*
VDD RXD
Regulator RXD 30 k
12 V VDD LIN LIN Bus
Receiver
5.0 V

INH TXD
TXD
Slope GND
Control

* Optional

Figure 19. Slave Node Typical Application

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Freescale Semiconductor 17
PACKAGING
PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the
98ASB42564B drawing number below.Dimensions shown are provided for reference ONLY.

EF SUFFIX (PB-FREE)
8-PIN SOIC NARROW BODY
98ASB42564B
ISSUE V

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18 Freescale Semiconductor
 PACKAGING
PACKAGE DIMENSIONS

EF SUFFIX (PB-FREE)
8-PIN SOIC NARROW BODY
98ASB42564B
ISSUE V

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Freescale Semiconductor 19
REFERENCE DOCUMENTS
PACKAGE DIMENSIONS

REFERENCE DOCUMENTS

Table 6. Reference Documents

Title Literature Number

Local Interconnect Network (LIN) Physical Interface: Difference Between MC33399 and MC33661 EB215

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20 Freescale Semiconductor
 REVISION HISTORY

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES

5.0 10/2006 • Implemented Revision History page

• Updated the Freescale format and style
• Added MCZ33661EF/R2 to the part number Ordering Information
6.0 11/2006 • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
MAXIMUM RATINGS 4. Added note with instructions from www.freescale.com.
7.0 2/2012 • Updated Freescale format and package drawing. No content was altered.
• Updated ordering information. Removed MC33661D/R2 and MCZ33662EF/R2, and replaced with
MC33661PEF/R2.
4/2012 • Corrected the definition of LIN
• Updated Freescale form and style
8.0 4/2013 • Change TSTG to -55 to 150
• Revised back page. Updated document properties. Added SMARTMOS sentence to first
paragraph.

33661

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Freescale Semiconductor 21
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Document Number: MC33661

Rev. 8.0
4/2013