Freescale Semiconductor Document Number: MC33977

Technical Data Rev. 2.0, 1/2007

Single Gauge Driver

The 33977 is a Serial Peripheral Interface (SPI) Controlled, stepper 33977
motor gauge driver Integrated Circuit (IC). This monolithic IC consists
of a dual H-Bridge coil driver and its associated control logic. The H-
Bridge drivers are used to automatically control the speed, direction,
and magnitude of current through the coils of a two-phase
instrumentation stepper motor, similar to an MMT-licensed AFIC 6405 SINGLE GAUGE DRIVER
of Switec MS-X156.xxx motor.

ARCHIVE INFORMATION
ARCHIVE INFORMATION

The 33977 is ideal for use in instrumentation systems requiring

distributed and flexible stepper motor gauge driving. The device also
eases the transition to stepper motors from air core motors by
emulating the damped air core pointer movement.

Features
• MMT-Licensed Two-Phase Stepper Motor Compatible
• Switec MS-X15.xxx Stepper Motor Compatible
• Minimal Processor Overhead Required
• Fully Integrated Pointer Movement and Position State Machine DW SUFFIX
with Air Core Movement Emulation EG SUFFIX (Pb-FREE)
• 4096 Possible Steady State Pointer Positions 98ASB42344B
24-PIN SOICW
• 340° Maximum Pointer Sweep
• Maximum Acceleration of 4500°/s2
• Maximum Pointer Velocity of 400°/s
• Analog Microstepping (12 Steps/Degrees of Pointer Movement) ORDERING INFORMATION
• Pointer Calibration and Return to Zero (RTZ) Temperature
Device Package
• Controlled via 16-Bit SPI Messages Range (TA)
• Internal Clock Capable of Calibration
MC33977DW/R2
• Low Sleep Mode Current - 40°C to 125°C 24 SOICW
• Pb-Free Packaging Designated by suffix code EG MCZ33977EG/R2

V PWR

33977
VPWR
V DD
5.0 V VDD
Regulator
SIN+
SIN-
Motor
RTZ COS+
RST COS-
CS
MCU SCLK
SI
SO
GND

Figure 1. 33977 Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
 INTERNAL BLOCK DIAGRAM

INTERNAL BLOCK DIAGRAM

VPWR

VDD INTERNAL
REGULATOR

COS+
ARCHIVE INFORMATION

ARCHIVE INFORMATION
CS COS
COS-
SCLK
SPI
SO
SI

RST LOGIC
STATE
MACHINE H-BRIDGE
UNDER- AND SIN+
AND ILIM CONTROL SIN-
OVERVOLTAGE
DETECT OVERTEMPERATURE
DETECT SIN

VDD
SIGMA-DELTA MULTIPLEXER
ADC

OSCILLATOR
AGND RTZ

GND (8)

Figure 2. 33977 Simplified Internal Block Diagram

33977

Analog Integrated Circuit Device Data

2 Freescale Semiconductor
 PIN CONNECTIONS

PIN CONNECTIONS

COS+ NC
COS- NC
SIN+ NC
SIN- NC

ARCHIVE INFORMATION
ARCHIVE INFORMATION

GND GND
GND GND
GND GND
GND GND
CS VPWR
SCLK RST
SO VDD
SI RTZ

Figure 3. 33977 Pin Connections

Table 1. 33977 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning onpage 10.
Pin Pin Name Pin Function Formal Name Definition

(MS Motor Output H-Bridge Outputs 0 Each pin is the output of a half-bridge, designed to source or sink current.
Pin #)
1 COS+ (MS #4)
2 COS- (MS #3)
3 SIN+ (MS #1)
4 SIN- (MS #2)

5 to 8, GND N/A Ground Ground pins

17 to 20
9 CS Input Chip Select This pin is connected to a chip select output of a Large Scale Integration
(LSI) Master IC and controls which device is addressed.
10 SCLK Input Serial Clock This pin is connected to the SCLK pin of the master device and acts as a
bit clock for the SPI port.
11 SO Output Serial Output This pin is connected to the SPI Serial Data Input pin of the Master device
or to the SI pin of the next device in a daisy chain.
12 SI Input Serial Input This pin is connected to the SPI Serial Data Output pin of the Master
device from which it receives output command data.
13 RTZ Multiplexed Return to Zero This is a multiplexed output pin for the non-driven coil, during a Return to
Output Zero (RTZ) event.

14 VDD Input Voltage This SPI and logic power supply input will work with 5.0 V supplies.

15 RST Input Reset This pin is connected to the Master and is used to reset the device, or
place it into a sleep state by driving it to Logic [1]. When this pin is driven
to Logic [0], all internal logic is forced to the default state. This input has
an internal active pull-up.
16 VPWR Input Battery Voltage Power supply
21, 22, 23, 24 NC – No Connect These pins are not connected to any internal circuitry, or any other pin,
and may be connected to the board where convenient.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 3
 ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
ARCHIVE INFORMATION

ARCHIVE INFORMATION
Ratings Symbol Value Unit

ELECTRICAL RATINGS

Power Supply Voltage VPWRSS V

Steady-State -0.3 to 41

Input Pin Voltage (1) VIN -0.3 to 7.0 V

SIN± COSI± Continuous Current Per Output (2) IOUTMAX 40 mA

ESD Voltage (3) VESD V

Human Body Model (HBM) ±2000
Machine Model (MM) ±2000
Charge Device Model (CDM) ±200
THERMAL RATINGS

Operating Temperature °C
Ambient TA -40 to 125
Junction TJ -40 to 150
Storage Temperature TSTG -55 to 150 °C

Thermal Resistance °C/W

Junction-to-Ambient RJA 60
Junction-to-Lead RJL 20
Peak Package Reflow Temperature During Reflow (4), (5) TPPRT Note 5 °C

Notes
1. Exceeding voltage limits on Input pins may cause permanent damage to the device.
2. Output continuous output rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature
will require maximum output current computation using package thermal resistances.
3. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM)
(CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM).
4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.

33977

Analog Integrated Circuit Device Data

4 Freescale Semiconductor
 ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 4.75 V  VDD  5.25 V, and - 40C  TA 125C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

POWER INPUT (VDD)

ARCHIVE INFORMATION
ARCHIVE INFORMATION

Battery Supply Voltage Range VPWR V

Fully Operational 6.5 – 26
Limited Operation (6), (7) 4.0 26

VPWR Supply Current IPWR mA

Gauge Outputs ON, No Output Loads – 4.0 6.0
VPWR Supply Current (All Outputs Disabled) µA
Reset = Logic [0], VDD = 5.0 V IPWRSLP1 – 42 60
Reset = Logic [0], VDD = 0 V IPWRSLP2 – 15 25

Overvoltage Detection Level (8) VPWROV 26 32 38 V

(9)
Undervoltage Detection Level VPWRUV 5.0 5.6 6.2 V
Logic Supply Voltage Range (5.0 V Nominal Supply) VDD 4.5 5.0 5.5 V
Under VDD Logic Reset VDDUV – – 4.5 V
VDD Supply Current
Sleep: Reset Logic [0] IDDOFF – 40 65 µV
Outputs Enabled IDDON – 1.0 1.8 mA
POWER OUTPUT (SIN-, SIN+, COS-, COS+)

Microstep Output (Measured Across Coil Outputs) V

SIN± (COS±) (Refer to Pin Definitions onpage 3)
ROUT = 200 , PE6 = 0

Steps Pin Definitions

6, 18, 0, 12 VST6 4.82 5.3 6.0

5, 7, 17, 19 1, 11, 13, 23 VST5 0.94 VST6 0.97 VST6 1.0 VST6
4, 8, 16, 20 2, 10, 14, 22 VST4 0.84 VST6 0.87 VST6 0.96 VST6
3, 9, 15, 21 3, 9, 15, 21 VST3 0.68 VST6 0.71 VST6 0.8 VST6
2, 10, 14, 22 5, 7, 17, 19 VST2 0.47 VST6 0.50 VST6 0.57 VST6
1, 11, 13, 23 5, 7, 17, 19 VST1 0.23 VST6 0.26 VST6 0.31 VST6
0, 12 6, 18 VST0 0.1 0.0 0.1

Full Step Active Output (Measured Across Coil Outputs) (10) VFS V
SIN± (COS±), Steps 1,3 (Pin Definitions 0 and 2) 4.9 5.3 6.0

Notes
6. Outputs and logic remain active; however, the larger coil voltage levels may be clipped. The reduction in drive voltage may result in a
loss of position control.
7. The logic will reset at some level below the specified Limited Operational minimum.
8. Outputs will disable and must be re-enabled via the PECCR command.
9. Outputs remain active; however, the reduction in drive voltage may result in a loss of position control.
10. See Figure 7.



33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 5
 ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V  VDD  5.25 V, and - 40C  TA 125C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

POWER OUTPUT (SIN-, SIN+, COS-, COS+) (Continued)

Microstep Full Step Output (Measured from Coil Low Side to Ground) VLS V
SIN± (COS±) IOUT = 30 mA 0.0 0.1 0.3
ARCHIVE INFORMATION

ARCHIVE INFORMATION
Output Flyback Clamp (11) VFB – VST6 + 0.5 VST6 + 1.0 V
Output Current Limit (Output - VST6) ILIM 40 100 170 mA
Overtemperature Shutdown (12)
TSD 155 – 180 °C
(12)
Overtemperature Hysteresis THYST 8.0 – 16 °C
CONTROL I/O (SI, SCLK, CS, RST, SO)

Input Logic High Voltage (12) VIH 2.0 – – V

(12)
Input Logic Low Voltage VIL – – 0.8 V
(12)
Input Logic Voltage Hysteresis VINHYST – 100 – mV
Input Logic Pull-Down Current (SI, SCLK) IDWN 3.0 – 20 µA
Input Logic Pull-Up Current (CS, RST) IUP 5.0 – 20 µA
SO High State Output Voltage (IOH = 1.0 mA) VSOH 0.8 VDD – – V
SO Low State Output Voltage (IOL = 1.6 mA) VSOL – 0.2 0.4 V
SO Tri-State Leakage Current (CS = 3.5 V) ISOLK -5.0 0.0 5.0 µA
(13)
Input Capacitance CIN – 4.0 12 pF
(13)
SO Tri-State Capacitance CSO – – 20 pF

ANALOG TO DIGITAL CONVERTER (RTZ ACCUMULATOR COUNT)

ADC Gain (12), (14) GADC 100 188 270 Counts/V/

ms

Notes
11. Outputs remain active; however, the reduction in drive voltage may result in a loss of position control.
12. This parameter is guaranteed by design; however, it is not production tested.
13. Capacitance not measured. This parameter is guaranteed by design; however, it is not production tested.
14. Reference RTZ Accumulator (Typical) on page 30

33977

Analog Integrated Circuit Device Data

6 Freescale Semiconductor
 ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V  VDD  5.25 V, and - 40C  TA  125C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

POWER OUTPUT AND CLOCK TIMINGS (SIN+, SIN-, COS+, COS-) CS

ARCHIVE INFORMATION
ARCHIVE INFORMATION

SIN± (COS±) Output Turn ON Delay Time (Time from Rising CS tDLYON ms
Enabling Outputs to Steady State Coil Voltages and Currents) (15) – – 1.0
SIN± (COS±) Output Turn OFF Delay Time (Time from Rising CS tDLYOFF ms
Disables Outputs to Steady State Coil Voltages and Currents) (15) – – 1.0
Uncalibrated Oscillator Cycle Time tCLU 0.65 1.0 1.7 µs
Calibrated Oscillator Cycle Time tCLC µs
Calibration Pulse = 8.0 µs, PECCR D4 = Logic [0] 1.0 1.1 1.2
Calibration Pulse = 8.0 µs, PECCR D4 = Logic [1] 0.9 1.0 1.1
(16)
Maximum Pointer Speed VMAX – – 400 °/s
(16)
Maximum Pointer Acceleration AMAX – – 4500 °/s2

SPI INTERFACE TIMING (CS, SCLK, SO, SI, RST) (17)

Recommended Frequency of SPI Operation fSPI – 1.0 2.0 MHz

(18)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) tLEAD 167 – – ns
(18)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) tLAG 167 – – ns
(18)
SI to Falling Edge of SCLK (Required Setup Time) tSISU – 25 83 ns
Falling Edge of SCLK to SI (Required Hold Time) (18) tSIHOLD – 25 83 ns
SO Rise Time tRSO ns
CL = 200 pF – 25 50

SO Fall Time tFSO ns

CL = 200 pF – 25 50

SI, CS, SCLK, Incoming Signal Rise Time (19) tRSI – – 50 ns

SI, CS, SCLK, Incoming Signal Fall Time (19)
tFIS – – 50 ns
(18)
Falling Edge of RST to Rising Edge of RST (Required Setup Time) tWRST – – 3.0 µs
(18), (20)
Rising Edge of CS to Falling Edge of CS (Required Setup Time) tCS – – 5.0 µs
Falling Edge of RST to Rising Edge of CS (Required Setup Time) (18)
tEN – – 5.0 µs

Notes
15. Maximum specified time for the 33977 is the minimum guaranteed time needed from the microcontroller.
16. The minimum and maximum value will vary proportionally to the internal clock tolerance. These numbers are based on an ideally
calibrated clock frequency of 1.0 MHz. These are not 100 percent tested.
17. The 33977 shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the specified
temperature range. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 33 ns. The device shall
be fully functional for slower clock speeds. Reference Figure 4 and 5.
18. The required setup times specified for the 33977 are the minimum time needed from the microcontroller to guarantee correct operation.
19. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
20. The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 7
 ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V  VDD  5.25 V, and - 40C  TA  125C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

SPI INTERFACE TIMING (CS, SCLK, SO, SI, RST) ‘ (CONTINUED)

Time from Falling Edge of CS to SO Low Impedance (22) tSOEN – – 145 ns

(23)
Time from Falling Edge of CS to SO High Impedance tSODIS – 1.3 4.0 µs
ARCHIVE INFORMATION

ARCHIVE INFORMATION
(24)
Time from Rising Edge of SCLK to SO Data Valid tVALID ns
0.2 VDD SO 0.8 VDD, CL = 200 pF – 90 150

Notes
21. The 33977 shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the specified
temperature range. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 33 ns. The device shall
be fully functional for slower clock speeds.
22. Time required for output status data to be terminated at SO 1.0 k load on SO.
23. Time required for output status data to be available for use at SO 1.0 k load on SO.
24. Time required to obtain valid data out from SO following the rise of SCLK.

33977

Analog Integrated Circuit Device Data

8 Freescale Semiconductor
 ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS

TIMING DIAGRAMS

VIN
RST 0.2 VDD
VIL
t
WRST
tCS

ARCHIVE INFORMATION
ARCHIVE INFORMATION

0.7 VDD VIH

CS
0.7 VDD VIL

tLEAD tRSI tLAG

0.7 VDD VIH

0.2 VDD

SCLK tFIS
tSISU
tSI(HOLD)
0.7 VDD
SI Don’t Care Valid Don’t Care Valid Don’t Care
0.2 VDD

Figure 4. Input Timing Switching Characteristics

tFIS
tRSI

3.5V VOH
50%
SCLK 1.0V VOL

tSO(EN)
VOH
0.7 VDD

SO 0.2 VDD
Low-to-High VOL
tRSO
tVALID
tRSO
SO VOH
High-to-Low 0.7 VDD
0.2 VDD
tSO(DIS)
VOL

Figure 5. Valid Data Delay Time and Valid Time Waveforms

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 9
 FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

This 33977 is a single-packaged, Serial Peripheral associated control logic. The dual H-Bridge driver is used to
INterface (SPI) controlled, single stepper motor gauge driver automatically control the speed, direction, and magnitude of
integrated circuit (IC). This monolithic stepper IC consists of current through the coils of a two-phase instrumentation
[deleted two per D. Mortensen] a dual output H-Bridge coil stepper motor, similar to an MMT-licensed AFIC 6405 of
ARCHIVE INFORMATION

ARCHIVE INFORMATION
driver [deleted plural s for accurate tense] and the Switec MS-X 156.xxx motor.

FUNCTIONAL PIN DESCRIPTION

COSINE POSITIVE (COS0+) SCLK has an internal pull down (lDWN), as specified in the
The H-Bridge pins linearly drive the sine and cosine coils section of the Static Electrical Characteristics Table. When
of a stepper motor, providing four-quadrant operation. CS is logic [1], signals at the SCLK and SI pins are ignored
and SO is tri-stated (high impedance). Refer to the data
transfer Timing Diagrams on page 9.
COSINE NEGATIVE (COS0-)
The H-Bridge pins linearly drive the sine and cosine coils
SERIAL OUTPUT (SO)
of a stepper motor, providing four-quadrant operation.
The SO data pin is a tri-stateable output from the Shift
register. The Status register bits are the first 16 bits shifted
SINE POSITIVE (SIN+)
out. Those bits are followed by the message bits clocked in
The H-Bridge pins linearly drive the sine and cosine coils FIFO, when the device is in a daisy chain connection or being
of a stepper motor, providing four-quadrant operation. sent words that are multiples of 16 bits. Data is shifted on the
rising edge of the SCLK signal. The SO pin will remain in a
SINE NEGATIVE (SIN-) high impedance state until the CS pin is put into a logic low
The H-Bridge pins linearly drive the sine and cosine coils state.
of a stepper motor, providing four-quadrant operation.
SERIAL INPUT (SI)
GROUND (GND) The SI pin is the input of the SPI. Serial input information
Ground pins. is read on the falling edge of SCLK. A 16-bit stream of serial
data is required on the SI pin, beginning with the most
CHIP SELECT (CS) significant bit (MSB). Messages that are not multiples of 16
bits (e.g., daisy chained device messages) are ignored. After
The pin enables communication with the master device.
transmitting a 16-bit word, the CS pin must be de-asserted
When this pin is in a logic [0] state, the 33977 is capable of
(logic [1]) before transmitting a new word. SI information is
transferring information to, and receiving information from,
ignored when CS is in a logic high state.
the master. The 33977 latches data in from the Input Shift
registers to the addressed registers on the rising edge of CS.
RETURN TO ZERO (RTZ)
The output driver on the SO pin is enabled when CS is
logic [0]. When CS is logic high, signals at the SCLK and SI This is a multiplexed output pin for the non-driven coil,
pins are ignored and the SO pin is tri-stated (high during a Return to Zero (RTZ) event.
impedance). CS will only be transitioned from a logic [1] state
to a logic [0] state when SCLK is logic [0]. CS has an internal VOLTAGE (VDD)
pull-up (IUP) connected to the pin, as specified in the section The SPI and logic power supply input will work with 5.0 V
of the Static Electrical Characteristics Table. supplies.

SERIAL CLOCK (SCLK) RESET (RST)

SCLK clocks the Internal Shift registers of the 33977 If the master decides to reset the device, or place it into a
device. The SI pin accepts data into the Input Shift register on sleep state, the RST pin is driven to a Logic [0]. A Logic [0] on
the falling edge of the SCLK signal, while the Serial Output the RST pin forces all internal logic to the known default state.
pin (SO) shifts data information out of the SO Line Driver on This input has an internal active pull-up.
the rising edge of the SCLK signal. It is important that the
SCLK pin be in a logic [0] state whenever the CS makes any VOLTAGE POWER (VPWR)
transition.
This is the power supply pin.

33977

Analog Integrated Circuit Device Data

10 Freescale Semiconductor
 FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION (OPTIONAL)

FUNCTIONAL INTERNAL BLOCK DESCRIPTION (OPTIONAL)

SPI Logic Internal

Reference

ARCHIVE INFORMATION
ARCHIVE INFORMATION

Under and H-Bridge

Overvoltage Oscillator and Control
Detect

RTZ

Figure 6. Functional Internal 33977 Block Illustration

SERIAL PERIPHERAL INTERFACE (SPI) OSCILLATOR

This circuitry manages incoming messages and outgoing The internal oscillator generates the internal clock for all
status data. timing critical features.

LOGIC H-BRIDGE AND CONTROL

This design element includes internal logic including state This circuitry contains the output coil drivers and the
machines and message decoding. multiplexers necessary for four quadrant operation and RTZ
sequencing. This circuitry is repeated for the Sine and Cosine
INTERNAL REFERENCE coils.
This design element is used for step value levels. • Overtemperature — Each output includes an
overtemperature sensing circuit
UNDER AND OVERVOLTAGE DETECTION • ILIM — Each output is current limited
This design element detects when VPWR is out of the
normal operating range. RETURN TO ZERO (RTZ)
This circuitry outputs the voltage present on the non-driven
coil during RTZ operation.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 11
 FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

STATE MACHINE OPERATION

The 33977 is ideal for use in instrumentation systems
requiring distributed and flexible stepper motor gauge driving.
The device also eases the transition to stepper motors from
ARCHIVE INFORMATION

ARCHIVE INFORMATION
air core motors by emulating the air core pointer movement
with little additional processor bandwidth utilization. The two-
phase stepper motor has maximum allowable velocities and
acceleration and deceleration. The purpose of the stepper
motor state machine is to drive the motor with the maximum
performance while remaining within the motor’s voltage,
velocity, and acceleration constraints.
A requirement of the state machine is to ensure the
deceleration phase begins at the correct time and pointer
position. When commanded, the motor [will deleted PV]
accelerates constantly to the maximum velocity, and then it
moves toward the commanded position at the maximum
velocity. Eventually, the pointer reaches the calculated
location where the movement has to decelerate, safely
slowing to a stop at the desired position. During the
deceleration phase, the motor does [will deleted PV] not
exceed the maximum deceleration.
During normal operation, both stepper motor rotors are
microstepped at 24 steps per electrical revolution, illustrated
in Figure 7. A complete electrical revolution results in two
degrees of pointer movement. There is a second smaller
[parentheses removed-unnecessary] state machine in the IC
controlling these microsteps. The smaller state machine
receives clockwise or counter-clockwise index commands at
timed intervals, thereby stepping the motor in the appropriate
direction by adjusting the current in each coil. Normalized
values are provided in Table 5.

Figure 7. Clockwise Microsteps

Table 5. Coil Step Value

SINE COS (Angle -30)* COS (Angle -30)*
Step Angle
(Angle)* PE6=0 PE6=1
0 0.0 0.0 1.0 0.866
1 15 0.259 0.965 0.966
2 30 0.5 0.866 1.0
3 45 0.707 0.707 0.966
4 60 0.866 0.5 0.866
5 75 0.966 0.259 0.707
6 90 1.0 0.0 0.500
7 105 0.966 -0.259 0.259
8 120 0.866 -0.5 0.0
9 135 0.707 -0.707 -0.259
10 150 0.5 -0.866 -0.500

33977

Analog Integrated Circuit Device Data

12 Freescale Semiconductor
 FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES

Table 5. Coil Step Value and solving for v in terms of u, s, and t gives: 
11 165 0.259 -0.966 -0.707
v = 2/t - u
12 180 0.0 -1.0 -0.866
The correct value of t to use in the equation is the
13 195 -0.259 -0.966 -0.966
quantized value obtained above.
14 210 -0.5 -0.867 -1.0
From these equations, a set of recursive equations can be
15 225 -0.707 -0.707 -0.966 generated to give the allowed time step between motor
16 240 -0.866 -0.5 -0.866 indexes when the motor is accelerating from a stop to its

ARCHIVE INFORMATION
ARCHIVE INFORMATION

17 255 -0.966 -0.259 -0.707

maximum velocity.
18 Starting from a position p of 0 and a velocity v of 0, these
270 -1.0 0.0 -0.500
equations define the time interval between steps at each
19 285 -0.966 0.259 -0.259 position. To drive the motor at maximum performance, index
20 300 -0.866 0.5 0.0 commands are given to the motor at these intervals. A table
21 315 -0.707 0.707 0.259 is generated giving the time step *t at an index position n.
22 330 -0.5 0.866 0.500
p0 = 0
23 345 -0.259 0.966 0.707 v0 = 0
* Denotes normalized values

 -vn -1 +  v2 + 2a 
The motor is stepped by providing index commands at n -1
intervals. The time between steps defines the motor velocity tn =
a
and the changing time defines the motor acceleration.
The state machine uses a table to define the allowed time
and the maximum velocity. A useful side effect of the table is where indicates rounding up
that it also allows the direct determination of the position at
which the velocity should reduce to stop the motor at the vn = 2/tn - Vn -1
desired position.
pn = n
Motor motion equations follow: [reworded for efficient use
of space] Note: [chgd for format consistency AND deleted that as PV]
(The units of position are steps and velocity and For pn = n, on the nth step, the motor [has deleted as PV]
acceleration are in steps/second and steps/second2.) indexed by n positions and has been accelerating steadily at
the maximum allowed rate. This is critical because it also
From an initial position of 0 with an initial velocity (u), the
indicates the minimum distance the motor must travel while
motor position (s) at a time (t) is:
decelerating to a stop. For example, the stopping distance is
also equal to the current value of n.
s = ut + 1/2 at 2
The algorithm of pointer movement can be summarized in
two steps:
For unit steps, the time between steps is: 1. The pointer is at the previously commanded position
and is not moving.

- u +  u2 + 2a 2. A command to move to a pointer position (other than

t= the current position) has been received. Timed index
a
pulses are sent to the motor driver at an ever-
increasing rate, according to the time steps in Table 6,
This defines the time increment between steps when the until:
motor is initially traveling at a velocity u. In the ROM, this time aThe maximum velocity (default or selected) is
is quantized to multiples of the system clock by rounding reached after which the step time intervals will no
upwards, ensuring acceleration never exceeds the allowed longer decrease.
value. The actual velocity and acceleration is calculated from bThe distance in steps that remain to travel are less
the time step actually used. Using: than the current step time index value. The motor
then decelerates by increasing the step times
v2 = u2 + 2as according to Table 6 until the commanded
and position is reached. The state machine controls
v = u + at the deceleration so that the pointer reaches the
commanded position efficiently.
An example of the velocity table for a particular motor is
provided in Table 6. This motor’s maximum speed is 4800

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 13
 FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES

microsteps/s (at 12 microsteps/degrees), and its maximum

acceleration is 54000 microsteps/s2. The table is quantized
to a 1.0 MHz clock.
Table 6. Velocity Table
Velocity Time Between Velocity Velocity Time Between Velocity Velocity Time Between Velocity
Position Steps (µs) (µSteps/s) Position Steps (µs) (µSteps/s) Position Steps (µs) (µSteps/s)

0 0.0 0.00 76 380 2631.6 152 257 3891.1

1
ARCHIVE INFORMATION

27217 36.7 77 377 2652.5 153 256 3906.3

ARCHIVE INFORMATION
2 13607 73.5 78 374 2673.8 154 255 3921.6
3 11271 88.7 79 372 2688.2 155 254 3937.0
4 7970 125.5 80 369 2710.0 156 254 3937.0
5 5858 170.7 81 366 2732.2 157 253 3952.6
6 4564 219.1 82 364 2747.3 158 252 3968.3
7 3720 268.8 83 361 2770.1 159 251 3984.1
8 3132 319.3 84 358 2793.3 160 250 4000.0
9 2701 370.2 85 356 2809.0 161 249 4016.1
10 2373 421.4 86 354 2824.9 162 248 4032.3
11 2115 472.8 87 351 2849.0 163 248 4032.3
12 1908 524.1 88 349 2865.3 164 247 4048.6
13 1737 575.7 89 347 2881.8 165 246 4065.0
14 1594 627.4 90 344 2907.0 166 245 4081.6
15 1473 678.9 91 342 2924.0 167 244 4098.4
16 1369 730.5 92 340 2941.2 168 244 4098.4
17 1278 782.5 93 338 2958.6 169 243 4115.2
18 1199 834.0 94 336 2976.2 170 242 4132.2
19 1129 885.7 95 334 2994.0 171 241 4149.4
20 1066 938.1 96 332 3012.0 172 241 4149.4
21 1010 990.1 97 330 3030.3 173 240 4166.7
22 960 1041.7 98 328 3048.8 174 239 4184.1
23 916 1091.7 99 326 3067.5 175 238 4201.7
24 877 1140.3 100 324 3086.4 176 238 4201.7
25 842 1187.6 101 322 3105.6 177 237 4219.4
26 812 1231.5 102 321 3115.3 178 236 4237.3
27 784 1275.5 103 319 3134.8 179 265 4255.3
28 760 1315.8 104 317 3154.6 180 235 4255.3
29 737 1356.9 105 315 3174.6 181 234 4273.5
30 716 1396.6 106 314 3184.7 182 233 4291.8
31 697 1434.7 107 312 3205.1 183 233 4291.8
32 680 1470.6 108 310 3225.8 184 232 4310.3
33 663 1508.3 109 309 3236.2 185 231 4329.0
34 648 1543.2 110 307 3257.3 186 231 4329.0
35 634 1577.3 111 306 3268.0 187 230 4347.8

33977

Analog Integrated Circuit Device Data

14 Freescale Semiconductor
 FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES

Table 6. Velocity Table (continued)

Velocity Time Between Velocity Velocity Time Between Velocity Velocity Time Between Velocity
Position Steps (µs) (µSteps/s) Position Steps (µs) (µSteps/s) Position Steps (µs) (µSteps/s)

36 621 1610.3 112 304 3289.5 188 229 4366.8

37 608 1644.7 113 303 3300.3 189 229 4366.8
38 596 1677.9 114 301 3322.3 190 228 4386.0
39 585 1709.4 115 300 3333.3 191 227 4405.3

ARCHIVE INFORMATION
ARCHIVE INFORMATION

40 575 1739.1 116 298 3355.7 192 227 4405.3

41 565 1769.9 117 297 3367.0 193 226 4424.8
42 555 1801.8 118 295 3389.8 194 226 4424.8
43 546 1831.5 119 294 3401.4 195 225 4444.4
44 538 1858.7 120 293 3413.0 196 224 4464.3
45 529 1890.4 121 291 3436.4 197 224 4464.3
46 521 1919.4 122 290 3448.3 198 223 4484.3
47 514 1945.5 123 289 3560.2 199 222 4504.5
48 507 1972.4 124 287 3484.3 200 222 4504.5
49 500 2000.0 125 286 3496.5 201 221 4524.9
50 493 2028.4 126 285 3508.8 202 221 4524.9
51 487 2053.4 127 284 3521.1 203 220 4545.5
52 481 2079.0 128 282 3546.1 204 220 4545.5
53 475 2105.3 129 281 3558.7 205 219 4566.2
54 469 2132.2 130 280 3571.4 206 218 4587.2
55 464 2155.2 131 279 3584.2 207 218 4587.2
56 458 2183.4 132 278 3597.1 208 217 4608.3
57 453 2207.5 133 277 3610.1 209 217 4608.3
58 448 2232.1 134 275 3636.4 210 216 4629.6
59 444 2252.3 135 274 3649.6 211 216 4629.6
60 439 2277.9 136 273 3663.0 212 215 4651.2
61 434 2304.1 137 272 3676.5 213 215 4651.2
62 430 2325.6 138 271 3690.0 214 214 4672.9
63 426 2347.4 139 270 3703.7 215 214 4672.9
64 422 2369.7 140 269 3717.5 216 213 4694.8
65 418 2392.3 141 268 3731.3 217 212 4717.0
66 414 2415.5 142 267 3745.3 218 212 4717.0
67 410 2439.0 143 266 3759.4 219 211 4739.3
68 406 2463.1 144 265 3773.6 220 211 4739.3
69 403 2481.4 145 264 3787.9 221 210 4761.9
70 399 2506.3 146 263 3802.3 222 210 4761.9
71 396 2525.3 147 262 3816.8 223 209 4784.7
72 393 2544.5 148 261 3831.4 224 209 4784.7
73 389 2570.7 149 260 3846.2 225 208 4807.7
74 386 2590.7 150 259 3861.0
75 383 2611.0 151 258 3876.0

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 15
 FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES

INTERNAL CLOCK CALIBRATION 3. A third, and even more expensive approach requires
Timing-related functions on the 33977 (e.g., pointer, the use of an additional crystal, or resonator.
velocities, acceleration, and Return to Zero Pointer speeds) The internal clock in the 33977 is temperature
depend upon a precise, consistent time reference to control independent and area efficient; however, it can vary up to 70
the pointer accurately and reliably. Generating accurate time percent due to process variation. Using the existing SPI
references on an integrated circuit can be accomplished. inputs and the precision timing reference already available to
There are three methods to generate accurate time the microcontroller, the 33977 allows more accurate clock
references on an integrated circuit: calibration to within ±10 percent without requiring extra pins,
1. One option is trimming; however, timing tends to be components, or costly circuitry.
ARCHIVE INFORMATION

ARCHIVE INFORMATION
costly due to the large amount of die area required for Calibrating the internal 1.0 MHz clock is initiated by writing
trim pads. Logic [1] to PECCR bit PE3, illustrated in Figure 8.
2. Another, but expensive possibility is an externally
generated clock signal. This option requires a
dedicated pin on the device and controller.

Figure 8. Gauge Enable and Clock Calibration Example

fall below 1.0 MHz. The frequency range of the calibrated
The 8.0 µs calibration pulse is then provided by the clock is always below 1.0 MHz if PECCR bit PE4 is Logic [0]
controller to result in a nominal internal 33977 clock speed of prior to initiating a calibration command, followed by an 8.0 µs
1.0 MHz. The pulse is sent on the CS pin immediately after reference pulse. The frequency is centered at 1.0 MHz if bit
the SPI calibration command is sent. During the calibration, D4 is written Logic [1].
no other SPI lines should be toggled. At the moment the CS The 33977 can be fooled into calibrating faster or slower
pin transitions from Logic [1] to Logic [0], an internal 7-bit than the optimal frequency by sending a calibration pulse
counter counts the number of cycles of an internal, 8.0 MHz longer or shorter than the intended 8.0 µs. As long as the
clock. The counter stops when the CS pin transitions from calibration divisor remains between four and 15 there is no
Logic [0] to Logic [1]. The value in the counter represents the calibration flag. For applications requiring a slower calibrated
number of cycles of the 8.0 MHz clock occurring in the 8.0 µs clock, e.g., a motor designed with a gear ratio of 120:1
window; it should range from 32 to 119. An offset is added to (8 microsteps/deg), users will have to provide a longer
this number to help center, or skew, the calibrated result to calibration pulse. The internal oscillator can be slowed with
generate a desired maximum, or normal frequency. The the PECCR command, so the calibration divisor safely falls
modified counter value is truncated by four bits to generate within the four to 15 range when calibrating with a longer time
the calibration divisor, potentially ranging from four to 15. The reference. Fro example, for the 120:1 motor, the pulse would
8.0 MHz clock is divided by the calibration divisor, resulting in be 12 µs instead of 8.0 µs. The result of this slower calibration
a calibrated 1.0 MHz clock. If the calibration divisor lies is longer step times resulting in generating pointer
outside the range of four to 15, the 33977 flags the CAL bit in movements capable of meeting acceleration and velocity
the device Status register, indicating the calibration requirements. The resolution of the pointer positioning
procedure was not successful. A clock calibration is allowed decreases from 0.083 deg/microstep (180:1) to 0.125 
only if the gauge is disabled, or the pointer is not moving as deg/microstep (120:1) while the pointer sweep range
indicated by the Status bit of MOV, illustrated in Table 16 increases from approximately 340° to over 500°.
section of this document. Note: A fast calibration could result in violations of the
Some applications may require a guaranteed maximum motor acceleration and a velocity maximums, resulting in
pointer velocity and acceleration. Guaranteeing these missed steps.
maximums requires the nominal internal clock frequency to

33977

Analog Integrated Circuit Device Data

16 Freescale Semiconductor
 FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES

POINTER DECELERATION position step values as the pointer decelerates. The default
Constant acceleration and deceleration of the pointer movement in the 33977 uses this ramp modification feature.
produces relatively choppy movements when compared to An example is illustrated in Figure 9. If the maximum
those of an air core gauge. Modification of the velocity acceleration and deceleration of the pointer is desired, the
position ramp during deceleration can create the desired repetitive steps can be disabled by writing Logic [1] to the
damped movement. This modification is accomplished in the PECCR bit PE5.
33977 by adding repetitive steps at several of the last velocity
.

ARCHIVE INFORMATION
ARCHIVE INFORMATION

De
Velocity ce
Position 24 le
23
24
23 ra
22 22 te
21 21
20 20
19 19
18 18
17 17
16 16
e

15
at

15
14
er

14
13 13
Hold Counts
el

12 12
cc

11 11
A

10 10
9 9
8
7 8
6 7
5 6
4 5
3 4
2 3
1
2
1
Position = 0 0

Microsteps
Figure 8. Deceleration Ramp

Figure 9. Deceleration Ramp

RETURN TO ZERO CALIBRATION determines an RTZ sequence is not working properly, for
Many stepper motor applications require [that deleted as example, the RTZ taking too long; it can disable the
PV] the IC detect when the stepper motor stalls after command via the RTZR bit RZ1. [Altered for better read flow]
commanded to return to the zero position for calibration RTZCR bits RC10:RC5 are written to preload the
purposes. In instrumentation applications, the stalling occurs accumulator with a predetermined value assuring accurate
when the pointer hits the end stop on the gauge bezel, pointer stall detection. This preloaded value can be
[which is deleted as PV] usually at the zero position. It is determined during application development by disabling the
important to know [that PV] when the pointer reaches the end automatic shutdown feature of the device with the RTZR bit
stop, it immediately stops without bouncing away. The 33977 RZ4. This operating mode allows the master to monitor the
device provides the ability to automatically and independently RTZ event, using the accumulator information available via
return the pointer to the zero position via the RTZR and the SO if the device is configured to provide the RTZ
RTZCR SPI commands. An automatic RTZ is initiated, using Accumulator Status. The unconditional RTZ event can be
the RZ1 and RZ2 bits, provided the RZ4 is Logic [1]. During turned OFF using the RTZR bit RZ1.
an RTZ event, all commands related to the gauge being If the Position 0 location bit, RZ2, is in the default Logic [0]
returned are ignored until the pointer has successfully mode, then during an RTZ event the pointer is returned
zeroed, or the RTZR bit RZ1 is written to disable the event. counterclockwise (CCW) using full steps at a constant speed
Once an RTZ event is initiated, the device reports back via determined by the RTZCR RC3:RC0 and RC12:RC11 bits
the SO pin an RTZ event is underway. written during RTZ configuration, see Figure 10. Full steps
The RTZCR command is used to set the RTZ pointer are used during an RTZ so only coil of the motor is being
speed, choose an appropriate blanking time, and preload the driven at any time. The coil not being driven is used to
integration accumulator with an appropriate offset. On determine if the pointer is moving. If the pointer is moving, the
reaching the end stop, the device reports back to the flux present in the non-driven coil is processed by integrating
microcontroller via the status message [that PV] the RTZ was the back EMF signal present on the opened pin of the coil
successful. The RTZ automatically disables, [that will PV] while applying a fixed potential to the other end.
allowing other commands to be valid. In the event the master

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 17
 FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES

IMAX
Imax

ICOIL
Icoil 0
SINE
ARCHIVE INFORMATION

ARCHIVE INFORMATION
IMAX
Imax
0 1 2 3 0

IMAX
Imax

+ COSINE
ICOIL
Icoil 0

_
IMAX
Imax
0 1 2 3 0

Figure 9. FULLSTEPS (Counter Clockwise)

Figure 10. Full Steps (Counterclockwise)
The IC automatically prepares the non-driven coil at each held constant. The full steps are evenly spaced, resulting in
step, waits for a predetermined blanking time, and then equidistant movement as the motor is full stepped.
processes the signal for the duration of the full step. When In comparison, motors [that have deleted PV] whose coils
the pointer reaches the stop and not longer moves, the aligned at a 60° angle [will deleted PV] results in two distinct
dissipating flux is detected. The processed results are placed flux values as a the coils are driven in the same full step
in the RTZ accumulator, and then compared to a decision fashion. This lack of symmetry in the measured flux is due to
threshold. If the signal exceeds the decision threshold, the the difference in the electrical angles between full steps.
pointer is assumed to be moving. If the threshold value is not Clearly stated, the distance the rotor moves changes from full
exceeded, the drive sequence is stopped if RTZR bit RZ4 is step to full step. This difference can be observed in Figure 7
Logic [0]. If bit RZ4 is Logic [1], the RTZ movement will and Table 5.
continue indefinitely until the RTZR bit RZ1 is used to stop the
In Figure 7, where PE6 = 0, the difference in microsteps
RTZ event.
between alternating full steps (one coil at maximum current
A pointer [that is PV] not on a full step location, or [that while the other is at zero) is always six. In contrast, the same
PV] is in magnetic alignment prior to the RTZ event may figure illustrates PE6 = 1 showing the difference in
cause a false RTZ detection. More specifically, an RTZ event microsteps between full steps of the 60° coils alternating
beginning from a non-full step position may result in an between four and eight. These expected differences should
abbreviated flux value potentially interpreted as a stalled be taken into account when setting the RTZ threshold.
pointer. Advancing the pointed by at least 12 microsteps
After completion of an RTZ, the 33977 automatically
clockwise (if PE7 = 0) to the nearest full step position (e.g., 0,
assigns the zero step position to the full step position at the
6, 12, 18, 24, etc.) prior to initiating an RTZ ensures the
end-stop location. Because the actual zero position could lie
magnetic fields line up and increases the chances of a
anywhere within the full step where the zero was detected,
successful pointer stall detection. It is important that the
the assigned zero position could be within a window of ±0.5°.
pointer be in a static, or commanded, position before starting
An RTZ can be used to detect stall, even if the pointer rests
the RTZ event. Because the time duration and the number of
on the end-stop when RTZ sequence is initiated. However, it
steps the pointer moves prior to reaching the commanded
is recommended to advance the pointer by at least 12
position can vary depending upon its status at the time a
microsteps to the nearest full step prior to initiating the RTZ.
position change is communicated, the master should make
sure that the rotor is not moving prior to starting an RTZ.
Cessation of movement can be inferred by monitoring the RTZ OUTPUT
CMD and/or the MOV status bits. During an RTZ event the non-driven coil is analyzed to
It should be pointed out, the flux value, for an ideal motor determine the state of the motor. The 33977 multiplexes the
with the coils perfectly aligned at 90°, will vary little from full coil voltages, [chgd PV and provides to read as active voice]
step to full step if all other variables, such as temperature, are providing signal from the non-driven coil to the RTZ pin.

33977

Analog Integrated Circuit Device Data

18 Freescale Semiconductor
 FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES

DEFAULT MODE continues to be set until the gauge is successfully re-enacted,

Default mode refers to the state of the 33977 after an provided the junction temperature has fallen below the
internal or external reset prior to SPI communication. An hysteresis level.
internal reset occurs during VDD power-up or if VPWR falls
below 4.0 V. An external reset is initiated by the RST pin OVERVOLTAGE FAULT REQUIREMENTS
driven to Logic [0]. With the exception of the RTZCR full step The device is capable of surviving VPWR voltages within
time, all of the specific pin functions and internal registers will the maximum specified in Maximum Ratings, Table 2. VPWR
operate as though all of the addressable configuration levels resulting in an overvoltage shutdown condition can
register bits were set to Logic [0]. This means, for example, result in uncertain pointer positions. Therefore, the pointer

ARCHIVE INFORMATION
ARCHIVE INFORMATION

[deleted PV that] the outputs will be disabled after a power- position should be re-calibrated. The master will be notified of
up or external reset, and SO flag OD6 and OD8 are set, an overvoltage event via the SO pin if the device status is
indicating an undervoltage event. Anytime an external reset selected. Overvoltage detection and notification occurs
is exerted and the default is restored, all configuration regardless of whether the gauge(s) are enabled or disabled.
parameters [replaced e.g. with such as] such as clock
calibration, maximum speed, and RTZ parameters are lost OVERCURRENT FAULT REQUIREMENTS
and must be reloaded.
Outcome currents are limited to safe levels allowing the
device to rely on thermal shutdown to protect itself.
FAULT LOGIC REQUIREMENTS
The 33977 device indicates each of the following faults as UNDERVOLTAGE FAULT REQUIREMENTS
they occur:
Undervoltage VPWR conditions may result in uncertain
• Overtemperature fault pointer positions. Therefore, the internal clock and the pointer
• Undervoltage VPWR position may require re-calibration. The state machine
• Overvoltage VPWR continues to operate with VPWR voltage levels as low as 4.0
• Clock Out of Specification [Formalized spec] V; however, the coil voltages may be clipped. Notification of
These fault bits remain enabled until they are clocked out an undervoltage event is provided via the SO pin.
of the SO pin with a valid SPI message.
Overcurrent faults are not reports directly; however, it is RESET (SLEEP MODE)
likely an overcurrent condition will become a thermal issue The device can reset internally or externally. If the VDD
and be reported. level falls below the VDDUV level, the device resets and
powers up in the Default mode. See Static Electrical
OVERTEMPERATURE FAULT REQUIREMENTS Characteristics table under the sub-heading: Power Input in
Table 3. Similarly, if the RST pin is driven to Logic [0], then
The 33977 incorporates overtemperature protection
the device resets to its default state. The device consumes
circuitry, shutting off the gauge driver when an excessive
the least amount of current (IDD and IPWR) when the RST pin
temperature is detected. In the event of a thermal overload,
is Logic [0]. This is also referred to as the Sleep mode.
the gauge driver is automatically disabled and the fault is
flagged via the OT device status bit. The indicating flag

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 19
 FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS

LOGIC COMMANDS AND REGISTERS

SPI PROTOCOL DESCRIPTION Figure 11 and Figure 12. [figure numbers changed due to
The SPI interface has a full-duplex, three-wire template formatting]
synchronous,16-bit serial synchronous interface data It transitions one time per bit transferred at an operating
transfer and four I/O lines associated with it: Chip Select frequency, fSPI, defined in the SPI Interface Timing section of
(CS), Serial Clock (SCLK), Serial Input (SI), and Serial Output the Dynamic Electrical Characteristics Table 4. It is idle
(SO). The SI/SO pins of the 33977 follow a first in/first out between command transfers. The pin is 50 percent duty
(D15/D0) protocol with both input and output words cycle, with CMOS logic levels. This signal is used to shift data
ARCHIVE INFORMATION

ARCHIVE INFORMATION
transferring the most significant bit first. All inputs are to and from the device.
compatible with 5.0 V CMOS logic levels.
SERIAL OUTPUT (SO)
CHIP SELECT (CS) The SO data pin is a tri-stateable output from the Shift
The CS pin enables communication with the master register. This output will remain tri-stated unless the device is
device. selected by a low CS signal. The output signal generated will
When this pin is in a Logic [0] state, the 33977 is capable have CMOS logic levels and the output will transition on the
of transferring information to, and receiving information from, rising edges of SCLK. The serial output data provides status
the master. The 33977 latches data in from the Input Shift feedback and fault information for each output and is returned
registers to the addressed registers on the rising edge of CS. MSB first when the device is addressed.
The output driver on the SO pin is enabled when CS is Logic The Status register bits are the first 16 bits shifted out.
[0]. When CS is logic high, signals at the SCLK and SI pins Those bits are followed by the message bits clocked in FIFO,
are ignored and the SO pin is tri-stated (high impedance). CS when the device is in a daisy chain connection, or being sent
will only be transitioned from a Logic [1] state to a Logic [0] words [that are deleted as PV] multiples of 16 bits. Data is
state when SCLK is Logic [0]. CS has an internal pull-up (IUP) shifted on the rising edge of the SCLK signal. The SO pin
connected to the pin, as specified in the section of the Static [will deleted as PV] remains in a high impedance state until
Electrical Characteristics table entitled CONTROL I/O, the CS pin is put into a logic low state.
[which is found on page...deleted for consistent format]
Table 3. This pin is also used to calibrate the internal clock. SERIAL INPUT (SI)
The SI pin is the input of the SPI. This input has an internal
SERIAL CLOCK (SCLK) active pull-down requiring CMOS logic levels. The serial data
SCLK clocks the Internal Shift registers of the 33977 transmitted on this line is a 16-bit control command sent MSB
device. The SI pin accepts data into the Input Shift register on first, controlling the gauge functions. The master ensures
the falling edge of the SCLK signal, while the Serial Output data is available on the falling edge of SCLK.
pin (SO) shifts data information out of the SO line driver on Serial input information is read on the falling edge of
the rising edge of the SCLK signal. It is important the SCLK SCLK. A 16-bit stream of serial data is required on the SI pin,
pin be in a Logic [0] state whenever the CS makes any beginning with the most significant bit (MSB). Messages [that
transition. SCLK has an internal pull-down (lDWN), as are deleted as PV] not multiples of 16 bits (e.g., daisy
specified in the section Control I/O of the Static Electrical chained device messages) are ignored. After transmitting a
Characteristics, [which is found on page...deleted for 16-bit word, the CS pin must be de-asserted (Logic [1]) before
consistent format] Table 3. When CS is Logic [1], signals at transmitting a new word. SI information is ignored when CS
the SCLK and SI pins are ignored and SO is tri-stated (high is in a logic high state.
impedance). Refer to the data transfer timing diagrams in

33977

Analog Integrated Circuit Device Data

20 Freescale Semiconductor
 FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS

This section provides a description of the 33977 SPI Table 7 and to the timing diagrams illustrated in Figure 11
behavior. To follow the explanation below, please refer to and Figure 12.

Table 7. Data Transfer Timing

Pin Description
CS (1-to-0) SO pin is enabled
CS (0-to-1) 33977 configuration and desired output states are transferred and executed according to the data in the Shift registers

ARCHIVE INFORMATION
ARCHIVE INFORMATION

SO Will change state on the rising edge of the SCLK pin signal

SI Will accept data on the falling edge of the SCLK pin signal

CS

Output Shift register is loaded here

Note: SO is tri-stated when CS is Logic [1]
Figure 11. Single 16-Bit Word SPI Communication

CS

SCLK
D12 D11 D2
SI

0D12 OD
SO
Notes:
1. SO is tri-stated when CS is Logic [1].
2. D15, D14, D13, , and D0 refer to the first 16 bits of data into the 33977.
3. D15*, D14*, D13*,. . . ., and D0* refer to the most recent entry of program data into the 33977.
4. OD15, OD14, OD13, . . .,and OD0 refer to the first 16 bits of fault and status data out of the 33977.

Figure 12. Multiple 16-Bit Word SPI Communication

DATA INPUT DATA OUTPUT

The Input Shift register captures data at the falling edge of At the first rising edge of the SCLK [clock deleted to
the SCLK. The SCLK pulses exactly 16 times only inside the eliminate redundancy], with CS at Logic [1], the contents of
transmission windows (CS in a Logic [1] state). By the time the selected Status Word register are transferred to the
the CS signal goes to Logic [1] again, the contents of the Output Shift register. The first 16 bits clocked out are the
Input Shift register are transferred to the appropriate internal status bits. If data continues to clock in before the CS
register addressed in bits 15:13. The minimum time CS transitions to Logic [1], the device begins to shift out the data
should be kept high depends on the internal clock speed, previously clocked in FIFO after the CS first transitioned to
specified in the SPI Interface Timing section of the [Static Logic[1].
replaced with Dynamic - correcting table location] Dynamic
Electrical Characteristics, Table 4. It must be long enough so COMMUNICATION MEMORY MAPS AND
the internal clock is able to capture the data from the Input REGISTER DESCRIPTIONS
Shift register and transfer it to the internal registers.
The 33977 device is capable of interfacing directly with a
microcontroller via the 16-bit SPI protocol specified below.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 21
 FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS

The device is controlled by the microprocessor and reports • Battery overvoltage

back status information via the SPI. This section provides a • Battery undervoltage
detailed description of all registers accessible via serial • Pointer zeroing status
interface. The various registers control the behavior of this • Internal clock status
device. • Confirmation of pointer movement commands
A message is transmitted by the master beginning with the • Real time pointer position information
MSB (D15) and ending with the LSB (D0). Multiple messages • Real time pointer velocity step information
can be transmitted in succession to accommodate those • Pointer movement direction
applications where daisy chaining is desirable, or to confirm
ARCHIVE INFORMATION

• Command pointer position status

ARCHIVE INFORMATION
transmitted data, as long as the messages are all multiples of
• RTZ accumulator value
16 bits. Data is transferred through daisy-chained devices, as
illustrated in Figure 12. If an attempt is made to latch in a
message smaller than 16 bits wide, it is ignored. REGISTER DESCRIPTIONS
Table 8 lists the five registers the 33977 uses to configure The following section describes the registers, their
the device, control the state of the [Chgd to two per D. addresses, and their impact on device operation.
Mortensen] two H-bridge outputs, and determine the type of
status information [that is deleted PV] clocked back to the ADDRESS 000 - POWER, ENABLE, CALIBRATION,
master. The registers are addressed via D15:D13 of the AND CONFIGURATION REGISTER (PECCR)
incoming SPI word. The Power, Enable, Calibration, and Configuration
Register is illustrated in Table 9. A write to the 33977 using
Table 8. Module Memory Map this register allows the master to:
• Enable or disable the output drivers of the gauge
Address
Register Name See controller
[15:13]
• Calibrate the internal clock
000 Power, Enable, Calibration, and PECCR Table • Disable the air core emulation
Configuration Register 9 • Select the direction of the pointer movement during
001 Maximum Velocity Register VELR Table pointer positioning and zeroing
10 • Configure the device for the desired status information
010 Gauge Position Register to be clocked out into the SO pin, or
POSR Table
11 • Send a null command for the purpose of reading the
status bits.
011 Not Used – –
This register is also used to place the 33977 into a low
100 Return to Zero Register RTZR Table current consumption mode.
12
The gauge drivers can be enabled by writing Logic [1] to
101 Return to Zero Configuration RTZCR Table the assigned address bits, PE0. This feature could be used
Register 13 to disable a driver if it is failing. The device can be placed into
110 Not Used a standby current mode by writing Logic [0] to PE0. During
RMPSELR –
this state, most current consuming circuits are biased off.
111 Reserved for Test – – When in the Standby mode, the internal clock will remain ON.
[The word Zero omitted above in 101 my error] The internal state machine utilizes a ROM table of step
times defining the duration that the motor will spend at each
MODULE MEMORY MAP microstep as it accelerates or decelerates to a commanded
position. The accuracy of the acceleration and velocity of the
Various registers of the 33977 SPI module are addressed
motor is directly related to the accuracy of the internal clock
by the three MSBs of the 16-bit word received serially.
Although the accuracy of the internal clock is temperature
Functions to be controlled include:
independent, the non-calibrated tolerance is +70% to -35%.
• Individual gauge drive enabling The 33977 was designed with a feature allowing the internal
• Power-up/down clock to be software calibrated to a tighter tolerance of ±10%,
• Internal clock calibration using the CS pin and a reference time pulse provided by the
• Gauge pointer position and velocity microcontroller.
• Gauge pointer zeroing Calibration of the internal clock is initiated by writing Logic
• Air core motor movement emulation [1] to PE3. The calibration pulse, which must be 8.0 µs for an
• Status information internal clock speed of 1.0 MHz, will be sent on the CS pin
Status reporting includes: immediately after the SPI word is sent. No other SPI lines will
be toggled. A clock calibration will be allowed only if the
• Individual gauge overtemperature condition
gauge is disabled or the pointer is not moving, as indicated

33977

Analog Integrated Circuit Device Data

22 Freescale Semiconductor
 FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS

by status bits MOV0. Additional details are provided in the Similarly, this bit must always be written as Logic [1] when
Internal clock Calibration section. being used to control Switec style motors.
Some applications may require a guaranteed maximum The default Pointer Position 0 (PE7 = 0) will be the farthest
pointer velocity and acceleration. Guaranteeing these fall counter-clockwise position. A Logic [1] written to bit PE7 will
below 1.0 MHz. The frequency range of the calibrated clock change the location of the position 0 for the gauge to the
maximums requires [that deleted PV] the nominal internal farthest clockwise position. The pointer will always move
clock frequency will always be below 1.0 MHz if bit PE4 is towards position 0 when executing an RTZ. Exercise care
Logic [0] when initiating a calibration command, followed by when writing to PECCR bit PE7 in order to prevent an
an 8.0 µs reference pulse. The frequency will be centered at accidental change of the position 0 location.

ARCHIVE INFORMATION
ARCHIVE INFORMATION

1.0 MHz if bit PE4 is Logic [1]. Some applications may require
Bits PE11:PE9 determine the content of the bits clocked
a slower calibrated clock due to a lower motor gear reduction
out of the SO pin. When bit PE11 is at Logic [0], the clocked
ratio. Writing Logic [1] to bit PE2 will slow the internal
out bits will provide device status. If Logic [1] is written to bit
oscillator by one-third. Slowing the oscillator accommodates
PE11, the bits clocked out of the SO pin, depending upon the
a longer calibration pulse without overrunning the internal
state of bits PE10:PE9, provides either:
counter - a condition designed to generate a CAL fault
indication. For example, calibration for a clock frequency of • Accumulator information and detection status during
667 kHz would require a calibration pulse of 12 µs. Unless the the RTZ (PE10 Logic [0])
internal oscillator is slowed by writing PE2 to Logic [1], a 12 • Real time pointer position location at the time CS goes
µs calibration pulse may overrun the counter and generate a low (PE10 Logic [1] and PE9 Logic [0]), or
CAL fault indication. • The real time step position of the pointer as described
Some applications may require faster pointer positioning in the velocity Table 6 (PE10 and PE9 Logic [1]).
than is provided with the air core motor emulation feature. Additional details are provided in the SO Communication
Writing Logic [1] to bit PE5 will disable the air core emulation section.
for both gauges and provide an acceleration and deceleration If bit PE12 is Logic [1] during a PECCR command, the
at the maximum that the velocity position ramp can provide. state of PE11:PE0 is ignored. This is referred to as the null
Bit PE6 must always be written Logic [0] during all PECCR command and can be used to read device status without
writes if the device is being used to drive an MMT style motor. affecting device operation.

Table 9. Power, Enable, Calibration, and Configuration Register (PECCR)

Address 000

Bits D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Read – – – – – – – – – – – – –
Write PE12 PE11 PE10 PE9 0 PE7 PE6 PE5 PE4 PE3 PE2 0 PE0


The bits in Table 9 are write-only. Pointer Position or Pointer Speed Select (PE9) Bit D9
This bit is recognized only if PE11 and PE10 = 1.
Null Command for Status Read (PE12) Bit D12 • 0 = Gauge Pointer Position
• 0 = Disable • 1 = Gauge Pointer Speed
• 1 = Enable
(PE8) Bit D8
Status Select (PE11) Bit D11 This bit must be transmitted as Logic [0] for valid PECCR
This bit selects the information clocked out of the SO pin. commands.
• 0 = Device Status (the logic states of PE10, and PE9
are don’t cares) Position 0 Location Select (PE7) Bit D7
• 1 = RTZ Accumulator Value, Gauge Pointer position, or This bit determines the Position 0 of the gauge. RTZ
Gauge Velocity ramp position (depending upon the direction will always be to the position 0.
logic states of PE10, and PE9) • 0 = Position 0 is the most CCW (counterclockwise)
position
RTZ Accumulator or Pointer Status Select (PE10) Bit D10 • 1 = Position 0 is the most CW (clockwise) position
This bit is recognized only when PE11 = 1.
• 0 = RTZ Accumulator Value and status Motor Type Selection (PE6) Bit D6
• 1 = Pointer Position or Speed • 0 = MMT Style (coil phase difference = 90°)
• 1 = Switec Style (coil phase difference = 60°)

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 23
 FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS

Air Core Motor Emulation (PE5) Bit D5 Gauge Enable (PE0) Bit D0
This bit is enabled or disabled (acceleration and This bit enables or disables the output drivers of the
deceleration is constant if disabled). Gauge.
• 0 = Enable • 0 = Disable
• 1 = Disable • 1 = Enable

Clock Calibration Frequency Selector (PE4) Bit D4 ADDRESS 001 - MAXIMUM VELOCITY REGISTER
• 0 = Maximum f =1.0 MHz (for 8.0 µs calibration pulse) (VELR)
ARCHIVE INFORMATION

ARCHIVE INFORMATION
• 1 = Nominal f =1.0 MHz (for 8.0 µs calibration pulse) The Gauge Maximum Velocity Register is used to set a
maximum velocity for the gauge (refer to Table 4). Bits V7:V0
Clock Calibration Enable (PE3) Bit D3 contain a position value from 1 - 225 representative of the
This bit enables or disables the clock calibration. velocity position value described in the Velocity Table,
Table 6. The table value becomes the maximum velocity until
• 0 = Disable
it is changed to another value. If a maximum value is chosen
• 1 = Enable that is greater than the maximum velocity of the acceleration
table, the maximum table value becomes the maximum
Oscillator Adjustment (PE2) Bit D2
velocity.
• 0 = tCLU
If the motor is turning at a speed greater than the new
• 1 = 0.66 x tCLU maximum, the motor immediately moves down the velocity
ramp until the speed falls equal to or below it. Bit V8 must be
(PE1) Bit D1 written to a Logic [1] when changing the maximum velocity of
This bit must be transmitted as Logic [0] for valid PECCR the motor. Bits V12:V10 must be at Logic [0] for valid VELR
commands commands.
.
Table 10. Maximum Velocity Register (VELR)
Address 001

Bits D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Read – – – – – – – – – – – – –
Write 0 0 0 0 V8 V7 V6 V5 V4 V3 V2 V1 V0

The bits in Table 10 are write-only. (V7:V0) Bits D7:D0
These bits can be used to program the device to limit the
(V12:V9) Bits D12:D9 maximum velocity of the pointer movement. to one of over
200 speeds listed in the Velocity Table 6. This velocity will
These bits must be transmitted as Logic [0] for valid VELR
remain the maximum of the intended gauge until changed by
commands.
command. Velocities can range from position 1 (00000001)
to position 225 (11111111).
Gauge Velocity (V8) Bit D8
Enables the maximum velocity as determined in the V7: ADDRESSES 010 - GAUGE POSITION REGISTER
V0. (POSR)
• 0 = Velocity change disabled SI Address 010 (Gauge Position Register) register bits
• 1 = Velocity change enabled PO11: PO0 are written to when communicating the desired
pointer positions. Commanded positions can range from 0 to
4095

Table 11. Gauge Position Register (POSR)

Address 010

Bits D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Read – – – – – – – – – – – – –
Write 0 P011 P010 P09 P08 P07 P06 P05 P04 P03 P02 P01 P00

The bits in Table 11 are write-only.

33977

Analog Integrated Circuit Device Data

24 Freescale Semiconductor
 FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS

PO012 (D12) steps, where only one coil is driven at any point in time. The
This bits must be transmitted as Logic [0] for valid POSR back electromotive force (EMF) signal present on the non-
commands. driven coil is integrated and its results are stored in an
accumulator. A Logic [1] written to bit RZ1 enables a Return
P011:P00 (D11:D0) to Zero for the Gauge if RZ0 is Logic [0]. A Logic [0] written to
bit RZ1 disables a Return to Zero for the Gauge when RZ0 is
Desired pointer position of Gauge. Pointer positions can
Logic [0].
range from 0 (000000000000) to position 4095
(111111111111). For a stepper motor requiring 12 Bits D12:D5 and D3:D2 must be written Logic [0] for valid
RTZR commands. An unconditional RTZ event can be

ARCHIVE INFORMATION
microsteps per degree of pointer movement, the maximum
ARCHIVE INFORMATION

pointer sweep is 341.25° (4095 12 enabled or disabled with Bit RZ4. Writing Logic [0] results in
a typical RTZ event, automatically providing a Stop when a
stall condition is detected. A Logic [1] will result in RTZ
ADDRESS 100 - GAUGE RETURN TO ZERO
movement, causing a Stop if a Logic [0] is written to bit RZ0.
REGISTER (RTZR)
This feature is useful during development and
Gauge Return to Zero Register (RTZR), Table 12 below, characterization of RTZ requirements.
is written to return the gauge pointers to the zero position.
During an RTZ event, the pointer is returned to zero using full
Table 12. Gauge Return to Zero Register (RTZR)
Address 100

Bits D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Read – – – – – – – – – – – – –
Write 0 0 0 0 0 0 0 0 RZ4 0 RZ2 RZ1 0

The register bits in Table 12 are write-only. (RZ0) Bit D0
Return to Zero Enable. This bit must always be written
(RZ12:RZ5) Bits D12:D5 Logic [0].
These bits must be transmitted as Logic [0] for valid
commands. ADDRESS 101 - GAUGE RETURN TO ZERO
CONFIGURATION REGISTER
(RZ4) Bit D4 Gauge Return to Zero Configuration Register (RTZCR) is
This bit is used to enable an unconditional RTZ event. used to configure the Return to Zero Event, Table 13. It is
written to modify the: [listed as bullets for reading ease]
• 0 = Automatic Return to Zero
• 1 = Unconditional Return to Zero • Step time, or rate at which the pointer moves during an
RTZ event
(RZ3) Bit D3 • Integration blanking time, which is the time immediately
following the transition of a coil from a driven state to an
This bit must be transmitted as Logic [0] for valid open state in the RTZ mode
commands.
• Threshold of the RTZ integration register
(RZ2) Bit D2 Values used for this register should be selected during
development to optimize the RTZ for each application.
Return to Zero Direction bit. This bit is used to properly Selecting an RTZ step rate resulting in consistently
sequence the integrator, depending upon the desired zeroing successful zero detections depends on a clear understanding
direction. of the motor characteristics. Specifically, resonant
• 0 = Return to Zero will occur in the CCW direction frequencies exist due to the interaction between the motor
(PE7 = 0) and the pointer. This command allows for the selection of an
• 1 = Return to Zero will occur in the CW direction RTZ pointer speed away from these frequencies. Also, some
(PE7 =1) motors require a significant amount of time for the pointer to
settle to a steady state position when moving from one full
(RZ1) Bit D1 step position to the next. Consistent and accurate integration
Return to Zero Enable. This bit commands the gauge to values require that the pointer be stationary at the end of the
return the pointer to zero position. full step time.
• 0 = Return to Zero Disabled Bits RC3:RC0, RC12:RC11, and RC4 determine the time
spent at each full step during an RTZ event. Bits RC3:RC0
• 1 = Return to Zero Enabled
are used to select a t ranging from 0 ms (0000) to 61.44 ms

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 25
 FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS

(1111) in increments of 4.096 ms (refer to Table 14). The t and is compared to a threshold. Values above the threshold
is multiplied by the factor M, defined by bits RC12:RC11. The indicate a pointer is moving. Values below the threshold
product is then added to the blanking time, selected using bit indicate a stalled pointer, thereby resulting in the cessation of
RC4, to generate the full step time. The multiplier selected the RTZ event.
with RC12:RC11 will be 1 (00), 2 (01), or 4 (10) as illustrated The RTZ accumulator bits are signed and represented in
in the equations below. Note that the RC12:RC11 value of 8 two’s complement. After a full step of integration, a sign bit of
(11) is not recommended for use in a product design 0 is the indicator of an accumulator exceeding the decision
application, because of the potential for an RTZ accumulator threshold of 0, and the pointer is assumed to still be moving.
internal overflow, due to the long time step. The blanking time Similarly, if the sign bit is Logic [1] after a full step of
ARCHIVE INFORMATION

ARCHIVE INFORMATION
is either 512 µs when RC4 is Logic [0], or 768 µs when it is integration, the accumulator value is negative and the pointer
Logic [1].The full step time is calculated using the following is assumed to be stopped. The integrator and accumulator
equations: are initialized after each full step. If the PECCR command is
When D3:D0 (RC3:RC0) = 0000 written to clock out the RTZ accumulator values via the SO,
Full Step (t) = t x M+ blanking (t) (1) the OD14 bit corresponds to the sign bit of the RTZ
accumulator.
When D3:D0 (RC3:RC0) = 0000
Accurate pointer stall detection depends on a correctly
Full Step (t) = blanking (t) + 2.048 ms (2)
preloaded accumulator for specific gauge, pointer, and full
Note: In equation (2), a 2.048 ms offset is added to the full step combinations. Bits RC10:RC5 are used to offset the
step time when the RC3:RC0 = 0000. The full step time initial RTZ accumulator value, properly detecting a stalled
default value after a logic reset is 12.80 ms (RC12:RC11 = motor. The initial accumulator value at the start of a full step
00, RC4 = 0, and RC3:RC0 = 0011). of integration is negative. If the accumulator was correctly
If there are two full steps per degree of pointer movement, preloaded, a free moving pointer will result in a positive value
the pointer speed is 1/(Full Step x 2) deg/s. at the end of the integration time, and a stalled pointer will
Detecting pointer movement is accomplished by result in a negative value. The preloaded values associated
integrating the EMF present in the non-driven coil during the with each combination of bits RC10:RC5 are illustrated in
RTZ event. The integration circuitry is implemented using a Table 15. The accumulator should be loaded with a value
Sigma-Delta converter resulting in the placement of a value resulting in an accumulator MSB to Logic [1] when the motor
in the 15-bit RTZ accumulator at the end of each full step. The is stalled. For the default mode, after a power-up or any reset,
value in the RTZ accumulator represents the change in flux the 33977 device sets the accumulator value to -1.
Table 13. Return to Zero Register Configuration Register (RTZCR)
Address 101

Bits D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Read – – – – – – – – – – – – –
Write RC12 RC11 RC10 RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

The bits in Table 13 are write-only. Values range from -1 (00000000) to -1009 (11111111) as
shown in Table 15, the default value = 000000.
(RC12:RC11) Bits D12:D11
These bits, along with RC3:RC0 (D3:D0) and RC4 (D4), (RC4) Bit D4
determine the full step time and, therefore, the rate at which This bit determines the RTZ blanking time (blanking (t)).
the pointer will move during an RTZ event. The values of The default value = 0
D12:D11 determine the multiplier (M) used in equation (1) • 0 = 512 µs
(refer to the previous page). • 1 = 768 µs
RC12:RC11 = M; default value = 00
• 00 = 1 (RC3:RC0) Bits D3:D0
• 01 = 2 These bits, along with RC12:RC11 (D12:D11) and RC4
• 10 = 4 (D4), determine the time variables used to calculate the full
• 11 = 8 (Not to be used for design) step times with equations (1) or (2) illustrated above.
RC3:RC0 determines the t time. The t values range from 0
(RC10:RC5) Bits D10:D5 (0000) to 61.440 ms (1111) and are shown in Table 14. The
default t is 0 (0011).
These bits determine the value preloaded into the RTZ
integration accumulator to adjust the detection threshold. Note: Equation (2) (refer to the preceding page) is only
used to calculate the full step time if RC3:RC0 = 0000. Use
equation (1) for all other combinations of RC3:RC0.

33977

Analog Integrated Circuit Device Data

26 Freescale Semiconductor
 FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS

Table 14. RTZCR Full Step Time

Table 14. RTZCR Full Step Time 1 0 0 0 32.768
RC3 RC2 RC1 RC0 t (ms) 1 0 0 1 36.864
0 0 0 0 0.0 1 0 1 0 40.960
0 0 0 1 4.096 1 0 1 1 45.056
0 0 1 0 8.192 1 1 0 0 49.152
0 0 1 1 12.288 1 1 0 1 53.248

ARCHIVE INFORMATION
ARCHIVE INFORMATION

0 1 0 0 16.384 1 1 1 0 57.344
0 1 0 1 20.480 1 1 1 1 61.440
0 1 1 0 24.576
0 1 1 1 28.672

Table 15. RTZCR Accumulator Offset

RC10 RC9 RC8 RC7 RC6 RC5 Preload Value Initial Accumulator Value = (-16xPV) -1
0 0 0 0 0 0 0 -1
0 0 0 0 0 1 1 -17
0 0 0 0 1 0 2 -33
0 0 0 0 1 1 3 -49
0 0 0 1 0 0 4 -65
. . . . . . . .
. . . . . . . .
. . . . . . . .
1 1 1 1 1 1 63 -1009

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 27
 FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS

SO COMMUNICATION PECCR command determines the nature of the status data

When the CS pin is pulled low, the internal status register, that is clocked out of the SO pin. There are four different
as configured with the PECCR command bits PE11:PE8, is types of status information available:
loaded into the output register and the data is clocked out 1. Device Status (Table 16)
MSB (OD15) first. Following a CS transition 0 to 1, the device 2. RTZ Accumulator Status (Table 17)
determines if the shifted-in message was of a valid length (a 3. Gauge Pointer Position Status (Table 18)
valid message length is one that is greater than 0 bits and a
4. Gauge Pointer Velocity Status (Table 19)
multiple of 16 bits) and, if so, latches the incoming data into
the appropriate registers. At this time, the SO pin is tri-stated Once a specific status type is selected, it will not change
ARCHIVE INFORMATION

ARCHIVE INFORMATION
and the status register is now able to accept new status until either the PECCR command bits PE11:PE8 (D11:D8)
information. Fault status information will be latched and held are written to select another or the device is reset. Each of the
until the Device Status Output register is selected and it is Status types and the PECCR bit necessary to select them ar
clocked out via the SO. If the message length was described in the following paragraphs.
determined to be invalid, the fault information will not be
cleared and will be transmitted again during the next valid SPI DEVICE STATUS INFORMATION
message. Pointer status information bits (e.g., pointer Most recent valid PECCR command resulting in the Device
position, velocity, and commanded position status) will
Status output:
always reflect the real time state of the pointer. Any bits
clocked out of the SO pin after the first 16 are representative
of the initial message bits clocked into the SI pin since the CS D11 D10 D9 D8
pin first transitioned to a Logic [0]. This feature is useful for 0 x x x
daisy-chaining devices as well as message verification. As
described above, the last valid write to bits PE11:PE8 of the x = Don’t Care

Table 16. Device Status Output Register

Bits OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Read ST15 DIR ST13 0POS ST11 CMD OV UV CAL OVUV ST5 MOV ST3 RTZ ST1 OT
Write – – – – – – – – – – – – – – – –

The bits in Table 16 are read-only bits. • 0 = At commanded position

• 1 = Not at commanded position
(ST15) Bit OD15
This bit has no meaning. Overvoltage Indication (OV) Bit OD9
A Logic [1] on this bit indicates VPWR voltage exceeded the
(DIR) Bit OD14 upper limit of VPWROV since the last SPI communication.
This bit indicates the direction that the Gauge is moving. Refer to the Static Electrical Characteristics Table 3 under
POWER INPUT.
• 0 = Toward position 0
• 1 = Away from position 0 An overvoltage event will automatically disable the driver
outputs. Because the pointer may not be in the expected
(ST13) Bit OD13 position, the master may want to re-calibrate the pointer
position with an RTZ command after the voltage returns to a
This bit has no meaning. normal level. For an overvoltage event, both gauges must be
re-enabled as quickly as this flag returns to Logic [0]. The
(0POS) Bit OD12 state machine will continue to operate properly as long as
This bit indicates the configured Position 0 for the Gauge. VDD is within the normal range.
• 0 = Farthest CCW • 0 = Normal range
• 1 = Farthest CW • 1 = Battery voltage exceeded VPWROV

(ST11) Bit OD11 Undervoltage Indication (UV) Bit OD8

This bit has no meaning. A Logic [1] on this bit indicates the VPWR voltage fell below
VPWRUV since the last SPI communication. Refer to the Static
(CMD) Bit OD10 Electrical Characteristics Table 3 under the heading of
POWER INPUT. An undervoltage event is just flagged;
This bit indicates if the Gauge is at the most recently
however, at some voltage level below 4.0 V, the outputs turn
commanded position.
OFF and the state machine resets. Because the pointer may

33977

Analog Integrated Circuit Device Data

28 Freescale Semiconductor
 FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS

not be in the expected position, the master may want to re- This bit may also be used to determine if the Gauge is
calibrate the pointer position with an RTZ command after the enabled or disabled.
voltage returns to a normal level. For an undervoltage vent, • 0 = Gauge position has not changed since the last SPI
both gauges may need to be re-enabled as quickly as this command
flag returns to Logic [0]. The state machine will continue to • 1 = Gauge pointer position has changed since the last
operate properly as long as VDD is within the normal range. SPI command
• 0 = Normal range
• 1 = Battery voltage fell below VPWRUV ST3 (OD3) - This bit has no meaning

ARCHIVE INFORMATION
ARCHIVE INFORMATION

Calibrated Clock out of Specification (CAL) Bit OD7 RTZ0 Is Enabled or Disabled (RTZ) Bit OD2
Reading Logic [1] on this bit indicates the clock count A Logic [1] on this bit indicates the gauge is in the process
calibrated to a value outside the expected range given the of returning to the zero position as requested with the RTZ
tolerance specified by tCLC in the Dynamic Electrical command. This bit continues to indicate Logic [1] until the SPI
Characteristics Table 4 under POWER OUTPUT and message following a detection of the zero position, or the
CLOCK TIMING. RTZ feature is commanded OFF using the RTZ message.
• 0 = Clock within specification • 0 = Return to Zero disabled
• 1 = Clock out of specification • 1 = Return to Zero enabled successfully

Undervoltage or Overvoltage Indication (OVUV) Bit OD6 (ST1) Bit OD1

A Logic [1] on this bit indicates VPWR voltage fell to a level This bit has no meaning.
below the VPWRUV since the last SPI communication. Refer
to the Static Electrical Characteristics table, Table 3 under Gauge Driver Junction Overtemperature (OT) Bit OD0
the subheading INPUT POWER. An undervoltage event is A Logic [1] on this bit indicates that the coil drive circuitry
just flagged, while an overvoltage event automatically has exceeded the maximum allowable junction temperature
disables the drive outputs. Because the pointer may not be in since the last SPI communication and that the Gauge has
the expected position, the master may want to re-calibrate been disabled. It is recommended that the pointer be re-
the pointer with an RTZ command after the voltage returns to calibrated using the RTZ command after re-enabling the
normal level. For an overvoltage event, both gauges must be gauge using the PECCR command. This bit remains Logic [1]
re-enabled as soon as this flag returns to Logic [0]. The state until the gauge is re-enabled.
machine will continue to operate properly as long as VDD is
• 0 = Temperature within range
within the normal range.
• 1 = Maximum allowable junction temperature condition
• 0 = Normal range
is reached
• 1 = Battery voltage fell below VPWRUV or exceeded
VPWROV
RTZ ACCUMULATOR STATUS INFORMATION
(ST5) Bit OD5 Most recent valid PECCR command resulting in the RTZ
This bit has no meaning Accumulator status output:
D11 D10 D9 D8
Gauge Movement Since last SPI Communication (MOV)
1 0 x x
Bit OD4
A Logic [1] on this bit indicates the Gauge pointer position x = Don’t Care
has changed since the last SPI command. This information
allows the master to confirm the pointer is moving as [Used headings to distinguish bits and accompanying text.]
commanded.

Table 17. RTZ Accumulator Status Output Register

Bits OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Read RTZ ACC14 ACC13 ACC12 ACC11 ACC10 ACC9 ACC8 ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0
Write – – – – – – – – – – – – – – – –

The bits in Table 17 are read-only bits. (RTZ) Bit OD15

RTZ Bit Is Enabled or Disabled. Reading Logic [1] on this
bit indicates that the Gauge is in the process of returning to
the zero position as requested with the RTZ command. This

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 29
 FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS

bit will continue to indicate Logic [1] until the SPI message The analog-to-digital converter's linear input range covers
following a detection of the zero position, or after the RTZ the expected magnitude of motor back e.m.f. signals, which
feature is commanded OFF using the RTZ message. is usually less than 500mV. Input signals greater than this will
• 0 = Return to Zero disabled not cause any damage (the circuit is connected to the motor
• 1 = Return to Zero enabled successfully H-Bridge drivers, and thus is exposed to the full magnitude of
the drive voltages), but may cause some small loss of
[Corrected original entry above to ACC2]
linearity. A typical plot of output vs. input is shown in
Figure 13 for 4ms step times.
(ACC14:ACC0) Bits OD14:OD0
ARCHIVE INFORMATION

ARCHIVE INFORMATION
These 15 bits are from the RTZ accumulator. They GAUGE POINTER POSITION STATUS
represent the integrated signal present on the non-driven coil INFORMATION
during an RTZ event. These bits are Logic [0] after power-on
Most recent valid PECCR command resulting in the
reset, or after the RST pin transitions from Logic [0] to [1].
Gauge Pointer Position status output:
After an RTZ event, they will represent the last RTZ
accumulator result before the RTZ was stopped.
ACC14 is the MSB and is the sign bit used for zero D11 D10 D9 D8
detection. Negative numbers have MSB Logic [1] and are
coded in twos complement. 1 1 0 0
omitted “don’t care--because N/A

Figure 13. RTZ Accumulator (Typical)

Table 18. Gauge Pointer Position Status Output Register
Bits OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Read ENB DIR DIRC CMD POS11 POS10 POS9 POS8 POS7 POS5 POS5 POS4 POS3 POS2 POS1 POS0
Write – – – – – – – – – – – – – – – –

The bits in Table 18 are read-only bits. (DIRC) Bit OD13

This bit is used to determine whether the direction of the
(ENB) Bit OD15 most recent pointer movement is toward the last commanded
This bit indicates whether the Gauge is enabled. position or away from it.
• 0 = Disabled • 0 = Direction of the pointer movement is toward the
commanded position
• 1 = Enabled
• 1 = Direction of the pointer movement is away from the
(DIR) Bit OD14 commanded position

This bit indicates the direction the Gauge is moving. (CMD) Bit OD12
• 0 = Toward position 0 This bit indicates whether the gauge is at the most recently
• 1 = Away from position 0 commanded position.
• 0 = At commanded position
• 1 = Not at commanded position

33977

Analog Integrated Circuit Device Data

30 Freescale Semiconductor
 FUNCTIONAL DEVICE OPERATION

(POS11:POS0) Bits OD11:OD0

D11 D10 D9 D8
These 12 bits represent the actual position of the pointer
at the time CS transitions to a Logic [0]. 1 1 1 x
x = Don’t Care
GAUGE POINTER VELOCITY STATUS
INFORMATION
Most recent valid PECCR command resulting in the
Gauge and 1 Pointer Velocity status output:

ARCHIVE INFORMATION
ARCHIVE INFORMATION

Table 19. Gauge Pointer Velocity STatus Output Register

Bits OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Read V15 V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0
Write – – – – – – – – – – – – – – – –

The bits in Table 19 are read-only bits. (V7:V0) Bits OD7:OD0

These eight bits represent the step table value, [that
(V15:V8) Bits OD15:OD8 deleted PV] indicating the actual velocity step location (refer
These eight bits have no meaning. Velocity position that to Table 19) of the Gauge pointer at the time that the CS
identifies it in the un-truncated ramp (e.g., if RS = 2, then the transitions to a Logic [0].
velocity step location will be 3 when the pointer is at the
commanded position).

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 31
 TYPICAL APPLICATIONS

TYPICAL APPLICATIONS

The 33977 is an extremely versatile device that can be following figures. For applications where configurable pointer
used in a variety of applications, Figure 1. The acceleration response and damping are desirable, consider the features
and deceleration ramps have been designed for applications of the MC33976. Figure 14 shows the characteristics of the
where smooth movement is of the highest priority. These acceleration ramp.
ramps are fixed and the characteristics can be seen in the
ARCHIVE INFORMATION

ARCHIVE INFORMATION
6000

76m s
5000

4000
SP E E D (usteps/S)

Ideal
Acceleration
(4500 deg/s^2)
3000
M C 33977
Acceleration

2000

1000

0
0 20000 40000 60000 80000 100000 120000 140000 160000 180000

TIM E (us)

Figure 14. Acceleration Response Characteristics

33977

Analog Integrated Circuit Device Data

32 Freescale Semiconductor
 TYPICAL APPLICATIONS

Figure 15 illustrates the deceleration damping characteristics of the device with the hold counts enabled and disabled.

1250

1200
MC33977
1150
without

Position (usteps)
Hold Counts

ARCHIVE INFORMATION
ARCHIVE INFORMATION

1100
MC33977
1050
with
Hold Counts 1000

950

900

850

800
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Time (s)

Figure 15. Deceleration Damping Response Examples

Table 20 provides a step-by-step example of configuring example is intended to familiarize users with some of the
and using many of the features designed into the IC This device features.

Table 20. 33977 Setup, Configuration, and Usage Example

Reference Table
Step Command Description
and/or Figure
a) Enables the gauge
• Bit PE0: Gauge enable bit
b) Clock calibration Table 9,
1 PECCR
• Bit PE3: Enables calibration procedure Figure 8
• Bit PE4: Set clock f = 1.0 MHz maximum or nominal
c) Send 8.0 µs pulse on CS to calibrate 1.0 MHz clock
a) Set RTZ full step time Table 13
• Bit RC3:RC0 Table 14
b) Set RTZ blanking time Table 15
• Bits RC4 Table 9
2 RTZCR
c) Preload RTZ accumulator
• Bits RC12:RC11 and RC10:RC5 Table 16
d) Check SO for an out-of-range clock calibration
• Is Bit CAL Logic [1}? If so, repeat Steps 1 and 2
a) Move pointer to position 12 prior to RTZ Table 11
4 POSR b) Check SO to determine if gauge has moved Table 9
• Is bit MOV (OD4) Logic [1]? If so, the gauge moved to the first microstep Table 16
a) Send null command to determine if gauges moved
• Bit PE12
b) Check SO to determine if the gauge has moved Table 9
5 PECCR • Is bit MOV (OD4) Logic [1]? If so, the gauge moved another microstep since the last Table 9
SPI message. Keep track of movement and if 12 steps are finished, and both gauges Table 16
are at a static position, the RTZ. Otherwise, repeat steps a) and b).
• Bit CMD (OD10) could also be monitored to determine if the pointer is static.

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 33
 TYPICAL APPLICATIONS

Table 20. 33977 Setup, Configuration, and Usage Example

Reference Table
Step Command Description
and/or Figure
a) Return the gauge to the zero stop using the RTZ command
• Bit RZ1 enables or disables an RTZ Table 12
6 RTZ • Bits RZ2 and PE7 select the direction
Table 9
b) Select the RTZ accumulator bits to clock out on the SO bits using bits PE11:PE10. Table 15
These will be used if characterizing the RTZ.
ARCHIVE INFORMATION

ARCHIVE INFORMATION
a) Check the status of the RTZ by sending the null command to monitor bit RTZ of the Table 9
Device Status SO. Table 16
7 PECCR • Bit PE12 is the null command
b) Is RTZ (OD2) Logic [1]? If not, the gauge is still returning and null command should be
resent.
a) Change the maximum velocity of the gauge
Table 9
10 VELR • Bit V8 enables a change to the maximum velocity
Table 6
• Bits V7:V10 determine the maximum velocity position from Table 6, Velocity Table
a) Position gauge pointer
• Bits P011:P00: Desired pointer position
b) Check SO for out-of-range VPWR
• Is bit OVUV (OD6) Logic [1] If so, use UV (OD8) and OV (OD9) to decide whether to
Table 11
11 POSR RTZ after valid VPWR
Table 6
c) Check SO for overtemperature
• Is bit OT Logic [1]? If so, enable driver again. If OT continues to indicate
overtemperature, shut down the gauge.
• Once OT returns to normal, re-establish the zero reference by RTZ command.
a) Return the pointer close to zero position using POSR
13 POSR Table 11
b) Move pointer position at least 12 microsteps CW to the nearest full step prior to RTZ
f) Send null command to see if gauges moved
• Bit PE12
g) Check SO to determine if the gauge moved.
Table 9
15 PECCR • Is bit MOV (OD4) Logic [1]? If so, the gauge moved another microstep since the last
Table 16
SPI message. Keep track of movement and if 12 steps are finished, and both gauges
are at a static position, then RTZ. Otherwise, repeat steps a) and b).
• Bit CMD (OD10) could also be monitored to determine the pointer is static.
a) Return the gauge to the zero stop using the RTZ command.
• Bit RZ1 enables or disables an RTZ TABLE 9
16 RTZ • Bits RZ2 and PE7 select the direction TABLE 12
b) Select the RTZ accumulator bits clocking out on the SO bits using bits PE11:PE10 TABLE 16
These will be used if characterizing the RTZ.
a) Check the status of the RTZ by sending the null command to monitor SO bit RTZ
• Bit PE12 is the null command TABLE 9
17 PECCR
TABLE 16
b) Is RTZ Logic [0]? If not, the gauge is still returning and null command should be resent
a) Disable the gauge driver and go to standby
• Bit PE0:PE1 disable the gauge
20 PECCR TABLE 9
b) Put the device to sleep
• RST pin is pulled to Logic [0]

33977

Analog Integrated Circuit Device Data

34 Freescale Semiconductor
 PACKAGING
PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current revision of the package, visit www.freescale.com and do a keyword search using the “98A” number listed
below.

ARCHIVE INFORMATION
ARCHIVE INFORMATION

DW SUFFIX
EG SUFFIX (PB-FREE)
24-PIN
PLASTIC PACKAGE
98ASB42344B
ISSUE F

33977

Analog Integrated Circuit Device Data

Freescale Semiconductor 35
 REVISION HISTORY

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES

1.0 8/2006 • Initial release

2.0 1/2007 • Updated to the current Freescale format
• Revised Internal Block Diagram to enhance readability
ARCHIVE INFORMATION

• Added parameter Peak Package Reflow Temperature During Reflow (4), (5) on page 4

ARCHIVE INFORMATION
and notes (4) and (5)
• Made wording additions to Address 101 - Gauge Return to Zero Configuration Register
on page 25 and (RC12:RC11) Bits D12:D11 on page 26
• Added ADC Gain (12), (14) to Static Electrical Characteristics table
• Added RTZ Accumulator (Typical) on page 30 and accompanying text

33977

Analog Integrated Circuit Device Data

36 Freescale Semiconductor
ARCHIVE INFORMATION

ARCHIVE INFORMATION
How to Reach Us:
Home Page:
www.freescale.com RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free
Web Support: counterparts. For further information, see http://www.freescale.com or contact your
http://www.freescale.com/support Freescale sales representative.

USA/Europe or Locations Not Listed:

Freescale Semiconductor, Inc. For information on Freescale’s Environmental Products program, go to http://
Technical Information Center, EL516 www.freescale.com/epp.
2100 East Elliot Road
Tempe, Arizona 85284
+1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center Information in this document is provided solely to enable system and software
Schatzbogen 7 implementers to use Freescale Semiconductor products. There are no express or
81829 Muenchen, Germany implied copyright licenses granted hereunder to design or fabricate any integrated
+44 1296 380 456 (English) circuits or integrated circuits based on the information in this document.
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French) Freescale Semiconductor reserves the right to make changes without further notice to
www.freescale.com/support any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Japan: Freescale Semiconductor assume any liability arising out of the application or use of any
Freescale Semiconductor Japan Ltd. product or circuit, and specifically disclaims any and all liability, including without
Headquarters limitation consequential or incidental damages. “Typical” parameters that may be
ARCO Tower 15F provided in Freescale Semiconductor data sheets and/or specifications can and do vary
1-8-1, Shimo-Meguro, Meguro-ku,
in different applications and actual performance may vary over time. All operating
Tokyo 153-0064
Japan parameters, including “Typicals”, must be validated for each customer application by
0120 191014 or +81 3 5437 9125 customer’s technical experts. Freescale Semiconductor does not convey any license
support.japan@freescale.com under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
Asia/Pacific: surgical implant into the body, or other applications intended to support or sustain life,
Freescale Semiconductor Hong Kong Ltd. or for any other application in which the failure of the Freescale Semiconductor product
Technical Information Center could create a situation where personal injury or death may occur. Should Buyer
2 Dai King Street purchase or use Freescale Semiconductor products for any such unintended or
Tai Po Industrial Estate unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
Tai Po, N.T., Hong Kong
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
+800 2666 8080
support.asia@freescale.com claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
For Literature Requests Only: unintended or unauthorized use, even if such claim alleges that Freescale
Freescale Semiconductor Literature Distribution Center Semiconductor was negligent regarding the design or manufacture of the part.
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
Fax: 303-675-2150 All other product or service names are the property of their respective owners.
LDCForFreescaleSemiconductor@hibbertgroup.com © Freescale Semiconductor, Inc., 2007. All rights reserved.

MC33977
Rev. 2.0
1/2007
Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

NXP:
MCZ33977EG MCZ33977EGR2