MC14536B

Programmable Timer
The MC14536B programmable timer is a 24–stage binary ripple
counter with 16 stages selectable by a binary code. Provisions for an
on–chip RC oscillator or an external clock are provided. An on–chip
monostable circuit incorporating a pulse–type output has been
included. By selecting the appropriate counter stage in conjunction
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with the appropriate input clock frequency, a variety of timing can be
achieved.
• 24 Flip–Flop Stages — Will Count From 20 to 224 MARKING
DIAGRAMS
• Last 16 Stages Selectable By Four–Bit Select Code 16
• 8–Bypass Input Allows Bypassing of First Eight Stages PDIP–16
MC14536BCP
• Set and Reset Inputs P SUFFIX
CASE 648 AWLYYWW
• Clock Inhibit and Oscillator Inhibit Inputs 1
• On–Chip RC Oscillator Provisions
16
• On–Chip Monostable Output Provisions
• Clock Conditioning Circuit Permits Operation With Very Long Rise SOIC–16 14536B
and Fall Times DW SUFFIX
• Test Mode Allows Fast Test Sequence CASE 751G
AWLYYWW
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
1

Schottky TTL Load Over the Rated Temperature Range 16

SOEIAJ–16
F SUFFIX MC14536B
CASE 966 ALYW

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) 1

Symbol Parameter Value Unit

A = Assembly Location
VDD DC Supply Voltage Range –0.5 to +18.0 V WL, L = Wafer Lot
YY, Y = Year
Vin, Vout Input or Output Voltage Range –0.5 to VDD + 0.5 V
WW, W = Work Week
(DC or Transient)
Iin, Iout Input or Output Current ±10 mA
(DC or Transient) per Pin
ORDERING INFORMATION
PD Power Dissipation, 500 mW
per Package (Note 3.) Device Package Shipping

TA Operating Temperature Range –55 to +125 °C MC14536BCP PDIP–16 2000/Box

Tstg Storage Temperature Range –65 to +150 °C MC14536BDW SOIC–16 47/Rail
TL Lead Temperature 260 °C
MC14536BDWR2 SOIC–16 1000/Tape & Reel
(8–Second Soldering)
2. Maximum Ratings are those values beyond which damage to the device MC14536BF SOEIAJ–16 See Note 1.
may occur. 1. For ordering information on the EIAJ version of
3. Temperature Derating: the SOIC packages, please contact your local
Plastic “P and D/DW” Packages: – 7.0 mW/
C From 65
C To 125
C ON Semiconductor representative.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS  (Vin or Vout)  VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.

 Semiconductor Components Industries, LLC, 2000 1 Publication Order Number:

August, 2000 – Rev. 6 MC14536B/D
 MC14536B

PIN ASSIGNMENT

SET 1 16 VDD
RESET 2 15 MONO IN
IN 1 3 14 OSC INH
OUT 1 4 13 DECODE
OUT 2 5 12 D
8-BYPASS 6 11 C
CLOCK INH 7 10 B
VSS 8 9 A

BLOCK DIAGRAM
CLOCK INH. RESET SET 8 BYPASS
7 2 1 6

OSC. INHIBIT14

STAGES STAGES 9 THRU 24

IN1 Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
3 1 THRU 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

4 5
OUT1 OUT2 A9
B10
C11 DECODER
VDD = PIN 16 D12
VSS = PIN 8
MONOSTABLE DECODE
MONO-IN15 13
MULTIVIBRATOR OUT

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 MC14536B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
Vdc Min
– 55
C
Max Min
25
C
Typ (4.) Max Min
125
C
Max
Characteristic Symbol Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) Pins 4 & 5 5.0 – 0.25 — – 0.25 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 — mAdc
(VOH = 4.6 Vdc) Pin 13 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.010 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.020 10 — 300
15 — 20 — 0.030 20 — 600
Total Supply Current (5.) (6.) IT 5.0 IT = (1.50 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.30 µA/kHz) f + IDD
Per Package) 15 IT = (3.55 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25
C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.

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 MC14536B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25
C)
Characteristic
Output Rise and Fall Time (Pin 13)
Symbol
tTLH,
VDD Min Typ (8.) Max Unit
ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
Clock to Q1, 8–Bypass (Pin 6) High tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 1715 ns 5.0 — 1800 3600
tPLH, tPHL = (0.66 ns/pF) CL + 617 ns 10 — 650 1300
tPLH, tPHL = (0.5 ns/pF) CL + 425 ns 15 — 450 1000
Clock to Q1, 8–Bypass (Pin 6) Low tPLH, µs
tPLH, tPHL = (1.7 ns/pF) CL + 3715 ns tPHL 5.0 — 3.8 7.6
tPLH, tPHL = (0.66 ns/pF) CL + 1467 ns 10 — 1.5 3.0
tPLH, tPHL = (0.5 ns/pF) CL + 1075 ns 15 — 1.1 2.3
Clock to Q16 tPLH, µs
tPHL, tPLH = (1.7 ns/pF) CL + 6915 ns tPHL 5.0 — 7.0 14
tPHL, tPLH = (0.66 ns/pF) CL + 2967 ns 10 — 3.0 6.0
tPHL, tPLH = (0.5 ns/pF) CL + 2175 ns 15 — 2.2 4.5
Reset to Qn tPHL ns
tPHL = (1.7 ns/pF) CL + 1415 ns 5.0 — 1500 3000
tPHL = (0.66 ns/pF) CL + 567 ns 10 — 600 1200
tPHL = (0.5 ns/pF) CL + 425 ns 15 — 450 900
Clock Pulse Width tWH 5.0 600 300 — ns
10 200 100 —
15 170 85 —
Clock Pulse Frequency fcl 5.0 — 1.2 0.4 MHz
(50% Duty Cycle) 10 — 3.0 1.5
15 — 5.0 2.0
Clock Rise and Fall Time tTLH, 5.0 —
tTHL 10 No Limit
15
Reset Pulse Width tWH 5.0 1000 500 — ns
10 400 200 —
15 300 150 —
7. The formulas given are for the typical characteristics only at 25
C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

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 MC14536B

PIN DESCRIPTIONS

INPUTS OSC INHIBIT (Pin 14) — A high level on this pin stops
SET (Pin 1) — A high on Set asynchronously forces the RC oscillator which allows for very low–power standby
Decode Out to a high level. This is accomplished by setting operation. May also be used, in conjunction with an external
an output conditioning latch to a high level while at the same clock, with essentially the same results as the Clock Inhibit
time resetting the 24 flip–flop stages. After Set goes low input.
(inactive), the occurrence of the first negative clock MONO–IN (Pin 15) — Used as the timing pin for the
transition on IN1 causes Decode Out to go low. The on–chip monostable multivibrator. If the Mono–In input is
counter’s flip–flop stages begin counting on the second connected to VSS, the monostable circuit is disabled, and
negative clock transition of IN1. When Set is high, the Decode Out is directly connected to the selected Q output.
on–chip RC oscillator is disabled. This allows for very The monostable circuit is enabled if a resistor is connected
low–power standby operation. between Mono–In and VDD. This resistor and the device’s
RESET (Pin 2) — A high on Reset asynchronously internal capacitance will determine the minimum output
forces Decode Out to a low level; all 24 flip–flop stages are pulse widths. With the addition of an external capacitor to
also reset to a low level. Like the Set input, Reset disables VSS, the pulse width range may be extended. For reliable
the on–chip RC oscillator for standby operation. operation the resistor value should be limited to the range of
IN1 (Pin 3) — The device’s internal counters advance on 5 kΩ to 100 kΩ and the capacitor value should be limited to
the negative–going edge of this input. IN1 may be used as an a maximum of 1000 pf. (See figures 3, 4, 5, and 10).
external clock input or used in conjunction with OUT1 and A, B, C, D (Pins 9, 10, 11, 12) — These inputs select the
OUT2 to form an RC oscillator. When an external clock is flip–flop stage to be connected to Decode Out. (See the truth
used, both OUT1 and OUT2 may be left unconnected or tables.)
used to drive 1 LSTTL or several CMOS loads.
OUTPUTS
8–BYPASS (Pin 6) — A high on this input causes the first
8 flip–flop stages to be bypassed. This device essentially OUT1, OUT2 (Pin 4, 5) — Outputs used in conjunction
becomes a 16–stage counter with all 16 stages selectable. with IN1 to form an RC oscillator. These outputs are
Selection is accomplished by the A, B, C, and D inputs. (See buffered and may be used for 20 frequency division of an
the truth tables.) external clock.
CLOCK INHIBIT (Pin 7) — A high on this input DECODE OUT (Pin 13) — Output function depends on
disconnects the first counter stage from the clocking source. configuration. When the monostable circuit is disabled, this
This holds the present count and inhibits further counting. output is a 50% duty cycle square wave during free run.
However, the clocking source may continue to run. TEST MODE
Therefore, when Clock Inhibit is brought low, no oscillator
start–up time is required. When Clock Inhibit is low, the The test mode configuration divides the 24 flip–flop
counter will start counting on the occurrence of the first stages into three 8–stage sections to facilitate a fast test
negative edge of the clocking source at IN1. sequence. The test mode is enabled when 8–Bypass, Set and
Reset are at a high level. (See Figure 8.)

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 MC14536B

TRUTH TABLES

Input Input
Stage Selected Stage Selected
8–Bypass D C B A for Decode Out 8–Bypass D C B A for Decode Out
0 0 0 0 0 9 1 0 0 0 0 1
0 0 0 0 1 10 1 0 0 0 1 2
0 0 0 1 0 11 1 0 0 1 0 3
0 0 0 1 1 12 1 0 0 1 1 4
0 0 1 0 0 13 1 0 1 0 0 5
0 0 1 0 1 14 1 0 1 0 1 6
0 0 1 1 0 15 1 0 1 1 0 7
0 0 1 1 1 16 1 0 1 1 1 8
0 1 0 0 0 17 1 1 0 0 0 9
0 1 0 0 1 18 1 1 0 0 1 10
0 1 0 1 0 19 1 1 0 1 0 11
0 1 0 1 1 20 1 1 0 1 1 12
0 1 1 0 0 21 1 1 1 0 0 13
0 1 1 0 1 22 1 1 1 0 1 14
0 1 1 1 0 23 1 1 1 1 0 15
0 1 1 1 1 24 1 1 1 1 1 16

FUNCTION TABLE

Clock OSC Decode

In1 Set Reset Inh Inh Out 1 Out 2 Out
0 0 0 0 No
Change
0 0 0 0 Advance to
next state
X 1 0 0 0 0 1 1
X 0 1 0 0 0 1 0
X 0 0 1 0 — — No
Change
X 0 0 0 1 0 1 No
Change
0 0 0 0 X 0 1 No
Change
1 0 0 0 Advance to
next state
X = Don’t Care

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 RESET
2 8-BYPASS
6

OSC INHIBIT
14

3 STAGES
STAGES STAGES
T 1 8 T 9 10 THRU 16 17 18 THRU 24
2 THRU 7 15
IN1 23

7
4 OUT 2 5
OUT 1 A9
S B10
C C11 DECODER
Q
MC14536B

D12

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LOGIC DIAGRAM

En R

SET DECODER
1 OUT
7 13
CLOCK
INHIBIT

15 VDD = PIN 16
MONO-IN VSS = PIN 8
 MC14536B

TYPICAL RC OSCILLATOR CHARACTERISTICS

(For Circuit Diagram See Figure 11 In Application)
8.0 100
VDD = 15 V VDD = 10 V
50
4.0 f AS A FUNCTION

f, OSCILLATOR FREQUENCY (kHz)

20 OF RTC
FREQUENCY DEVIATION (%)

(C = 1000 pF)
0 10
(RS ≈ 2RTC)
10 V 5.0
-
4.0
2.0 f AS A FUNCTION
OF C
-
8.0 1.0 (RTC = 56 kΩ)
5.0 V
0.5 (RS = 120 k)
-
12
RTC = 56 kΩ, RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C 0.2
C = 1000 pF RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
-
16 0.1
-
55 -
25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 M
RTC, RESISTANCE (OHMS)
* Device Only. TA, AMBIENT TEMPERATURE (°C)*
0.0001 0.001 0.01 0.1
C, CAPACITANCE (µF)
Figure 1. RC Oscillator Stability Figure 2. RC Oscillator Frequency as a
Function of RTC and C

MONOSTABLE CHARACTERISTICS
(For Circuit Diagram See Figure 10 In Application)
100 100
FORMULA FOR CALCULATING tW IN FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS: MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX • CX 0.85 tW = 0.00247 RX • CX 0.85
WHERE R IS IN kΩ, CX IN pF. WHERE R IS IN kΩ, CX IN pF.
t W, PULSE WIDTH ( µs)

t W, PULSE WIDTH ( µs)

10 10

RX = 100 kΩ RX = 100 kΩ
50 kΩ 50 kΩ
1.0 10 kΩ 1.0
5 kΩ 10 kΩ
TA = 25°C 5 kΩ TA = 25°C
VDD = 5 V VDD = 10 V
0.1 0.1
1.0 10 100 1000 1.0 10 100 1000
CX, EXTERNAL CAPACITANCE (pF) CX, EXTERNAL CAPACITANCE (pF)
Figure 3. Typical CX versus Pulse Width Figure 4. Typical CX versus Pulse Width
@ VDD = 5.0 V @ VDD = 10 V

100
FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX • CX 0.85
WHERE R IS IN kΩ, CX IN pF.
t W, PULSE WIDTH ( µs)

10

RX = 100 kΩ
50 kΩ
1.0
10 kΩ
5 kΩ TA = 25°C
VDD = 15 V
0.1
1.0 10 100 1000
CX, EXTERNAL CAPACITANCE (pF)
Figure 5. Typical CX versus Pulse Width
@ VDD = 15 V

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 MC14536B

VDD

0.01 µF
500 µF ID
CERAMIC

SET 20 ns 20 ns
RESET OUT 1
8-BYPASS CL VDD
PULSE IN1 50%
IN1
GENERATOR tWL tWH
C INH SET
MONO IN OUT OUT 1
RESET 90%
OSC INH 2 OUT 50%
CL 8-BYPASS 10%
A PULSE
IN1 tPLH tPHL
B GENERATOR
C INH tTLH tTHL
C DECODE MONO IN OUT
D OUT CL 2
OSC INH
VSS A
B
C DECODE
20 ns 20 ns D OUT CL
90% VSS
50%
10%
50%
DUTY CYCLE

Figure 6. Power Dissipation Test Figure 7. Switching Time Test Circuit and Waveforms
Circuit and Waveform

FUNCTIONAL TEST SEQUENCE VDD

Test function (Figure 8) has been included for the SET

PULSE RESET OUT 1
reduction of test time required to exercise all 24 counter
GENERATOR 8-BYPASS
stages. This test function divides the counter into three IN1
8–stage sections and 255 counts are loaded in each of the C INH
8–stage sections in parallel. All flip–flops are now at a “1”. MONO IN OUT
OSC INH 2
The counter is now returned to the normal 24–stages in
A
series configuration. One more pulse is entered into In1
B
which will cause the counter to ripple from an all “1” state C DECODE
to an all “0” state. D OUT

VSS

Figure 8. Functional Test Circuit

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 MC14536B

FUNCTIONAL TEST SEQUENCE

Inputs Outputs Comments
Decade Out
In1 Set Reset 8–Bypass Q1 thru Q24 All 24 stages are in Reset mode.
1 0 1 1 0
1 1 1 1 0 Counter is in three 8 stage sections in parallel mode.
0 1 1 1 0 First “1” to “0” transition of clock.
1
0
— 1 1 1 255 “1” to “0” transitions are clocked in the counter.
—
—
0 1 1 1 1 The 255 “1” to “0” transition.
0 0 0 0 1 Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from “1” to “0”.
1 0 0 0 1 In1 Switches to a “1”.
0 0 0 0 0 Counter Ripples from an all “1” state to an all “0” state.

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 MC14536B

+V

16
6 VDD
8-BYPASS
9 4
A OUT 1
10 B
11 C
12
D
2 OUT 2 5
RESET
14
OSC INH
15
MONO-IN
PULSE 1
SET
GEN. 7
CLOCK INH
3 DECODE OUT 13
PULSE IN1
VSS
GEN.
CLOCK 8

IN1

SET

CLOCK INH

DECODE OUT

POWER UP

NOTE: When power is first applied to the device, Decode Out can be either at a high or low state.
On the rising edge of a Set pulse the output goes high if initially at a low state. The output
remains high if initially at a high state. Because Clock Inh is held high, the clock source on
the input pin has no effect on the output. Once Clock Inh is taken low, the output goes low
on the first negative clock transition. The output returns high depending on the 8–Bypass,
A, B, C, and D inputs, and the clock input period. A 2n frequency division (where n = the
number of stages selected from the truth table) is obtainable at Decode Out. A 20–divided
output of IN1 can be obtained at OUT1 and OUT2.

Figure 9. Time Interval Configuration Using an External Clock, Set,

and Clock Inhibit Functions
(Divide–by–2 Configured)

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 MC14536B

+V

16
6 VDD
8-BYPASS
RX 9 4
A OUT 1
10 B
11 C
12
D
PULSE 2 5
RESET OUT 2
GEN. 1
SET
7
CLOCK INH
15
MONO-IN
14
CLOCK INH
3 DECODE OUT 13
CLOCK IN1
VSS
CX 8

IN1

RESET

*tw ≈ .00247 • RX • CX0.85

DECODE OUT tw in µsec

RX in kΩ
CX in pF
*tw
POWER UP

NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset
input low enables the chip’s internal counters. After Reset goes low, the 2n/2 negative transition of the clock input causes
Decode Out to go high. Since the Mono–In input is being used, the output becomes monostable. The pulse width of the
output is dependent on the external timing components. The second and all subsequent pulses occur at 2n x (the clock
period) intervals where n = the number of stages selected from the truth table.

Figure 10. Time Interval Configuration Using an External Clock, Reset,

and Output Monostable to Achieve a Pulse Output
(Divide–by–4 Configured)

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 MC14536B

+V

RS
16
6 VDD
8-BYPASS
9 4
A OUT 1
10 B C
11 C
RTC
12
D
PULSE 2 5
RESET OUT 2
GEN. 14
SET
15
CLOCK INH
1
MONO-IN
7
CLOCK INH
3 DECODE OUT 13
IN1
VSS
8

RESET

OUT 1

OUT 2

fosc
1
2.3RtcC
DECODE OUT
Rs ≥ Rtc
F = Hz
tw R = Ohms
POWER UP
C = FARADS

NOTE: This circuit is designed to use the on–chip oscillation function. The oscillator frequency is deter-
mined by the external R and C components. When power is first applied to the device, Decode Out
initializes to a high state. Because this output is tied directly to the Osc–Inh input, the oscillator is
disabled. This puts the device in a low–current standby condition. The rising edge of the Reset pulse
will cause the output to go low. This in turn causes Osc–Inh to go low. However, while Reset is high,
the oscillator is still disabled (i.e.: standy condition). After Reset goes low, the output remains low
for 2n/2 of the oscillator’s period. After the part times out, the output again goes high.

Figure 11. Time Interval Configuration Using On–Chip RC Oscillator and

Reset Input to Initiate Time Interval
(Divide–by–2 Configured)

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 MC14536B

PACKAGE DIMENSIONS

PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08 NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE R Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C A 0.740 0.770 18.80 19.55
L
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0
10
0
10

0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

SOIC–16
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–03
ISSUE B
D A


16 9 NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
M

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.
B

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD

H

h X 45

PROTRUSION.
M

E
8X

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

0.25

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
1 8 CONDITION.

MILLIMETERS
16X B B DIM MIN MAX
A 2.35 2.65
0.25 M T A S B S A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60
e 1.27 BSC
A

H 10.05 10.55
h 0.25 0.75
L

SEATING
14X e PLANE L 0.50 0.90

0
7

A1

T C

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 MC14536B

PACKAGE DIMENSIONS

SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
16 9 LE MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
E HE M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
1 8 L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DETAIL P DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DAMBAR CANNOT BE LOCATED ON THE LOWER
D RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P
e A MILLIMETERS INCHES
c DIM MIN MAX MIN MAX
A --- 2.05 --- 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
A1 D 9.90 10.50 0.390 0.413
b E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0
10
0
10

Q1 0.70 0.90 0.028 0.035
Z --- 0.78 --- 0.031

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 MC14536B

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