Internal Architecture of 8086

Microprocessor
EE304- Microprocessors and
Microcontrollers
Architecture of 8086 Microprocessor

• It is a 16-bit Microprocessor
• It has 16-bit databus
– It can read data from or write data to memory and ports
either 16-bits or 8-bits at a time
• It has 20-bit Address bus
– It can address 220 memory locations i.e. 1MB
– Each location is of Byte wide
– 16-bit word will be stored in two consecutive memory
locations
– If the first byte of a word is at even address, 8086 can read
the entire word in one operation and if odd, in two
operations
Architecture of 8086 Microprocessor

• 8086 microprocessor contains 29000 transistors and

fabricated using HMOS technology (n-mos and p-mos
amalgumated)
• It is 40-pin IC
• It has 20-address pins, 16 of which used as data pins
– AD0-AD15
– A16-A19
• Multiplexing of addresses and data reduces the no. of
pins needed, but slow down the transfer of data.
• Because of the timing on the bus, the transfer rate is
not decreased as much.
Architecture of 8086 Microprocessor

• 16-control lines for providing Handshaking

signals during bus transfers and for permitting
at least some external control of the CPU.
• +5V supply voltage
• Clock frequency
– 5MHz (8086)
– 8 MHz (8086-version 2)
– 10 MHz (8086-version 1)
 Architecture of 8086 Microprocessor
Register organization of 8086 microprocessor

General Data Registers Pointer Registers

15 8 7 0 IP Instruction Pointer Register
AX AH AL BP Base Pointer Register
BX BH BL SP Stack Pointer Register
CX CH CL
DX DH DL
Index Registers
Segment Registers SI Source Index Register
CS Code Segment Register
DI Destination Index Register
DS Data Segment Register
SS Stack Segment Register Flag Register
ES Extra Segment Register 6-Conditional Flags 3-Control Flags
 Architecture of 8086 Microprocessor
Address/Data AD0-AD15 Address/Status
Memory Address and data bus Interface A16/S3-A17/S6

Internal Data Bus

CS
Bus DS Instruction Byte
Address Queue
Interface SS Conversion
Unit mechanism 1- Byte
ES
(adder) 2- Byte
IP
3- Byte
Internal Data Bus 4- Byte
5- Byte
15 0
AH AL
6-Byte
AX
BX BH BL
ALU (16)
CX CH CL
Decoding
DX DH DL circuit
Execution SP
Unit BP
Timing and
SI Flags (16)
Clock and Control Control circuit
DI
Signals
 Architecture of 8086 Microprocessor
Bus Interface Unit Execution Unit
Segment
Registers and Data Pointer
Instruction and Index Regs
Pointer (8 words)
(5words)

BHE/S7
16-bit
AD19/S6…. AD16/S3 Bus ALU
AD15-AD0 Interface
INTA, RD, WR Unit Flags

DT/R, DEN,ALE
6-Byte
Instruction Queue
TEST
Lock
INT
QS0-QS1 NMI
Control & Timing RQ/GT0
S2,S1,S0 HOLD
GND
CLK Reset Ready MN/MX VCC HLDA
Architecture of 8086 Microprocessor
15 0
AX AH AL
BX BH BL
CX CH CL
Nibble 4-bit
DX DH DL
Byte 8-bit
word 16-bit
AX 0001001000110100 Double 32-bit
AH AL 00010010 00110100 Word
AX 1234H
AH AL 12H 34H
Architecture of 8086 Microprocessor

Special functions of General Purpose Data Registers

AX Register

• It is used as 16-bit accumulator

• AL is used as 8-bit accumulator
• Default operand in MUL and DIV
operation
• Source and Destination for data during
I/O operations
Architecture of 8086 Microprocessor

Special functions of General Purpose Data Registers

BX Register

• It can be used as a Memory

Pointer to access data i.e. used as a
base register in address calculation

• MOV AX,[BX]
• MOV AX, [BX][SI]
Architecture of 8086 Microprocessor

Special functions of General Purpose Data Registers

CX Register

• It is used as Implied counter by certain

Instructions
• During rotate and shift operations it acts
as an operand for no of shifts or rotations

• ROR opr, CX
Architecture of 8086 Microprocessor

Special functions of General Purpose Data Registers

DX Register

• It is used to hold the I/O address during

certain I/O operations
• During MUL of 16 bit x 16bit, DX is used as
MSB in product
• During division operation 16bit/bbit, holds
remainder
Architecture of 8086 Microprocessor
Pointer Registers

Pointer Registers
IP Instruction Pointer Register
BP Base Pointer Register
SP Stack Pointer Register

• All are 16-bit registers

• IP & SP registers are essentially the program counter
• Base pointer register is a base register for accessing
the stack and may be used with other registers &/or
a displacement that is part of the instruction.
Architecture of 8086 Microprocessor
Index Registers
Index Registers
SI Source Index Register
DI Destination Index Register

• All are 16-bit registers

• They may be used by themselves
• Often used with BX or BP registers and/or a
displacement

• MOV AX,SI
• MOV AX,[SI]
• MOV AX,[BX][SI]
• MOV AX,1234[BX][SI]
Architecture of 8086 Microprocessor

To provide flexible base addressing and indexing, a data

address may be formed by adding together

Combination of [ BX or BP register contents, SI or DI

register contents and Displacement]

The result of such an address computation is called an

Effective address (EA)

Effective address (EA) = Displacement + Base register + Index register

• MOV AX,[BX][SI]
• MOV AX,1234[BX][SI]
Architecture of 8086 Microprocessor
The final data address (Physical address), however is
determined by the EA and appropriate shifted
contents of DS, ES or SS register.

Effective Address Segment Points to

(EA) Register (SR)
IP CS Code
SP SS Stack
BP SS Stack
SI DS Data
DI ES Data
BX DS Data
Architecture of 8086 Microprocessor
Segment Registers
Segment Registers
CS Code Segment Register
DS Data Segment Register
SS Stack Segment Register
ES Extra Segment Register

Segment registers in the BIU are used to hold

the upper 16-bits of the starting addresses of
four memory segments that the 8086 is
working with at a particular time.
Architecture of 8086 Microprocessor
Code Segment Register (CS)

Addressing a memory location in the code segment of

the memory, where executable program is stored.

CS register holds the upper 16-bits of the starting

address (points to the base or start of the current
code segment) of the segment from which the BIU is
currently fetching instruction code bytes
The IP register holds the upper 16-bits where in that
64kB code segment the next instruction byte is to be
fetched from (contains the offset from this base
address)
Architecture of 8086 Microprocessor
Data Segment Register (DS) ion
Points to the data segment of the memory where the data is
resided.
Extra Segment Register (ES)
It is another data segment of the memory which contains data.
Stack Segment Register (SS)
A stack is a section of memory set aside to store addresses and
data while a sub program is executing
SS reg- Holds upper 16-bits of starting address for stack segment
memory
SP reg- it holds the 16-bit offset from the start of the segment
memory where the data was recently stored on the stack
The Mem location where a word was most recently stored is Top
of Stack (TOS)
Architecture of 8086 Microprocessor

• A segment reg is used to hold the upper 16-

bits of the starting address for each of the
segment
• The BIU always inserts zeros for the lowest 4-
bits of the 20-bit starting address for a
segment.
• 64kB segment can be located anywhere within
the 1Mbyte address space
 Memory Segmentation
7FFFFH
64k Extra Segment Memory
70000H

Top of the Stack (TOS)

5FFFFH
64k Stack Segment Memory
50000H

CS=1000 3FFFFH
IP=01FFF 64k Data Segment Memory
EA ? 30000H
PA?
1FFFFH
64k Code Segment Memory
10000H
 Memory Segmentation

Code Segment
8086 Microprocessor
Memory
64kB
CS
SS Stack Segment
DS Memory
ES 64kB

Data Segment
Memory
64kB

ExtraSegment
Memory
64kB
 Memory Segmentation
Non
7FFFFH
Overlapping
Segments 64k Extra Segment Memory
70000H

Top of the Stack (TOS)

5FFFFH
64k Stack Segment Memory
50000H

3FFFFH
64k Data Segment Memory
30000H

1FFFFH
64k Code Segment Memory
10000H
 Memory Segmentation
Overlapping
Segments 7FFFFH
64k
70000H
61FFFH
Extra Segment 64k 5FFFFH
Memory
64k Stack Segment Memory
52000H
50000H

3FFFFH
64k
30000H
24FFFH
Data Segment 1FFFFH
Memory
64k
64k Code Segment Memory
15000H
10000H
Physical Memory Address Calculation
15 0
Segment Register 0000 OFFSET Value

ADDER

19 0
20-Bit
Physical Memory Address
Physical Memory Address Calculation

CS 1234 12340 Beginning Segment Address

IP 0022 0022 EA

Physical address of
PA 12362 Instruction
 Instruction Queuing

Fetching the next instruction while the current

instruction executes is called pipelining

8086 has an Instruction queue of 6 bytes

(enough to hold one or more opcodes)

While EU is decoding an instruction or executing an

instruction, it doe not require use of the buses
 Flag Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

U U U U OF DF IF TF SF ZF U AF U PF U CF

U-undefined • Conditional Flags

Flag is a flipflop that – Carry Flag (CF)
indicates some condition – Parity Flag (PF)
produced by the – Auxiliary Flag (AF)
execution of an – Zero Flag (ZF)
instruction or controls – Sign Flag (SF)
certain operations of the – Overflow Flag (OF)
EU
• Control Flags
 Trap Flag
 Interrupt Flag
 Direction Flag
 Flag Register-Conditional Flags

Carry Flag

• An addition causes this flag to be set if there is

a carry out of the MSB
• During subtraction, the carry flag functions as
borrow flag
CMP BX,CX
Condition CF ZF
CX >BX 1 0
CX<BX 0 0
CX=BX 0 1
 Flag Register-Conditional Flags

1+0 =1
Addition operation 0+1 =1
1+1 =10
1+1+1 =11

89H 1 0 0 0 1 0 0 1
95H 1 0 0 1 0 1 0 1
11EH 0 0 0 1 1 1 1 0
C
1
 Flag Register-Conditional Flags

Subtraction operation

06H 0 0 0 0 0 1 1 0
09H 0 0 0 0 1 0 0 1
-3 1 1 1 1 1 1 0 1
B 00000010
1 2’s Complement
1
00000011
 Flag Register-Conditional Flags
Parity Flag

Parity is a term used to indicate whether a

binary word has an even number of 1’s or an
odd number of 1’s.

8086 Parity flag will set to a 1 after an

instruction execution if the lower 8-bits of
destination operand has even number of 1s
 Flag Register-Conditional Flags
Auxiliary Carry Flag

• It has significance in BCD addition or

subtraction

• If a carry is produced/Borrow required when the

least significant nibbles of 2-bytes are
added/subtracted , AC will set to 1.

• AC flag is used only by DAA/DAS instruction

 Flag Register-Conditional Flags
1+0 =1
BCD Addition operation 0+1 =1
1+1 =10
1+1+1 =11
88 1 0 0 0 1 0 0 0
39 0 0 1 1 AC 1 0 0 1
127 1 1 0 0 0 0 0 1
AC 0 0 1
0 1 1 1 0
1
Correction Factor
C
1
0 0 1 0 0 1 1 1
Correction Factor: Add 6, when AC is set, C is set, 4-bits (Lower /Higher) >9
 Flag Register-Conditional Flags
BCD Subtraction operation

80 1 0 0 0 0 0 0 0
38 0 0 1 1 AC 1 0 0 0
42 0 1 0 0 1 0 0 0
AC 0 0 1
0 0 0 1 0
1
Correction Factor

0 1 0 0 0 0 1 0
Correction Factor: Subtract 6, when AC is set, C is set, 4-bits (Lower /Higher) >9
 Flag Register-Conditional Flags
Zero Flag

• This flag set to ‘1’ if the result of an arithmetic

or logic operation is zero

• The execution of CMP, DEC and INC

instructions, affects ZF.
 Flag Register-Conditional Flags

Sign Flag (+Ve & -Ve numbers)

• The MSB of the byte or word is used as a sign bit.

Remaining 7 bits of byte or remaining 15 bits of
word are used to represent magnitude of the
number

• 0- In the MSB bit indicates that the number is +Ve

• 1- In the MSB bit indicates that the number is -Ve
 Flag Register-Conditional Flags

Overflow Flag

• This flag will be set if the result of a signed

operation is too large to fit in the no of bits
available to represent it.
 Flag Register-Conditional Flags

Addition operation of 2-8-bit signed number

75H 0 1 1 1 0 1 0 1
37H
OF
0 0 1 1 0 1 1 1
ACH 1 0 1 0 1 1 0 0
 Flag Register-Control Flags
Direction Flag

• Used by string manipulation instructions. If

clear DF=0, the string is processed from its
beginning with the first ellement having the
lowest address
 Flag Register-Control Flags
Interrupt Flag

• IF =1 All the external Hardware interrupt are

enabled
• IF =0 All the external Hardware interrupt are
disabled
 Flag Register-Control Flags
Trap Flag

• TF =1 Execute one instruction at atime and

stops
• TF =0 Allows entire program execution