INTEL MICROPROCESSORS 8086/8088

SALIENT FEATURES: 8086 is the first 16-bit microprocessor from INTEL, released in the year 1978 It is a

!0 pin "I# chip based on N-channel, depletion load silicon $ate technolo$y%&'()* The term 16 bit means that its +L,,its internal re$isters and most of the instr-ctions are desi$ned to .or/ .ith 16 bit binary .ords 8086 is a0ailable at different cloc/ speeds 1i2, 3 ' &2%8086*48' &2%8086-5* and 10%8086-1* ' &2 8086 microprocessor has a 16-bit data b-s and 50-bit address b-s )o, it can address any one of 5 50 610!837661 me$a byte memory locations INTEL 8088 has the same +L, ,same re$isters and same instr-ction set as the 8086 7-t the only difference is 8088 has only 8-bit data b-s and 50-bit address b-s &ence the 8088 can only read8.rite8ports of only 8-bit data at a time The 8088 .as -sed as the 9#, in the ori$inal I7' personal comp-ters : I7'#98;T< The 8086 microprocessor can .or/ in t.o modes of operations They are 'inim-m mode and 'a=im-m mode In the minim-m mode of operation the microprocessor do not associate .ith any co-processors m-ltiprocessor processor or co-processor and can not be -sed for systems 7-t in the ma=im-m mode the 8086 can .or/ in m-lticonfi$-ration This minim-m or ma=im-m operations are

decided by the pin 'N8 ';%+cti0e lo.* >hen this pin is hi$h 8086 operates in minim-m mode other.ise it operates in 'a=imi-m mode Differences between 8086 n! 8088 Micr"#r"cess"rs : Tho-$h the architect-re and instr-ction set of both 8086 and 8088 processors are same, still .e find certain differences bet.een them They are %i* 8086 has 16-bit data b-s lines .hereas 8088 has 8-data lines %ii* 8086 is a0ailable in three cloc/ speds namely 3 ' &2,8' &2%8086-5* and 10 ' &2 %8086-1* .hereas 8088 is a0ailable is only a0ailable only in t.o speeds namely 3' &2 and 8' &2 %iii* The memory address space of 8086 is or$ani2ed as t.o 315/7 ban/s .hereas 8088 memory space is implemented as a sin$le 1'; 8 memory ban/ 1

%i0* 8086 has a 6-byte instr-ction ?-e-e .hereas 8088 has a ! byte instr-ction ?-e-e The reason for this is that 8088 can fetch only one byte at a time %0* In 8086 the memory control pin % '8 I(* si$nal is complement of the 8088 e?-i0alent si$nal%I(8'* %0i* The 8086 has 7&E%7an/ hi$h enable .hereas 8088 has ))( stat-s si$nal %0ii* The byte and .ord data operations of 8086 are different from 8088 %0iii* 8086 can read or .rite either 8-bit or 16-bit .ord at a time ,.hereas 8088 can read only 8-bit data at a time %i=* The I8( 0olta$e le0els for 8086 are , 1ol is meas-red at 5 3m+ and for 8088 it is meas-red at 5 0m+ %=* 8086 dra.s a ma=im-m s-pply c-rrent of @60 m+ and the 8088 dra.s a ma=im-m of @!0 m+ ARC$TECTURE OF 8086/8088 : To impro0e the performance by implementin$ the parallel processin$ concept the 9#, of the 8086 88088 is di0ided into t.o independent sections They are 7-s Interface ,nit %7I,* and E=ec-tion ,nit %EI* The 7I, sendso-t addresses ,fetches instr-ctions ,read data from ports and memory and .rites data to ports and memory i e the 7I, handles all transfers data and addresses on the b-ses re?-ired by the e=ec-tion ,nit >hereas the E=ec-tion ,nit decodes the instr-ctions and e=ec-tes the instr-ctions T%e E&ec'ti"n Unit : The E=ec-tion ,nit consists of a control system , a 16-bit +L,, 16-bit Ala$ re$ister and fo-r $eneral p-rpose re$isters%+;,7;,9;,";*, pointer re$isters %)#,7#* and Inde= re$isters%)I,"I* of each 16-bits The control circ-itry controls the internal operations The decoder in the e=ec-tion -nit decodes the instr-ctions fetched from the memory into a series of actions The +L, can add ,s-btract, perform operations li/e lo$ical +N",(B,;(B, increment, decrement, complement ,and shiftin$ the binary n-mbers ('s Interf ce Unit : The 7I, consists of a 6-byte lon$ instr-ction re$ister called C-e-e +nd fo-r stac/ se$ment re$isters %E),9),)),")* , one Instr-ction #ointer%I#* and an adder circ-it to calc-late the 50bit physical address of a location This b-s interface -nit .ill perform all the e=ternal b-s operations They are fetchin$ the instr-ctions from the

memory, read8.rite data from8into memory or port and also s-pportin$ the instr-ction C-e-e etc The 7I, fetches -p to si= instr-ction bytes from the memory and stores these pre-fetched bytes in a first Din first o-t re$ister set called C-e-e >hen the e=ec-tion -nit is ready for the e=ec-tion of the instr-ction ,instead of fetchin$ the byte from the memory ,it reads the byte from the C-e-e called pipelinin$ or parallel processin$ This .ill increase the o0erall speed of microprocessor Aetchin$ the ne=t instr-ction .hile the c-rrent instr-ction e=ec-tes is

Fi)*+*Arc%itect're "f 8086 Micr"#r"cess"r RE,ISTER OR,ANISATION : The 1! re$isters of 8086 microprocessor are cate$ori2ed into fo-r $ro-ps They are $eneral p-rpose data re$isters , #ointer E Inde= re$isters , )e$ment re$isters and Ala$ re$ister as sho.n in the table belo.

S*N" 1 5 @

T.#e General p-rpose Be$isters%!* #ointer Be$isters Inde= Be$isters

Re)ister wi!t% 16-bit 8-bit 16-bit 16-bit

N /e "f t%e Re)isters +;,7;,9;,"; +L,+&,7L,7&,9L,9&,"L,"& )tac/ #ointer%)#* 7ase #ointer%7#* )o-rce Inde=%)I* "estination Inde=%"I* 9ode )e$ment%9)* "ata )e$ment%")* )tac/ )e$ment%))* E=tra )e$ment%E)* Instr-ction #ointer %I#* Ala$ Be$ister

)e$ment Be$isters

16-bit 16-bit 16-bit

3 6

Instr-ction Ala$ %#)>*

8086 Micr"#r"cess"r Re)isters ,ener - #'r#"se re)istersF There are fo-r 16-bit ! $eneral p-rpose re$isters namely

%+&, +L*4%7&,7L*4 %9&,9L*4 %and "&,"L* .hich are part of E=ec-tion -nit These re$isters can be -sed indi0id-ally for storin$ 16-bit data temporarily The +L re$ister is also called the acc-m-lator The pairs of re$isters can be -sed to$ether to store 16-bit data .ords It is al.ays ad0anta$eo-s to store the data in these re$isters beca-se the data can be accessed m-ch more easily as these re$isters are already in the e=ec-tion -nit &ere L indicates the lo.er byte and & indicates the hi$her byte ; indicates the e=tended re$ister The $eneral p-rpose data re$isters are -sed for data manip-lations The -se of these re$isters is more dependent on the mode of addressin$ also The other fo-r re$isters of E, are referred to as inde= 8 pointer re$isters They are

)tac/ #ointer re$ister , 7ase #ointer re$ister, )o-rce Inde= re$ister and "estination Inde= re$isters The pointer re$isters contain the offset .ithin a partic-lar se$ment

Fi) 0* Re)ister Or) nis ti"n The 7# E )# re$isters holds the offsets .ithin the data and stac/ se$ments respecti0ely The Inde= re$isters are -sed as $eneral p-rpose re$isters as .ell as for holdin$ the offset in case of inde=ed based and relati0e inde=ed addressin$ modes The so-rce Inde= re$ister is $enerally -sed to store the offset of so-rce data in data se$ment .hile the "estination Inde= re$ister -sed to store the offset of destination in data or e=tra se$ment These inde= re$isters are specifically -sed in strin$ manip-lations Se)/ent Re)isters :There are fo-r 16-bit se$ment re$isters namely code se$ment re$ister%9)*,)tac/ se$ment re$ister%))*,"ata se$ment re$ister%")* and E=tra se$ment re$ister%E)* The code se$ment re$ister is -sed for addressin$ the 6!/7 memory location in the code se$ment of the memory ,.here the code of the e=ec-table pro$ram is stored )imilarly the ") re$ister points to the data se$ment of the 6!/7 memory .here the data

is stored The E=tra se$ment re$ister also refers to essentially another data se$ment of the memory space The )) re$ister is -sef-l for addressin$ stac/ se$ment of memory )o, the 9),"),)) and E) se$ment re$isters respecti0ely contains the se$ment addresses for the code, data, stac/ and e=tra se$ments of the memory Instr'cti"n P"inter Re)ister: It is a 16-bit re$ister .hich al.ays points to the ne=t instr-ction to be e=ec-ted .ithin the c-rrently e=ec-tin$ code se$ment )o, this re$ister contains the 16-bit offset address pointin$ to the ne=t instr-ction code .ithin the 6!/7 of the code se$ment area Its content is a-tomatically incremented as the e=ec-tion of the ne=t instr-ction ta/es place F- ) Re)isterF This re$ister is also called stat-s re$ister It is a 16 bit re$ister .hich contains si= stat-s fla$s and three control fla$s )o, only nine bits of the 16 bit re$ister are defined and the remainin$ se0en bits are -ndefined Normally this stat-s fla$ bits indicate the stat-s of the +L, after the arithmetic or lo$ical operations Each bit of the stat-s re$ister is a flip8flop The Ala$ re$ister contains 9arry fla$, #arity fla$, +-=iliary fla$ Hero fla$, )i$n fla$ ,Trap fla$, Interr-pt fla$, "irection fla$ and o0erflo. fla$ as sho.n in the dia$ram The 9A,#A,+A,HA,)A,(A are the stat-s fla$s and the TA,IA and 9A are the control fla$s ; ; ; ; OF DF IF TF SF 1F 2 AF 2 PF 2 CF

F- ) Re)ister CF3 9arry Ala$F This fla$ is set, .hen there is a carry o-t of ')7 in case of addition or a borro. in case of s-btraction PF 3 #arity Ala$ F This fla$ is set to 1, if the lo.er byte of the res-lt contains e0en n-mber of 1Is else %for odd n-mber of 1s * set to 2ero AF3 +-=ilary 9arry Ala$F This is set, if there is a carry from the lo.est nibble, i e, bit three d-rin$ addition, or borro. for the lo.est nibble, i e, bit three, d-rin$ s-btraction

1F3 Hero Ala$F This fla$ is set, if the res-lt of the comp-tation or comparison performed by the pre0io-s instr-ction is 2ero SF3 )i$n Ala$ F This fla$ is set, .hen the res-lt of any comp-tation is ne$ati0e TF 3 Tarp Ala$F If this fla$ is set, the processor enters the sin$le step e=ec-tion mode IF3 Interr-pt Ala$F If this fla$ is set, the mas/able interr-pt INTB of 8086 is enabled and if it is 2ero ,the interr-pt is disabled It can be set by -sin$ the )TI instr-ction and can be cleared by e=ec-tin$ 9LI instr-ction DF3 "irection Ala$F This is -sed by strin$ manip-lation instr-ctions If this fla$ bit is J0I, the strin$ is processed be$innin$ from the lo.est address to the hi$hest address, i e , a-to incrementin$ mode (ther.ise, the strin$ is processed from the hi$hest address to.ards the lo.est address, i e , a-to incrementin$ mode OF3 (0er flo. Ala$F This fla$ is set, if an o0erflo. occ-rs, i e, if the res-lt of a si$ned operation is lar$e eno-$h to accommodate in a destination re$ister The res-lt is of more than 7-bits in si2e in case of 8-bit si$ned operation and more than 13-bits in si2e in case of 16-bit si$n operations, then the o0erflo. .ill be set 8086 PIN DIA,RAM 4 PIN DESCRIPTION Intel 8086 is a 16-bit &'() microprocessor It is a0ailable in !0 pin "I# chip It -ses a 31 d c s-pply for its operation The 8086 -ses 50-line address b-s It -ses a 16-line data b-s The 50 lines of the address b-s operate in m-ltiple=ed mode The 16-lo. order address b-s lines are m-ltiple=ed .ith data and ! hi$h-order address b-s lines are m-ltiple=ed .ith stat-s si$nals The pin dia$ram of Intel 8086 is sho.n in Ai$ ! AD03AD56 7(i!irecti"n -8 : +ddress8"ata b-s These are lo. order address b-s They are m-ltiple=ed .ith data >hen +" lines are -sed to transmit memory address the

symbol + is -sed instead of +", for e=ample +0-+13 >hen data are transmitted o0er +" lines the symbol " is -sed in place of +", for e=ample "0-"7, "8-"13 or "0-"13 A563A59 7O't#'t8 : &i$h order address b-s These are m-ltiple=ed .ith stat-s si$nals

Fi)*:* Pin Di )r / "f 8086 Pr"cess"r A56/S0; A5</S:; A58/S6; A59/S6 : The specified address lines are m-ltiple=ed .ith correspondin$ stat-s si$nals ($E %+cti0e Lo.*8)7 %(-tp-t* : 7-s &i$h Enable8)tat-s "-rin$ T1 it is lo. It is -sed to enable data onto the most si$nificant half of data b-s, "8-"13 8-bit de0ice connected to -pper half of the data b-s -se 7&E %+cti0e Lo.* si$nal It is m-ltiple=ed .ith stat-s si$nal )7 )7 si$nal is a0ailable d-rin$ T5, T@ and T!

RD 7Re !8 %+cti0e Lo.* : The si$nal is -sed for read operation It is an o-tp-t si$nal It is acti0e .hen lo. READ= : This is the ac/no.led$ement from the slo. de0ice or memory that they ha0e completed the data transfer The si$nal made a0ailable by the de0ices is synchroni2ed by the 858!+ cloc/ $enerator to pro0ide ready inp-t to the 8086 the si$nal is acti0e hi$h INTR3Interr'#t Re>'est : This is a tri$$ered inp-t This is sampled d-rin$ the last cloc/ cycles of each instr-ction to determine the a0ailability of the re?-est If any interr-pt re?-est is pendin$, the processor enters the interr-pt ac/no.led$e cycle This can be internally mas/ed by res-ltin$ the interr-pt enable fla$ This si$nal is acti0e hi$h and internally synchroni2ed NMI 7In#'t8 DN(N-'+)K+7LE INTEBB,#T F It is an ed$e tri$$ered inp-t .hich ca-ses a type 5 interr-pt + s-bro-tine is 0ectored to 0ia an interr-pt 0ector loo/-p table located in system memory N'I is not mas/able internally by soft.are + transition from L(> to &IG& initiates the interr-pt at the end of the c-rrent instr-ction This inp-t is internally synchroni2ed INTA: INT+F Interr-pt ac/no.led$e It is acti0e L(> d-rin$ T 5 ,T @ and T . of each interr-pt ac/no.led$e cycle MN/ M2 'INI',' 8 '+;I',' FThis pin si$nal indicates .hat mode the processor is to operate in R?/,T R?/,T0 : BEC,E)T8GB+NTF These pins are -sed by other local b-s masters to force the processor to release the local b-s at the end of the processorLs c-rrent b-s cycle Each pin is bidirectional .ith BC8GT ha0in$ hi$her priority than BC 8GT1 LOC@: Its an acti0e lo. pin It indicates that other system b-s masters are not to allo.ed to $ain control of the system b-s .hile L(9K is acti0e L(> The L(9K si$nal remains acti0e -ntil the completion of the ne=t instr-ction TEST : This inp-t is e=amined by a J>+ITI instr-ction If the TE)T pin $oes lo., e=ec-tion .ill contin-e, else the processor remains in an idle state The inp-t is synchroni2ed internally d-rin$ each cloc/ cycle on leadin$ ed$e of cloc/

CL@3 C-"cA In#'t : The cloc/ inp-t pro0ides the basic timin$ for processor operation and b-s control acti0ity Its an asymmetric s?-are .a0e .ith @@M d-ty cycle RESET 7In#'t8 : BE)ETF ca-ses the processor to immediately terminate its present acti0ity The si$nal m-st be acti0e &IG& for at least fo-r cloc/ cycles Bcc D #o.er )-pply % N31 " 9 * ,ND D Gro-nd ?S5;?S0 %C-e-e )tat-s* These si$nals indicate the stat-s of the internal 8086 instr-ction ?-e-e accordin$ to the table sho.n belo. C)I 0 %L(>* 0 1 %&IG&* 1 C)0 0 1 0 1 )-bse?-ent 7yte from C-e-e No (peration Airst 7yte of (p 9ode from C-e-e Empty the C-e-e )tat-s

DT/R : "+T+ TB+N)'IT8BE9EI1EF This pin is needed in minim-m system that desires to -se an 858688587 data b-s transcei0er It is -sed to control the direction of data flo. thro-$h the transcei0er DEN: "+T+ EN+7LE This pin is pro0ided as an o-tp-t enable for the 858688587 in a minim-m system .hich -ses the transcei0er "EN is acti0e L(> d-rin$ each memory and I8( access and for INT+ cycles $OLD/$OLDA : &(L" indicates that another master is re?-estin$ a local b-s This is an acti0e &IG& The processor recei0in$ the OOholdLL re?-est .ill iss-e &L"+ %&IG&* as an ac/no.led$ement in the middle of a T ! or T 1 cloc/ cycle

MEMOR= OR,ANI1ATION : 10

The 8086 processor pro0ides a 50-bit address toaccess any location of the 1 '7 memory space The memory is or$ani2ed as a linear array of 1 million bytes, addressed as 00000%&* to AAAAA%&* The memory is lo$ically di0ided into code, data, e=tra data, and stac/ se$ments of -p to 6!K bytes each #hysically, the memory is or$ani2ed as a hi$h ban/ %"13 - "8* and a lo. ban/ %"7 D"0* of 315 K 8-bitbytes addressed in parallel by the processorLs address lines +19 -+1 7yte data .ith e0en addresses is transferred on the "7 D "0 b-s lines .hile odd addressed byte data %+0 &IG&* is transferred on the "13"8 b-s lines The processor pro0ides t.o enable si$nals, 7&E and +0 , to selecti0ely allo. readin$ from or .ritin$ into either an odd byte location, e0en byte location, or both The instr-ction stream is fetched from memory as .ords and is addressed internally by the processor to the byte le0el as necessary INTERRUPTS : +n interr-pt to the microprocessor is defined as that .hich dist-rbs the normal e=ec-tion of a pro$ram 7roadly the interr-pts are di0ided into t.o types They are e=ternal The hard.are interr-pts are hard.are Interr-pts and internal %)oft.are* Interr-pts

classified as non-mas/able and mas/able interr-pts The hard.are interr-pt is ca-sed by any peripheral de0ice by sendin$ a si$nal thro-$h a specified pin to the microprocessor >hereas internal interr-pts are initiated by the state of the 9#, %e $ di0ide by 2ero error* or by an instr-ction )o, the soft.are interr-pt is one .hich interr-pts the normal e=ec-tion of a pro$ram of the microprocessor The 8086 has t.o hard.are interr-pt pins namely N'I and INTB In the t.o ,the N'I is a non-mas/able interr-pt and the INTB interr-pt re?-est is a mas/able interr-pt .hich has lo.er proirity The third pin associated .ith the hard.are interr-pts are the INT+ called interr-pt ac/no.led$e NMI F The processor pro0ides a sin$le non-mas/able interr-pt pin %N'I* .hich has hi$her priority than the mas/able interr-pt re?-est pin %INTB* + typical -se .o-ld be to acti0ate a po.er fail-re ro-tine The N'I is ed$e-tri$$ered on a L(>-to-&IG& transition The acti0ation of this pin ca-ses a type 5 interr-pt

11

INTRF The 8086 pro0ides a sin$le interr-pt re?-est inp-t %INTB* .hich can be mas/ed internally by soft.are .ith the resettin$ of the interr-pt enable AL+G stat-s bit The interr-pt re?-est si$nal is le0el tri$$ered It is internally synchroni2ed d-rin$ each cloc/ cycle on the hi$h-$oin$ ed$e of 9LK To be responded to, INTB m-st be present %&IG&* d-rin$ the cloc/ period precedin$ the end of the c-rrent instr-ction or the end of a .hole mo0e for a bloc/ type instr-ction S"ftw re Interr'#tsF 9omin$ to the soft.are interr-pts , 8086 can $enerate 536 interr-pt types thro-$h the instr-ction INT n +ny of the 536 interr-pt types can be $enerated by specifyin$ the interr-pt type after INT instr-ction Aor e=ample INT @@ .ill ca-se type @@ interr-pt I / 7ytes of memory from 00000& to 00@AA & is set aside to store the startin$ address of the Interr-pt ser0ice s-b-ro-tine%I))* pro$rams in an 8086 based systems To store the startin$ address of the each I)) , fo-r bytes of memory space is re?-ired T.o bytes are for storin$ 9) 0al-e and t.o bytes for I# 0al-e The startin$ address of an I)) stored in 1/7 of memory space is called Interr-pt pointer or Interr-pt 0ector The 1/7 memory Table%I1T* space acts as a table and it is called Interr-pt 1ector

15

The 536 interr-pt pointers ha0e been n-mbered from 0 to 533 The n-mber $i0en to an interr-pt pointer denotes the type of the interr-pt Aor e=ample Type0,Type1,Type5 etcPThe startin$ address of the I)) for type0 interr-pt is 000000& Aor type1 interr-pt is 0000!& similarly for type5 is 00008& PPIn the I1T the first fi0e pointers are dedicated interr-pt pointers They are F TQ#E 0 Interr-pt corresponds to di0ide by 2ero sit-ation TQ#E 1 Interr-pt corresponds to )in$le step e=ec-tion d-rin$ the deb-$$in$ of a pro$ram TQ#E 5 Interr-pts to non-mas/able N'I interr-pt TQ#E @ FInterr-pt corresponds to brea/ point interr-pt TQ#E ! Interr-pt corresponds to (0erflo. interr-pt The Interr-pts from Type 3 to Type @1 are reser0ed for other ad0anced microprocessors,and from @5 to Type 533 are a0ailable for hard.are and soft.are interr-pts Differences between CALL n! INT : In fact both the instr-ctions 9+LL and INT n .ill interr-pt the e=ec-tion of the main pro$ram 7-t there are certain differences bet.een their f-nctionin$ They are $i0en belo. in the table S*N" 1 CALL Instr'cti"n ,pon the e=ec-tion ,the control .ill R-mp to any one of the 1 '7 of memory locations The -ser can insert in the se?-ence of instr-ctions of a pro$ram (nce initiated it cannot be mas/ed >hen initiated ,it stores the 9)FI# of the ne=t instr-ction on the stac/ INTn instr'cti"n ,pon e=ec-tion the control .ill R-mp to a fi=ed location in the 0ector table 9an occ-r at any acti0ated by hard.are 9an be mas/ed >hen initiated ,it stores the 9)FI# of the ne=t instr-ction and also the fla$ re$ister on the stac/ time

5 @ !

The last instr-ction of the The last instr-ction of the s-bro-tine .ill be BET I)) .ill be IBET

1@

ADDRESSIN, MODES : The different .ays in .hich a so-rce operand is denoted in an instr-ction are /no.n as the addressin$ modes There are 8 different addressin$ modes in 8086 pro$rammin$ They are 1 Immediate addressin$ mode 5 Be$ister addressin$ mode @ "irect addressin$ mode ! Be$ister indirect addressin$ mode 3 7ased addressin$ mode 6 Inde=ed addressin$ mode 7 7ased inde=ed addressin$ mode 8 7ased, Inde=ed .ith displacement I//e!i te !!ressin) /"!eF The addressin$ mode in .hich the data operand is a part of the instr-ction itself is called Immediate addressin$ mode

Aor E=F '(1 9;, !8!7 & +"" +;, 5!36 & '(1 +L, AA&

Re)ister !!ressin) /"!e : Be$ister addressin$ mode means, a re$ister is the so-rce of an operand for an instr-ction

Aor E= F '(1 +;, 7; copies the contents of the 16-bit 7; re$ister into the 16-bit +; re$ister E; F +"" 9;,";

1!

Direct !!ressin) /"!e: The addressin$ mode in .hich the effecti0e address of the memory location at .hich the data operand is stored is $i0en in the instr-ction i e the effecti0e address is R-st a 16-bit n-mber is .ritten directly in the instr-ction

Aor

E=F '(1 7;, :1@3!&< '(1 7L,:0!00&<

The s?-are brac/ets aro-nd the 1@3! & denotes the contents of the memory location >hen e=ec-ted, this instr-ction .ill copy the contents of the memory location into 7; re$ister This addressin$ mode is called direct beca-se the displacement of the operand from the se$ment base is specified directly in the instr-ction

Re)ister in!irect

!!ressin) /"!eF Be$ister indirect addressin$ allo.s data to be

addressed at any memory location thro-$h an offset address held in any of the follo.in$ re$istersF 7#, 7;, "I and )I

E=F '(1 +;, :7;< )-ppose the re$ister 7; contains !673& ,the contents of the !673 & are mo0ed to +; +"" 9;,S7;T

( se! !!ressin) /"!eF The offset address of the operand is $i0en by the s-m of contents of the 7; or 7# re$isters and an 8-bit or 16-bit displacement E=F '(1 ";, :7;N0!< +"" 9L,:7;N08<

13

In!e&e! A!!ressin)

/"!eF

The operands offset address is fo-nd by addin$ the

contents of )I or "I re$ister and 8-bit or 16-bit displacements E=F '(1 7;,:)IN06< +"" +L,:"IN08<

( se! 3in!e& !!ressin) /"!e: The offset address of the operand is comp-ted by s-mmin$ the base re$ister to the contents of an Inde= re$ister

E=F +"" 9;,:7;N)I<

'(1 +;,:7;N"I<

( se! Iin!e&! wit% !is#- ce/ent /"!e: The operands offset is comp-ted by addin$ the base re$ister contents, an Inde= re$isters contents and 8 or 16-bit displacement* E= F '(1 +;,:7;N"IN08< +"" 9;,:7;N)IN16< INSTRUCTION SET OF 8086/8088 The 8086 microprocessor s-pports 6 types of Instr-ctions They are 1 "ata transfer instr-ctions 5 +rithmetic instr-ctions @ 7it manip-lation instr-ctions ! )trin$ instr-ctions 3 #ro$ram E=ec-tion Transfer instr-ctions %7ranch E loop Instr-ctions* 6 #rocessor control instr-ctions 16

5* D t Tr nsfer instr'cti"ns :These instr-ctions are -sed to transfer the data from so-rce operand to destination operand +ll the store, mo0e, load, e=chan$e ,inp-t and o-tp-t instr-ctions belon$ to to this $ro-p ,ener - #'r#"se b.te "r w"r! tr nsfer instr'cti"nsF '(1 : 9opy byte or .ord from specified so-rce to specified destination #,)& : #-sh the specified .ord to top of the stac/ #(# : #op the .ord from top of the stac/ to the specified location #,)&+ : #-sh all re$isters to the stac/ #(#+ : #op the .ords from stac/ to all re$isters ;9&G : E=chan$e the contents of the specified so-rce and destination operands one of .hich may be a re$ister or memory location ;L+T F Translate a byte in +L -sin$ a table in memory Si/#-e in#'t n! "'t#'t #"rt tr nsfer instr'cti"ns 1 5 IN F Beads a byte or .ord from specified port to the acc-m-lator (,T F )ends o-t a byte or .ord from acc-m-lator to a specified port

S#eci - !!ress tr nsfer instr'cti"ns 1 LE+ F Load effecti0e address of operand into specified re$ister 5 @ L") F Load ") re$ister and other specified re$ister from memory LE) F Load E) re$ister and other specified re$ister from memory

F- ) tr nsfer re)isters 1 5 @ ! L+&A F Load +& .ith the lo. byte of the fla$ re$ister )+&A F )tore +& re$ister to lo. byte of fla$ re$ister #,)&A F 9opy fla$ re$ister to top of the stac/ #(#A F 9opy .ord at top of the stac/ to fla$ re$ister

+* Arit%/etic instr'cti"ns : These instr-ctions are -sed to perform 0ario-s mathematical operations li/e addition, s-btraction, m-ltiplication and di0ision etcP A!!iti"n instr'cti"ns 1 +"" : +dd specified byte to byte or .ord to .ord 5 +"9 : +dd .ith carry @ IN9 : Increment specified byte or specified .ord by 1 ! +++ : +)9II adR-st after addition 3 "++ : "ecimal %79"* adR-st after addition 17

S'btr cti"n instr'cti"ns 1 ),7 F )-btract byte from byte or .ord from .ord 5 @ ! 3 6 7 )77 F )-btract .ith borro. "E9 F "ecrement specified byte or .ord by 1 NEG F Ne$ate or in0ert each bit of a specified byte or .ord and add 1%5Is complement* 9'# ++) "+) F 9ompare t.o specified byte or t.o specified .ords F +)9II adR-st after s-btraction F "ecimal adR-st after s-btraction

M'-ti#-ic ti"n instr'cti"ns 1 ',L : '-ltiply -nsi$ned byte by byte or -nsi$ned .ord or .ord 5 @ I',L : '-ltiply si$ned bye by byte or si$ned .ord by .ord ++' : +)9II adR-st after m-ltiplication

DiCisi"n instr'cti"ns 1 "I1 F "i0ide -nsi$ned .ord by byte or -nsi$ned do-ble .ord by .ord 5 @ ! 3 I"I1 F "i0ide si$ned .ord by byte or si$ned do-ble .ord by .ord ++" F +)9II adR-st after di0ision 97> F Aill -pper byte of .ord .ith copies of si$n bit of lo.er byte 9>" F Aill -pper .ord of do-ble .ord .ith si$n bit of lo.er .ord

0* (it M ni#'- ti"n instr'cti"ns : These instr-ctions incl-de lo$ical , shift and rotate instr-ctions in .hich a bit of the data is in0ol0ed L")ic - instr'cti"ns 1 N(T FIn0ert each bit of a byte or .ord 5 @ +N" F +N"in$ each bit in a byte or .ord .ith the correspondin$ bit in another byte or .ord (B F (Bin$ each bit in a byte or .ord .ith the correspondin$ bit in another

byte or .ord @ ! ;(B F E=cl-si0e (B each bit in a byte or .ord .ith the correspondin$ bit in another byte or .ord TE)T F+N" operands to -pdate fla$s, b-t donIt chan$e operands

S%ift instr'cti"ns

18

1 5 @

)&L8)+L F )hift bits of a .ord or byte left, p-t 2ero%)* in L)7s )&B )+B F )hift bits of a .ord or byte ri$ht, p-t 2ero%)* in ')7s F )hift bits of a .ord or byte ri$ht, copy old ')7 into ne. ')7

R"t te instr'cti"ns 1 B(L F Botate bits of byte or .ord left, ')7 to L)7 and to 9arry Ala$ :9A< 5 @ ! B(B B9B B9L F Botate bits of byte or .ord ri$ht, L)7 to ')7 and to 9arry Ala$ :9A< FBotate bits of byte or .ord ri$ht, L)7 T( 9A and 9A to ')7 FBotate bits of byte or .ord left, ')7 T( 9A and 9A to L)7

:* Strin) instr'cti"ns + strin$ is a series of bytes or a series of .ords in se?-ential memory locations + strin$ often consists of +)9II character codes 1 BE# F +n instr-ction prefi= Bepeat follo.in$ instr-ction -ntil 9;60 5 @ ! 3 6 7 8 9 BE#E8BE#H F Bepeat follo.in$ instr-ction -ntil 9;60 or 2ero fla$ HA61 BE#NE8BE#NH F Bepeat follo.in$ instr-ction -ntil 9;60 or 2ero fla$ HA61 '(1)8'(1)78'(1)>F 'o0e byte or .ord from one strin$ to another 9(')89('#)789('#)>F 9ompare t.o strin$ bytes or t.o strin$ .ords IN)8IN)78IN)>F Inp-t strin$ byte or .ord from port (,T)8(,T)78(,T)> F (-tp-t strin$ byte or .ord to port )9+)8)9+)78)9+)>F )can a strin$ 9ompare a strin$ byte .ith a byte in +L or a strin$ .ord .ith a .ord in +; L(")8L(")78L(")>F Load strin$ byte in to +L or strin$ .ord into +;

6*Pr")r / E&ec'ti"n Tr nsfer instr'cti"ns These instr-ctions are similar to branchin$ or loopin$ instr-ctions These instr-ctions incl-de conditional E -nconditional R-mp or loop instr-ctions Unc"n!iti"n - tr nsfer instr'cti"ns 1 9+LL F 9all a proced-re, sa0e ret-rn address on stac/ 5 @ BET U'# F Bet-rn from proced-re to the main pro$ram F Goto specified address to $et ne=t instr-ction

C"n!iti"n - tr nsfer instr'cti"ns 1 U+8UN7E F U-mp if abo0e 8 R-mp if not belo. or e?-al

19

5 @ ! 3 6 7 8 9

U+E8UN7 F U-mp if abo0e 8R-mp if not belo. U7E8UN+ F U-mp if belo. or e?-al8 U-mp if not abo0e U9 UE8UH F R-mp if carry fla$ 9A61 F R-mp if e?-al8R-mp if 2ero fla$ HA61

UG8UNLE F U-mp if $reater8 R-mp if not less than or e?-al UGE8UNL F R-mp if $reater than or e?-al8 R-mp if not less than UL8UNGE F R-mp if less than8 R-mp if not $reater than or e?-al ULE8UNG F R-mp if less than or e?-al8 R-mp if not $reater than F R-mp if no carry %9A60*

10 UN9

11 UNE8UNH F R-mp if not e?-al8 R-mp if not 2ero%HA60* 15 UN( 1@ UN#8U#( 1! UN) 13 U( 16 U#8U#E 17 U) F R-mp if no o0erflo.%(A60* F R-mp if not parity8 R-mp if parity odd%#A60* F R-mp if not si$n%)A60* F R-mp if o0erflo. fla$%(A61* F R-mp if parity8R-mp if parity e0en%#A61* F R-mp if si$n%)A61*

6*Iter ti"n c"ntr"- instr'cti"ns These instr-ctions are -sed to e=ec-te a series of instr-ctions for certain n-mber of times 1 L((# FLoop thro-$h a se?-ence of instr-ctions -ntil 9;60 5 @ ! L((#E8L((#H F Loop thro-$h a se?-ence of instr-ctions .hile HA61 and 9; 6 0 L((#NE8L((#NH F Loop thro-$h a se?-ence of instr-ctions .hile HA60 and 9; 60 U9;H F R-mp to specified address if 9;60

<* Interr'#t instr'cti"ns 1 INT F Interr-pt pro$ram e=ec-tion, call ser0ice proced-re 5 @ INT( F Interr-pt pro$ram e=ec-tion if (A61 IBET F Bet-rn from interr-pt ser0ice proced-re to main pro$ram 50

8*$i)% -eCe- - n)' )e interf ce instr'cti"ns 1 ENTEB F enter proced-re 5 @ LE+1E FLea0e proced-re 7(,N" F 9hec/ if effecti0e address .ithin specified array bo-nds

9*Pr"cess"r c"ntr"- instr'cti"ns Ala$ set8clear instr-ctions 1 )T9 F )et carry fla$ 9A to 1 5 @ ! 3 6 7 9L9 F 9lear carry fla$ 9A to 0 9'9 F 9omplement the state of the carry fla$ 9A )T" 9L" )TI 9LI F )et direction fla$ "A to 1 %decrement strin$ pointers* F 9lear direction fla$ "A to 0 F )et interr-pt enable fla$ to 1%enable INTB inp-t* F 9lear interr-pt enable Ala$ to 0 %disable INTB inp-t*

50* E&tern - $ r!w re s.nc%r"niD ti"n instr'cti"ns 1 &LT F &alt %do nothin$* -ntil interr-pt or reset 5 @ >+IT F >ait %"o nothin$* -ntil si$nal on the test pin is lo. E)9 F Escape to e=ternal coprocessor s-ch as 8087 or 8089

4. LOCK : An instruction prefix. Prevents another processor from taking the bus while the a !acent instruction executes. 11. No operation instruction

N(#

F No action e=cept fetch and decode

ASSEM(LER DIRECTIBES : +ssembler directi0es are the directions to the assembler .hich indicate ho. an operand or section of the pro$ram is to be processed These are also called pse-do operations .hich are not e=ec-table by the microprocessor The 0ario-s directi0es are e=plained belo. 5* ASSUME F The +)),'E directi0e is -sed to inform the assembler the name of the lo$ical se$ment it sho-ld -se for a specified se$ment E=F +)),'E ")F "+T+ tells the assembler that for any pro$ram instr-ction .hich refers to the data se$ment ,it sho-ld -se the lo$ical se$ment called "+T+

51

+*D( 3"efine byte It is -sed to declare a byte 0ariable or set aside one or more stora$e locations of type byte in memory Aor e=ample, 9,BBENTV1+L,E "7 @6& tells the assembler to reser0e 1 byte of memory for a 0ariable named 9,BBENTV 1+L,E and to p-t the 0al-e @6 & in that memory location .hen the pro$ram is loaded into B+' 0* DE 3Define w"r!* It tells the assembler to define a 0ariable of type .ord or to reser0e stora$e locations of type .ord in memory : DD7!efine !"'b-e w"r!* FThis directi0e is -sed to declare a 0ariable of type do-ble .ord or restore memory locations .hich can be accessed as type do-ble .ord 6*D? 7!efine >' !w"r!8 :This directi0e is -sed to tell the assembler to declare a 0ariable ! .ords in len$th or to reser0e ! .ords of stora$e in memory 6*DT 7!efine ten b.tes8:It is -sed to inform the assembler to define a 0ariable .hich is 50 bytes in len$th or to reser0e 10 bytes of stora$e in memory <* E?U 4E>' te It is -sed to $i0e a name to some 0al-e or symbol* E0ery time the assembler finds the $i0en name in the pro$ram, it .ill replace the name .ith the 0al-e or symbol .e ha0e e?-ated .ith that name 8*OR, -Ori)in te F The (BG statement chan$es the startin$ offset address of the data It allo.s to set the location co-nter to a desired 0al-e at any point in the pro$ram Aor e=ample the statement (BG @000& tells the assembler to set the location co-nter to @000& 9 *PROC- #roced-reF It is -sed to identify the start of a proced-re (r s-bro-tine 50* END- End pro$ram This directi0e indicates the assembler that this is the end of the pro$ram mod-le The assembler i$nores any statements after an EN" directi0e 55 ENDP- End proced-reF It indicates the end of the proced-re %s-bro-tine* to the assembler 5+*ENDS-End )e$mentF This directi0e is -sed .ith the name of the se$ment to indicate the end of that lo$ical se$ment E=F 9("E )EG'ENT F )tart of lo$ical se$ment containin$ code 9("E EN") F End of the se$ment named 9("E

ASSEM(L= LAN,UA,E DEBELOPMENT TOOLS:

55

To de0elop an assembly lan$-a$e pro$ram .e need certain e=plained belo.

pro$ram

de0elopment tools The 0ario-s de0elopment tools re?-ired for 8086 pro$rammin$ are 5* E!it"r : +n Editor is a pro$ram .hich allo.s -s to create a file containin$ the assembly lan$-a$e statements for the pro$ram E=amples of some editors are #9 .rite >ordstar +s .e type the pro$ram the editor stores the +9)II codes for the letters and n-mbers in s-ccessi0e B+' locations If any typin$ mista/e is done editor .ill alert -s to correct it If .e lea0e o-t a pro$ram statement an editor .ill let yo- mo0e e0erythin$ do.n and insert a line +fter typin$ all the pro$ram .e ha0e to sa0e the pro$ram for a hard dis/ This .e call it as so-rce file The ne=t step is to process the so-rce file .ith an assembler >hile -sin$ T+)' or '+)' .e sho-ld $i0e a file name and e=tension +)' E=F )ample asm +*Asse/b-er : +n +ssembler is -sed to translate the assembly lan$-a$e mnemonics into machine lan$-a$e% i e binary codes* >hen yo- r-n the assembler it reads the so-rce file of yo-r pro$ram from .here yo- ha0e sa0ed it The assembler $enerates t.o files The first file is the (bRect file .ith the e=tension *O(F The obRect file consists of the binary codes for the instr-ctions and information abo-t the addresses of the instr-ctions +fter f-rther processin$, the contents of the file .ill be loaded in to memory and r-n The second file is the assembler list file .ith the e=tension *LST 0* LinAer : + lin/er is a pro$ram -sed to connect se0eral obRect files into one lar$e obRect file >hile .ritin$ lar$e pro$rams it is better to di0ide the lar$e pro$ram into smaller mod-les Each mod-le can be indi0id-ally .ritten, tested and deb-$$ed Then all the obRect mod-les are lin/ed to$ether to form one, f-nctionin$ pro$ram These obRect mod-les can also be /ept in library file and lin/ed into other pro$rams as needed + lin/er prod-ces a lin/ file .hich contains the binary codes for all the combined mod-les The lin/er also prod-ces a lin/ map file .hich contains the address information abo-t the lin/ed files The lin/ers .hich come .ith T+)' or '+)' assemblers prod-ce lin/ files .ith the *E2E e=tension

5@

:*L"c t"r : + locator is a pro$ram -sed to assi$n the specific addresses of .here the se$ments of obRect code are to be loaded into memory + locator pro$ram called E;E57IN comes .ith the I7' #9 "is/ (peratin$ )ystem %"()* E;E57IN con0erts a E;E file to a 7IN file .hich has physical addresses 6* Deb'))er: + deb-$$er is a pro$ram .hich allo.s to load yo-r obRect code pro$ram into system memory, e=ec-te the pro$ram, and tro-bleshoot or deb-$ it The deb-$$er allo.s to loo/ into the contents of re$isters and memory locations after the pro$ram r-ns >e can also chan$e the contents of re$isters and memory locations and rer-n the pro$ram )ome deb-$$ers allo.s to stop the pro$ram after each instr-ction so that yocan chec/ or alter memory and re$ister contents This is called sin$le step deb-$ + deb-$$er also allo.s to set a brea/point at any point in the pro$ram If .e insert a brea/ point , the deb-$$er .ill r-n the pro$ram -p to the instr-ction .here the brea/point is p-t and then stop the e=ec-tion 6* E/'- t"r: +n em-lator is a mi=t-re of hard .are and soft.are It is -s-ally -sed to test and deb-$ the hard.are and soft.are of an e=ternal system s-ch as the prototype of a microprocessor based instr-ment

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5!

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