ISSCC 2020 / SESSION 1 / PLENARY / 1.

3 ISSCC 2020 / February 17, 2020 / 10:40 AM

1.3 Future Scaling: Where Systems and Technology Meet strength can typically be recovered by increasing the fin height. However, this 1
typically brings increased process and integration complexity whereby even
Nadine Collaert mechanical stability of these high-aspect-ratio fins starts to become a
showstopper.
Program Director, imec, Leuven, Belgium
Derived architectures like nanosheets [4] (Figure 1.3.2b), thin slabs of Si channels
1.0 Abstract stacked on top of each other, are gaining a lot of interest because these devices
In a smart society where everything will be connected, an avalanche of data is not only provide improved electrostatics but also increased performance efficiency
coming toward us, with numbers going to several hundreds of zettabytes per year over FinFETs, enabling shorter gate lengths, higher drive current per given
by 2025! This data will need to be distributed, stored, computed, and analyzed to footprint, and relaxed requirements for elements such as specific contact
glean its most valuable information. At the heart of it will be innovations at the resistivity. But the n-to-p separation challenge remains, limiting further decrease
technology level, but also on the system side. With Moore’s Law under pressure, of the cell footprint. In FinFETs, the gate-over-active extension basically limits the
a rethinking of what the semiconductor industry calls scaling will be needed. reduction of the SRAM cell height as the gate needs to completely cover the
vertical sidewalls. Therefore, a new device architecture was proposed [5]:
In this paper, we will show that there is a strong push to technology Forksheet (Figure 1.3.2c). Essentially, forked gate-structures rely on creating a
diversification, blending different technologies together to achieve benefits at the dielectric wall between NMOS and PMOS before gate patterning such that a
system level. This brings the interaction of technology and design to the next natural barrier is formed to self-align both the gate and the contact. It removes
level: system-technology co-optimization (STCO), with 3D technologies taking a the gate-over-extension margin on one side of the device, allowing it to self-align
central stage. Furthermore, the growing demand for storage will put an increasing the gate edge with the channel, thereby offering a 20% bit-cell reduction over the
pressure on the memory hierarchy where emerging concepts like MRAM, FeFET, standard nanosheet layout.
so on, have the potential to bring new speed and capacity benefits. Next to that,
memories such as RRAM are getting a lot of traction for analog in-memory A more revolutionary step from nanosheets is the Complementary FET or CFET
computing to enable energy efficient machine learning at the IoT edge. Finally, [6] (Figure 1.3.2d), where NMOS is stacked on top of PMOS. This device concept
we will also briefly review the status of quantum computing, these days gaining addresses specifically the complementary nature of the cells, thereby eliminating
a lot of interest as a path to ultra-powerful computing. the n-to-p separation bottleneck altogether. The structure allows area gains up to
50% for both standard cells as well as SRAM, making it a possible total CMOS
Essentially, in this paper we motivate the following conclusions: scaling solution. The integration scheme can be grafted on a typical gate-all-
around process flow or alternatively use sequential 3D processing [7], a flavour
• While there is an increasing pressure on CMOS scaling, the trend
of wafer-level 3D processing that allows connections between the different tiers
from pure dimensional 2D scaling to scaling at the cell level (track
with the same resolution and density that advanced lithography can offer for
height reduction) will extend to the (sub-)system level.
standard Back-End-Of-Line (BEOL) metallization.
• In that respect, heterogeneous integration being able to co-integrate
different technologies will gain in importance and 3D integration will CFET is basically a first step towards exploiting the third dimension. Today a single
take an important place as an enabling technology. CMOS technology often enables all functions in the system (SoC). However, today
there is more of a trend to more customized designs, picking the best technology
• There is an increasing demand for storage and the boundaries
for the required functionality and nicely blending it together with the other parts
between logic and memory are fading.
of the system, which can often be quite dissimilar, rather than imposing one
• New computing paradigms such as machine learning (ML) and generic technology that would fit all.
quantum computing needed for big data analytics and intractable
computing problems are gaining a lot of traction, and they will benefit This heterogeneous integration requires setting up a similar methodology as
from innovations at the material, device, and architecture level to DTCO but moving the abstraction level up to the (sub-)system: STCO where
enable powerful and energy-efficient solutions. optimization is done across many different levels, from process unit steps and
integration up to the application level (Figure 1.3.1). A few examples will be given
2.0 CMOS Scaling at its End? in upcoming sections.
Undeniably CMOS scaling [1] has been the fuel enabling the tremendous progress
over the past decades to boost performance, efficiency, and reduced cost of 3.0 Heterogeneous Integration and 3D Technologies
integrated circuits and systems, thereby enabling novel applications. Many times, Emerging applications such as ML, 5G, AR/VR and so on will require a variety of
the end of Moore’s Law has been predicted, while innovations in materials, device functionalities to be enabled (in-memory computation, ultra-low power, high
concepts, and patterning have cleared the path towards the current sub-10nm speed, and so on). There is increasing need for hybrid scaling where these various
technology. However, the industry has come to a point where the typical gains in technologies blend together. Device concepts considered before as part of the
Power, Performance, Area, and Cost (PPAC) that scaling has brought over five scaling roadmap, but discarded being not a complete CMOS solution, are being
decades have become increasingly hard to achieve especially when looking considered again in the context of other applications and in the context of
forward beyond 3nm. Already with the introduction of 22nm FinFET [2], it has heterogeneous integration.
become clear that pure dimensional scaling on its own is not enough to fulfill the
demands of semiconductor economics. The concept of Design-Technology Co- One example is resistive RAM (RRAM) for machine learning. This will be further
Optimization (DTCO) [3] (Figure 1.3.1), where scaling is ported to the level of explained in section 5.0. A second example is related to the use of compound
functional blocks, has gained a lot of traction, and is currently more and more semiconductors like GaN and III-V. In the quest for logic transistors that can
becoming a standard methodology used in industry to assess technology trade- deliver higher speed at reduced supply voltage, these materials have been
offs and define design rules for the next generation. For example, at 3nm the area considered as replacement of the Si channel in a MOSFET because of their intrinsic
reduction from scaling the gate pitch and metal pitch only is at most 34%, versus higher mobility and saturation velocity [8]. Challenges related to their co-
the required 50%. Therefore, special constructs that help to reduce the cell integration on CMOS-compatible Si substrates, reliability aspects related to the
scaling, have been proposed, like buried power rail [3, 4] where, by embedding gate stack and scalability have been the focus of the general R&D effort over the
the power lines in the isolation of the Front-End-Of-Line (FEOL) or the substrate, past decade. While it became increasingly clear that the performance of these
the track height of the standard cell can be scaled from 6 tracks (6T) to 5 tracks devices at ultra-scaled dimensions would not be able to compete with the mature
(5T). Si FinFET technologies, the progress that has been made on co-integration of
these dissimilar materials on a Si platform led the way to consider them again as
From a device architecture point of view, FinFET (Figure 1.3.2a) is still the main viable options for other applications (high-voltage and RF applications), but this
device concept of interest but cell-height scaling is forcing fin depopulation, time adding the advantage of being able to fabricate them in CMOS-compatible
reducing the number of fins per device from two fins to finally a single fin, thereby production lines. In the case of high-voltage applications, GaN-on-Si has gained
significantly weakening the device strength and increasing the variability. Device a lot of momentum over the past years as a cost-efficient option as compared to

DIGEST OF TECHNICAL PAPERS • 25

Authorized licensed use limited to: Siksha O Anusandhan University. Downloaded on April 09,2021 at 11:52:34 UTC from IEEE Xplore. Restrictions apply.
ISSCC 2020 / SESSION 1 / PLENARY / 1.3

GaN-on-SiC, enabling upscaling to larger size substrates than 6 inch, while write paths can be optimized separate from each other. By integrating a
delivering high output power at higher frequencies than LDMOS. Trends in the ferromagnet in the hard mask that shapes the SOT [21], faster switching at lower
GaN high-voltage area are related to looking at Coefficient of Thermal Expansion power can be achieved.
(CTE)-matched substrates beyond Si but still compatible with CMOS processing.
New device concepts like semi-vertical devices that allow high breakdown voltage Another approach looks at stacking memory like SRAM and logic on top of each
and higher current per area, improved reliability and easier thermal management, other. This allows increased bandwidth, reduced form factor, and increased
and moving from standalone components to GaN-IC options where more power efficiency. Standard 3D Through-Silicon-Via (TSV) or wafer-to-wafer
functionality is enabled in the GaN layer [9, 10] (Figure 1.3.3). Next to that, with bonding technologies can be used for this purpose, but also an hybrid approach
its unique properties like high sheet charge, high electron mobility and wide where the shortest interconnects between devices and standard cells can be
bandgap, GaN or III-V devices in general are also very interesting for high realized by sequential 3D processing and interconnects at block level by standard
frequency applications. With 5G deployment and already having the next 3D-technologies can give the best trade-off in process complexity and power-
generation wireless communication in mind where even higher data-rates are performance gain. It also allows introducing specific device architectures and
envisioned (>100Gb/s), there is a clear concern related to the increasing technologies for the logic part and for the SRAM part (vertical devices or VFET).
complexity of the RF Front-End-Module (RF-FEM), especially at the higher mm- It has been shown in [22] that VFET can be very beneficial for SRAM applications,
wave frequencies, where beamforming radio architectures will require the use of allowing one to reduce the area especially if one considers stacking them.
phased antenna arrays. This is particularly true where output power Pout and
efficiency PAE of the CMOS-based power amplifiers is becoming limited. Enabling DRAM scaling is under pressure and levelling off at 1nm. To replace DRAM is
a higher Pout and PAE means a lower number of elements will be needed to drive very difficult and most research is focused on stacking DRAM into high-bandwidth
the antennas and more energy-efficient systems at smaller form factor can be modules, while the technology is still expected to further scale.
enabled, which is essential for handheld devices and small cells limited in area.
But the lower integratability of these GaN and III-V devices, restricted to smaller Though not replacing NAND Flash and DRAM, 3D XPoint, based on PCRAM
size substrates and lab-like processing today, has been for long one of the key (introduced by Intel in 2015) [23], has gained a lot of attention over the past years.
concerns for adopting these technologies. Upscaling these devices to a 200mm Currently, a two-layer stacked architecture with 128Gb density and 20nm
and even 300mm Si platform will be a first step to making them more attractive geometries, is expected to go in the next generation to a four-layer stack and
for a variety of applications including photonics where III-V on Si laser integration double the density.
currently a very active field of research [11-14] (Figure 1.3.4). The co-integration
of these devices with Si CMOS opens up new opportunities to combine the power FeFET is a technology that is still in the R&D phase [24]. In this device,
and speed of the compound semiconductor devices with the CMOS control ferroelectric material is introduced in the gate stack of a standard MOSFET. The
circuitry [15], allowing more power-efficient systems (envelope tracking) [16]. dipole changes the threshold voltage of the transistor in a non-volatile way. While
This co-integration can be enabled in a few ways: Either by using monolithic still heavily debated regarding its use as a steep-slope device for logic
integration where the III-V devices are placed next to CMOS in the same substrate applications, its benefits for memory are more clear: scalability, fJ energy
or using 3D integration (Figure 1.3.5). The latter is gaining more interest as it consumption, write/read speed in 10ns, high endurance and retention. However,
allows one to process and optimize the dissimilar technologies in an independent upscaling from one device to millions of memory cells that need to perform almost
way and then put them together through wafer bonding or TSV-based in an identical way still needs to be proven.
interconnections [17]. Alternatively, sequential 3D processing [18], where the
different device tiers are processed in a sequential way, has the potential to In general, even earlier than logic applications, there is a continuing trend in
integrate smaller sized interconnects with high density and shorter length between memory to go 3D and stack more layers on top of each other to increase
the different tiers. Next to that, the reduced area has also been one of the main bandwidth.
drivers to look into this technology. In [19], this approach has been shown with
planar Si junction-less RF devices on bulk Si. No impact of the device stacking Finally, when looking at cold storage, DNA or more general molecular memory is
has been seen and the RF performance of the devices is in line with the expected one of the more exploratory routes. The idea is to use molecules to archive large
1/LG dependence of fT. This first demonstration shows the way to build dedicated amount of data. Challenges are related to writing and reading where based on life
top tier devices with different materials and architectures and combine them with science applications, specific sequencing techniques can be used [25].
advanced CMOS devices that provide the logic functionality.
5.0. The Era of Machine Learning (ML) and Quantum Computing
4.0. Increasing Demand for Storage – Memory in the Spotlight
Over the past years, the use of Artificial Intelligence (AI) has been booming,
There is an increasing demand for data storage and processing (automotive finding its way from image processing to speech recognition to diagnosing
applications). For years, people have been looking for a universal memory that diseases and predicting weather conditions. These applications often require
combines the best of DRAM and NAND Flash, which are low cost, proven, and energy-hungry data processing in the cloud. Most implementations are based on
versatile, and could potentially replace them and address the increasing demands GPUs, some on FPGAs, and few on ASICs specifically built for deep learning.
for bandwidth and reduced power consumption. When looking at the memory Issues related to latency, power efficiency, and privacy on the other hand demand
hierarchy (Figure 1.3.6), there is no shortage of new memories, materials, and that this processing is done at the edge, where battery-driven Internet-of-Things
architectures that are being considered to replace the various tiers in the memory (IoT) devices put high requirements related to energy efficiency and consumption,
hierarchy. While Phase Change RAM (PCRAM or PCM), Resistive RAM (RRAM), sometimes even at the mW level. For supervised learning, the parameters can still
Ferroelectric FETs (FeFETs) and various kinds of Magnetic RAM (MRAM) have be processed in the cloud, but inference, the decision-making needs to be brought
been the topic of most R&D effort over the past years, however, currently SRAM, to the sensors. This requires training layers of memory in the deep learning
DRAM, and NAND Flash are still the mainstream memories. process, fetching repetitively weighted data stored in this memory through those
successive layers. Each memory array represents one layer of the neural network.
To replace the SRAM L1 cache, Spin-Torque-Transfer MRAM (STT-MRAM) has Having the data close to the processor reduces latency and power consumption,
been considered, combining the speed of SRAM and the non-volatility of flash which are the premises of compute-in-memory.
[20]. Next to that, it is a 1-transistor architecture with a magnetic-tunnel junction
(MTJ) memory cell that could be an answer to the increasing difficulties to scale To store the values of the learned weights, analog non-volatile devices are used,
SRAM cell size. So far, STT-MRAM has a clear value proposition for SRAM L3 such as resistive RAM (RRAM) technology, once seen as a NAND Flash
but it is not fast enough to replace the L1 and L2 cache. Moreover, the memory replacement, but in the context of AI repositioned as a dedicated AI memory
cell suffers from reliability issues due to the shared write/read lines. Although still technology. In this case, the learned weights are encoded in the individual device
in an R&D phase, Spin-Orbit-Torque MRAM (SOT-MRAM) might be a better conductance, which changes as the number of writes increases, and the input
option, in that respect. SOT-MRAM integrates a SOT layer under the device. It values are set as the word line (WL) voltages of the RRAM arrays. The cell’s
induces switching of the layer by injecting an in-plane current in an adjacent SOT current is then a multiplication of the weight and the input value, and the word
layer. There are two different paths for read and write, where the read is STT-like, line’s current will be the summation of the cell currents in that line. This is an
while the write is not done through the MTJ. The advantage is that the read and efficient way of implementing convolutions without moving the weights around.

26 • 2020 IEEE International Solid-State Circuits Conference 978-1-7281-3205-1/20/$31.00 ©2020 IEEE

Authorized licensed use limited to: Siksha O Anusandhan University. Downloaded on April 09,2021 at 11:52:34 UTC from IEEE Xplore. Restrictions apply.
 ISSCC 2020 / February 17, 2020 / 10:40 AM

In general, analog computing will only be interesting if one can allow lower [5] P. Weckx et al.,” Stacked Nanosheet Fork Architecture for SRAM Design and 1
precision, increased variability, and systematic errors. Variation in these typical Device Co-Optimization toward 3nm”, IEDM Technical Digest, pp. 505-508, 2017.
filamentary RRAM cells is in general too high when operated at sufficiently high [6] J. Ryckaert et al., “The Complementary FET (CFET) for CMOS Scaling Beyond
resistance levels, and therefore other memory technologies like InGaZnO (IGZO)- N3”, VLSI Technology Symposium, pp. 141-142, 2018.
based 2T-1C DRAM [26], SOT-MRAM and PCM with separated write path are also [7] A. Vandooren et al., “First Demonstration of 3D Stacked FinFets at a 45nm Fin
being considered [27]. Pitch and 110nm Gate Pitch Technology on 300mm Wafers”, IEDM Technical
Digest, pp. 149-152, 2018.
Finally, quantum computing, using spins/electrons as quantum information [8] N. Waldron et al., “An InGaAs/InP Quantum Well FinFet Using the Replacement
carriers and holding great promise to solve intractable computing problems [28], Fin Process Integrated in an RMG Flow on 300mm Si Substrates”, VLSI
was until a few years ago only a dream in the mind of physicists. But large Technology Symposium, pp. 32-33, 2014.
momentum has been gained in the community to push this radical new computing [9] H. Amano et al., “The 2018 GaN Power Electronics Roadmap”, J. Phys. D:
paradigm where the basic building block is the q-bit (Figure 1.3.7), to the next Appl. Phys., 51, 163001, 2018.
level and make it a technological reality [29-31]. Increasingly more effort is being
[10] X. Li et al., “GaN-on-SOI: Monolithically Integrated All-GaN ICs for Power
put on the development of Si-based platforms for rapid and statistically relevant
Conversion”, accepted for presentation at IEDM, session 4.4, 2019.
pathfinding and benchmarking to solve the key challenges in quantum computing.
[11] B. Kunert et al., “III/V Nano Ridge Structures for Optical Applications on
Patterned 300mm Silicon Substrate”, Appl. Phys. Lett., 109, 091101, 2016.
6.0. Conclusions
[12] B. Kunert et al., “Gaining an Edge with Nano-Ridges”, Compound
While the death of Moore’s Law has been predicted many times over the past Semiconductor, vol. 24, no. 5, pp. 36-41, 2018.
decades, it is only now, with 3nm technology in sight, that industry has come to [13] A. Vais et al., “First Demonstration of III-V HBTs on 300mm Si Substrates
a point where the typical gains in power, performance, area, and cost (PPAC) have Using Nano-Ridge Engineering”, accepted for presentation at IEDM, session 9.1,
become increasingly harder to achieve. There is a clear trend to push the current 2019.
FinFET technology as far as possible, often enhanced by scaling boosters or [14] U. Peralagu et al., “CMOS-Compatible GaN-Based Devices on 200mm-Si for
special constructs that help to reduce the cell scaling. But derived architectures RF Applications: Integration and Performance”, accepted for presentation at IEDM,
such as nanosheets are also gaining a lot of interest as the ultimate device that session 17.2, 2019.
allows improving the electrostatics and increasing the performance efficiency, [15] D. Yan et al., “Design of a 28 GHz Differential GaAs Power Amplifier with
with CFET, where nMOS is stacked on top of pMOS or vice versa, as a more Capacitive Neutralization for 5G mm-Wave Applications”, 17th IEEE International
revolutionary step from nanosheets, that would enable further scaling.
NEWCAS Conference, 2019.
[16] Tong Ge et al., “Envelope Tracking RF Power Amplifiers: Fundamentals,
Today, a single CMOS technology often enables all functions in the system.
Design Challenges, and Unique Opportunities Offered by LEES-SMART InGaAs-
However, emerging applications such as ML, 5G, energy, AR/VR., and so on will
on-CMOS Process”, Procedia Engineering 141, pp. 94 – 97, 2016.
require a variety of functionalities to be enabled (in-memory computation, ultra-
low power, and so on) and there is an increasing need for hybrid scaling where [17] E. Beyne, “3D Interconnection and Packaging: Impending Reality or Still a
various technologies go together. 3D integration will be a key enabler, and thus Dream?”, IEEE International Solid-State Circuits Conference (ISSCC), 7.4, 2004.
bringing the scaling concept to the next level where an increased number of [18] P. Batude et al., “3DVLSI with CoolCube Process: An Alternative Path to
technologies will be customized to meet the system requirements, rather than Scaling”, VLSI Technology Symposium, p. 48-49, 2015.
imposing one generic technology. In this respect, system-technology co- [19] A. Vandooren et al., “3D Sequential Stacked Planar Devices on 300mm
optimization (STCO) is gaining importance as a means to guide the technology Wafers Featuring Replacement Metal Gate Junction-Less Top Devices Processed
choices that will impact the subsystem and/or system level. at 525°C with Improved Reliability”, VLSI Technology Symposium, p. 69-70,
2018.
In all these applications, there is also a clear need for more memory. While SRAM, [20] Y. K. Lee et al., “Embedded STT-MRAM in 28-nm FDSOI Logic Process for
DRAM and NAND Flash are still going strong, industry is continuously looking for Industrial MCU/IoT Application”, VLSI Technology Symposium, p. 181-182, 2018.
that universal memory that can replace all of them, with many new memories [21] K. Garello et al., “Manufacturable 300mm Platform Solution for Field-Free
being researched (SOT-MRAM, FeFET, PCM, and RRAM). Switching SOT-MRAM”, VLSI Technology Symposium, p. 194-195, 2019.
[22] T. Huynh-Bao et al., “A Comprehensive Benchmark and Optimization of 5-
Some of these emerging memories have also interesting properties for use in nm Lateral and Vertical GAA 6T-SRAMs”, IEEE TED, pp. 643-651, Vol. 63, 2016.
machine learning where in order to bring energy-efficient inference to the edge, [23] F. T. Hardy et al.,” Platform Storage Performance With 3D XPoint
analogue in-memory computing is being considered. Technology”, Proceedings of the IEEE, vol 105, no. 9, pp. 1822-1833, 2017.
[24] K. Florent et al., “First Demonstration of Vertically Stacked Ferroelectric Al
Further out on the roadmap, the promise of quantum computing is alluring, while Doped HfO2 Devices for NAND Applications”, VLSI Technology Symposium, p.
it is still very much in its infancy, the decades of experience in Si technology 158-159, 2017.
applied to the quantum world might give the research community that extra boost [25] D. Carmean et al., “DNA Data Storage and Hybrid Molecular–Electronic
to make this a technological reality! Computing”, Proceedings of the IEEE, vol 107, no. 1, pp. 63-72, 2019.
[26] H. Kunitake et al., “High Thermal Tolerance of 25-nm C-Axis Aligned
Acknowledgements:
Crystalline In-Ga-Zn Oxide FET”, IEDM Technical Digest, pp.312-315, 2018.
The author would like to thank Dr. Piet Wambacq for support and guidance. I also
[27] S. Cosemans et al., “Towards 10000TOPS/W DNN Inference with Analog in-
wish to acknowledge contributions of the LOGIC/NANOIC, memory, 3D, High-
Memory Computing – A Circuit Blueprint, Device Options and Requirements”,
speed analog/RF, machine learning and quantum computing research teams at
IEDM Technical Digest, invited, 2019.
imec. This research work was also supported by the imec’s IIAP program
[28] D. Loss and D. P. DiVincenzo, “Quantum Computation with Quantum Dots”,
members, the European Commission, and local authorities.
Phys. Rev. A, vol. 57, no. 1, pp. 120-126, 1998.
References: [29] B. Govoreanu et al., “Moving Spins from Lab to Fab: A Silicon-Based Platform
[1] G.E. Moore, “Cramming More Components onto Integrated Circuits”, for Quantum Computing Device Technologies”, IEEE Silicon Nanoelectronics
Electronics, 38, 1965. Workshop, pp. 1-2, 2019.
[2] C. Auth et al.,” A 22nm High Performance and Low-Power CMOS Technology [30] L. Hutin et al., “All-Electrical Control of a Hybrid Electron Spin/Valley Quantum
Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Bit in SOI CMOS Technology”, VLSI Technology Symposium, p. 125-126, 2018.
Density MIM Capacitors”, VLSI Technology Symposium, pp. 131-132, 2012. [31] F. A. Mohiyaddin et al.,”Multiphysics Simulation & Design of Silicon Quantum
[3] A. Mocuta et al., “Enabling CMOS Scaling Towards 3nm and Beyond”, VLSI Dot Qubit Devices”, accepted for presentation at IEDM, session 39.5, 2019.
Technology Symposium, pp. 147-148, 2018.
[4] J. Ryckaert et al., “Enabling Sub-5nm CMOS Technology Scaling: Thinner and
Taller!”, accepted for presentation at IEDM, session 29.4, 2019.

DIGEST OF TECHNICAL PAPERS • 27

Authorized licensed use limited to: Siksha O Anusandhan University. Downloaded on April 09,2021 at 11:52:34 UTC from IEEE Xplore. Restrictions apply.
 ISSCC 2020 / SESSION 1 / PLENARY / 1.3

Figure 1.3.2: Evolution of device architectures under consideration for the 3nm
Figure 1.3.1: From traditional dimensional scaling to Design Technology Co- technology nodes and beyond: (a) TEM picture of the high aspect ratio FinFET,
Optimization (DTCO)-guided scaling to System-Technology Co-Optimization (b) TEM picture of a stacked nanosheet device, (c) schematic of the fork-sheet
(STCO). and (d) schematic of the Complementary FET (CFET).

Figure 1.3.4: (left) SEM picture of a GaAs layer grown on a 300mm Si substrate
Figure 1.3.3: Schematic presentation of a GaN-on-SOI process with deep trench using a combination of aspect ratio trapping and overgrowth allowing to reduce
isolation enabling the integration of different GaN IC components on the same defectivity in the III-V material and (right) the use of this nano-ridge technology
substrate. for the monolithic integration of III-V lasers for photonics applications.

Figure 1.3.5: Different 3D technologies from package to die/wafer to device Figure 1.3.6: Memory hierarchy and schematic presentation of emerging
level stacking. memories being considered along the different levels of the hierarchy.

28 • 2020 IEEE International Solid-State Circuits Conference 978-1-7281-3205-1/20/$31.00 ©2020 IEEE

Authorized licensed use limited to: Siksha O Anusandhan University. Downloaded on April 09,2021 at 11:52:34 UTC from IEEE Xplore. Restrictions apply.
 ISSCC 2020 / February 17, 2020 / 10:40 AM

Figure 1.3.7: (left) Tilted SEM picture of a Si q-bit implementation and (right)
top view picture of a superconducting resonator.

DIGEST OF TECHNICAL PAPERS • 29

Authorized licensed use limited to: Siksha O Anusandhan University. Downloaded on April 09,2021 at 11:52:34 UTC from IEEE Xplore. Restrictions apply.