Vs10Xx Appnote: Connecting Analog Outputs
Vs10Xx Appnote: Connecting Analog Outputs
Solution y
PLe Public Document
Description
This document describes how to protect the analog outputs of VS10XX series
devices from ESD and how to make a prtoected line-out connection. It shows an
example schematic and gives general info on output protection including issues
with single ended line-out connections.
This document applies to VS1001, VS1011, VS1002, VS1003, VS1033, VS1053 and
VS1000.
Revision History
Rev Date Author Description
1.25 2009-03-23 PLe In Figure 7 R3 and R19 changed to 10kOhms
1.24 2008-12-04 PLe New “line-out”-circuit recommendation
1.23 2006-11-27 PLe GBUF RC values changed to 10ohm and 47n
1.22 2006-08-18 PLe Additional ESD protection and line-out info
1.21 2006-04-20 PLe New Simple line-out schematic.
1.20 2006-04-06 PLe Notes on power-down.
1.10 2006-03-06 PLe More info on ESD.
1.00 2006-02-28 PLe Initial revision.
Table of Contents
1 Background 3
3 Line-out Connection 6
5 Contact Information 10
List of Figures
1 Background
The Human Body Model (HBM) replicates the typical discharge from the finger of
a standing person of average weight and height. Testers use a 100pF capacitor in
series with a 1500ohm resistor to simulate the ESD from people. (Figure 1)
Machine Model (MM) shown in figure 2 replicates the charge generated by for
example “pick and place” IC handlers or soldering iron. The MM has no series
resistance but a larger capacitor. The voltages in MM test are generally lower than
in HBM. Due to the lack of the series resistor chips often fail in lower voltages than
in HBM tests. (Reference: Carl Duffy, AMD, Test & Measurement Europe/April-
May 1998)
Our qualification tests use the HBM. IC’s are tested (or “shot”) with three positive
and three negative pulses between each pin. Ground pins are grouped together.
Each pin is then tested against GND. Next each pin is tested against each power
pin group. In last phase each IO pin is tested against any other IO pin.
In VS10XX devices the analog output pins (LEFT, RIGHT and GBUF) are biased
close to 1.25V to allow DC-coupling to headphones. Minimal recommended output
connection is shown in figure 3.
The RC-combo on each analog pin protects the VS10XX device from ESD surges
on the analog signals. The RC-combo also provides a resistive load for the DAC at
high frequencies and must not be omitted even if other methods of ESD protection
are used. Notice the different values for R4 and C5.
Laboratory tests show that this connection can tolerate 8kV ESD pulses (HBM) re-
peatedly with no damage to the VS10XX device. Depending on the application the
system may halt or reset itself but the VS10XX device is not damaged. Tests were
cunducted with Prototyping board (http://www.vlsi.fi/player vs10xx proto/player.shtml)
and ESD pulses were shot to the output connector with power on and with and
wihtout headphones.
To prevent ESD surges entering the PCB the RC-combo should be placed as close
to the output connector as possible. High frequency capacitors with low internal
resistance should be used.
Extra protection can be achived by using a suitable TVS (Transient Voltage Su-
pressor). Figure 4 shows one way of connecting TVS to VS10XX. The TVS should
be connected as close to the input connector as possible. Quality device with
short turn-on time and suitable clamping voltage and peak pulse power should be
selected.
Our laboratory tests show that with a good TVS device VS10XX devices can
tolerate ESD pulses (HBM) up to 10kV contact discharge and 16kV air discharge
(HBM). Test setup was the same as with RC protection.
ESD protection diodes can also be used to provide extra protection. Figure 5 shows
one way of using diodes to protect the analog signals. Notice C8 which provides a
short path to GND for positive ESD surges when a short connection to AVDD is
not possible.
3 Line-out Connection
It’s not recommended to use GBUF as audio ground when connecting to other
electrical equipment such as power amplifiers or PC line-inputs. The GBUF pin
is internally biased to 1.25V and it is possible that a ground loop is formed when
the GBUF is connected to the ground of the target device. This may damage the
VS10XX device and will prevent normal operation.
Figure 6: Ground loop is formed when GBUF and USB is connected to PC ground
A ground loop can happen for example with a VS10XX application that uses GBUF
and has USB or Ethernet connected and the output of VS10XX is connected to a
PC souncard. Figure 6 illustrates this situation. DC blocking capacitors should be
Figure 7 shows a high quality and cost-effective solution to the transient problem.
The circuit uses bipolar NPN transistors to hold the outputs near ground level
when the output capacitors charge. PNP transistors are used to drive the NPN’s.
This way when the output mute is off (the /MUTE signal is high) and the output
signal goes below ground the NPN will not conduct due to reverse gain of the NPN.
The circuit was measured with Rohde&Schwarz audio analyzer. It did not effect
the THD+N performance of the analog output in normal operation mode. In
“Mute”-mode the attenuation was approximately 40dB.
Usage (power-up):
1. Keep VS10XX in reset
2. Use uC to pull the “/MUTE” signal down.
3. Release VS10XX from reset (set XRESET high)
Usage (power-down):
1. Pull “/MUTE” low to mute outputs.
2. Shutdown VS10xx
The value of coupling capacitors (C1 and C68) should be chosen based on the input
impedance of the amplifier the VS10XX will be connected to and on the low freq
cut-off desired. R2 and R80 should be in the range from 10k to 100k ohms.
1
The cut off frequency is calculated as follows: f−3dB = 2πRC where: C = C1
R2∗Rload
R = R1 + R2+Rload and Rload is the resistance of the load. Bigger C will give lower
cut-off frequecy but increases required wait time to disable the mute circuit.
C2 and C69 form a low-pass filter with R1 and R79. This filters some of the
quantization noise of the Delta-Sigma DA-converter. The values can be adjusted
to suit the application. 470ohm/3.3nF gives Fc of approx 100kHz.
Some transient in the outputs during power up and down will occure if the startup
is not slowed down with software.
5 Contact Information
VLSI Solution Oy
Hermiankatu 8 B
FIN-33720 Tampere
FINLAND