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Project Title 16 Bit ISA Design

This document outlines the design of a 16-bit RISC-type instruction set architecture. It includes 3 instruction formats (R-type, I-type, and J-type) and defines the operations, registers, and instructions. The objective is to design an assembler that takes assembly code as input and outputs the corresponding binary machine instructions. The design is limited by the 16-bit instruction size but provides students hands-on experience with computer architecture concepts.

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Sudipa Saha
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101 views7 pages

Project Title 16 Bit ISA Design

This document outlines the design of a 16-bit RISC-type instruction set architecture. It includes 3 instruction formats (R-type, I-type, and J-type) and defines the operations, registers, and instructions. The objective is to design an assembler that takes assembly code as input and outputs the corresponding binary machine instructions. The design is limited by the 16-bit instruction size but provides students hands-on experience with computer architecture concepts.

Uploaded by

Sudipa Saha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Project Title

16 bit ISA design

Course Title: Computer Organization and Architecture


Instructor Initial: TnR
Section: 01

12/20
Project done by:
Iftakhar Al Shahriar
ID: 1722253642
Nishat Maharin Bushra
ID: 1912903642
Fazlay Rabbi
ID: 1921598642
Introduction:
Instruction set architecture (ISA) is an abstract model of computers. Our task is to design
and implement an assembler for 16-bit RISC type CPU.

Objective:
After converting a high level programming language into assembly language by a compiler, the
assembler takes the assembly language as input and convert into a binary instruction (machine
language) for hardware as 16 bit output.

Operands:
By following the design principle 1, we have used 3 type of operands in our design. They are
mainly register based.
Format
R-Type
Op rs rt rd
Code

4 bit 4bit 4bit 4bit

I-Type
Op-Code rs rt Immediate

4 bit 4bit 4bit 4bit

J-Type
Op-Code Target Address

4 bit 12bit

requires compromises. In our Structure we have chosen 3 formats. If we deal with constant (like
a = a + 4), we can’t deal with R-Type format. So we need an immediate type format. For
conditional statements, sometime we need to jump to a particular line or need to out of a loop.
In that case, we need J-Type Design principle 3 says, good design e format.

Registers
Register Number Name of the Usage Value Assigned
Registers (4 bit)

0 $zero Hard-wired to 0 0000


(constant value 0)

1 $t0 Temporary 0001

2 $t1 Temporary 0010

3 $t2 Temporary 0011

4 $t3 Temporary 0100

5 $s0 Save 0101

6 $s1 Save 0110

7 $s2 Save 0111

8 $s3 Save 1000

9 $s4 Save 1001

10 $s5 Save 1010

11 $gp Global Pointer 1011

12 $sp Stack Pointer 1100

13 $fp Frame Pointer 1101

14 $ra Return Address 1110

15 $a0 Arguments to 1111


functions

unneccessery to declare rigisters


Operations
for stack pointers, frame pointer etc
R-Type Table
Instruction Type Instruction Op-Code

Arithmetic add 0000


sub 0001

Logical and 0010

or 0011

nor 0100

xor 1110

I-Type Table
Instruction Type Instruction Op-Code

Data Transfer lw 0101

sw 0110

Conditional Branch beq 0111

mul 1000
cant implement
Arithmetic addi 1001

Logical andi 1010

ori 1011

sll 1100

srl 1101

J-Type Table
Instruction Type Instruction Op-Code

Unconditional Jump J 1111

In and Out instructions are missing


Operations’ Instructions
add:
It adds the content of the source register 1 to the contents of the source register 2 and saves it
in the destination register.
Operation: $s0 = $s0 + $t0
Syntax: add $s0, $s0, $t0
sub:
It subtracts the content of the source register 2 from the contents of the source register 1 and
saves it in the destination register.
Operation: $s0 = $s0 – $t0
Syntax: sub $s0, $s0, $t0
and:
It does a bit by bit logical and operation between two source registers
contents. Operation: $s0 = $s0 & $t0

Syntax: and $s0, $s0, $t0


or:
It does a bit by bit logical or operation between two source registers
contents. Operation: $s0 = $s0 || $t0

Syntax: or $s0, $s0, $t0


nor:
It does a bit by bit logical “nor” operation between two source registers
contents. Operation: $s0 = ~ ($s0 | $t0)
Syntax: nor $s0, $s0, $t0
slt: you did not declare this instruction
It compares the contents of two source registers. If the content of 1st source register is less than
the second source register, then it sets the value of destination register to 1, otherwise 0
Operation: if ($s0 < $t0)
$s0 = 1
Else $s0 = 0
Syntax: slt $s0, $s0, $t0
lw:
It loads the contents of the memory specified by the offset and saves it into a destination
register.
Operation: $s0 = Memory [$s1 + offset]
Syntax: lw $s0, 2($s1)
sw:
It stores the contents of a source register to the memory address specified by the
offset. Operation: Memory [$s1 + offset] = $s0

Syntax: sw $s0, 2($s1)


beq:
It checks if the content of the provided register is equal to the contents of another register or not.
If equal jumps a relative number of instructions else continue.

Operation: if ($s0==$t0) jump to L (Label)


Else go to next line
Syntax: beq $s0, $t0, L

addi:
It can add direct value (constant) with a content of a source register.
Operation: $s0 = $t0 + immediate value
Syntax: addi $s0, $t0, 4
andi:
It does logic bit by bit and operation with a constant value and a content of a source register.
Operation: $s0 = $t0 & immediate value
Syntax: andi $s0, $t0, 4
ori:
It does logic bit by bit or operation with a constant value and content of a source register.
Operation: $s0 = $t0 || immediate value

Syntax: ori $s0, $t0, 4


srl:
This operation shifts the content of a register to right by a constant and stores shifted value
to the destination register.
Operation: $s0 = $t0 >> 4
Syntax: srl $s0, $t0, 4
sll​:
This operation shifts the content of a register to the left by a constant and stores shifted
value to the destination register.
Operation: $s0 = $t0 << 4
Syntax: sll $s0, $t0, 4
J:
It jumps a relative number of instruction/s specified by the given label
number. Operation: jump to Label

Syntax: J, L

Limitations
Our operations are limited because of limited instruction size for the CPU. And users must
provide valid instructions in the correct manner in order to decode and execute instructions
and must strictly follow syntax rules. Each instruction is separated by a new line and the user
must follow spacing rules.

Conclusions
Applying our methodology in computer architecture courses allows students to understand how
each part of a modern computer works, how the parts interact, and how to synchronize the
different functional units. It also allows visualizing the relation of theoretical concepts with
physical devices.

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