Improved SIMD Architecture for High

Performance Video Processors

Vicky Pawar Shivam Mandal
Student, Department of Electronic Engineering, Student, Department of Electronic Engineering,
Shree L.R.Tiwari college of Engineerig, Shree L.R.Tiwari college of Engineerig,
Mumbai, India. Mumbai, India.
pkpawar26@gmail.com shivam.mandal000@g,ail.com

Prof. Rohini Rathod

Department of Electronic Engineering,
Shree L.R.Tiwari college of Engineerig,
Mumbai, India.
rohini.jadhav@slrtce.in

Abstract – SIMD execution is in no doubt an efficient way to exploit the data level parallelism in image and video
applications. However, SIMD execution bottlenecks must be tackled in order to achieve high execution efficiency. We
first analyze in this paper the implementation of two major kernel functions of H.264/AVC namely, SATD and subpel
interpolation, in conventional SIMD architectures to identify the bottlenecks in traditional approaches. Based on the
analysis results, we propose a new SIMD architecture with two novel features: (1) parallel memory structure with
variable block size and word length support; and (2) configurable SIMD structure. The proposed parallel memory
structure allows great flexibility for programmers to perform data access of different block sizes and different word
lengths. The configurable SIMD structure allows almost “random” register file access and slightly different
operations in ALUs inside SIMD. The new features greatly benefit the realization of H.264/AVC kernel functions.
For instance, the fractional motion estimation, particularly the half to quarter pixel interpolation, can now be
executed with minimal or no additional memory access. When comparing with the conventional SIMD systems, the
proposed SIMD architecture can have a further speedup of 2.1X to 4.6X when implementing H.264/AVC kernel
functions. Based on Amdahl’s law, the overall speedup of H.264/AVC encoding application can be projected to be
2.46X. We expect significant improvement can also be achieved when applying the proposed architecture to other
image and video processing applications.

Keywords – Configurable SIMD, Parallel memory structure, SIMD bottlenecks, video codec processor

I. INTRODUCTION For this reason, the Single Instruction Multiple

Data (SIMD) architecture is most suitable and is
With the extensive use of image and video widely adopted. Two popular examples are Intel’s
information in modern computer applications, the MMX/SSE1/SSE2/SSE3 [2] and Motorola’s
development of high performance image and video AltiVec [3], where multimedia SIMD instruction
processing units has attracted much interest from set extensions have been added for efficient
both academic researchers and VLSI system realization of video processing applications.
designers. Among the image and video processing In recent years, many researchers studied how
operations that are performed in general computer much performance can be gained after using SIMD
applications, video coding is the most computation instructions in modern video codec [4]-[9].
intensive operation that is often used as the Simulation results using reference model
benchmark to measure the performance of a video demonstrate that there is at least 2-12X speedup. A
processor. For the rest of this paper, we shall focus basic requirement to employ SIMD instructions is
on the realization of the state-of-the-art video to possibly feed multiple data elements perfectly
coding standard H.264/AVC [1] and use it as an into vector registers so that the same computation
example to illustrate the merit of the proposed operation can be applied. Although much research
video processor design. effort [6] [10]-[12] has been made to address the
problem, there are often overheads and
To deal with the extremely high computational
performance bottlenecks when aligning the
complexity of video coding, one common approach
multiple data to feed into vector registers. Extra
is to exploit the data level parallelism (DLP) in the
memory loads and stores, unpacking, packing and
execution. As different from application specific
shuffling are often required that prevent SIMD
ASIC designs, a general purpose video processor
execution from achieving the peak performance.
should provide great flexibility for programmers
Besides, the memory mis-alignment, stride
while exploiting the parallelism in the execution.
 memory access, memory latency, random register “by”, “for”, “from”, “if”, “in”, “into”, “on”, “or”, “of”,
file access and branch mis-prediction also prevent “the”, “to”, “with”.
the processor from fetching data in a timely Author details must not show any professional title
fashion to achieve peak throughput [13]-[15]. (e.g. Professor), any academic title (e.g. Dr.) or any
membership of any professional organization.
To address the aforementioned problems, our To avoid confusion, the family name must be written
team has designed and implemented a new SIMD as the last part of each author name.
based video processor with architecture as shown Each affiliation must include, at the very least, the
in Fig. 1. Our video processor is a 5-stage pipeline name of the company and the name of the country where
multi-threaded multi-issue semi out-of-order the author is based (e.g. XXX Private Ltd, India).
superscalar processor. It supports a maximum of 4 3. Section Headings
No more than 3 levels of headings should be used.
threads of execution simultaneously. A maximum
Every word in a heading must be capitalized except for
of 4 instructions can be short minor words as listed in Section III-2.
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in 10pt bold font. For example, see heading “3. Section
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bits, the maximum block length in bits is mðq 1Þ and the
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symbol. RS codes are commonly expressed as RS(n, k, IV. FIGURES AND TABLES
m). The parity check matrix for an RS code is
constructed as shown in equation (1) where a is a Figures and tables must be centered in the columns.
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Fig.1. Process Design Gap (Figure shows drawn Vs VI. CONCLUSION (12, BOLD, SMALL CAPS)
printed gap increases as we move towards smaller device
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REFERENCES (12, BOLD, SMALL CAPS)
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[6]).
dny dy
f n ( x) n
 ....  f1 ( x )  f 0 ( x) y  h( x) (1)
[1] David Z. Pan, Senior Member, IEEE, Bei Yu, and Jhih-
dx dx
Rong Gao “Design for Manufacturing With Emerging
2. Abbreviations and Acronyms
Nanolithography” IEEE Transactions on Computer-
Define abbreviations and acronyms the first time they Aided Design of Integrated Circuits And Systems, Vol.
are used in the text, even after they have already been 32, No. 10, October 2013 (9, Regular)
defined in the abstract. Abbreviations such as SI, ac, and
[2] M. Lu, et al., “Novel customized manufacturable DFM
solutions,” Proc. SPIE Photo mask Technology 2012,
vol. 8522, pp. 852223, December 2012.
[3] Sergio Gomez and Francesc Moll. “Lithography aware
regular cell design based on a predictive technology
model.” J. Low Power Electronics, 6(4):1–14, 2010
[4] B. Le Gratiet, F. Sundermann, J. Massin, et al.,
“Improved CD control for 45-40 nm CMOS logic
patterning: anticipation for 32-28 nm”, In proceedings
of SPIE Vol. 7638,76380A (2010)
[5] Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin and
Cheng-Hong Tsai “DFM/DFY practices during physical
designs for timing, signal integrity, and power” 2007
IEEE conference.
[6] Wing Chiu Tam and Shawn Blanton “To DFM or Not to
DFM” IEEE Asia Pacific Conference on Circuits and
Systems, 2006.
[7] Raina Rajesh “What is DFM & DFY and Why Should I
Care?” INTERNATIONAL TEST CONFERENCE 2009
[8] Garg Manish, Kumar Aatish “Litho-driven Layouts for
Reducing Performance Variability” IEEE 2005
[9] Daehyun Jang, Naya Ha, Joo-Hyun Park, Seung-Weon
Paek “DFM Optimization of Standard Cells
Considering Random and Systematic Defect”
International SoC Design Conference 2008
[10] Sergio Gomez, Francesc Moll, Antonio Rubio “Design
Guidelines towards Compact Litho-Friendly Regular
cells” SPIE Photomask Technology 2012
[11] "Design for Manufacturability"
http://www.mentor.com/blogs/
[12] “Litho Friendly Design kit, a tool of DFM strategy”,
(http://www.eetimes.com/electrical-
engineers/education-training/tech-
papers/4130133/Litho-Friendly-Design-Kit-A-Tool-of-
DFM-Strategy).
[13] Y. Borodovsky, “Lithography 2009 overview of
opportunities,” in Proc.Semicon West, 2009.
[14] J. A. Torres, “Layout verification in the era of process
uncertainty: Target process variability bands versus
actual process variability bands,” in Proc. SPIE Design
Manufacturability through Design-Process Integration
II, vol. 6925. 2008, pp. 692509-1–692509-8.
[15] A. Carlson and T.-J. Liu, “Negative and iterated spacer
lithography processes for low variability and ultra dense
integration,” in Proc. SPIE Optical Microlithography
XXI, vol. 6924. 2008, pp. 69240B-1–69240B-9.

AUTHOR PROFILE (12, BOLD, SMALL CAPS)

<Author Photo>
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