BoardSim®

User Guide

Software Version 8.2

February 2012

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Table of Contents

Table of Contents

Chapter 1
Getting Started with Post-Layout Design Simulation - BoardSim. . . . . . . . . . . . . . . . . . . 47
Post-Layout Workflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Configuring the HyperLynx Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Transferring HyperLynx Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Specifying Device Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Opening BoardSim Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
About Field Solver Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Out-of-Memory Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
BoardSim Session Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Opening MultiBoard Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Simulations Overview - Post-Layout Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Measure Signal Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Verify Target Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Measure Timing for DDRx Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Verify SERDES Channel Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Verify PDN Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Measure PCB Heating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Verify Return Current Impedance for Single-Ended Signal Vias . . . . . . . . . . . . . . . . . . . 78
Export Models for Use in Other Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Resolve Post-Layout Signal-Integrity Problems with What If Experiments . . . . . . . . . . . 80
Resolve Post-Layout Power-Integrity Problems with What If Experiments . . . . . . . . . . . 83
SI QuickStart - BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
QuickStart - Power Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SI and PI Co-Simulation QuickStart - BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Chapter 2
BoardSim Tutorials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Batch Analysis of the Entire Board for Signal-Integrity and Crosstalk Problems . . . . . . . . 104
Predicting Crosstalk on a Clock Net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Advanced Via Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Visualizing the Geometric and Electrical Characteristics of a Via . . . . . . . . . . . . . . . . . . . . 136
Checking the Signal Quality of a Net Crossing Two Boards . . . . . . . . . . . . . . . . . . . . . . . . 139
Interactively Simulating the clk Net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Analyzing a Board Before Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
DC Voltage Drop Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Analyzing Crosstalk on the Virtex-4 Demo Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Locating Signal Quality and Timing Problems Using Batch Mode Simulation . . . . . . . . . . 183
BoardSim Tutorial Reference Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
MultiBoard Analysis of Signals Spanning Multiple Boards . . . . . . . . . . . . . . . . . . . . . . . 199
Electrical Versus Geometric Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Signal-Integrity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Crosstalk Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
GHz Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

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Library EASY.MOD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Eye Diagrams Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Multi-Bit Stimulus Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
BoardSim Crosstalk and Differential-Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Post-Layout Analysis: BoardSim and Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Simulating Multiple Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Adding IC Models to Your Existing Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
SPICE and Touchstone Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
MultiBoard Analysis with EBD Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Translating a Board into a BoardSim Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Chapter 3
Setting Up BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
About Reference-Designator Mapping in BoardSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Component Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
How BoardSim Identifies Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
One-Pin Components Automatically Treated as Test Points . . . . . . . . . . . . . . . . . . . . . . . 212
Helping BoardSim Recognize Power-Supply Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
BoardSim Hint - How to Simulate Unsupported Component Types. . . . . . . . . . . . . . . . . . . 213
Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Other Component Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
BoardSim Hint - How to Map a Reference-Designator Prefix to Multiple Component Types213

Chapter 4
Creating BoardSim Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
BoardSim Board Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Checklist for Translating Designs to BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Translators That Support Power-Integrity Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Translating Mentor Graphics Expedition and Board Station XE Designs . . . . . . . . . . . . . . 220
Translating PADS Layout Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Setting Resistor and Capacitor Values for BoardSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Preparing Accel EDA Designs for Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Defining Component Values and IC Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Preparing Cadence Allegro Designs for Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Updating Void Data in Static Metal Shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Preparing Mentor Graphics Board Station and Board Station RE Designs for Translation . 231
Adding Simulation Model Properties to Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Adding Assembly Variant Names to Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Board Station Layout Files Required by the Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Preparing Specctra DSN Designs for Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Preparing Valor ODB++ Designs for Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Preparing Visula-CADStar for Windows Designs for Translation . . . . . . . . . . . . . . . . . . . . 242
Creating an Alphanumeric Pin Name File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Preparing Zuken CR-3000 Designs for Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Preparing Zuken CR-5000 Board Designer Designs for Translation . . . . . . . . . . . . . . . . . . 246
Running the Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Translate File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

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Translator Options Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Chapter 5
Viewing BoardSim Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Board Viewer User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Identifying Stackup Layers Used to Implement Trace Segments and Metal Shapes . . . . . 257
Board Viewer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Summary of Board Viewer Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Zooming and Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Viewing All Nets Simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Removing All Highlighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Displaying Power-Supply Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Highlighting Decoupling and Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Highlighting Capacitor Mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Reviewing the Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Board Viewer Drawing Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Chapter 6
Setting Up Boards for Signal-Integrity Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Selecting Nets for SI Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Associated Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Selecting Nets by Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Selecting Nets by Reference Designator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Selecting Nets by Location in the Board Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Editing Power-Supply Net Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Why Power-Supply Nets Matter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
How BoardSim Identifies Power-Supply Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Undetected Power-Supply Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Editing Power-Supply Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Editing Trace Widths in BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Changing Trace Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
How to Change Trace Widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Examples of Changing Trace Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Reasons Why You Must Select Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Comparing Model-Selection Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
About Interactive and Automapping Model Assignment Methods . . . . . . . . . . . . . . . . . . 289
Interactive Method Enables Experimentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
An Example to Contrast Interactive and Automapping Methods. . . . . . . . . . . . . . . . . . . . 291
Tradeoffs Between REF and QPL Automapping Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Precedence Among Model and Value Selection Methods . . . . . . . . . . . . . . . . . . . . . . . . . 292
Troubleshooting Unexpected Model Selection Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Selecting Models and Values for Individual Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Selecting Models and Values for Entire Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
About REF and QPL Automapping Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Editing REF Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
QPL File Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Format of REF and QPL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Debugging Errors in REF and QPL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

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Temporarily Disabling REF and QPL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Interactively Editing Rs - Ls - Cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Editing Resistor - Capacitor - Inductor Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Value Applies to Whole Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Default Resistor - Capacitor - Inductor Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Choosing Resistor and Capacitor Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
About Networked-Component Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Default Package Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
How BoardSim Automatically Identifies Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Choosing a Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Editing Package Component Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Adding a User Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Reporting Board and Net Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Reporting Board Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Reporting Net Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Reporting Net Segment Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Reporting Design Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Chapter 7
Setting Up Designs for Power-Integrity Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Gathering Key Information About the PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Obtaining DC Current Properties for ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Design Setup Tasks for Power-Integrity Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Identifying Power-Supply Nets - BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Identifying Stackup Plane Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Setting Up Stackup Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Verifying Padstack Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Creating or Verifying Metal Shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Assigning Decoupling Capacitor Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Required Power-Integrity Model Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
About Power-Integrity Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
AC Current Sink Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
DC Current Sink Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
VRM Voltage Source Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Reference Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Series Components for Power-Supply Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Assigning Power-Integrity Models - BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Assigning Power-Integrity Models - LineSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

Chapter 8
Creating and Editing Stackups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
When to Use the Stackup Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Opening the Stackup Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
About Stackups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Effect of Stackups on Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Elements of a Stackup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Stackup Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
How BoardSim Reads Stackups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

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How LineSim Uses Stackups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

About the Default Stackup in LineSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
About the Stackup Editor User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Spreadsheet Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Picture Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Stackup Error Report Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Resizing and Rearranging the Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Undoing and Redoing Edits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Copying Data to Multiple Cells in the Same Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Selecting or Deselecting Layers in the Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Configuring the Custom View Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Reporting and Correcting Stackup Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Summary of Reported Stackup Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Stackup Error Reporting - Stackup Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Stackup Error Reporting - Stackup Verifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Editing Stackups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Editing Stackup Layer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Copying Stackup Parameters from Other Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Adding Layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Changing Layer Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Deleting Layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Changing a Layer From One Type to Another . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Total Board Thickness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
About Field Solver Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Table of Dielectric Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Viewing and Planning Impedances and DC Resistances. . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Viewing Characteristic Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Planning Characteristic Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Calculating DC Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Changing the Bulk Resistivity and Temperature Coefficient for a Layer . . . . . . . . . . . . . 392
Viewing Resistance and Attenuation Over a Frequency Range . . . . . . . . . . . . . . . . . . . . . 392
Setting Layer Display Options for the Board Viewer in BoardSim . . . . . . . . . . . . . . . . . . . 396
Setting Signal or Plane Layer Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Viewing Pours and Voids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
About Pour and Void Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Documenting Stackups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Printing Stackups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Copying a Stackup to the Clipboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Setting Measurement Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Setting Measurement Units from the Stackup Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Chapter 9
Creating and Editing IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
About the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
About the Main Areas in the Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Changing the Appearance of the Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Enabling Licensed Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Editing IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

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Opening the Visual IBIS Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

Opening an IBIS File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Finding an IBIS Keyword - Signal - Pin - Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Cutting Copying Pasting Replacing and Deleting Text . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Converting Tabs to Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Commenting or Uncommenting Selected Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Marking a Line with a Bookmark. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Going to a Line Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Selecting a Rectangular Block of Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Saving Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Printing an IBIS File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Removing Initial Delays from IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
About the Initial Delay Removal Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Time Correlation Across Multiple V-t Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Removing Initial Delays from Individual IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Removing Initial Delays from Multiple IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Examining and Editing V-I and V-t Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Viewing V-I or Waveform Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Displaying Combined Clamp and V-I Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Measuring Curves and Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Zooming Panning and Other Curve-Viewing Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Graphically Editing V-I or V-t Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Changing the Appearance of Curves or Legends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Printing Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Checking and Correcting IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Checking IBIS File Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Viewing the IBIS Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Correcting V-t and V-I Table Mismatches Automatically . . . . . . . . . . . . . . . . . . . . . . . . . 430
Verifying IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Checking an IBIS Model V-I or Waveform Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Identifying Common IBIS Model Problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Testing an IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Creating IBIS Models with the Easy IBIS Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
About the Easy IBIS Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Opening the Easy IBIS File Creation Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Creating a New Model or Opening an Existing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Easy IBIS Wizard Page Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Chapter 10
Assigning Models to Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Interactively Selecting IC Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Opening the Assign Models Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Assigning IC Models in Pins List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Selecting IBIS - MOD - PML Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Selecting SPICE and S-Parameter - Touchstone - Models. . . . . . . . . . . . . . . . . . . . . . . . . 471
Selecting IBIS Models Located Inside EBD Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Selecting Models for Programmable Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Tips for Selecting Models for Differential Pair Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

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Setting IC Buffer Direction-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Assigning Power Supplies to ICs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Assigning Power Supplies to Vcc and Vss Pins on ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
How LineSim Configures External Power-Supply Nets . . . . . . . . . . . . . . . . . . . . . . . . . . 479
How BoardSim Configures External Power-Supply Nets . . . . . . . . . . . . . . . . . . . . . . . . . 479
Importance of Power-Supply Pin Location in BoardSim EMC . . . . . . . . . . . . . . . . . . . . . 480
Copying Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Copying an Existing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Pasting to Another IC Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Pasting to All Other IC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Creating Multiple Receivers and One Driver of the Same Type . . . . . . . . . . . . . . . . . . . . 482
Removing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Removing Interactively-Assigned Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Cannot Interactively Remove Automapping Assignments. . . . . . . . . . . . . . . . . . . . . . . . . 483
Deactivating IC Components in Cell-Based Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Reference Information for Selecting Models Interactively . . . . . . . . . . . . . . . . . . . . . . . . . . 485
About the Assign Models Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Using the Port-Mapping Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
About the Select IC Model Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Default IC Model Direction and State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
If Second Pin is Not Visible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
About the MOD Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
TECH-MOD Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
GENERIC-MOD Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Searching for Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
About IC Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
How ICs are Modeled for Signal-Integrity Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
IC-Model Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Obtaining IC Models from Semiconductor Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
The MOD - Databook - Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
The PML - Package Model Library - Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
The IBIS Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
The EBD - Electrical Board Description - Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Editing IC Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Editing MOD IC Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Editing IBIS IC Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
How to Create a Custom IC Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Selecting and Creating Ferrite-Bead Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Selecting Ferrite-Bead Models in BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
About the Ferrite-Bead Models Supplied by Mentor Graphics . . . . . . . . . . . . . . . . . . . . . 527
Simulating Before a Ferrite-Bead Model is Chosen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
How Ferrite-Bead Models Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
Creating Your Own Ferrite-Bead Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Example of User-Defined Bead Model Library File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

Chapter 11
Simulating Signal Integrity with the Oscilloscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Preparing Designs for Interactive SI Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

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Minimum Simulation Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

Editing Lossy Transmission-Line Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Enabling SI Simulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Enabling Crosstalk Simulation in BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Enabling Crosstalk Simulation in LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Enabling Lossy Transmission-Line Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Enabling Via Modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Setting Up the Oscilloscope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Opening the Oscilloscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Setting Standard or Eye Diagram Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Setting Up Driver Stimulus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Setting IC Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Setting Oscilloscope Probes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
Viewing Waveforms and Eye Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Editing Eye Mask Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Running Interactive Signal-Integrity Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Running Native HyperLynx Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Running SPICE Simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
About Eye Diagram Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Running Standard Eye Diagram Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
Co-Simulation - Modeling Interactions Between Signal Vias and Transmission Planes. . 577
Measuring Waveforms and Eye Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Measuring Waveforms and Eye Diagrams Automatically . . . . . . . . . . . . . . . . . . . . . . . . . 579
About Automatic Measurements in the Oscilloscope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Measuring Waveforms and Eye Diagrams Manually. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Re-Simulating - Comparing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Saving and Loading Waveform Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Saving Waveform Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Loading Waveform Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
About Waveform Files in CSV Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Documenting Interactive Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Entering a Comment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Printing Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Copying Simulation Results to the Clipboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

Chapter 12
Simulating Signal Integrity with Sweeps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Sweep Simulation Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
Sweeping IBIS and MOD Models Uses Internal Supply Values . . . . . . . . . . . . . . . . . . . . 602
BoardSim Sweeps Do Not Support Electrical Crosstalk Thresholds . . . . . . . . . . . . . . . . . 602
Setting Up and Running Sweeps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
Procedure to Set Up and Run Sweep Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Copying Sweep Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Deleting Sweep Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Disabling Sweep Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Locking Sweep Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Stopping Sweep Simulations on an Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Highlighting Design Objects in LineSim Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

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Unrouted Trace Segment Sweeps in BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

Calculating and Managing the Number of Sweep Simulations . . . . . . . . . . . . . . . . . . . . . . . 607
Calculating the Number of Sweep Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Managing the Number of Sweep Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

Chapter 13
Simulating Signal Integrity with IBIS-AMI Channel Analysis . . . . . . . . . . . . . . . . . . . . . 611
IBIS-AMI Channel Analysis QuickStart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
IBIS-AMI Channel Analysis Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
IBIS-AMI Sweep Simulation Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

Chapter 14
Simulating Signal Integrity with FastEye Channel Analysis . . . . . . . . . . . . . . . . . . . . . . . 629
FastEye Channel Analysis QuickStart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
FastEye Channel Analysis Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
FastEye Channel Analysis Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Checking Channels for Linear and Time-Invariant Behavior. . . . . . . . . . . . . . . . . . . . . . . 642
Worst-Case Bit Patterns Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Model Channel Frequency Response with Complex-Pole Models . . . . . . . . . . . . . . . . . . 644
Bit Sequence for Automatic Channel Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
FastEye Diagram Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Measuring FastEye Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Zooming and Examining FastEye Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

Chapter 15
Simulating SI for Entire Boards or Multiple Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Batch Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Getting to Know Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
Quick Analysis and Detailed Simulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
Ways to Use Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Generic Batch Simulation Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Driver Logic State Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Preparing the Board for Batch Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Verifying BoardSim Recognizes All Power-Supply Nets . . . . . . . . . . . . . . . . . . . . . . . . . 656
Editing Crosstalk Threshold Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Assigning IC Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Enabling IC Driver Pins for Detailed Crosstalk Simulation. . . . . . . . . . . . . . . . . . . . . . . . 661
Running the Batch Simulation Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Viewing Batch SI Simulation Reports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Standard Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
CSV and XLS Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Differential Measurements in Batch Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
SDF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Audit File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Reference Information for Batch Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Batch Simulation Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Flight-Time Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Constraint Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

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Scope of Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715

Contents of Signal-Integrity Simulation Results Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Driver IC Behavior During Batch Crosstalk Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 718
High-Accuracy Signal-Integrity Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
About Importing Constraints from CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Miscellaneous Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Batch Simulation Wizard Dialog Box Help. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Editing Primary Batch Simulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Selecting Nets and Editing Constraints for Signal-Integrity Simulation . . . . . . . . . . . . . . 727
Selecting Nets and Editing Constraints for EMC Simulation. . . . . . . . . . . . . . . . . . . . . . . 730
Selecting Nets for Quick Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
Editing Driver and Receiver Options for Signal-Integrity Analysis. . . . . . . . . . . . . . . . . . 733
Editing Delay and Transmission-Line Options for Signal-Integrity Analysis . . . . . . . . . . 734
Editing Default IC Model Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
Editing Crosstalk Analysis Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Editing Quick Analysis Interconnect Statistics Options. . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Editing Shared Signal-Integrity and Crosstalk Analysis Options. . . . . . . . . . . . . . . . . . . . 741
Editing Terminator Wizard Reporting Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
Editing Batch Simulation Audit and Reporting Options . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Running Simulation and Showing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

Chapter 16
Simulating Multiple-Board Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
Getting Started with MultiBoard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
MultiBoard Project Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Unavailable Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Maximum Number of Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
Modeling Board-to-Board Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
Mated and Unmated Electrical Characteristic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
Nets are Associated by Interconnect Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
MultiBoard Project Wizard Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
About Board IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
Mapping a HYP File to a Board ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
Interconnection Mapping Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
Inserting New Board Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
Deleting Interconnected HYP Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
Inserting New Interconnection Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
Edit Box Tips for the MultiBoard Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
Creating or Editing MultiBoard Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
Dialog Box Help for MultiBoard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
Creating MultiBoard Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
Editing an Existing MultiBoard Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
Choosing Board Files for the MultiBoard Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
Defining Board-to-Board Interconnection Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
Defining Interconnect Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
Saving Session Edits for Multiple Board Instances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
Saving Changes for Each Instance or for a Selected Instance . . . . . . . . . . . . . . . . . . . . . . 769
Selecting a Board Instance to Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772

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Copying a Set of Interactive Changes to All Instances. . . . . . . . . . . . . . . . . . . . . . . . . . . . 772

Chapter 17
Simulating DDRx Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Preparing Designs for DDRx Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
DDRx Batch Simulation Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
Gathering Information About Your DDRx Memory Interface and Design . . . . . . . . . . . . 776
DDRx Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Setting Up HyperLynx for DDRx Simulation - Design Files and Models . . . . . . . . . . . . . 782
Creating Controller and DRAM Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
Adding Model Selector Keywords to IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
Verifying the Design Setup for DDRx Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
DDRx Background Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
Data Flow for DDRx Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
Mapping DDRx Interface Signals to Nets in the Design . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Pairing DDRx Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Supported IBIS Model Spec and Receiver Threshold Keywords. . . . . . . . . . . . . . . . . . . . 802
On-Die Termination - ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Derating DDR2 and DDR3 Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Physical Basis of DDR2 and DDR3 Slew-Rate Derating. . . . . . . . . . . . . . . . . . . . . . . . . . 813
Effects of Delay Ranges on Setup and Hold Measurements . . . . . . . . . . . . . . . . . . . . . . . 814
Write Leveling for DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
Round Robin for DDRx Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
About Measuring DDRx Signals with Eye Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
Running DDRx Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
Running DDRx Simulation for the First Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
Procedure to Run DDRx Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
Creating DDR3 Write-Leveling Delay Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
DDRx Batch Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
DDRx Results Spreadsheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
DDRx Waveform Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
DDR3 Write-Leveling Delay Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
DDRx Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
DDRx Audit Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
DDRx Batch-Mode Wizard Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
DDRx Wizard - Introduction Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
DDRx Wizard - Initialization Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
DDRx Wizard - Controller Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
DDRx Wizard - DRAMs Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
DDRx Wizard - PLLs and Registers Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
DDRx Wizard - IBIS Models Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
DDRx Wizard - Nets to Simulate Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
DDRx Wizard - DRAM Signals Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
DDRx Wizard - Data Strobes Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
DDRx Wizard - Data Nets Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
DDRx Wizard - Clock Nets Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
DDRx Wizard - Address and Command Nets Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
DDRx Wizard - Control Nets Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871

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DDRx Wizard - Disable Nets Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872

DDRx Wizard - IBIS Models Selectors Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
DDRx Wizard - ODT Models Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
DDRx Wizard - ODT Behavior Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
DDRx Wizard - Timing Models Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
DDRx Wizard - Write Leveling Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
DDRx Wizard - Stimulus and Crosstalk Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
DDRx Wizard - Simulation Options Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
DDRx Wizard - Report Options Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
DDRx Wizard - Simulate Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
DDRx Batch Mode - Run Simulation Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886

Chapter 18
Simulating EMC with the Spectrum Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
EMC Simulation Limitations and Special Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
About Radiation Prediction in LineSim EMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
EMC Simulation with Serpentined Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
Changing the EMC-Algorithm Short-Segment Threshold . . . . . . . . . . . . . . . . . . . . . . . . . 889
About LineSim EMC and BoardSim EMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
A Better Approach to EMC Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Radiated Emissions and Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
Preparing the Board or Schematic for EMC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
Setting Up the Spectrum Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Opening the Spectrum Analyzer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Choosing the Driver Waveform for EMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
How Duty Cycle Affects EMC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
Setting IC-Model Operating Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
Setting the Central Frequency and Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Choosing Regulatory Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
Defining User EMC Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
Setting Up the EMC Antenna or Current Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
Running EMC Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
Running an EMC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
EMC Simulation Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
Examining EMC Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
Setting the Vertical Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
Setting Auto Scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
Viewing Numeric EMC Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
Re-Simulating - Comparing EMC Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
Erasing a Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
Documenting EMC Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
Entering Spectrum-Analyzer Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
Printing EMC Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
Copying EMC Simulations to the Clipboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
Exporting EMC Simulation Data to Another Application - CSV File . . . . . . . . . . . . . . . . 920

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Chapter 19
Simulating Unrouted Nets with Manhattan Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
About Manhattan Routing in BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
How Manhattan Routing is Modeled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
Key Points From the Manhattan Routing Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
How Simulation Length for Manhattan Routing is Calculated . . . . . . . . . . . . . . . . . . . . . 923
Why Crosstalk is not Supported for Manhattan Routing . . . . . . . . . . . . . . . . . . . . . . . . . . 923
Creating Manhattan Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
Opening the Connect Nets with Manhattan Routing Dialog Box. . . . . . . . . . . . . . . . . . . . 924
Creating Manhattan Routing for All Unrouted Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
Creating Manhattan Routing for Selected Nets Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
Creating Manhattan Routing for Selected Nets and Associated Nets. . . . . . . . . . . . . . . . . 926
Saving and Restoring Session Edits for Manhattan Routing . . . . . . . . . . . . . . . . . . . . . . . . . 927
About Unrouting Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
Unrouting Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
Unrouting All Routed Nets - Except Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
Unrouting Selected Nets or Selected Nets and Associated Nets . . . . . . . . . . . . . . . . . . . . 929
Viewing Manhattan Routing and Unrouted Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
Reporting Manhattan Routing and Unrouting Changes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
Connect Nets with Manhattan Routing Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
The Nets to Connect with Manhattan Routing Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
The Routing Criteria Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Unroute Routed Nets Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934

Chapter 20
Terminating Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
About Quick Terminators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
When to Use Quick Terminators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
Quick Terminators and EMC Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
Quick Terminators and the Terminator Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
Adding a Quick Terminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
Where Quick Terminators Can be Placed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Types of Quick Terminators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Adding Quick Terminators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Editing Quick Terminator Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Single DC Resistor can be Pull-up or Pull-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Series or Differential Resistor Stub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Removing a Quick Terminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Removing the Effect of a Real Terminator to Try a Quick Terminator . . . . . . . . . . . . . . . . 942
Keeping a Record of Quick Terminators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Quick Terminators and the Design Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Selecting Second Pin for Differential Quick Terminator . . . . . . . . . . . . . . . . . . . . . . . . . . 943

Chapter 21
Optimizing Termination with the Terminator Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
About the Terminator Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
Terminated Versus Unterminated Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
Terminator Wizard Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946

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Terminator Wizard Unavailability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946

Differential Line-to-Line Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
No Placement Checks for Differential Terminators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
Some Combinations of Multiple Terminators Not Supported . . . . . . . . . . . . . . . . . . . . . . 948
Multiple Drivers Not Supported - Except for Differential IBIS Models . . . . . . . . . . . . . . 948
Ferrite Beads Not Supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
How the Wizard Recognizes Branched Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
Recognizing Terminator Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
Terminator Wizard Requires Driver IC Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Supported Termination Types and Net Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Running the Terminator Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
About Multiple Nets in LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
Terminator Wizard Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
Results Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
Component Values and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
Signal-Integrity Checks and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Pin-to-Pin Physical Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
Running the Terminator Wizard on the Entire Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961

Chapter 22
Simulating DC Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
DC Drop QuickStart - BoardSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
DC Drop QuickStart - LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
DC Drop Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
Current Flow For DC Drop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
DC Drop Conceptual Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
PowerScope Hides Some Shapes for DC Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
Design Factors Contributing to DC Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
Limitations of DC Drop Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
Data Flow for DC Drop - Interactive Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
Data Flow for DC Drop - Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
Running DC Drop Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
Running DC Drop Interactive Simulation - BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
DC Drop Analysis Display Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
Running DC Drop Interactive Simulation - LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
Example DC Drop Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
DC Drop Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
DC Drop Example Textual Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
DC Drop Example Voltage Drop Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
DC Drop Example Current Density Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010

Chapter 23
Analyzing Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
Decoupling Analysis QuickStart - BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
Decoupling Analysis QuickStart - LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
Running Decoupling Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
About the Decoupling Wizard Table of Contents Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
Data Flow for Decoupling Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027

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Circuit Topology for Lumped Decoupling Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029

Circuit Topology for Distributed Decoupling Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
Decoupling Capacitor Report Spreadsheets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031

Chapter 24
Simulating Plane Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
Plane Noise Simulation QuickStart - BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
Plane Noise Simulation QuickStart - LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
Running Plane-Noise Simulation - LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
Running Plane-Noise Simulation - BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Example Plane-Noise Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
Plane Noise Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
Plane Noise Example Voltage Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
Plane Noise Example Current Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048

Chapter 25
Analyzing Signal-Via Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
Data Flow for Signal-Via Bypass Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Running Signal-Via Bypass Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
About the Bypass Wizard Table of Contents Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054

Chapter 26
Viewing and Simulating Signal Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
Effects of Vias on Signal Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
Viewing Via Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
Steps to View Via Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
Coupled Vias in BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Warnings Reported by the Via Visualizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
What If Simulation Methods for Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Including or Excluding Vias During Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Via Electrical Modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
Physical Structure of Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
Electrical Modeling Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
Decomposing Vias Into Individual Physical Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
Building the Via Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063

Chapter 27
Viewing and Converting Touchstone and Fitted-Poles Models . . . . . . . . . . . . . . . . . . . . . 1065
About Touchstone and Fitted-Poles Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
S-Parameter Port Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
Mixed Mode S-Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
Opening Touchstone or Fitted-Poles Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
Checking and Fixing Passivity and Causality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
About Passivity and Causality Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
Automatically Reporting Passivity and Causality Errors . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
Manually Reporting Passivity and Causality Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
Fixing Passivity, Causality, and Symmetry Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
Graphically Viewing Model Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074

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Displaying Touchstone and Fitted-Poles Model Curves . . . . . . . . . . . . . . . . . . . . . . . . . . 1074

Zooming Panning and Other Curve-Examination Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
Documenting Touchstone and Fitted-Poles Model Curves . . . . . . . . . . . . . . . . . . . . . . . . 1079
Reporting Connectivity Among Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
Editing the Appearance of Curves and Legends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
Editing Curve Colors for the Current Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
Editing Default Curve Colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Editing Chart Appearance Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Checking S-Parameter Model Quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Displaying S-Parameter Models Graphically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Example of a Good or High-Quality S-Parameter Model . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Examples of Bad or Low-Quality S-Parameter Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
Cascading Multiple S-Parameter Models in Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
Algorithmic Complexity of S-Parameter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
High-Accuracy Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
Applying Cascading to Simulation of Certain IBIS-AMI Models . . . . . . . . . . . . . . . . . . . 1113
Converting and Fixing Touchstone and Fitted-Poles Models . . . . . . . . . . . . . . . . . . . . . . . . 1115
Simulating S-Parameter Models in the Time Domain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1116
Touchstone Viewer Dialog Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
Cascade 4-Port S-Parameter Models Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118
Combine to Standard Mode Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
Convert Mode Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
Convert Parameter Type Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
Convert to Fitted Poles Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
Convert to Touchstone Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Convert to Transfer Function Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
Reduce Number of Ports Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
Re-Normalize Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
TDR Impedance Plot Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
Time-Domain Response Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142

Chapter 28
Exporting Design and Model Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151
Exporting Nets to S-Parameter Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152
Reasons to Export S-Parameter Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153
About Exported S-Parameter Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153
Preparing the Design for Generating S-Parameter Models. . . . . . . . . . . . . . . . . . . . . . . . . 1153
Procedure to Export Nets to S-Parameter Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
Exporting Nets to SPICE Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157
Why the SPICE Writer is Needed to Model Interconnect in SPICE . . . . . . . . . . . . . . . . . 1157
Netlists Generated by the SPICE Writer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158
Compatibility with SPICE Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159
Generating the SPICE Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160
Exporting BoardSim Nets to LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161
Reasons to Use LineSim to Simulate Board Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162
Procedure to Export Nets to LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162
Naming Convention Change for Power-Supply Nets Exported to LineSim . . . . . . . . . . . 1164
Exporting BoardSim Topologies to HyperLynx 3D EM Designer . . . . . . . . . . . . . . . . . . . . 1165

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Evaluating Exported BoardSim Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167

Exporting BoardSim Boards to IBIS EBD Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
About EBD Models Generated by BoardSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
Preparing the Board for EBD Model Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
Generating an EBD Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
Exporting BoardSim Boards to ICX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
Limitations for Export to ICX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
Steps to Export the Board to ICX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
Optional Export Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
Exporting LineSim Schematics to BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174
Exporting Constraint Templates from LineSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
Exporting Nets from CES to LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
Importing Constraints from CES to BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
Exporting and Importing Stackups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
Layer Mapping for Importing Stackups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
Exporting Signal Vias to S-Parameter Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180
Running Export to Signal-Via Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
Files Written by Signal-Via Model Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
Exporting PDNs to S-Parameter Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
Running Export to PDN Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
Files Written by PDN Model Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
Gathering and Archiving Design Simulation Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
Files That Are Not Archived. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
About InfoZip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187

Chapter 29
About Crosstalk in LineSim and BoardSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189
Overview of LineSim and BoardSim Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189
About HyperLynx Crosstalk Analysis Options for LineSim and BoardSim . . . . . . . . . . . 1190
How the Crosstalk Analysis Option Works with the Base LineSim Product . . . . . . . . . . . 1193
How to Learn LineSim Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
What BoardSim Crosstalk Adds to the Base BoardSim Product . . . . . . . . . . . . . . . . . . . . 1195
Applications Made Possible by BoardSim Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
Recommended Way to Use BoardSim Crosstalk Features. . . . . . . . . . . . . . . . . . . . . . . . . 1198
Running the Field Solver in LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
Quick Summary of How to View Field-Solver Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
About the Field Solver in LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
How the Field Solver Works in LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
How the Field Solver Runs in LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
Viewing Detailed Field-Solver Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206
Viewing Electrical Field Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207
How Field Lines are Plotted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
Choosing a Propagation Mode to Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
Generating a Report of the Field Solver’s Numerical Results . . . . . . . . . . . . . . . . . . . . . . 1212
Contents of the Results Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
Running Interactive Crosstalk Simulations in BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
Enabling Interactive Post-Layout Crosstalk Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . 1219

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How BoardSim Crosstalk Finds Aggressor Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220

How Aggressor Nets are Displayed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
Setting IC Models for Crosstalk Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
Running Simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
How to Maximize Simulation Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233
Running the Field Solver in BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235
About BoardSim Crosstalk and the Field Solver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236
About the Field Solver in BoardSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236
How BoardSim Crosstalk Field Solver Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237
Viewing Coupling Regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239
Details of the Field-Solver Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
Generating a Report of the Field Solver Numerical Results. . . . . . . . . . . . . . . . . . . . . . . . 1251

Chapter 30
Back-Annotating Board Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
An Example Workflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254
Example Back Annotation Flow Using BoardSim and PADS Layout. . . . . . . . . . . . . . . . 1254
ASCII ECO Data File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
Dynamic Back Annotation Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
Dynamic Back Annotation Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
Setting Passive Component Attributes After Back Annotation. . . . . . . . . . . . . . . . . . . . . . . 1256
Quick Terminators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
Changed Passive Component Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
Preventing Redundant Quick Terminator Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
Generating Back Annotation Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
Setting Passive Component Attributes within the PCB CAD Program . . . . . . . . . . . . . . . 1259
Back Annotation Dialog Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
Generate ECO Back-Annotation File-Data Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . 1260
Options for New Terminators - Quick Terminators - Dialog Box . . . . . . . . . . . . . . . . . . . 1261
Save ECO Back-Annotation File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262

Chapter 31
Concepts and Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
Supported SI Models and Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264
File Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
FBD File Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
HyperLynx Timing Model Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270
HyperLynx DDRx Wizard Setup File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307
IBIS Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327
PAK File Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327
SLM File Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334
Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336
Converting SPICE Models to HyperLynx Databook Format . . . . . . . . . . . . . . . . . . . . . . . 1336
Creating IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342
Technical Background on Crosstalk and Differential Signaling . . . . . . . . . . . . . . . . . . . . . . 1348
About Crosstalk and its Causes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348
Forward and Backward Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1350
Electrical Parameters of Coupled Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357

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Propagation Modes-Single-Dielectric versus Layered-Dielectric Traces. . . . . . . . . . . . . . 1361

Differential Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
Terminating Coupled Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
About Transmission Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373
How Transmission Planes Propagate Energy to ICs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374
Jitter Distribution Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379
Gaussian Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379
Sinusoidal Deterministic Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382
Uniform Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383
Dual-Dirac Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
DjRj Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385
Jitter Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
Units for Gaussian and Uniform Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
Miscellaneous Reference Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
About Lossy Transmission-Line Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
About the Surface Roughness of Copper Foil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389
Measuring Delay and Overshoot on Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390
About Design Folder Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1391
Precedence Among Pad Sizes and Anti-Pad Clearances . . . . . . . . . . . . . . . . . . . . . . . . . . 1391
Precedence Among Anti-Segment Clearances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394
Overlapping Anti-Pads That Isolate Metal Shapes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395
Metal-Area and Padstack Usage for PI Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1398
Run HyperLynx with a Lower Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1409
Wizard Table of Contents Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410
HyperLynx Initialization File - BSW.INI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411

Appendix 32
Dialog Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413
Add/Edit Decoupling Capacitor(s) Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414
Add/Edit IC Power Pin(s) Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421
Add/Edit Via Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1428
Add/Edit VRM or DC to DC Converter Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430
Add Signal Via Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436
AMI File Assignment Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438
Archive Design Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440
Assign / Edit Capacitor Model Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442
Assign Decoupling-Capacitor Groups Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450
Assign Decoupling-Capacitor Models Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
Assign Power Integrity Models Dialog Box - IC Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
Assign Power Integrity Models Dialog Box - Supply-Net Resistors Tab . . . . . . . . . . . . . 1460
Assign Power Integrity Models Dialog Box - Supply-Net Inductors Tab . . . . . . . . . . . . . 1463
Assign Power Integrity Models Dialog Box - Other Supply-Net Components Tab. . . . . . 1466
Assign VRM Model Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470
Bathtub Chart Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474
Bypass Wizard - Check Capacitor Models Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
Bypass Wizard - Choose Easy / Custom Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
Bypass Wizard - Control Frequency Sweep Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480
Bypass Wizard - Customize Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483

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Bypass Wizard - Run Analysis Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485

Bypass Wizard - Select Signal Via Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
Bypass Wizard - Set the Target Impedance Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
Bypass Wizard - Start Analysis Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491
Channel Characterization Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493
Decoupling Mounting Scheme Editor Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
Decoupling Wizard - Check Capacitor Models Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
Decoupling Wizard - Choose a Type of Analysis Page . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508
Decoupling Wizard - Choose Easy / Custom Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
Decoupling Wizard - Control Frequency Sweep Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
Decoupling Wizard - Customize Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514
Decoupling Wizard - Run Analysis Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
Decoupling Wizard - Select IC Power Pins Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520
Decoupling Wizard - Select Nets for Analysis Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523
Decoupling Wizard - Set the Target Impedance Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525
Decoupling Wizard - Start Analysis Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1526
Define Constraint Template Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528
Define Constraint Template Dialog Box - Length/Delay Tab . . . . . . . . . . . . . . . . . . . . . . 1530
Define Constraint Template Dialog Box - Diff Pair Tab . . . . . . . . . . . . . . . . . . . . . . . . . . 1534
Define Constraint Template Dialog Box - Net Scheduling Tab . . . . . . . . . . . . . . . . . . . . . 1536
Define Constraint Template Dialog Box - Pin Sets Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . 1539
Differential Pair Net Suffixes Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
Differential Pairs Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543
Edit AC Power Pin Model Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547
Edit DC Power Pin Model Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551
Edit Reference Designator Mappings Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553
Edit Transmission Line Dialog Box - Add/Move to Coupling Region Tab . . . . . . . . . . . . 1555
Edit Transmission Line Dialog Box - Cables Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
Edit Transmission Line Dialog Box - Connectors Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
Edit Transmission Line Dialog Box - Edit Coupling Regions Tab . . . . . . . . . . . . . . . . . . 1562
Edit Transmission Line Dialog Box - Loss Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570
Edit Transmission Line Dialog Box - Transmission-Line Type Tab . . . . . . . . . . . . . . . . . 1573
Edit Transmission Line Dialog Box - Values Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579
eDxD/eExp View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584
Export to HyperLynx 3D EM Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588
FastEye Channel Analyzer - Add Jitter Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592
FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page. . . . . . . . . . . . . . . . . . . . . . . . 1596
Pre-Emphasis and DFE Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1599
Identifying Optimum Tap Weights. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1601
FastEye Channel Analyzer - Choose Fitting/Convolution Page. . . . . . . . . . . . . . . . . . . . . 1602
FastEye Channel Analyzer - Choose New/Saved Analysis Page . . . . . . . . . . . . . . . . . . . . 1604
FastEye Channel Analyzer - Define Stimulus Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
FastEye Channel Analyzer - FastEye/Worst-Case Analysis Page . . . . . . . . . . . . . . . . . . . 1612
FastEye Channel Analyzer - Introduction Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
FastEye Channel Analyzer - Set Up Channel Characterizations Page . . . . . . . . . . . . . . . . 1615
FastEye Channel Analyzer - Set Up Crosstalk Analysis Page . . . . . . . . . . . . . . . . . . . . . . 1624
FastEye Channel Analyzer - View Analysis Results Page . . . . . . . . . . . . . . . . . . . . . . . . . 1628
FastEye Step and Pulse Responses Dialog Box and PRBS Waveforms Dialog Box. . . . . 1632
Field Solver and Edit Transmission Line Dialog Box - Field Solver Tab . . . . . . . . . . . . . 1636

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Find Component Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640

Highlight Net Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
HyperLynx 3D EM Full-Wave EM Simulation Dialog Box . . . . . . . . . . . . . . . . . . . . . . . 1644
HyperLynx 3D EM Geometry Viewer - 3D Geometry View Dialog Box . . . . . . . . . . . . . 1646
HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View Dialog Box . . . . . 1649
HyperLynx 3D EM Project Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
HyperLynx File Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
HyperLynx IBIS-AMI Sweeps Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667
Organizing Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
HyperLynx PI PowerScope Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707
HyperLynx SI Eye Density Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
IBIS-AMI Channel Analyzer Wizard - Choose New/Saved Analysis Page. . . . . . . . . . . . 1729
IBIS-AMI Channel Analyzer Wizard - Configure AMI Models Page . . . . . . . . . . . . . . . . 1732
IBIS-AMI Channel Analyzer Wizard - Define AMI Stimulus Page . . . . . . . . . . . . . . . . . 1735
IBIS-AMI Channel Analyzer Wizard - Review Simulation Sweeps Page . . . . . . . . . . . . . 1739
IBIS-AMI Channel Analyzer Wizard - Set Up Channel Characterizations Page. . . . . . . . 1742
IBIS-AMI Channel Analyzer Wizard - Set Up Crosstalk Analysis Page. . . . . . . . . . . . . . 1749
IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model Settings Page . . . . . . . . . . . . 1753
IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page. . . . . . . . . . . . . . . . . 1756
IBIS AMI Parameter Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759
Illegal Single-Pin Components Found Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764
Installed Options Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1766
New HyperLynx 3D EM Project Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1769
PDN Model Extractor Wizard - Check Capacitor Models Page. . . . . . . . . . . . . . . . . . . . . 1770
PDN Model Extractor Wizard - Choose Easy / Custom Page . . . . . . . . . . . . . . . . . . . . . . 1771
PDN Model Extractor Wizard - Control Frequency Sweep Page. . . . . . . . . . . . . . . . . . . . 1772
PDN Model Extractor Wizard - Customize Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . 1775
PDN Model Extractor Wizard - Normalization Impedance Page. . . . . . . . . . . . . . . . . . . . 1777
PDN Model Extractor Wizard - Run Analysis Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778
PDN Model Extractor Wizard - Select IC Power Pins Page . . . . . . . . . . . . . . . . . . . . . . . 1780
PDN Model Extractor Wizard - Select Signal Vias Page . . . . . . . . . . . . . . . . . . . . . . . . . . 1783
PDN Model Extractor Wizard - Start Analysis Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1787
PDN Net Manager Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
Preferences Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1791
Reporter Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834
Restore Session Edits Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1838
Save Model As Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1841
Select Active Layers Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1842
Select Directories for IC-Model Files Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844
Select Directories for Stimulus Files Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847
Select Method of Simulating Vias Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1849
Set Directories Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854
Set Reference Nets Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1858
Setup Anti-Pads and Anti-Segments Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860
Specify Device Kit for Current Design Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
Specify DFE Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
Specify Pre-Emphasis Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
Statistical Contour Chart Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1868
Surface Roughness Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1871

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 Table of Contents

Sweeping Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1873

Synthesize DFE Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
Synthesize Pre-Emphasis Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
Synthesized DFE Weights Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
Synthesized Pre-Emphasis Weights Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1881
Target-Z Wizard - Finish Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883
Target-Z Wizard - Specify Peak Transient Current Page . . . . . . . . . . . . . . . . . . . . . . . . . . 1884
Target-Z Wizard - Specify Supply Voltage and Max Ripple Page . . . . . . . . . . . . . . . . . . 1886
Units Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888
Via Model Extractor Wizard - Check Capacitor Models Page. . . . . . . . . . . . . . . . . . . . . . 1889
Via Model Extractor Wizard - Choose Easy / Custom Page . . . . . . . . . . . . . . . . . . . . . . . 1890
Via Model Extractor Wizard - Control Frequency Sweep Page. . . . . . . . . . . . . . . . . . . . . 1891
Via Model Extractor Wizard - Customize Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
Via Model Extractor Wizard - Run Analysis Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
Via Model Extractor Wizard - Select Signal Via Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1898
Via Model Extractor Wizard - Set Model Type Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1902
Via Model Extractor Wizard - Start Analysis Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
Via Properties Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
View Options Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913
Viewing Filter Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1916

Appendix 36
What’s New . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1919

Appendix 37
Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925
File Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1926
Setup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1928
Edit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932
View Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1933
Models Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1934
Select Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1937
Simulate SI Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1938
Simulate PI Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1941
Simulate Thermal Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1943
Export Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944
Windows Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1947
Glossary
Third-Party Information
End-User License Agreement

24 BoardSim User Guide, v8.2

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List of Figures

List of Figures

Figure 1-1. Post-Layout Workflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 4-1. Translate File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 4-2. Translator Options Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 5-1. Example Board Viewer Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 5-2. Example Board Viewer Contents - MultiBoard Project . . . . . . . . . . . . . . . . . . . 257
Figure 5-3. Capacitor Mounting Before Highlighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 5-4. Capacitor Mounting After Highlighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 7-1. Electrical Schematic for an AC Current Sink Model . . . . . . . . . . . . . . . . . . . . . 349
Figure 7-2. Electrical Schematic for a DC Current Sink Model . . . . . . . . . . . . . . . . . . . . . . 350
Figure 7-3. Electrical Schematic for a VRM Voltage Source Model . . . . . . . . . . . . . . . . . . 350
Figure 7-4. Example Series Components for Power-Supply Nets. . . . . . . . . . . . . . . . . . . . . 351
Figure 8-1. GUI Overview for Stackup Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Figure 8-2. Example Stackup with Substrate and Solder Mask Dielectric Layers . . . . . . . . 373
Figure 9-1. GUI Overview for Visual IBIS Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Figure 9-2. Example of a Rectangular Selection in the Visual IBIS Editor . . . . . . . . . . . . . 412
Figure 9-3. Initial Delay Removal Algorithm Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Figure 9-4. Example Temporary Sub-Table Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Figure 9-5. Example Initial Merged V-t Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Figure 9-6. Endpoint DC Voltages do not Match Load-Line Analysis Prediction . . . . . . . . 430
Figure 9-7. Endpoint DC Voltages do Match Load-Line Analysis Prediction . . . . . . . . . . . 431
Figure 9-8. IBIS Model Error - Pullup Data with Wrong Sign . . . . . . . . . . . . . . . . . . . . . . . 434
Figure 9-9. Test Bench Configured to Collect Pulldown Data . . . . . . . . . . . . . . . . . . . . . . . 435
Figure 9-10. Test Bench Configured to Collect Pullup Data. . . . . . . . . . . . . . . . . . . . . . . . . 435
Figure 9-11. IBIS Model Error - Wrong Units for Y-Axis . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Figure 9-12. IBIS Model Error - Data with Noise Properties . . . . . . . . . . . . . . . . . . . . . . . . 438
Figure 9-13. Curves Showing Non-Monotonic Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Figure 9-14. IBIS Model Error - Spurious Datum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Figure 9-15. IBIS Model Error - Pin Information with the Wrong Data Order. . . . . . . . . . . 442
Figure 9-16. IBIS Model Error - Pulldown Data Not Passing Through the Origin. . . . . . . . 443
Figure 9-17. Plotting the V/I Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Figure 9-18. Plotting the Falling Waveform Load Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Figure 9-19. Plotting the Rising Waveform Load Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Figure 10-1. Series Bus Switch Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Figure 10-2. Location of SPICE Ports and Circuit Connections . . . . . . . . . . . . . . . . . . . . . . 498
Figure 11-1. ISI Absent - Identical Cycle-to-Cycle Shapes . . . . . . . . . . . . . . . . . . . . . . . . . 573
Figure 11-2. ISI Present - Different Cycle-to-Cycle Shapes . . . . . . . . . . . . . . . . . . . . . . . . . 574
Figure 11-3. ISI Sources - SERDES Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Figure 11-4. Example of Centered Eye Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Figure 11-5. Example of Eye Diagram Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
Figure 11-6. UI Origin for Eye Height Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
Figure 11-7. Example of a Waveform with Plateaus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

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 List of Figures

Figure 11-8. Example of a Waveform without Plateaus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

Figure 11-9. Example of Eye Aperture Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
Figure 11-10. Calculating High/Low Level Reference Voltages . . . . . . . . . . . . . . . . . . . . . 587
Figure 11-11. IBIS Sub-Keywords for Driver for Differential Flight Time Measurements . 590
Figure 11-12. Eye Width Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
Figure 11-13. Eye Height Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Figure 12-1. Swept Unrouted Trace Segment Location in Board Viewer. . . . . . . . . . . . . . . 607
Figure 13-1. IBIS-AMI Channel Analysis Task Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Figure 13-2. IBIS-AMI Channel Analysis Simulation Block Diagram - Main Flow . . . . . . 618
Figure 13-3. IBIS-AMI Channel Analysis Simulation Block Diagram - Crosstalk Flow . . . 624
Figure 14-1. FastEye Channel Analysis Task Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Figure 14-2. FastEye Channel Analysis Simulation Block Diagram - Main Flow . . . . . . . . 636
Figure 14-3. FastEye Channel Analysis Simulation Block Diagram - Crosstalk Flow. . . . . 640
Figure 14-4. Bit Sequence for Automatic Channel Characterization . . . . . . . . . . . . . . . . . . 645
Figure 14-5. Eye-Diagram Height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
Figure 14-6. Eye-Diagram Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
Figure 15-1. Single-Ended Flight-Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Figure 15-2. Differential Flight-Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Figure 15-3. System-Level Signal Passing from Pin A to Pin C . . . . . . . . . . . . . . . . . . . . . . 695
Figure 15-4. Test (datasheet) Single-Ended Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
Figure 15-5. Differential Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Figure 15-6. Interconnect (PCB) Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Figure 15-7. Tswitch_test and Tswitch_interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Figure 15-8. Effect of Tswitch_test and Tswitch_interconnect on System-level Delay
Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Figure 15-9. Measurements for Flight-time Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . 699
Figure 15-10. Max. Rise Static Rail Overshoot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Figure 15-11. Max. Fall Static Rail Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
Figure 15-12. Max. Rise Dyn. Rail Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
Figure 15-13. Max. Fall Dyn. Rail Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Figure 15-14. Max. Rise SI Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Figure 15-15. Max. Fall SI Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Figure 15-16. Min. Rise Ringback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
Figure 15-17. Min. Fall Ringback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Figure 15-18. Max. Rise/Fall Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
Figure 15-19. Min. Rise/Fall Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Figure 15-20. Max. Rise Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Figure 15-21. Secondary Dynamic Overshoot Scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
Figure 15-22. Aggressor and Victim Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
Figure 15-23. Generic Batch Simulation - Example Limits and Margins Columns . . . . . . . 744
Figure 16-1. Electrical Model of MultiBoard Interconnection Model . . . . . . . . . . . . . . . . . 750
Figure 16-2. Three Small Connectors Plugging Into One Large Connector . . . . . . . . . . . . . 756
Figure 16-3. Defining Connections Between Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
Figure 17-1. JEDEC Standard UDIMM — DDR, DDR2, DDR3 . . . . . . . . . . . . . . . . . . . . . 778
Figure 17-2. JEDEC Standard RDIMM — DDR and DDR2 . . . . . . . . . . . . . . . . . . . . . . . . 779

26 BoardSim User Guide, v8.2

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List of Figures

Figure 17-3. JEDEC Standard RDIMM — DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780

Figure 17-4. Non-JEDEC Standard — REGISTER Only . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Figure 17-5. Non-JEDEC Standard — PLL Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
Figure 17-6. tCKAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Figure 17-7. tCKCTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
Figure 17-8. tCKDQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
Figure 17-9. tDQSDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Figure 17-10. tDS and tDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
Figure 17-11. DDRx Address, Command, and Control Signal Timing at the Controller . . . 792
Figure 17-12. DDRx DQ/DM Signal Timing at the Controller During Write . . . . . . . . . . . 792
Figure 17-13. DDRx CK and DQS Timing at the Controller . . . . . . . . . . . . . . . . . . . . . . . . 793
Figure 17-14. DDRx DQ/DM Signal Timing at the Controller During Read . . . . . . . . . . . . 793
Figure 17-15. DDRx Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
Figure 17-16. Example ODT Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Figure 17-17. Setup and Hold Timing with Differential Clock or Strobe . . . . . . . . . . . . . . . 805
Figure 17-18. Setup and Hold Timing with Single-Ended Clock or Strobe . . . . . . . . . . . . . 806
Figure 17-19. Plotting Nominal Slew-Rate Lines for Setup Time Derating . . . . . . . . . . . . . 808
Figure 17-20. Plotting Nominal Slew-Rate Lines for Hold Time Derating . . . . . . . . . . . . . 809
Figure 17-21. Plotting Tangental Slew-Rate Lines for Setup Time Derating . . . . . . . . . . . . 810
Figure 17-22. Plotting Tangental Slew-Rate Lines for Hold Time Derating . . . . . . . . . . . . 811
Figure 17-23. Table Fragment from JEDEC Specification JESD79-2D . . . . . . . . . . . . . . . . 813
Figure 17-24. DDRx Slew-Rate Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
Figure 17-25. tDSQCK Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
Figure 17-26. DDR3 Fly-By Routing Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
Figure 17-27. Stimulus Offset is Calculated from Typical Delays . . . . . . . . . . . . . . . . . . . . 826
Figure 17-28. Selecting Spreadsheet Rows in the DDRx Wizard . . . . . . . . . . . . . . . . . . . . . 849
Figure 17-29. DDRx Batch Mode Wizard - Controller Page . . . . . . . . . . . . . . . . . . . . . . . . 853
Figure 17-30. Slot and Rank Landmarks for DDRx - Looking Down on DIMMs . . . . . . . . 855
Figure 17-31. DDRx Batch Mode Wizard - DRAMs Page . . . . . . . . . . . . . . . . . . . . . . . . . . 856
Figure 17-32. Slot and Rank Landmarks for DDRx - Stacked Dual-Die DRAM . . . . . . . . . 858
Figure 17-33. Specifying DRAM Locations for a Stacked Dual-Die DRAM. . . . . . . . . . . . 859
Figure 17-34. Default and User-Defined Speed Grade Assignments . . . . . . . . . . . . . . . . . . 876
Figure 22-1. DC Drop - BoardSim Task Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
Figure 22-2. DC Drop - LineSim Task Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
Figure 22-3. DC Drop Current Flow - Current Density. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
Figure 22-4. DC Drop Current Flow - Current Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
Figure 22-5. DC Drop Circuit - Simulate One Power-Supply Net . . . . . . . . . . . . . . . . . . . . 979
Figure 22-6. DC Drop Numerical Simulation Results - Simulate One Power-Supply Net. . 981
Figure 22-7. DC Drop Simulation Circuit - Simulate Selected and Reference Power-Supply Nets
982
Figure 22-8. DC Drop Circuit - Mixed Source/Sink Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
Figure 22-9. DC Drop Circuit - Other Via. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
Figure 22-10. PowerScope Hides Some Shapes for DC Drop. . . . . . . . . . . . . . . . . . . . . . . . 986
Figure 22-11. DC Current Flow Restriction - Narrow Trace Segments . . . . . . . . . . . . . . . . 988
Figure 22-12. DC Current Flow Restriction - Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988

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 List of Figures

Figure 22-13. DC Current Flow Restriction - BGA Antipads . . . . . . . . . . . . . . . . . . . . . . . . 989

Figure 22-14. DC Drop Data Flow - Interactive Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 991
Figure 22-15. DC Drop Data Flow - Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
Figure 22-16. Measuring DC Drop - Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
Figure 22-17. Measuring DC Drop - Reporter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
Figure 22-18. Measuring DC Drop - HyperLynx PI PowerScope 2-D . . . . . . . . . . . . . . . . . 1007
Figure 22-19. Measuring DC Drop - HyperLynx PI PowerScope 3-D Current Sink . . . . . . 1008
Figure 22-20. Measuring DC Drop - HyperLynx PI PowerScope 3-D Voltage Source . . . . 1009
Figure 22-21. Measuring Current Density - HyperLynx PI PowerScope 2-D . . . . . . . . . . . 1010
Figure 22-22. Measuring Current Density - HyperLynx PI PowerScope 3-D . . . . . . . . . . . 1011
Figure 23-1. Decoupling Analysis - BoardSim Task Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
Figure 23-2. Decoupling Analysis - LineSim Task Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
Figure 23-3. Decoupling Analysis Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
Figure 23-4. Lumped Decoupling Analysis - Circuit Topology . . . . . . . . . . . . . . . . . . . . . . 1030
Figure 23-5. Distributed Decoupling Analysis - Circuit Topology . . . . . . . . . . . . . . . . . . . . 1030
Figure 24-1. Plane Noise Simulation - BoardSim Task Flow . . . . . . . . . . . . . . . . . . . . . . . . 1039
Figure 24-2. Plane Noise SImulation - LineSim Task Flow . . . . . . . . . . . . . . . . . . . . . . . . . 1041
Figure 24-3. Plane Noise Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
Figure 24-4. Plane Noise Example Design - Zoomed In . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
Figure 24-5. Measuring Plane Voltage Noise - HyperLynx PI PowerScope 2-D . . . . . . . . . 1047
Figure 24-6. Measuring Plane Voltage Noise - HyperLynx PI PowerScope 3-D . . . . . . . . . 1048
Figure 24-7. Measuring Plane Surface and Capacitor Currents . . . . . . . . . . . . . . . . . . . . . . 1049
Figure 25-1. Bypass Analysis Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Figure 26-1. Example Physical Structure of a Through-Hole Via. . . . . . . . . . . . . . . . . . . . . 1060
Figure 26-2. Via Sections When Traces on Layers S1 and S4 Connect to Barrel. . . . . . . . . 1062
Figure 27-1. Recommended S-Parameter Port Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Figure 27-2. S-Parameter Port Numbering for Mixed Mode S-Parameter Models. . . . . . . . 1068
Figure 27-3. Mixed-mode S-Parameters for a 4 Port Model . . . . . . . . . . . . . . . . . . . . . . . . . 1069
Figure 27-4. Mixed Mode S-Parameter Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
Figure 27-5. Guideline with Two Line Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
Figure 27-6. Real and Imaginary Portions of the S11 Dependence. . . . . . . . . . . . . . . . . . . . 1084
Figure 27-7. Two Resonances with Sufficient Resolution-Moderate Zoom . . . . . . . . . . . . . 1085
Figure 27-8. Two Resonances with Sufficient Resolution-Extreme Zoom. . . . . . . . . . . . . . 1086
Figure 27-9. Proper Behavior of Real and Imaginary Parts of the Dependence . . . . . . . . . . 1087
Figure 27-10. Trajectory Plot with Clockwise Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Figure 27-11. Good Passivity Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
Figure 27-12. Insufficient Frequency Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
Figure 27-13. Overlaying Original and Post-Fit Dependencies of Previous Model . . . . . . . 1094
Figure 27-14. Non-passivity Between 25 GHz and 28 GHz for Previous Model . . . . . . . . . 1095
Figure 27-15. Comparison of Model Dependencies-Small Differences Exist . . . . . . . . . . . 1096
Figure 27-16. Insufficient Frequency Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
Figure 27-17. Trajectory Plot Showing a Chaotic Trajectory . . . . . . . . . . . . . . . . . . . . . . . . 1098
Figure 27-18. Results of Fitting Model from Previous Figure . . . . . . . . . . . . . . . . . . . . . . . 1099
Figure 27-19. Extreme Case of Under-Resolved Original Data . . . . . . . . . . . . . . . . . . . . . . 1100
Figure 27-20. Deviation of Fitted Dependence Near DC . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101

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List of Figures

Figure 27-21. Deviation of Fitted Dependence Near DC-More Severe . . . . . . . . . . . . . . . . 1102

Figure 27-22. Logarithmic Scale Shows Correct Asymptotic Behavior . . . . . . . . . . . . . . . . 1103
Figure 27-23. Inherent Non-Causality with Substantial Counterclockwise Rotation . . . . . . 1104
Figure 27-24. SERDES Channel Represented by a Cascaded Series of S-Parameter Models
1105
Figure 27-25. Interconnect Portion of SERDES Channel in a LineSim Schematic . . . . . . . 1105
Figure 27-26. Real and Imaginary Parts for Non-Cascaded and Undersampled Cascaded S-
Parameter Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
Figure 27-27. SPICE-Simulator AC-Sweep Interpolation of an Original S-Parameter Model -
Magnitude Plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108
Figure 27-28. SPICE-Simulator AC-Sweep Interpolation of an Original S-Parameter Model -
Real and Imaginary Plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
Figure 27-29. S-Parameter Cascading Work Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
Figure 27-30. Files to Cascade Spreadsheet - Example Contents . . . . . . . . . . . . . . . . . . . . . 1112
Figure 27-31. Cascade 4-Port S-Parameter Models Dialog Box . . . . . . . . . . . . . . . . . . . . . . 1118
Figure 27-32. Order of Models in Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
Figure 27-33. Combine to Standard Mode Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
Figure 27-34. Convert Mode Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
Figure 27-35. Convert Parameter Type Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
Figure 27-36. Convert to Fitted Poles Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
Figure 27-37. Convert to Touchstone Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Figure 27-38. Convert to Transfer Function Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
Figure 27-39. Reduce Number of Ports Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
Figure 27-40. Mapping Ports Between Original Model and Reduced-Port Model . . . . . . . . 1131
Figure 27-41. Re-Normalize Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
Figure 27-42. TDR Impedance Plot Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
Figure 27-43. Electrical Circuit Used for TDR Impedance Plots - Single-Ended. . . . . . . . . 1137
Figure 27-44. Electrical Circuit Used for TDR Impedance Plots - Mixed Mode Plot Type and
Differential Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
Figure 27-45. Electrical Circuit Used for TDR Impedance Plots - Mixed Mode Plot Type and
Common Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
Figure 27-46. Measure Delay Between Touchstone File Ports . . . . . . . . . . . . . . . . . . . . . . . 1138
Figure 27-47. Measure Stair Step Intervals - Single-Ended . . . . . . . . . . . . . . . . . . . . . . . . . 1139
Figure 27-48. Measure Stair Step Intervals - Differential . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
Figure 27-49. TDR Impedance Plots - Schematic for Extracted Touchstone Model . . . . . . 1141
Figure 27-50. Time-Domain Response Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
Figure 27-51. Parameter Spreadsheet in Touchstone Viewer . . . . . . . . . . . . . . . . . . . . . . . . 1142
Figure 27-52. Electrical Circuit Used for Time-Domain Reponses - S(a,b) . . . . . . . . . . . . . 1145
Figure 27-53. Electrical Circuit Used for Time-Domain Reponses - S(1,2) . . . . . . . . . . . . . 1146
Figure 27-54. Electrical Circuit Used for Time-Domain Reponses - Z(a,b) . . . . . . . . . . . . . 1146
Figure 27-55. Electrical Circuit Used for Time-Domain Reponses - Z(1,2) . . . . . . . . . . . . . 1146
Figure 27-56. Electrical Circuit Used for Time-Domain Reponses - Y(a,b). . . . . . . . . . . . . 1147
Figure 27-57. Electrical Circuit Used for Time-Domain Reponses - Y(1,2). . . . . . . . . . . . . 1147
Figure 27-58. Stimulus - Dirac Impulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
Figure 27-59. Stimulus - Unit Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148

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 List of Figures

Figure 27-60. Stimulus - Rectangular . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148

Figure 27-61. Stimulus - Trapezoidal Pulse, Rise Time is Less Than Pulse Time . . . . . . . . 1149
Figure 27-62. Stimulus - Trapezoidal Pulse, Rise Time is More Than Pulse Time . . . . . . . 1149
Figure 28-1. Mapping Spreadsheet Ports to Exported PDN Model Ports . . . . . . . . . . . . . . . 1186
Figure 29-1. Contents of Crosstalk Option in LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
Figure 29-2. Contents of Crosstalk Option in BoardSim. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
Figure 29-3. Example of a Field-Line Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
Figure 29-4. Example of Table Correlating Transmission Lines and Trace Indices . . . . . . . 1214
Figure 29-5. Aggressor and Victim Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221
Figure 29-6. Coupling Region Dialog Box Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
Figure 29-7. Example of Table Correlating Nets and Trace Indices . . . . . . . . . . . . . . . . . . . 1246
Figure 31-1. Slew Rate Derating Table - Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
Figure 31-2. Slew Rate Derating Table - Controller Wizard Page . . . . . . . . . . . . . . . . . . . . 1275
Figure 31-3. $fullskew Timing Check Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
Figure 31-4. Controller Parameters tCKAC and tCKCTL . . . . . . . . . . . . . . . . . . . . . . . . . . 1294
Figure 31-5. Controller Parameter tCKDQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294
Figure 31-6. Controller Parameter tDQSDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
Figure 31-7. Controller Parameter tDQDQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
Figure 31-8. Controller Parameters tDS and tDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296
Figure 31-9. DRAM Parameters tIS and tIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
Figure 31-10. DRAM Parameters tDQSS, tDSS, tDSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
Figure 31-11. DRAM Parameters tDS and tDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300
Figure 31-12. DRAM Parameter tDQSCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300
Figure 31-13. DRAM Parameter tDQSQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300
Figure 31-14. PLL Parameter tDPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
Figure 31-15. PLL Parameter tJIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
Figure 31-16. PLL Parameter tSKO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
Figure 31-17. Register Parameters tDS and tDH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
Figure 31-18. Register Parameter tCKQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
Figure 31-19. Connecting the Test Transmission Line to the Driver Model. . . . . . . . . . . . . 1339
Figure 31-20. Measuring Vstep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341
Figure 31-21. Aggressor and Victim Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349
Figure 31-22. Speedboat Analogy for Crosstalk Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
Figure 31-23. Forward and Backward Crosstalk Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
Figure 31-24. Capacitive Portion of Forward Crosstalk Signal; Same Polarity as Aggressor
Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352
Figure 31-25. Inductive Portion of Forward Crosstalk Signal; Opposite Polarity of Aggressor
Signal and Capacitive Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353
Figure 31-26. Shape of Backward Crosstalk Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
Figure 31-27. Length of Backward Crosstalk Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
Figure 31-28. Backward Crosstalk Reflecting Off of Victim Driver IC and Inverting. . . . . 1356
Figure 31-29. Classic Crosstalk Waveform at Victim-Trace Receiver IC . . . . . . . . . . . . . . 1357
Figure 31-30. Single-Dielectric Versus Layered-Dielectric Cross Sections . . . . . . . . . . . . . 1361
Figure 31-31. Two Coupled Microstrip Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362
Figure 31-32. Two Traces in an Asymmetric Cross Section . . . . . . . . . . . . . . . . . . . . . . . . . 1363

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List of Figures

Figure 31-33. TDR Waveforms Illustrating Stair Step Effect . . . . . . . . . . . . . . . . . . . . . . . . 1365

Figure 31-34. A Symmetric Microstrip Trace Pair, Driven with a Mixture of Differential and
Common Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367
Figure 31-35. Same Cross Section as Previous Figure, but Driven Differentially . . . . . . . . 1368
Figure 31-36. Differential and Common-Mode Terminators . . . . . . . . . . . . . . . . . . . . . . . . 1369
Figure 31-37. Cross Section with Three Coupled Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
Figure 31-38. Transmission-Plane Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373
Figure 31-39. Transmission-Line Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374
Figure 31-40. Transmission-Line Electromagnetic Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
Figure 31-41. Transmission Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376
Figure 31-42. Electromagnetic Wave Propagating in a Transmission Line . . . . . . . . . . . . . 1376
Figure 31-43. Electromagnetic Wave Propagating in a Transmission Plane. . . . . . . . . . . . . 1377
Figure 31-44. Example Containing Three Transmission Planes . . . . . . . . . . . . . . . . . . . . . . 1378
Figure 31-45. Gaussian Probability Density Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380
Figure 31-46. Timing Offset Over Sinusoidal Jitter Period - 0 Degrees Initial Phase . . . . . 1382
Figure 31-47. Timing Offset Over Sinusoidal Jitter Period - 90 Degrees Initial Phase . . . . 1383
Figure 31-48. Sinusoidal Jitter - Histogram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383
Figure 31-49. Uniform Jitter Histogram - Mean = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Figure 31-50. Uniform Jitter Histogram - Mean > 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Figure 31-51. Dual-Dirac Jitter Histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385
Figure 31-52. DjRj Jitter Histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385
Figure 31-53. Surface Roughness Example - Electrodeposited Copper Foil . . . . . . . . . . . . 1389
Figure 31-54. Surface Roughness Example - Rolled Copper Foil. . . . . . . . . . . . . . . . . . . . . 1389
Figure 31-55. Signal Integrity Overshoot and Pin Delay on Single-Ended Waveforms . . . . 1391
Figure 31-56. Overlapping Anti-Pads That Isolate Metal Shapes . . . . . . . . . . . . . . . . . . . . . 1396
Figure 31-57. Partial Via - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402
Figure 31-58. Partial Via - Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403
Figure 31-59. Partial Via - Side View and Removed Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405
Figure 31-60. Via Located in Gap Between Two Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
Figure 31-61. Run HyperLynx with a Lower Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410
Figure 31-62. Wizard Table of Contents Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
Figure 32-1. Add/Edit Decoupling Capacitor(s) Dialog Box - Place = Single . . . . . . . . . . . 1414
Figure 32-2. Add/Edit Decoupling Capacitor(s) Dialog Box - Place = Array . . . . . . . . . . . 1417
Figure 32-3. Add/Edit IC Power Pin(s) Dialog Box - Place = Single . . . . . . . . . . . . . . . . . . 1421
Figure 32-4. Add/Edit IC Power Pin(s) Dialog Box - Place = Array . . . . . . . . . . . . . . . . . . 1424
Figure 32-5. Add/Edit Via Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1428
Figure 32-6. Add/Edit VRM or DC to DC Converter Dialog Box . . . . . . . . . . . . . . . . . . . . 1431
Figure 32-7. Add Signal Via Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436
Figure 32-8. AMI File Assignment Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438
Figure 32-9. Archive Design Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440
Figure 32-10. Assign / Edit Capacitor Model Dialog Box - Simple C-L-R . . . . . . . . . . . . . 1443
Figure 32-11. Assign / Edit Capacitor Model Dialog Box - SPICE . . . . . . . . . . . . . . . . . . . 1444
Figure 32-12. Assign / Edit Capacitor Model Dialog Box - Touchstone . . . . . . . . . . . . . . . 1445
Figure 32-13. Capacitor Resonant Frequency Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449
Figure 32-14. Measurement Setup for Series Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449

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Figure 32-15. Measurement Setup for Shunt Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449

Figure 32-16. Assign Decoupling-Capacitor Groups Dialog Box. . . . . . . . . . . . . . . . . . . . . 1450
Figure 32-17. Assign Decoupling-Capacitor Models Dialog Box. . . . . . . . . . . . . . . . . . . . . 1453
Figure 32-18. Assign Power Integrity Models Dialog Box — IC Tab Contents. . . . . . . . . . 1457
Figure 32-19. Assign Power Integrity Models Dialog Box — Supply-Net Resistors Tab . . 1461
Figure 32-20. Assign Power Integrity Models Dialog Box — Supply-Net Inductors Tab . . 1464
Figure 32-21. Assign Power Integrity Models Dialog Box — Other Supply-Net Components Tab
1467
Figure 32-22. Assign VRM Model Dialog Box - Simple . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470
Figure 32-23. Assign VRM Model Dialog Box - Advanced . . . . . . . . . . . . . . . . . . . . . . . . . 1471
Figure 32-24. Bathtub Chart Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475
Figure 32-25. Bypass Wizard - Choose Easy / Custom Page . . . . . . . . . . . . . . . . . . . . . . . . 1479
Figure 32-26. Bypass Wizard - Control Frequency Sweep Page. . . . . . . . . . . . . . . . . . . . . . 1480
Figure 32-27. Bypass Wizard - Customize Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
Figure 32-28. Bypass Wizard - Run Analysis Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485
Figure 32-29. Bypass Wizard - Select Signal Via Page - LineSim . . . . . . . . . . . . . . . . . . . . 1487
Figure 32-30. Bypass Wizard - Select Signal Via Page - BoardSim . . . . . . . . . . . . . . . . . . . 1488
Figure 32-31. Bypass Wizard - Set the Target Impedance Page . . . . . . . . . . . . . . . . . . . . . . 1490
Figure 32-32. Bypass Wizard - Start Analysis Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491
Figure 32-33. Channel Characterization Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494
Figure 32-34. Pulse and Step Response Waveforms - Zoomed In . . . . . . . . . . . . . . . . . . . . 1501
Figure 32-35. Step Response Waveform - Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503
Figure 32-36. Pulse Response Waveform - Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503
Figure 32-37. Decoupling Mounting Scheme Editor Dialog Box . . . . . . . . . . . . . . . . . . . . . 1505
Figure 32-38. Decoupling Wizard - Choose a Type of Analysis Page . . . . . . . . . . . . . . . . . 1508
Figure 32-39. Decoupling Wizard - Choose Easy / Custom Page. . . . . . . . . . . . . . . . . . . . . 1510
Figure 32-40. Decoupling Wizard - Control Frequency Sweep Page . . . . . . . . . . . . . . . . . . 1511
Figure 32-41. Flat and Non-Resonant Region of an Impedance Profile . . . . . . . . . . . . . . . . 1513
Figure 32-42. Decoupling Wizard - Customize Settings Page - Lumped Analysis. . . . . . . . 1514
Figure 32-43. Decoupling Wizard - Customize Settings Page - Distributed Analysis . . . . . 1515
Figure 32-44. Decoupling Wizard - Run Analysis Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
Figure 32-45. Decoupling Wizard - Select IC Power Pins Page - LineSim . . . . . . . . . . . . . 1520
Figure 32-46. Decoupling Wizard - Select IC Power Pins Page - BoardSim . . . . . . . . . . . . 1521
Figure 32-47. Decoupling Wizard - Select Nets for Analysis Page . . . . . . . . . . . . . . . . . . . 1523
Figure 32-48. Decoupling Wizard - Set the Target Impedance Page . . . . . . . . . . . . . . . . . . 1525
Figure 32-49. Decoupling Wizard - Start Analysis Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1526
Figure 32-50. Define Constraint Template Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528
Figure 32-51. Define Constraint Templates Dialog Box - Length/Delay Tab . . . . . . . . . . . 1530
Figure 32-52. Define Constraint Templates Dialog Box - Diff Pair Tab . . . . . . . . . . . . . . . 1534
Figure 32-53. Define Constraint Templates Dialog Box - Net Scheduling Tab . . . . . . . . . . 1536
Figure 32-54. Virtual Pin Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539
Figure 32-55. Define Constraint Template Dialog Box - Pin Sets Tab . . . . . . . . . . . . . . . . . 1539
Figure 32-56. Differential Pair Net Suffixes Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
Figure 32-57. Differential Pairs Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544
Figure 33-1. Edit AC Power Pin Model Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547

32 BoardSim User Guide, v8.2

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List of Figures

Figure 33-2. Edit DC Power Pin Model Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551

Figure 33-3. Edit Reference Designator Mappings Dialog Box . . . . . . . . . . . . . . . . . . . . . . 1553
Figure 33-4. Edit Transmission Line Dialog Box - Add/Move to Coupling Region Tab . . . 1555
Figure 33-5. Edit Transmission Line Dialog Box - Cables Tab . . . . . . . . . . . . . . . . . . . . . . 1557
Figure 33-6. Edit Transmission Line Dialog Box - Connectors Tab. . . . . . . . . . . . . . . . . . . 1559
Figure 33-7. Edit Transmission Line Dialog Box - Edit Coupling Regions Tab . . . . . . . . . 1563
Figure 33-8. Example Coupling Region Tree List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564
Figure 33-9. Moving All Traces on the Lower Signal Layer to the Right. . . . . . . . . . . . . . . 1569
Figure 33-10. Edit Transmission Line Dialog Box - Loss Tab . . . . . . . . . . . . . . . . . . . . . . . 1570
Figure 33-11. Edit Transmission Line Dialog Box - Transmission-Line Type Tab . . . . . . . 1574
Figure 33-12. Values Tab - Uncoupled Stackup Transmission Lines . . . . . . . . . . . . . . . . . . 1580
Figure 33-13. Values Tab - Cross Section and Wire Over Ground Transmission Lines. . . . 1582
Figure 33-14. eDxD/eExp View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585
Figure 33-15. Export to HyperLynx 3D EM Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589
Figure 33-16. FastEye Channel Analyzer - Add Jitter Page . . . . . . . . . . . . . . . . . . . . . . . . . 1593
Figure 33-17. FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page . . . . . . . . . . . . . . 1597
Figure 33-18. FastEye Pre-Emphasis Filter - Feed-Forward . . . . . . . . . . . . . . . . . . . . . . . . . 1600
Figure 33-19. FastEye DFE Filter - Feed-Backward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1600
Figure 33-20. FastEye Channel Analyzer - Choose Fitting/Convolution Page . . . . . . . . . . . 1602
Figure 33-21. FastEye Channel Analyzer - Choose New/Saved Analysis Page . . . . . . . . . . 1605
Figure 33-22. FastEye Channel Analyzer - Define Stimulus Page - Worst Case . . . . . . . . . 1607
Figure 33-23. FastEye Channel Analyzer - Define Stimulus Page - PRBS. . . . . . . . . . . . . . 1607
Figure 33-24. FastEye Channel Analyzer - Define Stimulus Page - 8B/10B . . . . . . . . . . . . 1608
Figure 33-25. FastEye Channel Analyzer - Define Stimulus Page - Custom . . . . . . . . . . . . 1608
Figure 33-26. Checks Per UI - 11 Sampling Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
Figure 33-27. FastEye Channel Analyzer - FastEye/Worst-case Analysis Page. . . . . . . . . . 1612
Figure 33-28. FastEye Channel Analyzer - Introduction Page . . . . . . . . . . . . . . . . . . . . . . . 1614
Figure 33-29. FastEye Channel Analyzer - Set Up Channel Characterizations Page . . . . . . 1615
Figure 33-30. PCB Measurement Set Up to Measure Crosstalk . . . . . . . . . . . . . . . . . . . . . . 1623
Figure 33-31. FastEye Channel Analyzer - Set Up Crosstalk Analysis Page . . . . . . . . . . . . 1624
Figure 33-32. FastEye Channel Analyzer - View Analysis Results Page . . . . . . . . . . . . . . . 1628
Figure 33-33. Example FastEye Channel Analysis Contour . . . . . . . . . . . . . . . . . . . . . . . . . 1631
Figure 33-34. FastEye Step and Pulse Responses Dialog Box . . . . . . . . . . . . . . . . . . . . . . . 1632
Figure 33-35. PRBS Waveforms Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
Figure 33-36. Field Solver Dialog Box / Edit Transmission Line Dialog Box - Field Solver Tab
1637
Figure 33-37. Find Component Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
Figure 33-38. Highlight Net Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
Figure 33-39. Appearance of Highlighted Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643
Figure 33-40. HyperLynx 3D EM Full-Wave EM Simulation Dialog Box . . . . . . . . . . . . . 1644
Figure 33-41. HyperLynx 3D EM Geometry Viewer - 3D Geometry View Dialog Box . . . 1646
Figure 33-42. HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View Dialog Box
1650
Figure 33-43. HyperLynx 3D EM Project Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
Figure 33-44. Signal Via Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663

BoardSim User Guide, v8.2 33

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 List of Figures

Figure 33-45. Geometry Box for 3-D Electromagnetic Simulation . . . . . . . . . . . . . . . . . . . 1664

Figure 33-46. Connected Trace Angle for Differential Pairs . . . . . . . . . . . . . . . . . . . . . . . . 1665
Figure 33-47. HyperLynx File Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
Figure 33-48. HyperLynx IBIS-AMI Sweeps Viewer GUI Overview . . . . . . . . . . . . . . . . . 1668
Figure 33-49. HyperLynx IBIS-AMI Sweeps Viewer Cross Linking. . . . . . . . . . . . . . . . . . 1669
Figure 33-50. HyperLynx IBIS-AMI Sweeps Viewer - Toolbar - Plot View . . . . . . . . . . . . 1676
Figure 33-51. Plot View Pane - Eye Density Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678
Figure 33-52. Plot View Pane - BER Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679
Figure 33-53. HyperLynx IBIS-AMI Sweeps Viewer Spreadsheet . . . . . . . . . . . . . . . . . . . 1681
Figure 33-54. Highest BER is 5.97e-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687
Figure 33-55. Highest BER is Very Low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687
Figure 33-56. Plot View Options Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689
Figure 33-57. Spreadsheet Options Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
Figure 33-58. Sliders Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695
Figure 33-59. Pane Auto Hide Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701
Figure 33-60. Pane Dragging Attachment Landmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703
Figure 33-61. Drag Pane to Make Tabbed Item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
Figure 33-62. Drag Pane to Make New Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
Figure 33-63. Drag Pane to Attach to Other Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706
Figure 33-64. HyperLynx PI PowerScope Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . 1708
Figure 33-65. Plane Noise Tabs - HyperLynx PI PowerScope . . . . . . . . . . . . . . . . . . . . . . . 1709
Figure 33-66. DC Drop Tabs - HyperLynx PI PowerScope . . . . . . . . . . . . . . . . . . . . . . . . . 1709
Figure 33-67. HyperLynx PI PowerScope Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710
Figure 33-68. Hidden Numerical DC Drop Maximum Value . . . . . . . . . . . . . . . . . . . . . . . . 1712
Figure 33-69. Legend with Last and Previous Columns - HyperLynx PI PowerScope Contents
1713
Figure 33-70. HyperLynx PI PowerScope Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
Figure 33-71. HyperLynx SI Eye Density Viewer - Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
Figure 33-72. HyperLynx SI Eye Density Viewer - Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 1722
Figure 33-73. HyperLynx SI Eye Density Viewer Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . 1723
Figure 33-74. HyperLynx SI Eye Density Viewer Controls . . . . . . . . . . . . . . . . . . . . . . . . . 1725
Figure 33-75. IBIS-AMI Channel Analyzer Wizard - Choose New/Saved Analysis Page. . 1730
Figure 33-76. IBIS-AMI Channel Analyzer Wizard - Configure AMI Models Page . . . . . . 1732
Figure 33-77. IBIS-AMI Channel Analyzer Wizard - Define AMI Stimulus Page . . . . . . . 1735
Figure 33-78. IBIS-AMI Channel Analyzer Wizard - Review Simulation Sweeps Page . . . 1739
Figure 33-79. IBIS-AMI Channel Analyzer - Set Up Channel Characterizations Page . . . . 1742
Figure 33-80. IBIS-AMI Channel Analyzer Wizard - Set Up Crosstalk Analysis Page . . . . 1749
Figure 33-81. IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model Settings Page . . 1753
Figure 33-82. IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page. . . . . . . 1756
Figure 33-83. IBIS AMI Parameter Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759
Figure 33-84. Units for Jitter Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762
Figure 33-85. Illegal Single-Pin Components Found Dialog Box. . . . . . . . . . . . . . . . . . . . . 1764
Figure 33-86. Installed Options Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1766
Figure 34-1. New HyperLynx 3D EM Project Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . 1769
Figure 34-2. PDN Model Extractor Wizard - Choose Easy / Custom Page . . . . . . . . . . . . . 1771

34 BoardSim User Guide, v8.2

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List of Figures

Figure 34-3. PDN Model Extractor Wizard - Control Frequency Sweep Page. . . . . . . . . . . 1772
Figure 34-4. PDN Model Extractor Wizard - Customize Settings Page . . . . . . . . . . . . . . . . 1775
Figure 34-5. PDN Model Extractor Wizard - Normalization Impedance Page. . . . . . . . . . . 1777
Figure 34-6. PDN Model Extractor Wizard - Run Analysis Page. . . . . . . . . . . . . . . . . . . . . 1778
Figure 34-7. PDN Model Extractor Wizard - Select IC Power Pins Page - LineSim . . . . . . 1780
Figure 34-8. PDN Model Extractor Wizard - Select IC Power Pins Page -BoardSim . . . . . 1781
Figure 34-9. PDN Model Extractor Wizard - Select Signal Vias Page - LineSim . . . . . . . . 1783
Figure 34-10. PDN Model Extractor Wizard - Select Signal Vias Page - BoardSim . . . . . . 1784
Figure 34-11. PDN Model Extractor Wizard - Start Analysis Page . . . . . . . . . . . . . . . . . . . 1787
Figure 34-12. PDN Net Manager Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
Figure 34-13. Preferences Dialog Box - Advanced Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1793
Figure 34-14. CURVE Subrecord - Distance Between Center and End Points. . . . . . . . . . . 1799
Figure 34-15. Preferences Dialog Box - Appearance Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . 1801
Figure 34-16. Preferences Dialog Box - BoardSim Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
Figure 34-17. Preferences Dialog Box - Circuit Simulators Tab. . . . . . . . . . . . . . . . . . . . . . 1809
Figure 34-18. Preferences Dialog Box - Default Padstack Tab. . . . . . . . . . . . . . . . . . . . . . . 1813
Figure 34-19. Preferences Dialog Box - Default Stackup Tab . . . . . . . . . . . . . . . . . . . . . . . 1816
Figure 34-20. Preferences Dialog Box - General Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1818
Figure 34-21. Preferences Dialog Box - LineSim Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822
Figure 34-22. Preferences Dialog Box - Oscilloscope Tab . . . . . . . . . . . . . . . . . . . . . . . . . . 1824
Figure 34-23. Preferences Dialog Box - Power Integrity Tab . . . . . . . . . . . . . . . . . . . . . . . . 1829
Figure 34-24. Reporter Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835
Figure 34-25. Restore Session Edits Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1838
Figure 35-1. Save Model As Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1841
Figure 35-2. Select Active Layers Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1842
Figure 35-3. Select Directories for IC-Model Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844
Figure 35-4. Select Directories for Stimulus Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847
Figure 35-5. Select Method of Simulating Vias Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . 1850
Figure 35-6. Set Directories Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854
Figure 35-7. Setup Anti-Pads and Anti-Segments Dialog Box . . . . . . . . . . . . . . . . . . . . . . . 1860
Figure 35-8. Example Anti-Pad Visibility and Clearance Options . . . . . . . . . . . . . . . . . . . . 1862
Figure 35-9. Example Anti-Segment Visibility and Clearance Options . . . . . . . . . . . . . . . . 1862
Figure 35-10. Specify Device Kit for Current Design Dialog Box . . . . . . . . . . . . . . . . . . . . 1863
Figure 35-11. Specify DFE Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
Figure 35-12. Specify Pre-Emphasis Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
Figure 35-13. Statistical Contour Chart Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1868
Figure 35-14. Surface Roughness Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1871
Figure 35-15. Sweeping Dialog Box - Numerical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . 1873
Figure 35-16. Sweeping Dialog Box - Named Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1874
Figure 35-17. Synthesize DFE Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
Figure 35-18. Synthesize Pre-Emphasis Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
Figure 35-19. Synthesized DFE Weights Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
Figure 35-20. Synthesized Pre-Emphasis Weights Dialog Box . . . . . . . . . . . . . . . . . . . . . . 1881
Figure 35-21. Target-Z Wizard - Finish Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883
Figure 35-22. Target-Z Wizard - Specify Peak Transient Current Page . . . . . . . . . . . . . . . . 1884

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 List of Figures

Figure 35-23. Target-Z Wizard - Specify Supply Voltage and Max Ripple Page. . . . . . . . . 1886
Figure 35-24. Units Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888
Figure 35-25. Via Model Extractor Wizard - Choose Easy / Custom Page . . . . . . . . . . . . . 1890
Figure 35-26. Via Model Extractor Wizard - Control Frequency Sweep Page . . . . . . . . . . . 1891
Figure 35-27. Via Model Extractor Wizard - Customize Settings Page . . . . . . . . . . . . . . . . 1894
Figure 35-28. Via Model Extractor Wizard - Run Analysis Page . . . . . . . . . . . . . . . . . . . . . 1896
Figure 35-29. Via Model Extractor Wizard - Select Signal Via Page - LineSim . . . . . . . . . 1898
Figure 35-30. Via Model Extractor Wizard - Select Signal Via Page - BoardSim - Single-Ended
Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1899
Figure 35-31. Via Model Extractor Wizard - Select Signal Via Page - BoardSim - Differential
Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1900
Figure 35-32. Via Model Extractor Wizard - Set Model Type Page . . . . . . . . . . . . . . . . . . . 1902
Figure 35-33. Exported S-Parameter Models for Same Via Pair at 25 and 50 Ohms . . . . . . 1904
Figure 35-34. Port Mapping for Differential Via Symbols and Exported S-Parameter Models -
LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905
Figure 35-35. Port Mapping for Differential Via Symbols and Exported S-Parameter Models -
BoardSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905
Figure 35-36. Via Model Extractor Wizard - Start Analysis Page . . . . . . . . . . . . . . . . . . . . 1906
Figure 35-37. Via Properties Dialog Box - No 3-D Solver . . . . . . . . . . . . . . . . . . . . . . . . . . 1909
Figure 35-38. Via Properties Dialog Box - HyperLynx 3D EM Solver . . . . . . . . . . . . . . . . 1910
Figure 35-39. View Options Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913
Figure 35-40. Viewing Filter Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1916

36 BoardSim User Guide, v8.2

February 2012
List of Tables

List of Tables

Table 1-1. BSW.INI Sections and Keywords for Transferring Settings . . . . . . . . . . . . . . . . 52

Table 1-2. Measure Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 1-3. Verify Target Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 1-4. Measure Timing for DDRx Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 1-5. Verify SERDES Channel Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 1-6. Verify PDN Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 1-7. Measure PCB Heating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 1-8. Verify Return Current Impedance for Single-Ended Signal Vias . . . . . . . . . . . . 78
Table 1-9. Export Models for Use in Other Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 1-10. Resolve Post-Layout Signal-Integrity Problems with What If Experiments . . . 80
Table 1-11. Resolve Post-Layout Power-Integrity Problems with What If Experiments . . . 83
Table 1-12. View Simulation Results - QuickStart for BoardSim . . . . . . . . . . . . . . . . . . . . 92
Table 1-13. Power-Integrity Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 2-1. BoardSim Tutorials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 2-2. BoardSim Via Modeling Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 4-1. Good and Bad Reference Designator Mappings . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 4-2. Passive Component Value Formatting for PADS Layout . . . . . . . . . . . . . . . . . . 223
Table 4-3. Supported Scaling Factor Suffixes for PADS Layout . . . . . . . . . . . . . . . . . . . . . 223
Table 4-4. Passive Component Value Formatting for Accel EDA Translator . . . . . . . . . . . 226
Table 4-5. Supported Scaling Factor Suffixes for Accel EDA Translator . . . . . . . . . . . . . . 226
Table 4-6. Extracted Cadence Allegro ASCII Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 4-7. Board Station Variant Name Parameter Usage . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 4-8. Required ASCII File Names for Board Station Translator . . . . . . . . . . . . . . . . . 238
Table 4-9. Contents of ASCII Files for CR-5000 Board Designer . . . . . . . . . . . . . . . . . . . . 246
Table 4-10. Translate File Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 4-11. Translator Options Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 5-1. Summary of Board Viewer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 5-2. Board Viewer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 6-1. Net Selection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 6-2. Sorting Net Options in the Select Net by Name Dialog Box . . . . . . . . . . . . . . . 274
Table 6-3. Edit Power-Supply Nets Dialog Box Spreadsheets . . . . . . . . . . . . . . . . . . . . . . . 281
Table 6-4. Unique Characteristics of Model Selection Options . . . . . . . . . . . . . . . . . . . . . . 289
Table 6-5. Unique Characteristics of .REF and .QPL Files . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 6-6. Precedence Among Model Assignment Methods . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 6-7. Precedence Among Value Assignment Methods . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 6-8. Default Buffer Direction of Pins Selected by Automapping . . . . . . . . . . . . . . . . 298
Table 6-9. QPL-File Editor Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Table 6-10. Units for Resistor and Capacitor Values in .REF and .QPL Files . . . . . . . . . . . 312
Table 6-11. Maximum Length of Fields in .QPL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Table 7-1. Design Setup Tasks for PI Simulation and Related Model Exporting . . . . . . . . 344
Table 7-2. Required Models for PI Simulation and Exporting PI-Related Models . . . . . . . 348

BoardSim User Guide, v8.2 37

February 2012
 List of Tables

Table 8-1. Types of Stackup Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

Table 8-2. Common Layer Selection and Deselection Tasks . . . . . . . . . . . . . . . . . . . . . . . . 365
Table 8-3. Dielectric Constants of Common PCB Materials . . . . . . . . . . . . . . . . . . . . . . . . 386
Table 8-4. Graph Viewing and Documentation Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Table 8-5. Pour and Void Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Table 8-6. Types of Stackup Image Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Table 9-1. Calculated Pin Voltage with Respect to Ground . . . . . . . . . . . . . . . . . . . . . . . . . 436
Table 9-2. Message Fragments for V/I and V/t Mismatch Error . . . . . . . . . . . . . . . . . . . . . 447
Table 10-1. Methods to Open Assign Models Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Table 10-2. Pins List Icons in Assign Models Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Table 10-3. Series Bus Switch Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Table 10-4. Enabling Different Series Bus Switch Groups - Example 1 . . . . . . . . . . . . . . . 494
Table 10-5. Enabling Different Series Bus Switch Groups - Example 2 . . . . . . . . . . . . . . . 494
Table 10-6. SPICE Model Assignment - Contents of Circuit Connection Cell . . . . . . . . . . 496
Table 10-7. SPICE Model Assignment - Output Characteristic List . . . . . . . . . . . . . . . . . . 497
Table 10-8. SPICE Model Assignment - Delayed Stimulus Output Characteristic List . . . 497
Table 10-9. Single-Ended Driver Spreadsheet Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
Table 10-10. Single-Ended Receiver Spreadsheet Mapping . . . . . . . . . . . . . . . . . . . . . . . . 499
Table 10-11. Differential Driver Spreadsheet Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Table 10-12. Differential Modeling Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Table 10-13. Example of Modeling ICs with .MOD Models . . . . . . . . . . . . . . . . . . . . . . . . 505
Table 10-14. IC Model Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Table 10-15. .EBD Supply Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Table 10-16. Batch Simulation - Driver Measurement Thresholds and Loads . . . . . . . . . . 516
Table 10-17. Batch Simulation - Receiver Measurement Thresholds . . . . . . . . . . . . . . . . . 518
Table 11-1. Driver Stimulus Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Table 11-2. IC Operating Settings - IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Table 11-3. Pullup and Power Clamp Voltages - IBIS Models . . . . . . . . . . . . . . . . . . . . . . 553
Table 11-4. IC Operating Settings - .MOD Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Table 11-5. Description of Eye Masks in BSW.mask File . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Table 11-6. Availability of Automatic Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Table 12-1. Combination of Sweep Simulation Values - Independent Ranges . . . . . . . . . . 608
Table 12-2. Combination of Sweep Simulation Values - Locked Ranges . . . . . . . . . . . . . . 609
Table 13-1. IBIS-AMI Channel Analysis Simulation Block Diagram - Main Flow . . . . . . 619
Table 13-2. IBIS-AMI Channel Analysis Simulation Block Diagram - Crosstalk Flow . . . 624
Table 14-1. FastEye Channel Analysis Simulation Block Diagram - Main Flow . . . . . . . . 636
Table 14-2. FastEye Channel Analysis Simulation Block Diagram - Crosstalk Flow . . . . . 640
Table 14-3. Examination Controls for FastEye Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Table 15-1. Batch Simulation - Comparing Quick Analysis and Detailed Simulation . . . . 652
Table 15-2. Batch Simulation - IC Properties for Aggressor Nets . . . . . . . . . . . . . . . . . . . . 659
Table 15-3. Batch Simulation - Missing or Incorrectly Enabled ICs . . . . . . . . . . . . . . . . . . 659
Table 15-4. Batch Simulation - Format of Standard Report . . . . . . . . . . . . . . . . . . . . . . . . . 664
Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically . . . . . . . . . . . . . . 667
Table 15-6. Mapping IC Model Types to Rail Voltage Sources . . . . . . . . . . . . . . . . . . . . . 714
Table 15-7. Mapping IC Model Types to Timing Threshold Voltage Sources . . . . . . . . . . 715

38 BoardSim User Guide, v8.2

February 2012
List of Tables

Table 15-8. Batch Simulation - Signal-Integrity Simulation Results Table . . . . . . . . . . . . . 716

Table 15-9. Batch Simulation - Possible Strategy for Running High-Accuracy . . . . . . . . . 721
Table 15-10. Mapping CES and BoardSim Constraint Columns . . . . . . . . . . . . . . . . . . . . . 722
Table 15-11. Batch Simulation - Quick Analysis Options . . . . . . . . . . . . . . . . . . . . . . . . . . 725
Table 15-12. Calculating the Number of Round Robin Simulations . . . . . . . . . . . . . . . . . . 739
Table 16-1. MultiBoard - Unavailable Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Table 16-2. MultiBoard - Maximum Number of Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
Table 16-3. Pin-to-Pin Interconnection Mapping for Previous Figure . . . . . . . . . . . . . . . . . 756
Table 16-4. MultiBoard - Edit Box Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
Table 16-5. MultiBoard - Saving Changes for Multiple Instances of a Board . . . . . . . . . . . 769
Table 16-6. MultiBoard - Scope of Apply to All Similar Boards Check Box . . . . . . . . . . . 771
Table 17-1. DDR2 Signal Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Table 17-2. tCKAC(min) and tCKAC(max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Table 17-3. tCKCTL(min) and tCKCTL(max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
Table 17-4. tCKDQS(min) and tCKDQS(max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
Table 17-5. tDQSDQ(min) and tDQSDQ(max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Table 17-6. tDS and tDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Table 17-7. Summary of DDRx Timing Relationships at the Controller . . . . . . . . . . . . . . . 791
Table 17-8. DDRx Folders Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
Table 17-9. Setup and Hold Timing with Differential Clock or Strobe . . . . . . . . . . . . . . . . 805
Table 17-10. Setup and Hold Timing with Single-Ended Clock or Strobe . . . . . . . . . . . . . 806
Table 17-11. Plotting Nominal Slew-Rate Lines for Setup Time Derating . . . . . . . . . . . . . 808
Table 17-12. Plotting Nominal Slew-Rate Lines for Hold Time Derating . . . . . . . . . . . . . . 809
Table 17-13. Plotting Tangental Slew-Rate Lines for Setup Time Derating . . . . . . . . . . . . 810
Table 17-14. Plotting Tangental Slew-Rate Lines for Hold Time Derating . . . . . . . . . . . . . 811
Table 17-15. Driver-Enabling Rules for DDRx Round Robin . . . . . . . . . . . . . . . . . . . . . . . 819
Table 17-16. DDRx Data Spreadsheet Column Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 827
Table 17-17. DDRx Address Spreadsheet Column Definitions . . . . . . . . . . . . . . . . . . . . . . 832
Table 17-18. DDRx Skew Spreadsheet Column Definitions . . . . . . . . . . . . . . . . . . . . . . . . 836
Table 17-19. DDRx SI Spreadsheet Column Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Table 17-20. DDRx Batch Mode Wizard - Initialization Page Contents . . . . . . . . . . . . . . . 850
Table 17-21. DDRx Batch Mode Wizard - Controller Page Contents . . . . . . . . . . . . . . . . . 853
Table 17-22. DDRx Batch Mode Wizard - DRAMs Page Contents . . . . . . . . . . . . . . . . . . 856
Table 17-23. Specifying DRAM Locations for a Stacked Dual-Die DRAM . . . . . . . . . . . . 860
Table 17-24. DDRx Batch Mode Wizard - PLLs and Registers Page Contents . . . . . . . . . . 862
Table 17-25. DDRx Batch Mode Wizard - IBIS Models Page Contents . . . . . . . . . . . . . . . 863
Table 17-26. DDRx Batch Mode Wizard - Nets to Simulate Page Contents . . . . . . . . . . . . 864
Table 17-27. DDRx Batch Mode Wizard - DRAM Signals Page Contents . . . . . . . . . . . . . 865
Table 17-28. DDRx Batch Mode Wizard - Data Strobes Page Contents . . . . . . . . . . . . . . . 866
Table 17-29. DDRx Batch Mode Wizard - Data Nets Page Contents . . . . . . . . . . . . . . . . . 867
Table 17-30. DDRx Batch Mode Wizard - Clock Nets Page Contents . . . . . . . . . . . . . . . . 869
Table 17-31. DDRx Batch Mode Wizard - Addr/Comm Nets Page Contents . . . . . . . . . . . 870
Table 17-32. DDRx Batch Mode Wizard - Control Nets Page Contents . . . . . . . . . . . . . . . 871
Table 17-33. DDRx Batch Mode Wizard - Disable Nets Page Contents . . . . . . . . . . . . . . . 872
Table 17-34. DDRx Batch Mode Wizard - IBIS Model Selectors Page Contents . . . . . . . . 873

BoardSim User Guide, v8.2 39

February 2012
 List of Tables

Table 17-35. DDRx Batch Mode Wizard - ODT Models Page Contents . . . . . . . . . . . . . . . 874
Table 17-36. DDRx Batch Mode Wizard - ODT Behavior Page Contents . . . . . . . . . . . . . 875
Table 17-37. DDRx Batch Mode Wizard - Timing Models Page Contents . . . . . . . . . . . . . 877
Table 17-38. DDRx Batch Mode Wizard - Write Leveling Page Contents . . . . . . . . . . . . . 880
Table 17-39. DDRx Batch Mode Wizard - Stimulus and Crosstalk Page Contents . . . . . . . 882
Table 17-40. DDRx Batch Mode Wizard - Simulation Options Page Contents . . . . . . . . . . 883
Table 17-41. DDRx Batch Mode Wizard - Report Options Page Contents . . . . . . . . . . . . . 884
Table 17-42. DDRx Batch Mode Wizard - Simulate Page Contents . . . . . . . . . . . . . . . . . . 885
Table 17-43. DDRx Batch Mode - Run Simulation Dialog Box Contents . . . . . . . . . . . . . . 886
Table 18-1. EMC - Types of Nets Includes in Radiation Prediction . . . . . . . . . . . . . . . . . . 895
Table 18-2. IC Operating Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
Table 18-3. Current Probe Assignment Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
Table 19-1. Manhattan Routing - Net Selection Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
Table 19-2. Manhattan Routing - Icons in Net Selection Area . . . . . . . . . . . . . . . . . . . . . . . 932
Table 21-1. Terminator Wizard - Supported Terminations and Net Topologies . . . . . . . . . 949
Table 21-2. Terminator Wizard - Types of Signal-Integrity Checks . . . . . . . . . . . . . . . . . . 958
Table 22-1. DC Drop Current Flow - Current Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
Table 22-2. DC Drop Current Flow - Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
Table 22-3. DC Drop Circuit - Simulate One Power-Supply Net . . . . . . . . . . . . . . . . . . . . 980
Table 22-4. DC Drop Simulation Circuit - Simulate Selected and Reference Power-Supply Nets
982
Table 22-5. PowerScope Hides Some Shapes for DC Drop . . . . . . . . . . . . . . . . . . . . . . . . . 986
Table 22-6. DC Current Flow Restriction - Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989
Table 22-7. DC Current Flow Restriction - BGA Antipads . . . . . . . . . . . . . . . . . . . . . . . . . 989
Table 22-8. DC Drop Folders Legend - Interactive Simulation . . . . . . . . . . . . . . . . . . . . . . 991
Table 22-9. Output Files for DC Drop - Interactive Simulation . . . . . . . . . . . . . . . . . . . . . . 992
Table 22-10. DC Drop Folders Legend - Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 994
Table 22-11. Output Files for DC Drop - Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 994
Table 22-12. Measuring DC Drop - Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
Table 22-13. Measuring DC Drop - Reporter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
Table 22-14. Measuring DC Drop - HyperLynx PI PowerScope 2-D . . . . . . . . . . . . . . . . . 1007
Table 23-1. Decoupling Analysis Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
Table 23-2. Decoupling Capacitor Spreadsheet Column Definitions . . . . . . . . . . . . . . . . . . 1031
Table 24-1. Measuring Plane Voltage Noise - HyperLynx PI PowerScope 2D . . . . . . . . . . 1047
Table 24-2. Measuring Plane Surface and Capacitor Currents . . . . . . . . . . . . . . . . . . . . . . . 1049
Table 25-1. Bypass Analysis Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Table 26-1. What If Simulation Methods for Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Table 27-1. S-Parameters for Differential Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
Table 27-2. Convert Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
Table 27-3. Cascade 4-Port S-Parameter Models Dialog Box Contents . . . . . . . . . . . . . . . 1119
Table 27-4. Convert Mode Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
Table 27-5. Convert Parameter Type Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . 1124
Table 27-6. Convert to Fitted Poles Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
Table 27-7. Convert to Touchstone Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Table 27-8. Convert to Transfer Function Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . 1128

40 BoardSim User Guide, v8.2

February 2012
List of Tables

Table 27-9. TDR Impedance Plot Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134

Table 27-10. Time-Domain Response Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . 1143
Table 28-1. Export to ICX - Optional Export Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
Table 28-2. Signal-Via Output Files - Exporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
Table 28-3. PDN Output Files - Exporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
Table 29-1. Display of Impedance and Delay in Transmission-Line Symbols . . . . . . . . . . 1203
Table 29-2. Contents of Impedance Display Area in Field Solver . . . . . . . . . . . . . . . . . . . . 1205
Table 29-3. Detailed Field-Solver Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206
Table 29-4. Impedance and Termination Summary (Two Transmission Lines Coupling Regions
Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
Table 29-5. Crosstalk Simulation - Default IC Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
Table 29-6. Geometric Thresholds Used to Identify Aggressor Nets . . . . . . . . . . . . . . . . . . 1226
Table 29-7. Changing IC Models - Effect on Pins List . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
Table 29-8. Coupling Region Dialog Box - Contents Overview . . . . . . . . . . . . . . . . . . . . . 1242
Table 29-9. Coupling Region Dialog Box - Contents of Impedance Pane . . . . . . . . . . . . . . 1244
Table 29-10. Termination Recommendations for Two Coupled Transmission-Lines . . . . . 1250
Table 30-1. Default ASCII ECO File Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
Table 30-2. Back Annotation Support for IC and Ferrite Bead Models . . . . . . . . . . . . . . . . 1261
Table 31-1. Oscilloscope and Sweep Manager Simulations . . . . . . . . . . . . . . . . . . . . . . . . . 1264
Table 31-2. Generic Batch Simulation (Batch-Mode Wizard) . . . . . . . . . . . . . . . . . . . . . . . 1265
Table 31-3. DDRx Wizard Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265
Table 31-4. FastEye Channel Analyzer Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266
Table 31-5. IBIS-AMI Channel Analyzer Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
Table 31-6. Timing Model Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
Table 31-7. Timing Model Operator Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
Table 31-8. Contrasting HLTM and Verilog $delay Functions . . . . . . . . . . . . . . . . . . . . . . 1291
Table 31-9. DDRx Wizard Speed Grade Designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
Table 31-10. Timing Model Module Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292
Table 31-11. Controller Timing Model Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . 1293
Table 31-12. Controller Timing Model Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296
Table 31-13. Memory Timing Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298
Table 31-14. Memory Timing Model Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302
Table 31-15. PLL Timing Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
Table 31-16. Register Timing Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
Table 31-17. Pre-Defined Variables for Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306
Table 31-18. Comment Designators for DDRx Wizard Setup File . . . . . . . . . . . . . . . . . . . 1308
Table 31-19. Record Identifier Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310
Table 31-20. Sub-Record Identifier Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310
Table 31-21. Argument Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311
Table 31-22. Argument Unit-Type Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312
Table 31-23. Options and Option Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314
Table 31-24. .MOD Models - Specifying Other Parameters . . . . . . . . . . . . . . . . . . . . . . . . 1341
Table 31-25. Propagation Modes of Two Coupled Microstrip Traces . . . . . . . . . . . . . . . . . 1363
Table 31-26. Propagation Modes of Two Coupled Microstrip and Buried Microstrip Traces
1364

BoardSim User Guide, v8.2 41

February 2012
 List of Tables

Table 31-27. Comparing Transmission Planes to Transmission Lines . . . . . . . . . . . . . . . . . 1373

Table 31-28. Jitter Types Supported by HyperLynx Features . . . . . . . . . . . . . . . . . . . . . . . 1379
Table 31-29. Gaussian Distribution - Confidence Interval . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
Table 31-30. Jitter Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
Table 31-31. Overlapping Anti-Pads That Isolate Metal Shapes . . . . . . . . . . . . . . . . . . . . . 1397
Table 32-1. Add/Edit Decoupling Capacitor(s) Dialog Box Contents - Place = Single . . . . 1415
Table 32-2. Add/Edit Decoupling Capacitor(s) Dialog Box Contents - Place = Array . . . . 1417
Table 32-3. Add/Edit IC Power Pin(s) Dialog Box Contents - Place = Single . . . . . . . . . . 1422
Table 32-4. Add/Edit IC Power Pin(s) Dialog Box Contents - Place = Array . . . . . . . . . . . 1424
Table 32-5. Add/Edit Via Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1428
Table 32-6. Add/Edit VRM or DC to DC Converter Dialog Box Contents . . . . . . . . . . . . . 1432
Table 32-7. Add Signal Via Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436
Table 32-8. AMI File Assignment Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438
Table 32-9. Archive Design Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440
Table 32-10. Assign / Edit Capacitor Model Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . 1445
Table 32-11. Assign Decoupling-Capacitor Groups Dialog Box Contents . . . . . . . . . . . . . 1451
Table 32-12. Assign Decoupling-Capacitor Models Dialog Box Contents . . . . . . . . . . . . . 1454
Table 32-13. Assign Power Integrity Models Dialog Box — IC Tab Contents . . . . . . . . . . 1458
Table 32-14. Assign Power Integrity Models Dialog Box — Supply-Net Resistors Tab Contents
1461
Table 32-15. Assign Power Integrity Models Dialog Box — Supply-Net Inductors Tab Contents
1464
Table 32-16. Assign Power Integrity Models Dialog Box — Other Supply-Net Components Tab
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
Table 32-17. Assign VRM Model Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471
Table 32-18. Bathtub Chart Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475
Table 32-19. Bypass Wizard - Choose Easy / Custom Page Contents . . . . . . . . . . . . . . . . . 1479
Table 32-20. Bypass Wizard - Control Frequency Sweep Page Contents . . . . . . . . . . . . . . 1480
Table 32-21. Bypass Wizard - Customize Settings Page Contents . . . . . . . . . . . . . . . . . . . 1483
Table 32-22. Bypass Wizard - Run Analysis Page Contents . . . . . . . . . . . . . . . . . . . . . . . . 1485
Table 32-23. Bypass Wizard - Select Signal Via Page - LineSim Contents . . . . . . . . . . . . . 1487
Table 32-24. Bypass Wizard - Select Signal Via Page - BoardSim Contents . . . . . . . . . . . 1488
Table 32-25. Bypass Wizard - Set the Target Impedance Page Contents . . . . . . . . . . . . . . 1490
Table 32-26. Bypass Wizard - Start Analysis Page Contents . . . . . . . . . . . . . . . . . . . . . . . . 1491
Table 32-27. Channel Characterization Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . 1495
Table 32-28. Decoupling Mounting Scheme Editor Dialog Box Contents . . . . . . . . . . . . . 1505
Table 32-29. Decoupling Wizard - Choose a Type of Analysis Page Contents . . . . . . . . . . 1508
Table 32-30. Decoupling Wizard - Choose Easy / Custom Page Contents . . . . . . . . . . . . . 1510
Table 32-31. Decoupling Wizard - Control Frequency Sweep Page Contents . . . . . . . . . . . 1511
Table 32-32. Decoupling Wizard - Customize Settings Page Contents . . . . . . . . . . . . . . . . 1515
Table 32-33. Decoupling Wizard - Run Analysis Page Contents . . . . . . . . . . . . . . . . . . . . . 1518
Table 32-34. Decoupling Wizard - Select IC Power Pins Page Contents . . . . . . . . . . . . . . 1521
Table 32-35. Select Nets for Analysis Page Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523
Table 32-36. Decoupling Wizard - Set the Target Impedance Page Contents . . . . . . . . . . . 1525
Table 32-37. Decoupling Wizard - Start Analysis Page Contents . . . . . . . . . . . . . . . . . . . . 1526

42 BoardSim User Guide, v8.2

February 2012
List of Tables

Table 32-38. Define Constraint Template Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . 1529

Table 32-39. Define Constraint Templates Dialog Box - Length/Delay Tab Contents . . . . 1531
Table 32-40. Constraint Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532
Table 32-41. Define Constraint Templates Dialog Box - Diff Pair Tab Contents . . . . . . . . 1535
Table 32-42. Define Constraint Templates Dialog Box - Net Scheduling Tab Contents . . . 1537
Table 32-43. Define Constraint Templates Dialog Box - Pin Sets Tab Contents . . . . . . . . . 1540
Table 32-44. Differential Pair Net Suffixes Dialog Box Contents . . . . . . . . . . . . . . . . . . . . 1542
Table 32-45. Differential Pairs Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544
Table 33-1. Edit AC Power Pin Model Dialog Box - Current Source Area Contents . . . . . 1548
Table 33-2. Edit AC Power Pin Model Dialog Box - Stimulus Area Contents . . . . . . . . . . 1548
Table 33-3. Edit DC Power Pin Model Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . 1551
Table 33-4. Edit Reference Designator Mappings Dialog Box Contents . . . . . . . . . . . . . . . 1553
Table 33-5. Edit Transmission Line Dialog Box - Add/Move to Coupling Region Tab Contents
1556
Table 33-6. Edit Transmission Line Dialog Box - Cables Tab Contents . . . . . . . . . . . . . . . 1558
Table 33-7. Edit Transmission Line Dialog Box - Connectors Tab Contents . . . . . . . . . . . 1560
Table 33-8. Edit Transmission Line Dialog Box - Edit Coupling Regions Tab Contents . . 1564
Table 33-9. Edit Transmission Line Dialog Box - Loss Tab Contents . . . . . . . . . . . . . . . . . 1571
Table 33-10. Edit Transmission Line Dialog Box - Transmission-Line Type Tab Contents 1574
Table 33-11. Electrical Properties for Cross-Section Models . . . . . . . . . . . . . . . . . . . . . . . 1579
Table 33-12. Values Tab Contents for Uncoupled Stackup Transmission Lines . . . . . . . . . 1580
Table 33-13. Values Tab Contents for Cross Section Transmission Lines . . . . . . . . . . . . . 1583
Table 33-14. eDxD/eExp View Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585
Table 33-15. Zoom and Pan Commands for eDxD/eExp View . . . . . . . . . . . . . . . . . . . . . . 1586
Table 33-16. Export to HyperLynx 3D EM Dialog Box Contents . . . . . . . . . . . . . . . . . . . . 1589
Table 33-17. FastEye Channel Analyzer - Add Jitter Page Contents . . . . . . . . . . . . . . . . . . 1593
Table 33-18. FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page Contents . . . . . . 1597
Table 33-19. FastEye Pre-Emphasis Filter - Feed-Forward . . . . . . . . . . . . . . . . . . . . . . . . . 1600
Table 33-20. FastEye DFE Filter - Feed-Backward Contents . . . . . . . . . . . . . . . . . . . . . . . 1601
Table 33-21. FastEye Channel Analyzer - Choose Fitting/Convolution Page Contents . . . 1602
Table 33-22. Comparing the Strengths of Complex-Pole Fitting and Convolution . . . . . . . 1603
Table 33-23. FastEye Channel Analyzer - Choose New/Saved Analysis Page Contents . . 1605
Table 33-24. FastEye Channel Analyzer - Define Stimulus Page Contents . . . . . . . . . . . . . 1608
Table 33-25. FastEye Channel Analyzer - FastEye/Worst-Case Analysis Page Contents . . 1612
Table 33-26. FastEye Channel Analyzer - Set Up Channel Characterizations Page Contents
1616
Table 33-27. FastEye Channel Analyzer - Set Up Crosstalk Analysis Page Contents . . . . . 1624
Table 33-28. FastEye Channel Analyzer - View Analysis Results Page Contents . . . . . . . 1628
Table 33-29. FastEye Step and Pulse Responses Dialog Box and PRBS Waveforms Dialog Box
1633
Table 33-30. Field Solver Dialog Box / Edit Transmission Line Dialog Box - Field Solver Tab
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637
Table 33-31. Find Component Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
Table 33-32. Highlight Net Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
Table 33-33. HyperLynx 3D EM Full-Wave EM Simulation Dialog Box Contents . . . . . . 1644

BoardSim User Guide, v8.2 43

February 2012
 List of Tables

Table 33-34. HyperLynx 3D EM Geometry Viewer - 3D Geometry View Dialog Box Contents
1647
Table 33-35. HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View Dialog Box
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
Table 33-36. HyperLynx 3D EM Project Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . 1656
Table 33-37. HyperLynx IBIS-AMI Sweeps Viewer - File Menu Contents . . . . . . . . . . . . 1670
Table 33-38. HyperLynx IBIS-AMI Sweeps Viewer - Edit Menu Contents . . . . . . . . . . . . 1670
Table 33-39. HyperLynx IBIS-AMI Sweeps Viewer - View Menu Contents . . . . . . . . . . . 1671
Table 33-40. HyperLynx IBIS-AMI Sweeps Viewer - Spreadsheet Menu Contents . . . . . . 1671
Table 33-41. HyperLynx IBIS-AMI Sweeps Viewer - Plot Menu Contents . . . . . . . . . . . . 1672
Table 33-42. HyperLynx IBIS-AMI Sweeps Viewer - Toolbar - Main Contents . . . . . . . . 1674
Table 33-43. HyperLynx IBIS-AMI Sweeps Viewer - Toolbar - Plot View Contents . . . . 1676
Table 33-44. Plot View Pane Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679
Table 33-45. HyperLynx IBIS-AMI Sweeps Viewer Spreadsheet Contents . . . . . . . . . . . . 1681
Table 33-46. Plot View Options Pane Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1690
Table 33-47. Spreadsheet Options Pane Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
Table 33-48. Sliders Pane Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696
Table 33-49. HyperLynx PI PowerScope Toolbar Contents . . . . . . . . . . . . . . . . . . . . . . . . 1710
Table 33-50. HyperLynx PI PowerScope Controls - Plane Noise Simulation Options . . . . 1715
Table 33-51. HyperLynx PI PowerScope Controls - Positioning Options Area . . . . . . . . . 1716
Table 33-52. HyperLynx PI PowerScope Controls - Visual Options Area . . . . . . . . . . . . . 1716
Table 33-53. HyperLynx PI PowerScope Controls - T-Plane/Layer List Options Area . . . 1719
Table 33-54. HyperLynx PI PowerScope Controls - General Options . . . . . . . . . . . . . . . . . 1719
Table 33-55. HyperLynx SI Eye Density Viewer Toolbar Contents . . . . . . . . . . . . . . . . . . 1723
Table 33-56. HyperLynx SI Eye Density Viewer Contents - Positioning Options Area . . . 1726
Table 33-57. HyperLynx SI Eye Density Viewer Contents - Plot List Area . . . . . . . . . . . . 1726
Table 33-58. HyperLynx SI Eye Density Viewer Contents - Appearance Area . . . . . . . . . 1726
Table 33-59. IBIS-AMI Channel Analyzer Wizard - Choose New/Saved Analysis Page Contents
1730
Table 33-60. IBIS-AMI Channel Analyzer Wizard - Configure AMI Models Page Contents
1733
Table 33-61. IBIS-AMI Channel Analyzer Wizard - Define AMI Stimulus Page Contents 1735
Table 33-62. IBIS-AMI Channel Analyzer Wizard - Review Simulation Sweeps Page Contents
1740
Table 33-63. IBIS-AMI Channel Analyzer - Set Up Channel Characterizations Page Contents
1743
Table 33-64. IBIS-AMI Channel Analyzer - Set Up Crosstalk Analysis Page Contents . . . 1749
Table 33-65. IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model Settings Page Contents
1754
Table 33-66. IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page Contents
1757
Table 33-67. IBIS AMI Parameter Editor Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1760
Table 33-68. Gaussian Jitter Limits for IBIS-AMI Channel Analysis . . . . . . . . . . . . . . . . . 1761
Table 33-69. Dual Dirac Jitter Limits for IBIS-AMI Channel Analysis . . . . . . . . . . . . . . . 1761
Table 33-70. DjRj Jitter Limits for IBIS-AMI Channel Analysis . . . . . . . . . . . . . . . . . . . . 1762

44 BoardSim User Guide, v8.2

February 2012
List of Tables

Table 33-71. Illegal Single-Pin Components Found Dialog Box Contents . . . . . . . . . . . . . 1764
Table 33-72. Installed Options Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1766
Table 34-1. New HyperLynx 3D EM Project Dialog Box Contents . . . . . . . . . . . . . . . . . . 1769
Table 34-2. PDN Model Extractor Wizard - Choose Easy / Custom Page Contents . . . . . . 1771
Table 34-3. PDN Model Extractor Wizard - Control Frequency Sweep Page Contents . . . 1773
Table 34-4. PDN Model Extractor Wizard - Customize Settings Page Contents . . . . . . . . . 1775
Table 34-5. PDN Model Extractor Wizard - Normalization Impedance Page Contents . . . 1777
Table 34-6. PDN Model Extractor Wizard - Run Analysis Page Contents . . . . . . . . . . . . . 1778
Table 34-7. PDN Model Extractor Wizard - Select IC Power Pins Page . . . . . . . . . . . . . . . 1781
Table 34-8. PDN Model Extractor Wizard - Select Signal Vias Page Contents - LineSim . 1783
Table 34-9. PDN Model Extractor Wizard - Select Signal Vias Page Contents - BoardSim 1785
Table 34-10. PDN Model Extractor Wizard - Start Analysis Page Contents . . . . . . . . . . . . 1787
Table 34-11. PDN Net Manager Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
Table 34-12. Preferences Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1791
Table 34-13. Preferences Dialog Box - Advanced Tab Contents . . . . . . . . . . . . . . . . . . . . . 1793
Table 34-14. Appearance Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1801
Table 34-15. BoardSim Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
Table 34-16. Circuit Simulators Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810
Table 34-17. Default Padstack Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1813
Table 34-18. Default Stackup Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1816
Table 34-19. General Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819
Table 34-20. LineSim Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822
Table 34-21. Oscilloscope Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1824
Table 34-22. Preferences Dialog Box - Power Integrity Tab Contents . . . . . . . . . . . . . . . . 1829
Table 34-23. Reporter Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1836
Table 34-24. Restore Session Edits Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . 1838
Table 35-1. Save Model As Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1841
Table 35-2. Select Active Layers Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1842
Table 35-3. Select Directories for IC-Model Files Contents . . . . . . . . . . . . . . . . . . . . . . . . 1845
Table 35-4. Select Directories for Stimulus Files Contents . . . . . . . . . . . . . . . . . . . . . . . . . 1847
Table 35-5. Select Method of Simulating Vias Dialog Box Contents . . . . . . . . . . . . . . . . . 1851
Table 35-6. Set Directories Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1855
Table 35-7. Set Reference Nets Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1858
Table 35-8. Setup Anti-Pads and Anti-Segments Dialog Box Contents . . . . . . . . . . . . . . . 1861
Table 35-9. Specify DFE Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
Table 35-10. Specify Pre-Emphasis Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
Table 35-11. Statistical Contour Chart Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . 1869
Table 35-12. Surface Roughness Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1872
Table 35-13. Sweeping Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1874
Table 35-14. Supported Scaling Factor Suffixes for Sweeps . . . . . . . . . . . . . . . . . . . . . . . . 1876
Table 35-15. Synthesize DFE Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
Table 35-16. Synthesize Pre-Emphasis Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
Table 35-17. Synthesized DFE Weights Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . 1879
Table 35-18. Synthesized Pre-Emphasis Weights Dialog Box Contents . . . . . . . . . . . . . . . 1882
Table 35-19. Target-Z Wizard - Finish Page Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883

BoardSim User Guide, v8.2 45

February 2012
 List of Tables

Table 35-20. Target-Z Wizard - Specify Peak Transient Current Page Contents . . . . . . . . 1884
Table 35-21. Target-Z Wizard - Specify Supply Voltage and Max Ripple Page Contents . 1886
Table 35-22. Via Model Extractor Wizard - Choose Easy / Custom Page Contents . . . . . . 1890
Table 35-23. Via Model Extractor Wizard - Control Frequency Sweep Page Contents . . . 1892
Table 35-24. Via Model Extractor Wizard - Customize Settings Page Contents . . . . . . . . . 1894
Table 35-25. Via Model Extractor Wizard - Run Analysis Page Contents . . . . . . . . . . . . . 1896
Table 35-26. Via Model Extractor Wizard - Select Signal Via Page Contents - LineSim . . 1898
Table 35-27. Via Model Extractor Wizard - Select Signal Via Page Contents - BoardSim . 1900
Table 35-28. Via Model Extractor Wizard - Set Model Type Page Contents . . . . . . . . . . . 1903
Table 35-29. Via Model Extractor Wizard - Start Analysis Page Contents . . . . . . . . . . . . . 1906
Table 35-30. Via Properties Dialog Box - No 3-D Solver . . . . . . . . . . . . . . . . . . . . . . . . . . 1909
Table 35-31. Via Properties Dialog Box - HyperLynx 3D EM Solver Contents . . . . . . . . . 1911
Table 35-32. View Options Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1914
Table 35-33. Viewing Filter Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917
Table 36-1. Signal-Integrity and SERDES Analysis Features . . . . . . . . . . . . . . . . . . . . . . . 1919
Table 36-2. Power-Integrity Analysis Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
Table 36-3. Thermal Analysis Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
Table 36-4. 3-D Electromagnetic Analysis Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922
Table 36-5. Flow Integration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922
Table 36-6. Documentation Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923
Table 37-1. File Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1926
Table 37-2. Setup Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1928
Table 37-3. Edit Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932
Table 37-4. Models Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1934
Table 37-5. Select Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1937
Table 37-6. Simulate SI Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1938
Table 37-7. Simulate PI Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1941
Table 37-8. Simulate Thermal Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1943
Table 37-9. BoardSim Export Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944
Table 37-10. LineSim Export Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1946

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 Chapter 1
Getting Started with Post-Layout Design
Simulation - BoardSim

Welcome! This documentation strives to answer the questions you might have about using
HyperLynx® BoardSim® simulation software.

BoardSim is a post-layout PCB design simulation and analysis tool that enables you to evaluate
the signal-integrity performance of signal nets and the power-integrity performance of power-
distribution networks (PDNs).

You import layout data into BoardSim by exporting .HYP files directly from PCB layout
software (such as Mentor Graphics Expedition® PCB or PADS® Layout) or by running a
translator on PCB layout design files (such as Cadence Allegro). You can also load layout data
in the form of CAMCAD (.CCE) files exported from Expedition PCB or CAMCAD®
Professional.

Note
See the BoardSim Tutorials for a hands on introduction to BoardSim. Many lessons
include example designs and models, so you can often obtain simulation results in a few
minutes.

A partial list of PCB design tasks you can perform with BoardSim includes:

• Measuring signal integrity

• Verifying target impedance
• Measuring timing for DDRx interfaces
• Verifying SERDES channel performance
• Verifying PDN performance
• Exporting detailed models of vias and PDNs
• Measuring PCB heating
This topic contains the following:

• “Post-Layout Workflow” on page 49

• “Configuring the HyperLynx Environment” on page 50
• “Opening BoardSim Boards” on page 54

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• “Opening MultiBoard Projects” on page 60

• “Simulations Overview - Post-Layout Tasks” on page 61

Related Topics
“What’s New” on page 1919
“Getting Started with Pre-Layout Design Simulation - LineSim“

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Post-Layout Workflow

Post-Layout Workflow
Figure 1-1 shows the main tasks in the work flow for post-layout design simulation. Click a
block in the figure to display information about the task.

Figure 1-1. Post-Layout Workflow

Configuring the
HyperLynx
Environment

Creating Opening Opening Creating

BoardSim BoardSim MultiBoard MultiBoard
Boards Boards Projects Projects

Viewing
BoardSim
Boards

Identifying Types of Simulation to

Run, see Simulations Overview -
Post-Layout Tasks

Setting Up Boards for Simulation,

see Simulations Overview - Post-
Layout Tasks

Simulating and Viewing Results,

see Simulations Overview - Post-
Layout Tasks

Exporting Design
and Model Data

Related Topics
“BoardSim Tutorials” on page 101
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Getting Started with Post-Layout Design Simulation - BoardSim
Configuring the HyperLynx Environment

Configuring the HyperLynx Environment

Edit design-independent options to specify the locations of IC models and design simulation
files, license check in/out behaviors, measurement units, simulation and appearance
preferences, and so on.

The contents of the Setup menu depends on whether a design is loaded or not. This topic
describes the design-independent options that are always available, even when no design is
loaded. For information about Setup menu contents, see “Setup Menu” on page 1928.

Procedure
1. Optionally, transfer IC model folder, design folder, and other settings from a previous
HyperLynx installation. See “Transferring HyperLynx Settings” on page 52.
2. Select Setup > Options > Directories to edit paths to design, models, stimulus, and
other directories. This opens the “Set Directories Dialog Box” on page 1854.
3. Select Setup > Options > General to edit simulation and appearance preferences. This
opens the “Preferences Dialog Box” on page 1791.
4. Select Setup > Options > Reference Designator Mappings to edit reference
designator mappings. This opens the “Edit Reference Designator Mappings Dialog
Box” on page 1553.
5. Select Setup > Options > Units to set measurement units. This opens the “Units Dialog
Box” on page 1888.
6. Select Setup > Options > License Checkout and Checkin to select licenses and other
licensing options. This opens the “Installed Options Dialog Box” on page 1766. You
must close all designs before editing licensing options.
7. To enable Mentor Graphics flow releases to interact with HyperLynx on Linux or UNIX
computers, set the HYP_HOME environment variable on the computer with the flow
release software. For example, you might do this when exporting LineSim schematics
from Expedition.
c shell example:
setenv HYP_HOME MentorGraphics/2009.1HL/SDD_HOME/hyperlynx
See also: “Managing Environment Settings” chapter in Managing Mentor Graphics
PCB Systems Software. This book is located in the release_documents folder in the
software download file or CD.

Related Topics
“Specifying Device Kits” on page 53
“Post-Layout Workflow” on page 49

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Configuring the HyperLynx Environment

“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Getting Started with Post-Layout Design Simulation - BoardSim
Configuring the HyperLynx Environment

Transferring HyperLynx Settings

You can transfer IC model, design folder name, and differential pair net name suffix settings
(BoardSim only), stored in the HyperLynx initialization file (BSW.INI), from a previous
HyperLynx installation to the latest HyperLynx installation.

Caution
This topic describes how to manually edit a file containing formatted information. If you
create formatting errors, HyperLynx can produce unexpected simulation results.

Procedure
1. If HyperLynx is running, close it.
2. Rename the BSW.INI file for the latest installation.
Example: In the folder C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx,
rename BSW.INI to BSW.INI.save.
3. Copy the BSW.INI file from the previous installation to the latest installation.
Example: C:\MentorGraphics\<previous_release>\SDD_HOME\hyperlynx\BSW.INI
to C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx\BSW.INI.
4. Edit C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx\BSW.INI and
change the contents of the following sections:

Table 1-1. BSW.INI Sections and Keywords for Transferring Settings

Section Keyword Description
[BSW_LIBRARY] ModLibPath## Folder containing IC model library. Up to 99
folders can be specified.

Example:
ModLibPath00=C:\MentorGraphics\2009H
L\SDD_HOME\hyperlynx\LIBS\ becomes
ModLibPath00=C:\MentorGraphics\2009.1
HL\SDD_HOME\hyperlynx\LIBS\.
[BSW_PREFERENCES] HypPath Folder containing design files (.HYP, .CCE,
.FFS, .TLN).

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Configuring the HyperLynx Environment

Table 1-1. BSW.INI Sections and Keywords for Transferring Settings (cont.)
[DIFF_PAIR_SUFFIXES] Net name suffixes, such as _p and _n, used
to help BoardSim automatically identify
differential pairs.

Examples:
+=-
_n=_p

See also: “Differential Pairs Dialog Box” on

page 1543
5. Save the edited file and open HyperLynx.

Tip: You can automatically create an all-new BSW.INI file by renaming the current
BSW.INI file to something else, opening HyperLynx, and then closing HyperLynx. If no
BSW.INI file exists, HyperLynx automatically creates a new file when you close the
program.

Related Topics
“Configuring the HyperLynx Environment” on page 50

Specifying Device Kits

To specify a device kit, read the documentation that comes with it to learn how to set it up. In
some cases, when you open the design that comes with a device kit, HyperLynx automatically
loads the <device_kit>.INI file for the design. In other cases, you specify the device kit to
manually load the <device_kit>.INI file for the design by performing the instructions in this
topic.

Procedure
1. Open the schematic or board that comes with the device kit, or open a new schematic.
2. Select Setup > Device Kit. This opens the Specify Device Kit for Current Design
Dialog Box.
3. Browse to the <device_kit>.INI file for the device kit, set additional values according to
the device kit documentation, and click OK.

Related Topics
“Configuring the HyperLynx Environment” on page 50
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Opening BoardSim Boards

Opening BoardSim Boards

Open a BoardSim board to run simulation or analysis on it.

Prerequisites
• Do either of the following:
o Create BoardSim boards (.HYP files) by exporting them from PCB layout software
(such as Mentor Graphics Expedition or PADS Layout) or running a translator on
PCB layout design files (such as Cadence Allegro). See “Creating BoardSim
Boards” on page 215.
o Export a .CCE (CADCAM Professional, encrypted and compressed) file from
Mentor Graphics Expedition PCB or CAMCAD Professional. For instructions, refer
to the documentation for those products.
• Map all the reference designators in the board to component types, such as ICs and
resistors. See “About Reference-Designator Mapping in BoardSim” on page 209.
• Decide whether to remove redundant metal from nets when you load the board or when
you select a net for signal-integrity simulation. See “Preferences Dialog Box - BoardSim
Tab” on page 1804 for the description of the “Remove redundant metal from a board’s
nets as the board is loaded” option.

Procedure
1. Open the board:
• Click Open BoardSim Board .
Note: To load .CCE files with the Open BoardSim File dialog box, change the file
type option to CCE Files.

Restriction: The CCE Files option is unavailable when running the 64-bit version of
HyperLynx. On Windows, use the 32-bit version of HyperLynx (which is also
installed when you install the 64 bit version) to open CAMCAD files. Select Start >
All Programs > Mentor Graphics SDD > HyperLynx <release> 32-bit > HyperLynx
Simulation Software. By contrast, Linux installations are 64-bit only or 32-bit only.
• Select File > Open Board.
• Select File > Recent Files > <previously_opened_board>.
• Windows computer > Windows Explorer > double-click .HYP file.
2. If the board file contains single-pin components that are not recognized as ICs or test
points, the “Illegal Single-Pin Components Found Dialog Box” on page 1764 opens.

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Opening BoardSim Boards

Use this dialog box to convert the “illegal” single-pin components to test points. The
conversion takes place in memory (so you do not have to reload the board file after
conversion) and can optionally be saved to the board file on disk.
3. If the board file has missing stackup information or an assigned metal layer type (such as
plane or signal) does not match the recommended type, the Stackup Verifier dialog box
opens. See “Stackup Error Reporting - Stackup Verifier” on page 370.
4. If the .HYP file has been included as one of several instances in a MultiBoard project
and you have saved unique session edits for the instances (such as enabling and
disabling output buffers on the same net), the Select the Instance dialog box opens. See
“Selecting a Board Instance to Load” on page 772.
5. If completely unrouted nets exist in the board file, BoardSim asks whether you want to
route them with Manhattan routing now.
If you click “No”, you can still create Manhattan routing after the board file has been
loaded. See “Simulating Unrouted Nets with Manhattan Routing” on page 921.
6. If part of a metal area is located outside the board outline, BoardSim informs you that it
automatically edits the metal area so that it lies within the board outline. You may want
to verify the correctness of geometries in the board viewer, in case a translator error
caused the initial problem.
7. If you have previously opened this board and have saved your BoardSim session edits,
the Restore Session Edits dialog box opens. See “Restore Session Edits Dialog Box” on
page 1838.

Note
Other dialog boxes and messages can appear while the board loads. See “Results” on
page 55, “About Field Solver Messages” on page 56, and “Out-of-Memory Errors” on
page 56.

Results
As your board loads, a dialog box gives percent-done status. For large boards, it may take
several minutes for the board file to load.

First, BoardSim counts the number of nets in the file. (Messages about the current activity
appear in the dialog box.) Then the file’s details are read into the BoardSim database. Most of
the loading time is spent reading net data; the name of the net currently being read is shown in
the status message.

After all of the nets are loaded (when the percent-done indication = 100%), BoardSim makes a
second pass to find which nets are connected to which other nets. Then, after several more
seconds to sort the net names, characterize the stackup, and draw the board, the PCB appears, as
an outline filled with components, in the board viewer. New menu choices appear above the
viewer.

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Opening BoardSim Boards

Related Topics
“Opening MultiBoard Projects” on page 60
“BoardSim Session Files” on page 56
“Post-Layout Workflow” on page 49
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47
Board Viewer User Interface

About Field Solver Messages

In preparation for performing crosstalk analysis, BoardSim briefly calls its field solver near the
end of the board-loading process to characterize certain aspects of the PCB’s stackup. Often,
you will see a progress dialog box labeled “HyperLynx” and “Running field solver” while this
analysis is running.

Tip: The field solver is called regardless of whether or not you are licensed for
BoardSim’s Crosstalk option. If you are not licensed for Crosstalk analysis, then this (and
when certain other changes, like stackup editing, occur) is the only time the field solver
runs; it is not available during simulation or any other kind of analysis unless you own the
Crosstalk option.

Out-of-Memory Errors
If you get an “out-of-memory” error while the board file is loading, you do not have enough free
memory for BoardSim to store your board in its database. This can occur if your board is very
large and some of your PC’s memory is used by other applications.

If you get “out of memory” errors from BoardSim, try closing other open applications, or
freeing more memory for Windows to use. Note that BoardSim requires at least as much
memory to load your board as does your PCB-layout tool, since BoardSim reads most of the
data in the PCB-layout database, and then adds electrical information (like net connectivity) to
it.

BoardSim Session Files

When you run BoardSim, you typically make at least some interactive changes to its database:
you edit the board stackup, interactively assign IC models, edit passive-component values, add
Quick Terminators, and so on. Collectively, these changes are called “session edits”.

So that you do not have to re-specify this information each time you run the program, BoardSim
captures your edits during a session and saves them to a file when you exit or choose to save
them in the middle of a session (select File > Save BoardSim Session File). When you re-load

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Opening BoardSim Boards

the same board in another session, BoardSim reads the edits from the file and automatically
restores them.

This topic contains the following:

• Session File Types - BUD and BBD

• Information Stored in Session Files
• When to Not Save Session Files
• Session Edits for Multiple Board Instances
• When Session Files are Deleted
• Missing Models and Packages

Session File Types - BUD and BBD

BoardSim writes your interactive edits to the “BoardSim User Data” (.BUD) session file.
BoardSim keeps the last two versions of the session file. The .BUD file contains the most recent
set of changes. The .BBD file (backup .BUD file) contains the second most recent set of
changes. When a .BUD file exists and you exit BoardSim or manually save your interactive
changes (select File > Save BoardSim Session File), BoardSim renames the current .BUD file
by changing the file name extension to .BBD, and then writes the new .BUD file.

The .BUD file is named <board_file_name>.BUD, where <board_file_name> is the name of

the board .HYP/.CCE file. Similarly, the .BBD file is named <board_file_name>.BBD. These
files are stored in the same folder as the board file. See “About Design Folder Locations” on
page 1391.

Caution
Mentor Graphics recommends against editing or modifying in any way a .BUD session
file. Only the BoardSim program should ever write this file. The file is described in
“Information Stored in Session Files” on page 57 to help you understand how it
functions.

Information Stored in Session Files

BoardSim saves edits to the following items to the session file:

• Stackup
• Power supplies
• IC and ferrite-bead models
• Passive-component values

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Opening BoardSim Boards

• Passive-component packages
• For IC models, the Vcc-pin and Vss-pin settings
• New components (Quick Terminators)
• Simulation temperature
• Net-by-net batch simulation settings
• Manhattan routing
Restriction: Unrouting changes are not saved in the .BUD file. For example, if you
unroute a net without re-routing it, the unrouting changes will be absent when you
reload your board.
Restriction: For designs containing .EBD models, BoardSim does not save session edits inside
the .EBD models, such as buffer direction or interactive IC model selection.

Caution
The component information in a .BUD session file (that is, all the information other than
the stackup information) is based on reference designators. If you renumber the reference
designators on your board, you will invalidate most or all of the information in your
session file. This may force you to re-enter much of your component data.

When to Not Save Session Files

Normally, you would save the edits you make in a session, so that you do not have to re-make
them the next time you load your board. For example, if in a session you interactively choose IC
models for a number of component pins, you do not want to have to re-choose all the models
next time you run BoardSim.

However, you may not want to save a series of edits that are strictly experimental or “throw-
away”. For example, you might interactively try a series of different driver-IC models,
searching for one that improves a certain simulation waveform. In the end, you might decide
that none of the alternatives is any better than the IC with which you started. When you exit
BoardSim, do not save your edits.

Session Edits for Multiple Board Instances

Your multiple board design may use multiple copies (instances) of a particular board, for
example several identical memory modules that plug into a PC motherboard. BoardSim
MultiBoard projects support multiple instances of a board.

You can make the same interactive changes to all instances of a board or make unique
interactive changes to an individual instance. For example, you might interactively assign an IC
model to all instances. By contrast, you might make an unique interactive change to an
individual instance for the following reasons:

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Opening BoardSim Boards

• To simulate a data bus connecting multiple memory module instances, set data bus pins
on one instance to the output direction and set data bus pins on the other instances to the
input direction.
• To configure a SCSI bus termination, add terminators only to pins on an instance
positioned at the end of the bus.

When Session Files are Deleted

When you first create a given board file, there is no corresponding session file. The session file
is created only after you load the .HYP/.CCE file for the first time, make some edits in
BoardSim, and exit; or load the .HYP/.CCE file, make some edits, and force a session file to be
written (select File > Save BoardSim Session File).

You should not delete a session file unless you truly want to abandon the editing information it
contains.

If you accidentally delete or lose a session file, you can still load the previous backup session
file, saved as a .BBD file.

If you accidentally delete or lose both the .BUD and .BBD session files, you can still reload the
corresponding board: if BoardSim finds no session files, it proceeds assuming there are no edits
to load.

Missing Models and Packages

If the session file has saved some interactive IC-model edits which call out models that no
longer exist, the affected edits are simply ignored and no warning messages given. This
prevents the session file from becoming a barrier to loading a board.

For example, if you interactively choose a number of models from library MY_LIB.MOD; exit
BoardSim so that the choices are recorded in the .BUD file; later (for some reason) delete or
move MY_LIB.MOD; then re-load the board, the "bad" references to the now-missing models in
MY_LIB.MOD will simply be ignored.

Tip: If many IC models recorded in a session file do not “come in” when you re-load a
board, check your Model Library File Path (select Options/Directories) setting. Possibly,
BoardSim cannot find some of the required libraries.

Related Topics
Restore Session Edits Dialog Box
Saving Session Edits for Multiple Board Instances

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Opening MultiBoard Projects

Opening MultiBoard Projects

Open a MultiBoardTM project to run simulation or analysis on a multiple-board design with nets
that span more than one board.

Prerequisites
• For each board to include in the MultiBoard project, meet the prerequisites listed for
opening an individual board. See “Opening BoardSim Boards” on page 54.
• Create a MultiBoard project. See “Creating or Editing MultiBoard Projects” on
page 758.

Procedure
• Open the MultiBoard project:
o Select File > Open MultiBoard Project.
o Select File > Recent Files > <previously_opened_MultiBoard_project>.

Note
Various dialog boxes can appear while the board loads. See “Results” on page 55, “About
Field Solver Messages” on page 56, and “Out-of-Memory Errors” on page 56.

Related Topics
“Simulating Multiple-Board Designs” on page 747
“Post-Layout Workflow” on page 49
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Simulations Overview - Post-Layout Tasks

Simulations Overview - Post-Layout Tasks

This topic shows many of the simulation and analysis tasks you can perform on post-layout
designs and maps them to BoardSim features and Help topics. This information can help you
identify and learn about the BoardSim features needed to perform the simulation and analysis
tasks you have in mind. The Help topics listed in the tables provide detailed information about
setting up and running simulations or analyses, and viewing results.

This topic contains the following:

• Measure Signal Integrity

• Verify Target Impedance
• Measure Timing for DDRx Interfaces
• Verify SERDES Channel Performance
• Verify PDN Performance
• Measure PCB Heating
• Verify Return Current Impedance for Single-Ended Signal Vias
• Export Models for Use in Other Simulations
• Resolve Post-Layout Signal-Integrity Problems with What If Experiments
• Resolve Post-Layout Power-Integrity Problems with What If Experiments

Related Topics
“BoardSim Tutorials” on page 101
“SI QuickStart - BoardSim” on page 85
“QuickStart - Power Integrity” on page 97
“Post-Layout Workflow” on page 49
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47
“Supported SI Models and Simulators” on page 1264
“Run HyperLynx with a Lower Priority” on page 1409

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Simulations Overview - Post-Layout Tasks

Measure Signal Integrity

Find nets with poor signal integrity. See the effects of manufacturing and component tolerances
on signal integrity. You can sometimes improve signal integrity for nets containing impedance
discontinuities by optimizing the termination strategy and terminating component values.

Table 1-2 contains the following tasks:

• Measuring signal quality characteristics - batch simulation

• Measuring signal quality characteristics - interactive simulation
• Measuring signal quality characteristics - sweep simulations
• Measuring crosstalk between signal nets - interactive simulation
• Measuring crosstalk between signal nets - sweep simulations
• Measuring crosstalk between signal nets - including coupled noise from single-ended
signal vias
• Optimizing termination strategy and terminating component values

Table 1-2. Measure Signal Integrity

Task Description
Measuring signal quality characteristics - batch Use batch simulation to scan the entire board
simulation to find nets that fail signal-integrity constraints
and to report numerical measurements. You
can also save batch simulation waveforms and
view them in the oscilloscope.

Example measurements:
• Overshoot for rising and falling edges
• Rise/fall time
• Multiple crossing of receiver thresholds
• flight time
See:
• Batch Analysis of the Entire Board for
Signal-Integrity and Crosstalk Problems
• Analyzing Crosstalk on the Virtex-4 Demo
Board
• Simulating SI for Entire Boards or Multiple
Nets
• Viewing Batch SI Simulation Reports
• Saving Waveform Files From Generic
Batch Simulation
• Loading Waveform Files

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Table 1-2. Measure Signal Integrity (cont.)

Measuring signal quality characteristics - Use the oscilloscope to simulate the net and
interactive simulation measure waveforms.

Example measurements include:

• Overshoot for rising and falling edges
• Rise/fall time
• Multiple crossing of receiver thresholds
• flight time
See:
• Simulating Signal Integrity with the
Oscilloscope
• Measuring Waveforms and Eye Diagrams
Measuring signal quality characteristics - To optimize design tradeoffs and see the
sweep simulations effects of manufacturing tolerances that affect
signal integrity, use the Sweep Manager to set
up sweeps and set the oscilloscope to sweep
mode.

Examples:
• Verify that geometric tolerances caused by
PCB manufacturing, such as stackup layer
thicknesses, do not cause poor signal
integrity.
• Identify passive termination component
value tolerance that produces good signal
integrity.
See:
• Simulating Signal Integrity with Sweeps
• Measuring Waveforms and Eye Diagrams

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Table 1-2. Measure Signal Integrity (cont.)

Measuring crosstalk between signal nets - Use the oscilloscope to simulate the nets and
interactive simulation measure waveforms.

When setting up the design for simulation, you

set the IC driver on victim net(s) to stuck high
(or low) and set the IC driver on the aggressor
net to output (or output inverted). After
simulation, examine victim net waveform(s)
for voltage changes caused by crosstalk.

You can also switch victim/aggressor roles

among the various nets. For example, you can
drive one of the original victim nets and
examine voltage changes on the original
aggressor net and the remaining victim nets.

See:
• Predicting Crosstalk on a Clock Net
• Simulating Signal Integrity with the
Oscilloscope
• Measuring Waveforms and Eye Diagrams
Measuring crosstalk between signal nets - To optimize design tradeoffs that affect
sweep simulations crosstalk, use the Sweep Manager to set up
sweeps and set the oscilloscope to sweep
mode.

For example, verify that geometric tolerances

caused by PCB manufacturing, such as stackup
layer thicknesses, do not cause excessive
crosstalk.

See:
• Simulating Signal Integrity with Sweeps
• Measuring Waveforms and Eye Diagrams

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Table 1-2. Measure Signal Integrity (cont.)

Measuring crosstalk between signal nets - Use the oscilloscope to simulate the nets and
including coupled noise from single-ended measure waveforms.
signal vias
To isolate the effects of coupled noise between
single-ended signal vias, set up the design per
Measuring crosstalk between signal nets -
interactive simulation, but also assign power-
integrity models. Then run a pair of interactive
simulations, one with the “Simulate t-planes”
option enabled and the other with the option
disabled.

See:
• Co-Simulation - Modeling Interactions
Between Signal Vias and Transmission
Planes
• Simulating Signal Integrity with the
Oscilloscope
• Measuring Waveforms and Eye Diagrams
Optimizing termination strategy and Use the Terminator Wizard to automatically
terminating component values find optimal termination component values for
the net.

Use Quick Terminators to add new (but

virtual) passive termination components to the
net.

Use the Sweep Manager to set up sweeps and

set the oscilloscope to sweep mode. For
example, you can use sweeps to find a range of
passive termination component values for the
net that produce good signal quality.

See:
• Optimizing Termination with the
Terminator Wizard
• “About Quick Terminators” on page 935
• Simulating Signal Integrity with Sweeps

Related Topics
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Verify Target Impedance

Find parts of the net topology that contain impedance discontinuities.

Table 1-3 contains the following tasks:

• Measuring impedance for trace segments

• Measuring impedance for signal vias
• Measuring and optimizing characteristic trace impedances for each stackup layer
• Verifying signal via properties
• Optimizing on-die termination (ODT) settings

Table 1-3. Verify Target Impedance

Task Description
Measuring impedance for trace segments Use the Segment Properties dialog box to
display impedance for a trace segment.

See Reporting Net Segment Properties.

Measuring impedance for signal vias Do either of the following:
• Use the Via Visualizer to display the
electrical and geometric properties of vias.
See:
• Visualizing the Geometric and Electrical
Characteristics of a Via
• Viewing and Simulating Signal Vias
• Export BoardSim topologies, including
signal vias, to HyperLynx 3D EM to run 3-
D electromagnetic simulation and generate
an S-parameter model. See “Exporting
BoardSim Topologies to HyperLynx 3D
EM Designer” on page 1165.
Measuring and optimizing characteristic trace Use the Stackup Editor to view the
impedances for each stackup layer characteristic impedance of single-ended and
differential traces.

See Viewing and Planning Impedances and

DC Resistances.

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Table 1-3. Verify Target Impedance (cont.)

Task Description
Verifying signal via properties Use the Via Visualizer to display the electrical
and geometric properties of vias.

For example, you might do this to troubleshoot

a signal-integrity problem or design a
SERDES channel or critical net.

See:
• Visualizing the Geometric and Electrical
Characteristics of a Via
• Viewing and Simulating Signal Vias
Optimizing on-die termination (ODT) settings Find ODT settings that support the target
impedance. Correct ODT settings depend on
whether the IC pin is driving or receiving. The
IBIS IC model must contain the [Model
Selector] keyword.

See:
• “Selecting Models for Programmable
Buffers” on page 475
• “Adding Model Selector Keywords to IBIS
Models” on page 793

Related Topics
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Measure Timing for DDRx Interfaces

Find signals in the DDRx interface that fail timing requirements. Optimize the design to correct
timing failures.

Table 1-4 contains the following tasks:

• Finding nets with timing or signal quality problems

• Optimizing on-die termination (ODT) settings to improve signal quality
• Optimizing passive termination to improve signal quality

Table 1-4. Measure Timing for DDRx Interfaces

Task Description
Finding nets with timing or signal quality Use DDRx batch simulation to create
problems spreadsheets containing pass/fail results and
numerical measurements.

See:
• Simulating DDRx Memory Interfaces
• DDRx Results Spreadsheets
Optimizing on-die termination (ODT) settings Use a series of DDRx batch simulations to
to improve signal quality perform “what if” experiments with different
ODT settings.

See:
• Simulating DDRx Memory Interfaces
• DDRx Wizard - ODT Models Page

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Table 1-4. Measure Timing for DDRx Interfaces (cont.)

Task Description
Optimizing passive termination to improve Prerequisite: Optimize ODT settings before
signal quality optimizing passive termination.

Use a series of DDRx batch simulations to

perform “what if” experiments with different
terminations.

Edit existing passive termination component

values.

Use Quick Terminators to add new (but

virtual) passive termination components to the
net.

Export the net to LineSim, for more control

over the net topology.

See:
• Simulating DDRx Memory Interfaces
• Selecting Models and Values for Individual
Pins
• Selecting Models and Values for Entire
Components
• “About Quick Terminators” on page 935
• “Exporting BoardSim Nets to LineSim” on
page 1161

Related Topics
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Verify SERDES Channel Performance

Find channels with poor performance and reliability. You can also see the effects of different
transceiver pre-emphasis/DFE settings and loss on channel performance.

Table 1-5 contains the following tasks:

• Evaluating the eye diagram for the channel - IBIS-AMI eye diagrams
• Evaluating the eye diagram for the channel - FastEye diagrams
• Evaluating the eye diagram for the channel - standard eye diagrams
• Measuring bit error rate (BER)
• Optimizing pre-emphasis/DFE settings for transceivers
• Measuring loss - surface roughness
• Characterizing PDN, channel, and signal via behaviors in the frequency domain

Prerequisite
Verify the channel does not contain major impedance discontinuities. See Verify Target
Impedance.

Table 1-5. Verify SERDES Channel Performance

Task Description
Evaluating the eye diagram for the channel - Use the IBIS-AMI diagram wizard to create
IBIS-AMI eye diagrams eye diagrams and BER contour charts with
sufficiently long bit streams to produce results
approaching (in statistical accuracy) those
recorded at a test bench using real design
hardware and a BER (bit error rate) tester.

See “Simulating Signal Integrity with IBIS-

AMI Channel Analysis” on page 611.

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Table 1-5. Verify SERDES Channel Performance (cont.)

Task Description
Evaluating the eye diagram for the channel - Use the FastEye diagram wizard to create eye
FastEye diagrams diagrams with sufficiently long bit streams to
produce results approaching (in statistical
accuracy) those recorded at a test bench using
real design hardware and a BER (bit error rate)
tester.

Use the FastEye diagram wizard to

automatically create worst-case bit stimulus
that closes the eye the most and create eye
diagrams with statistical contours.

Verify the eye diagram meets eye mask

requirements.

See:
• Simulating Signal Integrity with FastEye
Channel Analysis
• FastEye Diagram Measurements
• Measuring Waveforms and Eye Diagrams
• Editing Eye Mask Properties
Evaluating the eye diagram for the channel - Use standard eye diagrams to create eye
standard eye diagrams diagrams for channels without linear and time-
invariant (LTI) behavior. In this case, you can
use the FastEye diagram wizard to create the
worst-case bit stimulus and then run standard
eye diagrams with the worst-case bit stimulus.

Verify the eye diagram meets eye mask

requirements.

See:
• Simulating Signal Integrity with the
Oscilloscope
• Measuring Waveforms and Eye Diagrams
• Editing Eye Mask Properties
Measuring bit error rate (BER) Use the FastEye diagram wizard to create
bathtub curves, which help identify valid data
sampling locations by reporting the BER as a
function of the sampling location across the
unit interval at several voltage offsets.

See: Simulating Signal Integrity with FastEye

Channel Analysis

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Table 1-5. Verify SERDES Channel Performance (cont.)

Task Description
Optimizing pre-emphasis/DFE settings for Use the FastEye diagram wizard to
transceivers automatically identify pre-emphasis/DFE tap
weights that open the eye the most.

See:
• Simulating Signal Integrity with FastEye
Channel Analysis
• FastEye Channel Analyzer - Add Pre-
Emphasis/DFE Page
Measuring loss - surface roughness To measure the effects of surface roughness
loss on the eye diagram opening, create a pair
of eye diagrams, one with surface roughness
modeling disabled and the other with surface
roughness modeling enabled.

See:
• Surface Roughness Dialog Box
• Simulating Signal Integrity with FastEye
Channel Analysis
• FastEye Diagram Measurements
• Simulating Signal Integrity with the
Oscilloscope
• Measuring Waveforms and Eye Diagrams

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Table 1-5. Verify SERDES Channel Performance (cont.)

Task Description
Characterizing PDN, channel, and signal via Export a single-ended S-parameter model of
behaviors in the frequency domain the entire PDN and channel, with external
ports at your choice of IC power-supply pin
and signal via locations, and convert it to a
mixed-mode S-parameter model to look for
resonances.

Export a S-parameter models of single-ended

and differential signal vias.

Use the Touchstone Viewer to display the

exported S-parameter model and measure any
of the following:
• Insertion loss—Transmission loss
• Return loss—Reflection
• Coupling—Near-end and far-end crosstalk
• Common mode and differential mode
characteristics for differential signal vias
See:
• Exporting Nets to S-Parameter Models
• Exporting Signal Vias to S-Parameter
Models
• Viewing and Converting Touchstone and
Fitted-Poles Models
• “Cascading Multiple S-Parameter Models
in Series” on page 1105

Related Topics
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Verify PDN Performance

Find poor general and detailed PDN behaviors.

Table 1-6 contains the following tasks:

• Meeting DC power loss and current density requirements

• Optimizing decoupling and stackup properties
• Minimizing plane noise using time domain simulation
• Measuring noise transmitted to the PDN by signal vias
• Characterizing PDN, channel, and signal via behaviors in the frequency domain

Table 1-6. Verify PDN Performance

Task Description
Meeting DC power loss and current density Use DC drop simulation to:
requirements • Measure IR drop and current density
between voltage-regulator module (VRM)
pins and IC power-supply pins.
• Identify stitching vias and power-supply
net geometries with excessive current
density.
See:
• DC Voltage Drop Analysis
• Simulating DC Voltage Drop.

Use DC drop and thermal co-simulation to

include the effects of metal resistivity changes
due to heating on DC drop measurements. Co-
simulation takes into account the heating
caused by current flowing between VRM and
IC power-supply pins.

See “Thermal QuickStart”.

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Table 1-6. Verify PDN Performance (cont.)

Task Description
Optimizing decoupling and stackup properties Use decoupling analysis to:
• Measure power-distribution network
(PDN) impedance over a frequency range.
• Identify capacitors that connect to the PDN
with highly-inductive mounting.
• Optimize the effect of buried capacitance
by editing stackup properties or using
special dielectric materials.
See:
• Analyzing Decoupling
• Decoupling Capacitor Report Spreadsheets
• Creating and Editing Stackups
Minimizing plane noise using time domain Prerequisite: Optimize the impedance profile
simulation before minimizing plane noise. See Optimizing
decoupling and stackup properties.

Use plane noise simulation to:

• Measure plane noise transmitted to the
PDN by IC power-supply pins drawing
large amounts of transient current.
• Identify PDN locations that need better
decoupling.
See Simulating Plane Noise.
Measuring noise transmitted to the PDN by Use the oscilloscope to simulate the net with
signal vias the “Simulate t-planes option” enabled and to
measure waveforms.

See Co-Simulation - Modeling Interactions

Between Signal Vias and Transmission Planes.

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Table 1-6. Verify PDN Performance (cont.)

Task Description
Characterizing PDN, channel, and signal via Export an S-parameter model of the entire
behaviors in the frequency domain PDN and channel, with external ports at your
choice of IC power-supply pin and signal via
locations.

Export an S-parameter model of single-ended

and differential signal vias.

Display the exported S-parameter model with

the Touchstone Viewer and measure any of the
following:
• Insertion loss—Transmission loss
• Return loss—Reflection
• Coupling—Near-end and far-end crosstalk
• Common mode and differential mode
characteristics for differential signal vias
See:
• Exporting Nets to S-Parameter Models
• Exporting Signal Vias to S-Parameter
Models
• Viewing and Converting Touchstone and
Fitted-Poles Models

Related Topics
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Measure PCB Heating

Find overheating problems for components and boards. See Table 1-8.

Table 1-7. Measure PCB Heating

Task Description
Measuring the ability of the board and Show how components and the board dissipate
components to dissipate heat. heat from ICs and other components. You can
optionally co-simulate with DC drop to take
into account the metal heating from current
flowing between VRM and DC sink
component pins.

HyperLynx Thermal can graphical display

simulation results in several ways.
Temperature gradient maps, for example, can
help identify thermal stress points on the
board, which can lead to board warpage or
cracking.

See “Thermal QuickStart”.

Related Topics
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Verify Return Current Impedance for Single-Ended Signal

Vias
Find poor bypass capacitor performance for a single-ended signal via. See Table 1-8.

Table 1-8. Verify Return Current Impedance for Single-Ended Signal Vias
Task Description
Measuring the ability of the PDN to provide Use signal-via bypassing analysis to create a
low-impedance return current paths for signals Z-parameter model that shows return current
transmitted through single-ended vias impedance across a frequency range.

See Analyzing Signal-Via Bypassing.

Related Topics
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Export Models for Use in Other Simulations

Export models from BoardSim to use in LineSim or in third-party simulation software. See
Table 1-9.
Table 1-9. Export Models for Use in Other Simulations
Task Description
Exporting nets, boards, models (such as S- Use various export features to create models.
parameters and SPICE netlists), to simulate or
analyze them with other software See Exporting Design and Model Data.

Related Topics
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Resolve Post-Layout Signal-Integrity Problems with What

If Experiments
Use BoardSim “what if” capabilities to find design changes that resolve signal integrity
problems. For additional “what if” capabilities, you can export signal nets to LineSim for full
control over net topologies.

Table 1-10 contains the following tasks:

• Evaluating different stackup values

• Evaluating different trace widths
• Evaluating different net lengths and trace widths
• Evaluating different termination component values
• Evaluating different termination strategies
• Evaluating different signal via properties
• Evaluating a range of different design property values

Table 1-10. Resolve Post-Layout Signal-Integrity Problems with What If

Experiments
Task Description
Evaluating different stackup values Edit stackup layer thicknesses and electrical
properties.

See Creating and Editing Stackups.

Evaluating different trace widths Edit trace widths.

See Editing Trace Widths in BoardSim.

Evaluating different net lengths and trace Reroute routed nets or route unrouted nets with
widths Manhattan routing. Note that crosstalk
simulation is unavailable for nets with
Manhattan routing.

See Simulating Unrouted Nets with Manhattan

Routing.

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Table 1-10. Resolve Post-Layout Signal-Integrity Problems with What If

Experiments (cont.)
Task Description
Evaluating different termination component Edit existing passive termination component
values values.

Use the Terminator Wizard to automatically

find optimal termination component values.

See:
• Selecting Models and Values for Individual
Pins
• Selecting Models and Values for Entire
Components
• Optimizing Termination with the
Terminator Wizard
Evaluating different termination strategies Use Quick Terminators to add new (but
virtual) passive termination components to the
net.

See Terminating Nets.

Evaluating different signal via properties Compare simulations made with different sets
of via simulation modeling enabled, including
custom via electrical properties.

See What If Simulation Methods for Vias.

Evaluating a range of different design property To optimize design tradeoffs and see the
values effects of manufacturing tolerances that affect
signal integrity, use the Sweep Manager to set
up sweeps and set the oscilloscope to sweep
mode.

Examples:
• Verify that geometric tolerances caused by
PCB manufacturing, such as trace width
and stackup layer thickness, do not cause
poor signal integrity.
• Identify passive termination component
value tolerance that produces good signal
integrity.
See:
• Simulating Signal Integrity with Sweeps
• Measuring Waveforms and Eye Diagrams

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Related Topics
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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Resolve Post-Layout Power-Integrity Problems with What

If Experiments
Use BoardSim “what if” capabilities to find design changes that resolve power integrity
problems. For additional “what if” capabilities, you can export signal nets to LineSim for full
control over PDN topologies, using the PDN Editor.

Table 1-11 contains the following tasks:

• Evaluating different stackup values

• Evaluating different PDN geometries and decoupling
• Evaluating different anti-pad and anti-segment clearances

Table 1-11. Resolve Post-Layout Power-Integrity Problems with What If

Experiments
Task Description
Evaluating different stackup values Edit stackup layer thicknesses and electrical
properties.

Examples:
• Reduce the mounting inductance for a
decoupling capacitor by making the
appropriate dielectric layer(s) thinner (to
shorten the mounting via tube and reduce
loop inductance).
• Improve buried capacitance by making the
appropriate dielectric layer(s) thinner and
using a material with a high dielectric
constant value.
See Creating and Editing Stackups.
Evaluating different PDN geometries and Export the signal net to LineSim and edit PDN
decoupling geometries.

Examples:
• Add an array of decoupling capacitors.
• Add stitching vias to decrease current
density at DC or to decrease signal via
return current bypass impedance.
See:
• Exporting BoardSim Nets to LineSim
• “Defining the Power-Distribution
Network”

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Table 1-11. Resolve Post-Layout Power-Integrity Problems with What If

Experiments (cont.)
Task Description
Evaluating different anti-pad and anti-segment Edit anti-pad and anti-segment clearances. You
clearances might do this to evaluate the effects of metal
etching tolerances during PCB manufacturing.

See Setup Anti-Pads and Anti-Segments

Dialog Box.

Related Topics
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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SI QuickStart - BoardSim
In this QuickStart, you will interactively simulate a net in your design.

To get up and running quickly, perform the steps in the following topics:

• Step 1 — “Opening PCB Designs in BoardSim” on page 85

• Step 2 — “Editing the Stackup” on page 86
• Step 3 — “Mapping Reference Designators to Component Types” on page 87
• Step 4 — “Editing Power-Supply Nets” on page 88
• Step 5 — “Selecting Nets” on page 89
• Step 6 — “Assigning IC Models” on page 89
• Step 7 — “Editing Resistor - Inductor - Capacitor Values” on page 90
• Step 8 — “Identifying Resistor and Capacitor Packages” on page 91
• Step 9 — “Setting Up and Running Interactive Simulations” on page 91
• Step 10 — “View Simulation Results” on page 92
• Step 11 — “Measuring Timing and Voltage” on page 93
• Step 12 — “Recording Simulation Results” on page 95

Opening PCB Designs in BoardSim

BoardSim can open designs that have been translated into ASCII BoardSim board (.HYP/.CCE)
files. The BoardSim board contains the information about your board layout that is relevant to
signal-integrity analysis.

Procedure
1. Translate the design into BoardSim board (.HYP file), performing the instructions
appropriate to the PCB design system you use. You can also export .CCE files from
Expedition PCB.
See also: “Creating BoardSim Boards”
2. Select Setup > Options > Directories. The Set Directories dialog box opens.
3. In the Set Directories Dialog Box, in the .HYP, .TLN, and .FFS file path box, notice the
folder name. You can change the folder.
4. Copy the board file to the folder named in step 3.
5. Open the board:

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• Click Open BoardSim Board .

Note: To load CAMCAD Professional (.CCE) files with the Open BoardSim File
dialog box, change the file type option to CCE Files.

Restriction: The CCE Files option is unavailable when the computer runs a 64-bit
operating system. On Windows, use the 32-bit version of HyperLynx (which is also
installed when you install the 64 bit version) to open CAMCAD files. Select Start >
All Programs > Mentor Graphics SDD > HyperLynx <release> 32-bit > HyperLynx
Simulation Software. By contrast, Linux installations are 64-bit only or 32-bit only.
• Select File > Open Board.
• Select File > Recent Files > <previously_opened_board>.
• Windows computer > Windows Explorer > double-click .HYP file.
6. If completely unrouted nets exist in the BoardSim board, BoardSim asks whether to
route them with Manhattan routing now, click No.
You can create Manhattan routing after opening the PCB design.

< Start Again Next Step >

“SI QuickStart - BoardSim” on page 85 “Editing the Stackup” on page 86

Editing the Stackup

When opening the design, BoardSim electrically validates the stackup information in the board
file. For example, the stackup must contain at least one plane layer, and must not contain layers
with zero thickness. If the stackup is invalid, the Stackup Wizard corrects the errors and
displays the changes it made.

You should manually verify that the stackup is correct, using the stackup editor. Because the
stackup properties affect the impedances of the traces on your board, the stackup directly affects
BoardSim simulation results.

Note
You can export a known good stackup from another BoardSim design and import it into
the current design. You can also import a stackup directly from a LineSim free-form
schematic file (.FFS). See “Exporting and Importing Stackups” on page 1177.

Procedure
1. Click Edit Stackup .
2. Click the Basic tab and review the stackup parameters.

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3. If needed, do any of the following:

• To change a cell value, click in the cell, and then type in a new value or select a new
value from the list.
• To add a layer, click in the first column cell for the layer at which you want to add a
layer, right-click, click Insert Above or Insert Below, and then click the layer type
to add.
• To delete a layer, click in the first column cell for the layer you want to delete, right-
click, and click Delete.
• To move a layer, in the picture pane area, drag the layer to the new position.
4. Click OK.

< Start Again Next Step >

“SI QuickStart - BoardSim” on page 85 “Mapping Reference Designators to
Component Types” on page 87

Mapping Reference Designators to Component Types

When opening the design, BoardSim examines the reference designator prefix for each device
to map it to a component type, such as IC, R, L, C, and ferrite bead. The prefix is the first part of
the reference designator that stays the same for components of the same type.

Example: If the reference designator for all IC components on the board starts with U, such as
U1, U4B, and so on, then U is the prefix for ICs. Resistors commonly have the prefix R.

If needed, you can change the default mapping between prefixes and component types. See
“About Reference-Designator Mapping in BoardSim” on page 209.

Procedure
1. Select Setup > Options > Reference Designator Mappings. The Edit Reference
Designator Mappings Dialog Box opens.
2. Review the mapping.
3. To edit a mapping, select the prefix in the Mappings list, and then click the component
type.
4. To add a mapping, type the new prefix in the Ref. prefix box, and then click the
component type.
5. Click Add/Apply if changes are made.
6. Repeat steps 3-5 as needed, and then click OK.

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7. If you changed the mapping, you need to save the mapping and re-open the board
because mapping changes take effect the next time you open the board. Do the
following:
a. Select File > Open Board. Click Yes when prompted to save session edits.
b. In the Open BoardSim File dialog box, select the BoardSim board (.HYP/.CCE file),
and then click OK.

< Start Again Next Step >

“SI QuickStart - BoardSim” on page 85 “Editing Power-Supply Nets” on page 88

Editing Power-Supply Nets

When opening the design, BoardSim identifies power-supply nets by net name and by counting
how many capacitors are on the net. If BoardSim does not automatically identify all the power-
supply nets, use the power-supply editor to manually identify them.

Identifying power-supply nets is important because BoardSim treats a power supply as a DC

voltage. For example if the power-supply side of a pull-up resistor is mistaken for a non-power-
supply net, BoardSim simulates the resistor as a series terminator instead of a parallel
terminator. Also, the Vcc and Vss pins on an IC can only be attached in BoardSim to nets
identified as power supplies.

Click a column header in the spreadsheet to sort the rows. Clicking the blank column header
sorts by check boxes.

Procedure
1. Select Setup > Power Supplies. See “Identifying Power-Supply Nets - BoardSim” on
page 345.
2. To add a power-supply net to the Edit Supply Voltages spreadsheet, select its check box
in the Select Supply Nets spreadsheet.
To filter the nets displayed by the Select Supply Nets spreadsheet, type the filter string
into the Filter box and click Apply. Use the asterisk * wildcard to match any number of
characters. Use the question mark ? wildcard to match any one character.
3. To edit a power-supply voltage, click in the Voltage cell and type the new voltage.
4. To map a plane layer in the stackup to a power-supply net, select the net from the Supply
Net cell. This information is used by power-integrity simulation and not used by signal-
integrity simulation.
5. Click OK.

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< Start Again Next Step >

“SI QuickStart - BoardSim” on page 85 “Selecting Nets” on page 89

Selecting Nets
For interactive simulation, you select an individual net to simulate it.

Procedure
1. Click Select Net by Name or Select Select > Net by Reference Designator.
Named nets are easiest to choose by name and unnamed nets are easiest to choose by
reference designator.
2. Double-click the net or pin name.

< Start Again Next Step >

“SI QuickStart - BoardSim” on page 85 “Assigning IC Models” on page 89

Assigning IC Models
To simulate the net, a driver IC must be assigned to the net. You can also add ICs to other
drivers or receivers on the net. BoardSim treats as electrically open any drivers or receivers
without ICs.

Procedure
1. Click Select Component Models or Edit Values .
2. In the Pins list, select and then double-click a reference designator and pin.
3. In the Select IC Model dialog box, in the Libraries list, select a library file.
To display only one library type, click the library type to the left of the Libraries list.
To display a set of basic technology models, click the TECH.MOD button.
To display a set of generic technology models, click the GENERIC.MOD button.
4. In the Devices list, select a device.
5. If available, select a pin or signal in the Signal or Pin list.
6. Click OK.
7. In the Assign Models dialog box, set the buffer direction in the Buffer area.

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8. Verify the voltages in the Vcc pin and Vss pin lists are correct.
9. Repeat steps 2-8, as needed, for other IC pins on the net.
Requirement: Set only one driver on the net to the output state. If you assign models to
other drivers on the net, set them to the input state or the output high-impedance state.
Signal-integrity simulations require only models for device families, not specific
devices, since only output-buffer and input-stage characteristics need to be modeled.
There is another way to specify IC models, based on an ASCII automapping file, which
automatically loads models component-by-component. See “Selecting Models and
Values for Entire Components” on page 296.
10. Click Close.

< Start Again Next Step >

“SI QuickStart - BoardSim” on page 85 “Editing Resistor - Inductor - Capacitor
Values” on page 90

Editing Resistor - Inductor - Capacitor Values

When opening the design, BoardSim identifies resistor and capacitor values from data provided
by your PCB-layout tool. If BoardSim is not given the correct values, you need to manually
modify them.

Procedure
1. Click Select Component Models or Edit Values .
2. In the Pins list, select a resistor, inductor, or capacitor.
3. If needed, type a new value into the Value box.
4. Repeat steps 2-3 as needed.
For ferrite beads, you load a model rather than setting a simple value.
5. Click Close.

< Start Again Next Step >

“SI QuickStart - BoardSim” on page 85 “Identifying Resistor and Capacitor Packages”
on page 91

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Identifying Resistor and Capacitor Packages

When opening the design, BoardSim identifies resistors and capacitors that reside in packages
together with other Rs or Cs, rather than being discrete. If BoardSim cannot properly identify
the package style or internal connectivity of the packaged Rs or Cs, you manually identify them
with the package editor.

If your design does not contain resistor or capacitor package, go to the next step.

Procedure
1. Click Select Component Models or Edit Values .
2. In the Pins list, double-click the R or C reference designator.
hen you select a reference designator associated with a component package, the
Connectivity area appears above the Copy button.
3. In the Select Package dialog box, set the package and connectivity.
4. Repeat steps 2-3 as needed.
5. Click OK.

< Start Again Next Step >

“SI QuickStart - BoardSim” on page 85 “Setting Up and Running Interactive
Simulations” on page 91

Setting Up and Running Interactive Simulations

You use the oscilloscope to launch interactive simulation and view simulation results.

Procedure
1. Click Run Interactive Simulation (SI Oscilloscope) .
2. In the Driver waveform area, do one of the following:
• If you want a single-edge stimulus, click Edge.
This choice is better when you are trying to isolate transmission-line effects, since
you can study how a transition settles out without the possibly confusing effects of
additional transitions.
• If you want an oscillator stimulus, click Oscillator, type the frequency value in
megahertz into the MHz box, and then type the percentage of the period that the
driver is high in the Duty box.
This choice is better for studying the standing-wave effects of repetitive stimulus.

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You can also use the oscilloscope to define one or more sets of driver stimulus (that is,
driver waveforms) and assign them to nets or pins on the board or schematic. See
“Setting Up Driver Stimulus” on page 539.
3. In the IC modeling area, click the appropriate IC operating parameter.
4. Click Start Simulation.
Result: Simulation waveforms appear in the main screen.
5. To show or hide waveforms, select or clear the check boxes next to the pin name in the
probe spreadsheet.
To see simulations using two IC operating parameters, select the Previous results check box,
select one IC operating parameter, run the simulator, select another IC operating parameter, and
then run the simulator again. The oscilloscope displays the waveforms for the latest and
previous simulations.

< Start Again Next Step >

“SI QuickStart - BoardSim” on page 85 “View Simulation Results” on page 92

View Simulation Results

You can examine the simulation waveforms more closely by adjusting the oscilloscope settings
described in Table 1-12.

Table 1-12. View Simulation Results - QuickStart for BoardSim

How do I? Do this
Zoom in on a waveform region Click the Zoom button, position the mouse pointer over
one corner of the zoom box you want to create, drag to
define the other corner of the zoom box, and then
release the mouse button.

To display all the waveforms again, click the Fit to

Window button.
Resize the oscilloscope window Drag a corner or an edge of the window with the mouse
Set the horizontal time scale Click an arrow button beside the Horizontal Scale box
Set the vertical voltage scale Click an arrow button beside the Vertical Scale box

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Table 1-12. View Simulation Results - QuickStart for BoardSim (cont.)

Set the vertical position (GND Type a value in the Vertical Position box and press
Offset) Enter.

Use the vertical position control to shift the waveforms

in the main screen up or down relative to the grid. By
contrast, the vertical scroll bar moves the grids,
waveforms, and ground line up and down together.

The vertical position controls create a voltage offset by

adding or subtracting voltage to, or from, your
simulation data. When changing the vertical position,
the grids remain stationary while the waveforms and
ground line move up and down. Additional grids will
be created if necessary to display the waveforms with
the new vertical position setting. The allowed vertical
position range is plus/minus five divisions with a
precision of 1/10 division.
Scroll vertically Use the vertical scroll bar to move the grids,
waveforms, and ground line up and down together. By
contrast, use the vertical position control to shift the
waveforms in the main screen up or down relative to
the grid.

The vertical scroll bar is useful when you have zoomed

in on the vertical scale and some portion of the
waveforms falls outside the main screen.
An overview screen is available to help you visually relate the waveforms displayed in the main
screen to the entire simulation. It is positioned below the main screen and enabled by the
Overview pane check box. The portion of the overall simulation displayed in the main screen is
marked by a green hatched pattern in the overview screen.

< Start Again Next Step >

“SI QuickStart - BoardSim” on page 85 “Measuring Timing and Voltage” on page 93

Measuring Timing and Voltage

You can measure timing and voltage on waveforms already displayed in the Digital
Oscilloscope dialog box automatically or manually by using the pointer or measurement
crosshairs.

Procedure
1. To automatically measure waveforms:
a. In the Measurements area, do one of the following:

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• To measure across the entire simulation, click Entire.

• To measure within a window of time that you specify, click Region, position the
mouse pointer over one corner of the measurement box you want to create, drag
to define the other corner of the box, and then release the mouse button.
If the circuit exhibits a behavior that can distort the measurement, such as a capacitor
charging during design power-up, specifying a waveform region enables you to
specify a valid measurement window.
Restriction: The Region measurement region option is unavailable for eye
diagrams.
b. Select the waveform to measure from the Waveform list.
Waveform names correspond to the names in the probe spreadsheet. Because the
oscilloscope can display latest, previous, and loaded versions of a waveform for non-
eye diagrams, waveform names in the Waveform list include the simulation version.
c. Click a measurement button.
Click the arrow the right of the measurement button, if it exists, to review and edit
measurement options.
2. To manually measure waveforms with the pointer, move the pointer over the waveform
and read the voltage and time information displayed in the Cursors area.
3. To manually measure waveforms with measurement crosshairs, click over the waveform
to add the measurement crosshair and display its voltage and time information in the
Cursors area.
If you click again, another measurement crosshair appears and the delta voltage, delta
time, and slope (slew rate) information appears in the Cursors area. If you click a third
time, all measurement crosshairs disappear.

Attaching Measurement Crosshairs to Waveforms

You can make precise measurements by attaching measurement crosshairs to a waveform.

Procedure
1. In the Cursors area, click the Track Waveform button.
2. Click the waveform to attach the first measurement crosshair.
3. Position the measurement crosshair exactly where you want to make a measurement,
and then click.
Result: The measurement crosshair locks in place and its voltage and time appear in the
Cursors area next to Pt1. A new measurement crosshair appears and attaches to the same
waveform.

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4. To measure a delta voltage, delta time, or slope, do one of the following:

• To make another measurement on the same waveform, position the new
measurement crosshair exactly where you want to make a measurement, and then
click.
• To make the measurement between the current waveform and another waveform,
click the Track Waveform button twice, click the second waveform, position the
measurement crosshair exactly where you want, and then click.
Results:
• The second measurement crosshair locks in place and its voltage and time appear in
the Cursors area next to Pt2. The time and voltage differences between the two
measurement crosshairs appear next to Delta V, Delta T, and Slope.
• A new white measurement crosshair appears and it is attached to the selected
waveform.
To turn off waveform tracking and remove the measurement crosshairs:

1. Click the Track Waveform button until it is disabled.

2. Click in the screen until the measurement crosshairs disappear.

< Start Again Next Step >

“SI QuickStart - BoardSim” on page 85 “Recording Simulation Results” on page 95

Recording Simulation Results

You can print the waveforms, copy an image of the waveforms to the Windows Clipboard (in
order to paste the image into other Windows applications), or save the waveform data to a
comma-separated-value (CSV) text file.

Procedure
1. To add a description or comment to the simulation results, type the text into the
Comment box near the top of the oscilloscope.
2. Do any of the following:
• To print the simulation results, click Print.
• To copy the waveform image to the clipboard, click Copy to Clip.
• To save the waveform data to a CSV or HyperLynx .LIS file, click Save/Load.

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< Start Again

“SI QuickStart - BoardSim” on page 85

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QuickStart - Power Integrity

Use the QuickStarts listed in Table 1-13 to become familiar with basic power-integrity set up
and simulation.
Table 1-13. Power-Integrity Applications
Analysis Type Design Issue
Decoupling Analysis • Identify the minimum number of capacitors needed to meet the
QuickStart - BoardSim PDN target impedance
• Identify capacitors that connect to the PDN with highly-
“Decoupling Analysis inductive mounting
QuickStart - LineSim” • Identify optimum capacitor locations, in a manual PDN
planning or “what if” scenario
• Quantify benefits of new technologies. Embedded capacitance
technologies include C-ply and ultra-thin and high Er dielectric
materials. Via and IC mounting technologies include via-in-pad
and microvias.
Plane Noise Simulation • Understand how noise propagates across plane regions of the
QuickStart - BoardSim power-distribution network (PDN) when power-supply pins
draw large amounts of transient current
“Plane Noise Simulation • What is the maximum induced noise voltage?
QuickStart - LineSim” • Which areas of the planes need more capacitors?
DC Drop QuickStart - • Not enough voltage getting to ICs power-supply pins from
BoardSim VRMs, which leads to IC malfunction
• High current densities in voltage island neckdowns which leads
“DC Drop QuickStart - to dielectric breakdown, board failures, fires
LineSim” • Too much current in stitching vias connecting islands which
leads to via failure (disconnected power)
SI and PI Co-Simulation • View, in the HyperLynx PI PowerScope, the effects of the
QuickStart - BoardSim signals radiating into the planes from vias
• View, in the HyperLynx PI PowerScope, the effects of the
“SI and PI Co-Simulation power-distribution network (PDN) on noise radiated from vias
QuickStart - LineSim” • View, in the Digital Oscilloscope, the effect on the signals from
the via-PDN interaction

Related Topics
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

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SI and PI Co-Simulation QuickStart - BoardSim

Run signal-integrity simulations with enhanced accuracy by enabling signal-via models that
interact with transmission-plane structures in the design. This capability is called “co-
simulation” because it uses both signal-integrity and power-integrity circuit modeling and
simulation engines.

When signals from IC driver pins propagate through vias that penetrate transmission planes, the
vias radiate and generate noise between the planes. This noise can reduce the quality of the
incident signal and produce crosstalk in nearby signal and stitching vias. The energy radiated by
the signal propagating through the via provides all plane-noise stimulus; co-simulation ignores
AC signal-integrity models. Co-simulation takes into account the sets of transmission planes
connected by stitching vias.

Procedure
1. Open a BoardSim board.
• Select File > Open Board. See “Creating BoardSim Boards”.
2. Identify power-supply nets.
a. Select Setup > Power Supplies. The Edit Power-Supply Nets dialog box opens. See
“Identifying Power-Supply Nets - BoardSim” on page 345.
Verify that BoardSim has correctly identified all the power-supply nets. The
automatic identification algorithm can miss power-supply nets with arbitrary names
and few capacitor connections. This verification requirement includes both power
and ground nets.
b. In the Assign Supply Nets To Plane Layers area, assign at least two different power-
supply nets.
c. Click OK.
3. Set up stackup layer thicknesses and material properties.
• Select Edit > Stackup > Edit. See “Creating and Editing Stackups” on page 353.
4. Assign decoupling capacitor values or models.
a. Create groups of decoupling capacitors. This enables you to assign values or models
to many capacitors at the same time.
i. Select Models > Edit Decoupling-Capacitor Groups. The Assign Decoupling-
Capacitor Groups Dialog Box opens.
The left spreadsheet contains capacitors that have not been assigned to a
capacitor group. The right spreadsheet contains capacitor groups. BoardSim
automatically assigns decoupling capacitors with the same capacitance and
maximum pin-to-pin dimensions to the same group.

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ii. To assign a capacitor to a group, click the row header for the capacitor, click the
row header for the existing or <new> group, and then click >>.
iii. Click OK.
b. Assign values or models to decoupling capacitors or capacitor groups
i. Select Models > Edit Decoupling-Capacitor Models. The Assign Decoupling-
Capacitor Models Dialog Box opens.
ii. Double-click the spreadsheet row for a group or an individual capacitor. The
Assign / Edit Capacitor Model Dialog Box opens.
iii. Assign values or a model and click OK.
iv. Repeat steps ii-iii to assign models to remaining decoupling capacitors.
v. Click Close.
5. Assign AC sink models, VRM models, and reference nets.
a. Select Models > Assign Power Integrity Models. The Assign Power Integrity
Models Dialog Box - IC Tab opens.
b. To filter the spreadsheet contents, to make it easy to find key power-supply nets or
reference designators, do any of the following:
• Type a string in the Reference Designator box and click Apply.
• Type a string in the Power-Supply Net box and click Apply.
• Select an item in the Component Types list.
The filter boxes support wildcard characters. Use the asterisk * wildcard to match
any number of characters. Use the question mark ? wildcard to match any one
character.
c. Select one or more spreadsheet rows containing IC power-supply pins that you want
to assign a model or reference net to.
To select a block of rows, drag over the row headers. To select non-adjacent rows,
press Ctrl+Click over the row headers.
d. Click Assign in the appropriate model type area and perform the procedure in one of
the following topics:
• Assign Power Integrity Models Dialog Box - IC Tab
• Assign VRM Model Dialog Box
• “Set Reference Nets Dialog Box” on page 1858
See “About Power-Integrity Models” on page 349.
6. Simulate.

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a. Select Simulate SI > Run Interactive Simulation. The Digital Oscilloscope opens.
b. To perform co-simulation, select the Simulate t-planes check box.
c. Set up and run the simulation. See “Simulating Signal Integrity with the
Oscilloscope” on page 533.

Related Topics
“Setting Up Designs for Power-Integrity Simulation” on page 341
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47
“SI and PI Co-Simulation QuickStart - LineSim”

Simulations Overview - Pre-Layout Tasks

Please click “Simulations Overview - Pre-Layout Tasks“.

Note
Clicking the preceding link is a workaround because the Help menu can directly open this
topic only when a schematic is loaded.

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 Chapter 2
BoardSim Tutorials

This chapter walks you through how to use BoardSim to analyze a design after PCB placement
and routing, and perform a system analysis of a multiple-board design. In the process, you will
become familiar with BoardSim simulation and analysis features, as well as the graphical user
interface.

You can perform BoardSim signal-integrity simulations interactively for a selected signal net or
in batch mode for a large number of signal nets. Similarly, you can perform DC voltage drop
simulations interactively for a selected power-supply net or in batch mode for a large number of
power-supply nets.

Some of the designs contain very old signaling technology and circuit geometries. However, the
object of the tutorials is to show you how to use HyperLynx features.

Table 2-1 summarizes the goals and contents of the tutorials in this chapter.

Table 2-1. BoardSim Tutorials

Tutorial Description
Batch Analysis of the Entire Board Use the Quick Analysis feature in batch simulation to scan
for Signal-Integrity and Crosstalk the entire board for likely signal-integrity and crosstalk
Problems problems.

Use the detailed simulation feature in batch simulation to

run automated signal-integrity and crosstalk simulation on
a group of nets and write the results to a spreadsheet.

Run the Terminator Wizard to automatically identify and

apply optimum passive termination component values for a
selected net.

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Table 2-1. BoardSim Tutorials (cont.)

Tutorial Description
Predicting Crosstalk on a Clock Use electrical crosstalk thresholds to display the nets that
Net act as crosstalk aggressors to the selected clock net.

Use the Digital Oscilloscope (“oscilloscope” from now on)

to interactively simulate selected and aggressor nets to
measure crosstalk voltage on the clock waveform.

Use the Quick Analysis feature in batch simulation to

report the approximate crosstalk voltage received by the
clock net.

Use the detailed analysis feature in batch simulation to

report more-accurate crosstalk voltage received by the
clock net.
Advanced Via Modeling Use the oscilloscope to see the effects of via modeling
choices on simulation waveforms.
Visualizing the Geometric and Use the Via Visualizer to display the electrical and
Electrical Characteristics of a Via geometric characteristics of a differential via pair in the
board.
Checking the Signal Quality of a Use MultiBoard to simulate signal integrity for a net that
Net Crossing Two Boards spans more than one board in a multiple-board system.
Interactively Simulating the clk Use the oscilloscope to interactively simulate a clock net
Net on a synchronous design and measure signal-integrity
properties on waveforms.

Reduce overshoot and high-frequency waveform content

by running the Terminator Wizard to automatically identify
and apply optimum passive termination component values.

Assign an IC model to a reference designator for an IC

component. Assign IC models to individual IC pins.
Analyzing a Board Before Routing Use Manhattan Routing to perform “what if” experiments
to predict the effects of routing, re-routing, or component
repositioning.

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Table 2-1. BoardSim Tutorials (cont.)

Tutorial Description
DC Voltage Drop Analysis Use DC voltage drop simulation to see the IR drop (voltage
drop) and current density across power-supply nets. These
capabilities help you see the effects of IC and connector
pins drawing large amounts of current through power-
supply nets at DC operating conditions.

Assign voltage-regulator module (VRM) models and DC

sink models to component pins on the board.

Use the Reporter dialog box to see a textual report showing

current and voltage at pins with VRM and DC sink models
assigned to them.

Use the HyperLynx PI PowerScope to see a 3-D view of

current and voltage distributions across power-supply nets.
Xilinx Virtex-4 Technology Reference Board Tutorials
Analyzing Crosstalk on the Use the oscilloscope to interactively simulate selected and
Virtex-4 Demo Board aggressor nets to measure crosstalk voltage on a DDR
strobe signal.

Use the Quick Analysis feature in batch simulation to

identify nets with excessive crosstalk.
Locating Signal Quality and Use batch simulation and MultiBoard to report signal
Timing Problems Using Batch quality and timing problems on the multiple-board Xilinx
Mode Simulation reference design with Virtex-4 technology.

Compare batch simulation and interactive simulation

results.

Reduce overshoot by using a half-strength driver and

applying a Quick Terminator.

Restore Original Tutorial Design and Model Files

You can make changes to the tutorial designs and save them. To restore the original tutorial
design or model files, extract them from tutorial_golden_files.zip, which is located in the same
folder as the HyperLynx executable file (bsw.exe). Example locations:

\MentorGraphics\<release>\SDD_HOME\hyperlynx\tutorial_golden_files.zip
\MentorGraphics\<release>\SDD_HOME\hyperlynx64\tutorial_golden_files.zip

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Batch Analysis of the Entire Board for Signal-Integrity and Crosstalk Problems

Related Topics
“Getting Started with Post-Layout Design Simulation - BoardSim” on page 47

Batch Analysis of the Entire Board for Signal-

Integrity and Crosstalk Problems
BoardSim includes a batch-mode feature which allows you to analyze or simulate all of the
signal nets on your entire PCB in a single operation. The step-by-step batch wizard offers two
ways to perform analysis:

• A set of quick-analysis features that can run a fast analysis on an entire PCB, scanning
for likely signal-integrity and crosstalk problems
• Detailed-analysis features which perform automated simulations on a selected set of
nets, reporting accurate flight times for each net and analyzing in detail for other
parameters, such as overshoot, threshold violations, and crosstalk. You can
automatically check many of these parameters against user-defined violation limits,
which, for example, can flag nets with out-of-range delays, excess overshoot, or
crosstalk, and so forth.
In traditional, synchronous designs, PCB clock nets are typically the most critical in terms of
signal-integrity and crosstalk. SERDES-based designs do not use clock signals, but this tutorial
is based on a traditional, synchronous design. This example demonstrates how BoardSim can
help you check the clock and other edge-sensitive nets on a board, based on the actual routed
layout. BoardSim addresses the problems that can only be found after PCB layout. For example,
even a properly designed net can be negatively affected by the layout process, such as if the
trace length is not constrained properly during routing, or the router cannot meet a set
constraint, or if a net wanders through too many vias. Pre-planning nets beyond those that are
truly critical can also be a difficult task.

Note that you can prevent many of the problems included in this example by using LineSim.
LineSim is an excellent tool for solving signal-integrity and crosstalk problems before you
begin PCB layout. Problems such as clock nets that are improperly designed can be solved up-
front, before time is invested in board layout.

Prerequisites
The MultiBoard license is required to load and analyze multiple-board designs.

The Crosstalk license is required to run crosstalk simulation.

Third-party application software, such as Microsoft Excel, that can open Excel-formatted .XLS
spreadsheet files.

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Batch Analysis of the Entire Board for Signal-Integrity and Crosstalk Problems

Board Description
The demonstration board used in this example is a very simple mixed-technology PCB using
through-hole and surface-mount devices. Trace widths are fairly large and the board is not
completely routed. The demo board is deliberately small to facilitate this tutorial.

The PCB size that can run on BoardSim is limited only by the amount of memory in your
computer.

1. Close any open dialog boxes.

2. Select File > Open Board > double-click demo.hyp.
When prompted to restore session edits, click OK.
Loading time depends on the size of the board. Since demo.hyp is very small, loading
takes only a few moments.
The board viewer provides a convenient way to view your board. It also includes special
features not found in PCB layout tools that appeal to electrical engineers. See Viewing
BoardSim Boards for details on these features.
The viewer is currently showing the entire layout of the demo board including the
routing for each net, as well as the PCB outline, component outlines, and reference
designators.
3. Run batch quick analysis.
a. Select Simulate SI > Run Generic Batch Simulation. The Batch Mode wizard
dialog box opens.
b. Set the options on the first page of the wizard as follows:
i. In the Detailed Simulations area, disable both options.
ii. In the Quick Analysis area, enable the first six options and disable the remaining
options.

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c. Click Next three times to view the Batch Mode Setup - Default IC Model Settings
page.
d. Set Rise/fall time to 0.5 ns.
Instead of specifying specific IC models for the nets on the PCB, this example uses
the Default IC Model Settings page to allow the simulation to assume that any nets
not populated with models have driver ICs with approximately 0.5 ns switching
times. On this board, some nets have models assigned, but others do not. The ability
to assign default IC characteristics allows you get results quickly, even before
making detailed model assignments.

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e. Click Next four times, until the Run Simulation and Show Results page appears.
f. Click Finish. If asked whether to overwrite a previously generated report files, click
Yes.
The quick analysis of the batch wizard runs. Because the demo board is small, the
analysis takes only seconds to complete, even though it includes every net on the board.
When the simulation is complete, the HyperLynx File Editor opens and displays the
output.
4. View the batch quick-analysis output.
When opened by the batch wizard, the file viewer has special searching capabilities for
finding signal-integrity violations. This step demonstrates how to search for warnings
flagged by the Quick-Analysis simulation.
a. In the file viewer, click Find Warning. The viewer jumps to the first location of
the text warning.
b. Click Find Warning several more times. The Viewer jumps to various nets that are
likely to have signal-integrity problems because they are physically long and have
no termination, or have non-optimal terminating-component values.
You can use the batch wizard to automatically identify problem nets, and as a guide
to further detailed analysis and problem fixing.
c. In the file viewer, select Edit > Find.
d. In Find What, type datald.
e. Enable Wrap around search.

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f. Click Find Next.

The viewer jumps to the section corresponding to net datald. Here the batch engine
is reporting that net datald has no terminator. Given the default rise/fall time of 0.5
ns, net datald is too long to remain unterminated. The wizard gives a suggestion for
the maximum length of the net, if it remains unterminated.
g. Close the file editor.
5. Run a detailed batch analysis of critical nets.
Compared to the quick-analysis features, the detailed simulations offer an additional
level of accuracy that can report detailed minimum and maximum flight times,
overshoots, threshold violations, and crosstalk levels at every receiver-IC pin on a net.
An actual PCB includes a much larger set of nets than are included in this tutorial.
However, even one or two nets are enough to show how the batch detailed simulations
work.
For detailed simulation, the Board Wizard is capable of performing not only signal-
integrity, but also crosstalk analysis. This step focuses on the signal-integrity features.
See “Predicting Crosstalk on a Clock Net” on page 118 for an exercise using the
crosstalk features.
In general, batch-mode signal-integrity simulations are run for two major reasons. One
is to find the minimum and maximum delays, or flight times, on a collection of nets.
This makes sense because digital design is heavily centered on timing, and with tighter
margins, including the effects of interconnect delays in timing budgets is important. The
second reason is to scan for non-timing issues such as overshoot or crosstalk that can
compromise signal-integrity. You can look for both types of issues simultaneously using
the BoardSim batch feature.
6. Improve signal integrity before running batch simulation.
Before running a batch simulation, it is a good idea to improve the signal quality on the
net so that the simulation results are realistic. This step demonstrates how to calculate
accurate timing delays, and locate non-timing signal-integrity issues.
a. Interactively assign an IC model to U3, pin 20.
i. Select Select > Net by Name for SI Analysis. The Select Net by Name dialog
box opens.
ii. In the list of nets, double-click datald. The dialog box closes.
In the board viewer, only the net datald appears. All other board routing is
dimmed in the background. The only net that appears at full intensity is the
selected net.

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iii. Select Models > Assign Models/Values By Net. The Assign Models dialog box
opens.
iv. In the Pins list, double-click U3.20. The Select IC Model dialog box opens.
v. In the Libraries list, select easy.mod to select the library of HyperLynx-supplied
generic technology models.
vi. In the Devices list, select the model CMOS,5V,FAST and click OK.

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vii. In the Assign Models dialog box, set the Buffer Settings to Output.

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viii. Click Close. U3, pin 20 is now modeled as a fast 5V CMOS driver.
b. Select Simulate SI > Optimize Termination. The Terminator Wizard
automatically identifies and applies the optimal termination to improve the signal
integrity on net datald.
The wizard recommends adding a series terminator to the net to improve signal
quality. In cases where a terminator is recommended but is not present in the routed
design, the Terminator Wizard can add the terminator to the simulation circuit, with
the appropriate component value using Quick Terminator.
c. Click Apply Values to add the terminator to net datald.

d. Click OK to close the wizard.

7. Calculate flight times for net datald by running batch mode simulations using the
detailed simulation feature in the Board Wizard for signal-integrity simulation only. For
output reporting, choose the XLS file.
a. Select Simulate SI > Run Generic Batch Simulation. The first page of the Wizard
opens.

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b. In the Detailed Simulations area, select Run signal-integrity and crosstalk

simulations on selected nets and deselect Run EMC simulations on selected nets.
c. In the Quick Analysis area, disable all of the Quick Analysis features.

d. Click Next to display the Select Nets and Constraints for Signal-Integrity Simulation
page.
e. Click SI Nets Spreadsheet. This opens a spreadsheet in which you can select nets
for detailed signal-integrity analysis and set constraints for them. Re-size the
spreadsheet, if needed.
All of the nets on the PCB are listed in alphabetic order. Locate net datald, near the
top of the list.
f. Select the check box in the SI Enable column and the datald row. When you make
the selection, the previously grayed-out cells associated with the selected net turn
white and activate.

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This example looks at the min/max interconnect delays in the output report of the
batch feature.
g. Change the Max. Rise Static Rail Overshoot and Max. Fall Static Rail Overshoot
values to 1000 mV to allow 1 V of margin.
h. Click OK to close the spreadsheet.
i. In the wizard, click Next. The Set Driver/Receiver Options for Signal-Integrity
Analysis page opens.
j. In the I/O and open-drain model area, de-select Driver “round robin”.
k. In the IC-model corners area, select Fast-Strong, Typical, and Slow-weak.
l. In the IC-model Voltage References Area, select Always use model’s internal
values and When simulating, vary voltage reference values with IC corners.
m. Click Next. The Set Delay and Transmission-Line Options page opens.
n. In the Delay calculations area, select Flight-Time Compensation.
o. Click Next two times. The Set Options for Crosstalk Analysis opens.
p. In the Crosstalk analysis - detailed simulations area, de-select Crosstalk simulation.
q. Click Next two times, making no more changes until you move to the Select Audit
and Reporting Options page.
r. In the Audit options area, select Run batch simulation only (no audit).
s. In the After completion, automatically open area, de-select summary report file
and select detailed *.XLS report file.
t. Click Next. The Run Simulation and Show Results page opens.
u. Click Finish. If asked whether to overwrite a previously generated report files, click
Yes.
This step performed the following:
• Enabled detailed simulation on net datald.
• Enabled simulation at all IC operating corners (that is, the batch engine is set to run
three sets of simulations, one with the IC models in their Fast-Strong settings, one in
Typical, and one in Slow-Weak). This produces valid, worst-case minimum and
maximum delays in the output report.
• Enabled Flight-time Compensation, meaning that for each driver-to-receiver pin pair
in the output report, the delays automatically have the time-to-Vmeas value for the
driver subtracted. This means that the flight times can be added directly to a timing
spreadsheet.

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The delays reported in signal-integrity simulations are intended to represent the

interconnect delays between drivers and receivers on your routed PCB. You can add
these delays to your timing spreadsheet to make your calculations more accurate.
However, there is a possible problem: the Tco (clock-to-output) delays for driver ICs
in the spreadsheet already contain built-in delays that represent what happens
outside the IC when it drives a load.
Additionally, the built-in delay takes the form of a reference load, such as a 15-pF
capacitor, that does not match the actual transmission-line load on the board.
Increasing the value of Tco in the spreadsheet causes the inclusion of two output
loads. This means the simulation includes the effects of both the real transmission
line load, as calculated by BoardSim, and the reference load, which is assumed by
the IC vendor in the datasheet Tco.
Enabling Flight-Time Compensation in the wizard eliminates this problem because
the flight-time option causes the BoardSim batch engine to automatically determine
how much reference-load delay is present for the Tco of each driver, and subtract
this value from all reported delays. The reference-load delay is sometimes called the
time-to-Vmeas value for the driver. With this compensation in place, you can add
the numbers from the batch report directly to the timing spreadsheet, and the Tco
values are automatically adjusted, removing the effect of the extra, incorrect
reference load.
This is a valuable bookkeeping feature that BoardSim batch simulation performs
automatically. BoardSim does this based on simulating with reference-load
information that is contained in IC model of each driver.
8. The example opens an .XLS file in the batch wizard.
Look at the Driver, Receiver, and Simulation Corner columns. Each driver-receiver pin
pair has an output row for each chosen IC-model corner: Slow-Weak and Fast-Strong.
Farther to the right in each row are the measurements from each simulation.
The flight times associated with each pin pair are listed in the Rise/Fall and Min/Max
Delay columns. Place these values directly in the timing budget because the Tco
reference-load delay was removed prior to simulation.
The next simulation looks at how signal-integrity violations of various types are flagged
in the batch-mode results. An easy way to create some errors is to un-terminate the net.
9. Close the spreadsheet.
10. Re-run simulation with driver round robin and some non-timing constraints.
This simulation of net datald uses other batch-mode features. This step walks you
through assigning all IC pins on net datald to an I/O, bi-directional model, and
unterminating net datald to create some interesting signal-integrity problems.
a. Select Models > Assign Models/Values By Net. The Assign Models dialog box
opens.

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b. Select the IC tab and select the first pin in the Pins list. In the Buffer settings area,
note that the pin is set to Input.
c. Scroll down the pins list, selecting each pin and watching the Buffer Settings area.
For the previous simulation, the first four pins in the list all had input-only, or
receiver models attached, and pin U3.20 had an I/O pin that was manually set to state
output.
d. With pin U3.20 highlighted, in the Buffer Settings area, select Input.
e. In the Model to Paste area, click Copy and click Paste All. Scroll through the Pins
list to see that every pin is assigned to an I/O model and all are currently set to state
Input.
f. Select the Quick Terminator tab.
g. Highlight pin U3.20 in the Pins list.
h. In the Terminator Style area, enable None. Click Close.

i. A warning appears that the net does not have a driver.

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j. Click OK.
All of the IC models for the net are I/Os. The same situation occurs on any real,
multi-drop net on which multiple I/Os exist, any one of which can turn on and drive
the net.
When performing a batch simulation for a net populated with multiple bi-directional
buffers, each driver that can turn on requires a timing delay calculation. Multiple
driver states requires running multiple sets of simulations, one for each possible
driver.
Setting up such simulations manually is extremely time-consuming. Fortunately, the
BoardSim batch engine has an option called driver round robin. When enabled,
driver round robin automatically walks through all possible driver states and runs
simulations for each.
11. Set up a batch simulation.
a. Select Simulate SI > Run Generic Batch Simulation. The Batch Wizard dialog
box opens.
b. Click Next twice. The Set Driver/Receiver Options page opens.
c. Select Driver “round robin”.
d. In the IC-Model Corners area, de-select Typical and Slow-Weak and select Fast-
Strong.

e. Click Next five times. The Select Audits and Reporting Options page displays.
f. In the After completion, automatically open area, de-select summary report file
and select detailed *.XLS report file.

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g. Click Next. The Run Simulation and Show Results page displays.
h. Click Finish. If asked whether to overwrite the earlier report files, make sure that
Excel is not open on the old spreadsheet and click Yes.
The batch engine runs. When it completes, the results open in Excel or the
application mapped to the .XLS file extension.
12. Examine the new batch simulation output.
Notice some differences in the results this time compared to the previous. First, in the
left-most column of the spreadsheet, note that some simulations are marked Fail. To see
why, find a failing row, and look at its four Rise/Fall Rail Overshoot and Rise/Fall SI
Overshoot columns. At least one of these columns has a value greater than the 1V
constraint set before the previous run.

In general, the batch wizard automatically checks and flags any simulation that fails any
constraint you set in the Nets spreadsheet. Look at the other reporting columns in the
spreadsheet for more details on what kinds of measurements and constraints are
supported.
In the results, notice which simulations were performed. In the Simulation Corner
column, all simulations ran the Fast-Strong corner of the IC model, as requested. In the
Driver and Receiver columns, note that simulations occur in groups of four: the first I/O
is turned on and driving, and delays are reported to each of the other four I/Os; the first
I/O turning off and the next turning on to drive, and so forth until all possibilities are
exercised. This shows the automatic driver-round-robin feature in action.
Note that some users may wish to parse all of this delay data from the CSV file using a
custom program or script. Since the CSV file is ASCII and simply formatted, this is not

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difficult to do. HyperLynx preserves the format of the CSV file, so any investment you
make in custom scripting is preserved.
13. Close the spreadsheet application.
The BoardSim batch wizard offers many more advanced features that are not covered in
this example. See “Running the Batch Simulation Wizard” on page 663 for additional
information.

Related Topics
“Translating a Board into a BoardSim Format” on page 208
“MultiBoard Analysis of Signals Spanning Multiple Boards” on page 199
“Simulating Multiple Boards” on page 206
“BoardSim Tutorials” on page 101

Predicting Crosstalk on a Clock Net

A typical net in a modern digital system is in close proximity to many trace segments belonging
to other nets. This makes the net a potential victim of crosstalk generated by the other nearby
aggressor traces. The most important step when analyzing such a situation is accurately
identifying all of the aggressors that contribute significantly to crosstalk on the victim net. In
BoardSim Crosstalk, aggressors are automatically identified using an algorithm that chooses
only those neighboring nets with the potential to generate crosstalk above a specified threshold
on your victim net. This threshold is conveniently described in electrical terms such as mV of
crosstalk, rather than in geometric thresholds. However, BoardSim also provides the option of
using geometric thresholds, if you prefer that method.

This example demonstrates how the BoardSim Crosstalk option can help you design a critical
clock net, guaranteeing that no more than 50 mV of crosstalk can be coupled onto the victim net
from any nearby, aggressor nets.

Prerequisites
The Crosstalk license is required to run crosstalk simulation.

Procedure
1. Load the board demo2.hyp.
a. Close any open dialog boxes.
b. Select File > Open Board > double-click demo2.hyp.
When prompted to restore session edits, click OK.
2. Select Setup and de-select Enable Crosstalk Simulation.

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3. Run an analysis on net clk2.

This board has three clock nets: clk, clk2, and clkin. Run an analysis of clk2 to see
which other nearby nets BoardSim Crosstalk thinks are likely to be aggressor nets.
a. Select Select > Net by Name for SI Analysis. A dialog box opens.
b. In the Sort Nets By area, select Name.
c. Double-click clk2. The net appears in the board viewer, with other nets dimmed in
the background.

d. Select Setup > Enable Crosstalk Simulation.

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e. Select Setup > Crosstalk Thresholds. The Set Crosstalk Thresholds dialog box
opens.
f. Select Use electrical thresholds.
Note: BoardSim Crosstalk offers geometric thresholds, if you prefer. See “Setting
Geometric Thresholds” on page 1225 for details.
g. Edit Include nets with coupled voltages greater than so that it is 250 mV.
In the board viewer, only net clk2 and its associated net n00077, which are
connected together through a series resistor, are visible in the foreground. This
means that BoardSim predicts that no other nets will generate 250 mV of crosstalk or
more on net clk2. This demonstration board is low-density, for simplicity, so it is not
surprising that it does not exhibit a lot of crosstalk.
When simulating your own boards, you can adjust this threshold up or down as
needed to meet the requirements of your particular boards and nets.
4. Adjust the crosstalk threshold down to see if any nets exceed the new value.
a. Select Setup > Crosstalk Thresholds. The Set Crosstalk Thresholds dialog box
opens.
b. Edit Include nets with coupled voltages greater than so that it is 105 mV.

c. Click OK.
More nets have now appeared in the foreground in the board viewer. Each one
shows with a dashed line. These are the aggressor nets that could potentially
contribute more than 105 mV of crosstalk to the victim clk2 net.
5. View the clk2 aggressors.
a. Select Export > Reports > Net Statistics. The Statistics for Selected Net dialog box
opens.
b. In the Associated Nets area, note the list of nets.

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Nets setsec, datald, and reset are aggressor nets to clk2. Note they are labeled “by
coupling.” Net n00077 is not coupled. It is associated to clk2 conductively, through
a series resistor.

c. Click OK.
6. Set up IC models for simulation.
During crosstalk simulations, BoardSim Crosstalk is capable of simulating any number
of victim and aggressor nets, and each victim or aggressor may be either actively
switching or static. However, it is much easier to see the crosstalk amplitude and
waveform if the driver IC of the victim net is not switching.
a. Select Models > Assign Models/Values By Net. The Assign Models dialog box
opens.
b. In the Pins list, note that some pins have a coupled icon just to the left of the
reference-designator/pin label. These are the component pins on the aggressor nets.
Pins on the selected, victim net have no icon.
c. Select U2.1 in the Pins list and select Stuck Low in the Buffer settings area. The
driver IC of the victim net is U2.1.
d. Select U3.20 in the Pins list and select Output in the Buffer Settings area. Notice
that the pin icon changes from input to output.
e. Select U11.6 in the Pins list and select Output in the Buffer settings area.

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f. Click Close.
7. Look at the coupling regions where crosstalk is generated.
Before simulating to see how much crosstalk appears on net clk2, view the coupling
regions that will generate the crosstalk. Regions are the sections along the coupled nets.
This step walks you through how to view a coupling region along the victim and
aggressor nets. Viewing the physical and electrical properties of a coupling region can
help you understand how each net contributes to the coupling in the region.
a. Select View > Coupling Regions.
b. Move the dialog box so it is not overlapping the visible nets. In the board viewer,
note the set of segments highlighted in purple with yellow boxes as endpoint
markers.

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c. In the Coupling Region dialog box, click Next. Another coupling region is
highlighted.
The Coupling Region viewer displays the names of the coupled nets, information
about how far apart they are in the current region, and a graphical stackup cross-
section showing the nets.
d. Click Impedance. An impedance and termination summary appears in the window.
You can stretch the entire window vertically to more easily see its contents, or re-
size individual panes in the window.
Note that an accurate simulation of even this simple net requires the simulation of
several different coupling regions. On real nets on a dense board, it is not uncommon
to have a hundred or more regions. BoardSim Crosstalk automatically models all of
them. Coupling regions are sorted in the viewer from strongest coupling to weakest.

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e. Click Close to close the coupling-region viewer.

8. Slow down a driver to observe the effect of slew rate on the aggressor-selection
algorithm.
When BoardSim identifies aggressor nets, it considers many factors that influence
crosstalk including trace separation, dielectric thickness, and IC models. The forward
component of crosstalk, in particular, is sensitive to the slew rate of the driver ICs on the
aggressor net. The faster the aggressor drivers, the more crosstalk tends to develop. For
additional information, see “Electrical Versus Geometric Thresholds” on page 199.
a. Select Models > Assign Models/Values By Net. The Assign Models dialog box
opens.
b. Double-click pin U3.20 in the Pins list. The Select IC Model dialog box opens.
c. Select .MOD in the Select a library, device, and signal/pin area.
d. Select easy.mod in the Libraries list.
e. Double-click model CMOS,5V,MEDIUM in the Device list. It has a slower slew
rate than the previous model. The Select IC Model dialog box closes.

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f. Click Close to close the Assign Models dialog box.

g. The aggressor net datald is no longer visible in the board viewer, since its driver is
now not fast enough to cause crosstalk above our 105 mV threshold.
9. Simulate net clk2 Interactively.
a. Select Simulate SI > Run Interactive Simulation. The Digital Oscilloscope opens.
b. In the Show area, under Probes, locate the Pins list.
c. Expand U8 and select pin 9. U8.9 is the receiver IC on the victim net.

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d. Click Start Simulation.

10. Change the vertical scale to 50 mV/div to see the crosstalk shown by the probe at the
receiver IC for the victim net. Use the scroll bar to center the waveform.

Because this simple demonstration board is not densely routed and does not use close
trace spacing, it does not show a great deal of crosstalk. Additionally, we significantly
slowed the driver ICs on one of the aggressor nets. Nevertheless, you can see that about
+/- 60 mV of crosstalk does appear at the receiver IC on net clk2.

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BoardSim can simulate any mixture of victim and aggressor traces. In fact, the simulator
makes no distinction between the two. Generally victim nets, nets on which to measure
crosstalk, are stuck low or stuck high. However, in this simulation clk2 can also switch,
making it both an aggressor to the other nets AND their victim.
11. Run a quick analysis, generating a crosstalk strength report for an entire PCB.
A typical large PCB has several thousand nets. Focusing on all of them interactively is
nearly impossible and too time-consuming. Fortunately, BoardSim Crosstalk provides
two methods for dealing with a large board, or any board on which the location of the
crosstalk problems are unknown. The first is the Crosstalk Strength Report, a powerful
and fast feature that quickly generates a report estimating the amount of crosstalk for
every net on a board.
The second method is a detailed batch mode simulation, in which you can queue up a
large set of nets for simulation and run all of them as a batch job. Results are presented
in a report file.
This step addresses the first method, the Crosstalk Strength Report. For most boards,
this is the first analysis performed because the data it provides can identify which nets
require further investigation and which nets to disregard during crosstalk analysis.
a. Close the oscilloscope.
b. Select Simulate SI > Run Generic Batch Simulation. The Batch Mode Setup
wizard opens.
c. In the Quick Analysis area, enable Show crosstalk strength estimates, sorted by
largest crosstalk value and disable all other options on the page.
d. Click Next twice. The Set Delay and Transmission-Line Options for Signal-Integrity
Analysis page displays.
e. In the For Quick Analysis…include nets with coupled voltages greater than, change
the value to 50 mV.
f. Click Next again. The Default IC Model Settings page displays. Leave the default
settings. These values are used only for nets where a specific IC model is not loaded.
g. Click Next three more times to reach the Run Simulation and Show Results page.
h. Click Finish. If asked whether to overwrite a previously generated report files, click
Yes.
The batch engine runs briefly, generating a crosstalk strength report. The HyperLynx
File Editor displays the report. Note how fast each net is processed. A board of this
size finishes simulation quickly while a large board might take several minutes.
12. Review the crosstalk strength report.
a. In the file editor, use the scroll bar to the Crosstalk Report - Quick Analysis section.
For each net with crosstalk greater than the specified 50-mV threshold, the file editor

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lists the aggressor nets for each victim net and estimates how much crosstalk each
aggressor generates.
The contribution of the two strongest aggressors per victim net is summed to give a
realistic overall crosstalk estimate for that net. Nets are sorted from most to least
amount of crosstalk. This report provides a powerful and simple way to see which
nets on the board are most likely to suffer from crosstalk.

b. Close the file editor.

Since a Crosstalk Strength Report is electrically based, it is more accurate than a
simple geometric parallelism report. BoardSim can generate the report before final
IC model assignments are made and serves as an excellent guide to identify which
nets on the board need further analysis through interactive, batch mode, or a
combination of the two.
13. Run a detailed batch mode crosstalk simulation.

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This step demonstrates how to set up and run a simulation in batch mode. Batch
mode is performed when you need to analyze a large number of nets. However, this
example only runs on one net.
a. Select Simulate SI > Run Generic Batch Simulation. The Batch Wizard opens.
b. In the Detailed Simulations area, enable Run signal-integrity and crosstalk
simulations on selected nets. Disable all other options.
c. Click Next.
d. Click SI Nets Spreadsheet. The Net Selection Spreadsheet opens.
e. Select net clk2 in the SI Enable column. Lower in the spreadsheet, note that the
associated net n00077 is automatically selected because net n00077 is connected to
clk2 through a resistor.
f. For clk2, change the value in the Max Rise/Fall Crosstalk column (located at the far
right side of the spreadsheet) to 50. Note that the value for n00077 also changes.

g. Click OK to close the spreadsheet.

h. Back in the wizard, click Next. The Set Driver/Receiver Options page appears.
i. In the IC-Model Corners area, select only Fast/Strong driver IC models.
j. Click Next three times. The Set Options for Crosstalk Analysis page appears.

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k. Select Crosstalk Simulation and select Selected Nets as Victims Stuck Low.
l. Click Next three times. The Run Simulation and Show Results page appears.
m. Click Finish to start the simulation. If asked whether to overwrite the previously
generated .RPT file, click Yes.
After a short period of time, the batch engine finishes the requested simulations on
net clk2 and opens a report file.
The report contains a detailed table for net clk2, summarizing its signal-integrity and
crosstalk behavior. Several nets are identified as aggressor nets. After the numerical
data, warnings are issued to indicate these nets have no driver-IC model. This helps
you know whether any IC models are missing during simulations.
The numerical data gives the rising- and falling-edge pin-to-pin delays for the driver
IC and each receiver, as well as the maximum overshoot and peak-value crosstalk
that occurred. If any thresholds defined in the Nets Spreadsheet are exceeded, the
report flags them as warnings. In this case, we see that crosstalk on clk2 exceeds our
50 mV threshold on both edges.
This example looks at the text output for the batch engine, the .RPT file. This output
can also be viewed as a .CSV file, which is optimized for viewing in a spreadsheet
application (or parsing by a custom, external script).
n. Close the editor.
BoardSim Crosstalk is useful not only for identifying crosstalk problems, but also
fixing them. You can reduce crosstalk in a number of ways, including slowing the
driver IC slew rate, altering board stackup, and adding line termination.
14. Reduce crosstalk.
a. Simulate net clk2 as is by running interactive simulation with the oscilloscope
b. Reduce the thicknesses of each dielectric layer in the board to 5 mils using the
stackup editor (Edit > Stackup).
c. Rerun the simulation to see how the crosstalk is affected.

Related Topics
“Electrical Versus Geometric Thresholds” on page 199
“BoardSim Tutorials” on page 101

Advanced Via Modeling

This tutorial examines the ability to model vias in very-high-speed signal paths.

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At GHz frequencies, a lossy transmission line can increase receiver delay times when taking the
loss into consideration. A second phenomenon is often equally noticeable: the electromagnetic
effects of PCB vias. Vias, specifically via inductance and capacitance, can cause unexpected
delays and signal distortion, especially as frequencies grow higher. This tutorial looks at how to
model vias with BoardSim.

Note
This tutorial describes signal-via modeling that does not take the power-distribution
network (PDN) into account. See “Analyzing Signal-Via Bypassing“ and “Exporting
Signal Vias to S-Parameter Models“.

This tutorial also does not describe how to represent signal vias in free-form schematics
with S-parameter models created by 3-D electromagnetic simulators. See “Via Properties
Dialog Box” on page 1908.

Prerequisites
The Via Models license is required to include inductance in via models and to choose among
advanced via-modeling options.

Procedure
1. Select File> Load Schematic > double-click demo.hyp.
When prompted to restore session edits, click OK.
2. Select Select > Net by Name for SI Analysis > double-click clk to select the net.
This net is poorly routed from a high-speed standpoint because it contains multiple vias.
The effects of vias are easiest to see with fast switching edges because vias look
electrically longer to higher-frequency signals and cause more signal distortion.
a. Select Models > Assign Models/Values By Net.
b. In the Pins list, double-click pin U1.13. The Select IC Model dialog box opens.
c. In the Select a library, device, and signal/pin area, select .MOD.
d. In the Libraries list, select easy.mod.
e. In the Devices list, double-click CMOS,3.3V, ULTRA-FAST.

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f. Click Close to close the Assign Models dialog box.

3. Simulate without via modeling.
Simulating without via modeling provides the capability of isolating the effects of vias
on signal integrity. You can run simulation with via modeling enabled, disable via
modeling, run simulation again, and compare the waveforms.
a. Select Setup> Via Simulation Method. The Select Method of Simulating Vias
dialog box opens.
The Include Via L and C setting controls whether to use any via modeling during
simulation.
b. De-select Include Via L and C to turn off all via modeling. The other via modeling
options gray out.
c. Click OK.
d. Select Simulate SI > Run Interactive Simulation. The Digital Oscilloscope opens.
In the IC Modeling area, select Fast-Strong to simulate with the fastest possible
driver edge.

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e. Click Start Simulation. A waveform appears.

4. Re-simulate with via modeling enabled.

a. Minimize the oscilloscope.
b. Select Setup> Via Simulating Method. The Select Method of Simulating Vias
dialog box opens.
c. Select Include Via L and C and Auto-Calculate. This option uses built-in
automatic modeling algorithms for vias.
d. Click OK.
e. Restore the oscilloscope.
f. Click Start Simulation. A new waveform appears.

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Comparing the two waveforms, the delay at the receiver ICs displays a clear difference.
The delays are pushed out when via modeling is added to the simulation. The effect is
similar to increased delay caused by the addition of lossy transmission line analysis.
This means that for accurate delay calculations, it is often important to use accurate via
modeling. Note that in the BoardSim batch-mode wizard, you can enable both lossy
transmission line and via modeling.
5. Set up via modeling. This step briefly discusses the various methods of via modeling
supported by BoardSim.
a. Click Close to close the oscilloscope.
b. Select Setup > Via Simulation Method.
c. Select User-supplied padstack-specific L and C. A spreadsheet appears and values
are filled in after a short delay.

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The selections in the top half of the dialog box offer three types of via modeling:

Table 2-2. BoardSim Via Modeling Types

Via Modeling Type Description
Auto-calculate The most powerful method, this invokes internal algorithms to
automatically model each instance of a via. These algorithms
decompose each via into sections and call fast solvers, section-by-
section, accounting for detailed effects such as the frequency-
dependent inductance of a via as it changes the reference planes
of its signal. Also included are the effects of different signal entry
and exit layers.
User-supplied Global Allows knowledgeable users to supply a single L and C value to
L and C be used for all vias on a board.
User-supplied Padstack- A more-advanced type of user-supplied value, managed in a
specific L and C spreadsheet; the customer can mix auto-calculated values for
some vias and specify custom values for certain other padstacks.

Most customers prefer the accuracy of the automated algorithms. However, you can supply your
own inductance and capacitance values based on the results of external electromagnetic
extractions or lab-measured data. Look briefly at the contents of the padstack spreadsheet. Until
you disable some options, each pad stack shows its auto-calculated value. Note the typical
values: hundreds of pH and fF, for L and C respectively.

The inductance value is frequency-dependent for padstacks containing signals that change
reference planes at least once. Although BoardSim displays the inductance value in the
spreadsheet at f=250 MHz, during simulation it uses the knee frequency the driver-IC switching
edge for each net as the calculation frequency.

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Related Topics
“BoardSim Tutorials” on page 101

Visualizing the Geometric and Electrical

Characteristics of a Via
Because accurate via modeling is so important in high-speed designs, BoardSim offers a special
feature called the Via Visualizer which allows you to examine in detail the characteristics of any
via on your PCB. Accessible directly from the BoardSim board viewer, the Via Visualizer
automatically invokes the HyperLynx Via Calculator on any via you select, and shows you both
the geometric and electrical model of a single via, or a pair of coupled differential vias. Note
that accurately modeling via coupling is essential for accurate simulation results in SERDES
and other high-speed differential paths. This exercise looks briefly at the Via Visualizer for a
sample differential via pair.

Prerequisites
The Via Models license is required to view vias in the board viewer.

Procedure
1. Select File > Open Board > double-click demodiff.hyp.
When prompted to restore session edits, click OK.
2. Set up and examine one of the via pairs with the Via Visualizer.
a. Select Select > Net by Name for SI Analysis > double-click DRV1_OUT1+.
b. Verify Setup > Enable Crosstalk Simulation is enabled.

Note that in the board viewer, other nets are dimmed while net DRV1_OUT1+ and
its companion net DRV1_OUT1- appear as a differential pair.

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c. Select View > Zoom Area and zoom in on either of the two via pairs for the selected
net.
d. Right-click one of the two vias in the pair > select View Via Properties.

The entire via circle pad turns black when selected. Be careful not to highlight one of
the connecting trace segments. The Via Visualizer opens and displays the selected
via pair.
e. Resize the window, if necessary, to see the entire graphic in the Visualizer.
After running a fast geometric/electrical check, the via visualizer recognizes the
selected via as a coupled, partner via, and displays the via as a pair. As the dialog
box opens, the Visualizer runs the BoardSim Fast Via Calculator to determine the
coupled electrical characteristics of the via pair.

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In detail, the Via Visualizer is displays the following information:

Reference Description
The detailed stackup of the PCB. Signal layers are shown in solid color and plane
layers with hatched colors. All metal is displayed in its stackup layer color.

The visual geometry of each via in the differential pair, including connected
traces, pads and anti-pads, and drill hole.

Labeling for all geometric dimensions, including pad shapes/diameters, anti-pad

diameters, drill-hole diameter, and separation between the two vias.

The electrical model for each via (including the effects of coupling between
vias), including the impedance and delay of the via (drawn as a labeled
transmission line), 3-D pad capacitance for entry and exit layers (drawn as a
lumped capacitor).

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Reference Description
Connecting traces labeled with their impedance value.

Not shown in the figure: A message in red at the bottom of the dialog box
warning that there seems to be an impedance discontinuity between the
surrounding traces and the via pair (simulation will tell whether the mismatch is
serious or not).
Remember that all of this information is calculated automatically and used by the BoardSim
simulator whenever via modeling is enabled. The Via Visualizer makes the modeling
information explicit and accessible to the user, rather than completely hidden as it is in other
signal-integrity tools.

Note that you can easily create a SPICE sub-circuit of the entire via structure by selecting
Export to SPICE located at the bottom of the dialog box.

Related Topics
“Viewing and Simulating Signal Vias” on page 1055
“BoardSim Tutorials” on page 101

Checking the Signal Quality of a Net Crossing

Two Boards
This example uses the BoardSim MultiBoard option to evaluate signals when they reach the
receiver ICs on the daughter boards of a system consisting of a main board and two smaller
plug-in PCBs. Some nets in the system start on the main board and run through connectors onto
both of the plug-in boards.

The design is a system consisting of a main board and two identical smaller plug-in PCBs.
Some nets in the system start on the main board but run through connectors onto both of the
plug-in boards. This example consists of a main board and two plug-in modules.

Prerequisites
The MultiBoard license is required to load and analyze multiple-board designs.

Procedure
1. Load a MultiBoard Project.
a. Select File > Open MultiBoard Project > double-click demo_multiboard.pjh.

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If prompted to restore session edits, click OK.

A .PJH file stores information about a MultiBoard project. The file points to the
.HYP files that make up the project.
BoardSim loads each of the boards in the project, similar to how it loads a single
.HYP file. All three boards in this example are visible at the same time in the board
viewer.
2. Construct a project using MultiBoard Project Wizard.
BoardSim makes it easy to connect multiple boards together using the MultiBoard
Project Wizard. This example shows how this MultiBoard project was constructed.
a. Select Edit > MultiBoard Project. The MultiBoard Project Wizard opens.
The first page of the wizard lists the boards in the project. Note that a comment now
appears beside the .HYP file name for each board. These labels also appear in the
BoardSim dialog boxes.

If you were to add a board to the project, it is easy: just click Insert and select a
.HYP file for the board. But this example uses only the three currently-loaded
boards.
b. Click Next.
The second page of the wizard shows the connections between the boards. A single
entry in the Interconnection List covers any two connector halves whose pin names
match. BoardSim automatically does the pin-by-pin mating.

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In the Interconnection list, the main board connector J2 is connected to plug-in board
2, connector J1. The other board connection (main board, connector J1 to plug-in
board 1, connector J1) is not shown because this example does not connect it.

Note: If you have connectors with pin names that do not match, or a connector half
that connects to more than one other connector, you can list explicit pin-by-pin
connections. See “Defining Connections Between Boards” on page 761 for details.
c. Click Next again.
The third page of the Wizard shows the electrical characteristics of each board-to-
board connector. You can specify the electrical behavior of a connector by providing
either a capacitance and inductance, or a delay and impedance. The corresponding
transmission lines are created for each pin. For most connectors, use the information
from the manufacturer.

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d. Click Cancel to avoid re-loading the project.

3. Simulate Net A0. Net A0 is driven from the main board and has receiver ICs on each of
the plug-in boards (but only B02 is connected in this example).
a. Select Select > Net by Name for SI Analysis > double-click net A0. If you cannot
see A0 in the list, in the Sort Nets By area, click Name to sort alphabetically.
Note that Design File is set to B00 Main board, meaning the net is selected from the
main board.

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The dialog box closes, and net A0 is highlighted on the main board, along with the
nets on the plug-in boards to which it connects (only B02 is connected in this
example). Rats nest lines show the connections between boards, through connectors.
Notice the arrows on the boards which indicate the location of oscilloscope probes.

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4. Set up and run simulation.

a. Select Simulate SI > Run Interactive Simulation. The Digital Oscilloscope opens.
b. In the Stimulus Area, click Oscillator.
c. In the Pins spreadsheet in the Show area, verify that under U100_B00, pin AE19 is
selected, meaning the probe at that pin is activated. Pin AE19 is the driver pin on the
main board, B00.
d. In the Show > Probes area, in the pins list, verify that under U2_B02, pin 20 is
selected. Pin U2.20 is the receiver pin on plug-in board #2.

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e. Click Start Simulation.

The green and red waveforms show the signals at the receiver-IC pins on the plug-in
boards. Note that the receivers show some overshoot.
Simulating with just the main board or just one of the plug-in PCBs displays
different waveforms. Only by combining the traces from both boards in the
simulation do you see the actual, system-level waveforms.

Related Topics
“MultiBoard Analysis of Signals Spanning Multiple Boards” on page 199
“Simulating Multiple Boards” on page 206
“Simulating Multiple-Board Designs” on page 747
“BoardSim Tutorials” on page 101

Interactively Simulating the clk Net

BoardSim allows you to run interactive analysis with detailed simulation waveforms displaying
in an oscilloscope. This example looks at the waveforms for the clock net on the demonstration
PCB.

Prerequisites
None.

Procedure
1. Load the board.
• Select File > Open Board > double-click demo.hyp.

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When prompted to restore session edits, click OK.

2. Select Select > Net by Name for SI Analysis > double-click net clk.
Nets display in the board viewer much like in a PCB-layout tool. Each layer has its own
color and all aspects of the metal routing including vias and component pads are
displayed. The colors on a net correspond to different routing layers. Note also that the
routing for the selected net appears in the foreground with all other nets still visible, but
dimmed in the background. This allows you to see the context of the selected net.
3. Simulate the net clk.
a. Select Simulate SI > Run Interactive Simulation. The Digital Oscilloscope opens.
b. In the Stimulus area, select Oscillator.
c. Verify that the value of MHz is 133.

d. Change the Horizontal Scale timebase to 2 nsec/div.

e. Click Start Simulation.

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The waveforms appear in the digital oscilloscope. The waveforms display the
voltages at the receivers, U7 and U9, and show significant overshoot. Also, there is
considerable high-frequency content in the waveform, which is a potential source of
radiated-emissions trouble.

4. Improve the signal quality of net clk by using the Termination Wizard.
The Terminator Wizard analyzes the transmission line and suggests how to fix a net with
signal-integrity problems. This step runs the Terminator Wizard interactively on clk to
find out how to improve the signal quality of the net.
An AC terminator was added at the far end of the line (resistor + capacitor to ground) to
handle anticipated transmission-line problems. However, the terminator is not
functioning correctly.
a. Examine the AC terminator.
i. Minimize the Digital Oscilloscope.
ii. Select Models > Assign Models/Values By Net. The Assign Models dialog box
opens.
iii. In the Pins list, select R9.1. The content of the Models area changes to show a
resistor.

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The resistor value is 1000 ohms, which is too large for proper AC termination. It
is possible that the value was just a placeholder.

iv. In the Pins list, select C9.1. The Models area shows a capacitor.
The capacitor value is 33 pF. This is probably too small for a net as long as clk.

b. Run the Terminator Wizard for a recommendation.

i. Click Close to close the Assign Models dialog box.
ii. Select Simulate SI > Optimize Termination. The Terminator Wizard opens.
The wizard automatically analyzes the current net, presents a list of trace
statistics, and suggests termination values. In this case, the wizard correctly
determines that the termination type is parallel AC, and makes suggestions for
the optimum values of R and C. In these calculations, BoardSim automatically
accounts for such effects as capacitive loading of receiver ICs, total line length,
and driver impedance.

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iii. In the Termination suggestions area, click Apply Values.

The component values recommended by the Terminator Wizard are exported to
the resistor and capacitor on net clk.
iv. Click OK.
The next step is to re-simulate to see their effect.
5. Re-simulate the clk net.
a. Restore the oscilloscope.
b. Click Erase to clear the old waveforms.
c. Click Start Simulation.
The overshoot at the receiver ICs is eliminated and the high-frequency content in the
waveform is reduced. The signal is much improved from the signal integrity

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standpoint, and the optimal terminating-component values were found automatically

by the Termination Wizard.

One aspect of simulating net clk that this example did not discuss is IC models.
Because signal-integrity and crosstalk problems are caused by fast-switching driver
ICs, accurately modeling ICs when simulating is crucial. BoardSim ships with many
digital IC models and also makes it easy to add new models from IC vendors and add
them to the library.
The next step shows how ICs on net clk were matched to some of those models.
6. Look at the reference-designator-to-IC mappings provided with the PCB.
One way to specify IC models in BoardSim is to map the reference designators (or part
names) of the IC to components in the BoardSim model libraries.
a. Close the oscilloscope.
b. Select Models > Assign Models/Values by Reference Designator. The .REF File
Editor opens. The .REF file maps the reference designators on a specific board to IC
models.
The Design’s parts list contains all of the ICs on the board. The Model/value to
insert area enables you to select IC models for each reference designator. These
pairings are displayed in the bottom half of the dialog box in the text area and stored
in a file named demo.ref.
This example uses a simple .REF automapping file that maps reference designators
U1, U2, U7, U8, and U9 to various IC models. When you, or the batch-mode engine,

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selects a net with mapped ICs, the models for the IC pins on that net are assigned
automatically.
Note: For IBIS models, a .REF file only works if the pin names in the IBIS model
match the pin names of the device to which it is assigned.
c. Map the reference designator U3 to model type CMOS,5V,FAST in library
EASY.MOD.
i. In the Design’s parts list, click the spreadsheet row for reference designator U3.
ii. In the Model/value to insert > Library area, select .MOD and select easy.mod.
iii. In the Component/models list, select CMOS,5V,FAST.
iv. Click Assign Model. The new mapping appears in the text box.

v. Select File > Save on the .REF editor toolbar.

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When simulating any net attached to IC U3, the model CMOS,5V,FAST is used
automatically for all U3 pins.
BoardSim also supports a similar method that maps corporate part names to IC
models. This additional method uses an editor and a file called .QPL, or qualified
part list. These mappings are available for reuse on multiple boards/projects,
which is a benefit since corporate names for components rarely change. For
more information, see “Selecting Models and Values for Entire Components” on
page 296.
7. Interactively select a pin model.
Occasionally, you may need to run a quick simulation before you have an model for an
IC. Mentor Graphics supplies a library called EASY.MOD that contains technology-
oriented models. To use EASY.MOD, you need only know whether an IC is CMOS or
bipolar, and approximately how fast it switches (super-fast, fast, or slow).
Note: Gigabit-per-second, SERDES-style designs can not use approximate models due
to the required high speeds. These designs often use vendor-supplied SPICE models.
See “Running SPICE Simulations” on page 567 for information about assigning SPICE
models.
Sometimes, it is easier to select IC models interactively for only the nets of interest
rather than mapping reference designators, as when simulating a partially-routed board.
a. Close the .REF File Editor.
b. Select Models > Assign Models/Values By Net. The Assign Models dialog box
opens.
c. In the Pins list, double-click U1.13. The Select IC Model dialog box opens.
d. Click GENERIC.MOD to select generic.mod in the Libraries list.
e. In the Devices list, double-click the model 74AC11X:LINE-DRV. The Select IC
Model dialog box closes and U1, pin 13 is now modeled as a 74AC11X line driver.
If you have a library containing many models, scrolling through a list to find a
specific model can be difficult. HyperLynx also provides an IC Model Finder utility
that you can use to search and sort models based on various criteria, such as
manufacturer, part name, and creation date. For information, see “Searching for
Models” on page 505.
f. Click Close.
8. Set up and run the Terminator Wizard on net datald. Net datald is currently
unterminated.
You can add terminators to your layout, even though they are not present in the actual
placement/routing. This gives you the ability to experiment freely with terminations of

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various styles, and much more easily than if you had to actually add them to the layout
before seeing their effect.
a. Select Select > Net by Name for SI Analysis > double-click the net datald. The
dialog box closes, and net datald appears in the board viewer.
b. Select Models > Assign Models/Values By Net. The Assign Models dialog box
opens.
You must specify the driver pin on a net before the Terminator Wizard can make a
recommendation for the best terminator type. Earlier, we changed pin U3.20 to an
input, leaving no definite driver on the net. This step changes it back to an output
pin.
c. In the Pins list, select U3.20.
d. In the Buffer Settings area, click Output. Note that the icon to the left of U3.20
changes direction.
e. Click Close.
f. Select Simulate SI > Optimize Termination. The Terminator Wizard dialog box
opens.
After analyzing the details of the net, the wizard is recommending a series resistor
terminator.
The terminator type recommendation is based on a net topology analysis. The net
datald is a candidate for series termination because all of the receivers on net datald
are near the end of the net. When the receivers are distributed all along the net, the
Wizard recommends an AC parallel terminator instead.
When no physical terminator is present on a net and the Terminator Wizard
determines a terminator is required, the Wizard can create a quick terminator on-the-
fly using virtual components.
g. Create a Quick Terminator.
• In the Termination Suggestions area, click Apply Values. The Wizard warnings
disappear because a terminator is now present.
The Terminator Wizard creates a terminator representing the series terminator it
recommended.
h. Click OK.
9. Look at the Quick Terminator.
a. Select Models > Assign Models/Values By Net. The Assign Models dialog box
opens.

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b. In the Pins list, a resistor icon appears next to U3.20. This means that a Quick
Terminator was applied at pin 20 of U3. Select pin U3.20.
c. Select the Quick Terminator tab.
The picture of the terminator shows a series terminator, with values as specified in
the Terminator Values area. For series resistors, BoardSim always includes a short
default trace stub between the driver IC and the terminating resistor, for more
realistic simulations.
In the Terminator Style area, note the other types of Quick Terminators available:
• Parallel DC (single or split)
• Parallel AC (R-C)
• Line-to-line differential
These options provide the flexibility to virtually terminate almost any net in any
design. You can also apply multiple terminators to a single net such as pull-up
resistors at both ends of a bus, or differential terminators at both driver and receiver.
Quick Terminators are a powerful feature, because they allow you to add terminators
to your design without going back to the layout tool. You can create and access
Quick Terminators just like any other component.
Quick Terminators and the Terminator Wizard are linked; any termination
recommended by the wizard that is not present in your design can be implemented
by the wizard as a Quick Terminator.
d. Click Close.
10. Generate a report of board changes.
As you improve the signal integrity and crosstalk behavior of the nets on your board, a
list of component changes accumulates to make to your schematics and/or PCB layout.
BoardSim automatically tracks these changes, and conveniently outputs them in a report
called the Design Change Summary.
a. Select Export > Reports > Design Change Summary. The Design Changes dialog
box opens.
b. Click Finish. The report opens.
Page down in the report to see that the stackup on the board, changed component
values, and added components such as Quick Terminators are all recorded and ready
to be handed to those responsible for implementing the changes.
Note: HyperLynx supports automatic back annotation to one or more PCB-layout
systems such as PADS Layout. See “Back-Annotating Board Changes” on
page 1253.

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Related Topics
“Comparing Model-Selection Methods” on page 288
“BoardSim Tutorials” on page 101

Analyzing a Board Before Routing

BoardSim can analyze a board even before it is routed. BoardSim can connect any net on your
board that is unrouted with daisy-chain Manhattan routing. You can control this routing on a
per-net basis, choosing a pessimism factor for the Manhattan routing. For example, you can
specify a percentage longer than an ideal route, or even specify an exact length. The Manhattan
routes can be on any layer, but are limited to one layer per net.

Using this feature, you can analyze a board in any state of routing: placed but completely
unrouted, or placed and partially routed. Any unrouted nets can be Manhattan connected and
analyzed. Nets that are already routed are simulated using the existing routing. This tutorial
loads an unrouted version of the demonstration board to illustrate how Manhattan routing
works.

Prerequisites
None.

Procedure
1. Load the board.
• Select File > Open Board > double-click demo_unrouted.hyp.
2. When prompted to restore session edits, de-select Manhattan routes and click OK.

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When the board is finished loading, a warning displays stating that BoardSim found one
of more nets completely unrouted, and is asking whether you want to route them using
Manhattan interconnect.
3. Click Yes. The Connect Nets with Manhattan Routing dialog box opens.
4. In the Nets to connect with Manhattan routing area, select All unrouted nets (except
power supplies). This example routes the entire board – all nets – on the same layer.
5. In the Routing Criteria area, select Specify Manhattan multiplier. Note that by default,
the Multiplier is set to 1.20, the routing is implemented on the top layer, and the Width is
set to 6 mils.

6. Click Connect Net(s).

The Loading .HYP File dialog box appears while the board is routed. Move the Connect
Nets with Manhattan Routing dialog box to the side to view the routing progression.
7. When the routing finishes, click Close. The board appears in the board viewer. Note that
although the routing does not display as real copper, the simulation runs using real
copper routing.
8. View the Manhattan-routed board.
The board viewer shows the Manhattan-routed version of the demonstration board. Note
that the routing now appears as red dotted lines that indicate virtual routing. These
connections have the properties specified in the routing dialog box: the connections are
1.2 times longer than the ideal Manhattan length, and for impedance-calculation
purposes, they lie on the top layer of the board.

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You can now proceed to analyze the entire board, interactively or in batch mode, just as
if it contained real routing. However, note that this analysis is occurring before actually
routing the board. If you find serious signal-integrity problems at this stage, you can
attempt to fix them by altering your placement.

Related Topics
“Simulating Unrouted Nets with Manhattan Routing” on page 921
“BoardSim Tutorials” on page 101

DC Voltage Drop Analysis

This tutorial shows the basic steps of running a DC voltage drop analysis with BoardSim.

Prerequisites
The DC Drop license is required to run a DC drop analysis.

Procedure
1. Load the board.

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• Select File > Open Board > double-click dc_drop_lab_2.hyp.

When prompted to restore session edits, click OK.
2. Select Simulate PI > Run DC Drop Simulation.
If a message appears that says the .HYP file was created by a PCB translator that did not
record whether the physical information is sufficiently detailed for power-integrity
analysis, click OK.
The DC Drop Analysis window opens.
3. Select a net to analyze.
From the Power/Ground Net to Analyze list, select the 1.5V net. The viewer displays an
outline of the image of the selected net.
Note that the image of the net does not display routed traces. This means you can run a
simulation even if there is no image of the selected net, meaning the net contains only
traces.

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4. Assign models to pins.

The Assigned Models area displays all the models assigned to the different pins. Click
Assign. The Assign Power Integrity Models dialog box opens.
To run the DC Drop analysis, assign at least two pins to models: one for a DC Model
(source) and the other for a VRM Model (sink).
a. Select pin AA15 on component U30. Select the pin by clicking on the gray box next
to its number (hold down the Ctrl or Shift key for selecting more than one pin). This
highlights the whole line and activates the Assign and Remove buttons of the AC,
DC, and VRM models. However, assigning AC Models to the pin is irrelevant to this
simulation.

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b. From the DC Sink Model area, select Assign. The Edit DC Supply Pin Model dialog
box opens.
i. Set Apply Current to Each Sink.
ii. Set Current to 5 A.
iii. Set Resistance to 1000000 Ohms.
iv. Click OK.

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c. Repeat the same steps for assigning a VRM Model to a different pin on the power-
supply net.
i. Select pin 3 on component Q1.
ii. In the Assign Power Integrity Models dialog box, from the VRM Model area,
select Assign. The Assign VRM Model dialog box opens.
iii. Set Model to Simple.
iv. Set Voltage to 1.5 V.
v. Set Resistance to 1000 mOhms.
vi. Set Inductance to 10 nH.
vii. Click OK.

After assigning a model to a pin, the model/pin pair displays in the Assigned Models
area of the DC Drop Analysis dialog box.
5. Run the simulation.
a. Click OK to close the Assign Power Integrity Models dialog box.

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b. Click Simulate. The Running DC Drop Simulation dialog box appears and tracks
the run progress.

The DC drop analysis generates a textual report that shows the current and voltage of
the pins that we assigned models, and the voltage source and current sink vias. When
the simulation completes, the report appears.
c. Move the Reporter dialog box away from the board display area.
d. Click pin Q1.3 and notice that the display zooms to the area associated with the pin.

e. Click Close to close the Reporter.

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f. In the DC Drop Analysis dialog box, click Show PowerScope. The PI PowerScope
opens, displaying a 3D color image of the DC drop.

The display uses a color scale to represent DC drop: dark blue represent the lowest
DC voltage drop value and red represents the highest DC voltage drop value. The
total Voltage Drop numerical value is displayed below the 3D image.
g. Use the control boxes to manipulate the image.,

Control Function
Turn image

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Control Function
Shift image

Zoom in

Inspect image

Default view

Top view

Fit image to window

6. Improve the view by adding a reference plane to the model. The best way to detect a
problem in a design is by looking at the DC Current Density graph from a top view.
a. Click Visual Options. This changes the selections available in the right pane of the
viewer.
b. In Model view, select Meshed model.
c. In Graph Type, select DC Current Density.

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d. Click Positioning Options.

e. In Position and scale, disable Auto span & origin. This allows you to modify the
current density by modifying the Span, and visualize how the current density is
changing on the board section.
f. Change the Span to 15.6 mA/mil to view the current density across the board.
g. Change the Origin to 3.85 mA/mil.

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Note the maximum current density is 1587.3 mA/mil2.

7. Perform a batch DC drop analysis.

a. Click Close to close the PI PowerScope.
b. Click Close to close the DC Drop Analysis dialog box.
c. Select Simulate PI > Run DC Drop Batch Simulation. The Batch DC Drop
Simulation dialog box opens.
d. Click Uncheck All.
e. Select the 2.5V and 1.8V nets for analysis.

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f. Assign models to pins.

A DC drop analysis requires at least two pins to have models assigned to them: One
for a DC Sink Model (source) and the other for a VRM Model (sink). AC models are
ignored for DC drop analysis.
i. Click Assign Models. The Assign Power Integrity Models dialog box opens.
AC, DC, VRM models or reference nets are assigned to the pins.
ii. Assign models to the 2.5V rail. Type 2.5V into the Power-Supply net filter and
click Apply.

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iii. Select pin 7 of J1_MEM_L1.

To assign a model to a pin, select the gray box next to it.
Note that you can select multiple pins by holding down the Shift or Ctrl key.
iv. In the DC Sink Model area, click Assign. The Edit DC Supply Pin Model dialog
box opens.
v. Set Apply Current to Each Sink.
vi. Set Current to 5 A and Resistance to 1000000 Ohms.
vii. Click OK.

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viii. Type *Q4* into the Reference Designator filter and click Apply.
ix. Select pin 2 of Q4.
x. In the VRM Model area, select Assign.

xi. In the VRM Model area, click Assign. The Assign VRM Model dialog box
opens.
xii. Set Model to Simple.
xiii. Set Voltage to 2.5 V.
xiv. Set the Resistance to 1000 mOhms and the Inductance to 10 nH.
xv. Click OK.

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g. Assign models to the 1.8V rail.

i. Set Reference Designator to *.
ii. Set the Power-Supply net to 1.8V and click Apply.
iii. Select pin U29.AA8 and in the DC Sink Model area, click Assign Models. The
Edit DC Power Pin Model dialog box opens.
iv. Set Apply Current to Each Sink.
v. Set Current to 5A and Resistance to 1000000 Ohms.
vi. Click OK.

vii. Set the Reference Designator to U42* and click Apply.

viii. Select pin 3 of U42 and in the VRM Model area, click Assign. The Edit DC
Supply Pin Model dialog box opens.

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ix. Select Model to Simple.

x. Set Voltage to 1.8V.
xi. Set Resistance to 1 mOhms and Inductance to 5 nH.
xii. Click OK.

h. Click OK to close the Assign Power Integrity Models dialog box.

8. Run a DC Drop batch simulation.
a. From the Batch DC Drop Simulation dialog box, click Run.

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The Running Batch DC Drop Simulation dialog box reports the simulation status.
When the simulation completes, the DC drop analysis generates a textual report that
shows the maximum voltage drop and current density of each net analyzed, and the
pin on which it occurred.
b. Click on a highlighted pin in the report and your mouse pointer jumps to that pin on
the board. If the voltage drop of the net is greater than the voltage drop threshold, the
report displays a Test failed message.

c. Click J1_MEM_L1.7 to jump to the point on the board viewer.

d. Click the link for the detailed report to view the details (in another instance of the
Reporter window) created for each net.

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Related Topics
“Simulating DC Voltage Drop” on page 963
“BoardSim Tutorials” on page 101

Analyzing Crosstalk on the Virtex-4 Demo Board

Crosstalk, such as other signal-integrity problems, can negatively impact your final design and
manifest as false clocking, intermittent data errors, or other difficult-to-find and potentially
serious problems. It can also be difficult to know where crosstalk is likely to occur, and
eliminating it can be more troublesome than fixing single-trace signal-integrity problems.

A typical net in a modern digital system is in close proximity to many trace segments belonging
to other nets − especially on wide, parallel buses such as DDR. This makes the net a potential
victim of crosstalk generated by the other nearby aggressor traces.

The most important step to analyzing such a situation is accurately identifying all of the
aggressors that contribute significantly to crosstalk on the victim net. When simulating crosstalk

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in BoardSim, aggressors are automatically selected using an algorithm that chooses only those
neighboring nets with the potential to generate crosstalk above a specified threshold on victim
nets. This threshold is conveniently described in electrical terms (that is, mV of crosstalk) rather
than being geometric, although you have the option of using geometric thresholds, if you prefer.

This example has a design goal of guaranteeing that no more than 150 mV of crosstalk can be
coupled onto the “victim” net from any nearby “aggressor” nets when using a DDR memory
interface on the Virtex-4 demo design.

This example predicts crosstalk on a DDR DQS net.

Prerequisites
The MultiBoard license is required to load and analyze multiple-board designs.

The Crosstalk license is required to run crosstalk simulation.

Procedure
1. Load the board virtex4_sdram_multiboard.pjh
a. Close any open dialog boxes.
b. Select File > Open MultiBoard Project > double-click
virtex4_sdram_multiboard.pjh.
If prompted to restore session edits, click Yes. The board layout appears in the board
viewer.
2. Select Setup and verify that Enable Crosstalk Simulation is disabled.
Note the DDR interface on this board. One of the most important signals on a DDR
interface is a strobe, which acts as the clock for the interface. This step analyzes the
DDR strobe signal named SDRAM_DQS2.
3. Automatically find aggressor nets.
An important feature of BoardSim Crosstalk is that it automatically identifies which
other nets are coupled strongly enough to the selected victim net to be aggressors. For
more information on this powerful capability, see the “Electrical Versus Geometric
Thresholds” on page 199.
a. Select Select > Net by Name for SI Analysis.
Note that the Design File located at the bottom of the dialog box is set to B00
Virtex4 Demo, meaning the nets listed are located on the main board.
b. In the Filter box, type *DQS2 and click Apply.
c. Double-click net SDRAM_DQS2.

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The net SDRAM_DQS2 is highlighted on the main board, along with the nets on the
DIMM plug-in board to which it connects.

d. Select Setup > Enable Crosstalk Simulation. Rats nest lines show the connections
between boards, through connectors.

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For this example, BoardSim Crosstalk searches for all aggressor nets that contribute
150mV or more crosstalk to the selected victim net. Note that this threshold is
adjustable.
In addition to net SDRAM_DQS2 being visible in the foreground of the board
viewer, you can also see several other highlighted nets with dashed lines. The
highlighted dashed lines indicate that the surrounding dashed traces are aggressors to
SDRAM_DQS2. BoardSim predicts that these aggressor nets have the potential to
cause more than 150 mV of crosstalk on the victim net SDRAM_DQS2.
The next step is to look at a report of the crosstalk on the victim net.
e. Select Export > Reports > Net Statistics. The Statistics for Selected Net dialog box
opens.
The Associated Nets area shows the following nets are aggressor nets to
SDRAM_DQS2: SDRAM_RAS_Z_B00, RAS_B01, MRAS_B01,
SDRAM_DQ17_B00, DQ17_B01, and MDQ17_B01. The names of these nets are
followed by the (by coupling) label.

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The other nets listed, DQS2_B01 and MDQS2_B01, are associated to aggressor nets
through series resistors or a connection through the DIMM providing a path of
conductivity.

f. Click OK.
4. Set up IC models for simulation.
During crosstalk simulations, BoardSim Crosstalk is capable of simulating any number
of victim and aggressor nets, and each victim or aggressor is either actively switching or
static, that is, stuck high or low. However, it is much easier to see the crosstalk
amplitude and waveform if the driver IC of the victim net is not switching.
a. Select Models > Assign Models/Values by Net.
In the Pins list, note that some pins have a coupled icon just to the left of the
reference-designator/pin label. These are the component pins on the aggressor nets.
Pins on the selected victim net do not have an icon.
b. Click U1.M30, the driver IC of the victim net.
c. In the Buffer Settings area, select Stuck Low.

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d. In the Buffer Settings area, select Output.

e. In the Design file list, select B01 DIMM and select Input for pins U3.51 and
U16.51.

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f. Click Close.
5. View the crosstalk coupling regions.
Before simulating to see how much crosstalk appears on net SDRAM_DQS2, you can
view the crosstalk coupling regions, that is, sections along the coupled nets which
generate the crosstalk. Viewing the physical and electrical properties of a coupling
region can help you understand how each net contributes to the coupling in the region.
a. Select View > Coupling Regions.
b. Move the dialog box so you can view the visible nets.
c. In the board viewer, note the set of segments highlighted in black with yellow boxes
as endpoint markers.

d. In the Coupling Region dialog box, click Next. A different coupling region is
highlighted.
The Coupling Region viewer contains the names of the coupled nets, information
about how far apart they are in the currently displayed region, and a graphical
stackup cross-section showing the nets.

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e. Click Impedance to add an impedance and termination summary to the viewer. You
can stretch the entire window vertically to more easily see its contents, or re-size
individual panes in the window.
Coupling regions in the viewer are sorted from strongest coupling to weakest.
Note that even this simple net requires several different coupling regions to be
accurately simulated. For nets on a dense board, it is common to have a hundred or
more regions. BoardSim Crosstalk automatically models all regions.
f. Click Close to close the Coupling Region viewer.
6. Simulate Net SDRAM_DQS2 interactively and measure the crosstalk.
a. Select Simulate SI > Run Interactive Simulation. The Digital Oscilloscope opens.
b. In the Stimulus area, select Rising Edge.
c. In the IC modeling area, select Fast/Strong.

d. In the Show > Probes area, in the Pins list, de-select all probes.
e. In the Show > Probes area, in the Pins list, expand U3_B01, and select pin 51. Pin 51
is the first victim receiver pin on the DIMM.
f. In the Show > Probes area, in the Pins list, expand U16_B01, and verify that the
probe at pin 51 is enabled. Pin 51 is the second victim receiver pin on the DIMM.

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g. In the Vertical area, change the vertical position to -100 mV and the vertical scale to
20 mV/div.

h. Click Start Simulation. The crosstalk simulation runs.

The waveforms are from the probes at the receiver ICs on the victim nets.
i. Change the Horizontal Scale to 1 ns/div to see the crosstalk clearly.
j. Below the waveform display, click Track Waveform.
k. In the waveform display, hover over the waveform to locate U16_B01.51 and click
to select the waveform.

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l. Click to place a probe cursor at the pre-crosstalk, steady state condition on the left,
and click to place a second cursor at the largest departure from this value for either
waveform.
The observed Delta V value is about 50 mV as a result of coupling from the
aggressor net.

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This particular net still falls well within the originally selected threshold of 150 mV.
However, if the crosstalk limit is as low as 50 mV, the design has a problem.
BoardSim simulates any mixture of victim and aggressor traces. In fact, the
simulator makes no distinction between the two. Generally, the preference is to have
the victim nets - the nets on which you want to measure crosstalk- stuck either low or
high. However, in this simulation, SDRAM_DQS2 can also switch, making the net
both an aggressor to the other nets AND their victim.

Related Topics
“BoardSim Tutorials” on page 101

Locating Signal Quality and Timing Problems

Using Batch Mode Simulation
This example scans a Xilinx demonstration design with Virtex-4 technology for signal quality
and timing problems. Once the high-level problems on the board are identified, you can use
BoardSim to perform a more detailed net-by-net analysis using interactive analysis.

BoardSim batch simulation enables you to analyze multiple nets of interest at one time and
provide valuable signal-integrity information such as overshoot, flight time, and monotonicity
errors for every driver and receiver combination on the net. This example looks at the net

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SDRAM_DQS2 and the data signals SDRAM_DQS16 – SDRAM_DQS23 that correspond to

this DQS net in batch mode.

Prerequisites
The MultiBoard license is required to load and analyze multiple-board designs.

The Crosstalk license is required to run crosstalk simulation.

Third-party application software, such as Microsoft Excel, that can open Excel-formatted .XLS
spreadsheet files.

Procedure
1. Select File > Open MultiBoard Project > double-click
virtex4_sdram_multiboard.pjh.
2. Select Simulate SI > Run Generic Batch Simulation. The batch simulation wizard
opens.
3. In the Detailed simulations area, select Run signal-integrity and crosstalk simulations
on selected nets.
4. In the Quick analysis area, de-select all options.

5. Click Next. The Select Nets and Constraints page displays.

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6. Click SI Nets Spreadsheet. The spreadsheet opens.

You can select any part of this board as long as the IC models are in place. This example
looks at a complete data group. The next step looks at data bits 16-23, all associated with
the DQS2 strobe.
7. Type SDRAM_DQ1* into Filter and click Apply.
The filter box is case insensitive, so sdram_dq1* provides the same filter results.
8. In the SI Enable column, enable the following nets on board B00:
• SDRAM_DQ16_B00
• SDRAM_DQ17_B00
• SDRAM_DQ18_B00
• SDRAM_DQ19_B00
You may need to widen the Net Name column to see the full net names.
Note that the net name has an extension of _B00 or _B01 to indicate the board on which
the net resides. Nets associated with the selected nets through the multiple-board project
connector or a termination resistor, such as DQ16_B01, are automatically selected.

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9. Verify that the following electrical constraints are set for the selected signals:

Electrical Constraint Value

Max Rise Static Rail Overshoot 10 mV
Max Fall Static Rail Overshoot 10 mV
Max Rise SI Overshoot 500 mV
Max Fall SI Overshoot 500 mV
Max Rise/Fall Delay 2 ns
Min Rise/Fall Delay .250 ns
Max Rise/Fall Crosstalk 150 mV

10. Type SDRAM_DQ2* into Filter and click Apply.

11. Repeat steps 8 and 9 for the following nets on board B00:
• SDRAM_DQ20_B00
• SDRAM_DQ21_B00
• SDRAM_DQ22_B00
• SDRAM_DQ23_B00
Note that you can also import and export batch spreadsheet settings to Microsoft Excel
or other spreadsheet programs. For information, see “Exporting and Importing
Spreadsheet Contents” on page 687.

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12. Type SDRAM_DQS* into Filter and click Apply.

13. Repeat steps 8 and 9 for the following nets on board B00:
• SDRAM_DQS2_B00
14. Click OK to close the spreadsheet.
15. Click Next. The Set Driver/Receiver Options page appears.
16. In the I/O and open-drain models area, select Driver “round robin”.
17. In the IC-model corners area, select Fast/Strong and de-select the other options.

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18. Click Next. The Set Delay and Transmission-Line Options page appears.
19. In the Delay calculations area, select Flight-time compensation.

20. Click Next three times. The Set Options for Signal-Integrity and Crosstalk Analysis
page appears.
21. De-select Simulate loss and select Include Via L and C.

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22. Click Next. The Select Audit and Reporting Options page appears.
23. In the After completion, automatically open area, select detailed *.XLS report file and
if opening *.XLS, auto-format and show errors in red.

24. Click Next. The Run Simulation and Show Results page appears.
25. Click Finish to begin batch simulation. If prompted to overwrite the previously-
generated *.XLS and .RPT file, click Yes.
After a short period of time, the batch engine finishes the simulations on the DDR nets
and opens the .XLS file. Wait for the auto-formatting macro to complete, giving it time
to properly format the results.
The results in the .XLS output file show overall Pass/Fail results for each net that was
enabled for simulation. Since the simulate included driver round robin, the .XLS file
contains the simulation results for every driver/receiver combination. However, not all
of these combinations are necessarily valid. For instance, simulation results where one
component on a DIMM is driving to another component on a DIMM, B01 to B01 in
Column B, are not relevant since this operation never occurs.

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The Overall Pass/Fail column in the spreadsheet lists all of the failures. Scroll to
columns U-AA on the right to see that most of the failures result from SI Rail Overshoot
problems.
Note that the .XLS output file from the batch engine simulation, which is optimized for
viewing in a spreadsheet format, can also be parsed by a custom external script.
26. Investigate one of the failures that batch mode uncovered.
The batch results show that one of the SI Overshoot failures occurred on
SDRAM_DQS2, as the DIMM was driving back to the Controller on the main board.
The measured value was over 600 mV.
We will try two ways to fix the overshoot:
• Change termination
• Change model buffer. One feature of most DDR SDRAMs is that they offer full
and half drive-strength buffers.
27. Interactively simulate the net SDRAM_DQS2.
a. Close the spreadsheet.
b. Select Select > Net by Name for SI Analysis > select SDRAM_DQS2.
Note that the Design File is set to B00 Virtex4 Demo. This indicates that the net
selections are located on the main board.
If SDRAM_DQS2 does not appear in the list, set the Filter to *dqs2.
c. Click OK.
The dialog box closes, and net SDRAM_DQS2 is highlighted on the main board,
along with the nets on the DIMM plug-in board to which it connects. “Rats nest”
lines show the connections between boards.
d. Select Models > Assign Models/Values by Net. The Assign Models dialog box
opens.
e. Select Design File > B00 Virtex4 Demo.
f. In the Pins list, select U1.M30. In the Buffer settings area, set the pin to Input.

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g. Select Design File > B01 DIMM to switch to the DIMM plug-in board.
h. In the Pins list, select U3.51. In the Buffer settings area, set the pin to Output.

i. In the Pins list, select U16.51. In the Buffer settings area, set the pin to Input.
j. Click Close.

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28. Set up and run simulation.

a. Select Simulate SI > Run Interactive Simulation. The Digital Oscilloscope opens.
b. In the Show > Probes area, in the Pins list, disable all probes.
You can quickly disable all probes by selecting Latest Waveforms (to select all
probes) and re-selecting Latest Waveforms (to de-select all probes).
c. In the Show > Probes area, in the Pins list, select U1_B00, pin M30. This is the
receiver pin on the main board.
d. In the Show > Probes area, in the Pins list, select U3_B01, pin 51.
e. Note that there is no need to probe U16.51 since it is not be enabled to receive data
during a read operation.

Colored arrows display on each of the boards in the board viewer, indicating the
locations of the assigned probes.
f. In the Stimulus Area, select Rising Edge.
g. Set the IC modeling corner to Fast-Strong.
h. Set the Vertical scale to 500 mV/div and the Horizontal scale to 1 ns/div.

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i. Click Start Simulation.

The signal at the receiver-IC pin on the Virtex-4 board displays. Note the overshoot
seen at the receiver. The next step measures this voltage to see how it correlates to
the batch results.
29. Measure the overshoot voltage.
a. Below the display window, click Track Waveform, locate the waveform for pin
U1_B00_M30, the signal at the receiver-IC pin on the Virtex-4 board and click to
select the waveform.
b. Point to the peak of the waveform and click to place a marker, at about 2.6 V and
2.75 ns.
c. Point to the steady-state voltage, about 2.0 V and at 9.5 ns, and click to add a second
marker to the waveform.

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The difference between the two cursors shows over 600 mV of overshoot on this net
which corresponds to the results produced by the batch-mode analysis and whose
value is reported in step 26.
DDR buffers typically support two different classes of drive strength: a full-strength
buffer and a half-strength buffer. Since the board is currently set up for full-strength
drivers, the next step is to change the buffer drive strength to half strength and
determine its effect on the overshoot.
DDR buses typically also have series terminators, which can be another reason for
the overshoot. HyperLynx BoardSim provides the ability to add a Quick Terminator
to see if termination modifications improve signal quality. In addition to the buffer-
strength change, this example places a quick terminator on SDRAM_DQS2 to
improve signal quality.

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30. Improve the design by changing the buffer model of the driver U3.51 and add a quick
terminator.
a. Minimize (not close) the Oscilloscope.
b. Select Models > Assign Models/Values by Net. The Assign Models dialog box
opens.
c. Select Design File > B01 DIMM and select pin U3.51.

d. Click Select. The Select IC Model dialog box opens.

e. In the Select By area, enable Signal.
f. In the Signal list, select DQS_HALF.
g. Click OK.

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h. On the IC tab of the Assign Models dialog box, select Design File > B00 Virtex4
Demo > pin U1.M30.
i. Select the Quick Terminator tab.
j. Verify that pin U1.M30 is still selected on B00 Virtex4 Demo.
k. Enable R series in the Terminator style area.
l. Change the terminator value, Rs, to 22 ohms.
m. Set layer to L1=Top.
n. Set the Length to 0.500 inches and width to 5.00 mils.

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o. Click Close.
31. Set up and run the simulation.
a. Restore the oscilloscope.
b. Click Start Simulation.
The new simulation shows a significant improvement, reducing the overshoot on the
SDRAM_DQS2 net. Comparing the current and previous results shows about a 300
mV decrease in overshoot.

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Related Topics
“BoardSim Tutorials” on page 101

BoardSim Tutorial Reference Information

This topic includes background information related to the technology covered in the LineSim
tutorials.

• “MultiBoard Analysis of Signals Spanning Multiple Boards” on page 199

• “Electrical Versus Geometric Thresholds” on page 199
• “Signal-Integrity Analysis” on page 200
• “Crosstalk Analysis” on page 201
• “GHz Analysis” on page 202

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• “Library EASY.MOD” on page 203

• “Eye Diagrams Introduction” on page 203
• “Multi-Bit Stimulus Introduction” on page 203
• “BoardSim Crosstalk and Differential-Signal Analysis” on page 204
• “Post-Layout Analysis: BoardSim and Batch Mode” on page 205
• “Simulating Multiple Boards” on page 206
• “Adding IC Models to Your Existing Libraries” on page 207
• “SPICE and Touchstone Models” on page 207
• “MultiBoard Analysis with EBD Models” on page 208
• “Translating a Board into a BoardSim Format” on page 208

Related Topics
“IC Modeling with HyperLynx”

MultiBoard Analysis of Signals Spanning Multiple Boards

Many designs involve multiple, interconnected PCBs, such as a motherboard with one or more
memory modules plugged in, or a system consisting of several boards joined by connectors and
cables. The BoardSim MultiBoard option adds the ability to load multiple boards
simultaneously, virtually interconnect them, and simulate them together as a system. Each
board can be in the form either of a .HYP file, or a type of IBIS board model called .EBD,
electrical board description. If the system under analysis consists entirely of your own PCBs,
you will likely load all of your boards into BoardSim as .HYP files. If some of the boards come
from a third party (for example, memory modules), those 3rd-party boards might be provided in
EBD format.

Electrical Versus Geometric Thresholds

Selecting aggressors for crosstalk analysis can include the nearest-neighbor, geometric zone, or
electrical estimation. Because crosstalk analysis is CPU-intensive, the simulation time is
affected by the number of selected aggressor nets. Therefore, selecting only those nets that are
significantly coupled to the victim net maximizes simulation efficiency.

Often, the greatest amount of crosstalk on a given section of a victim net is due to the nearest
trace on either side. However, a fast driver can cause a more distant net to be the strongest
aggressor. Using a traditional geometric coupling window or zone to identify aggressors ignores
faster drivers on distant nets, while nets in closer proximity with slow drivers are included
needlessly. This scenario can lead to a significant underestimation of the crosstalk on the victim
net.

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If you chose a different approach and increased the width of the coupling zone, you might catch
further-away aggressor nets, but in many cases you would also include many nets which are not
significant aggressors and whose presence would simply slow your simulations.

By default, BoardSim Crosstalk uses electrical thresholds. This approach has several major
benefits. First, more distant nets with fast drivers are correctly found by the aggressor-finding
algorithm. Second, nearby nets with slower drivers are included only if they contribute crosstalk
above the threshold you specify. The result is a minimum but correct set of nets to simulate,
which can cut analysis time significantly, and increase accuracy. Finally, electrical thresholds
make crosstalk easier to visualize by presenting it as mV of noise rather than in geometric
limits.

Signal-Integrity Analysis
Signal-integrity analysis is concerned with the quality of the digital signals on a printed circuit
board. As driver ICs switch faster and faster, more and more boards suffer from signal
degradations such as overshoot and undershoot, ringing, non-monotonicity, crosstalk, and
excessive settling delays. When these become serious enough, the logic on a board can begin to
fail.

Signal-integrity concerns are critical for very-high-speed SERDES-based designs using

serializer/deserializer technology. Special methods such as eye diagrams are used to judge
whether signal quality is sufficient for a data stream to be recovered at the receiver IC. Analysis
must include such advanced effects as lossy transmission lines and complex via modeling.

Why do signal-integrity effects occur, and why so much more today than before? The answer
lies in the transmission-line behavior of the metal traces on a PCB. When a lower-frequency
digital signal (that is, a signal that switches relatively slowly) travels along a board trace, the
trace itself is almost invisible from a circuit standpoint. But when a higher-frequency signal
(that is, a signal that switches more quickly) travels along the same trace, the trace exhibits
circuit characteristics that distort and degrade the signal. The problems get worse at high
frequencies; at gigabit speeds, signals are sometimes attenuated by trace loss by more than 50%
before arriving at receivers.

The trend behind these problems is the driver IC switching rate. The reason that fewer designs
exhibited transmission-line effects in the past is that many of the ICs switched more slowly than
the ICs common today. For example, consider a 6-inch, 6-mil-wide trace on the outer layer of a
board, 5 mils above a ground plane. If driven with an older logic family with a switching time of
3 ns, there are only a few visible transmission-line effects. But when the same trace is driven by
a modern CMOS logic IC (switching time = 750 ps), the signal at the end of the trace overshoots
by more than a volt, and rings for more than 20 ns.

A rule of thumb to use is if the switching time of a driver IC on a trace is shorter in nanoseconds
than the length of the trace in inches, the signal will suffer from transmission-line effects. This
means that a driver IC with a 1 ns switching time will create transmission-line effects on any
trace 1 inch or longer.

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A number of factors affect how a trace on a PCB behaves from a signal-integrity standpoint:

• The geometric properties of the trace itself

• How it connects to other traces
• How the board layers are stacked up
• The materials used to manufacture the board
A signal-integrity/crosstalk/GHz-level simulator must accurately model all of these parameters.

Another important modeling factor involves the ICs on the trace, especially the driver IC. It is
typically the driver IC that causes transmission-line problems, because of fast rise and fall
times. Receiver ICs also play a role, especially as a result of their input capacitance and diode-
clamping effects.

For accurate signal-integrity of driver ICs, each of the following must be considered for
simulation:

• Switching time (rising and falling edges)

• Switching impedance (rising and falling edges)
• Switching shape (rising and falling edges)
• Clamp diodes (high and low side)
• Output capacitance.
For receiver ICs, the following are important: Input capacitance, clamp diodes (high and low
side), and input resistance.

Still, occasionally, you may need to run a quick simulation before you have the model for an IC.
For these cases, Mentor Graphics supplies a library called EASY.MOD that contains
technology-oriented models. To use EASY.MOD, you need only know whether an IC is CMOS
or bipolar, and approximately how fast it switches (such as super-fast, fast, slow). Once you
make the appropriate selection from EASY.MOD, you can begin simulation.

Note: Gigabit-per-second, SERDES-style designs, do not use approximate models because the
very high speeds and accuracy required for this type of design. In fact, many times vendor-
supplied SPICE or IBIS-AMI models are required. See “Setting Up a SPICE Simulation” or
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611.

Crosstalk Analysis
Crosstalk analysis is a particular category of signal-integrity simulation that looks specifically at
unwanted noise generated between signals. Crosstalk occurs when two or more nets on a PCB
are coupled to each other. Such coupling can arise any time two nets are routed next to each

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other for any significant length. When a signal is driven on one of the lines, the electric and
magnetic fields it generates cause an unexpected signal to also appear on the nearby line.

Crosstalk is a particularly hard phenomenon to anticipate and control without simulation

because there is almost no way of intuitively knowing how much crosstalk voltage and current
will develop due to a given coupling. Many complex factors combine to create an unwanted
crosstalk signal: The length over which the traces are coupled, the distance between the traces,
their positions in the PCB stackup, what driver ICs are used on both the aggressor and the
victim lines, whether or not the lines are terminated, and so forth. In order to resolve all of these
factors and produce an accurate simulation, the HyperLynx software uses a fast, built-in field
solver that can calculate the electromagnetic properties that govern the line-to-line coupling.

GHz Analysis
GHz analysis is a general term for the collection of special techniques used to analyze gigabit-
per-second (Gbps) SERDES-based designs. This type of signaling has appeared in the past few
years as a solution to the problem of how to push data rates into the multi-Gbps range, where
classic parallel, synchronous bus techniques become nearly impossible to manage. SERDES
data channels are serial (hence the need for SERializers and DESerializers), extremely fast, and
travel over interconnect without explicit clocks. Sophisticated receiver ICs use techniques such
as equalization to recover these signals after they are seriously degraded by propagation across a
PCB or down a cable.

GHz-level analysis must account for lossy effects and the electrical complexities of vias. Loss
refers to the phenomenon in which PCB-trace resistance and the heating of dielectric materials
(like FR-4) cause signals to lose amplitude (that is, attenuate) and suffer shape distortion
(disperse). These effects are hardly noticed at the frequencies present in a 2-ns driver edge, but
for the frequencies that make up a 200-ps edge, they can be quite severe. Accurately analyzing
loss is difficult because lossy effects are frequency-dependent, and digital signals contain a
wide range of frequencies. The situation is similar with vias: to a 2-ns signal edge, a via is
hardly noticeable, but to a 200-ps edge a via has significant electrical complexity. To accurately
simulate GHz-level designs, complex via modeling is needed.

Sub-GHz designs are typically characterized with simple waveforms and delay values, but
GHz-level designs require special techniques like eye diagrams and jitter measurement. An eye
diagram takes the results of a simulation driven by a long, multi-cycle bit sequence,
superimposes each bit period over the top of all others, and presents a waveform that looks
something like a human eye. How open the middle of the eye is at the receiver IC is a key factor
in judging how likely the receiver is to recover each bit of arriving data. The tendency of the bits
in a complex stream to wiggle around each other (in voltage and time) is called jitter. A data
channel with too much jitter will have a high bit error rate and be unreliable.

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Library EASY.MOD
Mentor Graphics supplies thousands of IC models with BoardSim and LineSim. In addition,
new models are easy to download from the website of almost any semiconductor vendor. You
can also create your own models for specialty or unusual ICs that are not in HyperLynx or
vendor libraries.

Eye Diagrams Introduction

Interactive waveforms are generally based on single switching edges or oscillating digital
waveforms. Indeed, these types of analysis are the backbone of traditional, synchronous digital
design. However, very-high-speed SERDES-style designs are usually examined in the time
domain in a different way – by the use of eye diagrams. Eye diagrams superimpose large
numbers of bit transitions one over the other to build a view of a data stream in which new
measures of signal quality such as jitter and eye opening, can readily be judged. Many modern
oscilloscopes can run either in traditional, single-edge mode or in eye-diagram mode. Likewise,
the HyperLynx GHz oscilloscope can run in either standard or eye-diagram mode.

Note that eye diagrams can only be constructed by driving a sequence of bits down a trace. This
means that in order to generate an eye diagram, you must define multi-bit stimulus. Thus, these
two features – eye diagrams and multi-bit driving – are tightly linked.

Several distinct differences exist between generating eye diagrams with a simulation tool and
generating them in the lab with physical hardware. In the lab, it takes only a brief amount of
time to capture hundreds of millions of bit cycles from a data stream. With software-based
simulation, however, it may take many minutes to generate a thousand or even a few hundred
cycles (especially if advanced IC modeling is required). Second, whereas in the lab, test
equipment is readily available to generate statistically useful bit sequences, in software the user
has the responsibility of creating the stimulus that should be used to drive the generation of an
eye diagram.

Multi-Bit Stimulus Introduction

Some designers of SERDES-based designs today use standalone SPICE netlists to create eye
diagrams. While possible, and sometimes even necessary because a certain IC model is
available only in SPICE format, using raw SPICE for eye diagrams is usually cumbersome and
time-consuming. SPICE simulations often run very slowly, and setting up for simulation,
especially, generating stimulus patterns, is awkward.

BoardSim, by contrast, makes the generation of eye diagrams fairly easy. Set-up activities, such
as defining a stimulus pattern, are much easier in HyperLynx than directly in SPICE.
Additionally, when simulations are performed using IBIS models, eye diagrams are created
quickly.

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BoardSim Crosstalk and Differential-Signal Analysis

BoardSim offers batch and interactive post-layout signal-integrity analysis. The BoardSim
Crosstalk option adds the ability to perform crosstalk analysis of a board after layout. As with
other signal-integrity problems, crosstalk can negatively impact your final design and manifest
as false clocking, intermittent data errors, or other difficult-to-find and potentially serious
problems. It can also be difficult to know where crosstalk is likely to occur, and eliminating it
can be even trickier than fixing single-trace signal-integrity problems.

For a description of crosstalk fundamentals, see “About Crosstalk in LineSim and BoardSim”
on page 1189. To review the uncoupled signal-integrity features BoardSim offers, including
batch and interactive modes, see “Predicting Crosstalk on a Clock Net” on page 118.

How BoardSim Crosstalk Analysis Works

BoardSim enables you to simulate in both batch and interactive modes. Batch-mode simulation
includes detailed simulation (with timing and crosstalk data saved into a report file), as well as a
Quick Analysis feature that can rapidly scan your entire PCB. An aspect of Quick Analysis is a
crosstalk feature that can provide a list – sorted from most to least – of the amount of crosstalk
that could potentially appear on each net of your board. This list is particularly powerful
because it helps you determine very quickly which nets on your board are likely to have
crosstalk trouble, and merit further investigation.

BoardSim Crosstalk also offers a unique way of automatically determining which nets are
coupled to any net that is selected for simulation (interactively or in batch mode). Rather than
forcing you to specify a geometric zone around each net in which to find aggressor nets,
BoardSim Crosstalk allows you simply specify an electrical crosstalk threshold. For example,
you can say, I want to include all nets in simulation that could generate 100 mV or more of
crosstalk on my victim nets, and BoardSim will automatically find them for you. This is a much
easier, less-error-prone, more-powerful way of finding aggressor nets than by crude geometric
methods.

BoardSim crosstalk features allow you to:

• Quickly predict which nets are likely to suffer the most crosstalk, and have BoardSim
determine automatically which nets are the likely aggressors
• Use electrical rather than geometric thresholds, for more-accurate and faster
simulations. Geometric thresholds are available, too, in case you prefer them. See
“Electrical Versus Geometric Thresholds” on page 199.
• Simulate a large number of nets in batch mode, with the numerical results of each net
(timing, overshoot, crosstalk) saved into a report file
• Simulate interactively to see in oscilloscope waveforms the exact amplitude of crosstalk
on a victim net

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• See the effects on crosstalk results of changing parameters like stackup layer, dielectric
thickness, driver-IC slew rate, driver impedance, line termination, and so forth
• Confidently design high-speed buses and other PCB structures that meet tight timing
and low-crosstalk-noise requirements
• Select termination strategies that greatly reduce or eliminate the crosstalk seen at
receiver ICs

Using BoardSim Crosstalk for Differential-Signal Analysis

The BoardSim coupled-line analysis features are also valuable in the design of differential
signals, since the same line-to-line coupling that causes unwanted crosstalk on unrelated signals
also generates the differential impedance and other electrical characteristics important in
differential signaling. Specifically, you can use BoardSim to:

• Determine the differential impedance of trace pairs on your routed board, and observe
the effects of stackup layer, dielectric thickness, and so forth
• Accurately simulate differential signals, taking into account the coupling between traces
and the presence of nearby aggressor and reference (power/ground) traces
• Analyze both differential- and common-mode propagation, or any mix of the two
• Easily design terminations that work for both the differential- and common-mode
components of your signals

Automatically Finding Aggressor Nets

An important feature of BoardSim Crosstalk is that it automatically identifies which other nets
are coupled strongly enough to the selected victim net to be aggressors. Guessing is eliminated
and, as with other crosstalk-analysis tools, you do not have to specify a geometric zone which
you hope is wide enough to include all of the important aggressor nets. For more information on
this powerful capability, see “Electrical Versus Geometric Thresholds” on page 199.

Post-Layout Analysis: BoardSim and Batch Mode

Using the data from your actual routed PCB layout, BoardSim moves the HyperLynx analysis
into the post-layout phase of your design cycle. Typically, when using BoardSim after
placement and routing, the analysis is based on the actual routing details of your board.
However, you can also analyze a board as soon as placement is complete and before routing.
BoardSim creates routing using Manhattan routes. Alternatively, you can use BoardSim when
your board is placed and only partially routed.

BoardSim reads the data representing a routed PCB and performs signal-integrity and crosstalk
analysis on the actual layout. In BoardSim, signal-integrity and crosstalk results appear either as
signal waveforms in an oscilloscope when using interactive mode, or in a multi-net analysis

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report when using batch mode. Eye diagrams for high-speed serial designs are produced in the
BoardSim oscilloscope.

Simulating Multiple Boards

Many modern designs involve multiple, interconnected PCBs. For example, a motherboard with
one or more memory modules plugged in, or a system consisting of several boards joined by
connectors and cables.

The BoardSim MultiBoard option adds the ability to load multiple boards simultaneously,
interconnect them, and simulate them together as a system. Each board can be in the form of a
.HYP file, or a type of IBIS board model called .EBD (Electrical Board Description). If the
system being analyzed consists entirely of your own PCBs, you will probably load all of your
boards into BoardSim as .HYP files. However, third party boards, for example, memory
modules, may be provided in EBD format.

The EBD format is part of the IBIS specification. IBIS is best-known for modeling IC buffers.
However, the EBD format allows the modeling of random interconnect, and is used to represent
PCBs, complex IC packages, and so forth.

The main difference between a .HYP file and an EBD model is that the .HYP file is a physical
representation of the PCB: it contains details such as trace routing and stackup, which can be
viewed. EBD models, on the other hand, are an electrical representation of the PCB: the
interconnection is represented as transmission lines, with previously calculated inductance and
capacitance, or impedance and delay. An .EBD file cannot be viewed because there is no
physical information to display. Also, .EBD files cannot represent coupling. However, either
type of file can include the effects of plug-in modules and boards in a multiple-board
simulation.

Other Analysis Features and MultiBoard Designs

The primary differences between simulating with one board versus multiple boards using the
BoardSim MultiBoard option include board-to-board connectors and simulating the complete
net that spans more than one board. In addition to simulating interactively, you can run a Board
Wizard batch analysis on multiple boards, enabling delay calculations for a complete multiple-
board system.

BoardSim is hardly any more difficult to use for multiple-board analysis than for single boards.
If your connectors use consistent pin names between the mating halves, you can usually set up a
multiple-board project in a few minutes.

Simulating with EBD Models

Sometimes, you may have a PCB in a multiple-board design that is modeled with an IBIS EBD
file rather than a .HYP file. This is typically a third party board that is included in your system,

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for example, memory modules. See “Simulating Multiple Boards” on page 206 for a general
description of EBD and how it differs technically from using .HYP files.

Generally, EBD models are treated as IC models rather than explicitly as .HYP boards. The
mapping of an EBD model to a reference designator happens in the .REF or .QPL IC
automapping files, as with any other IBIS model.

After auto-mapping an EBD model and beginning analysis, BoardSim automatically creates a
board representation of the EBD model in memory, and its circuit effects are included in
simulations. You can probe inside an EBD model in the same way plug-in boards in the
multiple-board system are probed. However, a .HYP file offers better ease-of-use because it can
be viewed and can model coupling, neither of which are true for an EBD file.

Adding IC Models to Your Existing Libraries

Adding IBIS Models
HyperLynx includes a Visual IBIS Editor. This tool allows you to easily view, syntax-check,
and maintain IBIS models that you receive from vendors and other third parties. See “Creating
and Editing IBIS Models” on page 403 for details.

Adding Databook Models

To create a model of your own, the HyperLynx databook (.MOD) modeling format provides an
easy way for you to generate models from data-sheet parameters.

View the databook-model editing/generation dialog box:

1. Select Models > Edit Databook IC Models. The Edit .MOD Model dialog box opens.
2. To see the parameters from which a output driver model is generated, in the Library and
Model area, click Output. To see the parameters from which an input receiver model is
generated, click Input.
3. Fill in the parameters to add the new model to your library. Starting with an existing
model and modifying it makes this process even easier.

SPICE and Touchstone Models

LineSim GHz and BoardSim GHz offer direct integration with SPICE (your choice of HSPICE
or Eldo/ADMS). SPICE IC models can be attached to component pins directly in HyperLynx, in
just the same way as IBIS or .MOD-databook models are assigned. SPICE or Touchstone
passive-interconnect models can be placed into a special symbol in the LineSim free-form
schematic editor. Simulation occurs in SPICE under the control of HyperLynx and results are
automatically read back and displayed in the HyperLynx digital oscilloscope. See “Setting Up a
SPICE Simulation” for a demonstration of SPICE integration.

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MultiBoard Analysis with EBD Models

When using third-party boards as part of a multiple-board design, these boards can come to you
in the form of IBIS EBD files (e.g., memory modules). Generally, EBD models are treated as IC
models rather than explicitly as .HYP boards. In HyperLynx, the mapping of an EBD model to
a reference designator occurs in the .REF or .QPL IC Automapping files, just as with any other
IBIS model. See “Selecting Models and Values for Entire Components” on page 296 for
additional information.

When you connect an EBD model and begin analysis, BoardSim automatically creates a board
representation of the model in memory, and its circuit effects are automatically included in
simulations. You can even probe inside an EBD model. However, you cannot physically view
an EBD file, and EBD files are not able to model coupling. When you have a choice, always use
.HYP files over EBD files for the simulation accuracy obtained from including coupling.

Translating a Board into a BoardSim Format

Before using BoardSim, you must translate your PCB layout into a BoardSim file format
(.HYP). In some PCB-layout tools, a BoardSim translator is built-in and accessed from a menu.
For other tools, you can use an external translator supplied with BoardSim. Either way, the end
result is a .HYP file that BoardSim can read.

For a complete list of translators, see “Creating BoardSim Boards” on page 215.

LineSim Tutorials
Please click “LineSim Tutorials“. Clicking the preceding link is a workaround because the Help
menu can directly open this topic only when a schematic is loaded.

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Setting Up BoardSim

BoardSim uses reference designators in the design file to identify components. You should
verify the accuracy and completeness of the mapping between reference designators and
component types before simulating the design.

BoardSim uses several methods to identify power-supply nets, including net names (such as
GND or VCC), counting the number of capacitors connected to each net, and counting the
number of segment in each net. You can edit the number of capacitors threshold and number of
segments threshold.

This topic contains the following:

• “About Reference-Designator Mapping in BoardSim” on page 209

• “Test Points” on page 211“Helping BoardSim Recognize Power-Supply Nets” on
page 212
• “BoardSim Hint - How to Simulate Unsupported Component Types” on page 213
• “BoardSim Hint - How to Map a Reference-Designator Prefix to Multiple Component
Types” on page 213

About Reference-Designator Mapping in

BoardSim
BoardSim uses reference designators to identify the types of components on the board. The
prefix of a component in the .HYP/.CCE file maps to component types Many commonly-used
prefixes are already mapped for you. However you may have to update the mapping for other
prefixes.

Use the Edit Reference Designator Mappings Dialog Box to define the reference-designator
mappings that BoardSim uses to identify component types (IC, R, C, L, connector, and ferrite
bead).

Component Types
When BoardSim loads your board, it examines the list of devices in the board file and tries to
determine the component type of each device. BoardSim must know component types in order
to simulate correctly.

BoardSim supports these component types:

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About Reference-Designator Mapping in BoardSim

• IC (any driver or receiver device)

• Resistor
• Capacitor
• Inductor
• Ferrite bead
• Connector
• Test point
Although BoardSim does not have direct support for other component types (like transistors),
this does not mean that you cannot simulate nets that include other types.

See also: “BoardSim Hint - How to Simulate Unsupported Component Types” on page 213

The component type is unrelated to how a component is packaged. A discrete resistor and the
resistors in an R network are both type “resistor”. Package types for R and C components are
handled separately from component types.

See also: “Choosing Resistor and Capacitor Packages” on page 322

Reference-Designator Prefixes
BoardSim determines each device’s type by looking at the device’s reference-designator prefix.
“Prefix” means the first part of the reference designator (the part that stays the same for
components of the same type).

For example, if you give all of the ICs on your board a reference designator of the form “Uxx”
(U1, U2, U3A, U3B, etc.), then “U” would be the reference-designator prefix for ICs. Resistors
would commonly have a prefix of “R”. You might also have some resistor networks that you
call “RPxx” (RP1, RP2, etc.), so “RP” might also be a valid prefix for resistors.

You are free to assign whatever reference designators you want to the devices on your board;
BoardSim’s reference-designator mappings are user-definable.

See also: “Edit Reference Designator Mappings Dialog Box” on page 1553

You should not assign the same reference-designator prefix to more than one component type.
BoardSim will get confused if, for example, you call an IC “U1” and a resistor “U2”. Each
prefix can map to only one component type.

See also: “Checklist for Translating Designs to BoardSim” on page 217

There is a workaround for situations in which mapping the same reference-designator prefix to
more than one component type cannot be avoided.

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 Setting Up BoardSim
Test Points

See also: “BoardSim Hint - How to Map a Reference-Designator Prefix to Multiple Component
Types” on page 213

Related Topics
“BoardSim Hint - How to Map a Reference-Designator Prefix to Multiple Component Types”
on page 213

“BoardSim Hint - How to Simulate Unsupported Component Types” on page 213

Test Points
In BoardSim you can choose to ignore test points on your board or to treat them as IC pins. You
can treat test points as IC pins to simulate board performance in test fixture applications where
signals are probed (loaded) at test points, or where signals are injected at test points and
therefore need model assignments.

Test points are ignored by default. When you choose to ignore test points they:

• Cannot be seen in the board viewer

• Cannot have oscilloscope probes attached to them
• Cannot have device models selected for them
• Are completely ignored during simulation (i.e., they are treated as electrical “opens”)
You can ignore test points or treat them as IC pins by setting an advanced simulation
preference.

See also: “Illegal Single-Pin Components Found Dialog Box” on page 1764

How BoardSim Identifies Test Points

BoardSim contains one default mapping for test points: the prefix “TP” is assumed to indicate a
test point (i.e., components named TP1, TP2, etc. will automatically map as test points.)

If you want “TP” to indicate something other than “test point”, you can change the mapping to
another component type. Also if you want another reference designator to map to test points,
you can add a new mapping.

See also: “Edit Reference Designator Mappings Dialog Box” on page 1553

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Helping BoardSim Recognize Power-Supply Nets

One-Pin Components Automatically Treated as Test

Points
BoardSim contains one other method for automatically identifying test points: all one-pin
components are automatically assumed to be test points. (For example, if “F5” is a component
that has only one pin, F5 will automatically be treated as a test point. The same would be true of
a one-pin component called U1.) This feature is not controlled by a reference-designator
mapping and cannot be overridden; it overrides all reference-designator mappings.

Helping BoardSim Recognize Power-Supply Nets

BoardSim uses several methods to recognize which nets on your board are power-supply nets.
This information is important so BoardSim knows which nets can propagate signals and which
nets are tied to DC voltages.

See also: “Editing Power-Supply Net Properties” on page 277.

The first method involves BoardSim recognizing certain names commonly used for power-
supply nets, such as GND or VCC.

Another method involves BoardSim counting the number of capacitors connected to each of the
board’s nets, and whenever the number of capacitors exceeds a threshold value (which you can
change), considering that net to be a power supply. A third method assumes that nets with more
metal segments than some very large number (which you can change) must be power supplies.

The capacitor-counting method was added after the initial release of BoardSim to make finding
power-supply nets more likely to succeed. The capacitor-based algorithm has proven successful
across a broad spectrum of customer designs. Note that it has the advantage of finding not only
power-supply nets (which typically have large numbers of decoupling capacitors connected),
but also analog nets, which, like power-supplies, should not be simulated as digital nets in
BoardSim.

The segment-counting method was added later in response to several extremely large customer
boards on which some power supplies slipped past the other two identification methods (names
and numbers of capacitors). Because very large nets tend to slow the loading of a board file (it
takes longer to build database information for large nets), this improvement had the added
benefit of improving the time required to load large board files.

Related Topics
“Preferences Dialog Box - Advanced Tab” on page 1792

“Preferences Dialog Box - BoardSim Tab” on page 1804

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 Setting Up BoardSim
BoardSim Hint - How to Simulate Unsupported Component Types

BoardSim Hint - How to Simulate Unsupported

Component Types
BoardSim’s simulator does not have direct support for some component types. However, you
can simulate nets that include non-supported components by using components that are
supported as substitutes.

The supported components are IC, R, C, L, connector, and ferrite bead.

See also: “About Reference-Designator Mapping in BoardSim” on page 209

Diodes
The current version of BoardSim does not explicitly support diodes. However, either of
BoardSim’s IC-modeling formats supports clamp diodes, so you can use an IC model to
describe a discrete clamp diode or diode-terminating network. (The mappings for prefixes “CR”
and “D” default to “IC”.)

For example, for a net that is clamped by pin A on a clamp diode CR3, choose a receiver-IC
model for CR3.A.

You can construct your own diode model by modifying a .MOD model or an IBIS file.
BoardSim ships with a library called DIODES.MOD that shows some sample clamp diodes
implemented in the .MOD format. Note that these models use only the “input” side of the .MOD
description; it makes no sense to run them as outputs.

See also: “Editing MOD IC Models” on page 513

Other Component Types

Here are some suggestions for how to model other non-supported component types in
BoardSim:

• transistor—model as IC
• relay—model as IC
• crystal—model as IC

BoardSim Hint - How to Map a Reference-

Designator Prefix to Multiple Component Types
BoardSim maps each reference-designator prefix to one component type. If you have a board on
which a single prefix must map to more than one type, you can use the workaround described
below.

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BoardSim Hint - How to Map a Reference-Designator Prefix to Multiple Component Types

Suppose you have a board on which the prefix “U” is used mostly for ICs, but also for two
terminating networks (U1 and U20) that are actually resistors (component type “R”).

See also: “About Reference-Designator Mapping in BoardSim” on page 209

Follow these steps to map most of the U’s as ICs but U1 and U20 as “R”:

1. Setup menu > Options > Reference Designator Mappings.

2. Verify that prefix “U” is mapped to component type “IC”. (This mapping is one of
BoardSim’s default mappings.)
3. Open the .HYP file for your board in a text editor (e.g., the HyperLynx File Editor).
4. Search from the top of the .HYP file for the keyword DEVICES.
5. Then search for “U1”. You should find a line that starts:
(? REF=U1 ...
6. Change the line so that it starts:
(R REF=U1 ...
7. Go back to the DEVICES keyword.
8. Repeat 5 and 6 for reference designator “U20”.
9. Save the edited .HYP file and exit.
You may have trouble editing the .HYP file because of its size; be sure you use a text editor that
can handle large files, like the HyperLynx File Editor. Also, it is a good idea to make a copy of
the .HYP file before editing it, in case you introduce an error into the file and need to restore it.
Finally, be sure you use a text editor, not an editor that introduces non-ASCII formatting
characters into the file.

Now, when you load the .HYP file, all of the reference designators prefixed with “U” but
marked in the DEVICES list as type “?” will be mapped according to the “U = IC” mapping
rule. But U1 and U20, since they are now “hard coded” as type “R”, will be forced to map as
resistors.

See also: “BoardSim Hint - How to Simulate Unsupported Component Types” on page 213

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 Chapter 4
Creating BoardSim Boards

To load a design into BoardSim, you first translate the PCB design into a BoardSim board
(.HYP file).

Note
You can also load designs into BoardSim by opening .CCE exported from Expedition
PCB or CAMCAD Professional.

This chapter describes the translators that ship with HyperLynx. Other companies deliver
products, such as Altium Designer, that can also create BoardSim boards. When you need help
creating BoardSim boards with a 3rd-party product, refer to the documentation that ships with
that product.

The method used to create a BoardSim board depends on which board design system you are
using. Some board design systems, such as Mentor Graphics Expedition and PADS Layout,
have built-in BoardSim board creation capabilities. However with many board design systems,
you will create an ASCII board file and then run a translator on it to create the .HYP file.

This topic contains the following:

• “BoardSim Board Contents” on page 216

• “Checklist for Translating Designs to BoardSim” on page 217
• “Translators That Support Power-Integrity Simulation” on page 218
• “Translating Mentor Graphics Expedition and Board Station XE Designs” on page 220
• “Translating PADS Layout Designs” on page 222
• “Preparing Accel EDA Designs for Translation” on page 225
• “Preparing Cadence Allegro Designs for Translation” on page 227
• “Preparing Mentor Graphics Board Station and Board Station RE Designs for
Translation” on page 231
• “Preparing Specctra DSN Designs for Translation” on page 240
• “Preparing Valor ODB++ Designs for Translation” on page 241
• “Preparing Visula-CADStar for Windows Designs for Translation” on page 242
• “Preparing Zuken CR-3000 Designs for Translation” on page 244

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BoardSim Board Contents

• “Preparing Zuken CR-5000 Board Designer Designs for Translation” on page 246
• “Running the Translator” on page 247
• “Translate File Dialog Box” on page 249
• “Translator Options Dialog Box” on page 251

Tip: If your board design system is not named in the preceding list, and it cannot create a
.HYP file directly, see if it can create an ASCII board file in the Specctra DSN format. If
it can, follow the .HYP file creation instructions for the Specctra DSN translator, see
“Preparing Specctra DSN Designs for Translation” on page 240.

Related Topics
“Post-Layout Workflow” on page 49

BoardSim Board Contents

A BoardSim Board is an ASCII file, with a .HYP file extension, formatted in a HyperLynx-
proprietary format. It contains all of the information about a PCB layout needed for signal-
integrity simulation. For each board you simulate, you run a translator on your PCB-layout data
to produce a BoardSim Board file. Then, you load the BoardSim board into BoardSim and
simulate.

This topic describes the major elements in a BoardSim board. You may never need to view the
contents of a BoardSim board file, but it is helpful to have a basic understanding of what the
BoardSim board contains.

Board Outline
The board outline data defines the shape of your board. An outline can include both linear and
curved segments.

The board-outline data are optional; not all PCB-layout tools provide it. If the data is missing,
BoardSim creates a rectangular outline big enough to encompass all of the components on the
board.

Stackup
The stackup data defines your board’s layer stackup. A stackup includes information about
signal, power-plane, and dielectric layers.

The stackup data are optional; not all PCB-layout tools provide it. If the data are missing,
BoardSim will attempt to create an electrically valid stackup, but will warn you to edit it.

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Checklist for Translating Designs to BoardSim

Devices
The device data defines the components on your board. Device information includes reference
designators, component names (for ICs), and component values (for passive components).

The device data are required. BoardSim must have at least some information about the devices
on a net to perform a simulation.

Pad Stacks
The pad-stack data defines the various pad stacks used on your board. Pad-stack definitions are
optional. Some older .HYP-file translators do not use explicit pad-stack definitions; newer ones
do.

Nets
The net data defines the nets on your board. Net information includes definitions for each metal
segment, via, pad, and device pin on the board.

The net information is required. BoardSim must have detailed information about trace metal to
model and simulate the net.

Comment Lines
Comment lines in the .HYP file must have an asterisk (*) in the first column. On rare occasions,
you may wish to remove an element from a .HYP file by commenting out the element's line. For
example, if you wished to remove a resistor's pin from a certain net, you could precede the pin's
record with an asterisk:

*(PIN X=2.100 Y=2.350 R=Udrv1.1 P=PS4) This is now a comment line

Checklist for Translating Designs to BoardSim

BoardSim can handle your boards almost regardless of how you design them. This topic
describes several steps you can take to design boards for BoardSim.

• Use consistent reference designators:

BoardSim identifies what kind of component a device is — an IC, a resistor, a capacitor
— by looking at the reference-designator prefix for the device. For example, BoardSim
might map the prefix "U" to component-type IC, and "R" to type resistor. The mapping
rules are user-definable.
See also: “Edit Reference Designator Mappings Dialog Box” on page 1553

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Translators That Support Power-Integrity Simulation

It is important to use reference-designator prefixes consistently. BoardSim will get

confused if, for example, you call an IC "U1" and a resistor "U2". Each prefix should be
unique to one component type. Table 4-1 provides examples.

Table 4-1. Good and Bad Reference Designator Mappings

OK: IC "U1", IC "U2", resistor "R1", capacitor "C1"
OK: IC "X1", IC "XYZ", resistor "A001", resistor "B001"
Bad: IC "U1", resistor "U2", resistor "A1", capacitor "A100"

• Name all nets:

BoardSim does not require nets to be named, but it is easiest to choose nets for
simulation by name. If you leave a net unnamed in your board schematic, it ends up with
a computer-generated name that you probably will not recognize when trying to find it
in BoardSim.
For unnamed nets, BoardSim lets you choose nets by component reference designator
and pin name, rather than by net name.
• When creating boards, try to avoid using names (for nets, stackup layers, and other
items) that contain any of the following characters:
(){}
BoardSim uses these characters as delimiters in ASCII files, such as .HYP and .BUD
session files. HyperLynx may read names containing the delimiter characters
incorrectly.
See also: “BoardSim Session Files” on page 56
BoardSim DOES allow parentheses in IC device names.
You may also want to avoid using the plus sign + for net names. If you export a comma
separated value (CSV) file containing plus signs, Microsoft Excel interprets the plus
signs as part of a formula. The plus sign does not cause any problems in BoardSim.

Related Topics
“Creating BoardSim Boards” on page 215

Translators That Support Power-Integrity

Simulation
Simulating power integrity requires .HYP files that contain highly-detailed metal area and via
clearance information for power-distribution networks (PDNs).

The following translators support power-integrity simulation:

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 Creating BoardSim Boards
Translators That Support Power-Integrity Simulation

• Cadence Allegro—Translator that ships with HyperLynx

• Mentor Graphics Board Station® and Board Station RE —Translator that ships with
HyperLynx
• Mentor Graphics Board Station XE — Translator built into Board Station for BSXE
2007.2 or newer
• Mentor Graphics Expedition—Translator built into Expedition for EE2007.2 or newer
• PADS Layout—Translator built into PADS Layout for PADS 9.0 or newer
• Zuken CR-5000 Board Designer—Translator that ships with HyperLynx

Tip: The translator version is written to the VERSION record of the .HYP file.

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Translating Mentor Graphics Expedition and Board Station XE Designs

Translating Mentor Graphics Expedition and

Board Station XE Designs
This topic describes how to create a BoardSim board from a Mentor Graphics Expedition
(2002.2 and newer) or Board Station XE (2007.3 and newer) board design, and to load it into
BoardSim.

Prerequisites
• Expedition 2007.5 and newer or Board Station XE 2007.5 and newer — There are no
special steps to prepare the software for exporting.
• Expedition 2007.3 and Board Station XE 2007.3 —The default behavior is to create
.HYP files that support signal-integrity simulations, but are not completely accurate for
power-integrity simulations. To create .HYP files that support power-integrity
simulations you must set the system/Windows environment variable
MGC_EXP_HL_PI_ON to “1” before invoking Expedition or Board Station XE.
• Expedition 2007.2 and Board Station XE 2007.2—The only available behavior is to
create .HYP files that support both SI and PI simulations.

Procedure
1. Load your board in Expedition or Board Station XE and do one of the following:
o Select Analysis > Export to HyperLynx Power Integrity.
This creates .HYP files with sufficient information and accuracy to support both
power-integrity and signal-integrity simulations.
o Select Analysis > Export to HyperLynx Signal Integrity.
This creates .HYP files that support signal-integrity simulations, but possibly do not
contain sufficient information for power-integrity simulations.
.HYP files containing only signal-integrity information take less time to create and
consume less disk space than .HYP files supporting both SI and PI simulation.

Tip: For the latest instructions in the Expedition PCB or Board Station XE
documentation, press F1 while the pointer is over Analysis > Export to HyperLynx.

Results
The HyperLynx translator runs and creates the following files in the <jobs>/output
subdirectory:

• <jobname>.hyp, which is the BoardSim board file

• <jobname>.ref, which maps board reference designators to models

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Translating Mentor Graphics Expedition and Board Station XE Designs

• GeneralInterfaces.txt, which contains translator log information

If HyperLynx is on the same computer, Expedition PCB or Board Station XE automatically
opens HyperLynx.

Caution
We recommend that you do not share a name among your board, schematic, or multiple
board project files. BoardSim and LineSim automatically create a .PJH file (named after
your board, schematic, or multiple board project) and can overwrite previously saved
settings.

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Creating BoardSim Boards
Translating PADS Layout Designs

Translating PADS Layout Designs

This topic describes how to create a BoardSim board from a PADS board design, and to load it
into BoardSim.

Note
For the latest instructions about creating a BoardSim board from PADS Layout, see the
PADS Layout documentation.

Caution
We recommend that you do not share a name among your board, schematic, or multiple
board project files. BoardSim and LineSim automatically create a .PJH file (named after
your board, schematic, or multiple board project) and can overwrite previously saved
settings.

Prerequisites
• Specify resistor and capacitor values by setting the Value attribute for the component to
the desired number. You can set this attribute either directly in PADS Layout, or in the
schematic (PADS Logic or DxDesigner®). See “Setting Resistor and Capacitor Values
for BoardSim” on page 223.

Procedure
1. Load your board in PADS Layout and do one of the following:
• HyperLynx is installed on the computer—Select Tools > Analysis > Signal/Power
Integrity.
• HyperLynx is not installed on the computer—Select File > Export > Save As HYP
Files > Save.
2. If needed, change the translator options.
3. Click OK.
The translator in PADS Layout runs and creates the BoardSim board.

Results
If you enabled modeling for unrouted nets, any such nets will be displayed in the board viewer
as narrow, point-to-point connections, rather than "normal" routed traces with realistic widths.
However, BoardSim uses the default trace width of the unrouted nets’ "Assumed Layer" when it
calculates the impedances of the nets’ segments.

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Translating PADS Layout Designs

Related Topics
“Creating BoardSim Boards” on page 215

Setting Resistor and Capacitor Values for BoardSim

PADS Layout can pass resistor and capacitor values directly to BoardSim board, ready for use
in BoardSim.

To specify a resistor or capacitor value, set the Value attribute for the component to the desired
number. You can set this attribute either directly in PADS Layout, or in the schematic (PADS
Logic or DxDesigner).

For passive components (Rs, C, Ls), BoardSim will properly convert the value if it is expressed
in the form of:
Table 4-2. Passive Component Value Formatting for PADS Layout
<number><suffix> where <number> is the numeric value and <suffix> is
an optional scaling suffix. See "Supported Scaling
Factor Suffixes" below.
Or
<number><scientific notation> where <scientific notation> is exxx or Exxx
xxx is any integer value, positive or negative

Table 4-3. Supported Scaling Factor Suffixes for PADS Layout

Suffix Name Scale
M mega 1,000,000x
K or k kilo 1,000x
m milli 0.001x
u or U micro 1e-6x
n or N nano 1e-9x
p or P pico 1e-12x

Supported Units
For units, you can use "ohm" or "farad" or "F". If no scaling factor is used, these units are "safe"
because the first letter of each ("o" in ohm and "f" in farad) will not be confused with a scaling
factor.

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Translating PADS Layout Designs

Examples
In the examples below, <other_Part_Type_information> means whatever additional, non-value
information you would normally have in the Part Type attribute.

<other_Part_Type_information>,100

<other_Part_Type_information>,33.0e-12

<other_Part_Type_information>,33.0p

<other_Part_Type_information>,33pF

<other_Part_Type_information>,33pFarads

<other_Part_Type_information>,10k

<other_Part_Type_information>,100Kohm

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 Creating BoardSim Boards
Preparing Accel EDA Designs for Translation

Preparing Accel EDA Designs for Translation

This topic describes how to create a BoardSim board from an Accel EDA (Sequoia) board
design, and load it into BoardSim.

Restriction: The Accel EDA translator is compatible with Accel P-CAD PCB, and Accel
Tango PCB (the "Sequoia" technology). It is not compatible with older, pre-Sequoia versions of
P-CAD or most old versions of Tango.

The Accel EDA translator runs on an ASCII version of your board file (.PCB). The translator
cannot read a binary .PCB file.

Prerequisites
Define passive-component values (values for resistors, capacitors, inductors) and IC names
using the Accel EDA Value attribute, see “Defining Component Values and IC Names” on
page 225.

Procedure
1. Load your design in Accel EDA.
2. Select File > Save As.
3. In the file type list, click ASCII.
4. Click OK. This creates an ASCII version of the design.
5. Open HyperLynx and translate your design, see “Running the Translator” on page 247.

Caution
We recommend that you do not share a name among your board, schematic, or multiple
board project files. BoardSim automatically creates a .PJH file (named after your board,
schematic, or multiple board project) and can overwrite previously saved settings.

Defining Component Values and IC Names

The translator takes passive-component values (values for resistors, capacitors, inductors) and
IC names from the Accel EDA "Value" attribute. Set the Value attribute in Accel EDA as
follows:

Procedure
1. Load your design in Accel EDA.
2. Select Edit > Components.
3. In the Components list, select the component whose value you wish to set.

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Preparing Accel EDA Designs for Translation

4. Click Properties.
5. Select the Pattern tab and, in the upper left corner, type the desired value in the Value
field.
6. Open HyperLynx and translate your design, see “Running the Translator” on page 247.

Results
For passive components (Rs, C, Ls), BoardSim will properly convert the value if it is expressed
in the forms provided in Table 4-4. and Table 4-5

Table 4-4. Passive Component Value Formatting for Accel EDA Translator
<number><suffix> where <number> is the numeric value and <suffix> is
an optional scaling suffix. See "Supported Scaling
Factor Suffixes" below.
Or
<number><scientific notation> where <scientific notation> is exxx or Exxx
xxx is any integer value, positive or negative

Table 4-5. Supported Scaling Factor Suffixes for Accel EDA Translator
Suffix Name Scale
M mega 1,000,000x
K or k kilo 1,000x
m milli 0.001x
u or U micro 1e-6x
n or N nano 1e-9x
p or P pico 1e-12x

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 Creating BoardSim Boards
Preparing Cadence Allegro Designs for Translation

Preparing Cadence Allegro Designs for

Translation
This topic describes how to create a BoardSim board from a Cadence Allegro board and load it
into BoardSim. The translator supports both the native binary design files (.BRD) and ASCII
design files.

You can run the translator directly on native binary files (.BRD) when both Cadence Allegro
and HyperLynx are installed on the same computer. The translator requires the Allegro Extracta
ASCII-extraction utility to be fully installed on the computer. It is not sufficient to copy the
Extracta executable file to the computer. Cadence Allegro and Allegro Physical Viewer (also
known as Cadence Viewer Plus) include Extracta. Note that Allegro FREE Physical Viewer
does not include Extracta.

The translator can also run on an ASCII version of the board. This capability is needed when
you do not have access to Cadence Allegro (and its Extracta utility), but can access an ASCII
version of the board. For example, you may rely on a PCB layout service bureau and they can
run Allegro Extracta to create the ASCII files and send them to you.

Note
The HyperLynx translator is licensed. You cannot copy the algbrd2hyp.exe translator file
to a computer with Cadence Allegro and run it.

Prerequisites
If the Allegro design contains static metal shapes, update the void data prior to creating an
ASCII version of the design. See “Updating Void Data in Static Metal Shapes” on page 229.

Procedure
• If HyperLynx and Allegro are installed on the same computer:
a. Open HyperLynx.
b. Select File > New Board and translate the design using the BRD file. See “Running
the Translator” on page 247.
• If HyperLynx and Allegro are installed on different computers:
Caution: Be sure to name the output files exactly as described below, because the
HyperLynx translator looks for only those names.
a. Copy control_hyp.txt and control_hyp2.txt to the folder containing the design.
These files are installed in the folder containing the HyperLynx application file
bsw.exe (Windows) or bsw (Linux/UNIX). For example
C:\MentorGraphics\<release>\SDD_HOME\hyperlynx.

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Preparing Cadence Allegro Designs for Translation

b. Open a command window, cd to the design folder, and type the following:
extracta <design>.brd control_hyp.txt <design>.a_b
<design>_COMPONENT.txt <design>_COMPONENT_PIN.txt
<design>_COMPOSITE_PAD.txt <design>_CONNECTIVITY.txt
<design>_FULL_GEOMETRY.txt <design>_LAYER.txt

For a brief description of the contents of these files, see Table 4-6 on page 229.
Result: The command window displays the extraction progress and completion
message. The extractor creates log and error files in the current folder.
c. In the same command window and folder, type the following:
extracta <design>.brd control_hyp2.txt <design>_NET.txt
<design>_RAT_PIN.txt <design>_SYMBOL.txt

Note: This step uses control_hyp2.txt instead of control_hyp.txt.

For a brief description of the contents of these files, see Table 4-6 on page 229.
Result: The command window displays the extraction progress and completion
message. The extractor creates log and error files in the current folder.
d. Copy the files in Table 4-6 on page 229 to a location that a computer with
HyperLynx can access.
e. Open HyperLynx and translate your design, see “Running the Translator” on
page 247.

Note
The Cadence Extracta ASCII-extraction utility must be fully installed on the computer to
create the ASCII version of the design. It is not sufficient to copy the Extracta executable
file to the computer. Cadence Allegro and Allegro Physical Viewer (also known as
Cadence Viewer Plus) include Extracta. Note that Allegro FREE Physical Viewer does
not include Extracta.

Caution
We recommend that you do not share a name among your board, schematic, or multiple
board project files. BoardSim and LineSim automatically create a .PJH file (named after
your board, schematic, or multiple board project) and can overwrite previously saved
settings.

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Preparing Cadence Allegro Designs for Translation

Table 4-6. Extracted Cadence Allegro ASCII Files

File Name Contains

<fname> is the basename of the

Allegro board file
<fname>.a_b Stackup and outline information for the board
<fname>_COMPONENT.txt Component information
<fname>_COMPONENT_PIN.txt Component pin information
<fname>_COMPOSITE_PAD.txt Pad data from symbol pins and vias in the design
<fname>_CONNECTIVITY.txt Connectivity information
<fname>_FULL_GEOMETRY.txt Geometry and pad data
<fname>_LAYER.txt Physical layer data
<fname>_NET.txt Net data
<fname>_RAT_PIN.txt Component pin and ratnesting data for a net
<fname>_SYMBOL.txt Symbol data

Related Topics
“Creating BoardSim Boards” on page 215

Updating Void Data in Static Metal Shapes

If the Allegro design contains static metal shapes, update the void data prior to creating an
ASCII version of the design. This step ensures that proper clearances exist around padstacks
and between metal shapes. Maximum data fidelity is especially needed for accurate power-
integrity simulations, such as decoupling capacitor analysis.

Note
Steps described in this topic are unnecessary for dynamic metal shapes, which
automatically create and adjust voids when something in the design changes. Allegro
15.0 and newer support dynamic metal shapes.

Steps to update void data in static metal shapes:

1. Optionally, create a copy of the design to use for analysis purposes.

2. In Allegro, perform the void operation on each static metal shape.

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For example, if the void clearance settings in Allegro are correct, the void operation may
be performed with the Shape > Manual Void > Element >
<select_a_static_metal_shape> sequence.

Related Topics
“Preparing Cadence Allegro Designs for Translation” on page 227

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Preparing Mentor Graphics Board Station and

Board Station RE Designs for Translation
This topic describes how to create a BoardSim board from a Mentor Graphics Board Station
Layout or Board Station RE board design, and load it into BoardSim.

The translator supports Board Station release 8.

Tip: Some versions of Board Station may not have the LIBRARIAN function. If your
version does not, use instead the Select PCB Diagram option in the LAYOUT portion of
the program.

Prerequisites
• If you want the translator to automatically create a .REF automapping file, use Board
Station Layout to add simulation model properties to components in the design. See
“Adding Simulation Model Properties to Components” on page 233.
• Add assembly variant names to components. You can run the Board Station to
HyperLynx translator on designs containing the component assembly variant attributes
MULTI_ASSY or EXCEPT_ASSY. You might use these attributes when the board can
be populated with different sets of components during assembly. See “Adding Assembly
Variant Names to Components” on page 233.
• If you are using Board Station Layout, configure Layout to create ASCII files, see
“Configuring Layout to Create ASCII Files” on page 237.

Procedure
1. Create an ASCII version of the board file using Layout or Librarian:
• Layout steps:
Note: For Layout, we provides AMPLE Userware script information that simplifies
the ASCII generation procedure.
i. Open Board Station Layout and load the design you want to translate.
ii. Select File > Create HyperLynx Files.
Result: The translator writes the following files to the $HOME\hyperlynx_files
directory: <boardname>.CMP, <boardname>.NET, <boardname>.PRT,
<boardname>.TEC and <boardname>.WIR.
• Librarian steps:
iii. In Board Station's LIBRARIAN functions, select LOAD PART FILE.

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iv. Select SAVE GEOMETRY ASCII. The ASCII files are created.
Or
v. In Board Station's LIBRARIAN functions, click MGC, and select the Design
Management function.
vi. Do a "COPY OBJECT."
vii. Select ASCII_GEOM as the source file and type <boardname.PRT> as the
output file name. The ASCII files are created.
2. If needed, rename the generated ASCII files to the file names required by the translator,
see “Board Station Layout Files Required by the Translator” on page 238
3. If needed, copy the required files to the computer where HyperLynx is installed.
4. Open HyperLynx and run the translator, see “Running the Translator” on page 247.

Tip: If your design contains assembly variant names, choose which variant-related
components to include in the .HYP file by using the “-a” command-line switch when
running the Board Station to HyperLynx translator (see Translator Options Dialog Box).
The “-a” switch is optional and if you do not use it, the translator writes all components to
the .HYP file.

Additional Information
• Board Station names (e.g., Padstacks, Parts, etc.) are not handled as case sensitive by the
translator.
• All vias must be part of a net.
• No $$ADD commands are supported, except in create_board mode.
• Only one VIEW per translation is supported.
• The WIRE/TRACE file can contain AREAs, which are filled polygons. These polygons
can have overlapping sides. (Overlapping sides are polylines that lie on top of existing
polylines and therefore do not form a "good" polygon.)
• The "Solder Layer" must be known by the translator for proper operation. The "Solder
Layer" is derived by the translator as follows:
a. SOLDERSIDE layer name (SIGNAL _xx) from the Board Station .TEC file is used.
b. XRF: the highest signal number from the wire reference table is used.
c. Routing_Layer attribute, i.e. the layer SIGNAL_number_of_routing_layers
• Unplaced components are positioned at location 0,0.

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• Attribute "DRILL_DEFINITION_UNPLATED" is not implemented (i.e., free standing

drill holes).

Related Topics
“Creating BoardSim Boards” on page 215

Adding Simulation Model Properties to Components

If you want the translator to automatically create a .REF automapping file, use Board Station
Layout to add simulation model properties to components in the design.

This is an optional step. You can manually create the .REF file in BoardSim.

See also: “Selecting Models and Values for Entire Components” on page 296

Procedure
1. In Board Station Layout, open the design you want to translate.
2. Select the component.
3. On the Properties menu, point to Component Properties, and click Component
Properties.
4. In the Add Property to Component dialog box, select Specify Name.
5. To specify model library information, do the following:
a. In the Name field, type HYP_LIB.
b. In the Value field, type the library file name. For example, lv032atm.lib.
6. To specify model name information, do the following:
a. In the Name field, type HYP_DEVICE.
b. In the Value field, type the model name. For example, DS90LV32ATM.
7. Click OK.
8. Repeat steps 2-6 as needed.

Adding Assembly Variant Names to Components

You can run the Board Station to HyperLynx translator on designs containing the component
assembly variant attributes MULTI_ASSY or EXCEPT_ASSY. You might use these attributes
when the board can be populated with different sets of components during assembly. Variant
information comes from the .CMP file.

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The translator looks for components with the MULTI_ASSY or EXCEPT_ASSY attribute
along with an assembly variant name. Use the usual and customary methods to assign attributes
to the design.

The HyperLynx .HYP file cannot contain variant information, so you choose which variant-
related components to include in the .HYP file by using the “-a” command-line switch when
running the Board Station to HyperLynx translator (see Translator Options Dialog Box). The “-
a” switch is optional and if you do not use it, the translator writes all components to the .HYP
file.

Table 4-7 shows the supported <variant_name> parameter usage.

Table 4-7. Board Station Variant Name Parameter Usage
<attribute> in <variant_name> You Result
.CMP File Supply
MULTI_ASSY A string identifying the Components with a matching variant name
name of the variant to are included in the .HYP file.
include in the .HYP file.
Components with a non-matching variant
name are not included in the .HYP file.
EXCEPT_ASSY A string identifying the Components with a matching variant name
name of the variant to are not included in the .HYP file.
exclude in the .HYP file.
Components with a non-matching variant
name are included in the .HYP file.
MULTI_ASSY or No string provided. All components are included in the .HYP
EXCEPT_ASSY file.

For an illustration of how the -a switch can affect translation results, see “Variant Translation
Examples” on page 234.

Variant Translation Examples

To illustrate how the -a switch works, let us translate a fictitious design three times by varying -
a switch values. A fragment of the .CMP file for the design includes these components:

U2 IOCTRL ICH5 mBGA460 444500 336176 1 0 (HIERARCHY,"/SBRIDGE_1") - \

MULTI_ASSY,"test_var0")
U3 IOCTRL ICH5 mBGA460 261470 336176 1 0 (HIERARCHY,"/SBRIDGE_2") - \
MULTI_ASSY,"test_var1")

Note
A backslash \ at the right end of a row represents line continuation, and is used when the
line is too wide to fit on the documentation page.

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The command line argument is -a <variant_name>. If the part in the .CMP file has
MULTI_ASSY and the variant name matches, the part is not deleted. If EXCEPT_ASSY is
used, the logic is reversed. This document does not contain an example using EXCEPT_ASSY.

Example 1 - No variants are added to .HYP file because no variant name matches "xxx"

C:\MentorGraphics\<flow>\SDD_HOME\hyperlynx\ment2hyp -a xxx C:\testdesign

ment2hyp: Mentor Graphics Board Station to HyperLynx Translator V: 8.0.71

Copyright Mentor Graphics Corporation 2009.
All rights reserved.

info : reading in Mentor data

info : initialising
info : reading and parsing Mentor design database
info : ...reading and parsing GEOMS file
info : ...reading and parsing COMPS file
info : ...reading and parsing NETS file
info : ...reading and parsing TRACES file
info : ...reading and parsing TECHNOLOGY file
info : processing Mentor data
info : ...processing layers
info : ...processing board outline
info : ...processing padstacks
info : ...processing shapes
info : ...processing components
Comp :U2: is unplaced or excluded from assembly; omitted from HYP
Comp :U3: is unplaced or excluded from assembly; omitted from HYP
Rev 0.1 January 2007 Page 3 of 5
info : ...processing pins
info : ...processing nets
info : ...processing break-out patterns
info : ...processing unused pins
info : writing out data in HYP format
info : writing .ref file
info : cleaning up
info : done writing out data in HYP format

Example 2 - Variant test_var0 is added to .HYP file, variant test_var1 is not

C:\MentorGraphics\<flow>\SDD_HOME\hyperlynx\ment2hyp -a test_var0 \
C:\testdesign

ment2hyp: Mentor Graphics Board Station to HyperLynx Translator V: 7.7.55

Copyright Mentor Graphics Corporation 2006.
All rights reserved.

info : reading in Mentor data

info : initialising
info : reading and parsing Mentor design database
info : ...reading and parsing GEOMS file
info : ...reading and parsing COMPS file
info : ...reading and parsing NETS file
info : ...reading and parsing TRACES file
info : ...reading and parsing TECHNOLOGY file
info : processing Mentor data

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info : ...processing layers

info : ...processing board outline
info : ...processing padstacks
info : ...processing shapes
info : ...processing components
Comp :U3: is unplaced or excluded from assembly; omitted from HYP
info : ...processing pins
info : ...processing nets
info : ...processing break-out patterns
info : ...processing unused pins
info : writing out data in HYP format
info : writing .ref file
info : cleaning up
info : done writing out data in HYP format

Example 3 - Variant test_var1 is added to .HYP file, variant test_var0 is not

C:\MentorGraphics\<flow>\SDD_HOME\hyperlynx\ment2hyp -a test_var1 \
C:\testdesign

ment2hyp: Mentor Graphics Board Station to HyperLynx Translator V: 7.7.55

Copyright Mentor Graphics Corporation 2006.
All rights reserved.

info : reading in Mentor data

info : initialising
info : reading and parsing Mentor design database
info : ...reading and parsing GEOMS file
info : ...reading and parsing COMPS file
info : ...reading and parsing NETS file
info : ...reading and parsing TRACES file
Rev 0.1 January 2007 Page 4 of 5
info : ...reading and parsing TECHNOLOGY file
info : processing Mentor data
info : ...processing layers
info : ...processing board outline
info : ...processing padstacks
info : ...processing shapes
info : ...processing components
Comp :U2: is unplaced or excluded from assembly; omitted from HYP
info : ...processing pins
info : ...processing nets
info : ...processing break-out patterns
info : ...processing unused pins
info : writing out data in HYP format
info : writing .ref file
info : cleaning up
info : done writing out data in HYP format

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Configuring Layout to Create ASCII Files

To configure Layout to create ASCII files:

1. Depending on how you installed Board Station, create an ASCII file named
layout.startup and a folder named startup, if it does not already exist, in one of the
following locations:
• Site specific: $HOME\shared\etc\cust\startup\layout.startup
Example: If $HOME is C:\MentorGraphics, create layout.startup in the
C:\MentorGraphics\shared\etc\cust\startup folder.
• Workstation specific: $HOME\etc\cust\startup\layout.startup
Example: If $HOME is C:\MentorGraphics, create layout.startup in the
C:\MentorGraphics\etc\cust\startup folder.
• User specific: $HOME\mgc\startup\layout.startup
Example: If $HOME is C:\MentorGraphics, create layout.startup in the
C:\MentorGraphics\mgc\startup folder.
2. Paste the following text into the file and save the file:
$insert_menu_item($menu_text_item("Create _Hyperlynx Files",
"create_hyperlynx_files()"), , "file_pulldown", @last);
Requirement: This text must be on a single line.
3. In the $HOME\mgc\userware\layout folder:
• If the file lay_area.ample already exists, append to the end of that file the function
create_hyperlynx_files() and its definition mentioned in step 5.
• If the file lay_area.ample does not exist, create a new ASCII file with that name.
Example: If $HOME is C:\Designs, lay_area.ample is located in the
C:\Designs\mgc\userware\layout folder.
4. Set the environment variable AMPLE_PATH to point to $HOME\mgc\userware.
5. Paste the following text into the lay_area.ample file and save it:
function create_hyperlynx_files()
{
local hyperfile_dir =
$strcat($get_design_name(),"/hyperlynx_files");
local board_name = $strcat("/", $get_board_name());
local hyperfile_name = $strcat(hyperfile_dir, board_name);
$writeln($strcat("writing hyperlynx files to ", hyperfile_dir));
$system($strcat("mkdir ", hyperfile_dir), @true);
$save_ascii_geometries($strcat(hyperfile_name, ".prt"), [""],
@replace, @all, @nodirectory, @version);

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$save_traces($strcat(hyperfile_name, ".wir"), @replace, @pathname,

@noguide, @partial_routes_also);
$save_nets($strcat(hyperfile_name, ".net"), @replace, @pathname);
$save_components($strcat(hyperfile_name, ".cmp"), @replace,
@pathname);
$save_technology($strcat(hyperfile_name, ".tec"), @replace,
@pathname);
}

Result: The Create HyperLynx File item is added to the Board Station Layout menu.
When you click Create HyperLynx Files on the File menu, Layout automatically creates
the ASCII files needed by the translator.

Board Station Layout Files Required by the Translator

Layout automatically creates the correct file names if you use Layout to create the ASCII files,
using the AMPLE script information described in “Configuring Layout to Create ASCII Files”
on page 237.

Caution
We recommend that you do not share a name among your board, schematic, or multiple
board project files. BoardSim and LineSim automatically create a .PJH file (named after
your board, schematic, or multiple board project) and can overwrite previously saved
settings.

The Board Station to HyperLynx translator requires each ASCII file to have a specific filename
extension. The following table summarizes the required filename extensions, common default
file names, and ASCII file descriptions:

Table 4-8. Required ASCII File Names for Board Station Translator
File names required Other common file Description
by translator names
<boardname>.PRT GEOMS_ASCII Includes geometry data such as package
shapes, decals, and so on.
<boardname>.WIR TRACES.TRACES_<#> Includes completely or partially routed
trace data, specifically the routed segment
vertices for each trace.
<boardname>.NET NETS_FILE, Includes electrical pin-to-pin connections
nets.nets_<#> such as the component pins belonging to
each net.
<boardname>.CMP COMP_FILE, Includes component information such as
comps.comps_<#> reference designator, part number (or part
type), geometry, and location.

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Table 4-8. Required ASCII File Names for Board Station Translator
<boardname>.TEC Includes board stackup information.

The translator does not require this file to

create a BoardSim board.

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Creating BoardSim Boards
Preparing Specctra DSN Designs for Translation

Preparing Specctra DSN Designs for Translation

This topic describes how to create a BoardSim board from a Specctra DSN file, and load it into
BoardSim.

The Specctra DSN format was previously named CCT, for the previous owners: Cooper and
Chan Technology, Inc.

Procedure
1. Create an ASCII Version of the Board File using your PCB CAD software. Follow the
usual and customary procedures to create a Specctra DSN file.
2. Open HyperLynx and translate your design, see “Running the Translator” on page 247.

Caution
We recommend that you do not share a name among your board, schematic, or multiple
board project files. BoardSim and LineSim automatically create a .PJH file (named after
your board, schematic, or multiple board project) and can overwrite previously saved
settings.

Related Topics
“Creating BoardSim Boards” on page 215

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Preparing Valor ODB++ Designs for Translation

Preparing Valor ODB++ Designs for Translation

This topic describes how to create a BoardSim board from an ODB++ board design file, and
load it into BoardSim.

Procedure
1. Perform the usual and customary procedures to create the <board_name>.odb file from
your PCB design system.
2. Open HyperLynx and translate your design, see “Running the Translator” on page 247.

Caution
We recommend that you do not share a name among your board, schematic, or multiple
board project files. BoardSim and LineSim automatically create a .PJH file (named after
your board, schematic, or multiple board project) and can overwrite previously saved
settings.

Related Topics
“Creating BoardSim Boards” on page 215

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Preparing Visula-CADStar for Windows Designs for Translation

Preparing Visula-CADStar for Windows Designs

for Translation
This topic describes how to create a BoardSim board from a Visula or CADStar for Windows
board design, and load it into BoardSim.

Caution
We recommend that you do not share a name among your board, schematic, or multiple
board project files. BoardSim and LineSim automatically create a .PJH file (named after
your board, schematic, or multiple board project) and can overwrite previously saved
settings.

The translator reads CADIF-format “neutral-database” files, which normally have a file
extension of .PAF.

Prerequisites
CADStar for Windows only: For designs containing alphanumeric pin names, create the
<design>.cpa (CADSTAR PCB Archive) file to extract the pin names. See “Creating an
Alphanumeric Pin Name File” on page 243.

Procedure
1. From Visula or CADStar for Windows, create a .PAF file with the same file name as for
your board.
Note: For Visula, this step must be run on a UNIX workstation, either directly or via a
TELNET session from your Windows computer; if you don't have access to a
workstation, ask your layout engineer or service bureau to run this for you.
2. Open HyperLynx and translate your design, see “Running the Translator” on page 247.

Results
• Padforms are derived from the PADASSIGN section (not from the padstack section).
Therefore PADFORMS are the same, regardless of the placement side of the shape.
• All pins are converted to the original defined pin numbers (not the optional pin names).
• Only 90-degree pad rotation is allowed.
• Diamond padforms are treated as round.
• Bullet padforms are treated as "finger."
• Dimension entities are ignored.
• Taper line ends and pads are ignored.

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• Copper areas and voids are not completely supported.

• Closed polylines containing arcs will not be filled.

Related Topics
“Creating BoardSim Boards” on page 215

Creating an Alphanumeric Pin Name File

For designs containing alphanumeric pin names, the translator requires the <design>.cpa
(CADSTAR PCB Archive) file to extract the pin names.

This capability is unavailable for Visula.

Procedure
1. Open the design in CADSTAR.
2. Select File > File Export.
The Export to File dialog box opens.
3. In the Format list, select PCB Archive.
4. Browse to save the .CPA file in the same folder that contains the ASCII version of the
design.
5. Click OK.

Related Topics
“Preparing Visula-CADStar for Windows Designs for Translation” on page 242

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Preparing Zuken CR-3000 Designs for Translation

Preparing Zuken CR-3000 Designs for

Translation
This topic describes how to create a BoardSim board from a Zuken CR-3000 board design, and
load it into BoardSim.

Caution
We recommend that you do not share a name among your board, schematic, or multiple
board project files. BoardSim and LineSim automatically create a .PJH file (named after
your board, schematic, or multiple board project) and can overwrite previously saved
settings.

Use the UNIX shell script called ZUKXTRACT that calls a series of CR-3000 utility programs to
create an ASCII representation of your board design. ZUKXTRACT is initially installed in the
same directory as BoardSim, on your Windows computer. Copy it to a workstation for use with
the CR-3000 utility programs.

Prerequisites
The ZUKXTRACT script was designed to run in an English-language environment. If you are
running instead in a Japanese or other non-English environment, you must add the following
two lines to the beginning of the script file:

setenv ZLANG english

setenv ZNLSLANG english

Procedure
1. On a UNIX workstation with access to the CR-3000 utility programs, run the shell script
ZUKXTRACT. The script will call several CR-3000 utilities and generate a series of
ASCII files representing your PCB.
ASCII files with the following extensions will be created: BSF, UDF, MDF, WDF,
WSF, CCF.
2. Move the intermediate ASCII files (.BSF, .UDF, .MDF, .WDF, .WSF, and .CCF)
created by the ZUKXTRACT script to the Windows computer that has BoardSim
installed. Then continue with the translation process on your Windows computer as
described in the next section.
3. Open HyperLynx and translate your design, see “Running the Translator” on page 247.

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Tip: The script file ZUKXTRACT is a UNIX shell script; therefore, it can only be
executed on a UNIX workstation (not on your Windows computer). If you attempt to run
the script and it fails because it cannot find the appropriate CR-3000 utility programs,
contact your CAD manager or network administrator for assistance. ZUKXTRACT must
be able to call the CR-3000 utility programs in order to run successfully.

Related Topics
“Creating BoardSim Boards” on page 215

“Preparing Zuken CR-5000 Board Designer Designs for Translation” on page 246

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Preparing Zuken CR-5000 Board Designer Designs for Translation

Preparing Zuken CR-5000 Board Designer

Designs for Translation
This topic describes how to create a BoardSim board from a Zuken CR-5000 Board Designer
design, and load it into BoardSim.

Restriction: The translator does not translate Zuken CR-5000 PWS designs.

Procedure
1. Using CR-5000 Board Designer, perform the usual and customary procedures to create
both of the ASCII files in the following table, using the same file name as for your
board:

Table 4-9. Contents of ASCII Files for CR-5000 Board Designer

ASCII file Contains
<board_name>.pcf PCB data
<board_name>.ftf Footprint data

2. Open HyperLynx and translate your design, see “Running the Translator” on page 247.

Caution
We recommend that you do not share a name among your board, schematic, or multiple
board project files. BoardSim and LineSim automatically create a .PJH file (named after
your board, schematic, or multiple board project) and can overwrite previously saved
settings.

Related Topics
“Creating BoardSim Boards” on page 215

“Preparing Zuken CR-3000 Designs for Translation” on page 244

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Running the Translator

Running the Translator

Finish the translation by running the translator.

Tip: If you plan to translate a BRD file, you must fully install the Cadence Extracta
ASCII-extraction utility to run the translator. It is not sufficient to copy the Extracta
executable file to the computer. Cadence Allegro and Allegro Physical Viewer (also
known as Cadence Viewer Plus) include Extracta. Allegro FREE Physical Viewer does
not include Extracta.

Procedure
1. Click Translate PCB to BoardSim Board . The Chose A File To Translate dialog
box opens.
2. In the Files Of Type list, select the type of file to translate and double-click the board file
you want to translate. The Translate File dialog box opens.
Restriction: .BRD files are displayed only if the CDSROOT environment variable is
defined. This environment variable is defined when you install Cadence software such
as Allegro or Allegro Physical Viewer (also known as Cadence Viewer Plus).
3. To specify translator options, do the following:
a. Click Options. The Translator Options Dialog Box opens.
b. Edit options in the Standard Options area.
Board Station RE Only: If the design contains variants, use the -a <variant_name>
option. See “Adding Assembly Variant Names to Components” on page 233. For an
illustration of how the -a switch can affect translation results, see “Variant
Translation Examples” on page 234.
Leave the Non-Standard Command-Line Options field empty, unless advised
otherwise by Mentor Graphics staff.
c. Click OK.
4. To run translation only, click Translate.
Alternative: To run translation and automatically load the board, click Translate &
Open. If the BoardSim board (.HYP file) is created, the Translate File dialog box closes
automatically and you can skip steps 5-6.
Results:
• A command window opens and displays translator progress. When translation is
complete the command window closes and the translation status is displayed in
Translate File dialog box, above the Translate button.

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Running the Translator

• The .HYP file, error file, and log file are written to the same directory that contains
the board file.
5. To view the .HYP file or report files after translation is complete, do the following:
• To view the .HYP file, click View .HYP File. This button is unavailable if the .HYP
file is not created.
• To view the error file, click View .ERR File.
• To view the log file, click View .LOG File.
To change the Report File Viewer from read only mode to edit mode, click Read Only
on the Viewer's Options menu.
6. Click Done.

Related Topics
“Preparing Zuken CR-5000 Board Designer Designs for Translation” on page 246

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Translate File Dialog Box

Translate File Dialog Box

To access:
• Select File > New Board (Run PCB Translator) and select a file to translate from the
Choose a File to Translate dialog box.
• Click Translate PCB to BoardSim Board . The Chose A File To Translate dialog
box opens.
In the Files Of Type list, select the type of file to translate and double-click the board file
you want to translate. The Translate File dialog box opens.
Restriction: .BRD files are displayed only if the CDSROOT environment variable is
defined. This environment variable is defined when you install Cadence software such
as Allegro or Allegro Physical Viewer (also known as Cadence Viewer Plus).
Use this dialog box to translate PCB boards to the BoardSim .HYP format.
The method used to create a BoardSim board depends on which board design system you are
using. Some board design systems, such as Mentor Graphics Expedition and PADS Layout,
have built-in BoardSim board creation capabilities. However with many board design systems,
you will create an ASCII board file and then run a translator on it to create the BoardSim board.

Tip: You can export .HYP files directly from Mentor Graphics Expedition, and Board
Station XE, and PADS Layout designs. For more information see, Translating Mentor
Graphics Expedition and Board Station XE Designs and Translating PADS Layout
Designs.

For instructions on how to prepare a design for translation, see:

• Preparing Accel EDA Designs for Translation

• Preparing Cadence Allegro Designs for Translation
• Preparing Mentor Graphics Board Station and Board Station RE Designs for Translation
• Preparing Specctra DSN Designs for Translation
• Preparing Valor ODB++ Designs for Translation
• Preparing Visula-CADStar for Windows Designs for Translation
• Preparing Zuken CR-3000 Designs for Translation
• Preparing Zuken CR-5000 Board Designer Designs for Translation

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Translate File Dialog Box

Figure 4-1. Translate File Dialog Box

Table 4-10. Translate File Dialog Box Contents

Field Description
Browse Use to select a file to translate. Opens the Choose A File To Translate
dialog box.

In the Files Of Type list, select the type of file to translate and double-
click the board file you want to translate. The Translate File dialog
box opens.

Restriction: .BRD files are displayed only if the CDSROOT

environment variable is defined. This environment variable is defined
when you install Cadence software such as Allegro or Allegro
Physical Viewer (also known as Cadence Viewer Plus).
Options Set translator options. Opens the Translator Options Dialog Box.
Translate Runs translation only. Does not load the design in BoardSim.

A command window opens and displays translator progress. When

translation is complete the command window closes and the
translation status is displayed in Translate File dialog box, above the
Translate button.

The .HYP file, error file, and log file are written to the same directory
that contains the board file.

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Table 4-10. Translate File Dialog Box Contents

Field Description
Translate & Open Runs translation and automatically loads the board. If the BoardSim
board (.HYP file) is created, the Translate File dialog box closes
automatically.

A command window opens and displays translator progress. When

translation is complete the command window closes and the
translation status is displayed in Translate File dialog box, above the
Translate button.

The .HYP file, error file, and log file are written to the same directory
that contains the board file.
Close --
View .HYP File Displays the .HYP file in the HyperLynx File Editor.

This button is unavailable if the .HYP file is not created.

View .ERR File Displays the .ERR file in the HyperLynx File Editor.
View .LOG File Displays the .LOG file in the HyperLynx File Editor.
Help --
Related Topics

Translator Options Dialog Box

To access: Click Options from the Translate File Dialog Box.

Use this dialog box to edit translator options. For some PCB design systems, key information
needed to create BoardSim boards is not stored in a predictable way and you provide attribute
names or other information to indicate how it is stored. Also, some translators support partial
plane layers and copper pours, and you decide whether to include this information in the
BoardSim board.

Standard options represent settings that you should carefully review and edit.

Caution
Non-standard options represent settings that you should not set unless you are advised to
do so.

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Figure 4-2. Translator Options Dialog Box

Table 4-11. Translator Options Dialog Box Contents

Field Description
Standard options Area
• VALUE Alias The name of the attribute used to specify part values. The
name is case insensitive.

Example: value

Available for the following translators:

• Mentor Graphics Board Station RE
• Specctra DSN Translator
• Valor ODB++ Translator
• Zuken CR-3000

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Table 4-11. Translator Options Dialog Box Contents

Field Description
• Library File Property The name of the attribute used to specify the filename of
the IC model library.

Example: HYP_LIB

Available for the following translators:

• Cadence Allegro
• Mentor Graphics Board Station RE
• Device Model Property The name of the attribute used to specify IC model
names.

Examples: COMP_PART_NUMBER, HYP_DEVICE

Available for the following translators:

• Cadence Allegro
• Mentor Graphics Board Station RE
• Default capacitance units Select the default unit for capacitance, to use when no
units are provided.

Available for the following translators:

• Mentor Graphics Board Station RE
• Include partial plane Select to write partial plane areas and copper pours
areas and copper pours (polygon fills) information to the .HYP file.

Requirement: Enable this option if you plane to run

power-integrity analysis. However, even if you plan to
run only signal-integrity analysis, enabling this option
means that you can see area fills in the board viewer.

Enabling this option produces larger .HYP files and can

increase drawing times in the BoardSim board viewer.

Available for the following translators:

• Cadence Allegro
• Mentor Graphics Board Station RE
• Specctra DSN Translator
• Visula/CADStar for Windows Translator
• Zuken CR-3000
• Zuken CR-5000 Translator

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Table 4-11. Translator Options Dialog Box Contents

Field Description
• Increase details for Select to write precise clearances among metal regions,
power integrity detailed capacitor mounting information, and other
physical information about the power-distribution
network.

This option writes explicit anti-pad values to the .HYP

file and may cause the Setup Anti-Pads and Anti-
Segments Dialog Box to be unavailable.

Available for the following translators:

• Cadence Allegro
• Mentor Graphics Board Station RE
• Zuken CR-5000 Translator
• Device Name Field Select the name of the attribute used to specify IC part
names:
• Symbol
• Part_number

The .CMP file provides this information.

Available for the following translators:

• Mentor Graphics Board Station RE
Non-Standard Command- Leave this field empty. Non-standard options represent
Line Options settings that you should not set unless you are advised to
do so.

Board Station RE only: If the design contains variants,

use the -a <variant_name> option. See “Adding
Assembly Variant Names to Components” on page 233.
For an illustration of how the -a switch can affect
translation results, see “Variant Translation Examples”
on page 234.

Related Topics
“Creating BoardSim Boards” on page 215

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Chapter 5
Viewing BoardSim Boards

Use the board viewer to display the topology and components for signal nets and power-
distribution networks on the board. You can right-click in the board viewer to select a signal net
to simulate for signal integrity, display object properties, interactively assign IC models or
passive component values, change the types of objects to display, and so on.

Note
Use eDxD/eExp View to display .CCE board files exported from Expedition PCB or
CAMCAD Professional. eDxD/eExp View displays custom pad shapes more accurately
than the BoardSim board viewer. The .CCE files provide additional layers to display
manufacturing and other types of information.

Restriction: The CCE Files option is unavailable when running the 64-bit version of
HyperLynx. On Windows, use the 32-bit version of HyperLynx (which is also installed
when you install the 64 bit version) to open CAMCAD files. Select Start > All Programs
> Mentor Graphics SDD > HyperLynx <release> 32-bit > HyperLynx Simulation
Software. By contrast, Linux installations are 64-bit only or 32-bit only.

This topic contains the following:

• “Board Viewer User Interface” on page 255

• “Board Viewer Operations” on page 259
• “Board Viewer Drawing Details” on page 267

Related Topics
“View Options Dialog Box” on page 1913

“Viewing Filter Dialog Box” on page 1916

“Setup Anti-Pads and Anti-Segments Dialog Box” on page 1860

“Overlapping Anti-Pads That Isolate Metal Shapes” on page 1395

“Post-Layout Workflow” on page 49

Board Viewer User Interface

Figure 5-1 shows how the board viewer displays layout and analysis-related information.

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Figure 5-1. Example Board Viewer Contents

Requirement: The BoardSim Crosstalk option is required to display aggressor signal nets in
the board viewer.

Figure 5-2 shows how the board viewer displays a MultiBoard project and its boards,
connectors, and so on. The interconnection between two boards is drawn as a single row of
interconnections outlined by a rectangle for all connector types, such as a ribbon cable, edge
connector, and coaxial cable. When you select a signal net that spans more than one board, a
thin line runs from the board to the interconnection block before continuing to a component on
the other board.

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Figure 5-2. Example Board Viewer Contents - MultiBoard Project

Identifying Stackup Layers Used to Implement Trace

Segments and Metal Shapes
The board viewer uses a color code when drawing the constituent metal, such as trace segments,
pads, copper pours, and so on. The colors correspond to the stackup layer colors, which you can
view and change in the stackup editor.

Procedure
1. In the board viewer, note the color of the segment or pad.
2. Select Setup > Stackup > Edit. The stackup editor opens.

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3. If you have loaded a MultiBoard project into BoardSim, select the board ID in the
Design File list.
4. In the spreadsheet, click the Basic tab.
5. Look for the color you noted in step 1. The segment or pad is on the layer that has the
matching color.
6. To edit the stackup layer color, click the color cell. and then click the arrow that appears
in the color cell to open the Color dialog box.

Note
For signal or power-supply nets that you highlight for viewing, as opposed to signal nets
that you select for signal-integrity simulation, you choose whether to draw the nets with
stackup layer colors or with user-defined colors. See “Highlight Net Dialog Box” on
page 1641.

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Board Viewer Operations

This topic contains the following:

• “Summary of Board Viewer Operations” on page 259

• “Zooming and Panning” on page 261
• “Viewing All Nets Simultaneously” on page 262
• “Removing All Highlighting” on page 263
• “Displaying Power-Supply Nets” on page 263
• “Highlighting Decoupling and Bypass Capacitors” on page 263
• “Highlighting Capacitor Mounting” on page 264
• “Reviewing the Board Layout” on page 266

Summary of Board Viewer Operations

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Table 5-1 shows common board viewer operations.

Table 5-1. Summary of Board Viewer Operations

Operation Links to Details
Display the board and • “Zooming and Panning” on page 261
its contents • Show specific types of reference designators and design objects
“View Options Dialog Box” on page 1913
• Show specific signal or plane layers
“Viewing Filter Dialog Box” on page 1916
“Setting Signal or Plane Layer Visibility” on page 397
• Show the location of decoupling and bypass capacitors
“Highlighting Decoupling and Bypass Capacitors” on page 263
• Show the location of a specific component
“Find Component Dialog Box” on page 1640
• Show the electrical connectivity of decoupling capacitor mounting
“Highlighting Capacitor Mounting” on page 264
• Show anti-pads and anti-segments
“Setup Anti-Pads and Anti-Segments Dialog Box” on page 1860
“View Options Dialog Box” on page 1913
• Edit the colors of stackup layers and copper pours
“Changing Stackup Layer Colors” on page 397
• Edit the display pattern for copper pours
“Viewing Pours and Voids” on page 398
Display geometric View properties for:
properties for board • Traces
objects “Highlight Net Dialog Box” on page 1641
“Viewing All Nets Simultaneously” on page 262
• Trace segments
“Viewing Net Segment Properties” on page 337
• Vias
“Viewing Via Properties” on page 1056
• Pours and voids in power planes or metal shapes
“Viewing Filter Dialog Box” on page 1916
“Viewing Pours and Voids” on page 398
Display electrical • View field solver output for a trace segment
properties for traces “Viewing Net Segment Field-Solver Output” on page 337
• View loss versus frequency for a trace segment
“Viewing Net Segment Attenuation Over a Frequency Range” on
page 338
• View coupling regions
“Viewing Coupling Regions” on page 1239

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Table 5-1. Summary of Board Viewer Operations (cont.)

Set up SI simulation • Select nets for simulation
“Selecting Nets by Location in the Board Viewer” on page 277
• Assign IC models
“Interactively Selecting IC Models” on page 467
• Edit passive component values
“Editing Resistor - Capacitor - Inductor Values” on page 320
• Set up driver stimulus for the oscilloscope
“Setting Up Per-Net and Per-Pin Stimulus” on page 541
• Attach a spectrum analyzer probe
“Attaching Probe by Pin Location in BoardSim” on page 912
Set up PI simulation • “Setting Up Designs for Power-Integrity Simulation” on page 341
• Include anti-pads in simulation
“Setup Anti-Pads and Anti-Segments Dialog Box” on page 1860

Related Topics
“Preferences Dialog Box - Appearance Tab” on page 1800

Zooming and Panning

To help you navigate boards of practically any size and complexity, the board viewer offers
many zooming, panning, and other display adjustment features. Use zooming to enlarge or
shrink the board image. Use panning (scrolling) to move the board image across the board
viewer without changing its zoom level.
Table 5-2. Board Viewer Operations
View Operation Procedure
Fit the Board to Click Fit to Window .
the Window
Pan in Board Press <Arrow Up>, <Arrow Down>, <Arrow Left>, <Arrow Right>,
Viewer <Page Up> (coarse), or <Page Down> (coarse).

Alternative: Select View > Zoom Pan, move the pointer to the location that
you want to move to the center of the board viewer, and click.
Zoom In By a Press and hold down Shift and rotate the top of the mouse wheel away from
Fixed Increment you.

Alternative: Select View > Zoom In.

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Table 5-2. Board Viewer Operations

Zoom In to an Draw a box around the area of the board you want to enlarge to fill the board
Area Defined by a viewer. The center of the box you draw becomes the new center of the board.
Box 1. To draw a zoom box by defining two of its corners, right-click over an
empty area of the board and click Zoom Area.

Alternative: Click Zoom Area In .

2. To draw a zoom box by defining its center and one of its corners, on the
View menu, click Zoom Point.
3. Drag a box around the area in the board you want to enlarge.

Result: BoardSim enlarges the board to fill the box.

Zoom Out By a Press and hold down Shift and rotate the top of the mouse wheel toward you.
Fixed Increment
Alternative: Select View > Zoom Out.

Zoom to the Zoom to any previous zoom level in the current session by stepping through
Previous Zoom the previous zoom levels one at a time.
Level • Right-click over an empty area of the board and click Zoom Previous.

Alternative: Click Zoom Previous .

Flip the Board When the board first appears in the board viewer, BoardSim automatically
sets the board orientation. You can change the orientation manually.
1. Select View > Flip Board.
2. Do one of the following:
• To flip the board around the vertical axis, click Right.
• To flip the board around the horizontal axis, click Down.
Results:
• Board outline changes orientation.
• Component outlines appear in new positions.
• Component outlines change sides on the board. Black component
outlines become gray and gray outlines become black.
• Vias change color because you are now viewing the via pads on the
opposite side of the board.

Viewing All Nets Simultaneously

After you select a signal net for simulation, you can display all the other nets with full
brightness, just like when you first opened the board. Since the board viewer is not optimized
for displaying all nets simultaneously, you may want to consider not using this capability on
larger boards.

When you select a signal net, the board viewer automatically displays only the selected net, its
associated nets, and its aggressor nets at full brightness. This means that selecting a net also

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automatically enables the Selected net and highlighted nets option in the View Options Dialog
Box.

Procedure
Do any of the following:

• Right-click over an empty area of the board and click Disable Dimming.
• Select View > Options, in the View Options Dialog Box select None (all objects at full
brightness).
• Viewing Filter Dialog Box > Disable Dimming.

Removing All Highlighting

To remove all highlighting:

1. Select View> Highlight Net. The View Options Dialog Box opens.
2. Click Remove All.
Or

1. Select View > Options. The Highlight Net Dialog Box opens.
2. Click Remove Highlights.
3. Click OK. Highlighting is not removed until you click OK.

Displaying Power-Supply Nets

The only way to display power-supply nets in the board viewer is to highlight them with the
Highlight Net Dialog Box. If you highlight a power-supply net that is implemented with a plane
layer in the stackup (or a copper pour), the board viewer displays only the vias, pads, and any
residual segments attached to the plane. The plane itself (or poured copper) is displayed when
you choose to view it.

Related Topics
“Viewing Pours and Voids” on page 398

Highlighting Decoupling and Bypass Capacitors

You can highlight all capacitors on the board that are connected only to power-supply nets. This
includes capacitor networks containing at least one capacitor connected to two power supplies.

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An oval enclosing the capacitor pins shows the location of an individual capacitor. Since
package sizes are usually indicative of the capacitance value, the size of the ovals can give a
sense of how decoupling is organized on the board.

Restrictions:

• The Decoupling license is required to highlight decoupling and bypass capacitors in

BoardSim.
• This feature is unavailable for MultiBoard projects.

Procedure
• Select View > Highlight Decoupling Caps.

Highlighting Capacitor Mounting

You can highlight the electrical path implemented by the pads, vias, and adjacent trace
segments connected to a capacitor pin and a power-supply net. You might do this to understand
how the capacitor is mounted to the board and connected to metal areas and IC pins, especially
when the design has dense routing and many stackup layers.

Restrictions:

• You can display connectivity for one capacitor pin at a time.

• This feature is unavailable for capacitor pins connected to signal nets.

Procedure
• Right-click capacitor pin connected to power-supply net > Show Mounting
Connectivity.
Figure 5-3 on page 265 shows a blue capacitor pad located among several BGA pads. Which
BGA pad connects to the capacitor pad?

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Figure 5-3. Capacitor Mounting Before Highlighting

Figure 5-4 on page 265 shows, with a white outline and a black path line, how the BGA pad
connects to the capacitor pad.

Figure 5-4. Capacitor Mounting After Highlighting

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Reviewing the Board Layout

The board viewer is a fairly powerful and easy to use tool for reviewing your PCB layout, even
though it is primarily designed to support BoardSim simulation and analysis features. For users
with no access to the PCB design system used to lay out the board, the board viewer can be
essential.

The board viewer has the following advantages over Gerber viewers and PCB design systems:

• It knows about nets electrically and displays not only selected nets but also their
associated nets. For example, if you select a series terminated clock net, the board
viewer displays the nets on both sides of the series resistor.
See also: “Associated Nets” on page 272
• The board viewer is probably simpler to use than the PCB design system viewer, unless
you are already intimately familiar with the PCB design system viewer.
• If you have purchased the BoardSim Crosstalk option, the board viewer is a powerful
way to see graphically which nets are coupled to other nets.
Why review your PCB layout? There are many reasons, even when thinking strictly from a
high-speed design perspective. For example, if you added terminators to your design, where
were they actually placed? Very close to the component they terminate or an inch away? If you
specified a clock net as critical, how was it actually routed? In a nice, clean, short daisy chain, or
in an unnecessarily long chain with half-inch stubs to every receiver IC?

Some BoardSim users actually review every net on their board each time they get a layout back
from their CAD group or PCB service bureau.

Procedure
1. Load the board file into BoardSim.
2. Review the power supplies list and modify it if needed.
See also: “Editing Power-Supply Net Properties” on page 277
3. Select Select > Net by Name.
4. Position the Select Net by Name dialog box in a corner of the screen. If needed, click the
Sort Nets By options to change the sorting criterion for the list of nets.
5. Select the first net in the list.
Result: The selected net, its associated nets, and its coupled aggressor nets (if crosstalk
is enabled), are displayed at full brightness while the other nets are not,
6. Review the routing displayed at full brightness.
7. To select the next net, press <down arrow>.

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8. Repeat steps 6-7 until the review is complete.

Board Viewer Drawing Details

This topic describes in detail how the board viewer draws the following:

• “Board Outline” on page 267

• “Component Outlines” on page 267
• “Pads” on page 268
• “Anti-Pads” on page 268
• “Drill Holes” on page 269
• “Pins” on page 269
• “Pin Numbers” on page 269
• “Pin Names” on page 269
• “Unattached Reference Designators” on page 269

Board Outline
The board viewer attempts to display the outline of the board. The .HYP file includes an
optional keyword BOARD which is followed by a detailed description of the line segments
making up the board outline. An outline can include both linear and curved segments.

Not all .HYP-file translators provide a board outline. If the data are missing from the .HYP file,
BoardSim will create a rectangular outline big enough to encompass all of the components on
your board.

Component Outlines
Component outlines are drawn with a dashed line. Components on one side of the board are
drawn in black and components on the other board are drawn in gray. Which side, top or
bottom, is which color depends on the .HYP-file translator. If you flip the board, the component
outlines change sides on the board, and therefore changes colors.

Instead of reading outline information from the PCB design system, BoardSim constructs
component outlines using the following method:

1. As the .HYP file is loaded, BoardSim builds a list of the pins on each component that are
connected to something on the board.
2. When loading is complete, draw a perimeter around the pins that were found for each
component.

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3. Use the perimeter as the component outline.

BoardSim uses a smart algorithm to construct the component outlines. This algorithm increases
the odds that the drawn outline matches the real one in situations where some component pins
are unconnected and are not present in the .HYP file. For example, if for a DIP package several
pins are missing on one side only, BoardSim will still draw a rectangular outline.

Pads
The .HYP file supports the following pad shapes: round, rectangular, oval, and oblong. An
oblong pad is rectangular with rounded corners. Pads are drawn with their proper shapes and
actual sizes.

When you reorient a board by flipping it over, vias will change color because you are viewing
the via pads on the opposite side of the board.

Anti-Pads
An anti-pad represents the clearance between an object, such as a pad, trace, or via, and the
plane layer on which it resides. You can choose to view or hide anti-pads generated by
BoardSim. However anti-pads are always displayed when the .HYP file contains explicit anti-
pad geometry information. For example, PADS Layout can export explicit anti-pad geometry
information to a .HYP file when the Export Hatch Outlines For Pours and Plane Areas option is
selected in the Tools > BoardSim dialog box.

The board viewer renders anti-pads exactly the same as the PCB design system when the .HYP
file contains explicit anti-pad geometry information. However, if the .HYP file does not contain
explicit anti-pad geometry information, the shape and size of the anti-pads generated by
BoardSim may differ slightly compared to those rendered by the PCB design system.

If BoardSim automatically generates anti-pads, the shape of the anti-pad is based on the object
metal shape information. The clearance between the object and plane layer is the maximum of
the following values:

• 0.1 times (object width+height) of the start and end layers of the via (the maximum)
• One of the following values, ordered from highest precedence to lowest precedence:
a. Plane separation information contained in the .HYP file for the net (highest
precedence)
b. Plane separation information contained in the .HYP file for the layer
c. Plane separation information contained in the .HYP file for the whole board
d. Plane separation information set for the system (set on the BoardSim tab on the
Preferences dialog box)
e. 8 mils or 203.2 microns

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Drill Holes
The .HYP file allows each via to have an independently sized drill hole. Drill holes are
displayed as filled-in black circles.

If the .HYP file contains padstacks with no drill holes, you can instruct BoardSim to synthesize
the missing drilling holes. See “Preferences Dialog Box - BoardSim Tab” on page 1804.

Pins
The .HYP file supports a construct called pin. A pin links a component to a physical location.
For example, consider this PIN record in a .HYP file:

(PIN X=2.5500 Y=1.9000 R=C2.2)

This record indicates that component C2 has a pin connected to the board at location 2.55,1.90.

The board viewer shows pins as small black dots. Pins remain the same size on the screen
regardless of how far in or out you zoom the board viewer.

To be connected to a net, a component pin also requires a pad on the board. In rare cases, a
.HYP-file translator may fail to provide a pad, but BoardSim may still be able to establish
connectivity with its own pad synthesis.

Pin Numbers
The board viewer displays pin numbers for component pins on the selected net, its associated
nets, and crosstalk aggressor nets. The pin numbers are not visible until you zoom in until the
component appears fairly large.

Restrictions:

• The BoardSim Crosstalk license is required to display aggressor nets in the board
viewer.
• Pin number display is disabled when you display all nets simultaneously. See “Viewing
All Nets Simultaneously” on page 262.

Pin Names
Pin names for components are displayed as ToolTips when you move the pointer over a
component pin on a net.

Unattached Reference Designators

The board viewer displays a reference-designator label for every component listed in the .HYP
file DEVICES list. If a component has no outline to which to attach the label, the board viewer

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displays the label at board position X=0,Y=0. If there are multiple unattached labels, they
overwrite each other at position X=0,Y=0.

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 Chapter 6
Setting Up Boards for Signal-Integrity Simulation

When you first load a board file, verify that BoardSim identified the correct set of power-supply
nets, check stackup properties, check passive component values, assign packages for networked
resistors or capacitors, and so on.

Additional setup tasks depend on whether you plan to simulate signal integrity, power integrity,
or both at the same (co-simulation). See “Setting Up Designs for Power-Integrity Simulation”
on page 341.

This topic contains the following:

• “Selecting Nets for SI Analysis” on page 272

• “Editing Power-Supply Net Properties” on page 277
• “Editing Trace Widths in BoardSim” on page 283
• “Reasons Why You Must Select Models” on page 288
• “Comparing Model-Selection Methods” on page 288
• “Selecting Models and Values for Individual Pins” on page 295
• “Selecting Models and Values for Entire Components” on page 296
• “Interactively Editing Rs - Ls - Cs” on page 319
• “Choosing Resistor and Capacitor Packages” on page 322
• “Reporting Board and Net Properties” on page 335

Related Topics
“Creating BoardSim Boards” on page 215

“Creating and Editing Stackups” on page 353

“Select Method of Simulating Vias Dialog Box” on page 1849

“Setup Anti-Pads and Anti-Segments Dialog Box” on page 1860

“Terminating Nets” on page 935

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Selecting Nets for SI Analysis

Select nets in BoardSim to choose them for signal-integrity analysis, display them prominently
in the board viewer, or to edit properties of components on the net. When you select a net,
BoardSim also automatically selects nets connected to the selected net (associated nets).

See also: “Associated Nets” on page 272

Displaying a net and its associated nets allows you to view the complete signal-integrity
simulation problem, that is, all of the trace segments, vias, pads, and components involved in
the simulation. You can place oscilloscope probes on associated nets as well as the selected net.

Table 6-1 shows the net selection methods and how to choose which method to use:
Table 6-1. Net Selection Methods
Method When to Use
“Selecting Nets by Name” on • You know the name of the net.
page 273 • You want to select a net from a list of nets sorted by
trace length, maximum trace width, or name.
“Selecting Nets by Reference You know the name of the reference designator
Designator” on page 276 connected to the net.

Unknown or arbitrary names typically result when you

do not name a net in the schematic. Then the net gets a
computer-generated name during netlisting.
“Selecting Nets by Location in the You can see the trace segments, pins, or vias for the
Board Viewer” on page 277 net.

Associated Nets
When you select a net for analysis, BoardSim automatically selects nets connected to the
selected net by any of the following:

• Passive components, including resistors, capacitors, inductors, and ferrite beads

• IBIS differential IC models, which contain information that identifies pin pairs
• IBIS models of bus switches using [Series MOSFET] keyword that includes a pin on the
selected net
• Differential resistor Quick Terminator
• Coupling that exceeds the crosstalk threshold (requires the Crosstalk option)
• MultiBoard interconnection model that connects the selected net to a net on another
board.

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See also: “Nets are Associated by Interconnect Models” on page 751

Example: To simulate Net1, which is connected to Net2 by a series resistor, BoardSim

simulates both nets, assuming Net2 contains only receiver IC model assignments. On the other
hand, if Net2 is a power-supply net, then BoardSim does not simulate Net2 because it represents
a DC voltage, not a continuation of Net1.

BoardSim displays all nets in a group of associated nets regardless of which net you choose to
simulate. For example, if Net1 and Net2 are tied together through a series resistor, the board
viewer will show both Net1 and Net2 regardless of whether you choose to simulate Net1 or
Net2.

The Pins list on the Assign Models dialog box displays components on nets associated to the
selected net, which helps you to assign models to all pins on the nets being simulated. The Pins
list also identifies some associating mechanisms, for example, crosstalk and MultiBoard
connectors.

Related Topics
“With IBIS Differential Model - Pin Names Must Match PCB - BoardSim” on page 476

Selecting Nets by Name

Use the Select Net by Name dialog box to select the name of the net you want to simulate or
display in the board viewer.

Procedure
1. Click Select Net by Name for SI Analysis or select Select > Net by Name for SI
Analysis.
2. If a MultiBoard project is loaded into BoardSim, select the board ID in the Design File
list.
3. In the Net Name list, scroll until you see the name of the net you want to simulate.
To quickly locate a net name, filter the list by typing a search string with wildcards into
the Filter box and then clicking Apply. Use the asterisk * wildcard to match any number
of characters. Use the question mark ? wildcard to match any one character.
You can change the net sorting criterion by clicking an option in the Sort Nets By area.
See “Sorting Nets” on page 274.
If you are not sure of the net you want to select, you can select the net name to display it
immediately in the board viewer to see if it is the correct net.
Restriction: You cannot select a power-supply net for signal-integrity simulation. The
green power icon that resembles the symbol for an ideal voltage source identifies power-

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supply nets. If a net is erroneously marked as a power-supply net, you can remove it
from the power-supplies list. See “Editing Power-Supply Nets” on page 281.
4. Select the net name and click OK.
Alternative: Double-click the net name.
Result: The net is selected for signal-integrity simulation and is displayed by the board
viewer.

Sorting Nets
You can sort nets in the Select Net by Name dialog box in the following ways:

Table 6-2. Sorting Net Options in the Select Net by Name Dialog Box
Sorting criterion When to use
Name You know the names of the net you want to simulate
Length You are not sure which nets on your board are most
likely to have transmission-line problems.

The longest nets are the likeliest culprits.

Lengths are for the named net only, so the "short side"
of net pairs that are series-terminated may not appear
high in the list. But whether it is worth simulating a net
also depends on whether or not the net is timing-critical
or edge-sensitive, and whether the driver IC on the net
has a fast slew rate or not. Nets that are not timing
critical, or do not drive edge-sensitive inputs, or are
driven by slow drivers, often do not have transmission-
line problems.
Width You want to sort by the maximum width of the trace

Net Lengths
The net length displayed in the area above the list of nets represents the sum of the lengths for
all trace segments on the net, regardless of how they are connected.

However, the length does not include the lengths of associated nets. For example, if a clock net
on the PCB consists of a short net named CLK, a series terminating resistor, and a continuation
net named CLK_T, the length shown for CLK is the short length because the length of net
CLK_T is not added.

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Net Lengths Reported are Pre-Cleanup Unless Enable Net Cleaning During
Loading Option is Enabled
Many PCB-layout programs make little or no attempt to "clean up" redundant or overlapping
trace segments on a board. (Such redundancy is particularly common in designs that have been
routed at least partially by hand.) Redundancy makes no difference when a Gerber file is output,
but is not acceptable to simulation tools like BoardSim that assign electrical characteristics to all
metal structures on a net.

Accordingly, BoardSim "cleans" all nets before you analyze them, eliminating redundant metal
and combining overlapping structures when possible into fewer, large structures. This
guarantees accurate signal-integrity simulation results. The cleaning process actually occurs
when a net is first selected.

The advantage to cleaning nets only when they are selected is that the task is distributed: the
other option is to clean all nets at board-loading time, but this effort increases (usually by about
a factor of two) the time required to load a board.

However, there is one disadvantage to cleaning nets only when selected. The net lengths
displayed in the Select Net by Name dialog box are calculated at board-loading time. If net
cleaning occurs only later when nets are selected, and if some nets contain large amounts of
redundant metal, then the lengths reported in the dialog box may be too long.

To avoid this problem, you can instruct BoardSim clean all nets at board-loading time. See
“Opening BoardSim Boards” on page 54.

Viewing Net Lengths Including Associated Nets and Cleanup

Use BoardSim’s Net Statistics feature in either of the following cases:

• If you do NOT enable the "net cleaning during loading option" (see above for details),
but you want to view "post-cleanup" net lengths.
• To view net lengths including the lengths of associated nets.
The Net Statistics dialog box cleans up redundant segments on a net (if they exist) and sums into
the reported net length the lengths of all associated nets.

Viewing Clean-Up Net Lengths

To view "cleaned-up" net lengths, including the lengths of associated nets:

1. Select the net whose length you want to view.

2. Select Export > Reports > Net Statistics. The Statistics for Selected Net dialog box
opens.
3. Examine the Total Length of All Segments value.

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Related Topics
“Selecting Nets for SI Analysis” on page 272

Selecting Nets by Reference Designator

Use the Select Net by Reference Designator dialog box to select by reference designator and pin
number the net you want to simulate or display in the board viewer.

To select a net by reference designator:

1. Select Select > Net by Reference Designator for SI Analysis.

2. If you have loaded a MultiBoard project, select the board ID from the Design File list.
The board ID is appended to net names displayed in the Information area.
3. In the Reference Designators list, select the reference designator of the component
connected to the net.
Restriction: You cannot select a power-supply net for signal-integrity simulation. The
green power icon that resembles the symbol for an ideal voltage source identifies power-
supply nets. If a net is erroneously marked as a power-supply net, you can remove it
from the power-supplies list.
See also: “Editing Power-Supply Nets” on page 281
4. In the Pin Names list, select the name of the pin connected to the net, and then click OK.
Alternative: Double-click the pin name.
Result: The net is selected for signal-integrity simulation and is displayed by the board
viewer.

Net Lengths
The net length displayed in the area above the list of nets represents the sum of the lengths for
all trace segments on the net, regardless of how they are connected.

However, the length does not include the lengths of associated nets. For example, if a clock net
on the PCB consists of a short net named CLK, a series terminating resistor, and a continuation
net named CLK_T, the length shown for CLK is the short length because the length of net
CLK_T is not added.

Related Topics
“Selecting Nets for SI Analysis” on page 272

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Selecting Nets by Location in the Board Viewer

You can select from within the board viewer the net you want to simulate or display in the board
viewer.

To select a net from the board viewer:

1. Point to a trace segment, pin, or via, on the net you want to select.
When you point to a net object, its color changes and the net name appears in the status
bar near the bottom left corner of the window.
2. Right-click and click Select Net.
Result: The net is selected for signal-integrity simulation and the board viewer displays
other nets at a lesser brightness.

Related Topics
“Selecting Nets for SI Analysis” on page 272

Editing Power-Supply Net Properties

This topic describes how BoardSim uses power-supply nets and how to edit power supply
properties in BoardSim.

This topic contains the following:

• “Why Power-Supply Nets Matter” on page 277

• “How BoardSim Identifies Power-Supply Nets” on page 278
• “Undetected Power-Supply Nets” on page 281
• “Editing Power-Supply Nets” on page 281

Why Power-Supply Nets Matter

In order to simulate properly, BoardSim must know the difference between signal nets and
power-supply nets:

• Signal nets—Ordinary digital nets that carry switching signals

• Power-supply nets—Nets that are tied to a non-switching, DC voltage
The difference is important because BoardSim propagates signals along signal nets, but not
along power-supply nets. Power supplies are treated as fixed DC sources. Also, ICs can only
run off of nets identified as power supplies.

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How BoardSim Identifies Power-Supply Nets

When BoardSim loads your board, it attempts to identify power-supply nets and to infer to what
voltage each power-supply net is tied. This identification occurs by looking for nets:

• With common power-supply names, for example GND or VCC

• Connected to multiple capacitors
• With very large numbers of metal segments
BoardSim attempts to automatically identify as many power-supply nets as possible. On some
boards, the automatic identification will work perfectly; on others, you may need to make
corrections to the list of power-supply nets yourself, manually, with the power-supply editor.

This topic contains the following:

• “Identifying by Name Matching” on page 278

• “Identifying by Counting Capacitors” on page 280
• “Identifying by Counting Metal Segments” on page 280
See also: “Editing Power-Supply Net Properties” on page 277

Identifying by Name Matching

The name-matching method attempts to identify power-supply nets by their names. The
identification process includes guessing from the name to what voltage each net is likely
attached.

Automatic Net Names

Some power-supply net names are recognized and assigned an "automatic" voltage. If
BoardSim cannot guess the voltage from the name of power-supply net, it assigns 0 V.

VCC
The following net names are automatically interpreted as being a 5 V power supply:

• PWR
• POWER
• VCC
• VDD
BoardSim automatically adds any of these to its list of power-supply nets, and assigns a voltage
of 5 V. The name-matching is case-insensitive, e.g., "VCC", "vcc", and "Vcc" all match.

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If the voltage is wrong (e.g., should be 3.3 V), it can easily be changed in the power-supply
editor. Also, if any of the nets is not actually a power-supply net, it can be removed from the list
in the editor.

GND
Similarly, BoardSim interprets the following as being a 0.0 V power supply:

• GND
• GRND
• GROUND
• VSS
The list above include the most-important of the automatically assigned names. BoardSim
actually recognizes a larger, growing list of power-supply-net names that HyperLynx has seen
frequently on customer boards.

Inferred Net Names

Some power-supply net names are recognized and assigned a voltage that is based on part of the
name.

Net names with the following forms are interpreted as being power-supply nets. The assigned
voltage is the number (i.e., <number>) found in the net name:

+<number>V or +<number> or V+<number>

-<number>V or -<number> or V-<number>

<number>V or <number>

The "V" can also be lower-case.

For example, each of the following is considered a power-supply net:

+12V, v+12, -12, 12V, 12

If the voltage is wrong or if any of these is not a power-supply net, the error can be fixed in the
power-supply editor.

BoardSim places one additional requirement on nets whose names are matched by "inference":
that the net must also have at least one capacitor on it. This occasionally prevents an entire
digital bus with supply-like net names from being mistaken as a collection of power supplies,
since digital nets rarely have capacitors connected directly to them.

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Identifying by Counting Capacitors

The capacitor-counting method takes advantage of the fact that most power-supply nets are
connected to a large number of decoupling capacitors. By default, BoardSim considers any net
with three or more capacitors connected to be a power-supply net. If this identification is ever
wrong, the misidentified net can be removed from the power-supplies list using the power-
supply editor.

You can modify the power-supply identification threshold to any number of capacitors you
want.

See also: “Preferences Dialog Box - BoardSim Tab” on page 1804 (Assume net is a power
supply if... option), “Helping BoardSim Recognize Power-Supply Nets” on page 212

However, the capacitor-based algorithm has proven successful across a broad spectrum of
customer designs, and HyperLynx recommends not changing the threshold unless you know
specifically that it is causing a problem with a particular board.

Tip: The capacitor-counting method has the advantage of finding not only power-supply
nets (which typically have large numbers of decoupling capacitors connected), but also
analog nets, which, like power-supplies, should not be simulated as digital nets in
BoardSim.

Identifying by Counting Metal Segments

The metal-segment-counting method relies on the fact that nets with a very large number of
metal segments (> 20,000) are almost always power-supply nets. By default, BoardSim
considers any net with 20,000 or more segments connected to be a power-supply net. If this
identification is ever wrong, the misidentified net can be removed from the power-supplies list
using the power-supply editor.

You can modify the power-supply identification threshold to any number of metal segments you
want.

See also: “Preferences Dialog Box - Advanced Tab” on page 1792 (Segment threshold for auto
power-supply ID option), “Helping BoardSim Recognize Power-Supply Nets” on page 212

However, HyperLynx recommends not changing the threshold unless you know specifically
that it is causing a problem with a particular board.

See also: “Undetected Power-Supply Nets” on page 281

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Undetected Power-Supply Nets

BoardSim may fail to identify some of the power-supply nets on your board. When this
happens, use the power-supply editor to add the undetected nets to the power-supplies list.

See also: “Editing Power-Supply Nets” on page 281

Undetected power-supply nets can lead to some nets looking complicated and huge in the
BoardSim’s board viewer. This occurs because BoardSim displays not only the chosen net, but
also all non-power-supply nets connected to the chosen net through passive components (e.g.,
resistors and capacitors). The connected nets are called "associated nets."

See also: “Associated Nets” on page 272

Also, when you choose IC models for signal-integrity simulation, you can "run" the ICs only off
of voltages in the power-supplies list.

See also: “Assigning Power Supplies to ICs” on page 478

If a major power-supply net is undetected, nets in the board viewer will be particularly "strange"
looking. Before proceeding (especially before simulating or running the Board Wizard), use the
power-supply editor to add the undetected power-supply nets to the power-supplies list.

See also: “Editing Power-Supply Nets” on page 281

In fact, it’s a good idea to always review the power-supplies list for any board the first time you
load it into BoardSim, to ensure that no supplies are missing from the list. Failure to do may
result in very slow analysis results, as BoardSim attempts to simultaneously analyze huge sets
of nets that are erroneously tied together.

Editing Power-Supply Nets

To access: Setup > Power Supplies

Use the Edit Power-Supply Nets dialog box to edit power-supply net properties. Table 6-3
describes the spreadsheets in the dialog box.

Table 6-3. Edit Power-Supply Nets Dialog Box Spreadsheets

Spreadsheet Description
Select supply nets Select check boxes to identify each power-supply net.

When you first open the board, BoardSim automatically identifies

power-supply nets and selects their check boxes. See “How
BoardSim Identifies Power-Supply Nets” on page 278.

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Table 6-3. Edit Power-Supply Nets Dialog Box Spreadsheets (cont.)

Spreadsheet Description
Edit supply voltages Enter the voltage for each power-supply net. Voltages enclosed by
angle brackets < > indicate an automatically assigned value.

You can add/remove power-supply nets from this spreadsheet by

selecting/clearing check boxes in the Select Supply Nets
spreadsheet.
Assign supply nets to Select the power-supply net for each plane layer. This option has
plane layers the effect of flooding the stackup layer with metal and assigning it
to the power-supply net you specify. Make this assignment only
when the stackup layer really should be flooded with metal.

This spreadsheet will be empty for many designs. Usually it is

necessary to make this assignment if some portion of the power-
supply net does not have an explicit metal area defined in the board
file. That is, an entire stackup layer is somehow assumed to be
filled with metal and assigned to a power-supply net.

The spreadsheet will also be empty when the stackup contains no

plane layers. The Supply Net list contains stackup layers that
function as plane layers (AC grounds).

Use the “Usage” column in the stackup editor spreadsheet to

identify plane layers. See “Creating and Editing Stackups” on
page 353.
Settings in this dialog box are written to the BoardSim session data (.BUD) file, which is
located in the same folder as the HyperLynx executable file (bsw.exe - Windows, bsw - Linux,
UNIX). For example, C:\MentorGraphics\<release>\SDD_HOME\hyperlynx.

To edit power-supply nets:

1. Select Setup > Power Supplies.

2. If a MultiBoard project is loaded, do the following:
a. Select the board from the Design File list.
b. Select the Apply To All Instances Of Board check box to propagate the changes to
all instances of the board in the MultiBoard project.
See also: “Design File List in BoardSim” on page 494, “Apply to All Similar Boards
Check Box” on page 495
3. To filter the Select Supply Nets spreadsheet, type the filter string into the Filter box and
click Apply.

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Use the asterisk * wildcard to match any number of characters. Use the question mark ?
wildcard to match any one character.
See also: “Sorting Power-Supply Nets” on page 283
4. To add a power-supply net to the Edit Supply Voltages spreadsheet, select its check box
in the Select Supply Nets spreadsheet.
If the .HYP file contains no area shapes of type PLANE and you assign a power-supply
net to a plane layer, BoardSim assumes the plane layer is flooded with metal and uses
anti-object clearances defined in the Setup Anti-Pads & Anti-Segments dialog box. See
“Setup Anti-Pads and Anti-Segments Dialog Box” on page 1860.
5. To assign a voltage to the power-supply net, click the Voltage cell in the Edit Supply
Voltages spreadsheet and type the voltage.
Voltages can be positive or negative.
Angle brackets < > in the Voltage cell identify an automatically-assigned voltage.
6. To map a plane layer in the stackup to a power-supply net used for power-integrity
simulation, click the Supply Net cell in the Assign Supply Nets To Plane Layers
spreadsheet and select a net.
7. Click OK.
After you edit power-supply nets, the board viewer may display the selected net differently.
This occurs because the list of associated nets for the selected net changes based on the new
power-supply list. When you close the dialog box with a very large board loaded, BoardSim
may pause as it relocates associated nets.

Sorting Power-Supply Nets

Click a column header in the spreadsheet to sort the rows. Clicking the blank column header
sorts by selected check boxes.

Power-supply nets are often the widest nets on the board and sorting by width usually brings
them to the top of the list.

Net lengths are calculated by summing the lengths of all the segments on the net, regardless of
how they are connected. Net lengths do not include the lengths of associated nets to which the
named net is connected by series components, such as a series resistor.

Editing Trace Widths in BoardSim

You can perform "what if" signal-integrity simulations by editing trace widths to vary the
impedance of traces on the board.

This topic contains the following:

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• “Changing Trace Widths” on page 284

• “How to Change Trace Widths” on page 284
• “Examples of Changing Trace Widths” on page 286

Changing Trace Widths

The widths of the traces on your board play a major role (along with your board's stackup) in
determining the impedance of your board's traces—and impedance, in turn, greatly affects
signal quality and even radiated-emissions behavior. For this reason, you may sometimes want
to experimentally change the widths of certain traces on your board to see how signal integrity
is affected.

For example, suppose you have a 10-mil-wide clock net which is not incident-wave switched by
the driver IC (i.e., the driver IC can't generate a large-enough initial voltage step into the trace to
make all of the receivers on the net switch until several transmission-line reflections occur). If
the clock trace's segments were higher impedance, the initial switching step would be larger,
and you might achieve incident-wave switching. You wonder if a 6-mil trace width on the clock
net would increase the impedance enough to solve the problem.

Or, suppose you have a net with marginal signal quality, and you notice that it transitions
several times between a layer with 8-mil-wide trace segments and one with 6-mil segments.
You wonder whether the impedance discontinuities caused by the differing widths are
generating the signal problems — what if both layers had 6-mil-wide segments?

Tip: A PCB trace normally consists of many individual "segments" which, taken
together, make up the complete trace. When simulating, BoardSim treats each of these
segments individually as a separate transmission line. This means that if you have a trace
which consists of a mixture segment widths, e.g., some of the segments on the trace are 8
mils wide and some are 6 mils wide, BoardSim will correctly account for the resulting
impedance discontinuities and delay changes.

How to Change Trace Widths

BoardSim allows you to change trace widths directly, without having to go back to your PCB-
layout tool. These changes are made to your current layout, and are experimental and
temporary: when you exit BoardSim or close your board, the changes are discarded; the next
time you load your board into BoardSim, the original layout, with its original trace widths, is
restored.

To change the widths of trace segments on your board:

1. Select Edit > Trace Widths.

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2. If you have a MultiBoard project loaded, select which board or boards you want to
modify from the Traces on Boards list.
3. In the Select Trace Segments To Change area, select the net(s), stackup layer(s), and
width(s) for which you want to change the widths. (See below for more details on
making these selections.)
4. Type the new width in the Width.
5. Click Change Widths. The widths are altered immediately, and are shown in the board
viewer.
6. Click Close and resume analysis.
The changed widths are in effect until you make additional changes that override them, or until
you close and reload the board. You cannot restore your original widths except by re-loading
your board.

Choosing Which Segments to Change

The Select Trace Segments To Change area in the Change Trace Widths dialog box gives you
considerable flexibility in choosing which trace segments to alter. Each of the sub-selections
below can be set independently of the other two selections:

Choosing Which Nets

In the Traces On These NETS area, you can choose to make width changes on only a selected
net, or on all of the board's nets. If you are choosing a particular net, you can change the order in
which the nets are listed in the Selected Net combo box by selecting the desired radio button in
the Sort Nets By area.

Choosing Which Layers

In the AND On These LAYERS area, you can choose whether to change widths on only a
selected stackup layer, or on all layers. The Selected Layer combo box lists all of the layers in
the current board stackup.

Choosing a Range of Widths

In the AND With WIDTHS In This RANGE area, you can choose to limit the changes to only
trace segments in a selected range of original widths, or to all segments regardless of width. If
you choose to enter a range, you enter the minimum and maximum widths in the range.

Conditions are ANDed

Notice that the three selection criteria (nets, layers, and width range) are ANDed together. To
eliminate one of the criteria, click the All radio button in that criterion's area. For example, to
eliminate the width range, click the All Widths radio button.

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Restoring Original Widths

To restore the original trace widths used in your PCB layout, you must re-load the board file.
When you re-load, the width changes made in the previous session are discarded and the
original widths from the board file are restored.

Possible Bad Effects from Width Changes

Changing the widths of a board's traces usually does not affect the electrical validity of the
traces, but this cannot always be guaranteed. Generally, narrowing traces (i.e., making them
narrower) is usually safe; widening traces (if the board is densely routed) may cause electrical
problems.

For example, if you widen a trace too much such that it touches another trace, BoardSim may
connect the two traces together (because you've "shorted" the widened trace to the other trace).

In a given signal-integrity simulation, BoardSim only "looks" at the net you've chosen for
simulation, plus any associated nets. Therefore, it's not as dangerous to widen traces as it might
seem. Problems only arise if the widened trace touches another segment on the same net or a
segment on an associated net.

See also: “Associated Nets” on page 272

In rare cases, narrowing a trace may cause electrical problems. This could occur, for example, if
a trace connects to a pad marginally, at the edge of the trace only. Narrowing the trace could
cause the trace-to-pad connection to be opened.

Width Changes Not Reported in Design Change Summary

Trace-width changes you make are not reported in BoardSim's Design Change Summary. Also,
although changed widths are used when the Board Wizard analyzes your PCB, the changes are
not summarized in the design-change sections of the board report.

Therefore, to keep a record of the traces and layers on which you've changed widths, you must
do so manually.

Examples of Changing Trace Widths

The following sections illustrate the effects of changing trace widths for various layers and
geometries.

Changing an Entire Single Trace on All Its layers

To change the width of a single trace on all of the layers on which it's routed:

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1. In the Traces On These NETS area, select Selected Net Only, and then select the net
with the Selected Net list.
2. In the AND On These LAYERS area, click All Layers.
3. In the AND With WIDTHS In This RANGE area, select All Widths.

Changing All Traces on a Single Stackup Layer

To change the widths of all the traces on a single stackup layer:

1. In the Traces On These NETS area, select All Nets.

2. In the AND On These LAYERS area, select Selected Layer Only, and then select the
desired layer in the Selected Layer list.
3. In the AND With WIDTHS In This RANGE area, select All Widths.

Changing All 10-Mil and 8-Mil Traces to 6 Mils Wide

To change all of the 10-mil and 8-mil traces on your board to 6 mils wide:

1. In the Traces On These NETS area, select All Nets.

2. In the AND On These LAYERS area, select All Layers.
3. In the AND With WIDTHS In This RANGE area, select Selected Range, and then type
8 into the Min Width box and 10 into the Max Width box.
4. In the Width To Change To area, type 6.

Changing the Top-Layer 6-Mil Segments on Net CLK to 8 Mils

Wide
To change the top-layer, 6-mil-wide segments on a net called "CLK" to 8 mils wide:

1. In the Traces On These NETS area, select Selected Net Only, and select CLK in the
Selected Net list.
2. In the AND On These LAYERS area, select Selected Layer Only, and select layer
"Top" on the Selected Layer list.
3. In the AND With WIDTHS In This Range area, select Selected Range, and type 6 into
the Min Width box and 6 into the Max Width box.
4. In the Width To Change To area, type 8.

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Reasons Why You Must Select Models

Reasons Why You Must Select Models

You must always select the models for active components on your board for BoardSim. More
exactly, models must be selected for the driver IC on each net before the net is simulated in
detail by any of the following:

• Oscilloscope
• Spectrum analyzer
• Batch signal-integrity simulation, detailed signal-integrity simulation
• DDRx Batch-Mode Wizard
• FastEye channel analysis
• IBIS-AMI channel analysis
If you plan to simulate just a few nets, or want to quickly perform “what if” signal-integrity
simulations, you may want to assign IC models to individual pins. If you plan to test many nets,
such as during batch simulation of the entire board, you may want to assign IC models to entire
components by creating .REF or .QPL automapping files.

On the other hand, you can run batch signal-integrity simulation in "Quick Analysis" mode to
get a fast signal-integrity scan of your entire board without specifying models. Batch simulation
uses a default driver switching time when no models are present. Detailed simulations, though,
require at least a driver-IC model.

See also: “Simulating SI for Entire Boards or Multiple Nets” on page 651

Comparing Model-Selection Methods

You can assign IC models to individual pins using interactive selection or to entire components
using .REF and .QPL automapping files. This topic provides background information that can
help to define a model-selection strategy that works best for you.

This topic contains the following:

• “About Interactive and Automapping Model Assignment Methods” on page 289

• “Interactive Method Enables Experimentation” on page 290
• “An Example to Contrast Interactive and Automapping Methods” on page 291
• “Tradeoffs Between REF and QPL Automapping Files” on page 291
• “Precedence Among Model and Value Selection Methods” on page 292
• “Troubleshooting Unexpected Model Selection Results” on page 294

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About Interactive and Automapping Model Assignment

Methods
You can select IC models for individual pins or for entire components. Use the interactive
method to assign IC models to individual pins and use automapping files to assign IC models to
entire components.

If you plan to simulate a large number of nets, such as for batch signal-integrity simulation, it
may be worth the time to set up an ASCII automapping file, .REF or .QPL, since every pin on
the ICs you map in the file automatically load a model when you simulate. .REF files map ICs
to reference designators and .QPL files map ICs to component names.

On the other hand, if you plan to simulate a small set of nets, the overhead of interactively
specifying models pin-by-pin may be acceptable compared to the time required to create and
debug an automapping file. Interactive model assignments are stored in the .BUD file
(BoardSim User Data).

You can combine the interactive and automapping model assignment methods. For example,
you could create a .REF or .QPL file from which to automatically load IC models for some of
the most important ICs on your board, such as the ones connected to nets you think are most
important to simulate. Then you could select models interactively for ICs connected to other
nets you decide to also simulate. You can also mix the automapping and interactive model
selection methods in preparation for batch signal-integrity simulation.

When you choose multiple models for a pin by combining interactive and automapping
assignment methods, BoardSim uses only the model specified by the method with the highest
precedence (priority).

Example: If you mapped a pin to a fast model using a .REF file and a slow model using the
interactive method, BoardSim attaches the slow model because an interactive model assignment
has precedence over the .REF model assignment.

See also: “About REF and QPL Automapping Files” on page 297, “Precedence Among Model
and Value Selection Methods” on page 292

Characteristics Not Shared by IC-Model Selection Methods

Table 6-4 lists some characteristics unique to the interactive and automapping methods.

Table 6-4. Unique Characteristics of Model Selection Options

Characteristics Interactive Automapping
Select IC models pin-by-pin X
Select IC models component-by- X
component

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Table 6-4. Unique Characteristics of Model Selection Options (cont.)

Easier if a large set of nets is being X
simulated
Requires ASCII file to be created; smart X
editors are available in BoardSim to
help though

See also:
• “Editing REF Files” on page 300
• “QPL File Editor” on page 305
Must select models for each net that is X
being simulated for the first time
Easy if only a small set of nets are being X
simulated
Efficient when a large set of nets are X
being simulated
Cannot be used to assign SPICE or X
Touchstone models
Cannot be used to assign ferrite bead X
models
Cannot be used to assign IBIS .EBD or X
series bus switch models

EBD and IBIS Series Bus Switch Models Cannot be Assigned

Interactively
An automapping file is required to choose an .EBD or IBIS series bus switch model. An .EBD
model or series bus switch pin is permitted by the IBIS specification to loop back out to another
external pin. To ensure valid signal-integrity simulation in this case, the load at the second pin
and its reflection effects must be taken into account. To ensure proper signal-integrity
simulation in the general case, it is only safe to assign .EBD and series bus switch models on a
component-wide basis.

See also: “Enabling Series Bus Switches for Simulation” on page 493

Interactive Method Enables Experimentation

When you use the interactive method of choosing IC models, BoardSim enables you to choose
any model you wish for each pin on an IC. There is no requirement that all the pins on an IC
belong to the same model family.

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Example: Set the IC model for pin 1 to a standard-logic 74AC driver and the IC model for pin
to a complex-PLD driver. BoardSim would not complain about this these mismatched families
even though on your real board the component uses one family or the other.

This feature lets you experiment with different IC types more easily. Even though you would
usually set all of the pins on an IC to models from the same family, you have the freedom to
make exceptions in order to experiment with different driver/receiver types.

Example: After running some signal-integrity simulations, you might say, "I wonder what
would happen to those control lines if I combined the decoder and buffer into a PLD and used
the PLD’s outputs as drivers?"—and try it on one net by changing a single output pin’s model to
a PLD, without bothering to change the other pins on the IC.

With the interactive method of choosing IC models, you are only required to choose models for
the pins on the net you are currently simulating. For example, if an IC connects to only one net
that you are interested in simulating, you never need to choose a model for more than the one IC
pin that drives the interesting net.

If there is no exact model for a pin you are trying to simulate, you can easily create one. See
“How to Create a Custom IC Model” on page 523.

An Example to Contrast Interactive and Automapping

Methods
Interactively, you choose IC models pin-by-pin, for each net you simulate or set up for batch
signal-integrity simulation. For example, if you simulate net FOO, and in the process choose IC
model 74AC11XX:GATE for pin 1 of component U1; then simulate net FOO2, which is
connected to pin 2 of U1, you must still choose a model for pin 2: the choice of model
74AC11XX:GATE for pin 1 applies only to that pin, not to the whole component.

By contrast, when you use an automapping file, you choose models component-wide. For
example, when you map U1 to model 74AC11XX:GATE; then simulate net FOO which is
connected to pin 1 of U1, the 74AC11XX:GATE model is automatically loaded for pin 1; if you
simulate FOO2 connected to pin 2 of U1, the model is also loaded for pin 2: the choice of
74AC11XX:GATE applies to the entire U1 component. Because 74AC11XX:GATE model is
formatted as a .MOD type, the same model is assigned to all pins on U1.

See also: “The MOD - Databook - Format” on page 509, “IC-Model Formats” on page 507

Tradeoffs Between REF and QPL Automapping Files

The .REF file maps models to reference designators, must be stored in the <design> folder, is
required to assign .EBD models, and is required to back annotate model changes to your PCB
design system, that is, an ECO—engineering change order. See “About Design Folder
Locations” on page 1391.

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The .QPL file maps models to component part names, can be stored in any directory your
computer can access, and more than one .QPL file may be used at the same time, such as a
company-standard .QPL file and a project-specific .QPL file.

Table 6-5 lists some characteristics unique to the .REF and .QPL files.
Table 6-5. Unique Characteristics of .REF and .QPL Files
Characteristics .REF .QPL
Models are mapped to a reference designator X
Can specify resistor and capacitor values X X
Models are mapped to a component part name X
Must be stored in board file directory X
Can be stored in any directory your computer can X
access
Can be used with ECO (back-annotation) X
Can be used in LineSim X
More than one file of the same automapping file type X
can be used at a time (e.g., "company_standard.qpl" vs.
"local project.qpl")

Precedence Among Model and Value Selection Methods

IC model selection precedence is a potential source of confusion when debugging a .REF or
.QPL file. If you plan to create .REF or .QPL files large enough to require any serious amount of
debugging, please read this section.

See also: “Troubleshooting Unexpected Model Selection Results” on page 294

When you assign different models or values to a pin, BoardSim attaches the model or value
assigned by the method with the highest precedence (that is, priority). Table 6-6 shows the
precedence among the model assignment methods and Table 6-7 shows the precedence among
the value assignment methods.

Note
Model assignments have higher precedence than value assignments. That means that any
model assignment method in Table 6-6 has higher precedence than any value assignment
method in Table 6-7.

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Table 6-6. Precedence Among Model Assignment Methods

Precedence Model Assignment Comment
(priority) Method
Highest .REF file's .EBD models Unlike non-.EBD models, an .EBD model assignment
made by the .REF file has the highest precedence.
Interactive model In memory and not yet saved to a .BUD file
.BUD file model A saved interactive selection
.REF file's non-.EBD Unlike .EBD models, a non-.EBD model assignment
models made by the .REF file does not have the highest
precedence.
Lowest .QPL file model You set the precedence among two or more .QPL files.
See “Set Directories Dialog Box” on page 1854.

Table 6-7. Precedence Among Value Assignment Methods

Precedence Model Assignment Comment
(priority) Method
Highest Interactive value In memory and not yet saved to a .BUD file
.BUD file value A saved interactive selection
.REF file value --
Lowest .QPL file value You set the precedence among two or more .QPL files.
See “Set Directories Dialog Box” on page 1854.

For example if you mapped a pin to a "fast" model using a .QPL file and a "slow" model using
the interactive method, BoardSim will attach the "slow" model because an interactive model
assignment has precedence and overrides the .QPL model assignment.

Models specified in an automapping file have lower precedence than models specified
interactively in the current session or a previously saved session (.BUD file). This allows you to
override, pin-by-pin, any models specified in a .REF or .QPL file by interactively re-choosing
them with BoardSim’s user interface; any such overrides are stored in the session file (.BUD)
when you close your board or BoardSim, and again take precedence the next time you load your
board.

Related Topics
“Selecting Models and Values for Individual Pins” on page 295

“Selecting Models and Values for Entire Components” on page 296

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“Troubleshooting Unexpected Model Selection Results” on page 294

“Reasons Why You Must Select Models” on page 288

“Supported SI Models and Simulators” on page 1264

Troubleshooting Unexpected Model Selection Results

If the expected model name does not appear in the Assign Models dialog box for a pin on the
selected net, you may need to perform some investigation to pinpoint the origin of the error. The
following topics offer some possible origins of a model selection error:

• “Precedence Error” on page 294

• “REF or QPL File Syntax Error” on page 294
• “Invalid REF or QPL Model Mapping” on page 295
• “QPL Automapping has Been Disabled” on page 295
• “QPL File or Directory Name Error” on page 295
See also: “Cannot Interactively Remove Automapping Assignments” on page 483

Precedence Error
More than one method has selected a model for the pin. Only the method with the highest
precedence is used. For example, interactive model selections have precedence over .REF and
.QPL file model selections. Another example is where multiple .QPL files have been specified,
but appear in the wrong order in the Set Directories dialog box.

The Assign Models dialog box identifies when IC model assignments are made by .REF and
.QPL files. The Pins list displays an R next to the driver or receiver symbol when the .REF file
assigns the model. Similarly, a Q is displayed when the .QPL file assigns the model.

See also: “Precedence Among Model and Value Selection Methods” on page 292, “Set
Directories Dialog Box” on page 1854

REF or QPL File Syntax Error

A line in a .REF or .QPL file used to select a model is ignored when it contains a syntax error.
Worse, for .REF files only, all the following lines in the file are ignored too.

See also: “Debugging Errors in REF and QPL Files” on page 316

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Invalid REF or QPL Model Mapping

While a line in a .REF or .QPL file may be syntactically correct, it may point to libraries or
components/models that do not exist.

See also: “Debugging Errors in REF and QPL Files” on page 316

QPL Automapping has Been Disabled

If a .QPL file specifies the desired model selection, it is possible that BoardSim has been
instructed not to use .QPL files for automapping.

See also: “Temporarily Disabling REF and QPL Files” on page 319

QPL File or Directory Name Error

If a .QPL file specifies the desired model selection, it is possible the wrong file or directory
name has been entered into the Set Directories dialog box.

See also: “Set Directories Dialog Box” on page 1854

Selecting Models and Values for Individual Pins

Use the Assign Models dialog box to interactively select IC and ferrite bead models, and to edit
resistor and capacitor values. This dialog box also displays connectivity among bus switch pins.

This topic contains the following:

• “Interactively Selecting IC Models” on page 467

• “Interactively Editing Rs - Ls - Cs” on page 319
• “About Quick Terminators” on page 935
• “Selecting and Creating Ferrite-Bead Models” on page 526
• “Setting IC Buffer Direction-State” on page 477
• “Assigning Power Supplies to ICs” on page 478
• “Copying Models” on page 480
• “Removing Models” on page 483
• “Choosing Resistor and Capacitor Packages” on page 322
• “Board Viewer Drawing Details” on page 267

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Related Topics
“About the Assign Models Dialog Box” on page 485

“Comparing Model-Selection Methods” on page 288

Selecting Models and Values for Entire

Components
Use .REF and .QPL automapping files to assign, or map, models or values to all the eligible pins
on a component with a specific reference designator or part type. A mapping in a .REF file
assigns a model or value to pins on a component with a specific reference designator. A
mapping in a .QPL file assigns a model or value to pins on all components with a specific part
name, regardless of its reference designator.

Automapping files provide an efficient method to assign models and values to many
components on the board, which is useful when running detailed batch signal-integrity
simulation on many or all nets on the board.

You create and edit .REF and .QPL files with the REF- and QPL-File Editors, which provide a
fill-in-the-blank interface and create files without syntax errors.

Restriction: The REF-File Editor does not support decoupling capacitor models.

This topic contains the following:

• “About REF and QPL Automapping Files” on page 297

• “Editing REF Files” on page 300
• “QPL File Editor” on page 305
• “Format of REF and QPL Files” on page 308
• “Debugging Errors in REF and QPL Files” on page 316
• “Temporarily Disabling REF and QPL Files” on page 319
Restrictions:

• SPICE, Touchstone, and ferrite-bead models must be assigned interactively.

• LineSim does not support .QPL files because schematics do not contain part name
information.

Related Topics
“Comparing Model-Selection Methods” on page 288

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“Simulating SI for Entire Boards or Multiple Nets” on page 651

“Importing Model Assignments from CES to REF Files” on page 304

About REF and QPL Automapping Files

Before you start using automapping files, you may want to familiarize yourself with the details
of how they work.

This topic contains the following:

• “How Automapping Works” on page 297

• “Default Buffer Direction of Pins Selected by Automapping Files” on page 298
• “Using Multiple IC Model-Assignment Methods” on page 298
• “Creating Automapping Files” on page 299
• “Locations and Names of Automapping Files” on page 299

How Automapping Works

Automapping is activated when a net is selected interactively or by batch signal-integrity
simulation. If any of the components on the net are listed in the .REF or .QPL file, the models or
values for those components are automatically loaded.

Automapping is refreshed every time you select a net, start signal-integrity simulation,
interactively delete a model on the selected net, edit the .REF or .QPL file, or reload the board.
You do not have to reload the design for an updated automapping file to take effect.

ICs
When you map an IC model with one signal pin, such as a .MOD model, that model signal pin is
assigned to all signal pins on the component.

When you map an IC model with multiple pins, such as an IBIS model, signal pins in the model
are assigned to component pins with the same signal name.

If the automapping file maps models to all ICs on the net, you do not need to make any
interactive IC model assignments before running signal-integrity simulations, but you may need
to set the buffer direction on bidirectional or driver pins.

See also: “Setting IC Buffer Direction-State” on page 477

Restriction: SPICE, Touchstone, and ferrite-bead models must be assigned interactively.

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Resistors and Capacitors

If the board file contains correct values for all the resistors and capacitors, you do not have to
specify resistor and capacitor values in .REF or .QPL files. However you can override resistor
and capacitor values in the board file by specifying values for the components in .REF or .QPL
files, or by assigning values interactively. You can also use automapping files to assign a
package model to resistors or capacitors contained in network packages.

For schematics, it is probably not efficient to use model automapping files to assign values to
resistors and capacitors.

Default Buffer Direction of Pins Selected by Automapping Files

When the IC model for a pin is assigned by an automapping file, as much information as
possible about the model is set automatically. However you may need to manually set the buffer
direction for the pin.

Table 6-8 provides the default buffer direction, based on the model format and model direction
of the pin.
Table 6-8. Default Buffer Direction of Pins Selected by Automapping
Model Format Model Direction Default Buffer Direction
.IBS, .PML Output Driver; no need to change manually
.IBS, .PML Input Receiver; no need to change manually
.IBS, .PML Bi-directional Receiver; may need to change manually to driver
.EBD Any An .EBD model pin takes on the characteristics
of the .IBS model pin(s) that it points to; if the
.IBS model pin(s) creates a bi-directional signal,
you may need to change manually to driver
.MOD Any Receiver; may need to change manually to driver

.MOD models do not contain information about

pin directionality.

For driver pins that are set by automapping files as receivers, you must manually set them to the
driver buffer direction.

See also: “Setting IC Buffer Direction-State” on page 477

Using Multiple IC Model-Assignment Methods

You can use more than one IC model-assignment method at the same time. For example you
can use a .REF file to assign a model to a reference designator and then interactively assign
models on a per-pin basis to override the REF file assignments.

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You can use more than one .QPL file for the board. When different models are assigned to a pin,
due to multiple .QPL files, BoardSim attaches the model from the .QPL file with the highest
precedence. For example, one .QPL file might represent the models available on a company-
wide basis and another .QPL file might represent the models available to a specific project.

See also: “Precedence Among Model and Value Selection Methods” on page 292, “Set
Directories Dialog Box” on page 1854

Creating Automapping Files

.REF and .QPL files are formatted in ASCII and you can create or edit them with a text editor.
However the REF- and QPL-File Editors provide convenient ways to create automapping files
and have the following advantages over text editors:

• You do not have to learn the syntax of .REF or .QPL files

• You will not create syntax errors
• You can use the REF-File Editor to find and select library and component/model names,
rather than having to remember them and enter them
See also: “Editing REF Files” on page 300, “QPL File Editor” on page 305

Locations and Names of Automapping Files

.REF files have the following location and name requirements:

• Store .REF files in the same folder as the HYP/FFS/TLN file

• Name .REF files in form <design_file_name>.REF
where <design_file_name> is the name of the HYP/FFS/TLN file
Example: The .REF file for demo.hyp is named demo.ref and located in the same folder
as demo.hyp
.QPL files have the following location and name requirements:

• Store .QPL files anywhere on the computer or network

• Name .QPL files in form <alpha_numeric>.QPL
Example: The .QPL file for demo.hyp can be named foo.qpl and located on the
network.
See also: “Set Directories Dialog Box” on page 1854

Related Topics
“Selecting Models and Values for Entire Components” on page 296

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Editing REF Files

Use the REF-File Editor to create or edit .REF automapping files, which are used to assign
models and values to components with specific reference designators.

This topic contains the following:

• “About the REF-File Editor User Interface” on page 300

• “Selecting REF File Spreadsheet Rows” on page 301
• “Editing a REF File” on page 301
• “Editing Composite REF Files for MultiBoard Projects” on page 303
• “About Part Names in BoardSim” on page 303
• “Importing Model Assignments from CES to REF Files” on page 304
Requirement: SPICE, Touchstone, and ferrite bead models must be assigned interactively to a
pin.

Related Topics
“Selecting Models and Values for Entire Components” on page 296

About the REF-File Editor User Interface

The editor contains the following main areas:

Design’s parts list—Where you select the reference designator to receive the model or value
assignment.

The left-most column indicates whether an automapping file has assigned a model or value to
the reference designator. A checkmark followed by an R or Q means the .REF or .QPL file has
assigned a model or value.

You can filter the spreadsheet with any of the following methods:

• Click a column header to sort the rows

• Type a string in the filter box and click Apply. The filter box supports the asterisk *
(substitute any number of characters) and question mark ? (substitute one character)
wildcard characters.
• Select or clear the check boxes below the filter box for more filtering options.
Model/value to insert—Where you specify a model or value for a reference designator. The
contents of this area depends on the component type you select in the spreadsheet in the
Design’s Parts List area.

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REF-file model assignment—.REF file contents.

Finding Text in the Assignment Spreadsheet

To help find text in .REF files with many rows, you can search for text located in specific
columns in the spreadsheet in the REF-File Model Assignment area.

To find text in the assignment spreadsheet:

1. Select Search > Find.

2. Type the text into the box, click the column to search, and then click OK.
Restriction: The search is case sensitive.

Selecting REF File Spreadsheet Rows

You can select rows in the spreadsheet by doing the following:

• To select one row, click anywhere in the row.

• To select multiple adjacent rows, drag over the row headers.
• To select any additional row, press Ctrl+Click over the row header.

Filtering REF File Reference Designator Spreadsheets

Large designs contain many reference designators. To make finding and selecting individual
reference designators easier, you can display a subset of all the reference designators in the
design.

To filter the REF file reference designator spreadsheet, do any of the following:

• Type the filter value and click Apply.

The filter box supports the asterisk * (substitute any number of characters) and question
mark ? (substitute one character) wildcard characters.
• Select the Show only parts without models check box to hide reference designators
with model assignments (ICs) or values (passive components).
• Select the Show ICs check box to display reference designators for ICs.
• Select the Show passive components check box to display reference designators for
resistors and capacitors.

Editing a REF File

To edit a .REF file:

1. Load the board or schematic.

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You must open the board or schematic because the REF-File Editor needs to know
which reference designators are present in the design.
See also: “Editing Composite REF Files for MultiBoard Projects” on page 303
2. Select Models > Assign Models/Values by Reference Designator. The REF-File
Editor opens.
You can also open the REF-File Editor from the IBIS Models page in the DDRx batch
simulation wizard. See “DDRx Wizard - IBIS Models Page” on page 863.
3. To import IC model assignments from Constraint Editor System® (CES), click Import
from CES.
See also: “Importing Model Assignments from CES to REF Files” on page 304
Restriction: The Import from CES button is unavailable when a LineSim schematic or
MultiBoard project is loaded.
4. In the Design’s Part List area, select spreadsheet rows to identify the reference
designators to receive the model or value assignment.
See also: “Selecting REF File Spreadsheet Rows” on page 301, “Filtering REF File
Reference Designator Spreadsheets” on page 301
5. To assign a model or value to the selected reference designator(s), do one of the
following in the Model/Value To Insert area:
• To assign an IC model, select a library, select a component in the library, and then
click Assign Model.
To search for a model, click Find Model.
• To assign a value to a discrete (two pin) resistor or capacitor, click Discrete, type the
value in the box, and then click Assign Model.
See also: “Units for Resistor and Capacitor Values” on page 311
• To assign a value to a resistor or capacitor package (network of resistors or
capacitors), click Package / network, select the package from the list, type values in
the boxes, and then click Assign Model.
See also: “The Connectivity Picture” on page 330
Restriction: LineSim does not support resistor and capacitor packages.
6. To edit an assignment, double-click a row in the spreadsheet in the REF-File Model
Assignment area and repeat step 5.
Press Ctrl+Z to undo an edit.
7. To remove assignments, select one or more rows in the assignment spreadsheet and
click Remove or press <Delete>.

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See also: “Selecting REF File Spreadsheet Rows” on page 301

8. To copy the contents of the assignment spreadsheet to the Windows clipboard, click
Copy to Clip. This capability enables you to share assignment information with other
people.
9. File > Save.
10. File > Exit.

Caution
While you can save a .REF file to a different file name (using File > Save As), only
<design_file_name>.ref works with a board or schematic named
<design_file_name>.[hyp, ffs, tln].

Editing Composite REF Files for MultiBoard Projects

When you load the MultiBoard project, BoardSim automatically reads in the .REF file for the
individual board and then creates an all-new composite .REF file that applies to the entire
MultiBoard project.

If you edit the composite .REF file for the MultiBoard project, the board ID suffix (such as
_B00) in the RefDes column of the lower spreadsheet indicates on which board the reference
designator is located. When you close the MultiBoard project, the composite .REF file is split
into individual .REF files for the individual boards.

Edit the .REF file for an individual board by closing the MultiBoard project, loading the board,
and then editing the .REF file.

About Part Names in BoardSim

The part name data displayed by the upper-left spreadsheet is taken from the NAME= fields in
the DEVICE section of the .HYP file. The NAME field is intended to allow PCB-layout
translators to record whatever information exists in the layout database about the name of a part.

The part name is displayed only to help you identify (or remember) which device a particular
reference designator refers to. BoardSim does not use the Part Name data in the .HYP file when
mapping reference designators on your board to models in a .REF file.

Related Topics
“Selecting Models and Values for Entire Components” on page 296

“Adding a User Package Definition” on page 332

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Importing Model Assignments from CES to REF Files

Use the Import Model Assignments from CES dialog box to import component-wide IBIS .IBS
and .EBD IC/module model assignments from a CES project and write them to .REF
automapping files.

Restrictions
• The capability to import model assignments from CES into the REF file is unavailable
when a LineSim schematic or MultiBoard project is loaded. CES does not define
constraints for multiple-board projects.
• You cannot import the values of discrete Rs, Ls, and Cs.

Procedure
1. Select Models > Assign Models/Values by Reference Designator (.REF File) to open
the REF-File Editor.
2. In the REF-File Editor, on the menu bar, click Import from CES. The Import Model
Assignments from CES dialog box opens.
Restriction: The Import from CES button is unavailable when a LineSim schematic or
MultiBoard project is loaded.
3. Open the CES project file by doing any of the following:
• Click Browse, navigate to the CES project file (.PRJ), and click Open.
• Select a previously-opened CES project by selecting it from the list.
• Type the path to the CES project file (.PRJ).
4. In the Flow Type area, click one of the following:
• Schematic—Import data from the schematic copy of the design database (iCDB).
• Layout—Import data from the layout copy of the design database (iCDB).
5. Select the design name from the Design list. The CES project file (.PRJ) provides the set
of available design names.
6. Click OK.

Related Topics
“Editing a REF File” on page 301

“Importing Constraints from CES to BoardSim” on page 1177

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Components Without Model Assignment Dialog Box

To access: This dialog box opens automatically, if needed.

Use the Components Without Model Assignment dialog box to display the reference
designators of components in BoardSim that failed to receive values from CES.

BoardSim components can fail to receive values from CES when reference designators in the
BoardSim board do not have corresponding reference designators in the CES project. This
might happen if you loaded the wrong CES project or BoardSim board, or if there are some
minor reference-designator mismatches.

Related Topics
“Importing Model Assignments from CES to REF Files” on page 304

QPL File Editor

To access: Select Models > Assign Models/Values by Part Name
One of the following occurs, depending on the contents of the BoardSim Qualified-Parts-List
File(s) (QPL) box in the Set Directories dialog box (Options > Directories):

• If the box contains no files, the editor starts with a new file. After you add rows to the
file and click OK, the editor prompts you to specify the name of the file.
• If the box contains only one file, the editor automatically opens it.
• If the box contains multiple files, the Select QPL-file dialog box opens, which enables
you to select a file to edit or create a new file.
To edit a different file or a new file, select File > Open or File > New.

Description
Use the QPL-File Editor to create or edit .QPL automapping files, which are used to assign
models and values to components with specific part names.

Requirement: SPICE, Touchstone, and ferrite bead models must be assigned interactively to a
pin.

Restriction: LineSim does not support .QPL files because schematics do not contain part name
information.

Note
If you create a new QPL file, make sure to add the path of new .QPL file to the BoardSim
Qualified-Parts-List File(s) field in the Set Directories Dialog Box.

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Table 6-9. QPL-File Editor Contents

Field Description
Part Type Info area Use this section to specify part type information
Part type Select the component type to assign a model to. The
following options are available:
• IC
• Resistor
• Capacitor
• Decoupling Capacitor
Part name Type the part name.
Description Type a brief description of the component or a general
comment. Do not use commas because they are used as
field delimiters. Comments can contain only printable
characters. Comments can be up to 80 characters long.
Model/value to insert Specify a model or value for a part. The contents of this
area area depends on the Part Type list item you select in the
Part Type Info area.
Part type = IC To assign an IC model:
1. Select a library.
2. Select a component in the library.
3. Click Assign Model.
Tip: To search for a model, click Find Model.
Part type = • To assign a value to a discrete (two pin) resistor or
Resistor or capacitor, click Discrete, type the value in the box, and
Capacitor click Assign Model.

See also: “Units for Resistor and Capacitor Values” on

page 311

• To assign a value to a resistor or capacitor package

(network of resistors or capacitors), click Package /
network, select the package from the list, type values in
the boxes, and click Assign Model.

See also: “The Connectivity Picture” on page 330

Restriction: LineSim does not support resistor and

capacitor packages.

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Table 6-9. QPL-File Editor Contents

Field Description
Part type = 1. Enter a Part name in the Part type info area.
Decoupling 2. Select the type of model to assign:
Capacitor • Simple C-L-R — Enter values for capacitance, ESR
(equivalent series resistance), and ESL (equivalent
series inductance).

If you know the exact amount of ESL, select ESL by

value and enter the value.

If you do not know the exact value for ESL, select

ESL by capacitor size and select your packaging
from the menu or select <Custom> and enter the
Width and Length of your packaging. HyperLynx
automatically computes the ESL based on these
dimensions.
• Library — Select a library and a model.
Use the Assign / Edit Capacitor Model Dialog Box to
create decoupling-capacitor libraries.
• SPICE — Select a library and a device, and then
assign capacitor pin names (numbers) to model node
names.
• Touchstone — Select a library (but not a device) and
assign capacitor pin names (numbers) to model port
index numbers.
3. Select Includes mounting inductance only if the
decoupling capacitor model includes the effects of the
via and its connectivity to the capacitor package. This
situation happens when the vendor did not de-embed the
capacitor model from how the capacitor package was
mounted in the test fixture.
4. Click Assign Model.

Note: If you assign a model by entering the C-L-R

values, the values do not display in the Value fields of
the QPL-file model assignment section, but they are
saved to the QPL file in the order you enter them,
Capacitance, ESR, ESL. To view the values, select a
Part Name and look in the Model/value to insert section
of the QPL file Editor or open the QPL file in a text
editor.

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Table 6-9. QPL-File Editor Contents

Field Description
QPL-file model Displays the contents of the .QPL file.
assignment area • To sort spreadsheet rows, click a column header.
• To edit an assignment, double-click a row in the lower
spreadsheet. Press Ctrl+Z to undo an edit.

See also: “Selecting QPL File Spreadsheet Rows” on

page 308 and “Finding Text in the Assignment
Spreadsheet” on page 308

Selecting QPL File Spreadsheet Rows

You can select rows in the spreadsheet by doing the following:

• To select one row, click anywhere in the row.

• To select multiple adjacent rows, drag over the row headers.
• To select any additional row, press Ctrl+Click over the row header.

Finding Text in the Assignment Spreadsheet

To help find text in .QPL files with many rows, you can search for text located in specific
columns in the spreadsheet in the QPL-File Model Assignment area.

To find text in the assignment spreadsheet:

1. Select Search > Find.

2. Type the text into the box, click the column to search, and then click OK.
Restriction: The search is case sensitive.

Related Topics
“Selecting Models and Values for Entire Components” on page 296

“Adding a User Package Definition” on page 332

Format of REF and QPL Files

You do not have to learn the syntax of .REF and .QPL files if you create them with the REF- or
QPL-File Editors. However the syntax is provided in the following sections. If your company
already has qualified parts list files in a non-.QPL format, knowledge of the syntax can help you
to convert them.

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This topic contains the following:

• “Example REF File” on page 309

• “Example QPL File” on page 310
• “Formatting Shared by REF and QPL Files” on page 311
• “Units for Resistor and Capacitor Values” on page 311
• “Formatting Unique to REF Files” on page 312
• “Formatting Unique to QPL Files” on page 313

Example REF File

The .REF file format is very simple, as illustrated in the following examples:

IC assignments

U1, 701V.IBS, CGS701V

U2, MEMS.EBD, SDRAM512
U7, 74AC.PML, 74AC161_SOIC
U9, GENERIC.MOD, 74HCTXX:GATE-2

Resistor assignments

R9, 69
RP1, 1000, , RES-SIP6-SERIES-1

Capacitor assignments

C9, 81pF
C23, 33uF, , CAP-SIP14-PULLUP-1

This example .REF file works with the demo.hyp board and specifies the following:

• U1 is an IC modeled as a CGS701V component from the .IBS library file 701V.IBS

• U2 is an IC modeled as an SDRAM512 path description from the .EBD library file
MEMS.EBD
• U7 is an IC modeled as a 74AC161_SOIC component from the .PML library file
74AC.PML
• U9 is an IC modeled as 74HCTXX:GATE-2 component from the .MOD library file
GENERIC.MOD
• R9 is a 69 Ohm resistor
• RP1 is a resistor package modeled with the RES-SIP6-SERIES-1 component from the
BSW.PAK package library, with a 1000 ohm value

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• C9 is an 81pF discrete capacitor

• C23 is a capacitor package modeled with the CAP-SIP14-PULLUP-1 component from
the BSW.PAK package library, with a 33uF value

Example QPL File

The .QPL file format is very simple, as illustrated in the following examples:

IC assignments

IC, CLOCK-701V, "National CGS701V", 701V.IBS, CGS701V

IC, RAM-512, "MemWell SDRAM512", MEMS.EBD, SDRAM512
IC, 74AC161S, "HyperLynx 74AC", 74AC.PML, 74AC161_SOIC
IC, 74HCT99, "LineSim Model", GENERIC.MOD, 74HCTXX:GATE-2

Resistor assignments

R, R-1K, "", 1000

R, RPACK-1K, "", 1000, , RES-SIP6-SERIES-1

Decoupling-capacitor assignments

DECAP, C123, “”, RLC, 10U, 5M, no

DECAP, C124, “”, RLC, 10U, 5M, 3P, no
DECAP, C125, “”, RLC, 10U, 5M, 0.032IN, 0.063IN, 0.035IN, no
DECAP, C126, “”, LIB, DECAP.LIB, 10UF

This example .QPL file specifies the following:

• CLOCK-701V is an IC modeled as a CGS701V component from the .IBS library file

701V.IBS
• RAM-512 is an IC modeled as a SDRAM512 path description from the .EBD library file
MEMS.EBD
• 74AC161S is an IC modeled as a 74AC161_SOIC component from the .PML library
file 74AC.PML
• 74HCT99 is an IC modeled as a 74HCTXX:GATE-2 component from the .MOD library
file GENERIC.MOD
• R-1K is a 1000 ohm resistor
• RPACK-1K is a resistor package modeled as RES-SIP6-SERIES-1 component from the
BSW.PAK package library, with a 1000 ohm value
• C123 is a decoupling capacitor with a nominal value of 10 uF, ESR of 5 milliohms, and
an automatically-calculated ESL value based on a capacitor package size that is also
automatically calculated. The ESL value does not account for mounting inductance.

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• C124 is a decoupling capacitor with a nominal value of 10 uF, ESR of 5 milliohms, and
ESL of 3 picoHenries. The ESL value does not account for mounting inductance.
• C125 is a decoupling capacitor with a nominal value of 10 uF, ESR of 5 milliohms, and
package dimensions of width = 0.032 inch, length = 0.063 inch, and height = 0.35 inch.
The ESL is automatically calculated from the capacitor package dimensions. The ESL
value does not account for mounting inductance.
• C126 is a decoupling capacitor with values defined by the 10UF model in the
DECAP.LIB library file. The ESL value comes from the model in the library.

Formatting Shared by REF and QPL Files

• Automapping files are ASCII files and cannot contain binary characters
• Automapping files are case-insensitive, except when the computer is running under
Solaris
• Comment lines are not supported. While the REF- and QPL-file editors insert comments
at the top of the automapping files, any comments you manually add are not preserved.
• Each model record must be on a single line, with fields separated by commas
• Any kind of white space between fields is allowed
• Library files are specified with a name excluding the file path. The path is assumed to be
one of the values specified in the Model-Library File Path(s) box in the Set Directories
dialog box.
See also: “Set Directories Dialog Box” on page 1854
• Automapping files are comma delimited, which means the parameters on each line are
separated from one another by comma characters. Many other software packages can
write data out in this format. This means that if you have bill-of-material data about the
components on your board in another program, such as a database program, you may be
able to create a template for the .REF or .QPL file by writing that data out in comma-
delimited form.
Examples of other programs in which you might have your component data, and which could be
capable of writing it out in comma-delimited form: a spreadsheet application such as Microsoft
Excel, a database program such as Microsoft Access or an Oracle application, and PCB-layout
tools with flexible report-generating capabilities.

Units for Resistor and Capacitor Values

Units for resistor and capacitor values can be specified in either of two ways:

• By an exponent of form exxx or Exxx, where xxx is any integer value, positive or
negative. For example, R1, 1e3.

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• By any of the alphabetic suffixes in Table 6-10.

Table 6-10. Units for Resistor and Capacitor Values in .REF and .QPL Files
Suffix Name Scaling Factor
M mega 1,000,000x
K or k kilo 1,000x
m milli 0.001x
u or U micro 1e-6x
n or N nano 1e-9x
p or P pico 1e-12x

Formatting Unique to REF Files

Rules in this section apply only to .REF files. Square brackets [] enclose optional fields.

• .MOD IC models—Name of the model that applies to the entire IC component. The
model name must be present in the specified library file.
To specify a .MOD IC model, use a line of form:
<reference_designator>, <library.MOD>, <model_name>
• .IBS, .EBD, and .PML models—Name of the component. The component name must
match a component described in the specified library file.
To specify an .IBS IC model, use a line of form:
<reference_designator>, <library.IBS>, <component_name>
To specify an .EBD model, use a line of form:
<reference_designator>, <library.EBD>, <board_description>
To specify a .PML IC model, use a line of form:
<reference_designator>, <library.PML>, <component_name>
• Resistors—A resistor-value line can contain one or two values, depending on whether
the resistor is a single component (discrete or a single-valued pull-up or pull-down
network) or a pull-up/pull-down network.
To specify a resistor value for a discrete resistor or for a network-package resistor with a
single value, such as a pull-up resistor, use a line of form:
<reference_designator>, <value>
To specify a resistor value for a network-package resistor with two values, such as used
for pullup and pulldown resistors, use a line of form:

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<reference_designator>, <value1> [, [ <value2>] [, <package_name>]]

where <value1> maps to the common pin in the resistor package with the lower pin
number.
Example: If pin 5 represents a pullup common pin and pin 8 represents a pulldown
common pin, then <value1> represents the pullup common pin because pin 5 is a
"lower" number than pin 8.
See also: “Choosing a Package” on page 328
• Capacitors—To specify a capacitor value, use a line of form:
<reference_designator>, <value>
To specify a capacitor value for a network-package capacitor with two values, use a line
of form:
<reference_designator>, <value1> [, [<value2>] [, <package_name>]]
where <value1> maps to the common pin in the capacitor package with the lower pin
number.
Example: If the package has two common pins 5 and 8, then <value1> represents pin 5
because it is a "lower" number than pin 8.
See also: “Choosing a Package” on page 328

Formatting Unique to QPL Files

Rules in this section apply only to .QPL files. Square brackets [] enclose optional fields.

The .HYP file contains Part Name data in the NAME= fields in the DEVICE section of the
.HYP file. The NAME field is intended to enable PCB-layout translators to record whatever
information exists in the layout database about the name of a part. BoardSim uses the part name
data in a .QPL file to map to Part Name data in the .HYP file.

• .MOD IC models—Name of the model that applies to the entire IC component. To

specify a .MOD IC model, use a line of form:
IC, <part_name>, "description", <library.MOD>, <model_name>
.IBS, and .PML models—Specify a component name. The component name must match
a component described in the specified library file.
To specify an .IBS IC model, use a line of form:
IC, <part_name>, "description", <library.IBS>, <component_name>
To specify a .PML IC model, use a line of form:
IC, <part_name>, "description", <library.PML>, <component_name>

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• .EBD models—Board description. The board description must match a board

description described in the specified library file.
To specify an .EBD IC model, use a line of form:
IC, <part_name>, "description", <library.EBD>, <board_description>
• The description field may be left blank by typing two double quotes followed by a
comma or by typing just the comma. Examples:
IC, <part_name>, "", <library.IBS>, <component_name>
IC, <part_name>, , <library.IBS>, <component_name>
• Resistors—A resistor-value line can contain one or two values, depending on whether
the resistor is a single component (discrete or a single-valued pull-up or pull-down
network) or a pull-up/pull-down network.
To specify a resistor value for a discrete resistor or for a network-package resistor with a
single value, such as a pull-up resistor, use a line of form:
R, <part_name>, "description", <value>
To specify a resistor value for a network-package resistor with two values, such as used
for pullup and pulldown resistors, use a line of form:
R, <part_name>, "description", <value1> [, [<value2>] [, <package_name>]]
where <value1> maps to the common pin in the resistor package with the lower pin
number.
Example: If pin 5 represents a pullup common pin and pin 8 represents a pulldown
common pin, then <value1> represents the pullup common pin because pin 5 is a
"lower" number than pin 8.
See also: “Choosing a Package” on page 328
• Capacitors—To specify a non-decoupling capacitor value, use a line of form:
C, <part_name>, "description", <value>
To specify a capacitor value for a network-package capacitor with two values, use a line
of form:
C, <part_name>, "description", <value1> [, [<value2>] [, <package_name>]]
where <value1> maps to the common pin in the capacitor package with the lower pin
number.
Example: If the package has two common pins 5 and 8, then <value1> represents pin 5
because it is a "lower" number than pin 8.
See also: “Choosing a Package” on page 328

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• Decoupling capacitors
To specify a decoupling capacitor value and manually specify ESL, use a line of form:
o DECAP, <part_name>, “description”, RLC, <C>, <ESR>, <ESL>,
<capacitor_model_includes_mounting_inductance yes| no>
To specify a decoupling capacitor value and automatically calculate ESL by
automatically determining package dimensions (equivalent to using the QPL-File Editor
ESL by capacitor size option using the <Auto-estimate> list item), use a line of form:
o DECAP, <part_name>, “description”, RLC, <C>, <ESR>,
<capacitor_model_includes_mounting_inductance yes | no>
To specify a decoupling capacitor value and automatically calculate ESL by manually
specifying package dimensions, use a line of form:
o DECAP, <part_name>, “description”, RLC, <C>, <ESR>, <package_width>,
<package_length>, <package_height>,
<capacitor_model_includes_mounting_inductance yes | no>
Units for package dimensions can be: m, cm, mm, in, mil.
To specify a decoupling capacitor model in a library, use a line of form:
o DECAP, <part_name>, “description”, Library, <library_name>, <model_name>
To specify a decoupling capacitor model in a SPICE file, use a line of form:
o DECAP, <part_name>, “description”, SPICE, <file_name>, <device_name>,
<capacitor_model_includes_mounting_inductance yes | no>,
<model_node>=<capacitor_pin_name>
To specify a decoupling capacitor model in a Touchstone file, use a line of form:
o DECAP, <part_name>, “description”, Touchstone, <file_name>,
<capacitor_model_includes_mounting_inductance yes | no>,
<model_port>=<capacitor_pin_name>
• BoardSim reads only lines starting with IC, R, and C. No warnings are written when
lines start with different characters.
• Table 6-11 specifies the maximum length of the various fields.

Table 6-11. Maximum Length of Fields in .QPL Files

part_name 40
description 80
library_name 100
component/model_name 50

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Related Topics
“Selecting Models and Values for Entire Components” on page 296

Debugging Errors in REF and QPL Files

Particularly if you create a large automapping files, you may accidentally introduce errors into
the file that need to be corrected before they work perfectly.

This topic contains the following:

• “Syntax Errors in REF Files” on page 316

• “Syntax Errors in QPL Files” on page 317
• “Model Contents and Model Location Errors” on page 317
You might not experience these types of errors if you use the REF-File Editor or QPL-File
Editor to create and maintain automapping files.

See also: “Selecting Models and Values for Entire Components” on page 296

Syntax Errors in REF Files

Syntax errors in .REF files are reported immediately when you load the board or schematic.
While syntax errors are not fatal (that is, you do not have to immediately correct the errors and
reload the design), the erroneous line and all the lines following it are discarded.

The following .REF file illustrates some syntax errors:

*Line 3 is bad (this is line one)

U1, generic.mod, 74ac11xx:gate
x
U7, GENERIC.MOD, 74HCTXX:GATE-2
U9, GENERIC.MOD, 74HCTXX:GATE-2

Line 2 is read and will be activated when a net connected to U1 is selected for signal-integrity
simulation.

Line 3 has a syntax error and the remaining lines are not read.

You have the following options when errors for a .REF file are reported:

• Ignore the errors, and interactively load the models that failed to load automatically
from the .REF file
• Fix the .REF file to eliminate the errors, save the fixed file, and then continue working in
BoardSim or LineSim

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To make the second option (fixing the .REF file) easier, BoardSim and LineSim do not require
you to reload your board or schematic after editing and saving the fixed .REF file. Instead,
BoardSim/LineSim detects when the .REF file has changed, automatically reloads it, and then
uses information from the new version of the file.

Syntax Errors in QPL Files

Syntax checks are not performed on .QPL file(s) when you load the board file into BoardSim or
load the .QPL file into the QPL-File Editor. The reason is that .QPL files can be very large and
syntax-checking would be CPU-intensive.

By contrast to .REF files, lines following an erroneous line in the .QPL file are not discarded.

You have the following options when errors for a .QPL file are reported:

• Ignore the errors, and interactively load the models that failed to load automatically
from the .QPL file
• Fix the .QPL file to eliminate the errors, save the fixed file, and then continue working
in BoardSim
To make the second option (fixing the .QPL file) easier, BoardSim does not require you to
reload your board after editing and saving the fixed .QPL file. Instead, BoardSim detects when
the .QPL file has changed, automatically reloads it, and then uses information from the new
version of the file.

Model Contents and Model Location Errors

Automapping files might specify models or libraries that do not exist. One reason might be the
model library file no longer exists at the location specified in the Model-Library File Path(s)
box in the Set Directories dialog box. Another reason is that the name of the model, component,
or board description specified in the automapping file does not exist in the model library.

See also: “Set Directories Dialog Box” on page 1854

Errors Reported During Interactive Signal-Integrity Simulation

During interactive signal-integrity simulation, model content or location errors are not reported
until the information in the line is actually used. For example, if you are using BoardSim and
select and simulate a net that includes IC components that receive model assignments from an
automapping file, but one of the lines used to map the component to a model specifies a model
library location that does not exist. In this case, errors are reported when attempting to load
models for the just-selected net.

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Errors Reported During Batch Signal-Integrity Simulation

Because batch signal-integrity simulation must run unattended, BoardSim suppresses real-time
reporting of model-related errors. Instead, model assignment errors are listed in the batch
simulation report.

Example REF File Errors

The following .REF file illustrates model contents and model location errors:

*Two errors in this file (this is line one)

U1, generic.mod, foo
U7, GENERIC.MOD, 74HCTXX:GATE-2
U9, GENERIC.FOO, 74HCTXX:GATE-2

Assume that library GENERIC.MOD does not contain the model foo and that net CLK connects
to pins on components U1 and U9. When net CLK is selected and interactively simulated, the
errors that occur on lines 2 and 4 are reported.

Line 2 is erroneous because the model foo cannot be found in the library GENERIC.MOD.

Line 4 is erroneous because GENERIC.FOO does not have a .MOD, .PML, or .IBS/.EBD
library filename extension.

Example QPL File Errors

The following .QPL file illustrates model contents and model location errors:

*Two errors in this file (this is line one)

IC, 74AC161S, "HyperLynx 74AC", 74AC.PML, 74AC161_FOO
IC, 74HCT99, "LineSim Model", GENERIC.FOO, 74HCTXX:GATE-2
IC, 74AC160, "HyperLynx 74AC", 74AC.PML, 74AC160_SSOP

Assume that library 74AC.PML does not contain the component 74AC161_FOO and that net
CLK connects to pins on components with part names of 74AC161S and 74HCT99. When net
CLK is selected and interactively simulated, the errors that occur on lines 2 and 3 are reported.

Line 2 is erroneous because the component 74AC161_FOO cannot be found in the library
74AC.PML.

Line 3 is erroneous because GENERIC.FOO does not have a .MOD, .PML, or .IBS/.EBD
library filename extension.

Note that these errors are not fatal, but they do indicate that some of the models that were
specified in the .QPL file have not been loaded for the selected net. These errors occur line-by-
line and are independent of other such errors in the .QPL file.

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For example, in the example .QPL file above, if net CLK connects to components named
74AC160, 74AC161S and 74HCT99, no models would be loaded for 74AC161S or 74HCT99,
but the model would be loaded for 74AC160_SSOP.

Related Topics
“Selecting Models and Values for Entire Components” on page 296

Temporarily Disabling REF and QPL Files

You can temporarily disable .REF and .QPL model and value assignments. You might want to
do this during a "what if" experiment.

To disable .REF files:

1. Do either of the following:

• Rename the .REF file name or extension so that it does not match
<design_file_name>.ref. For example, if the design is named demo.hyp, rename
demo.ref to demox.ref.
• Move the .REF file to another folder.
2. Activate the changes by reloading the board or schematic.
To disable all .QPL files:

1. Select Setup > Options > Directories.

2. Clear the Use QPL File To Assign Models check box.
3. Click OK.
4. Activate the changes by selecting a net.

Related Topics
“Selecting Models and Values for Entire Components” on page 296

Interactively Editing Rs - Ls - Cs
Use the Assign Models dialog box to verify and edit resistor, capacitor, and inductor values.
BoardSim has built-in models for resistors, capacitors, and inductors, but it must know the value
of the component.

For resistors or capacitors that are packaged as networks rather than discretely, BoardSim must
also know how the components are packaged. For example, a discrete resistor R1 has only one
parameter that can be edited: Its resistance. But resistor network RP1 (a network of four
resistors to be used as pull-ups or pull-downs) has two parameters that can be edited: The

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resistance of the resistors in the network and the type of package in which the resistors are
housed.

See also: “Choosing Resistor and Capacitor Packages” on page 322

You should check the values of all the resistors, capacitors, and inductors on a net before you
simulate the net for the first time. BoardSim attempts to automatically determine the values for
components as it loads the board file for your board. For resistors, capacitors, and inductors,
each record in the .HYP-file DEVICES list contains a field called VAL; BoardSim examines
the VAL record and attempts to convert it to a component value.

This topic contains the following:

• “Editing Resistor - Capacitor - Inductor Values” on page 320

• “Value Applies to Whole Component” on page 322
• “Default Resistor - Capacitor - Inductor Values” on page 322

Editing Resistor - Capacitor - Inductor Values

Edited resistor, capacitor, and inductor values are stored in the BoardSim session-edit file
(.BUD) and are available when you re-open the board file.

See also: “BoardSim Session Files” on page 56

You can also use .REF and .QPL automapping files to specify resistor and capacitor values.

See also: “Selecting Models and Values for Entire Components” on page 296

To interactively edit resistor, capacitor, and inductor values:

1. Do any of the following:

• Select the net or reference designator for the R, L, or C component, and click Select
Component Models and Values on the toolbar.
See also: “Selecting Nets for SI Analysis” on page 272
• Right-click over the component pin and click Assign Value.
2. If you right-clicked over the component pin to open the Assign Models dialog box, go to
step 5.
3. If you have loaded a MultiBoard project into BoardSim, select the correct board from
the Design File list.
4. In the Pins list, select the component pin for the R, L, or C value you want to edit.

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5. If you have loaded a MultiBoard project into BoardSim, and selected a board that is used
multiple times in the MultiBoard project, do one of the following:
a. To propagate the new R, L, or C value to all copies, that is, instances, of that board,
select the Apply to all similar boards check box.
b. To edit the R, L, or C value for only the current instance of the board, clear the
Apply to all similar boards check box.
Recommendation: Do not clear the Apply to all similar boards check box unless you
have read the linked topic below.
See also: “Steps to Save Session Edits for Multiple Board Instances” on page 770
Clearing the Apply to all similar boards check box does not persist. The check box will
be selected the next time you open the Assign Models dialog box.
6. In the Value box, type a new value.
Values can be entered as a simple number, for example 1000 or .01, or in scientific
notation, for example 1e3 or 1e-2.
If the pin is part of a networked-resistor or networked-capacitor package, there may be
one or two Value boxes for the component. See “Editing Package Component Values”
on page 330.
If you have used the .REF file to assign resistor or capacitor values, the value in the
Value box overrides the .REF file value. However because there is no Remove button in
the Assign Models dialog box when the Resistor tab is selected, you cannot
automatically restore the .REF file value for an individual pin. A workaround is to
interactively assign the value from the .REF file. See “Selecting Models and Values for
Entire Components” on page 296.
7. To copy the value to other components of the same type on the selected net and
associated nets, click Copy, and then do one of the following:
a. To paste the value to one other component, select the other component in the Pins
list and click Paste.
b. To paste the value to all other components, click Paste All.
Separate copy buffers are maintained for each component type.
Example: If you select a pin on a component of a different type, such as you copied a
value from a resistor and selected a pin on a capacitor, the Model to Paste area shows the
last value (if any) copied from a capacitor.
8. Click Close.

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Value Applies to Whole Component

When you change the value for one pin on an R, L, or C component, the value changes for all
pins on the component. For example, if a discrete resistor has pins 1 and 2, and you change the
value for pin 1, it is automatically changed for pin 2. However, since the Pins list normally
shows only one of the resistor pins, you would have to select another net to see the second pin.
The same is true of resistor networks (multiple resistors in a network, inside a single package).
If you change the resistor value for any pin on the package, the value of all resistors in the
network changes.

See also: “Choosing Resistor and Capacitor Packages” on page 322

Default Resistor - Capacitor - Inductor Values

Unfortunately, there is no guarantee that the VAL record in the .HYP file will be set by the
.HYP-file translator to the component value. In fact, some translators do not support VAL
records at all. In other cases, VAL may be set properly for some components on your board and
not for others. If the VAL record is missing or invalid, the corresponding component values are
set as follows:

• R1000 ohms
• C0.0 Farads
• L1.0 nanoHenry

Related Topics
“Terminating Nets” on page 935

Choosing Resistor and Capacitor Packages

This topic describes what is meant by a "packaged" component, and how to choose and define
component packages.

This topic contains the following:

• “About Networked-Component Packages” on page 323

• “Default Package Library” on page 324
• “How BoardSim Automatically Identifies Packages” on page 325
• “Choosing a Package” on page 328
• “Editing Package Component Values” on page 330
• “Adding a User Package Definition” on page 332

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About Networked-Component Packages

On your board, resistors and capacitors can be packaged either discretely (e.g., a single resistor)
or as part of a component network (e.g., one of four pull-up resistors in a single package).

In order to simulate a net that connects to a networked component, BoardSim must know in
what kind of package the component is housed. In particular, BoardSim must know how the
package connects the networked components internally.

For example, there is a big difference to BoardSim’s simulator between an -pin SIP with four
series resistors, and an -pin SIP with 7 pull-up resistors.

This topic contains the following:

• “Supported Component Types” on page 323

• “Supported Connection Styles” on page 323
• “How Networked-Component Packages Affect Signal-Integrity Simulation” on
page 324

Supported Component Types

BoardSim allows resistors and capacitors to be housed in network packages. BoardSim does not
currently support inductors, ferrite beads, or R-C combinations in network packages.

See also: “About Reference-Designator Mapping in BoardSim” on page 209

Supported Connection Styles

BoardSim recognizes several styles of internal connection in network packages:

• Series—each component in the package has two independent pins, i.e., is independent of
the other components
• Pull-up—each component in the package has one independent pin and one pin in
common with the other components
• Pull-up/pull-down—each component in the package has one independent pin and two
pins in common with the other components
The names of the connection styles are descriptive of how each style is typically used, but you
can connect a package to the nets on your board in any way you like.

Example: A pull-up-style package with four resistors is typically used to implement four pull-
up or pull-down resistors, but BoardSim does not care if you use it some other way.

However, in the preceding example, BoardSim will not automatically identify the correct
package. You will have to change the package choice manually.

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See also: “How BoardSim Automatically Identifies Packages” on page 325, “Choosing a
Package” on page 328

How Networked-Component Packages Affect Signal-Integrity

Simulation
BoardSim uses package information to identify associated nets, when the net being simulated
connects to a resistor or capacitor network. If BoardSim does not know how a network package
is connected internally, it cannot properly find associated nets.

It is not just a matter of BoardSim omitting associated nets if it has wrong connectivity
information—it may actually find incorrect associations. Always be sure that any network
packages on nets you are simulating are correctly identified.

See also: “Associated Nets” on page 272, “Choosing a Package” on page 328

Default Package Library

BoardSim supplies a library of common network packages in the file BSW.PAK. BoardSim
automatically loads BSW.PAK and makes the package definitions in the library available for
assigning to network packages on your board. It also attempts to make automatic assignments
for networked components on your board to packages in the library.

If your board uses a package not described in BSW.PAK, you can add a definition of your own.
See “Adding a User Package Definition” on page 332.

See also: “How BoardSim Automatically Identifies Packages” on page 325, “Choosing a
Package” on page 328

Elements of a Package Definition

Each package definition consists of the following information:

• Name—a name for the package

• Style—combination of connection style and component type (e.g., R_PULLUP,
meaning a resistor network connected internally in pull-up style)
• Shape—SIP or DIP
• Number of pins—the total number of pins on the package
• List of pin pairs—a list showing to which pins each component in the package is
connected
BoardSim shows you each package definition graphically when you choose packages.

The library BSW.PAK is written in the .PAK format.

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See also: “PAK File Specification” on page 1327

How BoardSim Automatically Identifies Packages

When you load your board (and again if you edit power-supply nets), BoardSim scans your
board to find associated nets. Part of finding associated nets is attempting to automatically
identify a package definition for each resistor or capacitor network on your board.

BoardSim cannot correctly determine the package for every networked component on your
board. You should check the package assignments of all the networked components on a net
before you simulate the net for the first time. Make changes to any incorrect definitions that
BoardSim has made.

See also: “Associated Nets” on page 272, “Choosing a Package” on page 328, “Adding a User
Package Definition” on page 332

Once you have chosen a package, BoardSim remembers your choice; if you come back to re-
simulate the net (in the same BoardSim session or in another), BoardSim will automatically re-
load the package for you. See “BoardSim Session Files” on page 56 for details on how packages
are remembered.

This topic contains the following:

• “Details of Package Matching” on page 325

• “If Matching Problems Occur” on page 327
You probably will not need to know these rules, unless you are confused about why BoardSim
cannot match a particular component, or need to create your own package definition.

Details of Package Matching

Determining There is a Package

BoardSim determines that a passive component is in a networked package by looking at the
number of pins on the component. If the component has three or more pins, BoardSim assumes
that it is in a networked package, not discrete.

For example, if R2 has only pins 1 and 2, BoardSim assumes it is a discrete resistor. But if R2
has six pins:

(1—6), BoardSim assumes it is a resistor network.

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Package Shape
BoardSim supports two package shapes: DIP and SIP. To determine which shape a component
is, BoardSim looks at the location of its pins. If all the pins fall on a line, the package is SIP; if
not, it is assumed to be DIP.

See "Number of Pins" below for more information.

Number of Pins
BoardSim uses two methods to count the number of pins on a networked component. The larger
of the two counts is used for the number of pins.

By Counting Connections
The first method for counting pins is to simply count the number of pins on the component that
are connected to nets on the board.

Though this method sounds fool-proof, it is not: some pins on a component may be
unconnected. Unconnected pins are not reported in the board file for your board, and the
resulting pin count is too low.

By Looking at Pin Names

The second method for counting pins is to attempt to convert each pin name on the component
into an integer. (This works only for components that have numeric names, e.g., "1", "2", etc.
All packages defined in BSW.PAK have numeric names.) The largest resulting integer is used
as the pin count.

Limitations on Automatic Pin Counting

There is at least one situation in which BoardSim cannot correctly count the number of pins on
a networked component: if the highest-numbered pin on the component is unconnected, and
therefore not reported in the board file. For this reason, BoardSim will always make available
the candidate packages with the next-highest pin count (e.g., 10-pin packages even if only pins
are counted.

See also: “Next-Bigger Packages Included - In the Select Package Dialog Box” on page 328

Connection Style
BoardSim determines the connection style of a package by counting the number of power-
supply nets connected to the component. The rules are:

• 0 power-supply nets series style

• 1 power-supply net pull-up style

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• 2 power-supply nets pull-up/pull-down style

If a package is connected in an unusual way (e.g., a pull-up-style package is used to implement
series resistors), BoardSim may assign an incorrect package (with the wrong connection style)
to the component. You may need to manually change the assignment.

See also: “Choosing a Package” on page 328

Final Matching
When BoardSim has determined all of the criteria for a networked component (package shape,
number of pins, and connection style), it begins searching its package definitions for a match to
the component.

When a candidate definition is found, BoardSim applies two additional criteria before declaring
a match:

• if the package is pull-up style or pull-up/pull-down style, are the power-supply nets
connected to the power-supply pins (i.e., "common" pins) on the candidate package?
• does the name of every pin on the component match the name of a pin on the candidate
package?
If the answer to both questions is "yes," BoardSim matches the package definition to the
networked component. If either answer is "no," BoardSim continues searching for a match.

All of the package definitions in BSW.PAK use numeric pin name (1, 2, etc.). The requirement
that pin names on the component match pin names in the package definition means that if you
number your networked-component pins differently (e.g., A, B, etc.), you must create your own
package definition that includes your custom pin names.

See also: “Adding a User Package Definition” on page 332

If Matching Problems Occur

If No Match is Found
If no match is found, BoardSim will omit nets associated through the resistor or capacitor
network with the net being simulated. This can result in serious signal-integrity simulation
errors.

For example, if you ask BoardSim to simulate Net1 which is connected through a networked
series resistor to Net2, but BoardSim cannot identify a package style for the resistor network,
BoardSim will fail to find Net2 as an associated net and will not simulate it.

Or, similarly, if Net1 is connected through a networked resistor to a power-supply voltage, but
the network has no package, BoardSim will ignore the pull-up voltage, resulting in an incorrect
signal-integrity simulation waveform.

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The solution to these problems is to manually choose the correct packages for mis-identified
component packages on your board, before simulating. Sometimes, this requires creating your
own custom package definition.

See also: “Adding a User Package Definition” on page 332

If Multiple Matches are Found

It is possible for multiple package definitions in BoardSim’s list to match a networked
component. For example, for an -pin series-style resistor network in a DIP package, there may
be two kinds of internal connection: resistors between adjacent pins (1 and 2, 3 and 4, etc.); and
resistors between opposite pins (1 and 2, 2 and 7, etc.).

Also, BoardSim generally offers not only packages with a matching number of pins, but also
packages with the next-highest number of pins, in case the highest-numbered pin on the
component is unconnected. These next-larger packages are also available for selection.

See also: “Next-Bigger Packages Included - In the Select Package Dialog Box” on page 328

In cases where there are multiple matches, BoardSim arbitrarily uses the first match. This may
not be correct. The solution to this problem is to choose the correct package before simulating.

See also: “Choosing a Package” on page 328

Next-Bigger Packages Included - In the Select Package Dialog Box

Because it is not uncommon for a resistor or capacitor package to have one or more of its
highest-numbered pins unconnected, the Select Package dialog box displays not only package
styles that match the number of connected pins on a package, but also styles with the next-
largest number of pins.

For example, if a package has 8 pins connected, the dialog box lists possible 8-pin packages
AND (if the next-largest packages in the database are 10-pin) possible 10-pin packages. Then, if
the 8-pin package really has 10 pins but pins 9 and 10 are unconnected, you can still choose the
correct, 10-pin package.

Next-Bigger Packages Included - During Automatic Selection

Also, if there are no packages in the database with a matching number of pins, BoardSim tries to
automatically match the package to styles with the next-highest number of pins. For example, if
a package has 9 connected pins, but the package database has no 9-pin packages, BoardSim will
try to match the package to a 10-pin package.

Choosing a Package
Use the Assign Models dialog box to choose a package for a networked resistor or capacitor.

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This topic contains the following:

• “Selecting a Package For a Networked Resistor or Capacitor” on page 329

• “The Packages List” on page 330
• “The Connectivity Picture” on page 330
You can also use the REF-File Editor and QPL-File Editor to choose resistor and capacitor
packages and specify component values.

See also: “Selecting Models and Values for Entire Components” on page 296

Selecting a Package For a Networked Resistor or Capacitor

To select a package for a networked resistor or capacitor:

1. Click Select Component Models or Edit Values or Select Models > Assign
Models/Values by Net.
2. In the Pins list, select a pin on the network-packaged component. Be sure that the
component-type icon in the models area shows a resistor or capacitor rather than an IC
or other component. (You can choose network packages only for resistor or capacitors.)
3. Click Select.
Alternative: Double-click the pin in the Pins list.
Result: The Select Package dialog box opens.
4. If the Packages list is empty, BoardSim cannot match any existing package descriptions
to the component; you must add a description to file USER.PAK.
Close the editor and refer to “Adding a User Package Definition” on page 332 If the
Packages list has entries, the Connectivity area displays the current package choice.
5. In the Packages list, select the new package you want to choose.
(As you highlight packages in the list, the connectivity picture changes to show you how
the package is connected internally.)
6. Click OK.
Alternative: Double-click the package name.
Result: The Select Package dialog box closes, and the package is chosen. Its
connectivity picture appears in the Connectivity area.
You can choose a new package by selecting any pin on the affected component; changing the
package for one pin changes it for the whole component.

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You can change the component value for a networked component just like you would for a
discrete component.

See also: “Interactively Editing Rs - Ls - Cs” on page 319

The Packages List

The information in the Packages list includes:

• Package name
• Package shape (SIP or DIP)
• Total number of pins on the package
The package names in BSW.PAK are fairly detailed, so the shape and number of pins are
usually obvious just from reading the name.

The packages listed in the Packages list are taken from the file BSW.PAK when BoardSim
loads your board from the file BSW.PAK. If you create any additional package definitions and
put them in file USER.PAK, your packages are displayed at the end of the list.

See also: “Adding a User Package Definition” on page 332

The Connectivity Picture

The connectivity picture attempts to show you graphically how the components in a network
package are connected. The following points apply to the connectivity picture:

• Internal components (resistors or capacitors) are displayed only as little boxes

• Package pins are displayed in blue
• Connections are displayed in the following colors:
• Black for connections between independent pins and component ends
• Maroon for connections between common pin #1 (i.e., power-supply pin #1) and
component ends
• Green for connections between common pin #2 and component ends
• As much of a package as will fit in the Connectivity area is displayed; if a package is too
long, its picture is truncated

Editing Package Component Values

Use the Assign Models dialog box to interactively edit package component values.

You can also edit package component values using .REF or .QPL automapping files.

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See also: “Selecting Models and Values for Entire Components” on page 296

This topic contains the following:

• “Editing Component Values for Series-Style Packages” on page 331

• “Editing Component Values for Pullup-Style Packages” on page 331
• “Editing Component Values for Pullup- and Pulldown-Style Packages” on page 331

Editing Component Values for Series-Style Packages

To edit the component value for series-style package:

1. Click Select Component Models or Edit Values or select Models > Assign
Models/Values by Net.
2. In the Assign Models dialog box, in the Pins list, select a pin on the network package.
3. Type the new value in the Value box.
The new value applies to all components in the network package.
4. Click OK.

Editing Component Values for Pullup-Style Packages

To edit the component value for pull-up-style package:

1. Click Select Component Models or Edit Values or select Models > Assign
Models/Values by Net.
2. In the Assign Models dialog box, in the Pins list, select a pin on the network package.
3. Type the new value in the Value field.
The label around the Value field identifies the pin name of the single common pin on the
package.
The new value applies to all components in the network package.
4. Click OK.

Editing Component Values for Pullup- and Pulldown-Style

Packages
To edit the component value for pullup/pulldown-style package:

1. Click Select Component Models or Edit Values or select Models > Assign
Models/Values by Net.

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2. In the Assign Models dialog box, in the Pins list, select a pin on the network package.
3. Do the following:
a. In the upper Value field, type the value for the components connected to the
common pin with the lower pin number. The pin number of the common pin is
displayed above this field.
b. In the lower Value field, type the value for the components connected to the
common pin with the higher pin number.
The Connectivity area provides information about package connectivity, including how
the color of the lines indicates which common pin they connect to.
See also: “The Connectivity Picture” on page 330
4. Click OK.

Adding a User Package Definition

BoardSim ships with a library of passive-component packages (BSW.PAK). However,
eventually you may use a component network that is not described in BSW.PAK. Fortunately, it
is easy to add your own package definitions to the user-defined package library, USER.PAK.

When you first install BoardSim, there is no file USER.PAK. You create it the first time you
need to add your own package definition.

This topic contains the following:

• “Reasons for Creating a Custom Package” on page 332

• “How User Package Library Supplements Default Package Library” on page 333
• “Syntax for Package Definitions” on page 333
• “How to Create a Custom Package Definition” on page 333
• “User Package Library Example - Defining a New Package” on page 334
• “Saving User Package Libraries” on page 335

Reasons for Creating a Custom Package

You must create your own custom package definition any time there is a passive-component
network on your board that does not match any definition in BoardSim’s package library. There
are several reasons why there might be no matches:

• You have a component on your board for which there is truly no definition. For
example, you have a component with 2 pins, but BSW.PAK only supports components

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up to 24 pins; or you have a custom component with an unusual interconnection scheme

not covered in BSW.PAK
• You have a component on your board that IS described in BSW.PAK—but BoardSim
does not recognize the component. For example, you have 16-pin DIP series resistor
network, but pin 16 is unconnected and so does not appear in BoardSim’s database.
BoardSim thinks the package has 15 pins, and cannot find a match.
For more insight into how mis-identifications can occur, see “How BoardSim Automatically
Identifies Packages” on page 325 for a complete description of how BoardSim matches
packages.

If you must create a package definition to cover a mis-identification, the package may well be
"phony," i.e., something that does not really exist, but that matches BoardSim’s "understanding"
of what the component looks like.

How User Package Library Supplements Default Package Library

At the end of loading your board, BoardSim loads the file BSW.PAK. BSW.PAK is a package
library supplied by HyperLynx; it contains package definitions for a wide range of common
resistor and capacitor networks. The information in BSW.PAK is displayed in the Packages list
when you open the package editor.

See also: “Choosing a Package” on page 328

After loading BSW.PAK, BoardSim looks to see if there is a file called "USER.PAK." If so, it
loads USER.PAK and appends the information in it to the packages list. Thus, you can add
package definitions of your own to USER.PAK to supplement the packages in BSW.PAK.

Syntax for Package Definitions

USER.PAK must be written in BoardSim’s .PAK-file format. Before you attempt to create your
own definition, you should understand the .PAK file syntax fully.

See also: “PAK File Specification” on page 1327

How to Create a Custom Package Definition

USER.PAK must be ASCII-only; create it in a text editor, not an editor that introduces non-
ASCII formatting characters into the file. The HyperLynx file editor is a good choice for this
purpose. The file must be located in BoardSim’s root directory (i.e., the directory that
BSW.EXE is installed in.)

You might want to copy a portion of BSW.PAK to USER.PAK to give yourself a "head start."
Then you can modify existing definitions to create your own. Be careful not to leave any
PACKAGE names in USER.PAK that already exist in BSW.PAK.

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User Package Library Example - Defining a New Package

Suppose you need to model a resistor network that is a 9-pin pull-up style (resistors, each with
one end tied to a common pin), in a SIP package. There is no definition for this package in
BSW.PAK.

To create USER.PAK:

1. In a text editor (like the HyperLynx File Editor), begin editing a new file.
Use a text editor, not a word processor that inserts non-ASCII formatting characters into
the file.
2. At the top of the file, place these two lines:
{PAK}
{VERSION=1.10}

To enter the package’s definition:

• Immediately following the two header lines, add the definition of the new package,
followed by the {END} record:
{PACK=9_PIN_SIP_PULLUP
(STYLE=R_PULLUP)
(SHAPE=SIP)
(TOTAL_PINS=9)
(PIN_PAIR=2,1)
(PIN_PAIR=3,1)
(PIN_PAIR=4,1)
(PIN_PAIR=5,1)
(PIN_PAIR=6,1)
(PIN_PAIR=7,1)
(PIN_PAIR=,1)
(PIN_PAIR=9,1)
(PIN_LOC=1,1)
(PIN_LOC=2,2)
(PIN_LOC=3,3)
(PIN_LOC=4,4)
(PIN_LOC=5,5)
(PIN_LOC=6,6)
(PIN_LOC=7,7)
(PIN_LOC=,)
(PIN_LOC=9,9)
}
{END}

If there are aspects of the package definition in this example that you do not understand, see the
PAK file specification, which includes more example definitions:

See also: “PAK File Specification” on page 1327

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Saving User Package Libraries

To save USER.PAK:

• Save the file as USER.PAK, into BoardSim’s root directory.

For example, if BoardSim is installed in
C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx, save the file as
C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx\USER.PAK.
The package description defines a 9-pin resistor network in a SIP package, with PULL_UP
connection style, model name 9_PIN_SIP_PULLUP, and pin 1 as the common pin shared by
each resistor. It is easily created by copying the -pin SIP pull-up from BSW.PAK, pasting it into
USER.PAK, and modifying it slightly.

The new package model will be available in BoardSim as soon as you load (or re-load) a board.
(BSW.PAK and USER.PAK are read every time a board is loaded.)

Reporting Board and Net Properties

This topic contains the following:

• “Reporting Board Properties” on page 335

• “Reporting Net Properties” on page 336
• “Reporting Net Segment Properties” on page 337
• “Reporting Design Changes” on page 338

Related Topics
“Viewing Via Properties” on page 1056

Reporting Board Properties

You can create a report containing the total number of nets, segments, pins, and vias on the
board.

BoardSim reads the board file to generate the report. Depending on how the .HYP-file translator
for your PCB-layout package works, there may be small discrepancies from similar totals
reported by your layout software.

To view board statistics:

• Select Export > Reports > Board Statistics.

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Reporting Net Properties

Use the Statistics for Selected Net dialog box to report a set of statistics for the selected net.

See also: “Selecting Nets for SI Analysis” on page 272

To report net statistics:

1. Select Export > Reports > Net Statistics.

Result: The Statistics for Selected Net dialog box displays several statistics for the
selected net and its associated nets.
2. To copy the report to the Windows clipboard, so you can paste the information to an
application such as Word or Wordpad, click Copy to Clip.
3. Click OK.

Report Description
In the following paragraphs, "net" represents both the selected net and its associated nets.

The total delay gives the summed propagation delay of every metal segment on the net. Total
length gives the summed physical length of every segment.

The minimum and maximum characteristic impedances are per-segment on the net, and give a
rough indication of how much impedance mismatch there is on the net.

The total receiver load capacitance gives the summed value of all the receiver capacitances on
the selected net. Large capacitance values may indicate increased signal delays.

Total resistance gives the summed DC resistance of every segment on the net.

The effective net Z0 is a figure that attempts to show by how much the selected net’s actual
characteristic impedance is effectively lowered by the presence of IC capacitance along the net.
This value can be used as a guide when choosing termination resistances, since for nets that are
significantly loaded by IC capacitance, the proper termination value is often lower than
suggested by the net’s actual Z0.

Estimated peak crosstalk gives a rough estimate of the total amount of crosstalk that could occur
on the net, based on the neighboring "aggressor" nets and the ICs driving them.

Requirement: This value is displayed only if you are licensed for BoardSim Crosstalk, have
crosstalk analysis enabled, and are using electrical (rather than geometric) thresholds.

See also: “How to Set the Crosstalk Threshold” on page 1223

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For convenience, the Associated Nets list displays the nets associated with the selected net and
—if you are licensed for BoardSim Crosstalk and have crosstalk analysis enabled—the
aggressor nets coupled to it. Nets that are coupled are identified in the list with the tag "by
coupling."

Related Topics
“Reporting Board and Net Properties” on page 335

Reporting Net Segment Properties

You can view properties and field solver results for individual net segments that you select in
the board viewer.

You can use the board viewer to:

• “Viewing Net Segment Properties” on page 337

• “Viewing Net Segment Field-Solver Output” on page 337
• “Viewing Net Segment Attenuation Over a Frequency Range” on page 338

Viewing Net Segment Properties

To report properties for a net segment:

1. Right-click over the segment and click View Segment Properties.

Result: The Segment Properties dialog box displays various segment properties.
2. To copy the segment properties to the Windows Clipboard, so you can paste the values
into another application such as Word or Wordpad, click Copy to Clip, and then click
Close.

Viewing Net Segment Field-Solver Output

To view field solver output for a net segment:

1. Right-click over the segment and click View Field-Solver Output.

2. Click the Field Solver tab.
See also: “Viewing Electrical Field Lines” on page 1207
3. To view numerical field-solver results, click View.
Result: A file editor displays the results.
4. Click Close.

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Viewing Net Segment Attenuation Over a Frequency Range

To view attenuation over a frequency range for a net segment:

1. Right-click over the segment and click View Field-Solver Output.

2. Click the Loss tab.
Restriction: The Loss tab is unavailable unless you enable both Crosstalk and Lossy
simulation options on the toolbar.
See also: “Displaying Loss Versus Frequency in BoardSim” on page 394
3. Click Close.

Related Topics
“Reporting Board and Net Properties” on page 335

Reporting Design Changes

To access: Export > Reports > Design Change Summary

Use the Design Changes dialog box to generate a concise report of all the component changes
you have made on your board to improve signal quality or lower radiated emissions (EMC).
This report might be appropriate to give to your layout designer or service bureau as a record of
changes you want made to your board in its next revision. You could also use the list yourself to
drive changes in schematics for the board.

The design change summary includes the following changes:

• Stackup—Such as thickness adjustments to affect impedances

• Changed components—Such as modified terminating component values to improve
signal quality
• New components—Such as new terminators (Quick Terminators) to improve signal
quality
To create the design change summary:

1. Select Export > Reports > Design Change Summary.

2. Click Finish.
Result: The HyperLynx File Editor opens and displays the report. The report file is
named <board_file_name>.txt and is located in the folder that contains the board file.

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Related Topics
“Reporting Board and Net Properties” on page 335

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Setting Up Designs for Power-Integrity
Simulation

Power-integrity simulation requires detailed physical information about the power-distribution

network (PDN) in the design. This information can take the form of metal shapes (areas) and
trace segment geometries for power-supply nets, IC power/ground pin locations, stitching via
locations, via/padstack geometries, stackup layer geometries and material properties, and so on.

You assign power-integrity models to IC power-supply pins to apply simulation stimulus and
loads. AC power-integrity simulations, such as decoupling analysis, additionally require you to
map IC power-supply pins to reference nets and to assign values or models to decoupling
capacitors.

Restriction: Power-integrity simulation is unavailable for BoardSim MultiBoard designs and

LineSim cell-based schematics.

This topic contains the following:

• “Gathering Key Information About the PDN” on page 341

• “Design Setup Tasks for Power-Integrity Simulation” on page 344
• “About Power-Integrity Models” on page 349
• “Assigning Power-Integrity Models - BoardSim” on page 351
• “Assigning Power-Integrity Models - LineSim” on page 352

Related Topics
”QuickStart - Power Integrity”
“Assign Decoupling-Capacitor Groups Dialog Box” on page 1450
“Assign / Edit Capacitor Model Dialog Box” on page 1442

Gathering Key Information About the PDN

Before you begin setting up the design in BoardSim or LineSim, gather vital statistics about the
power-distribution network (PDN).

Note that DC drop simulation does not require AC-related information, such as power-supply
voltage ripple, IC on/off switching times, decoupling capacitor properties or models, and so on.

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Procedure
1. Obtain the voltage and allowed voltage ripple (in percent) for each power supply.
Specify ripple as an offset from the nominal DC voltage. Do not specify ripple as the
peak-to-peak range of the nominal DC voltage.
You may allocate 30% (or some other value) of the power budget for DC drop and the
rest for AC. To map this to a ripple value, if you have a 5% ripple budget, then you
would assign 1.5% (that is, 5% times 30%) to DC drop and 3.5% to AC impedance. The
30% value for the DC drop share of the power budget may not apply to your design. If
the design has very good AC impedance, you can allocate less to AC impedance and
more to DC drop. Similarly, if the design has few DC drop problems, you can allocate
more to AC impedance and less to DC drop.
2. Calculate the target impedance for the PDN, which is based on the peak transient current
for the PDN, power-supply voltage, and allowable voltage ripple.
The Decoupling Wizard provides access to the Target-Z Wizard. See “Decoupling
Wizard - Set the Target Impedance Page” on page 1525.
3. Identify the reference designators for ICs that consume significant power.
4. Obtain the current consumption properties for ICs that consume significant power.
o Maximum or typical current. See “Obtaining DC Current Properties for ICs” on
page 342.
o On/off switching times
5. Obtain decoupling capacitor properties or circuit models.
o Properties include capacitance, ESL (equivalent series inductance), and ESR
(equivalent series resistance).
o Supported circuit models include SPICE and Touchstone S-parameter models.
6. Obtain voltage-regulator module (VRM) resistance and inductance properties.
7. Identify the major power-supply nets. In BoardSim, you may have to manually identify
power-supply nets that are short or have few capacitors. See “Identifying Power-Supply
Nets - BoardSim” on page 345.

Obtaining DC Current Properties for ICs

For each power-supply net with significant current consumption, you obtain a typical or
maximum value for the total DC current for each current consumer (sink). You can obtain DC
current values by any of the following ways:

• Catalog IC—View the datasheet or ask the vendor

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Datasheets may provide parameter values that vary by system operation mode.
Depending on the details of the design, you may have to run multiple power-integrity
simulations (with different sink model values) to account for the different operational
modes, especially if it is not obvious which mode produces the highest DC current.
• FPGA—Run the power calculator provided by the FPGA development system
• ASIC—Ask the in-house IC designers at your company
You may not know exactly how the total current is distributed among the set of individual
component pins. In this case, assign the average of the total current to all component pins.

Related Topics
“Setting Up Designs for Power-Integrity Simulation” on page 341

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Design Setup Tasks for Power-Integrity Simulation

Design Setup Tasks for Power-Integrity

Simulation
Setting up designs for power-integrity simulation is a mixture of general and power-integrity-
specific set up tasks. The following types of model export also require setting up the design for
power-integrity simulation: 1) export PDN or channel models, 2) export signal via models.

See Table 7-1. The set of required setup tasks is almost the same for all the types of power-
integrity simulation and related model-exporting features. The exception is that you do not have
to assign decoupling capacitors when setting up designs for DC drop simulation.
Table 7-1. Design Setup Tasks for PI Simulation and Related Model Exporting
Bypass DC Drop
Co-Simulation
Decoupling
Export PDN or channel models
Export signal via models
Plane Noise
“Identifying Power-Supply Nets - BoardSim” Required Required
on page 345
“Identifying Stackup Plane Layers” on page 345 Required Required
“Setting Up Stackup Properties” on page 346 Required Required
“Verifying Padstack Properties” on page 346 Required Required
“Creating or Verifying Metal Shapes” on Required Required
page 346
“Assigning Decoupling Capacitor Models” on Required Ignored
page 347
“Required Power-Integrity Model Assignments” Required Required
on page 348
“Setup Anti-Pads and Anti-Segments Dialog Optional Optional
Box” on page 1860
“Surface Roughness Dialog Box” on page 1871 Optional Optional

Caution
BoardSim translators released prior to HyperLynx 8.0 do not provide sufficient details to
simulate power integrity. For a list of translator versions that support power integrity, see
“Translators That Support Power-Integrity Simulation”.

Power-supply net properties, model assignment values, and other design setup information, are
saved in the .BUD (BoardSim user session data) file or .FFS (LineSim free-form schematic)

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file, which is located in the <design> folder. See “About Design Folder Locations” on
page 1391.

Related Topics
“Assigning Power-Integrity Models - BoardSim” on page 351

“Adding Symbols to Power-Distribution Networks” - LineSim

“Setting Up Designs for Power-Integrity Simulation” on page 341

Identifying Power-Supply Nets - BoardSim

Verify the power and ground nets that you plan to simulate have been identified as power-
supply nets. Even though BoardSim attempts to automatically identify all power-supply nets,
the identification algorithm can miss power-supply nets with arbitrary names and few capacitor
connections. See “How BoardSim Identifies Power-Supply Nets” and “Editing Power-Supply
Net Properties”.

For example, see Figure 7-4 on page 351. At the top of the figure, a short trace connects the
VRM to an inductor that connects to a connector that brings in power from an off-board power
supply. BoardSim may not automatically identify the short trace as a power-supply net,
especially if it has an arbitrary net name, such as $483.

Caution
If a power-supply net is incorrectly identified as a signal net, it is subject to “net
cleaning” if you either select it for signal-integrity simulation or enable the “Remove
redundant metal from a board’s nets as the board is loaded” on page 1806 option.

For example, if a pair of IC power-supply and decoupling-capacitor pins are mounted

back to back with SMD pads and a through-hole via connects them, net cleaning replaces
the via with a simple Z model. This model can cause inaccurate DC drop and other
power-integrity simulation results.

If this happens, close the board, disable the Remove redundant metal from a board’s nets
as the board is loaded option, re-open the board, identify the net as a power-supply net,
and then run power-integrity simulation.

Identifying Stackup Plane Layers

Use the Stackup Editor to identify which metal layers act as reference layers by providing return
current paths for IC power-supply pins. Assign the Plane usage type to reference layers. See
“Creating and Editing Stackups” on page 353.

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When you open a board in BoardSim, the Stackup Verifier automatically calculates the
percentage of each metal layer that is consumed by metal shapes and trace segments. If a metal
layer has the Signal usage type and contains a percentage of metal that exceeds the threshold,
the Stackup Verifier opens automatically and recommends that you assign the Plane usage type
to that layer. You can then use the Stackup Verifier to edit usage type assignments. See
“Reporting and Correcting Stackup Errors” on page 366.

Setting Up Stackup Properties

Use the Stackup Editor to verify the thickness, lossy, and other material property values for
metal and dielectric layers. For DC drop, you do not have to edit dielectric layer properties. See
“Creating and Editing Stackups” on page 353.

Restrictions: AC power-integrity simulation requires a loss tangent of 0.001 or more and a

metal stackup layer resistivity value of 1e-9 ohms or more. These restrictions do not apply to
DC drop simulation.

Verifying Padstack Properties

Verify the design contains the correct pad shapes, pad sizes, anti-pad sizes, and barrel sizes.

LineSim
Use the PDN Editor to create or verify padstack properties. See “Editing Padstack Properties“.

BoardSim
Board files usually contain padstack information. You may not need to verify padstack
information unless you are investigating unexpected simulation results.

You can verify padstacks by displaying individual vias (that implement specific padstacks) in
the Via Visualizer. See “Viewing Via Properties” on page 1056.

Creating or Verifying Metal Shapes

Create (LineSim) or verify (BoardSim) the metal shapes and connections that form the PDN.
Connections include power-supply pins (current sinks), voltage-regulator module (VRM) pins
(current sources), decoupling capacitor pins, stitching vias, and so on.

LineSim
Use the PDN Editor to define the power-distribution network. See “Adding Symbols to Power-
Distribution Networks”. You can also export power-supply nets from BoardSim to the PDN
Editor. See “Exporting BoardSim Nets to LineSim” on page 1161.

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BoardSim
The board file usually contains the PDN. You may not need to verify metal shapes or
connections unless you are investigating unexpected simulation results. See “Creating
BoardSim Boards”.

Assigning Decoupling Capacitor Models

Verify that decoupling capacitors have the correct values or models. Values you can assign
include capacitance, equivalent series inductance (ESL), and equivalent series resistance (ESR)
values. Models you can assign include SPICE and Touchstone S-parameter.

Whether you assign values or models, indicate whether or not the values or models include the
effects of mounting structures, including vias and trace segments.

Note
Decoupling capacitors connect to a pair of power-supply nets while signal termination
capacitors connect to a signal net and a power-supply net. Power-integrity analysis
ignores capacitors connected to signal nets.

LineSim
Use the PDN Editor to add decoupling capacitor symbols to the power-distribution network.
Verify the decoupling capacitors have the correct values or models, and connect to the PDN
with the correct geometries. See“Add/Edit Decoupling Capacitor(s) Dialog Box” on page 1414.

BoardSim
You can interactively assign decoupling capacitor models to individual components. See Assign
Decoupling-Capacitor Models Dialog Box.

You can use a .QPL automapping file to assign decoupling capacitor models to part names. See
“Format of REF and QPL Files”.

Restriction: The QPL-File Editor does not support decoupling capacitor models, so you use a
text editor to assign them to part names.

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Required Power-Integrity Model Assignments

Table 7-2 shows the required models for power-integrity simulation and some export features.
The following export features run power-integrity simulation: a) export PDN or channel
models, b) export signal via models.
Table 7-2. Required Models for PI Simulation and Exporting PI-Related Models
DC Sink Models AC Source Models VRM Source Models
Bypass Analysis Ignored Ignored Optional
Co-Simulation Ignored Ignored Optional
DC Drop Simulation Required Ignored Required
Decoupling Ignored Ignored Ignored
Analysis—Quick
Decoupling Ignored Ignored Optional
Analysis—Lumped
Decoupling Ignored Ignored Optional
Analysis—Distributed
Export PDN Model Ignored Ignored Optional
Export Signal-Via Ignored Ignored Optional
Model
Plane Noise Analysis Ignored Required Optional

Other considerations:

• Series component models are required when a series component connects the VRM
output pin to the main power-supply net. In BoardSim, see “Assigning Power-Integrity
Models - BoardSim” on page 351. In LineSim, the PDN Editor does not provide a way
to model VRM-related series components.
• Frequency-domain simulations: VRMs (with their low-R DC paths) potentially can
significantly lower PDN impedance at low frequencies. By contrast, a PDN without a
VRM behaves like a simple capacitor at low frequencies.
• Time-domain simulations: VRMs work with the current-source stimulus to avoid
possibly too-high voltage near time zero, due to high impedance at very low frequencies.

Related Topics
“Assigning Power-Integrity Models - BoardSim” on page 351

“Assigning Power-Integrity Models - LineSim” on page 352

“Setting Up Designs for Power-Integrity Simulation” on page 341

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About Power-Integrity Models

About Power-Integrity Models

The library of power-integrity models includes the following types of models:

• Simulation stimulus—Models that provide a current sink (load) or voltage source.

• Reference nets—Nets that provide return current paths.
• Series components—Resistance or inductance of components that “associate” one
power-supply net to another power-supply net.
This topic contains the following:

• “AC Current Sink Models” on page 349

• “DC Current Sink Models” on page 350
• “VRM Voltage Source Models” on page 350
• “Reference Nets” on page 350
• “Series Components for Power-Supply Nets” on page 351

Related Topics
“Required Power-Integrity Model Assignments” on page 348

“Assigning Power-Integrity Models - BoardSim” on page 351

“Assigning Power-Integrity Models - LineSim” on page 352

“Setting Up Designs for Power-Integrity Simulation” on page 341

AC Current Sink Models

AC models apply a current sink waveform to the IC power-supply pin. AC models typically
represent I/O buffer switching and IC core-logic power on/off transitions.

Figure 7-1 shows the electrical model for the current sink. For details about the types of
waveforms and electrical model parameters supported by this model, see “Edit AC Power Pin
Model Dialog Box” on page 1547.

Figure 7-1. Electrical Schematic for an AC Current Sink Model

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DC Current Sink Models

DC models apply a constant current sink to the IC power-supply pin. DC models typically
represent the steady state current consumption of an IC or other component in the design that
draws significant current.

Figure 7-2 shows the electrical model for the current sink. For details about electrical model
parameters, see “Edit DC Power Pin Model Dialog Box” on page 1551.

Figure 7-2. Electrical Schematic for a DC Current Sink Model

VRM Voltage Source Models

Voltage-regulator module (VRM) models provide a voltage source to the IC power-supply pin.
VRM models typically represent the power-supply voltage in the design.

Figure 7-3 shows the electrical model for the voltage source. For details about the electrical
model parameters supported by this model, see “Assign VRM Model Dialog Box” on
page 1470.

Figure 7-3. Electrical Schematic for a VRM Voltage Source Model

Reference Nets
Reference nets provide return-current paths for current sinking into IC power-supply pins.
Reference nets may be implemented across multiple stackup layers, where stitching vias
connect metal areas on different stackup layers.

In LineSim, you specify the reference layer(s) when assigning AC or VRM models.

In BoardSim, you specify the reference net and layer(s) when assigning AC or VRM models,
see “Assign Power Integrity Models Dialog Box - IC Tab” on page 1456 and “Set Reference
Nets Dialog Box” on page 1858. BoardSim automatically finds available reference layers when
you specify the reference net. You can deselect an available reference layer if you know that it
is not well connected by stitching vias to another reference layer.

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Series Components for Power-Supply Nets

Series components connect one power-supply net to another power-supply net. These series
components “associate” power-supply nets in the same way that series components can
associate signal nets. Associated power-supply nets are included in the power-integrity analysis.
See “Associated Nets”.

Figure 7-4 shows how resistors and inductors can associate power-supply nets. Inductor L1
associates nets $435 and $483. Resistor R1 associates nets 1_8V and VCORE.

Figure 7-4. Example Series Components for Power-Supply Nets

Non-resistor/inductor components, such as high-current power FETs, can also associate power-
supply nets.

You assign values to series components in a BoardSim board. You can edit existing series
connection resistance/inductance values, plus you can define series connections through a
resistor package.

Restriction: You cannot model series components for power-supply nets in the PDN Editor.

Assigning Power-Integrity Models - BoardSim

Use the Assign Power Integrity Models Dialog Box - IC Tab to assign power-integrity models
to IC power-supply pins. The types of models you assign depend on the type of power-integrity
simulation you plan to run. Power-integrity models are also required for the types of model-
export features that use power-integrity simulation results. See “Required Power-Integrity
Model Assignments” on page 348.

If the design uses series components, such as an inductor or resistor, to connect one power-
supply net to another power-supply net, use the various Supply-Net tabs in this dialog box to
assign a value to them. These series components associate power-supply nets in the same way

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Assigning Power-Integrity Models - LineSim

that series components associate signal nets, which means the associated power-supply nets are
included in the power-integrity analysis. See “Series Components for Power-Supply Nets” on
page 351 and “Associated Nets”.

Before you begin assigning models or series component values, verify that the key power-
supply nets have been identified. You should identify power-supply nets that connect directly,
or through series components, to IC power-supply pins that you plan to simulate. BoardSim
automatically identifies power-supply nets, but can miss nets with arbitrary names, few pins or
capacitors, and so on. See “How BoardSim Identifies Power-Supply Nets” and “Editing Power-
Supply Nets”.

The BoardSim user session data (.BUD) file contains power-integrity model and value
assignments. The .BUD file is located in the <design> folder. See “About Design Folder
Locations” on page 1391.

Related Topics
“Required Power-Integrity Model Assignments” on page 348

“About Power-Integrity Models” on page 349

“Setting Up Designs for Power-Integrity Simulation” on page 341

“Assign Power Integrity Models Dialog Box - IC Tab” on page 1456

“Assign Power Integrity Models Dialog Box - Supply-Net Resistors Tab” on page 1460

“Assign Power Integrity Models Dialog Box - Supply-Net Inductors Tab” on page 1463

“Assign Power Integrity Models Dialog Box - Other Supply-Net Components Tab” on
page 1466

Assigning Power-Integrity Models - LineSim

You assign power-integrity models at the same time you add symbols to the design in the PDN
Editor. See “Add/Edit IC Power Pin(s) Dialog Box” on page 1421 and “Add/Edit VRM or DC
to DC Converter Dialog Box” on page 1430.

You assign reference nets (planes) when adding symbols supply pins or VRM pins.

Related Topics
“Setting Up Designs for Power-Integrity Simulation” on page 341

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When to Use the Stackup Editor

Chapter 8
Creating and Editing Stackups

Use the Stackup Editor to create, verify, and modify the stackup for the printed circuit board.

This topic contains the following:

• “When to Use the Stackup Editor” on page 353

• “Opening the Stackup Editor” on page 354
• “About Stackups” on page 354
• “About the Stackup Editor User Interface” on page 360
• “Reporting and Correcting Stackup Errors” on page 366
• “Editing Stackups” on page 371
• “Viewing and Planning Impedances and DC Resistances” on page 386
• “Setting Layer Display Options for the Board Viewer in BoardSim” on page 396
• “Documenting Stackups” on page 399

Related Topics
“Exporting and Importing Stackups” on page 1177

“Surface Roughness Dialog Box” on page 1871

When to Use the Stackup Editor

In LineSim, you need to first create a stackup for your schematic with the Stackup Editor if you
plan to do any of the following:

• Model any of the transmission lines in your schematic with the stackup or coupled
stackup methods
• Analyze transmission planes
BoardSim reads your board's stackup from the board file. You might edit your board with the
Stackup Editor for any of the following reasons:

• You just loaded a new board into BoardSim, and the Stackup Verifier reports there were
errors

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Opening the Stackup Editor

• You just loaded a new board into BoardSim; the Stackup Verifier did not report any
errors, but you want to verify that the stackup matches exactly what you expected.
• You want to experiment with a different stackup, since stackup affects trace-segment
and transmission-plane impedance (and buried capacitance) and therefore signal-
integrity and power-integrity results
• You want a reminder of what stackup you are currently using
• You want to print or document your stackup

Opening the Stackup Editor

To open the Stackup Editor:

1. BoardSim or LineSim > Edit Stackup button .

Alternative: Setup menu > Stackup > Edit.
2. If a MultiBoard project is loaded, select the board ID on the Board list on the Stackup
Editor toolbar.

About Stackups
The properties of the metal and dielectric layers arranged in a “stackup” to form the PCB can
have a profound effect on simulation results. This topic describes the relationship between
stackups and simulation, the physical and electrical properties of layers in a stackup, and how
BoardSim/LineSim use stackups.

This topic contains the following:

• “Effect of Stackups on Signals” on page 354

• “Elements of a Stackup” on page 356
• “Stackup Limitations” on page 359
• “How BoardSim Reads Stackups” on page 359
• “How LineSim Uses Stackups” on page 360
• “About the Default Stackup in LineSim” on page 360

Effect of Stackups on Signals

Nearly every detail of a board’s stackup affects two key characteristics of the trace segments on
a board:

• Characteristic impedance (Z0)

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About Stackups

• Propagation velocity
Together, these parameters determine how signals interact with and propagate along the traces
on a board.

Characteristic impedance (or "Z0") is a property unique to the distributed nature of

transmission lines. Because transmission lines consist of a continuous mixture of capacitance
and inductance, they "look" instantaneously to a transmitted signal like a resistance.

Transmission-line impedance affects such behavior as signal reflection and step size (the
percentage of a switching signal’s voltage swing that enters a transmission line).

Propagation velocity specifies how quickly a signal travels along a transmission line.

Propagation velocity determines whether or not a signal trace is likely to exhibit transmission-
line effects. If the total delay time down a trace is short compared to how fast the driving IC
switches, the trace will not behave much like transmission line. If the delay time is long, the
transmission-line effects become significant.

Stackup Parameters That Affect Impedance and Velocity

The following stackup parameters all affect the characteristic impedances and propagation
velocities of the trace segments on a board:

• Layer order
• Trace thickness
• Trace width
While trace width affects characteristic impedance and propagation velocity, it is not
considered by BoardSim to be a "stackup parameter." Rather, trace widths used for
simulation are based on your PCB layout and may vary from trace to trace. To predict
the effect of trace width on the net's characteristic impedance and propagation velocity,
you can specify a test trace width.
See also: “Viewing Characteristic Impedances” on page 387
• Dielectric thickness
• Dielectric constant
• Outer dielectric type (solder mask or substrate types)
• Loss tangent
You can edit all of these parameters in the Stackup Editor. For details about modeling
transmission lines with a stackup in LineSim, see“Edit Transmission Line Dialog Box -
Transmission-Line Type Tab” on page 1573. In BoardSim, the modeling is completely
automatic.

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About Stackups

Elements of a Stackup
"Stackup" refers to how the metal and dielectric layers in a printed circuit board are ordered and
constructed.

The main types of layers in a stackup:

Table 8-1. Types of Stackup Layers

Types Means
“Plane Layers” on page 356 A layer of solid metal, tied to a DC voltage
Or
A layer containing both signal traces and solid metal tied
to a DC voltage
“Signal Layers” on A layer that carries signal traces
page 357
“Dielectric Layers” on A non-conducting layer separating two metal layers or
page 358 coating the board surface, such as solder mask
“Plating Layers” on A plating layer is deposited onto a thicker base metal layer
page 359 on the outside of the stackup

The following sections describe in greater detail the geometric and material properties of
individual stackup layers and of a complete stackup.

Plane Layers
A plane layer can consist of either:

• A solid sheet of metal

• A combination of signal and plane regions
This arrangement is also known as a split/mixed plane layer.

Plane layers, or plane regions within a plane layer, are tied to a DC voltage, such as VCC or
ground. Plane layers function electrically as AC grounds.

Assumption About Plane Layers

The current version of BoardSim/LineSim assumes that a board or stackup-based transmission
line has at least one plane layer that allows for effective ground-return currents for the traces on
the board. "Effective" means that the plane layer provides a low-inductance, close-to-the-trace
return path.

From a practical standpoint, this means that:

• Every board has at least one plane layer

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About Stackups

• Plane layers are solid, not hatched, do not contain copper voids or are otherwise
seriously "broken"
• Plane layers are complete, not partial or mixed significantly with signal traces
BoardSim’s plane viewing capability does not imply that impedance calculations take
non-ideal plane features, such as gaps resulting from copper voids or hatching, into
account.
Use the plane viewing capability to identify portions of the PCB (e.g. specific signals crossing a
ground gap or void) that are likely to cause problems, even if BoardSim itself cannot predict the
details of the problem.

See also: “Viewing Pours and Voids” on page 398

If a plane layer in a stackup is seriously "compromised" in one of these ways, some of

LineSim's/BoardSim’s impedance calculations may be inaccurate.

Plane Layers in LineSim

In LineSim, if you need to model transmission lines that interact with a compromised ground
plane, do not model the lines with the stackup method. For descriptions of alternate modeling
methods, see “Edit Transmission Line Dialog Box - Transmission-Line Type Tab” on
page 1573.

Plane Layers in BoardSim

In BoardSim, another assumption is that plane layers are reported as nets, so they can be
connected to by terminating components and assigned to power-supply voltages.

The assumption that every board has at least one plane layer restricts the current version of
BoardSim from simulating boards that are single-sided or double-sided with no ground plane.
The remaining assumptions about plane layers do not prevent simulation, but may lessen its
accuracy in some cases.

Note: The above restrictions do NOT mean that BoardSim cannot simulate boards with planes
that are not completely perfect. For example, consider a board with a split 5-V/3.3-V power
plane. BoardSim can handle perfectly well any traces that are isolated to one side or the other of
the split (i.e., the 5-V side or 3.3-V side), because the return currents for such traces are never
interrupted by the power-plane gap. Traces that cross the split, on the other hand, may be
problematic, although even they may simulate with sufficient accuracy if enough bypass
capacitors are available in the vicinity of the trace’s crossing of the gap to keep the trace’s return
current from deviating too wildly from the signal current.

Signal Layers
A signal layer is a metal layer that contains signal traces. Vias can connect traces on different
signal layers.

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About Stackups

Signal layers are classified into categories depending on how they are positioned relative to the
plane layers in a stackup. The individual segments on a trace can be in differing categories,
since various segments on a single trace can be on different layers. BoardSim/LineSim
automatically accounts for each signal layer’s cross-section type when it performs impedance
calculations. For a detailed discussion of PCB cross sections, see “Edit Transmission Line
Dialog Box - Transmission-Line Type Tab” on page 1573.

Microstrip
A "microstrip" is a trace segment on a layer with the following characteristics:

• Has a dielectric + a plane layer on one side

• Has only air on the other side
This describes an outer-layer trace on a board. Microstrip traces usually have higher
impedances than traces of other types.

Buried Microstrip
A "buried microstrip" is a trace segment on a layer with the following characteristics:

• Has a dielectric + a plane layer on one side

• Has a dielectric + air on the other side
This describes an inner-layer trace with a plane layer on only one side.

Stripline
A "stripline" is a trace segment on a layer with the following characteristics:

• Has a dielectric + a plane layer on both sides

This describes an inner-layer trace between two plane layers. Stripline traces usually have lower
impedances than traces of other types.

Dielectric Layers
A dielectric layer is a non-conducting material that does one of the following:

• Separates two metal layers (an inner dielectric)

• Coats the board surface (an outer dielectric)
Dielectric layers can be made from a variety of materials, though fiberglass and solder mask are
common in PCBs.

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About Stackups

Dielectric Constants
Associated with every dielectric material is a property called "relative permittivity," or
"dielectric constant." Dielectric constant measures how effective a material is in establishing a
capacitance.

See also: “Table of Dielectric Constants” on page 386

Plating Layers
A plating layer is deposited onto a thicker base metal layer on the outside of the stackup. The
plating layer shields, or passivates, the base metal layer from prolonged exposure to air

Stackup Limitations
Requirement: Stackups must have at least one power plane.

BoardSim/LineSim places several restrictions on plane layers in a stackup, among them that
there must be at least one plane layer per board. This means that you cannot model double-sided
boards (boards with only two signals layers, and no planes).

See also: “Assumption About Plane Layers” on page 356

How BoardSim Reads Stackups

When BoardSim loads your board, it looks for stackup data in the board file.

BoardSim also looks to see if there is a previous session (.BUD, or BoardSim User Data) file for
the board. If so, and if there are stackup edits recorded in the session file, BoardSim
incorporates them into the stackup.

See also: BoardSim Session Files

After the board and session files are read, BoardSim examines the stackup to determine if it is
electrically valid. If not, BoardSim runs the Stackup Verifier to report errors and make
corrections.

See also: “Summary of Reported Stackup Errors” on page 367

The first time you load a new board into BoardSim, it is a good idea to check the stackup, even
if the Stackup Verifier does not report any errors. The stackup in the board file can be
electrically valid but still not match your real stackup.

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About the Stackup Editor User Interface

How LineSim Uses Stackups

LineSim uses a stackup only to accomplish one method of transmission-line modeling: the
"stackup" model type. If you never model transmission lines with this method, you never need
to worry about stackups in LineSim.

On the other hand, the stackup method of modeling transmission lines is powerful, since it
allows you to control the electrical properties of many transmission lines simultaneously by
editing a single, global stackup.

Related Topics
“Edit Transmission Line Dialog Box - Transmission-Line Type Tab” on page 1573

About the Default Stackup in LineSim

When you open a new schematic in LineSim, the schematic comes with a default stackup. This
default stackup has six layers:

• Two outer signal layers, "TOP" and "BOTTOM"

• Two inner plane layers, "VCC" and "GND"
• Two inner signal layers, "InnerSignal1" and "InnerSignal2"
The other parameters of the stackup—dielectric constant, thickness of dielectrics, and metal-
layer thicknesses—are based on default-layer settings you make.

See also: “Setting Default Layer Parameters” on page 381

If the settings you supply for default layers are such that the default stackup would be thinner
than 62.5 mils (still often used as a standard thickness for PCBs), the stackup is automatically
thickened by increasing the thickness of the innermost dielectric layer.

See also: “Editing Stackup Layer Parameters” on page 371

Since the six-layer stackup is only a guess at what you’ll actually be using for your boards,
normally you’ll use LineSim’s Stackup Editor to modify the default stackup to match the one
you actually want to model. This may include adding or deleting layers, changing dielectric
constants, changing thicknesses, and so forth.

About the Stackup Editor User Interface

Use the spreadsheet pane in the Stackup Editor to specify stackup properties. The Stackup
Editor displays a picture of the stackup in the picture pane. If stackup errors exist, they are
reported in the stackup report area.

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About the Stackup Editor User Interface

This topic contains the following:

• “Spreadsheet Pane” on page 361

• “Picture Pane” on page 363
• “Stackup Error Report Area” on page 363
See also: “Creating and Editing Stackups” on page 353

Figure 8-1. GUI Overview for Stackup Editor

Spreadsheet Pane
You can do the following tasks with the spreadsheet pane:

• Edit stackup properties such as layer thickness, material parameters, add/delete layers,
and so on.
See also: “Editing Stackups” on page 371
• View the characteristic impedance and DC resistance for a metal layer.
See also: “Viewing Characteristic Impedances” on page 387, “Calculating DC
Resistance” on page 390

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About the Stackup Editor User Interface

• Calculate the trace width or trace-to-trace separation needed to achieve a specific

characteristic impedance.
See also: “Planning Characteristic Impedances” on page 388
• In BoardSim, use the spreadsheet to control the visibility of metal layers and copper
pour/void shapes in the board viewer.
See also: “Setting Layer Display Options for the Board Viewer in BoardSim” on
page 396
• Select the dielectric/metal measurement unit and the metal thickness type.
See also: “Setting Measurement Units” on page 401
The spreadsheet has five tabs representing the following specialized views of the stackup data:

Basic—Use this tab to enter the basic set of stackup layer information, set measurement
units and metal thickness type, and to view the characteristic impedance for a test width.
In BoardSim, you can use this tab to control how to display traces and plane layers in the
board viewer.
• Dielectric—Use this tab to enter information for dielectric layers. Dielectric
information includes technology (prepreg or core), loss tangent (for lossy transmission
line simulation), the dielectric constant measurement frequency, and whether to
calculate the dielectric constant and loss tangent for the metal layer from surrounding
dielectric layers.
• Metal—Use this tab to enter information for metal layers, including whether to
calculate the dielectric constant for the metal layer from surrounding dielectric layers, or
enter a custom dielectric constant.
• Z0 Planning—Use this tab to calculate the optimal physical data when you supply the
target impedance for the single trace or for the differential traces. This feature makes
planning for controlled-impedance PCBs easy and fast.
• Custom View—Use this tab to display any combination of columns from the other four
tabs.
See also: “Configuring the Custom View Tab” on page 366
To modify the spreadsheet, you can do any of the following:

• To edit an individual cell, click in the cell and backspace over the existing value and
type in the new value.
Alternative: Select a new value from the list.
• Use standard Windows keyboard shortcuts to copy (Ctrl+C), cut (Ctrl+X), and paste
(Ctrl+V) data among individual spreadsheet cells.

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• Use standard Windows keyboard shortcuts to undo (Ctrl+Z) or redo (Ctrl+Y)

spreadsheet edits.
See also: “Undoing and Redoing Edits” on page 364
• To copy data to multiple cells in the same spreadsheet column, see “Copying Data to
Multiple Cells in the Same Column” on page 364 and “Selecting or Deselecting Layers
in the Spreadsheet” on page 364.

Picture Pane
Display the stackup layers in a proportional scale or in a constant scale in the picture pane. To
visually check the layer thickness data for gross errors, select Draw proportionally on the
picture pane. In addition, you can do the following:

• Change layer order by dragging the layer to a new location.

• Use standard Windows keyboard shortcuts to undo (Ctrl+Z) or redo (Ctrl+Y) picture
pane edits.
See also: “Undoing and Redoing Edits” on page 364
• Select a spreadsheet row by double-clicking its layer in the picture pane.

Stackup Error Report Area

The stackup verifier writes its report to this area.

See also: “Stackup Error Reporting - Stackup Editor” on page 369

Resizing and Rearranging the Dialog Box

Using standard Windows mouse drag operations, you can resize the Stackup Editor dialog box
and change the relative sizes of the Spreadsheet Pane and the Stackup Picture Pane.

You can arrange the spreadsheet and picture panes to be side-by-side (split Stackup Editor
dialog box vertically) or to be top-and-bottom (split Stackup Editor dialog box horizontally).

To change the pane split orientation:

• Split window vertically button or Split window horizontally button .

Alternative: View menu > Split > Vertical or Horizontal.

Related Topics
“Creating and Editing Stackups” on page 353

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About the Stackup Editor User Interface

Undoing and Redoing Edits

You can undo or redo multiple levels of edits in the spreadsheet or picture pane (for example,
changing layer order).

To undo an edit:

• Press Ctrl+Z.
Or
Undo previous command button .
To redo an edit:

• Press Ctrl+Y.
Or
Redo undone command button .

Copying Data to Multiple Cells in the Same Column

In the spreadsheet, you can copy data from one cell to multiple cells in the same column. You
first select the destination layers, point to the cell containing the data you want to copy, and then
paste the data to the cells on the destination layers.

To copy data to multiple cells in the same column:

1. Select the layers into which you want to paste data.

See also: “Selecting or Deselecting Layers in the Spreadsheet” on page 364
2. Right-click over the cell containing the data to copy, and then click Apply to Selection.
Result: The data is copied to the cells in the same column for the selected layers and the
layers remain selected.
3. Repeat step 2 as needed for other cells.

Selecting or Deselecting Layers in the Spreadsheet

You can select or deselect an individual layer by clicking the first column cell for the layer. The
Stackup Editor also offers functions to select or deselect groups of layers, such as "select all
dielectric layers" and "deselect all selected layers."

Finally, the Stackup Editor has a "persistent layer selection" function that allows a layer to
remain selected until you deselect it. This function is very similar to the Windows Ctrl+Click
function, except the selected layer remains selected if you click in the first column cell for a
layer.

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To enable the persistent layer selection function:

• Keep selections on during editing operations button .

Alternative: View menu > Keep Selection "On" During Edit.

Common Layer Selection and Deselection Tasks

Table 8-2 shows how to perform several common layer selection and deselection tasks:

Table 8-2. Common Layer Selection and Deselection Tasks

Task Steps to perform
Select one layer Click in the first column cell for the layer

Alternative: Double-click the row in the spreadsheet

pane.
Select all metal layers Select all metal layers button

Alternative: View menu > Select Metal.

Select all dielectric layers Select all dielectric layers button

Alternative: View menu > Select Dielectric.

Select all layers Select all layers button

Alternative: View menu > Select All

Select non-adjacent layers If persistent selection is enabled, click in the first column
cell for each layer

Or

If persistent selection is disabled, press Ctrl+Click over

the first column cell for each layer
Select a block of adjacent layers Click in the first column cell for the start layer, and then
press Shift+Click in the first column cell for the end layer

Alternative: Drag from the first column cell for the start
layer to the first column cell for end layer
Deselect all layers Deselect selected layers button
Alternative: View menu > Clear Selection

Or

If persistent selection is disabled, click in any cell that is

not in a selected layer

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Reporting and Correcting Stackup Errors

Table 8-2. Common Layer Selection and Deselection Tasks (cont.)

Deselect one layer Press Ctrl+Click in the first column cell for the layer to
deselect

Configuring the Custom View Tab

The Custom View tab can contain any set of columns from the other spreadsheet tabs, and it can
display the columns in any order. This capability enables you to create a Custom View tab
containing exactly the information you need.

Restriction: Some columns are available only if you have licensed the appropriate option.

To configure the Custom View tab:

1. In the Custom View tab, click Customize.

2. Do any of the following:
• To hide a column, select the check box for the column name.
• To display a column, clear the check box for the column name.
3. To change the column order, select a column name in the Columns list, and then click
the up and down arrows as needed. The top column in the Columns area is displayed at
the left side of the spreadsheet.
4. Repeat steps 2-3 as needed.
5. Click OK.

Reporting and Correcting Stackup Errors

The following features provide independent ways to report and correct stackup errors:

• Stackup Editor—Reports stackup errors when you edit the stackup. You can use the
Stackup Editor to edit all stackup properties.
• Stackup Verifier—Reports stackup errors when you open the BoardSim board or when
you manually open it. You can use the Stackup Verifier to assign the plane or signal
layer type to metal stackup layers, but not to edit other stackup properties.
This topic contains the following:

• “Summary of Reported Stackup Errors” on page 367

• “Stackup Error Reporting - Stackup Editor” on page 369
• “Stackup Error Reporting - Stackup Verifier” on page 370

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Reporting and Correcting Stackup Errors

Summary of Reported Stackup Errors

Although this topic applies to both LineSim and BoardSim, only BoardSim is mentioned. This
is because in LineSim, the Stackup Editor prevents most of the errors described in this section
from happening in the first place. See “Stackup Error Reporting - Stackup Editor” on page 369.

By contrast, the .HYP file created by PCB design system translators may contain incorrect
stackup-related properties or may be missing stackup-related properties.

The Stackup Editor and Stackup Verifier report mostly the same set of stackup errors. The main
exception is that the Stackup Verifier additionally reports the overall metal usage on plane and
signal layers, to help you identify plane layers that provide return current.

This topic contains the following:

• “No Stackup at All” on page 367

• “Missing Layers” on page 368
• “Zero Thicknesses” on page 368
• “Zero Dielectric Constants” on page 369
• “Negative Dielectric Loss Tangent” on page 369
• “Negative Metal Layer Resistivity” on page 369
• “Metal Usage Threshold Exceeded for Signal Layer” on page 369

No Stackup at All
The most obvious deficiency in a board file’s stackup is having no stackup at all. This is not
uncommon because some PCB-layout tools do not carry or use stackup information.

When the stackup is completely missing, the Stackup Verifier attempts to synthesize one when
you open the board. Since it is unlikely that the synthesized stackup matches your real stackup
exactly, you should run the Stackup Editor and make any required changes.

If there is no stackup at all in the board or session (.BUD) files, the Stackup Verifier takes the
following steps:

1. Creates signal layers for all the layers on which there are trace segments.
2. Separates the signal layers with dielectric layers.
3. Sets signal-layer thicknesses to a default thickness.
4. Sets dielectric thicknesses and constants to default values.
5. Warns you that there is still no plane layer.

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Reporting and Correcting Stackup Errors

Missing Layers

Missing Signal Layers

If there is no stackup in the board or session (.BUD) files, BoardSim automatically records the
layers of all the trace segments on the board, and adds the layers to the stackup. Therefore, there
should never be any signal layers missing from the stackup.

Synthesized (that is, automatically created) signal layers are given a BoardSim-created layer
name.

BoardSim automatically reports signal layers that are used by at least one trace segment
somewhere in the board file. If you think a signal layer is missing, consider whether it is
actually used by a routed trace on your board. If not, it does not need to be included in your
BoardSim stackup.

Missing Plane Layers

The Stackup Verifier reports a board that has no plane layers, and reports an error. BoardSim
requires every board to have at least one plane layer.

Since the Stackup Verifier has no idea where the missing plane goes in the stackup, and since
the positioning of plane layers is so critical to trace impedance (for signal-integrity simulation)
and transmission planes (for power-integrity simulation), it does not automatically insert a
plane. Use the Stackup Editor to add plane layers.

If the metal usage on a signal layer exceeds a threshold (that you set), the Stackup Verifier
opens when you load the board, so you can review the metal usage for each metal layer. You
can then assign the plane layer type to every metal layer that provides return current.

Missing Dielectric Layers

The Stackup Verifier reports metal layers that are shorted together because there is no dielectric
between them, and reports the condition.

The Stackup Verifier automatically adds a dielectric layer between shorted metal layers.
Synthesized dielectric layers are given a default thickness and dielectric constant.

It is possible for a dielectric layer to be missing because it is out-of-order in the board-file

stackup. The synthesized layer will then be redundant; use the Stackup Editor to delete the
synthesized layer and move the real one.

Zero Thicknesses
The Stackup Verifier reports layers (signal, plane, and dielectric) that have zero or missing
thicknesses. BoardSim requires every layer to have a non-zero thickness.

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The Verifier automatically changes zero thicknesses to a default thickness. (The default
thickness differs for metal and dielectric layers.)

Zero Dielectric Constants

The Stackup Verifier reports dielectric layers that have zero or missing dielectric constants.
BoardSim requires every dielectric to have a non-zero dielectric constant.

The Verifier automatically changes zero dielectric constants to a default constant.

Negative Dielectric Loss Tangent

The Stackup Verifier reports dielectric layers that have negative or missing loss tangent values.
BoardSim requires every dielectric to have non-negative loss tangent values.

Negative Metal Layer Resistivity

The Stackup Verifier reports metal layers that have negative bulk resistivity values. Boardsim
requires every metal layer to have non-negative metal bulk resistivity values.

Metal Usage Threshold Exceeded for Signal Layer

The field solver in signal-integrity simulations uses only metal layers assigned to the plane type.
If there are no plane layers in the design, HyperLynx assumes that a distant ground plane exists,
which enables simulation but can decrease accuracy.

Use the spreadsheet in the Stackup Verifier to assign the plane type to metal layers that provide
return currents and AC grounds.

Restriction: When you open Stackup Verifier with LineSim, it does not report metal usage and
you cannot use it to assign plane/signal usage types to metal layers.

Stackup Error Reporting - Stackup Editor

If there are currently any errors in the stackup, or if an editing change you make to the stackup
causes an error, the Stackup Editor reports the error immediately. Errors appear near the bottom
of the picture pane of the Stackup Editor dialog box. Errors are reported in a red font.

If there are no errors, that is, the stackup is electrically valid, the status line changes to a black
font and reports "no errors in stackup."

If there are multiple errors simultaneously, the status line reports them one-at-a-time. Continue
fixing the indicated errors until the status line reports no errors.

Watch the status line as you edit a stackup. The status messages tell you immediately if an
editing change has made the stackup invalid.

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Reporting and Correcting Stackup Errors

Stackup Error Reporting - Stackup Verifier

Use the Stackup Verifier dialog box to view stackup error and per-layer metal usage
information. You can also use this dialog box to assign plane/signal types to metal layers.

The appearance and contents of the dialog box depends on whether it displays stackup error
information, metal usage information, advanced metal usage settings, or all at the same time.

To open the Stackup Verifier:

• Open a board in BoardSim.

The Stackup Verifier automatically opens when you open the board with a stackup error
or if the currently-assigned metal layer type does not match the recommended metal
layer type. See “Summary of Reported Stackup Errors” on page 367.
To disable these checks when you open this particular board, clear the Check every
time .HYP file is loaded or Don’t ask me again check box (whichever is displayed) in
the Stackup Verifier dialog box. This setting is saved in the <design>.PJH file for the
currently-loaded board. The .PJH file is stored in the <design> folder. See “Set
Directories Dialog Box” on page 1854.
• Setup menu > Stackup > Check.
To assign plane/signal types to metal layers:

1. If a MultiBoard project is loaded, select the board ID from the Board list. See “About
Board IDs“.
2. Click the Final spreadsheet cell, and select Signal or Plane.
To set metal usage and void area thresholds in BoardSim:

1. Click Advanced .
2. To edit the metal usage threshold, drag the slider in the Preferences area.
When the metal usage exceeds this value and the layer type assignment is “Signal”, the
color of text in the Recommended cell changes to red.
The field solver in signal-integrity simulations uses only metal layers assigned to the
plane type. If there are no plane layers in the design, HyperLynx assumes that a distant
ground plane exists, which enables simulation but can decrease accuracy.
3. To exclude voids less than a certain area from metal usage calculations, type the area in
the Maximum Ignored Void Size box.
Power-integrity simulations also ignore voids and pours that are smaller than a certain
area, so this option enables you to fine tune how the metal usage is calculated. See the
geometric resolution section in the “Preferences Dialog Box - Power Integrity Tab” on
page 1829 topic.

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Editing Stackups

Related Topics
“Reporting and Correcting Stackup Errors” on page 366

Editing Stackups
Use the Stackup Editor to edit the properties of individual stackup layers and to edit the quantity
or sequence of layers in the stackup.

This topic contains the following:

• “Editing Stackup Layer Parameters” on page 371

• “Copying Stackup Parameters from Other Designs” on page 380
• “Setting Default Layer Parameters” on page 381
• “Adding Layers” on page 381
• “Changing Layer Order” on page 383
• “Deleting Layers” on page 384
• “Changing a Layer From One Type to Another” on page 385

Related Topics
• “Total Board Thickness” on page 385
• “About Field Solver Messages” on page 385
• “Table of Dielectric Constants” on page 386

Editing Stackup Layer Parameters

Use the spreadsheet to edit layer parameters. To display the layer parameter you want to edit,
click the Basic, Dielectric, or Metal tab as needed. Generally, you change a layer parameter in a
spreadsheet cell by typing a new value or by selecting a new value from a list.

This topic contains the following:

• “Dielectric Layer Parameters” on page 372

• “Plane or Signal Layer Parameters” on page 374
• “Calculated Dielectric Permittivity and Loss Tangent for Metal Layers” on page 377
See also: “About the Stackup Editor User Interface” on page 360

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Dielectric Layer Parameters

A dielectric layer has the following parameters:

• “Thickness and Dielectric Constant” on page 372

• “Dielectric Layer Name” on page 372
• “Usage Parameter for Dielectric Layers” on page 372
• “Technology” on page 373
• “Loss Tangent” on page 374
• “Thermal Conductivity” on page 377

Thickness and Dielectric Constant

For BoardSim/LineSim to simulate, the dielectric layer must have a non-zero thickness and a
non-zero dielectric constant. You can display the thickness in various units.

See also: “Setting Measurement Units” on page 401, “Table of Dielectric Constants” on
page 386

The Er frequency box displays the recommended frequency used to measure the dielectric
constant, or Er, of the dielectric material. When you look up the dielectric constant in a
dielectric-materials datasheet, use the value that best corresponds to the frequency displayed in
the Er frequency box, down to 1 MHz.

Dielectric Layer Name

When creating stackups, avoid using layer names that contain parentheses ( ) or curly braces {
}. These characters are used as delimiters in the stackup section of LineSim’s .FFS or .TLN file
and BoardSim's .HYP and .BUD files. Names containing the delimiter characters may cause the
files to be read incorrectly.

See also: “Layer Names in LineSim” on page 375, “Layer Names in BoardSim” on page 375

Usage Parameter for Dielectric Layers

The usage parameter indicates whether the dielectric layer is implemented as a substrate or as a
solder mask. For an example stackup that uses the substrate and solder mask usage types, see
Figure 8-2.

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Figure 8-2. Example Stackup with Substrate and Solder Mask Dielectric Layers

The outer dielectric layer extends to the inner surface of the outer signal layer (if any). For
example, in Figure 8-2, the solder mask extends to the bottom of the top signal layer.

Inner dielectric layers are always implemented as a substrate type. However the outer dielectric
layers used to coat the board can be implemented as a substrate type or a solder mask type. See
the following descriptions:

• Substrate layers have a flat surface profile, even when they cover underlying profiles
such as signal traces or components. To maintain the flat surface, a substrate layer has a
variable thickness and a thinner cross-section where it covers high spots on the board.
Substrate dielectric layers are usually thicker overall than a solder mask dielectric layer,
even at the thinnest cross-section.
• Solder mask layers tend to have a bumpy surface profile because they have a relatively
uniform thickness, even when they cover high spots on the board, such as signal traces.
Solder mask is also known as "conformal coating" or "SMOBC" (solder mask over bare
copper).

Technology
The technology parameter indicates whether the dielectric layer material is rigid or soft when
PCB layers are initially put together.

Note
The Stackup Editor does not use values from the Technology column, which is available
only for you to document the stackup.

• Core materials are rigid and typically serve as the backbone, or foundation, of the PCB
during fabrication.
• Prepreg materials are semi-soft and must be baked to become rigid. Signal traces can
sink a little into prepreg dielectric layers prior to baking. This changes the distance from
the signal traces on prepreg layers to metal on adjacent core layers.

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Loss Tangent
If your PCB has high-speed signals, or has signals that propagate over very long or very narrow
conductors, you can improve PCB modeling by specifying the dielectric material's loss tangent
parameter. With loss tangent information, the simulator is better able to predict frequency-
dependent transmission line losses.

Restriction: This column is available only if you have licensed the appropriate option.

Thermal Conductivity - Dielectric

You can type the thermal conductivity value into the Thermal Conductivity cell. The Dielectric
and Metal tabs display this column.

The Metric unit is W/m-C—Watts / (meter * degrees Celsius)

The English unit is Btu/hrftF—British Thermal Units / (hour * feet * degrees Fahrenheit)

The default value for dielectric layers applies to FR-4. The default value for metal layers applies
to copper. Changing the dielectric technology or metal material does not automatically update
the value of this cell.

Note: HyperLynx Thermal and other high-speed analysis products do not use the thermal
conductivity values in the Stackup Editor.

Plane or Signal Layer Parameters

A metal layer has the following parameters:

• “Thickness” on page 375

• “Layer Name” on page 375
• “Usage Parameter for Metal Layers” on page 375
• “Metal” on page 376
• “Bulk Resistivity” on page 376
This is an advanced parameter that you do not normally need to change.
• “Temperature Coefficient” on page 376
This is an advanced parameter that you do not normally need to change.
• “Dielectric Constant” on page 376
• “Loss Tangent” on page 377

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Thickness
For BoardSim/LineSim to simulate, a non-zero thickness is required for every signal or plane
layer. Thickness can be displayed in either English or metric units, and in length or weight units;
see “Setting Measurement Units” on page 401 for details.

If your PCB manufacturer uses plating for outer metal layers, you must add a plating layer to the
outside of the outer metal layers.

Layer Name
When creating stackups, avoid using layer names that contain parentheses ( ) or curly braces {
}. These characters are used as delimiters in the stackup section of LineSim’s .FFS or .TLN file
and BoardSim's .HYP and .BUD files. Names containing the delimiter characters may cause the
files to be read incorrectly.

Layer Names in LineSim

For a signal or plane layer, you can enter a layer name only before the layer has had a
transmission line in the schematic placed on it with the stackup modeling method. For details on
stackup modeling of transmission lines, see “Edit Transmission Line Dialog Box -
Transmission-Line Type Tab” on page 1573. Once a transmission line somewhere in the
schematic has been assigned to a layer, the layer’s name can no longer be edited.

This is true even if the assigned transmission line has subsequently been assigned to another
layer or modeling method, or removed from the schematic. Therefore, you should name all of
your layers before assigning any transmission lines to them.

Layer Names in BoardSim

For a signal or plane layer, you can enter a layer name only if the layer does not contain any
signal routing. If the layer does contain routing, you cannot edit the layer name. This occurs
because the layer name is recorded in the session (.BUD) file and the layer name must be the
same in both the session and board files.

Usage Parameter for Metal Layers

The usage parameter indicates one of the following metal layer types:

• Signal
• Plane
• Plating
See also: “Elements of a Stackup” on page 356

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Metal
The metal parameter indicates the material used to implement the metal layer. You can select a
standard material or a custom material. If you select a standard material, the spreadsheet
automatically supplies its bulk resistivity and temperature coefficient values. If you select a
custom material, you manually set the bulk resistivity and temperature coefficient values.

Tip: If you change the Metal parameter from a standard metal type, such as Copper, to
<Custom> and do not change either the Bulk Resistivity or Temperature Coefficient
value, the Metal parameter resets to the original standard metal type when you close and
reopen the Stackup Editor. This behavior happens because the Stackup Editor does not
explicitly save the Metal parameter from the spreadsheet. Instead it tries to map the Bulk
Resistivity or Temperature Coefficient values to a standard metal type. The Stackup
Editor retains the <Custom> Metal parameter only when the combination of Bulk
Resistivity or Temperature Coefficient values fails to map to a standard metal type.

Bulk Resistivity
Every signal and plane layer is required to have a bulk resistivity for the layer’s metal material.
The resistivity is used when BoardSim/LineSim calculates DC resistances for trace segments on
the layer.

Bulk resistivity is considered to be an advanced parameter, that is, one that you normally do not
need to change. Signal and plane layers automatically default to the bulk resistivity of the metal
selected in the Metal column. To edit the bulk resistivity, set the Metal parameter to <Custom>.

See also: “Calculating DC Resistance” on page 390

Temperature Coefficient
Every signal and plane layer is required to have a resistivity temperature coefficient for the
layer’s metal material. The temperature coefficient is used in conjunction with the layer’s bulk
resistivity when BoardSim/LineSim calculates DC resistances for trace segments on the layer.

Temperature coefficient is considered to be an advanced parameter, that is, one that you
normally do not need to change. Signal and plane layers automatically default to the
temperature coefficient of the metal selected in the Metal column. To edit the temperature
coefficient, set the Metal parameter to <Custom>.

See also: “Calculating DC Resistance” on page 390

Dielectric Constant
You can type the Er value into the Er cell, or select Calculate Er for metal layers from
surrounding dielectrics (this check box controls automatic calculation for both Er and Loss
Tangent columns).

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To display the calculated values, enable the Calculate Er for metal layers from surrounding
dielectrics option (which displays <Auto> in the Er and Loss Tangent spreadsheet cells for
metal layers) and then disable the option.

For information about how the stackup editor calculates Er, see “Calculated Dielectric
Permittivity and Loss Tangent for Metal Layers” on page 377.

Loss Tangent
You can type the loss tangent value into the Loss Tangent cell, or select Calculate Er for metal
layers from surrounding dielectrics (this check box controls automatic calculation for both Er
and Loss Tangent columns).

To display the calculated values, enable the Calculate Er for metal layers from surrounding
dielectrics option (which displays <Auto> in the Er and Loss Tangent spreadsheet cells for
metal layers) and then disable the option.

For information about how the stackup editor calculates loss tangent, see “Calculated Dielectric
Permittivity and Loss Tangent for Metal Layers” on page 377.

The Loss Tangent column is displayed only on the Dielectric tab. The Er column is displayed on
the Metal tab because it can affect the value in the Z0 column. Loss tangent does not affect Z0,
and so Loss Tangent is not displayed on the Metal tab.

Thermal Conductivity
You can type the thermal conductivity value into the Thermal Conductivity cell. The Dielectric
and Metal tabs display this column.

The Metric unit is W/m-C—Watts / (meter * degrees Celsius)

The English unit is Btu/hrftF—British Thermal Units / (hour * feet * degrees Fahrenheit)

The default value for dielectric layers applies to FR-4. The default value for metal layers applies
to copper. Changing the dielectric technology or metal material does not automatically update
the value of this cell.

Note: HyperLynx Thermal and other high-speed analysis products do not use the thermal
conductivity values in the Stackup Editor.

Calculated Dielectric Permittivity and Loss Tangent for Metal

Layers
Most PCB layout tools do not provide dielectric permittivity (Er from now on) and loss tangent
values for metal layers, but the field solver used by the Stackup Editor requires Er to calculate
electrical properties (such as Z0).

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Editing Stackups

You can have the Stackup Editor automatically calculate the values by enabling the Calculate
Er for metal layers from surrounding dielectrics option on the Dielectric or Metal tabs. To
display the calculated values, enable the option (which displays <Auto> in the Er and Loss
Tangent spreadsheet cells for metal layers) and then disable the option.

The Stackup Editor uses the following algorithm to calculate dielectric permittivity and loss
tangent for metal layers:

1. If the metal layer is an outer layer, then assign Er = 1 and loss tangent = 0 (which are the
values for air).

2. If the metal layer is adjacent to a dielectric layer with an Er of 1, then assign Er = 1 and
loss tangent = 0.

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3. If the metal layer is adjacent to a dielectric layer with the Solder Mask usage value, then
copy the Er and loss tangent values from the adjacent dielectric layer with the Solder
Mask usage value.

4. If the metal layer is adjacent to dielectric layers on both sides, these dielectric layers are
adjacent to more layers (let us call them adjacent_plus_one layers), and one of the
adjacent_plus_one layers is a dielectric layer with an Er of 1, then copy the Er and loss
tangent values from the adjacent layer that is adjacent to the dielectric layer with an Er
of 1.

5. For inner metal layers that are not described by conditions 1-4, then use the following
formulas to calculate the Er and loss tangent values:
• Er
((Er layer_above * thickness layer_above) + (Er layer_below * thickness layer_below)) /

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(thickness layer_above + thickness layer_below)

• Loss tangent
((Loss tangent layer_above * thickness layer_above) +
(Loss tangent layer_below * thickness layer_below)) /
(thickness layer_above + thickness layer_below)

Note
When calculating Er and dielectric constant values for inner metal layers, the Stackup
Editor uses the average value for the adjacent dielectric layers. Even though metal traces
placed on substrate or core dielectric layers will sink slightly into the adjacent prepreg
layer (which is semi-soft prior to baking), the core layer may not be completely planar
after board pressing and may recede a little in areas with traces.

The Stackup Editor does not use values from the Technology column, which is available
only for you to document the stackup.

Copying Stackup Parameters from Other Designs

You can use the Windows clipboard to quickly copy stackup parameters from one design to
another. This capability enables you to reuse stackups. For example, if you create a new
LineSim schematic, you can replace the default stackup with the stackup from a BoardSim
board or another LineSim schematic.

To copy stackup parameters from another design:

1. Open the design that provides the stackup parameters to copy, and then open the
Stackup Editor.
2. Select the stackup layers with the parameters you want to copy and press Ctrl+C.
3. Open the design that receives the copied stackup parameters, and then open the Stackup
Editor.

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You can open a second copy of HyperLynx to open the board or schematic to receive the
copied stackup parameters, or you can close the current design and then open the board
or schematic to receive the copied stackup parameters.
4. Do any of the following;
• To replace all the stackup layers, select all the layers and press Ctrl+V.
• To replace some of the stackup layers, select the layers to replace and press Ctrl+V.
Result: Copied layers are inserted at the location of the first selected layer.

Adding Layers
Use the spreadsheet to add new layers to the stackup. The new layers use default properties
taken from the Preferences dialog box.

This topic contains the following:

• “Setting Default Layer Parameters” on page 381

• “Adding Dielectric Layers” on page 382
• “Adding Plane Layers” on page 382
• “Adding Signal Layers” on page 382
• “Adding the Most-Suitable Layer” on page 383
See also: “Editing Stackup Layer Parameters” on page 371

Setting Default Layer Parameters

As you edit a stackup and add layers to it, BoardSim/LineSim applies default parameter values
to the new layers (e.g., for thickness or dielectric constant). You can edit these values after the
layer is added, but sometimes it is more convenient to define what default values you want the
program to use for new layers — doing so may save your having to edit multiple, individual
layers.

To set default stackup-layer parameter values:

1. Setup menu > Options > General > Default Stackup tab.
2. Type the desired default parameter values.
3. Click OK.
Result: When you create a new layer in the Stackup Editor, it has the parameters you
just specified.

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Editing Stackups

Adding Dielectric Layers

To add a dielectric layer:

1. If any layers are currently selected, click Deselect selected layers on the toolbar.
2. Click in the first column for the layer at which you want to add a dielectric layer.
3. Right-click over the layer, click Insert Above or Insert Below, and then click one of the
following:
• Substrate
• Solder Mask—Available only for dielectric layers on the outside of the stackup.
See also: “Table of Dielectric Constants” on page 386

Adding Plane Layers

To add a plane layer:

1. If any layers are currently selected, click Deselect selected layers on the toolbar.
2. Click in the first column for the layer at which you want to add a plane layer.
3. Right-click over the layer, click Insert Above or Insert Below, and then click Plane.
If you selected a metal layer, so that the new plane would have been shorted to it, a new
dielectric layer is automatically added between the metal layer and the new plane. The new
dielectric layer is given a default thickness and dielectric constant.

The new plane layer is given a default thickness; you can change this default value.

See also: “Editing Stackup Layer Parameters” on page 371, “Setting Default Layer Parameters”
on page 381

Adding Signal Layers

Signal layers are automatically recorded when the .HYP file is loaded: BoardSim records the
layers of all the trace segments on the board. Therefore, there should never be any signal layers
missing from the stackup that involve routed traces on your board.

See also: “Summary of Reported Stackup Errors” on page 367

However, you can use the Stackup Editor to add signal layers to document a layer you plan to
add in a future board revision or to see how a new signal layer would affect trace impedances.

To add a signal layer:

1. If any layers are currently selected, click Deselect selected layers on the toolbar.

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2. Click in the first column for the layer at which you want to add a signal layer.
3. Right-click over the layer, click Insert Above or Insert Below, and then click the layer
type.
If you selected a metal layer, so that the new signal layer would have been shorted to it, a new
dielectric layer is automatically added between the metal layer and the new signal layer. The
new dielectric layer is given a default thickness and dielectric constant.

The new plane layer is given a default thickness; you can change this default value.

See also: “Editing Stackup Layer Parameters” on page 371, “Setting Default Layer Parameters”
on page 381

Adding the Most-Suitable Layer

To have BoardSim/LineSim select and add the most-suitable layer:

1. If any layers are currently selected, click Deselect selected layers on the toolbar.
2. Click in the first column for the layer at which you want to add a dielectric layer.
3. Right-click over the layer, click Insert Above or Insert Below, and then click Most
Suitable. The Stackup Editor selects an appropriate layer type.
Alternative: On the toolbar, click Insert the most suitable layer above the selected layer
button or Insert the most suitable layer below the selected layer button .

Changing Layer Order

You can change layer order using the picture pane or using the spreadsheet.

To change the order of a stackup’s layers using the picture pane:

• In the picture pane area, drag the layer to the new location.
To change the order of a stackup’s layers using the spreadsheet:

1. If any layers are currently selected, click Deselect selected layers on the toolbar.
2. Click in the first column for the layer you want to move, and then release the mouse
button. If you drag the pointer to another layer before releasing the mouse button, you
select additional adjacent layers instead of moving the layer.
3. Drag the selected layer to its new location. As you drag the layer, a red horizontal line
appears. When you release the mouse button, the layer is moved to the layer above the
red horizontal line.
Restriction: If the design has partial vias, the Stackup Editor prevents you from dragging signal
layers to locations that break the connectivity among signal layers used by partial vias.

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Editing Stackups

If you move a solder mask outer dielectric layer to an inner location in the stackup, its type
automatically changes to substrate but its thickness and dielectric values are unchanged.
Because solder mask dielectric layers tend to be much thinner and have a somewhat lower
dielectric constant value, you may want to review the moved layer's properties. See “Editing
Stackup Layer Parameters” on page 371.

If you move an outer plating layer to an inner location in the stackup, its type automatically
changes to signal but its thickness is unchanged.

Deleting Layers
Use the spreadsheet to delete stackup layers. You can cut a layer, which is copied to the
Windows clipboard, or you can delete a layer, which is not copied to the Windows clipboard.

To cut or delete a layer:

1. If any layers are currently selected, click Deselect selected layers on the toolbar.
2. Click in the first column for the layer you want to delete.
Or
Select multiple layers.
See also: “Selecting or Deselecting Layers in the Spreadsheet” on page 364
3. Right-click over the layer and click Cut.
Alternative: Cut to clipboard .

Cannot Delete Signal Layers with Routing

The exact rules about deleting signal layers depend on whether you use BoardSim or LineSim.

Deleting Signal Layers in BoardSim

The Stackup Editor does not allow you to delete signal layers that have routed traces on them.
Deleting a routed signal layer would invalidate simulation for many nets or transmission lines.

You can delete completely unrouted signal layers in your stackup; these could be either
unrouted layers that came in from your PCB-layout tool or new signal layers that you added in
the Stackup Editor.

Deleting Signal Layers in LineSim

The Stackup Editor does not allow you to delete signal layers that have transmission lines on
them. Deleting such a layer would invalidate your schematic for simulation.

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You can delete a signal layer if you first move the transmission lines on that layer to other
layers, or if you remove the transmission lines on that layer from the schematic.

Changing a Layer From One Type to Another

Planes With Signal Routing
If your board has a plane layer that contains some trace routing, BoardSim will incorrectly
identify the layer as a signal layer, rather than a plane. This will result in the wrong impedances
being calculated for the surrounding signal layers. For this reason, the Stackup Editor allows
you to change a signal layer’s type to "plane."

Restriction: The only layer-type change that BoardSim does not allow is from signal to
dielectric, for signal layers that have routed traces. This change would effectively delete many
routed traces from the board.

Changing a Layer Type

To change a layer from one type to another:

1. In the spreadsheet, click the Dielectric or Metal tab.

2. Click in the Usage cell for the layer you want to change to display the list, and then click
the new type.

Total Board Thickness

The Stackup Editor displays the total thickness of your stackup in the picture pane, below the
stackup image. As you edit the stackup, the total thickness changes.

Total thickness may affect the manufacturability of your board. For example, 62 mils is a
standard thickness for many fabricators. Thick boards often increase drilling cost because fewer
panels at-a-time can be drilled. On the other hand, an extra-thick board is often used for
backplane applications because of the improved rigidity.

About Field Solver Messages

When you finish editing a stackup, such as making changes and then closing the Stackup Editor,
BoardSim/LineSim briefly calls its field solver to characterize certain aspects of the new
stackup. Often, you will see a progress dialog box labeled "HyperLynx" and "Running field
solver" while this analysis is running.

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Viewing and Planning Impedances and DC Resistances

Table of Dielectric Constants

Table 8-3 lists dielectric constants (relative permittivities), for several common printed-circuit-
board materials.

Table 8-3. Dielectric Constants of Common PCB Materials

Material Name Fiber Material Bulk Material Dielectric
Constant
Rogers RO2800 2.9
Rogers RO4003 3.38
Rogers RO4350 3.48
FR-2 paper phenolic 4.3
FR-4 fiberglass epoxy 4.8
FR-5 fiberglass epoxy 4.8
G-2 staple-glass phenolic 5.1
G-5 fiberglass melamine 7.3
G-7 fiberglass silicone 3.9
G-10 fiberglass epoxy 4.8
G-11 fiberglass epoxy 4.8
XXPC paper phenolic 4.1
N-1 Nylon phenolic 3.6
GORE-PTFE expanded epoxy 2.8
PTFE/glass
alumina 10.0

Viewing and Planning Impedances and DC

Resistances
Use the Stackup Editor to view the characteristic impedance and DC resistance of an existing
stackup. You can also use the Stackup Editor to perform “what if” experiments to identify
stackup properties that achieve specific characteristic impedances and DC resistances.

This topic contains the following:

• “Viewing Characteristic Impedances” on page 387

• “Planning Characteristic Impedances” on page 388
• “Calculating DC Resistance” on page 390

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• “Changing the Bulk Resistivity and Temperature Coefficient for a Layer” on page 392
• “Viewing Resistance and Attenuation Over a Frequency Range” on page 392

Viewing Characteristic Impedances

The characteristic impedance is automatically calculated during simulation for each trace
segment in the selected net (BoardSim) or for the transmission line modeled with the stackup
method (LineSim). However you may want to calculate the characteristic impedance using a
specific test trace width to represent the following:

• A less-commonly used trace width on the net

• An experimental trace width to see how different impedances could be achieved with
different widths
Use the Stackup Editor to calculate the characteristic impedance resulting from the test trace
width on a specific layer in the stackup.

Calculating the Characteristic Impedance for Schematics

When you model a transmission line with the stackup method, LineSim automatically calculates
the line’s characteristic impedance and displays it on the schematic editor, in blue, on the
transmission line itself.

See also: “Edit Transmission Line Dialog Box - Transmission-Line Type Tab” on page 1573

Calculating the Characteristic Impedance for Boards

When you simulate a net, BoardSim automatically calculates the characteristic impedance for
each trace segment. To calculate the impedances, BoardSim uses your current stackup and the
width of the individual trace segments.

A PCB trace normally consists of many individual "segments" which, taken together, make up
the complete trace. BoardSim treats each of these segments individually as a separate
transmission line. If you have a trace that consists of a mixture of segment widths, for example,
some of the segments on the trace are 8 mils wide and some are 6 mils wide, BoardSim will
correctly account for the resulting impedance discontinuities and delay changes.

Calculating the Characteristic Impedance For a Test Trace Width

If you have an electrically valid stackup (no errors reported), the Stackup Editor displays the
characteristic impedance of the trace segments on each signal layer. The impedances appear
next to each signal layer in the picture pane. This data can help you to create or edit a stackup.
The Stackup Editor bases the impedance it displays on a test trace width that you can set for
each stackup layer. For plane layers, the trace width is used as the side-to-side distance from the
trace to a plane on the same stackup layer.

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About Test Trace Widths in BoardSim

As a convenience, when the design loads, BoardSim automatically sets each layer’s test trace
width to the most-commonly used trace width on that layer. Thus, the impedances in the
Stackup Editor should almost always correspond to the impedances you would naturally think
of for each layer. For example, if you have a layer on which almost all traces are 8 mils wide,
but there are a few 12-mil traces, by default the Stackup Editor will display the 8-mil impedance
— the most logical choice, given that only one impedance can be displayed at a time.

Note
It is important to realize that the Test Trace Width parameter does NOT affect the
impedances calculated for any of the traces on your board during simulation or any other
kind of analysis. The impedances used for simulation are based on the actual widths of
the traces in your PCB layout. The Test Trace Width only affects the impedance values
displayed in the picture pane. You can change the Test Trace Width to see what effect
various trace widths have on the characteristic impedance for each layer in your stackup.

To edit a layer’s test trace width:

1. In the spreadsheet, click the Metal tab.

2. Click in the Test Width cell for the layer you want to analyze, backspace over the value,
type the new value, and then click a different cell.
Result: The layer’s characteristic-impedance value in the Z0 column and the picture
pane updates immediately.
3. If you have multiple trace widths on a single layer and want to see the characteristic
impedance for each trace width, repeat step 2 as needed.
If you print the stackup or copy it to the Windows Clipboard, each layer’s characteristic
impedance and test-trace width display next to the layer.

Planning Characteristic Impedances

Use the spreadsheet Z0 Planning tab to calculate the trace geometries needed to achieve the
target characteristic impedance. Given your stackup's layer thickness and dielectric constant
information, the Stackup Editor can solve the trace geometry problem for single traces and for
differential pairs.

To copy all of the values from the Width column to the Test Width column in the Metal tab,
click the Apply as Test Width button. This capability is especially useful when the Width
numbers result from calculations to achieve a required impedance.

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Single Traces
For single traces, you can use the Z0 Planning tab to calculate the trace width needed to achieve
the target characteristic impedance.

To calculate the required trace width for a single trace:

1. In the spreadsheet, click the Z0 Planning tab.

2. In the Plan for list, select Single trace.
3. Click in the Target Z0 cell for the layer, backspace over the value, and then type the
new target characteristic impedance (in ohms).
4. Press Enter or click in a different cell.
Result: The required width is displayed in the Width column.

Differential Pairs
For differential pairs, you can use the Z0 Planning tab to calculate the geometries needed to
achieve the target differential characteristic impedance.

This topic contains the following:

• “Calculating Trace Separation For a Differential Pair” on page 389—You provide trace
width
• “Calculating Trace Width For a Differential Pair” on page 390—You provide separation
• “Calculating Trace Separation and Width For a Differential Pair” on page 390—You do
not provide either trace width or separation
Restriction: Impedance planning for differential pairs is available only if you have licensed the
appropriate option.

Calculating Trace Separation For a Differential Pair

To calculate the required trace separation for a differential pair:

1. In the spreadsheet, click the Z0 Planning tab.

2. In the Plan for list, select Differential pair.
3. In the Strategy list, select Solve for separation.
4. Click in the Diff Z0 cell for the signal layer, backspace over the value, and then type the
new target characteristic impedance (in ohms).
5. Click in the Width cell for the signal layer, backspace over the value, and then type the
new width.

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6. Press Enter or click in a different cell.

Result: The required separation is displayed in the Gap column for the signal layer.

Calculating Trace Width For a Differential Pair

To calculate the required trace width for a differential pair:

1. In the spreadsheet, click the Z0 Planning tab.

2. In the Plan for list, click Differential pair.
3. In the Strategy list, click Solve for width.
4. Click in the Diff Z0 cell for the signal layer, backspace over the value, and then type the
new target characteristic impedance (in ohms).
5. Click in the Gap cell for the signal layer, backspace over the value, and then type the
new trace separation.
6. Press Enter or click in a different cell.
Result: The required width is displayed in the Width column for the signal layer.

Calculating Trace Separation and Width For a Differential Pair

To calculate the required trace width and trace separation for a differential pair:

1. In the spreadsheet, click the Z0 Planning tab.

2. In the Plan for list, click Differential pair.
3. In the Strategy list, click Solve for both.
4. Click in the Diff Z0 cell for the signal layer, backspace over the value, and then type the
new target characteristic impedance (in ohms).
5. In the Curve column, click View in the cell for the signal layer.
Result: The Width Versus Separation Graph dialog box opens and displays the width
versus separation curve.
6. If needed, you can examine or document the curves using zoom, pan, copy to clip, print,
and so on.
See also: “Examining and Documenting Curves” on page 395

Calculating DC Resistance
When you simulate a net, BoardSim/LineSim automatically calculates the DC resistance of
every segment on the trace. To calculate DC resistance, BoardSim/LineSim uses the following
parameters:

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• Trace width, thickness, and length

• Bulk resistivity of trace’s metal
• Resistivity temperature coefficient of trace’s metal
• Simulation temperature
Trace width, thickness, and length are based on the:

• Actual segment-by-segment parameters in your board’s layout (BoardSim)

• Data you enter when specifying the transmission line (LineSim)
However you can adjust the remaining parameters (resistivity, temperature coefficient, and
temperature) as in the following sections.

Bulk Resistivity and Temperature Coefficient

In BoardSim/LineSim, each metal layer’s bulk resistivity and temperature coefficient default to
the values for copper (resistivity = 1.724e-8 ohms-meter, temperature coefficient = 3.93e-3).
This means that unless you are using a metal other than copper (e.g., aluminum, for an MCM
application), you do not need to change the resistivity or temperature-coefficient parameters.

See also: “Changing the Bulk Resistivity and Temperature Coefficient for a Layer” on page 392

How Resistivity - Temperature Coefficient - Temperature Are Used

The DC resistance of a piece of metal conductor varies with temperature. When
BoardSim/LineSim calculates the DC resistance of a trace, it uses the following equation to
include the effects of temperature:

where Rb is the bulk resistivity of the trace’s metal at 20 degrees C; Tc the temperature
coefficient; and T the temperature at which the simulation is being run. If the temperature for
the bulk resistivity of the trace's metal is not 20 degrees C, subtract that temperature value from
T within the parenthesis.

Simulation Temperature
The temperature for a BoardSim/LineSim simulation defaults to 20 degrees C.

The board temperature affects only DC resistance calculations. It does not, for example, also
affect IC-model parameters. Since DC resistance does not play a large role in most
BoardSim/LineSim simulations, you can generally leave the temperature at its default value
without sacrificing any significant simulation accuracy. You should only change the
temperature if you know for some reason that it will have a significant effect on your
simulation.

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To change the simulation temperature:

1. Setup menu > Options > General > General tab.

2. In the Analysis Options area, type the new temperature in the Board Temperature box.
3. Click OK.
Board temperature affects not only the simulator (oscilloscope), but also the Terminator Wizard
and Board Wizard. For this reason, BoardSim/LineSim refers to this feature as an "analysis"
(not just "simulation") option. The same applies to inclusion of vias.

Changing the Bulk Resistivity and Temperature

Coefficient for a Layer
In the Stackup Editor, you can review or change the bulk resistivity or temperature coefficient
values with the Metal tab on the spreadsheet. For common metals, the bulk resistivity and
temperature coefficient values are automatically provided in the spreadsheet.

If you are using a special metal, or you do not want to use the default values, you can create a
custom metal type and provide the bulk resistivity and temperature coefficient values for it.

To change bulk resistivity and temperature coefficient values:

1. In the spreadsheet, click the Metal tab.

2. On the layer you want to change, do the following:
• Click in the Metal cell to display the list, and then click <Custom>.
• Click in the Bulk R cell, backspace over the old bulk resistivity value, and then type
the new value.
• Click in the T coef cell, backspace over the old temperature coefficient value, and
then type the new value.

Viewing Resistance and Attenuation Over a Frequency

Range
Run the field solver to calculate and graph transmission line resistance and attenuation over a
frequency range.

This topic contains the following:

• “Displaying Loss Versus Frequency in the Edit Transmission Line Dialog Box” on
page 393
• “Displaying Loss Versus Frequency in the Stackup Editor” on page 393

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• “Displaying Loss Versus Frequency in BoardSim” on page 394

Restriction: This feature is unavailable if you have not licensed the appropriate option.

See also: “Examining and Documenting Curves” on page 395

Displaying Loss Versus Frequency in the Edit Transmission Line

Dialog Box
Use the Edit Transmission Line Dialog Box - Loss Tab to graph resistance or attenuation over a
frequency range for transmission lines modeled using the following stackup types:

• Stackup
• Coupled Stackup
• Microstrip
• Buried Microstrip
• Stripline
• Wire Over Ground

Related Topics
“Edit Transmission Line Dialog Box - Loss Tab” on page 1570

Displaying Loss Versus Frequency in the Stackup Editor

In the Stackup Editor, the field solver runs on a test conductor within the stackup, using the Test
Width value from the Metal tab on the spreadsheet. Unlike the LineSim transmission line editor,
the Stackup Editor does not provide conductor length and coupling information to the field
solver, so per-unit and propagation mode results are unavailable.

To view transmission line resistance and attenuation:

1. In the Stackup Editor, click the Metal tab.

2. In the Loss Curve column, click the View button for the appropriate metal layer.
Restriction: This tab is unavailable if you have not enabled Lossy Simulations on the
toolbar.
3. In the loss versus frequency graph, do any of the following:
• Click Resistance to view resistance information.
• Click Attenuation to view signal attenuation information. The blue curve represents
the combined resistive and dielectric attenuation. To view the resistive and dielectric
attenuation components, select the Resistive or Dielectric check boxes.

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You can examine or document the curves using zoom, pan, copy to clip, print, and so on.
See “Examining and Documenting Curves” on page 395.
4. If you selected the Resistive and Dielectric check boxes under the Attenuation radio
button, the Dielectric loss dominates at box is available. It displays the frequency at
which dielectric attenuation crosses resistive attenuation and therefore begins to
dominate.

Displaying Loss Versus Frequency in BoardSim

BoardSim can graph resistance or attenuation over a frequency range for a trace segment that
you point to in the board viewer.

To view transmission line resistance and attenuation:

1. In the board viewer, right-click over the trace segment, and then click View Field-
Solver Output.
2. In the Field Solver and Lossy dialog box, click the Loss tab.
Restriction: This tab is unavailable if you have not enabled Crosstalk Analysis on the
toolbar.
3. In the loss versus frequency graph, do any of the following:
• Click Resistance to view resistance information.
• Click Attenuation to view signal attenuation information. The blue curve represents
the combined resistive and dielectric attenuation. To view the resistive and dielectric
attenuation components, select the Resistive or Dielectric check boxes.
You can examine or document the curves using zoom, pan, copy to clip, print, and so on.
See “Examining and Documenting Curves” on page 395.
4. Do any of the following:
• Select the Surf. Roughness check box to include the effects of conductor surface
roughness. See “Surface Roughness Dialog Box” on page 1871.
• Clear the Per Unit Length check box to display the resistance or attenuation for the
full transmission line length.
• Select the Per Unit Length check box to display the resistance or attenuation on a
per-unit basis. This information can be helpful if the net/trace must meet a specified
per-unit value.
5. Type the frequency range into the Min and Max boxes.
6. Select or clear, as needed, the Log Scale At X Axis and Log Scale At Y Axis check
boxes.

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7. In the Propagation Mode list, select the propagation mode for which you want to see
field lines. The list is unavailable when the selected transmission line is not coupled to
another transmission line. The list contains one of the following sets of items:
• If the selected transmission line is coupled to one other transmission line, the
Propagation Mode list contains Differential(+-) and Common(++) items, where +
and - are the voltage polarity of the stimulus applied to the coupled transmission
lines. For example Differential(+-) indicates that the field solver stimulates the
coupled transmission lines with opposite polarity signals.
• If the selected transmission line is coupled to two or more other transmission lines,
the Propagation Mode list contains #(<polarity list>) items. # is the mode number.
<polarity list> is the stimulus applied to the coupled transmission lines. <polarity
list> values can be +, -, or 0, where + and - are signal voltage polarity and 0 is no
signal. For example if there are three coupled transmission lines, the Propagation
Mode list may contain 1(+-+), 2(+++), and 3(-+-).
See also: “Choosing a Propagation Mode to Plot” on page 1210, “Propagation Modes-
Single-Dielectric versus Layered-Dielectric Traces” on page 1361
8. If you select the Resistive and Dielectric check boxes under the Attenuation radio
button, the Dielectric loss dominates at box is available. It displays the frequency at
which dielectric attenuation crosses resistive attenuation and therefore begins to
dominate.

Examining and Documenting Curves

You can adjust the graph appearance, print the graph, copy the graph to the clipboard, and so on.

Restriction: Toolbar buttons are unavailable in the Loss-vs-Frequency Graph dialog box.

Table 8-4. Graph Viewing and Documentation Tasks

Task Procedure
Zoom in 1. Enable zoom mode by doing one of the following:
• Click Zoom to selection .
• Right-click over the graph and click Zooming.
This mode is disabled when you enable a different mode.
2. Position the mouse pointer over one corner of the zoom box
you want to create, and then drag to define the other corner of
the zoom box.
3. Release the mouse button to magnify the contents of the zoom
box to fill the graph.

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Table 8-4. Graph Viewing and Documentation Tasks

Task Procedure
Pan 1. Enable pan mode by doing one of the following:
• Click Pan picture .
• Right-click over the graph and click Panning.
This mode is disabled when you enable a different mode.
2. Drag the graph across the graph.
This option enables you to view different portions of the curve
without changing magnification.
Attach measurement 1. Enable tracking mode by doing one of the following:
crosshairs to a waveform • Click Cursor Tracking Mode .
• Right-click over the graph and click Track Cursor.
This mode is disabled when you enable a different mode.
2. Click the waveform to measure.
Result: As you move the mouse horizontally, the measurement
crosshairs tracks the selected curve.
Fit the entire curve to • Click Fit to window .
window • Right-click over the graph and click Fit to window.
Display lines between curve • Click Display lines between curve vertices .
vertices
Display curve vertices only • Click Display curve vertices only
Display both lines and • Click Display both lines and vertices .
vertices
Print (white background) • Click Print curve .
• Right-click over the graph and click Print.
Copy to clipboard (white • Right-click over the graph and click Copy.
background) This option uses less printer ink or toner if you print it out.

You can paste the image from the Windows clipboard into
another program such as Microsoft WordPad.
Copy to clipboard (black • Right-click over the graph and click Copy inverted.
background) You can paste the image from the Windows clipboard into
another program such as Microsoft WordPad.

Related Topics
“Viewing Resistance and Attenuation Over a Frequency Range” on page 392

Setting Layer Display Options for the Board

Viewer in BoardSim
In BoardSim, you can set several board viewer display options with the Stackup Editor.

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This topic discusses the following

• “Changing Stackup Layer Colors” on page 397

• “Setting Signal or Plane Layer Visibility” on page 397
• “Viewing Pours and Voids” on page 398
• “About Pour and Void Terminology” on page 398
See also: “Viewing Filter Dialog Box”

Changing Stackup Layer Colors

The plane and signal layer colors in the Stackup Editor match the colors in the board viewer. A
maroon trace segment, for example, is on the layer which is shown in the Stackup Editor as
maroon. The only exception to the color matching between Stackup Editor and board viewer is
if you have deliberately highlighted nets in the board with non-stackup-layer colors.

See also: Board Viewer User Interface, Board Viewer Operations

Procedure
You can change the color of any metal layer. The color for dielectric layers cannot be changed.

To change a layer’s color:

1. In the spreadsheet click the Basic tab.

2. Click in the Color cell for the layer you want to change, and then click the arrow that
appears.
3. In the Color dialog box, select a new color, and then click OK.

Setting Signal or Plane Layer Visibility

In BoardSim's Stackup Editor, you can select the signal or plane layers to display in the board
viewer. This capability enables you to select a net that is routed on multiple layers, yet not
display one or more of the layers used to route the net.

See also: “Viewing Filter Dialog Box”

To set visibility for an individual signal or plane layer:

1. In the spreadsheet, click the Basic tab

2. In the Visible column, clear the layer you want to not display in the board viewer.
Alternative: Select the layer you want to display in the board viewer.

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Viewing Pours and Voids

Many PCBs have plane layers in their stackup that are not literally solid sheets of copper, but
instead consist of a collection of copper pours or voids that together form a plane. Similarly,
many PCBs have signal layers with copper pours or voids that form a plane region. BoardSim’s
board viewer can display the actual structure of the metal layer, including any copper pours or
voids that may be present.

From a high-speed perspective, copper pours and voids on a plane may cause impedance
discontinuities, excessive radiated emissions, and other undesirable electromagnetic effects.
Along with power-integrity analysis features, you can use BoardSim's board viewer to identify
portions of your PCB that are likely to cause trouble, such as specific traces crossing a ground
gap or copper void.

See also: “About Pour and Void Terminology” on page 398, “Preferences Dialog Box -
BoardSim Tab” on page 1804

To view copper pours and voids on a metal layer:

1. In the spreadsheet, click the Basic tab.

2. In the Pour Draw Style column for the metal layer, click the cell to display the list, and
then select a style.
Restriction: The Draw Style column is not displayed on the Basic tab when the board
does not contain pour or void data.

About Pour and Void Terminology

The terminology used to describe PCB structures like "copper pours" and "copper voids" differs
among PCB layout tools, and is often ambiguous or conflicting.

Terms used by BoardSim:

Table 8-5. Pour and Void Terminology

Term Definition
copper pour, pour outline, plane A closed, arc-shaped polygon that specifies a region
area that should be poured by metal.

The PCB design system's pouring operation creates

clearance areas around pins, traces, and vias on other
nets. Also see the anti-pad definition below.
copper void, pour cutout A region inside a copper pour that is kept free of metal
when pouring occurs.

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Table 8-5. Pour and Void Terminology (cont.)

anti-pad Defines the shape and size of the clearance area
(copper void) that should be created while pouring
around a pin, trace or via if it drops onto the copper
pour polygon.

Related Topics
“Viewing Pours and Voids” on page 398

“Preferences Dialog Box - BoardSim Tab” on page 1804

Documenting Stackups
You can distribute stackup information to other people, such as the PCB fabricator, by printing
the stackup or copying its image to the Windows clipboard and pasting the contents of the
clipboard into a document that can accept it, such as Microsoft Word.

This topic contains the following:

• “Printing Stackups” on page 399

• “Copying a Stackup to the Clipboard” on page 400

Printing Stackups
You can document the stackup by printing it from the Stackup Editor. Some possible reasons to
print the stackup follow:

• You change your stackup in BoardSim/LineSim in order to achieve certain impedances,

improve signal integrity, and so on, and you need to communicate the change to others
in your engineering, CAD, or manufacturing departments.
• You need to document the new stackup properties to your PCB fabricator.

Printing the Stackup Spreadsheet

To print the stackup spreadsheet:

1. Print layers info button .

Alternative: File menu > Print.
2. In the Print layers area of the Print dialog box, select one of the following:
• Whole Stackup
• Range, then type the spreadsheet layer numbers to print

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Documenting Stackups

• Selection, which prints only the selected layers. This option is unavailable if no
layers are selected.
3. In the Print columns area, select the columns to print or clear the columns to not print.
4. Click OK.

Printing the Stackup Picture

To print the stackup picture:

1. Print Stackup as a picture button .

Alternative: File menu > Print Picture.
2. Portrait orientation is best for large stackups. If necessary, click Properties, and then
click the Layout tab to check your printer setup.
3. Click OK. Stackup pictures sent to a color printer are output in color.

Setting Up For Printing

You can set up printing-related defaults—such as printer choice, paper size, and page
orientation—once in BoardSim/LineSim, and then have them apply for the remainder of your
work session, and for all types of printing (schematics, stackups, oscilloscope results, etc.).

To set up "persistent" printing defaults:

1. File menu > Print Setup.

2. Change any parameters you wish.
3. Click OK.
Result: BoardSim/LineSim now remembers the choices you’ve made, and it will
continue to use them.

Copying a Stackup to the Clipboard

You can copy your stackup in the Stackup Editor to the Windows Clipboard in order to paste it
into other Windows applications. The image copied to the clipboard includes the board name,
total board thickness, and so on.

The size of the image pasted into the other application may vary. You can resize the image as
needed because the image file is vectorized (using the Windows Enhanced Metafile format) and
can be resized without damaging image quality.

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Setting Measurement Units

Two forms of stackup information are available. See Table 8-6.

Table 8-6. Types of Stackup Image Information

Information type Means
Manufacturing documentation A schematic image that emphasizes manufacturing
information, such as layer thickness
Picture Same as the image in the picture pane

Copying Stackup Manufacturing Documentation to the Clipboard

To copy stackup manufacturing documentation to the Windows Clipboard:

• Click the Copy to Clipboard as Manufacturing Documentation button.

Or
Edit menu > Copy Special > Manufacturing Documentation.

Copying Stackup Pictures to the Clipboard

To copy the stackup picture to the Windows Clipboard:

• Click the Copy to clipboard button.

Or
Edit menu > Copy Special > Picture.

Setting Measurement Units

You can set the measurement units displayed in the Stackup Editor, board viewer (BoardSim),
and Edit Transmission Line dialog box (LineSim), and other dialog boxes that display
geometric information. For metal layer thickness, you can select between thickness or weight
units. For all other dimensions, you can select between English or metric units.

The default settings are English and weight, meaning dimensions are displayed in inches (or
mils for dielectric thickness) and metal thickness is displayed in ounces. International users may
prefer metric and length, meaning dimensions are displayed in centimeters (or microns for
dielectric thickness) and metal thickness is displayed in microns.

You can change units from the Stackup Editor or from the Units Dialog Box.

Setting Measurement Units from the Stackup Editor

To set measurement units from the Stackup Editor:

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Setting Measurement Units

1. Setup menu > Stackup > Edit.

2. In the spreadsheet, click the Basic tab, and then do any of the following:
• To set the dimension units, select the unit from the Measurement units list.
• To set the metal thickness units, select Weight or Length on the Metal thickness as
list.

Related Topics
“Units Dialog Box” on page 1888

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 Creating and Editing IBIS Models

Chapter 9
Creating and Editing IBIS Models

Use the HyperLynx Visual IBIS Editor to create, edit, verify, and maintain IBIS (I/O Buffer
Information Specification) device models. Mentor Graphics developed the HyperLynx Visual
IBIS Editor ("Editor" from now on) to encourage the development of IBIS device models. The
Editor’s IBIS-optimized features make creating and verifying IBIS models much simpler than
using IBIS-ignorant tools.

The Editor has several useful features for IBIS model developers, including:

• An integrated IBIS-syntax-check utility

• A graphical viewer for looking at IBIS V-I tables and waveform tables
• An online IBIS specification
The following Editor features are licensed with the purchase of a qualifying Mentor Graphics
product:

• A wizard to help create a new IBIS model

• Modify table data by graphically editing V-I and V-t curves
• Automatically modify V-t table data to correct V-I / V-t table mismatches
• Automatically modify V-t table data to remove initial delays
This topic contains the following:

• “About the Graphical User Interface” on page 404

• “Enabling Licensed Features” on page 406
• “Editing IBIS Models” on page 406
• “Removing Initial Delays from IBIS Models” on page 414
• “Examining and Editing V-I and V-t Curves” on page 420
o “Graphically Editing V-I or V-t Curves” on page 424
• “Checking and Correcting IBIS Models” on page 428
o “Correcting V-t and V-I Table Mismatches Automatically” on page 430
• “Verifying IBIS Models” on page 432
o “Identifying Common IBIS Model Problems” on page 433

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About the Graphical User Interface

• “Creating IBIS Models with the Easy IBIS Wizard” on page 450

About the Graphical User Interface

It can helpful to understand the names and contents of the editor’s graphical user interface.
Also, you can customize the appearance of the editor.

This topic contains the following:

• “About the Main Areas in the Editor” on page 404

• “Changing the Appearance of the Editor” on page 405

About the Main Areas in the Editor

Figure 9-1 shows the main sections of the graphical user interface (GUI).

Figure 9-1. GUI Overview for Visual IBIS Editor

The Editor panes display the IBIS file's content and structure. The panes are linked so you can
quickly display in another pane the data related to the current cursor/pointer position.

• Tree-view pane:
o Displays the keywords in the IBIS file. To display the keyword in the edit window,
double-click the keyword in the tree-view pane.
o Displays table data in the graphical viewer. To display the table data graphically,
right-click a keyword, and then click View data. By visualizing table data as a curve
or waveform, you may spot data with mistyped numbers or bad signs.
• Edit window: Displays and edits the text of your IBIS files. The Editor displays
keywords, comments, and other text in different colors, which may help you to visually
spot syntax errors. To select the keyword in the tree-view pane, right-click on the line in
the Editor and click Synch Content.

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• Output window: Displays the IBIS syntax checking results and other Editor messages.
To jump to the edit window line containing the IBIS syntax error, double-click a
warning or error message in the output window (the message must contain a line
number).

Changing the Appearance of the Editor

This topic contains the following:

• “Resizing the Editor Dialog Box or Internal Panes” on page 405

• “Hiding or Displaying Editor Windows or Menus” on page 405
• “Setting Font Color and Tab Preferences” on page 405

Resizing the Editor Dialog Box or Internal Panes

Use standard window-operating procedures to manipulate this window.

To resize the Editor dialog box:

• Drag a corner or side of the window to resize the Editor.

To resize the edit window, tree-view pane, or output window:

• Drag the splitter bar separating the Editor's windows to resize them.

Hiding or Displaying Editor Windows or Menus

To hide or display Editor windows or menus:

• View menu > select or clear feature name.

The checkmark indicates the feature is displayed.

Restriction: The edit window and menu bar cannot be hidden.

Setting Font Color and Tab Preferences

You can change the text font and background color used by the edit and output windows. The
font and color settings for the edit and output windows are independent.

The Visual IBIS Editor has a feature that automatically converts tab characters to space
characters. See “Converting Tabs to Spaces” on page 411 for details. The IBIS specification
allows tabs, but recommends against using them because different tools expand them in
different ways.

To set text preferences for the editor window or output window:

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Enabling Licensed Features

1. Edit menu > Preferences.

2. In the Window list, select the window for which you want to change the text
appearance.
3. Change the options as needed.
Alternative: Click Defaults to apply the default settings to the Editor Window and
Output Window.
Restriction: Tabs options are not available for the Output Window.
New tabs are automatically converted to spaces unless you select the Keep Tabs check
box. Tabs already present in the file are not converted to spaces when you select the
Keep Tabs check box.
4. Click OK.

Enabling Licensed Features

A qualifying Mentor Graphics product, such as HyperLynx or ICX, must be installed on the
computer to enable licensed features, such as the following:

• Easy IBIS Wizard

• Correct V/t Tables
• Graphically Editing V-I or V-t Curves
If a qualifying product is on the computer, you can use Preferences dialog box to disable
licensed features.

To disable licensed features:

1. Edit menu > Preferences.

2. Clear the Enable licensed features check box.
3. Click OK.

Editing IBIS Models

The Visual IBIS Editor provides features that are optimized for viewing and editing IBIS
models.

This topic contains the following:

• “Opening the Visual IBIS Editor” on page 407

• “Opening an IBIS File” on page 407

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• “Finding an IBIS Keyword - Signal - Pin - Text” on page 408

• “Cutting Copying Pasting Replacing and Deleting Text” on page 408
• “Converting Tabs to Spaces” on page 411
• “Commenting or Uncommenting Selected Lines” on page 411
• “Marking a Line with a Bookmark” on page 411
• “Going to a Line Number” on page 412
• “Selecting a Rectangular Block of Text” on page 412
• “Saving Files” on page 413
• “Printing an IBIS File” on page 413

Opening the Visual IBIS Editor

You can open the Editor from the Windows Start menu or from within Mentor Graphics
HyperLynx programs.

To open the Editor:

• Select Start > All Programs > Mentor Graphics SDD > HyperLynx <release> >
HyperLynx Visual IBIS Editor
To open the Editor from within HyperLynx BoardSim or LineSim:

• Click
• Select Models > Edit IBIS IC Models

Opening an IBIS File

To open an IBIS file:

1. Open button .
2. Select the file you want to edit.
3. Click Open.
Alternatives:
• From Windows Explorer, drag the IBIS file into the Edit window.
• The last four files opened by the Editor are listed on the File menu. Select the file to
open it.
4. To set read-only mode, click Read-Only on the File menu.

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Finding an IBIS Keyword - Signal - Pin - Text

Linking between the tree-view pane and the edit window helps you quickly find a keyword in
the IBIS file.

To display an IBIS keyword in the edit window:

• Double-click a keyword in the tree-view window, or right-click the keyword and then
click Go To Item.
Click the plus sign in front of a keyword to expand the tree and display more keywords.
To display a signal or pin in the edit window:

1. Select a component, pin, or signal in the tree-view pane.

2. Right-click and click Find signal or Find pin.
3. Select the signal or pin then click Go.
To find text:

1. Press CTRL+F or click Edit menu > Find.

The search begins at the line with the cursor.
2. In the Find What box, type in the text you want to find.
To find previously found text, click the down arrow next to the Find What box and then
click a row of text from the list.
3. Select the options you want to use.
4. Click Find Next.
Result: If the text is found, the cursor jumps to the line matching the search.
Click Mark All to add a bookmark to all the lines containing the text for which you are
searching. To remove all bookmarks click View menu > Clear Bookmarks.
5. To find additional matches, press F3 or click Edit menu > Find Next.

Cutting Copying Pasting Replacing and Deleting Text

The Editor supports common text-editing functions such as cut, copy, paste, replace, and delete.
These functions are available using the standard Windows keyboard shortcuts (pressing two or
more keys simultaneously), the Edit menu, or the toolbar.

You can select the text in the edit window for a keyword by selecting the keyword in the tree-
view pane, right-click, and then click Select text.

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You can select a rectangular block of text to edit, in addition to the standard line-based selection
type. See “Selecting a Rectangular Block of Text” on page 412.

This topic contains the following:

• “Cutting Text” on page 409

• “Copying Text” on page 409
• “Pasting Text” on page 409
• “Replacing Text” on page 410
• “Deleting Text” on page 410
• “Undoing or Redoing an Edit” on page 410

Cutting Text
To cut text:

1. Select the text you want to cut.

2. Press CTRL+X or on the toolbar click .
Result: The text disappears and is copied into the Windows clipboard.

Copying Text
To copy text:

1. Select the text you want to copy.

2. Press CTRL+C or on the toolbar click .
Result: The text is copied into the Windows clipboard.

Pasting Text
To paste text:

1. Position the cursor where you want the text from the Windows clipboard to be pasted.
2. Press CTRL+V or on the toolbar click .
Alternatives:
• Drag selected text from another Windows application and drop the selection into the
Editor window.
• Drag selected text to another location in the Editor window.

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Result: Text is pasted into the file.

Replacing Text
To replace text:

1. Position the cursor on the line in the file where you want to start replacing text.
Skip this step if you plan to replace all occurrences.
2. On the Edit menu, click Replace, or press CTRL+H.
3. In the Find What box, type in the text you want to replace.
Previous find strings are available from the list.
4. In the Replace With box, type the text you want to insert.
Previous replace strings are available from the list.
5. Select the options you want to use.
6. Click Replace to replace only the first occurrence, starting from the current cursor
position.
Alternative: Click Replace All to replace all occurrences.

Deleting Text
To delete text:

1. Select the text you want to delete.

2. Press Delete.
Result: The text disappears.

Undoing or Redoing an Edit

The Editor provides multiple-level undo and redo capabilities.

To undo an edit:

• Press CTRL+Z.
Alternative: Edit menu > Undo.
To redo an edit (restore an edit that was undone):

• Press CTRL+Y.
Alternative: Edit menu > Redo.

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Converting Tabs to Spaces

The Visual IBIS Editor can convert all the tab characters in the file to one or more space
characters. The IBIS specification allows tabs, but recommends against using them because
different tools expand them in different ways.

Caution
You cannot undo tab-to-space conversions.

To convert tab characters to space characters:

1. Edit menu > Convert Tabs. The Convert tabs to spaces dialog box appears.
2. If necessary, type the number of space characters used to replace each tab.
3. Click Convert.
Result: The Editor replaces all tabs in the file with spaces.

Commenting or Uncommenting Selected Lines

You can comment out a line by inserting the comment character (|) at the beginning of the line.
You can use the Editor's commenting feature to add or remove comment characters for the
selected lines.

To add or remove comment characters:

1. Select the lines you want to comment or uncomment.

2. On the toolbar, click or press CTRL+M.
When multiple lines are selected, the comment character is added to all the selected lines if any
of them are not currently commented.

Marking a Line with a Bookmark

You can use a bookmark to mark a line to which you want to return. This topic discusses how to
manually add or remove bookmarks, and how to navigate among multiple bookmarks.

Bookmarks are discarded when you close the IBIS file.

For example you may be editing a [Pin] statement and do not remember which model you want
to assign to a pin. Mark the [Pin] statement line, find the model you want to use, then return to
the [Pin] statement by finding its bookmark.

To add or remove an individual bookmark:

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1. Position the cursor on the line you want to add or remove a bookmark.
2. Press CTRL+F2, or click View menu > Toggle Bookmark.
The find function can add bookmarks to all lines containing the text for which you are
searching. See “Finding an IBIS Keyword - Signal - Pin - Text” on page 408.
To remove all bookmarks:

• Click View menu > Clear Bookmarks.

To go to the next bookmark:

• Press F2 or click View menu > Next Bookmark.

Going to a Line Number

The line number for the cursor position is displayed on the Editor's status bar, near the bottom of
the window.

To go to a line number:

1. Press CTRL+G or click Edit menu > Go To Line.

Select Keep Open to keep the Go To Line dialog box open after clicking the Go To.
2. Type the line number that you want to display.
3. Click Go To.
Result: The Editor displays the target line and positions the cursor on it.

Selecting a Rectangular Block of Text

You may select a rectangular block of text, which consists of a column of text that spans
multiple lines, and perform on it such common edit functions such as copy, cut, paste, and
delete. Rectangular selections may improve your table editing efficiency by limiting your edits
to specific columns in the table.

Figure 9-2. Example of a Rectangular Selection in the Visual IBIS Editor

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To select a rectangular block of text:

• Press ALT+drag.

Saving Files
The Visual IBIS Editor allows you to save a file as long as the Editor is not running in read-only
mode.

To save the file under the current name:

• Save button or press CTRL+S.

To save the file under a new name or format:

1. File menu > Save As.

2. Type the new file name, and then click Save.
Use the Save As Type list to filter the types of files displayed in the area below the Save
In list.
Use the File Format list to save the file in the DOS or UNIX format. At the end of a line,
the Editor writes a carriage return code for DOS-formatted files or a line feed code for
UNIX-formatted files.

Printing an IBIS File

You can print the IBIS file that is open in the Editor. Standard Windows print preview and print
setup capabilities are also available from within the Editor.

To print the IBIS file:

1. Print button .
2. If needed, change the printing options.
3. Click OK.
To run print preview:

1. File menu > Print Preview.

Use the page and zoom buttons to help evaluate the predicted appearance of the printed
file.
2. Click Print to print the file, or click Close to close print preview without printing the
file.
To set printer properties:

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Removing Initial Delays from IBIS Models

1. File menu > Print Setup.

2. If needed, change the printing options.
3. Click OK.

Removing Initial Delays from IBIS Models

Use the Remove Initial Delays dialog box to remove the initial non-switching time from the V-t
waveform tables in an IBIS model, and then save the modifications to a new model file.

Common reasons to remove initial delays from IBIS models include the following:

• Reducing simulation run time.

• When viewing waveforms, eliminate the need to reposition the waveform past the start
up delay to see the switching area of the waveform.
• Avoid mistaking a meaningless initial delay present in one model (but not the other
models) may be mistaken for real skew. This can happen in source-synchronous designs,
or in other cases where you want to measure skew among waveforms for multiple nets.
This topic contains the following:

• “About the Initial Delay Removal Algorithm” on page 414

• “Time Correlation Across Multiple V-t Tables” on page 415
• “Removing Initial Delays from Individual IBIS Models” on page 419
• “Removing Initial Delays from Multiple IBIS Models” on page 419

About the Initial Delay Removal Algorithm

Conceptually, removing the initial non-switching time from a V-t waveform table seems simple.
You look at the table to see if there is some initial portion of the waveform before switching
begins. If there is, you remove it by moving the t=0 time to the point in the table just before
switching begins.

However, a robust algorithm that works for a wide variety of models is more complicated than
that. A key requirement of a robust algorithm is to not interpret noise as switching, so the
algorithm applies a filter to identify the start of switching.

Main steps in the algorithm used by the Visual IBIS Editor:

1. Find the switching voltage by recording the voltage values from the first and last entries
in the V-t waveform table (these values are assumed to be the initial and final DC values
of the waveform), and then subtracting the low DC voltage from the high DC voltage.

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2. Find the approximate start of the switching by moving forward in time along the V-t
waveform, starting from the first point. Using linear interpolation, mark the time at
which the V-t waveform first moves 1% of the switching voltage away from the initial
DC voltage.
You can edit the 1% noise threshold when removing initial delays for an individual IBIS
model. See step 3 in “Removing Initial Delays from Individual IBIS Models” on
page 419.
3. Remove all points in the table that are earlier in time than the interpolated 1% point. In
Figure 9-3 on page 415, these are the gray dots.
4. Extrapolate linearly back from the retained points to the initial DC voltage, and add this
as a new point to the beginning of the table. Record this first new point as the "removal
time." In Figure 9-3, this is the left red dot.
5. Add a second new point that is located linearly between the first new point and the first
point retained from the original waveform, where the 1% threshold is crossed. Record
this second new point as the “stripping time.” In Figure 9-3 this is the right red dot.
Figure 9-3 graphically shows the algorithm for an example falling-edge waveform with
a slightly noisy initial DC non-switching time.

Figure 9-3. Initial Delay Removal Algorithm Example

6. Subtract the removal time from all points in the table.

Time Correlation Across Multiple V-t Tables

Most IBIS models contain multiple V-t tables, each one of which could easily have a unique
amount of initial non-switching time removed per the algorithm described in “About the Initial
Delay Removal Algorithm” on page 414.

The most-typical scenario is where the model contains four tables, two each for the rising and
falling edges, with each edge described by one table driving into an opposing load and the other
table driving into an assisting load.

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The initial delay removal application supports the following time correlation methods:

• “All Tables Correlated” on page 416

• “Rising and Falling Tables Treated Separately” on page 416
• “Corners Treated Separately” on page 417

All Tables Correlated

The IBIS 4.x specification states that the initial delay timing in all V-t waveforms should be
correlated. That is, if the switching waveform for one table is delayed relative to the waveform
of another table, the delay is intentional and describes the true behavior of the device.

Many or most of the IBIS models available today are created by running a SPICE buffer model
through a SPICE-to-IBIS converter available from the University of North Carolina. By default,
this converter creates models with all model V-t tables being time correlated, per the IBIS
specification recommendation.

Main steps in the algorithm:

1. Find the first V-t table in the model, run on a column the algorithm discussed in “About
the Initial Delay Removal Algorithm” on page 414, and then record the removal time.
2. Repeat for the other columns (that contain data) in the table.
3. Repeat steps 1-2 for all the other tables in the model.
4. Find the smallest stripping time (see step 5 of the algorithm description). For the column
that generated it, retain the table modified by the initial delay removal algorithm. The
removal time for this column is the “global” removal time.
5. Modify all the other columns by doing the following:
a. Restore them to their original state.
b. Remove all points that occur earlier than the global removal time.
c. Add a new first point at the removal time, with a voltage value equal to the initial
DC time for this column.
d. Subtract the global removal time from each point in the table, and make the time for
the first point equal to 0.0.

Rising and Falling Tables Treated Separately

Sometimes a model created from measured data has uncorrelated rising- and falling-edge tables.
For example, a clocked oscilloscope waveform containing a rising and then falling edge might
be cut in half, and the raw times from the second half of the waveform placed directly into a V-

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t table. This kind of model will not behave properly if initial delays are removed using the
default method described by “About the Initial Delay Removal Algorithm” on page 414.

In this case, you can instruct the initial delay removal application to treat rising and falling V-t
tables independently. Time correlation is maintained within all tables for each edge. This means
that unique initial delay values are removed from the falling-edge tables and rising-edge tables.

Caution
This method can destroy possible information about asymmetric duty cycles, and could
make eye diagrams overly optimistic.

Corners Treated Separately

While delay correlation among corners (that is, min/typ/max columns) should be maintained per
the IBIS specification, the following example exceptions may exist:

• Different test circuits or test conditions are used for min/typ/max measurements or
simulation.
• A portion of the delay in a minimum waveform (for example) actually comes from
core/internal logic and is already being accounted for in the clock-to-output (or similar)
delay for the buffer in a timing spreadsheet.
You can instruct the initial delay removal application to remove delays from each corner
independently. Time correlation is maintained within all tables (both rising and falling edges)
within a given corner/column. This means that unique initial delay values are removed from the
min, typ, and max columns in all tables.

Main steps in the algorithm:

1. Find the first V-t table in the model, run on a column the algorithm discussed in “About
the Initial Delay Removal Algorithm” on page 414, record the removal time, and then
create a temporary sub-table containing time/voltage for only that corner/column.
2. Repeat for all the other columns (that contain data) in the table.
3. Repeat steps 1-2 for all the other tables in the model.
4. For each column, find the smallest stripping time (see step 5 of the algorithm
description). For the column that generated it, retain the temporary sub-table modified
by the initial delay removal algorithm. The removal time for this column is the “corner-
specific” removal time.
5. For the first corner, modify the other temporary sub-tables by doing the following:
a. Restore them to their original state.
b. Remove all points that occur earlier than the corner-specific removal time.

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c. Add a new first point at the removal time, with voltage value equal to the initial DC
time for this column.
d. Subtract the corner-specific removal time from each point in the table for that
corner/column, and make the time for the first point equal to 0.0.
6. Repeat steps 4-5 for the other corners.
7. Merge the temporary corner sub-tables (each containing one column) to create a full V-t
table (containing three columns) that contains a super-set of the rows/times from the
temporary sub-tables.
Figure 9-4 shows an example of what the temporary sub-tables for each corner might
contain.

Figure 9-4. Example Temporary Sub-Table Contents

Figure 9-5 shows the contents of the three sub-tables from Figure 9-4 merged into an
initial merged table.

Figure 9-5. Example Initial Merged V-t Table

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8. Replace each NA in Figure 9-5 with interpolated values from surrounding values or with
extrapolated values from nearby values.
9. If the number of rows in the initial merged V-t table does not exceed the maximum set
by the IBIS specification (for example, 100 for IBIS 3.x), then table processing is
complete and the modifications are written to the file.
10. If the number of rows in the initial merged V-t table exceeds the maximum, then rows
are removed per the option you select in step 2 in the procedure described by
“Removing Initial Delays from Individual IBIS Models” on page 419.

Removing Initial Delays from Individual IBIS Models

To remove initial delays from an IBIS model file already loaded in the Visual IBIS Editor:

1. IBIS menu > Remove Initial Delays. The Remove Initial Delays dialog box opens.
2. In the Correlation list, select one of the following:
• All tables correlated (recommended)— Correlate all columns in all V-t tables.
Select this option unless you have a reason not to.
• Rising and falling tables treated separately— Correlate [Rising Waveform] tables
to each other, and then correlate [Falling Waveform] tables to each other.
• Corners treated separately— Correlate min columns in all tables to each other.
Correlate typ columns in all tables to each other. Correlate max columns in all tables
to each other.
See “About the Initial Delay Removal Algorithm” on page 414.
3. In the V Threshold box, type in percentage of voltage below which voltage variations at
the beginning of the table are considered to be noise, as opposed to switching activity.
The value range is 0.01 to 0.2.
4. Click OK.

Removing Initial Delays from Multiple IBIS Models

Run IBISVTC from the command line to remove initial delays for all IBIS models in a folder or
from an individual IBIS model.

To run IBISVTC from the command line:

1. Open a command window. In Windows, use Start menu > Run > cmd. In
Linux/UNIX, open a new shell.
2. Change to the folder containing IBISVTC.exe (Windows) or IBISVTC (Linux/UNIX).

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This is the same folder containing the HyperLynx executable (bsw.exe or bsw).
Example: cd MentorGraphics\<release>\SDD_HOME\hyperlynx
3. To remove initial delays from all IBIS models in a folder:
IBISVTC in=<folder_path> out=<existing_folder_path> log=<file_path> [options]
Paths can be relative or fully qualified. To display complete command-line syntax
information, run IBISVTC.exe or IBISVTC with no options.
4. To remove initial delays from an individual IBIS model:
IBISVTC infile=<file_path> outfile=<file_path> log=<file_path> [options]

Examining and Editing V-I and V-t Curves

The Editor can display V-I or rising/falling waveform table data as a curve, which helps you to
visually find errors in the data, such as a mistyped number or bad sign.

The graphical display shows the table’s minimum, typical, and maximum curves, if available,
each in a different color. The display scales itself automatically to best fit the table data. To help
you examine a curve, the View IBIS Data dialog box offers a versatile set of controls, such as
zoom and pan.

This topic contains the following:

• “Viewing V-I or Waveform Tables” on page 420

• “Displaying Combined Clamp and V-I Data” on page 421
• “Measuring Curves and Waveforms” on page 422
• “Zooming Panning and Other Curve-Viewing Tools” on page 422
• “Graphically Editing V-I or V-t Curves” on page 424
• “Changing the Appearance of Curves or Legends” on page 426
• “Printing Curves” on page 427
To correct table data using the Editor's graphical curve-editing capabilities, see “Graphically
Editing V-I or V-t Curves” on page 424.

For examples of model problems that can be detected by viewing V-I or waveform curves, see
“Identifying Common IBIS Model Problems” on page 433.

Viewing V-I or Waveform Tables

To graphically view V-I or waveform table data:

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1. In the tree-view window right-click over Model, Component, or a table keyword, and
then click View data.
2. To select the type of data you want to view, click a tab below the toolbar.
To view data for a different table without leaving the View IBIS Data dialog box, click
the Select/Info tab and then select a new value in the Component, Signal, Pin, or Model
list.
If the model contains additional V-t tables for different test loads, you can select a
different test load from the Conditions list below the Rising Waveform or Falling
Waveform tab.
The Golden Waveforms tab is displayed when the IBIS model contains “golden”
waveforms for accuracy comparisons. The golden waveform is intended to show the
actual waveforms measured or simulated with the respective model in a simple circuit.
This provides a method to compare the simulation results with what the device vendor
declares to be correct.
3. If you have selected the Power Clamp or Pullup tab, select Vcc relative or Ground
relative, on the Display curves list.
The IBIS specification requires V-I data for the [Pullup] and [POWER Clamp] tables to
be "Vcc relative," which means the data values are referenced to Vcc. For example if the
Vcc-relative datum is 1v and Vcc=5v, the actual pin voltage is 5v-1v=4v.

Displaying Combined Clamp and V-I Data

The Editor can sum clamp and V-I table data, if they are available, into a single curve that
shows the model behavior over the combined voltage and current ranges.

To display combined clamp and V-I data:

1. In the View IBIS Data dialog box, click the Combine tab.
2. In the Combination list, click one of the following:
• Pullup + POWER Clamp
• Pulldown + GND Clamp
• Pullup + Both Clamps
• Pulldown + Both Clamps
• GND + Power Clamp
3. In the Display curves list, click Vcc relative or Ground relative.

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The IBIS specification requires V-I data for the [Pullup] and [POWER Clamp] tables to
be "Vcc relative," which means the data values are referenced to Vcc. For example if the
Vcc-relative datum is 1v and Vcc=5v, the actual pin voltage is 5v-1v=4v.
If you prefer to view the data as relative to ground, click Ground Relative on the
Display Curves list.

Measuring Curves and Waveforms

You can manually measure between two points on any curve in the View IBIS Data dialog box.
When viewing Pullup or Pulldown curves, this capability enables you to measure buffer
impedance based on two points on the V/I curve.

To measure curves and waveforms:

1. Measurement Mode button .

Alternative: Right-click over the graph and click Measure.
2. Click over the curve or waveform. A pair of measurement crosshairs tracks the selected
curve/waveform.
3. Click the first measurement point. A pair of measurement crosshairs attaches to the
measurement point.
4. Click the second measurement point. The Measurement Results dialog box displays the
measurement data.
5. Click OK to close the Measurement Results dialog box and the measurement crosshairs.

Zooming Panning and Other Curve-Viewing Tools

When you first open the View IBIS Data dialog box to view a table's curve, it automatically
scales itself to display all the table’s data.

This topic contains the following:

• “Resizing the View IBIS Data Dialog Box” on page 423

• “Zooming to Selection” on page 423
• “Fitting the Curve to Window” on page 423
• “Fitting the Curve to User-Defined Extents” on page 423
• “Tracking Curves and Waveforms” on page 423
• “Panning in the IBIS Editor” on page 424
See also: “Changing the Appearance of Curves or Legends” on page 426

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Resizing the View IBIS Data Dialog Box

Use standard Windows procedures to manipulate this dialog box.

To resize the View IBIS Data dialog box:

• Drag a corner or side of the window to resize it. The curves are automatically scaled to
fit the new window size.

Zooming to Selection
To zoom in:

1. Zoom to selection button .

Alternative: Right-click over the graph and click Zooming.
2. Drag the zoom rectangle to enclose the area you want to enlarge. The curves are
automatically scaled to fit the zoom rectangle.

Fitting the Curve to Window

To fit the curve to the window:

• Fit to window button . The curves are automatically scaled to fit the window.
Alternative: Right-click over the graph and click Fit To Window.

Fitting the Curve to User-Defined Extents

You can fit the curve to a rectangle you define by typing the time and voltage values for the
bottom-left and upper-right corners of the rectangle.

To fit the curve to user-defined extents:

• Set Zoom Extents button . The curves are automatically scaled to fit the rectangle
you defined.
Alternative: On the View menu, click Extents.

Tracking Curves and Waveforms

You can attach measurement crosshairs to a curve or waveform, so you can display exact values
for points on the curve/waveform as you move the pointer.

To track curves and waveforms:

1. Cursor Tracking Mode button .

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Alternative: Right-click over the graph and click Track Cursor.

2. Click over the curve or waveform.
3. Move the pointer to display the exact value of any data point on the curve/waveform.

Panning in the IBIS Editor

Panning moves the curves on the display's X- or Y-axis without changing the magnification.

To pan:

1. Panning button .
Alternative: Right-click over the graph and click Panning.
2. Click anywhere in the viewing area and drag the curves to the desired position.

Graphically Editing V-I or V-t Curves

In the View IBIS data dialog box, you can do any of the following to modify V-I and V-t table
data:

• Drag a point on a curve to a new location

• Add data points
• Remove data points
Requirement: This is a licensed feature and requires the purchase of a qualifying Mentor
Graphics product.

When you save the graphical edits, you cannot undo the changes. You may want to backup the
IBIS model file before editing the file.

To graphically edit V-I or V-t curves:

1. Display the curve you want to edit. If necessary, zoom in to the portion of the curve you
want to change.
See also: “Viewing V-I or Waveform Tables” on page 420
2. If the editing mode is disabled, right-click over the curve display area and click Editing.
Editing mode is enabled when the Enable Editing button is unavailable .
Restriction: Editing mode is unavailable for the Combine tab.
3. Click the curve to select it.

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If the pointer shape is not a hollow square, which indicates the curve selection mode,
right-click and click Select.
Result: When you select the curve, the Move point edit mode is automatically enabled
and the curve turns white.
4. If needed, right-click and select any of the following edit options:
• Rubber Curve—When you move a point, the viewer moves other points to
maintain a smooth curve.
• Vertical Motion—The viewer ignores horizontal pointer motions.
5. If needed, right-click and click any of the following edit modes:
• Move point
• Insert point
• Delete point
• Exact position
6. To the edit curve, move the pointer over the curve until a small square (the data point)
appears, and then do one of the following:
• Move point edit mode—Drag the point to the new location.
• Insert point edit mode—Click to insert a point.
• Delete point edit mode—Click to delete a point.
• Exact position edit mode—Click to select the point and open the Exact Point
Position dialog box. Type the position values into the boxes, and then click Apply or
OK.
If you have zoomed in on the curve, locating points on a curve is easier if you display
the curve's vertices. On the toolbar, click Display curve vertices only or Display
both lines and vertices .
7. To edit points on another curve, right-click and click Select, and then click the curve you
want to edit.
8. If needed, repeat steps 4-7.
9. To save the changes to the IBIS file, do the following:
• On the View IBIS data dialog box File menu, click Save.
• Close the View IBIS data dialog box.
• On the Editor File menu, click Save.
If you make changes that produce endpoint DC voltage mismatches between the V-I and
V-t tables, the Editor prompts you whether to correct the mismatches automatically. For

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information about endpoint DC voltage mismatches, see “V-t and V-I Table Data are
Mismatched” on page 443.

Changing the Appearance of Curves or Legends

You can change the appearance of the curves and legends displayed in the View IBIS Data
dialog box.

The following information applies to the File menu in the View IBIS Data dialog box, not the
Visual IBIS Editor.

This topic contains the following:

• “Plotting Table Data Using Curves Points or Both” on page 426

• “Changing Data Point Size” on page 426
• “Changing Curve and View Colors” on page 427
• “Changing Legend Font” on page 427
See also: “Zooming Panning and Other Curve-Viewing Tools” on page 422.

Plotting Table Data Using Curves Points or Both

To plot table data using only curves:

• Display lines between curve vertices button .

Alternative: View menu > Lines Only.
To plot table data using only points:

• Display curve vertices only button .

Alternative: View menu > Points Only.
To plot table data using both curves and points:

• Display both lines and vertices button .

Alternative: View menu > Both.

Changing Data Point Size

To change the data point size:

1. Set user preferences button .

Alternative: Edit menu > Preferences.

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2. In the View Data Preferences dialog box, select a new value from the Point Size list.

Changing Curve and View Colors

To change curve and viewer colors:

1. Set user preferences button .

Alternative: Edit menu > Preferences.
2. In the View Data Preferences dialog box, in the Colors area or in the Editing area, click
the color palette for the viewer element you want to change.
3. In the Color dialog box, choose a basic or custom color and then click OK twice.

Changing Legend Font

To change the curve legend font:

1. Set user preferences button .

Alternative: Edit menu > Preferences.
2. In the View Data Preferences dialog box, to the right of the Font box, click Choose.
3. In the Font dialog box, choose the font properties and then click OK twice.
To change the font used in the text editor, see “Setting Font Color and Tab Preferences” on
page 405.

Printing Curves
Print table data curves from the View IBIS Data dialog box. The curves are automatically scaled
to fit the paper specified in the standard Windows print setup options dialog box. You can
change the scale of the curves using the page layout options. The page layout and the standard
Windows print setup options can be set from this dialog box.

To print the graphed IBIS data:

1. In the View IBIS Data dialog box, click the tab for the graphed IBIS data you want to
print.
2. Print chart button .
3. If needed, change the printing options.
4. Click OK.
To set page layout options:

1. File menu > Page Layout.

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2. If needed, change the page layout options.

3. Click OK.
To set printer properties:

1. File menu > Print Setup.

2. If needed, change the printing options.
3. Click OK.

Checking and Correcting IBIS Models

The Editor provides several ways to detect and correct problems in IBIS models.

This topic contains the following:

• “Checking IBIS File Syntax” on page 428

• “Viewing the IBIS Specification” on page 430
• “Correcting V-t and V-I Table Mismatches Automatically” on page 430

Checking IBIS File Syntax

You can perform syntax and limited data checking on the IBIS model without leaving the
Editor. If you are creating or editing a model, you can periodically check the syntax of the
model to check whether you have introduced errors.

Several problems that can be detected by syntax or graphical verification are described in the
section “Identifying Common IBIS Model Problems” on page 433.

This topic contains the following:

• “Running the Syntax Checker on IBIS Models” on page 428

• “Jumping to a Line in the IBIS Model Containing a Syntax Violation” on page 429
• “Resolving Errors and Warnings” on page 430

Running the Syntax Checker on IBIS Models

The Editor can run the official EIA-656 (IBIS) validation-checking program (IBIS committee
parser) and, if you have Mentor Graphics ICX 3.1 or newer installed on the computer, it can
also run the ICX syntax checker.

To run the syntax validation check on the IBIS file using the IBIS committee parser:

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• Check file for IBIS spec conformance button .

To display warnings in the output window, click so that it appears to be recessed.
Errors are always displayed.
To run the syntax validation check on the IBIS file using the ICX parser:

• Check file for IBIS spec conformance (ICX parser) button .

To display warnings in the output window, click so that it appears to be recessed.
Errors are always displayed.
To specify ICX parser command-line options:

1. IBIS menu > ICX parser Command Line.

2. To ignore monotonicity errors in I-V tables, select the Ignore non-monotonicity in I-V
tables check box.
3. Type options into the box and click OK.
Use this option only if you need to. See the documentation that comes with ICX for information
about ICX parser command-line options.

Jumping to a Line in the IBIS Model Containing a Syntax

Violation
Linking, or cross probing, between the output and editor windows can help you quickly
associate the violation message to the line in the IBIS model causing the syntax violation.

Restriction: Linking is not available for syntax violations reported by the ICX parser. Linking
is supported only for IBIS committee parser violation messages that contain a line number.

To go to a line containing a syntax violation:

• In the output window, double-click anywhere on the violation message. The cursor
jumps to the line containing the syntax violation.
To go to the next warning or error:

• IBIS menu > Go To Next Error.

The cursor jumps to the line containing the next syntax violation and the line marker jumps to
the violation message in the output window.

To go to the previous warning or error:

• IBIS menu > Go To Previous Error.

The cursor jumps to the line containing the previous syntax violation and the line marker jumps
to the violation message in the output window.

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Resolving Errors and Warnings

You should always correct errors reported by the IBIS Golden Parser. Errors may prevent the
simulator from running or cause the simulator to produce unusual simulation results.

You should examine and judge warnings reported by the IBIS Golden Parser. Simulators will
accept models containing warning-level violations, but may produce incorrect simulation
results. Model developers should document in the [Notes] section of the IBIS model any
warnings that were not fixed.

You decide whether to fix an IBIS model or simply to document the warnings and their causes.
If the IBIS model was downloaded from a vendor, you should check with the vendor before
making any changes to the model.

If you edit an IBIS model, you should rerun syntax checking and graphical verification.

Viewing the IBIS Specification

The IBIS specification is available online from the Visual IBIS Editor.

To view the online IBIS specification:

• Help menu > IBIS Specification.

Correcting V-t and V-I Table Mismatches Automatically

A somewhat common syntax-checking warning reported by the IBIS Golden Parser is a
mismatch between the endpoint DC voltages in a V-t table and the endpoint DC voltages
predicted by the intersection of the load line and the V-I tables. For information about how the
IBIS Golden Parser identifies V-t and V-I table endpoint DC voltage mismatches, see “V-t and
V-I Table Data are Mismatched” on page 443.

Figure 9-6 illustrates how the endpoint DC voltages from the V-t table do not match the
endpoint DC voltages predicted by the intersection of the load line and V-I tables:

Figure 9-6. Endpoint DC Voltages do not Match Load-Line Analysis Prediction

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Errors in the V-t or V-I tables causing the endpoint DC voltage mismatch warning can be
tedious to fix. The Editor can automatically scale and vertically offset the V-t table data to fix
the DC voltage endpoint mismatch.

Figure 9-7 illustrates how the Editor scales and vertically offsets the original V-t curve to create
the corrected V-t curve:

Figure 9-7. Endpoint DC Voltages do Match Load-Line Analysis Prediction

Before using the Editor to automatically correct mismatches, you should first try to understand
why the mismatches occurred. You can look for reactance in the V-t data extraction process and
you can check the voltage references used in the V-I data sweeps.

If you are a model developer, you can use the Editor to check your work when graphically
editing V-t or V-I tables. If the edits create an endpoint DC voltage mismatch and you save the
edits, the Editor asks whether you want to correct the V-t tables.

See also: “Graphically Editing V-I or V-t Curves” on page 424.

If you are not a model developer, you can use the Editor to check the model for correctness, and
you can choose to correct the model yourself.

Restriction: This is a licensed feature and requires the purchase of a qualifying Mentor
Graphics product.

You can undo V-t corrections.

To correct a specific V-t table:

• In the tree-view pane, right-click the model, and then click Correct V-t tables.
Or

• If the graphical edits create a voltage mismatch and you save the edits, the Editor
prompts you whether to correct the V-t tables.
To correct all V-t tables in the IBIS model:

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• IBIS menu > Correct V-t tables.

Verifying IBIS Models

You can use the Editor to verify an IBIS (IO Buffer Information Specification) model. IBIS
models that you create or download from an IC vendor may have defects in them that prevent an
IBIS simulator from running or yielding the expected results.

The main steps to verify an IBIS model include:

1. “Checking IBIS File Syntax” on page 428

2. “Checking an IBIS Model V-I or Waveform Curves” on page 432
3. “Identifying Common IBIS Model Problems” on page 433
4. “Testing an IBIS Model” on page 449

Checking an IBIS Model V-I or Waveform Curves

One of the most valuable features of the Editor is its ability to graphically show V-I or
waveform table data. Viewing table data graphically makes it easier to find errors in the data.

Errors that can be easily found in the graphical viewer:

• Bad numerical value, possibly due to a typographical error

• Bad numerical sign
• Noise
• Non-monotonic behavior
The graphical viewer displays the table's data as a set of curves. If the data are available, the
minimum, typical, and maximum curves are displayed in different colors. The graphical viewer
scales itself automatically to best fit the table’s data.

The View IBIS Data dialog box provides controls such as zoom and pan, to help you focus on a
portion of a curve.

See also: “Zooming Panning and Other Curve-Viewing Tools” on page 422, “Identifying
Common IBIS Model Problems” on page 433

To view V-I or waveform table data graphically:

1. In the tree-view window right-click a keyword containing V-I or waveform table data
and then click View data. The View IBIS Data dialog box displays the table data for the
keyword.

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Click the plus sign in front of a keyword to expand the tree and display more keywords.
2. Click a tab below the toolbar to select the type of data you want to view.
For input buffers, there should be data for the Clamp diode curves and Pin Info tabs.
For output buffers, there should be data for the V/I curves and Pin Info tabs. V/t and
Clamp diode curves are optional.
To view data for a different table without leaving the View IBIS Data dialog box, click the
Select/Info tab and then select a new value in the Component, Signal, Pin, or Model list.

If the model contains additional V-t tables for different test loads, you may select a different test
load on the Conditions list below the Rising Waveform or Falling Waveform tab.

Identifying Common IBIS Model Problems

The following IBIS model problem descriptions are presented in a random order. Syntax or
graphical examples are provided when available.

This topic assumes that you are familiar with the IBIS specification. The Editor displays the
IBIS specification when you click Help menu > IBIS Specification.

You can read about any of following problems:

• “Data Have the Wrong Sign” on page 434

• “Data Have the Wrong Units” on page 436
• “Data Have Noise Properties” on page 437
• “Data Have Non-Monotonic Properties” on page 438
• “Data Have Spurious Points” on page 440
• “Data Do Not Follow Typ-Min-Max Order” on page 441
• “V-I Table Data Do Not Pass Through the Origin” on page 442
• “V-t or V-I Table Data are Missing” on page 443
• “V-t and V-I Table Data are Mismatched” on page 443
• “Paired Curves Do Not Have the Opposite Polarity” on page 448
• “Ramp Table Data Have Zero or Negative Values” on page 449
• “Vmeas Voltage Does Not Cross V-I Data” on page 449

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Data Have the Wrong Sign

Check for table data that have the wrong sign. You can detect data with the wrong sign by
looking at the table data graphically or by reading syntax-warning messages.

Syntax Example for Data Have the Wrong Sign

The following warning occurs when [Pullup] data have the wrong sign:

WARNING - Model Buffer1: Pullup has Increasing Current

Graphical Example for Data Have the Wrong Sign

Figure 9-8 shows [Pullup] current data with the wrong sign. A typical device sources current for
positive voltages and the IBIS specification defines current flowing out of the device as
negative. Figure 9-8 shows a positive current at voltages where a negative current is expected.

Figure 9-8. IBIS Model Error - Pullup Data with Wrong Sign

Special Explanation for Pullup Data

Wrong sign errors in [Pullup] data occur frequently enough to justify further explanation.

The voltage in a [Pullup] table is referenced to VCC. A positive [Pullup] voltage value
represents an offset toward ground. The equation to convert the [Pullup] table voltage to a
ground-referenced value is:

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VCC - [Pullup] table voltage = ground-referenced voltage.

For example if VCC=3.3V and [Pullup] table voltage=1.3V, the ground-referenced voltage is
2V.

Figure 9-9 and Figure 9-10 illustrate how the connections between the curve tracer and the
CMOS driver change when collecting [Pullup] data versus [Pulldown] data. For example,
connect the negative curve tracer probe to OUT to collect [Pullup] data but connect it to GND to
collect [Pulldown] data.

Figure 9-9. Test Bench Configured to Collect Pulldown Data

Figure 9-10. Test Bench Configured to Collect Pullup Data

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Table 9-1 shows a [Pullup] V/I table fragment in columns one and two. Column three calculates
the pin voltage when VCC = 3.3V.

Table 9-1. Calculated Pin Voltage with Respect to Ground

Table V Table I Calculated pin voltage with respect to ground when
VCC = 3.3V
-2V +1000mA 3.3V - (-2V) = 5.3V
-1V +100mA 3.3V - (-1V) = 4.3V
0V 0mA 3.3V - 0V = 3.3V
+1V -20mA 3.3V - 1V = 2.3V
+2V -35mA 3.3V - 2V = 1.3V

Data Have the Wrong Units

Check that the units for the X-axis and Y-axis have the correct magnitude. You can detect data
with the wrong units by looking at the table data graphically.

Graphical Example for Data Have the Wrong Units

Figure 9-11 shows [Rising Waveform] data with an amplitude exceeding 1250V. Assuming the
model represents a 3.3V product, the amplitude is too large. This error may result from a scaling
factor being dropped, such as the omission of "mV" in the [Rising Waveform] table.

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Figure 9-11. IBIS Model Error - Wrong Units for Y-Axis

Data Have Noise Properties

The characterization test hardware and setup may introduce noise or other artifacts into the data
table. These artifacts may not represent how the IO buffer switches in a "clean" environment.

Models that contain table data with noise or other artifacts of the test setup can lead to
artificially noisy simulation output waveforms.

Graphical Example for Data Have Noise Properties

Figure 9-12 shows a dip starting at 500ps and ringing that starts near 1.75ns.

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Figure 9-12. IBIS Model Error - Data with Noise Properties

Data Have Non-Monotonic Properties

V/I tables may have non-monotonic data in a single column. The term non-monotonic describes
data that reverse a trend of an ever-increasing or ever-decreasing numeric sequence. Constant
data values do not reverse a trend.

Switching to a monotonic perspective, the IBIS specification defines monotonic behavior as:

To be monotonic, the V/I table data must meet any one of the following 8 criteria:

1- The CURRENT axis either increases or remains constant as the voltage

axis is increased.
2- The CURRENT axis either increases or remains constant as the voltage
axis is decreased.
3- The CURRENT axis either decreases or remains constant as the voltage
axis is increased.
4- The CURRENT axis either decreases or remains constant as the voltage
axis is decreased.
5- The VOLTAGE axis either increases or remains constant as the current
axis is increased.
6- The VOLTAGE axis either increases or remains constant as the current
axis is decreased.
7- The VOLTAGE axis either decreases or remains constant as the current
axis is increased.
8- The VOLTAGE axis either decreases or remains constant as the current
axis is decreased.

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Syntax Example for Data Have Non-Monotonic Properties

The following message specifies the IBIS model's line number that contains non-monotonic
[Pulldown] data.

WARNING (line 80) - Pulldown Typical data is non-monotonic

WARNING (line 80) - Pulldown Minimum data is non-monotonic

WARNING (line 80) - Pulldown Maximum data is non-monotonic

Graphical Example for Data Have Non-Monotonic Properties

Figure 9-13 shows a dip in the V/I curves at 1.2V. The V/I curves in Figure 9-13 may be okay
because most simulators try to clean the data, but in general these negative-resistance regions
can cause simulation problems and probably do not reflect real device behavior.

Definition: Negative-resistance describes a segment of a V/I curve where the current shifts
toward 0mA while voltage shifts away from 0V.

Reexamine Figure 9-8. Does it represent non-monotonic data? Yes. If the data sign values were
corrected, would it be a problem? No. Figure 9-8 is an example of non-monotonic data resulting
from incorrect separation of the clamp current and output driver current. The simulator will add
these two curves back together so they are not a problem, unlike the non-monotonic glitch
shown in Figure 9-13.

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Figure 9-13. Curves Showing Non-Monotonic Data

Data Have Spurious Points

Individual data points may have the wrong value or the wrong scaling.

Syntax Example for Data Have Spurious Points

Spurious points are sometimes reported as non-monotonic data:

WARNING (line 465) - Pulldown Typical data is non-monotonic

Graphical Example for Data Have Spurious Points

Figure 9-14 shows a bad data point between –1V and 0V.

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Figure 9-14. IBIS Model Error - Spurious Datum

Data Do Not Follow Typ-Min-Max Order

Data table columns must be arranged in typical/minimum/maximum order.

Syntax Example for Data Do Not Follow Typ-Min-Max Order

WARNING (line 56) - Typ value is not in between min and max

Graphical Example for Data Do Not Follow Typ-Min-Max Order

You can double-check the pin parasitic data order by clicking on the Select/Info tab in the View
IBIS Data dialog box and examining data in the Model Info area.

Figure 9-15 shows that the typical capacitance is incorrectly less than the minimum capacitance.

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Figure 9-15. IBIS Model Error - Pin Information with the Wrong Data Order

V-I Table Data Do Not Pass Through the Origin

V/I curves typically pass through the origin (that is, zero volts and zero amperes).

However V/t waveforms do not pass through zero seconds when an arbitrary timing offset is
written into the IBIS model.

Graphical Example for V-I Table Data Do Not Pass Through the Origin
Figure 9-16 shows V/I curves with zero current at about -0.3V.

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Figure 9-16. IBIS Model Error - Pulldown Data Not Passing Through the Origin

V-t or V-I Table Data are Missing

V/I and V/t tables are required to simulate output and bi-directional IO buffers. The buffer type
determines which tables are required. The IBIS model for an Output buffer must contain the
[Pullup] and [Pulldown] tables, and optionally the [Rising Waveform] and [Falling Waveform]
tables.

The IBIS Golden Parser does not check for missing tables. However Mentor Graphics LineSim
product does. To use LineSim to catch this type of error, see “Testing an IBIS Model” on
page 449. This problem is also detected by Mentor Graphics BoardSim product.

V-t and V-I Table Data are Mismatched

The IBIS Golden Parser uses load line analysis to correlate V/t and V/I table data. Each V/t
table specifies V_fixture and R_fixture parameters that can be converted to a load line. When
the IBIS Golden Parser calculates the intersections between the load line and V/I curves, it
expects the intersections to predict the starting and ending DC voltages (or "endpoints") in the
V/t tables. The V/I and V/t data are mismatched when load line analysis predicts a DC voltage
that is over 2% different from the V/t table endpoint.

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Most simulators tolerate mismatches greater than 2%, at least somewhat. The size of the
mismatch is key. Mismatches between 0%-10% are probably okay and are accepted by most
simulators. Larger mismatches may cause simulation problems.

The Visual IBIS Editor can automatically correct V/t and V/I table mismatches. See “Correcting
V-t and V-I Table Mismatches Automatically” on page 430.

IBIS models may have multiple [Rising Waveforms] or [Falling Waveform] V/t tables. For
example, the V_fixture value may be 3.3V in one [Falling Waveform] table and 0V in another
[Falling Waveform] table. The IBIS Golden Parser checks all the V/t tables for mismatches with
the V/I tables.

This section discusses the following:

• “Load Line Analysis Example” on page 444

• “Syntax Example for V-t and V-I Table Data are Mismatched” on page 447

Load Line Analysis Example

Figure 9-18 shows the [Pulldown] and [Pullup] V/I curve. Key points:

• The Y-axis represents current and the X-axis represents voltage.

• The [Pullup] V/I curve has been referenced to ground to allow it to intersect the load
lines that will be plotted in Figure 9-18 and Figure 9-19.
[Pullup] V/I table data in the IBIS model are referenced to VCC. To generate the ground-
referenced [Pullup] V/I curve in Figure 9-18, Figure 9-18, and Figure 9-19, each of the table
data were subtracted from VCC (for example, 3.3V – 0.83V = 2.47V).

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Figure 9-17. Plotting the V/I Curves

Figure 9-18 shows the [Falling Waveform] load line plotted across the [Pulldown] and [Pullup]
V/I curves introduced in Figure 9-18. Key points:

• The load line is based on the R_fixture=50 Ohms and V_fixture=3.3V values from the
[Falling Waveform] table.
• A load line typically intersects 0ma at the voltage set by V_fixture.
• The intersection of the load line and the [Pulldown] V/I curve should predict the [Falling
Waveform] table's end value.
• The intersection of the load line and the [Pullup] V/I curve should predict the [Falling
Waveform] table's start value.

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Figure 9-18. Plotting the Falling Waveform Load Line

Figure 9-19 shows the [Rising Waveform] load line plotted across the [Pulldown] and [Pullup]
V/I curves introduced in Figure 9-18. Key points:

• The load line is based on the R_fixture=50 Ohms and V_fixture=0V values from the
[Rising Waveform] table.
• A load line typically intersects 0ma at the voltage set by V_fixture.
• The intersection of the load line and the [Pulldown] V/I curve should predict the [Rising
Waveform] table's start value.
• The intersection of the load line and the [Pullup] V/I curve should predict the [Rising
Waveform] table's end value.

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Figure 9-19. Plotting the Rising Waveform Load Line

Syntax Example for V-t and V-I Table Data are Mismatched
The data in this section correspond to Figure 9-18.

WARNING-Model Buffer1: The [Rising Waveform]

with [R_fixture]=50 Ohms and [V_fixture]=0V
has TYP column DC endpoints of 0.00V and 2.47v, but
an equivalent load applied to the model's I-V tables yields
different voltages ( 0.00V and 2.58V),
a difference of 0.00% and 4.41%, respectively.

The author has altered the last row of the message because the IBIS Golden Parser incorrectly
reports a very large difference value for very small mismatches, for example +0.000V versus -
0.000V. The unaltered message generated in August 2001 reported a "difference of 263.93%
and 4.41%, respectively."

Table 9-2 describes each of the mismatch message fragments.

Table 9-2. Message Fragments for V/I and V/t Mismatch Error
Message Fragment Description
Model Buffer1 The model name. This message applies to "[MODEL]
Buffer 1" in the IBIS model.
[Rising Waveform] The V/t waveform table name.
[R_fixture]=50 Ohms The R_fixture value from the [Rising Waveform] table.

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Table 9-2. Message Fragments for V/I and V/t Mismatch Error (cont.)
[V_fixture]=0V The V_fixture value from the [Rising Waveform] table.
TYP column The simulation condition. The TYP column is the second
column from the left in a V/t table.
DC endpoints of 0.00V and The [Rising Waveform] table's endpoint voltages are
2.47V 0.00V and 2.47V.
equivalent load applied to The load line intersects the V/I curves at 0.00V and 2.58V.
the model's I-V tables yields The terms V/I and I-V are interchangeable.
different voltages (0.00V
and 2.58V) 0.00V is the voltage predicted by load line analysis that
should match the starting endpoint, or pre-transition,
voltage in the associated V/t table. The intersection of the
[Rising Waveform] load line and the [Pulldown] V/I curve
predicts the starting [Rising Waveform] table voltage.

2.58V is the voltage predicted by load line analysis that

should match the ending endpoint, or post-transition,
voltage in the associated V/t table. The intersection of the
[Rising Waveform] load line and the [Pullup] V/I curve
predicts the ending [Rising Waveform] voltage.

[Pullup] table data are relative to VCC but this message

prints all voltages relative to ground. Subtract the voltages
in this message fragment from VCC to obtain voltages
that resemble the [Pullup] table data. For example, 3.3V –
2.58V = 0.72V.
difference of 0.00% and The differences between the predicted intersections
4.41%, respectively between the load line and the [Rising Waveform] table are
0.00% and 4.41%.

0.00% is the difference between the [Rising Waveform]

table's starting endpoint DC voltage and the voltage
predicted by load line analysis.

4.41% is the difference between the [Rising Waveform]

table's ending endpoint DC voltage and the voltage
predicted by load line analysis.

To calculate the difference:

[abs(endpoint DC voltage - predicted voltage) * (end DC
voltage)] * 100

Paired Curves Do Not Have the Opposite Polarity

The following paired curves must contain data with the opposite polarity.

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• Pullup and Pulldown

• Rising Waveform and Falling Waveform
• POWER Clamp and GND Clamp

Ramp Table Data Have Zero or Negative Values

The Ramp keyword should contain positive time values for the dV/dt_r and dV/dt_f
subparameters. A zero or a negative value is nonsensical and will likely cause troubles at
simulation.

The IBIS Golden Parser does not yet check for zero or negative dV/dt_r and dV/dt_f
subparameter values. However Mentor Graphics LineSim product does. To use LineSim to
catch this type of error, see “Testing an IBIS Model” on page 449. This problem is also detected
by Mentor Graphics BoardSim product.

Vmeas Voltage Does Not Cross V-I Data

The optional Vmeas sub-parameter for the [Model] keyword must define a voltage that is
crossed by the V/I table data. The IBIS Golden Parser reports a syntax warning when the IO
buffer cannot drive past Vmeas using the specified Rref and Vref sub-parameter values.

Syntax Example for Vmeas Voltage Does Not Cross V-I Data
WARNING - Model 'PCI': TYP VI curves cannot drive through Vmeas=1.5V
given load Rref=40 Ohms to Vref=0V

Testing an IBIS Model

If you own Mentor Graphics LineSim, you can verify that your IBIS model's driver will drive
into a set of recommended loads. Your model is probably bad if it cannot drive the
recommended loads with acceptable results.

The recommended loads assume the IBIS model you are creating represents a normal CMOS or
TTL push-pull driver that does not need any special external load to switch properly. You may
need to modify the loads to test drivers that do not fit this description. For example, an open-
drain driver won’t switch unless pulled up by an appropriate resistor. Similarly, ECL drivers
need a pull-down to Vtt.

Using LineSim to Test an IBIS Model

LineSim ships with two schematics that implement the recommended loads. The schematics are
typically located in the <design> folder. The following instructions assume you are familiar
with using LineSim. For help, see the LineSim documentation.

To test an IBIS model using LineSim:

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1. Copy the IBIS model you created to the library sub-directory, typically LIBS.
2. Load the schematic IBISTest.tln or IbisDiff.tln into LineSim.
Use IBISTest.tln to test a single-ended driver and use IbisDiff.tln to test a differential
driver.
3. Assign your IBIS model to all the outputs in the schematic.
4. If you are testing a bidirectional IBIS model, set the buffer to the output mode.
5. Open the Oscilloscope and click Start Simulation. The Oscilloscope displays the
simulation results.
The Oscilloscope automatically attaches scope probes.
6. Determine whether the simulation results are acceptable.

Creating IBIS Models with the Easy IBIS Wizard

The Easy IBIS Wizard ("Wizard" from now on) is a powerful model-generation utility that
automatically generates an IBIS model from the characteristics you provide. The Wizard's
series of dialog boxes interviews you about the characteristics of the component you want to
model. An IBIS model generated by the Wizard is syntactically correct and ready to simulate.

You can also view or edit an IBIS model previously created by the Wizard by opening the
model in the Wizard.

Restriction: This is a licensed feature and requires the purchase of a qualifying Mentor
Graphics product.

This topic contains the following:

• “About the Easy IBIS Wizard” on page 450

• “Opening the Easy IBIS File Creation Wizard” on page 451
• “Creating a New Model or Opening an Existing Model” on page 452
• “Easy IBIS Wizard Page Information” on page 453

About the Easy IBIS Wizard

The design of the Easy IBIS Wizard is intended to be easy to use. However, you may want to
familiarize yourself with several details about how it works.

This topic contains the following:

• “Text String Restrictions” on page 451

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• “Data Requirements” on page 451

• “Limitations for the Wizard” on page 451
• “About Hints Displayed by the Wizard” on page 451
See also: “Opening the Easy IBIS File Creation Wizard” on page 451

Text String Restrictions

The IBIS syntax specifies the maximum length of user-created text strings. If you try to type in
a string that is too long, the Wizard will not accept the extra characters. This cues you to shorten
the text string.

Data Requirements
The Wizard's Next and Finish buttons are unavailable until the required data are entered into the
boxes.

Limitations for the Wizard

Easy IBIS Wizard limitations:

• There is no direct support for ECL or pseudo-ECL models. If you need to generate such
a model, you can start with a standard technology type (like CMOS), then modify the
resulting IBIS file as needed to make it work for your ECL buffer. (See the IBIS
specification for details on the changes needed.) The CMOS model will be incorrect in
some important respects (like table reference voltages and model type), but will at least
give you a starting "skeleton" to work with. A second option would be to find an
existing ECL IBIS model and modify it (i.e., not use the Easy IBIS Wizard at all).
The IBIS syntax allows most numerical values without limits, but IBIS simulators will
sometimes have trouble with absurdly large or small values. The Models Wizard will
typically not warn you about unreasonable values and it may generate a model that some
simulators may not simulate properly.
• The Wizard creates IBIS v1.1 models. The Wizard does not create models containing
features from later versions of the IBIS language, such as V-T tables.

About Hints Displayed by the Wizard

The Hint area displays advice about entering data into the Wizard. The Hint text is context-
sensitive and will change, if necessary, when you click a list or box in the dialog box.

Opening the Easy IBIS File Creation Wizard

To open the Easy IBIS Wizard:

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• Visual IBIS Editor > IBIS menu > Easy IBIS Wizard.
Restriction: The Easy IBIS Wizard is unavailable if you have not purchased the
appropriate option.

Creating a New Model or Opening an Existing Model

The Starting Information page prompts you to specify information needed to create a new IBIS
model with the Wizard. Alternatively you can open an existing IBIS model in the Wizard from
this page.

This topic contains the following:

• “Creating New IBIS Models” on page 452

• “Opening Existing IBIS Models” on page 453
• “Resetting the Wizard” on page 453

Creating New IBIS Models

The Starting Information page prompts you for an integrated circuit name for the model you are
about to create. Every IBIS file can contain multiple buffer models that are tied together through
a pin out to make up a "component"; a component models a complete IC.

The IBIS specification requires the [File Name] keyword and IBIS model filename values to be
the same. The Wizard helps satisfy this requirement by basing the filename on the text you type
into the Integrated Circuit box.

To create a new IBIS model:

1. In the Integrated Circuit Name box type the name of the model you want to create.
This should generally be a fairly specific name; typically it might include manufacturer,
device, and package information.
Result: The IBIS File Name box is automatically filled in with the text you typed into
the Integrated Circuit Name box (up to 20 characters), plus the ".ibs" filename suffix.
2. In the Create In box, type the directory name into which you want the new model
written.
Alternative: Click Browse, select the directory in the Browse for Folder dialog box, and
then click OK.
3. Click Next to advance to the General Information page.

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Opening Existing IBIS Models

You can use the Wizard to edit or view an IBIS model previously created by the Wizard.

Requirement: If you open an IBIS model not previously created by the Wizard, you must
manually add the pin model information into the Wizard. This is because the Wizard does not
read pin models from an existing IBIS model. Instead, the pin model information that you enter
into the Wizard is stored elsewhere on your computer.

To open an existing IBIS model:

1. Click Open Existing File.

2. Select or type the existing IBIS model file name and then click Open.
Alternative: Double-click the file.
Result: The Wizard loads the contents of the IBIS model.
Restriction: IBIS models containing syntax errors cannot be loaded into the Wizard. If
the IBIS model contains syntax errors, open it in the Visual IBIS Editor to fix the syntax
errors and then retry opening the model in the Wizard.

Resetting the Wizard

When you open an existing IBIS model, the Wizard's pages are filled with the contents of the
IBIS model. To create a new IBIS model after opening an existing model, reset the Wizard to
clear the existing IBIS model data from the Wizard's pages.

To reset the Wizard:

• Click Reset.
Result: The Wizard pages are cleared.
Requirement: The Reset button is available only when an existing IBIS model has been
opened.

Easy IBIS Wizard Page Information

This section provides information about using each page in the Easy IBIS Wizard. The Help
button on the Wizard pages opens these topics.

Setting Model Name Type and Technology

To specify the model name, type, and technology:

1. In the Model Name box, type a name for your new buffer.

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2. In the Buffer Type list, select the buffer type that you're modeling.
3. In the Technology list, select either CMOS or TTL (that is, bipolar).
4. Click Next to advance to the Operating Parameters page.

Entering Header Information

The General Information page prompts you for several header keywords that contain vital
statistics for the file you are about to create.

The IBIS language version is required and indicates the data types that must be supported by
programs that read the IBIS file.

The manufacturer name is required to be supplied. Any reasonable entry can be made in the
manufacturer field; if you are creating a model but do not work for the company that actually
manufactures the silicon, enter your own company name.

Model developers are encouraged to include a file-creation date, file-revision number, and
copyright. This information helps both the developer and users of a model track multiple
revisions of the file. The copyright notice protects the model legally.

To enter header information:

1. Type text into the appropriate boxes.

The data in these fields is free form, although the IBIS Version and File Revision boxes
typically contain a number.
The typical copyright form is "Copyright <year>, <manufacturer name>, All Rights
Reserved". For example: Copyright 2001, XYZ Corp., All Rights Reserved
2. Click Next to advance to the Source Information page.

Choosing a Pre-Defined Buffer Model

This topic contains the following:

• “About the Pre-Defined Buffer Models that Ship with the Wizard” on page 454
• “Mapping Power and Ground Pins” on page 455
• “Single-Pin versus Multi-Pin Models” on page 455

About the Pre-Defined Buffer Models that Ship with the Wizard
The pre-defined buffer models are classified by several categories:

• Technology: CMOS or TTL?

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• Power supply: 5-V or 3.3-V?

• Switching speed: Slow, medium, fast?
• Type: I/O (i.e., bi-directional), output-only, or input-only?
If you can categorize the IC buffer you're trying to model by these criteria, then you can choose
the proper pre-defined model for the buffer.

The switching speeds in the pre-defined buffer models (fast, slow, etc.) equate to approximately
the switching times shown below.

Switching time for pre-defined buffer models:

• CMOS, 3.3V, ULTRA-FAST = 0.3 ns

• CMOS, 3.3V, FAST = 1 ns
• CMOS, 3.3V, MEDIUM = 3 ns
• CMOS, 5V, ULTRA-FAST = 0.3 ns
• CMOS, 5V, FAST = 2.5 ns
• CMOS, 5V, MEDIUM = 6 ns
• CMOS, 5V, SLOW = 15 ns
• TTL, 5V, FAST = 3 ns rising / 2 ns falling
• TTL, 5V, MEDIUM = 6 ns rising / 4 ns falling

Mapping Power and Ground Pins

For power and ground pins, the IBIS specification uses special, reserved keywords. When you
map the pins on your IBIS component, map power pins to pre-defined buffer model POWER,
and ground pins to model GND.

Single-Pin versus Multi-Pin Models

Although you would normally create an IBIS model that has as many pins as the actual IC
you're trying to model, there are occasions when you might create a single-pin model. One
example would be to test a single custom ASIC buffer that is of interest: you are focused on one
buffer type and do not know or do not care about how it will be pinned out in the eventual
silicon.

There is a slight behavior difference between single-pin and multi-pin IBIS models. When you
map pins to buffer models, if the IBIS component is multi-pin, you are required to map at least
one pin to a power-supply buffer. However, if the component is single-pin, then the Wizard
assumes you are not modeling a real pin out and relaxes this restriction.

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Specifying Clamp Diodes

To specify the data for clamp diodes:

1. In the High Rail Clamp Diode area, select the clamp type.
If the buffer has no high-side clamp diode, choose None.
If there is a clamp diode, choose between silicon and Schottky diodes (check the IC data
sheet for which is correct) and then choose an approximate clamping strength (strong,
typical, weak).
If you know little about the diodes, select Silicon Typical.
If you know in detail about the diode's characteristics, choose Silicon—Custom or
Schottky—Custom, and then type the appropriate value into the On Impedance box.
2. Repeat step 11for the Low Rail Clamp Diode.
3. Click Next.

Setting Operating Voltage - Die Capacitance - Thresholds -

Scaling Factors
To specify the operating voltage, die capacitance, thresholds, and scaling factors:

1. In the Operating Voltage box, type the typical Vcc value for the IC.
2. In the Die Capacitance box, type the typical die capacitance for this buffer.
Die capacitance represents I/O capacitance, which is almost always given in the IC data
sheet, minus the package capacitance. A typical value range is 2-8 pF.
3. In the Logic High Threshold box, type the value of the worst-case high-going threshold.
Steps 3 and 4 apply only if buffer is type Input or I/O; do not apply if Output, 3-State, or
Open Sink/Source.
For most devices this is 2.0V. it may be higher for certain older CMOS families, like
HC. It may also be different for newer, very-low-Vcc devices.
4. In the Logic Low Threshold box, type the value of the worst-case low-going threshold.
For most devices this is 0.8V. However it may be different for certain older CMOS
families, like HC. It may also be different for newer, very-low-Vcc devices.
5. In the Min Scaling Factor box, type the value of the worst-case (that is, slowest/weakest)
scaling factor.
See also: “Entering Min-Max Scaling” on page 464
6. In the Max Scaling Factor box, type the value of the best-case (that is, strongest/fastest)
scaling factor.

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7. Click Next to advance to the Clamp Diodes page.

Specifying Pull-Up and Pull-Down Buffers

Specifying Pull-Up Buffers

Specifying pull-up (output high) data applies only for output, I/O, 3-state, and open source
buffers. The Models Wizard will automatically skip the Output High Parameters page for input
and open sink buffers.

To specify the high-side driver-transistor parameters:

1. In the Open Circuit Voltage box, type the DC voltage at which the driver "sits" when it
is unloaded (that is, no external load) and switched high.
For standard CMOS outputs, this generally equals Vcc; for bipolar, NMOS, and
specialty outputs, it is different than Vcc.
2. In the Saturation Current box, type the approximate maximum or saturation current of
the transistor stage, in Amperes. Every output design differs, but all technologies limit at
some reasonable value.
3. In the Output Impedance box, type the approximate driving impedance of the buffer.
See also: “Determining Output Impedance” on page 464
4. In the Slew Time box, type the amount of time it takes the driver to slew from 20% to
80% of the final DC values (in ns, rising edge).
5. In the Slew Voltage box, type the voltage difference between the 20% and 80% final DC
values (in ns, rising edge).
6. In the Pull Up/Down Load Resistance box, type the value of the resistance into which
the driver's rising-edge switching characteristics are specified (check the data sheet).
If you do not know the value, type "50".
7. Click Next.

Specifying Pull-Down Buffers

Specifying pull-down (output low) data applies only for output, I/O, 3-state, and open sink
buffers. The Models Wizard will automatically skip the Output Low Parameters page for input
and open source buffers.

To specify the low-side driver-transistor parameters:

• Repeat steps 11-77 in the preceding section, except enter the data for the low-side
transistor stage.

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Specifying Output Polarity and Load Circuit

Specifying output polarity and load circuit data applies only for output (any type) and I/O
buffers. The Models Wizard will automatically skip the Load and Logic page for input buffers.

To specify output polarity and manufacturer load circuit:

1. In the Polarity list, select the buffer's output polarity.

For most devices, the value is Direct.
2. In the Vmeasure box, type the voltage at which the manufacturer of the IC considers the
output buffer to have switched for timing measurements, for example, propagation
delay.
For most devices, this value is 1.5V. It may be different for newer, very-low-Vcc
devices.
3. In the Rref, Vref, and Cref boxes, type the circuit values that describe the manufacturer's
standard test loads for timing measurements.
This information is almost always specified in the data sheet. If it is not, use the default
values of 1000 ohms, 0V, and 50 pF.
4. Click Finish.
Result: The Wizard returns to the Edit Models page, where you can add additional new
buffers, if needed.

Entering Pin Data - Selecting Buffers - Creating or Editing the

Model
This topic contains the following:

• “About the Pin Table” on page 458

• “Modifying Pin Data and Selecting Buffers” on page 459
• “Creating the IBIS Model” on page 459
• “What to do With the New Model You Have Just Created” on page 460

About the Pin Table

The Pin table in an IBIS file lists the component pin's pin name, signal name, buffer model
name, and an optional set of pin-specific package parasitics (R_pin, L_pin, and C_pin). The
package data are optional on a per-pin basis. If no pin-specific parasitics are supplied, then all
pins will be simulated using the default package parasitics specified on a previous Wizard page.
If pin-specific parasitics are supplied for some pins and not others, then the pins with parasitics
will be simulated using the pin-specific values, and the pins without will use the default values.

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Modifying Pin Data and Selecting Buffers

Every pin in an IBIS file is required to have a pin number, signal name, and model (including
the reserved models named POWER, GND, and NC). The Easy IBIS Wizard creates a default
pin number, signal name, and model value for every pin, but you should modify the pin data to
match the signals on the IC you are modeling.

The pin data are displayed in spreadsheet cells on the Edit Pins page. You can edit the pin data
value for an individual cell or for a group of cells in a column.

There is no requirement to map every pin to a model, but since pins by default are "no
connects," any pins that you do not map will not be available for analysis in an IBIS simulator.

The spreadsheet supports many standard Windows editing accelerator keys (that is, key
combinations), such as CTRL+Z to undo the last change, CTRL+C to copy the selected text
from a cell to the Windows clipboard, and CTRL+V to paste the contents of the Windows
clipboard into a cell.

Creating the IBIS Model

When you have successfully defined your IC component, created buffer models for all of its
pins, and mapped the buffer models to the pins, you are ready to generate the IBIS file
representing the IC. The power of the Easy IBIS Editor is that it generates the file automatically
for you, with the correct syntax.

You can modify individual spreadsheet cells or a group of spreadsheet cells.

To modify the value of an individual cell and generate the model:

1. In the spreadsheet, click the pin property that you want to change.
2. Type or select the new value.
For information about creating a new buffer or editing an existing buffer, see “Creating -
Editing - Deleting Buffer Models” on page 460.
3. Repeat steps 11-22 as needed.
4. Click Finish.
Result: The Wizard automatically generates the IBIS file and then opens it in the Visual
IBIS Editor for viewing and editing.
To modify the value of a group of spreadsheet cells and generate the model:

1. In the spreadsheet, click the row header button and drag to select the rows you want to
modify.
Alternative: Click the column header button to select all the rows.

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Result: The Group Edit list becomes available.

2. In the Group Edit list, select the column of cells you want to modify.
Result: If you selected Names or Signals in the Group Edit list, the Prefix box and
Numerate list become available.
For information about creating a new buffer or editing an existing buffer, see “Creating -
Editing - Deleting Buffer Models” on page 460.
3. Type or select the new value.
4. Click Apply.
5. Repeat steps 11-44 as needed.
6. Click Finish.
Result: The Wizard automatically generates the IBIS file and then opens it in the Visual
IBIS Editor for viewing and editing.

What to do With the New Model You Have Just Created

At this point, there are several things you can do with your new IBIS model:

• Verify the model does not contain common IBIS model problems.
• Modify the model, using the text-editing features in the Visual IBIS Editor.
• View the V-I or waveform table data as a set of curves, using the graphing features in
the Visual IBIS Editor.
See also: “Verifying IBIS Models” on page 432, “Viewing V-I or Waveform Tables” on
page 420

Creating - Editing - Deleting Buffer Models

The "core" element in an IBIS file is one or more buffer models. Signal-integrity simulators use
these models to produce the analog waveforms that are used to analyze transmission-line effects
and other high-speed phenomena. The pin table in an IBIS file connects pins/signals with
underlying buffer models. Once you have defined the pin table in the Easy IBIS Wizard, you
must then create models for the various buffer types present on your IC.

Almost any real IC has at least two buffer types, a basic output or I/O buffer, and an input
buffer. Large, complex devices may have many different buffer types, for example, a very
strong output buffer on clock-signal outputs, a medium-strength buffer used for address and
data lines, and a relatively weak buffer used for non-critical signals. There might also be
multiple input-buffer types, with different input capacitances or clamp-diode strengths, for
example.

This topic contains the following:

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• “How the Wizard Models Buffers” on page 461

• “Pre-Defined Versus User-Created Buffer Models” on page 461
• “Creating a New Buffer Model” on page 461
• “Editing an Existing Buffer Model” on page 462
• “Deleting an Existing Buffer Model” on page 462

How the Wizard Models Buffers

In the IBIS specification, buffers are described with V-I tables. In the Easy IBIS Wizard, to
simplify the data-entry process, these tables are generated from single-valued impedances plus
saturation currents. The Wizard uses this data along with internal knowledge about transistor V-
I curves for various technologies (like CMOS or TTL) to generate detailed V-I curves from the
simplified impedance and saturation data.

In addition, output buffers have slew-rate data, which in the IBIS specification can either be
input as a simple slew rate into a given resistive load, or in a more-complex V-t table. The
Wizard uses the slew-rate/load method.

Pre-Defined Versus User-Created Buffer Models

The Easy IBIS Wizard allows you to either create your own custom buffers, or if you're in a
hurry or don't know the exact characteristics of the buffer you're trying to create, base your
model on a generic, technology-based buffer. Creating a custom buffer requires you to know the
approximate driving impedance of the buffer, slew rate, and so forth. Basing a model on a pre-
defined buffer requires only that you know the technology type of the model (CMOS or TTL?)
and the approximate slew rate (fast, medium, slow?). When you base a model on a pre-defined
model, you can either use the pre-defined model "as is," or use it as a starting point and then
modify some of its characteristics.

Creating a New Buffer Model

To create a new buffer model:

1. In the Edit Pins page, click Edit Models.

2. Click Add.
Alternative: To base the new buffer model on data from an existing model, select the
existing model from the Models list and then click Copy.
See also: “Setting Model Name Type and Technology” on page 453.
3. Repeat step 22 as needed.
4. Click OK to return to the Edit Pins page.

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Editing an Existing Buffer Model

To edit an existing buffer model:

1. In the Edit Pins page, click Edit Models.

2. In the Models area, click the buffer you want to edit.
3. Click Edit.
See also: “Setting Model Name Type and Technology” on page 453.
4. Repeat steps 22-33 as needed.
5. Click OK to return to the Easy IBIS Wizard's Edit Pins page.

Deleting an Existing Buffer Model

To delete an existing buffer model:

1. In the Edit Pins page, click Edit Models.

2. In the Models area, click the buffer you want to delete.
3. Click Delete.
4. Click OK to return to the Easy IBIS Wizard's Edit Pins page.

Entering Notes
The [NOTES] section of an IBIS file can be used to add for the user any amount of clarifying
detail about the model that is not already captured in the preceding fields. Typical information
included here might be caveats about data missing from the model; descriptions of when the
model is most accurate, and when it is not; and so forth.

The [NOTES] section can also contain information about whom to contact regarding the model.
The contact information is optional (although encouraged, since they give the user of the model
someone to query if technical questions arise). When the IBIS file is generated, the contact
information, if present, is preceded by the phrase "If you have comments concerning this file,
please address them to:".

To enter notes:

1. Type the appropriate text into the boxes.

The data in this field is free form, and often spans multiple lines. Use as much detail as is
needed.
When the Easy IBIS Wizard writes out the Notes section, it will wrap it as needed to
prevent from exceeding the 80-character line-length restriction imposed by the IBIS

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specification. This means that the text may not appear exactly as you enter it on this
page of the Wizard.
2. Click Next to advance to the Device Package page.

Entering Package Pin Count and Parasitics

Every IBIS file is required to contain a pin out table that lists the pins on the IC component
being modeled, and connects each pin to a buffer model in the file (or specifies that a pin is a
power pin or not connected).

Every IBIS file is also required to contain a package table defining the default package
parasitics (that is, R_pkg, L_pkg, and C_pkg) to be assumed for pins for which no pin-specific
parasitic data are explicitly specified. The package table is required to contain at least one pin,
although in a complete model it would contain an entry for every pin on the IC. The package
parasitic data can be all 0.0, although doing so will omit package effects from consideration
when the model is simulated.

Predefined versus User-Defined Packages

You can specify either your own user-defined package, or start with a predefined one. You
specify the number of pins on the package, or use a predefined package, whose definition
includes not only a fixed number of pins, but also parasitic R/L/C data for the package.

The R/L/C parasitics will be used to model the bond wires and package pins. The R/L/C
parasitic values included in a predefined package represent typical values for a package of that
style (e.g., larger values for DIPs, smaller for SMD packages, etc.). The advantage to using a
predefined package is that it comes "for free" with a complete list of pins and parasitics,
meaning you have less data to enter than with a user-defined package. However, there may not
be a predefined package that matches the IC you're trying to model, so you may need to create
your own.

To select a package and define default parasitic values:

1. In the Package list, click the name of the predefined package.

Alternative: To create your own user-defined package, click Custom and then type the
number of pins for your package into the Number Of Pins box.
• If necessary, change the default values in the boxes in the Default Parasitics area.
These values will be used during simulation for any pins that do not have pin-specific
R/L/C values that are specified later in the Wizard. The values can be 0.0 if you do not
wish to simulate package parasitic values, which provides a less-accurate simulation, but
is acceptable.
See also: “Entering Min-Max Scaling” on page 464
1. Click Next to advance to the Edit Pins page.

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Entering Min-Max Scaling

Throughout an IBIS file, data can be supplied either with a typical value only, or with typical,
minimum, and maximum values. In the Easy IBIS Wizard, to keep entry of a model simple and
yet still provide for minimum and maximum data, the values you enter are used as "typical," and
then two scaling factors are used to generate min/max data automatically from the typical
values. This is a reasonable approach, since ICs are subject to process variations that cause
various circuit parameters to scale up and down.

Using this approach, if you have more exact min/max data and want to include it in your model,
you can generate the IBIS file and then manually edit it to replace the min/max values created
by the Wizard.

Most minimum and maximum values written by the Wizard are created with the scaling factors.
An exception is the power-supply min/max values, which are automatically set to +/-10% of the
typical value you enter.

Entering Data Source and Disclaimer Information

Near the top of an IBIS file, model developers are encouraged to specify, in detail if needed, the
source of the model's data. In particular, users are interested in knowing whether the model was
developed from measured or simulated data, and any other information pertinent to how the
model was created.

The [DISCLAIMER] section of an IBIS file is primarily for use by semiconductor

manufacturers. It is typically used to disclaim legal responsibility for the model's accuracy,
suitability, and so forth.

To enter source and disclaimer information:

1. Type the appropriate text into the boxes.

The Wizard suggests a typical starting phrase and disclaimer, but its use is not required.
The data in this field is free form, and often spans multiple lines. Provide as much detail
as is needed.
When the Easy IBIS Wizard writes out the Source and Disclaimer sections, it will wrap
it as needed to prevent from exceeding the 80-character line-length restriction imposed
by the IBIS specification. This means that the text may not appear exactly as you enter it
on this page of the Wizard.
2. Click Next to advance to the Notes page.

Determining Output Impedance

IC datasheets do not always specify driver output impedances. Lacking a manufacturer's
specification for impedance, there are several ways to obtain it, as described in the following
sections.

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Measure from Published V-I Curves

Many manufacturers are now publishing (or have readily available) V-I curves for their output-
buffer stages (high and low). If you can obtain such curves, output impedance is easy to
calculate.

To measure impedance from a V-I curve:

1. Draw a straight line along the linear portion of the V-I curve, before the current "flattens
out" or saturates.
2. Take two points on the line. Measure delta(v) and delta(i) between the points.
3. Then calculate the output impedance as Zout = delta(v) / delta(i)

Extract from a SPICE Model

Mentor Graphics has an application note describing how to extract output-impedance from a
SPICE buffer model. See the section "Finding Driver Resistance from a SPICE Model" in
“Converting SPICE Models to HyperLynx Databook Format” on page 1336.

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Chapter 10
Assigning Models to Pins

You can interactively assign models to pins on components in the schematic or board. For IC
models, you also set IC buffer direction or state and assign power supplies to ICs.

This topic contains the following:

• “Interactively Selecting IC Models” on page 467

• “Setting IC Buffer Direction-State” on page 477
• “Assigning Power Supplies to ICs” on page 478
• “Copying Models” on page 480
• “Removing Models” on page 483

Related Topics
“Selecting Models and Values for Entire Components”

“About the MOD Libraries” on page 503

“Searching for Models” on page 505

“About IC Models” on page 506

“Editing IC Models” on page 513

“Reference Information for Selecting Models Interactively” on page 485

“Selecting and Creating Ferrite-Bead Models” on page 526

Interactively Selecting IC Models

Use the Assign Models dialog box to interactively select an IC model for a component or
schematic pin.

This topic contains the following:

• “Opening the Assign Models Dialog Box” on page 468

• “Assigning IC Models in Pins List” on page 469
• “Selecting IBIS - MOD - PML Models” on page 469

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• “Selecting SPICE and S-Parameter - Touchstone - Models” on page 471

• “Selecting IBIS Models Located Inside EBD Models” on page 473
• “Selecting Models for Programmable Buffers” on page 475
• “Tips for Selecting Models for Differential Pair Pins” on page 475
In the free-form schematic editor, you can assign SPICE or S-parameter models to S-
Parameter/SPICE Model symbols.

Restriction: .EBD models can only be mapped by automapping files.

Related Topics
“About the Assign Models Dialog Box” on page 485

“Viewing Series Bus Switch Pin Connectivity” on page 492

“Selecting S-Parameter and SPICE Models for Packages and Connectors”

“How ICs are Modeled for Signal-Integrity Simulation” on page 507

“IC-Model Formats” on page 507

“Editing IC Models” on page 513

“Assigning Models to Pins” on page 467

Opening the Assign Models Dialog Box

Table 10-1 contains the methods to open the Assign Models dialog box:

Table 10-1. Methods to Open Assign Models Dialog Box

Tool Method
LineSim free-form schematic editor Double-click the component
LineSim cell-based schematic Right-click over the component
editor
BoardSim Select the net or reference designator and, on the
toolbar, click Select Component Models or Edit
Values
Or
Right-click over the component pin and click
Assign Model

See also: “Selecting Nets for SI Analysis”

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Assigning IC Models in Pins List

For an IC component, you can interactively choose an IC model for any pin that appears in the
Assign Models pins list, even if the pin appears in the list by mistake. For example, if a resistor
is somehow mapped to component type IC, it can only be modeled as an IC and not as a resistor.
By contrast, you cannot choose a non-IC model for an IC component.

While many common reference-designator mappings are provided by default, if the mapping is
wrong or incomplete, you can edit it.

See also: Edit Reference Designator Mappings Dialog Box

Selecting IBIS - MOD - PML Models

To interactively select .IBS, .MOD, and .PML models:

1. If you have a MultiBoard project open, do the following:

a. Select the board ID from the Design File list.
If the selected net spans more than one board, you can assign models to selected net
pins located on other boards. The Pins list is empty if the selected net does not
connect to the board in the Design File list.
b. To apply the IC model selection or its driver settings to all instances of the selected
board, select the Apply To All Similar Boards check box.
This option applies only to the selected pin.
This option takes effect when you perform step 2. Make sure the check box is set the
way you want before performing step 2.
This option is displayed when more than one copy, that is, instance, of a board exists
in the MultiBoard project. For information about multiple instances and why you
might want to select or clear the check box, see “Saving Session Edits for Multiple
Board Instances”. The check box is automatically selected when you assign the same
model to all instances of a board.
2. In the Pins list, double-click the reference designator/pin for the IC driver or receiver pin
to which you want to assign a model. The Select IC Model dialog box opens.
Restriction: You can assign IC models only to IC and connector pins. For information
about the component symbols in the Pins list, see “Pins List Icons” on page 487.
3. In the Libraries list, select the library containing the model you want to use.
To filter the Libraries list, click a model format to the left of the Libraries list, click
TECH.MOD (basic technology models), or click GENERIC.MOD (standard logic
models). See “TECH-MOD Library” on page 503 and “GENERIC-MOD Library” on
page 504.

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To search all libraries for a model, click Find Model.

The I/O type area displays model information and is updated when you select items in
the Libraries, Devices, or Pin/Signal lists.
4. Do one of the following:
• If you selected an .IBS library, do the following:
i. Select the device in the Devices list.
ii. Select the pin/signal in the Pin/Signal list.
iii. Select Model Selector (if available) to select the model buffer, and then click
OK.
See also: “Selecting Models for Programmable Buffers” on page 475
iv. To toggle between the Signal and Pin lists, click Signal or Pin in the Select By
area.
v. Optionally for LineSim schematics only, select Assign model’s pin name to
automatically assign the IBIS pin name to the IC symbol in the schematic.
• If you selected a .PML library, select the device in the Devices list, and then double-
click the pin/signal in the Pin/Signal list. To toggle between the Signal and Pin lists,
click Signal or Pin in the Select By area.
• If you selected a .MOD library, double-click the device in the Devices list.
Result: The Select IC Model dialog box closes and the Assign Models dialog box
becomes available.
5. Click Edit Model File to display the contents of the selected model file without closing
the Assign Models dialog box. The appropriate model file editor opens.
6. If you assigned an output or bidirectional model, select its direction or state in the Buffer
Settings area.
7. Verify the power supply assignments and voltages in the Vcc Pin and Vss Pin lists.
You can power the driver or receiver from any two power-supply nets, or from the
typical voltage contained in the model.
For power-supply nets, you can edit Vcc or Vss voltages.
See also: “Editing Power-Supply Net Properties” (LineSim), “Editing Power-Supply
Nets” (BoardSim)
8. If you assigned a differential model, do the following:
a. In the Buffer Settings Area, click Output for the + or positive pin, or click Output
Inverted for the - or negative pin.

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b. In the Model to Paste area, click Copy.

c. In the Pins list, select the other differential pair pin.
d. In the Model to Paste area, click Paste, and then repeat step a for the other
differential pair pin.
If you have a MultiBoard project open, the paste behavior depends on the Apply To All
Similar Boards check box value. If the check box is selected, the model is pasted to all
instances. If the check box is cleared, the model is pasted to only the current instance.
If you are using BoardSim and the Pins list does not display the other differential pair
pin, see “If Second Pin is Not Visible” on page 502 for possible reasons why.
See also: “Tips for Selecting Models for Differential Pair Pins” on page 475
9. If you assigned a .MOD model in LineSim, and want to model package parasitics
exactly, click the .MOD Pin Parasitics tab and type pin values.
See also: “Editing Parasitic Values”
10. Repeat steps 1-9 as needed to select models for other driver or receiver pins.
11. Click Close.
Result: In LineSim, you return to the schematic editor and the model names are
displayed next to the IC. In BoardSim, you return to the board viewer and the model
names are not displayed in the board viewer.

Selecting SPICE and S-Parameter - Touchstone - Models

Caution
If you assign multiple Touchstone models, make sure the main file names (not just the
extensions) are different. For example, assigning connector.s2p and connector.s4p to the
design can produce inaccurate simulation results.

The ADMS simulator converts the Touchstone models to fitted-poles models before
running simulation. Because fitted-poles models have the .PLS extension, connector.s2p
and connector.s4p are both converted to connector.pls. Once a fitted-poles file is
available, ADMS uses it instead of again fitting the Touchstone model.

Continuing the example, if you run the first simulation with connector.s2p (which
produces connector.pls) and run the second simulation with connector.s4p, the second
simulation uses the fitted-poles file converted from connector.s2p.

To interactively select SPICE and Touchstone models:

1. If you have a MultiBoard project open, do the following:

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a. Select the board ID from the Design File list.

If the selected net spans more than one board, you can assign models to selected net
pins located on other boards. The Pins list is empty if the selected net does not
connect to the board in the Design File list.
b. To apply the IC model selection or its driver settings to all instances of the selected
board, select the Apply To All Similar Boards check box.
This check box is displayed when more than one copy, that is, instance, of a board
exists in the MultiBoard project. For information about multiple instances and why
you might want to select or clear the check box, see “Saving Session Edits for
Multiple Board Instances”. The check box is automatically selected when you assign
the same model to all instances of a board.
2. In the Pins list, double-click the reference designator/pin for the IC driver or receiver pin
to which you want to assign a model.
Result: The Select IC Model dialog box opens.
Restriction: You can assign IC models only to IC and connector pins. For information
about the component symbols in the Pins list, see “Pins List Icons” on page 487.
3. In the Libraries or Files list, select the file containing the model you want to use.
To filter the Libraries or Files list, click a model format to the left of the Libraries or
Files list.
To search all the libraries for a model, click Find Model.
4. In the Devices or Models list, double-click the model.
Result: The Select IC Model dialog box closes and the Assign Models dialog box
becomes available.
To display the contents of the model file without closing the Assign Models dialog box,
click the Edit Model File button.
5. If you have assigned an output or bidirectional model, click Output in the Buffer Is An
area.
6. Use the spreadsheet to map the model ports to pins and power-supply nets on the board
or schematic. For each port, click in the Circuit Connection cell and select the
appropriate connection from the list.
Requirement: If you are using the free-form schematic editor and are assigning an
instance of a model to more than symbol in the schematic, specify the same reference
designator for the symbols sharing the model instance. Specify the reference designator
and pin information in the Reference Designator and Pin Name boxes. For the free-form
schematic editor, the Circuit Connection list displays only pins for one reference
designator.

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For information about using the spreadsheet and the SPICE simulation characteristics
items that appear immediately below the spreadsheet, see “Using the Port-Mapping
Spreadsheet” on page 495.
For power-supply nets, you can edit Vcc or Vss voltages. For information, see “Editing
Power-Supply Nets” (BoardSim) or “Editing Power-Supply Net Properties” (LineSim).
7. If you need to pass parameters to the model, click Edit Parameters and specify the
parameter-value pairs.
Some complex models have different modes of operation that may be selected by
passing parameters to the simulator.

Tip: If you use the ADMS simulator, the Eldo CPF simulation method, and have assigned
to the port a Touchstone model that you know is strictly passive, we recommend that you
set the FORCE_PASSIVITY parameter to 2. When enforcing passivity, ADMS tries to
detect and eliminate modelling discrepancies that can lead to instability or non-physical
behavior.

If you know the model is not symmetric, we recommend that you set the SYMMETRY
parameter to 0 to avoid potentially wrong simulation results. Symmetrical models
typically contain resistance, inductance, capacitance, and inductive capacitance models,
but do not contain controlled sources.

If the Touchstone model does not provide data at zero frequency, we recommend that you
set the EXTRAP_TO_DC parameter to 1. This setting extrapolates to DC the curve from
low frequency points given in the Touchstone model. This setting has no effect if the
Touchstone model provides data at zero frequency.

For information about setting the CPF simulation method, see “Preferences Dialog Box -
Circuit Simulators Tab” on page 1808.

8. If needed, repeat steps 1-7 to select models for other driver or receiver pins.
9. Click Close.
Result: In LineSim, you return to the schematic editor and the model names are
displayed next to the IC. In BoardSim, you return to the board viewer and the model
names are not displayed in the board viewer.

Selecting IBIS Models Located Inside EBD Models

You typically do not select an .IBS model within an .EBD model because the .EBD model itself
specifies the .IBS model assignment. You usually only need to set the IBIS model pin direction
for bidirectional pins and output state for three-state output pins. To perform "what if"
simulations, however, you can interactively select an .IBS model within an .EBD model.

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Requirement: For a board, use a .REF or .QPL file to assign the .EBD model. For a schematic,
use a .REF file to assign the .EBD model.

See also: “Selecting Models and Values for Entire Components”

To interactively select .IBS models inside .EBD models:

1. From the Design File list, do one of the following:

• If you are using BoardSim, select the board ID for the .EBD component.
• If you are using LineSim, select the user-defined reference designator for the .EBD
component. The reference designator name is EBD-** where ** represents the user-
defined reference designator you created.
See also: “Selecting Models Using the REF File”
2. In the Pins list, double-click the reference designator/pin for the IC driver or receiver pin
to which you want to assign a model.
Restriction: You can assign IC models only to IC and connector pins. For information
about the component symbols in the Pins list, see “Pins List Icons” on page 487.
Result: A Warning dialog box opens, indicating the .EBD model contains model
assignments.
3. Click OK. The Select IC Model dialog box opens.
4. In the Libraries list, select the library containing the .IBS model you want to use.
To display only .IBS models in the Libraries list, click .IBS to the left of the Libraries
list.
To search all the libraries for a model, click Find Model.
The I/O type area displays model information and is updated when you select items in
the Libraries, Devices, or Pin/Signal lists.
5. Select the device in the Devices list and double-click the pin/signal in the Pin/Signal list.
Result: The Select IC Model dialog box closes and the Assign Models dialog box
becomes available.
To toggle between the Signal and Pin lists on the Select IC Model dialog box, click
Signal or Pin in the Select By area.
To display the contents of the selected model file without closing the Assign Models
dialog box, click the Edit Model File button. The appropriate model file editor opens.
6. If you have assigned an output or bidirectional model, select its direction or state in the
Buffer area.
See also: “Setting IC Buffer Direction-State” on page 477

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7. Verify the power supply assignments and voltages in the Vcc Pin and Vss Pin lists.
You can power the driver or receiver from any two power-supply nets, or from the
typical voltage contained in the model.
For power-supply nets, you can edit Vcc or Vss voltages. For information, see “Editing
Power-Supply Nets” (BoardSim) or “Editing Power-Supply Net Properties” (LineSim).
8. If needed, repeat steps 1-7 to select models for other driver or receiver pins.
9. Click Close.
Result: In LineSim, you return to the schematic editor and the model names are
displayed next to the IC. In BoardSim, you return to the board viewer, however the
model names are not displayed in the board viewer.

Selecting Models for Programmable Buffers

For pins on the IC with programmable drive or receive characteristics, IBIS models with the
[Model Selector] keyword enable you to select which model to use for simulation. For example,
if you plan to simulate at VCC = 1.8V and the [Model Selector] keyword contains the models
named Output_CMOS_2.5V and Output_CMOS_1.8V, you would select the
Output_CMOS_1.8V model.

By default, interactive and batch simulation uses the buffer model associated with the first entry
under the [Model Selector] keyword. Use the Select IC Model dialog box to override the default
assignment. You can select models for programmable buffers either as you assign the IBIS
model interactively, or after you assign the IBIS model with a model automapping file
(.REF/.QPL).

For detailed procedural information selecting models for programmable buffers, see “Selecting
IBIS - MOD - PML Models” on page 469.

You can also select models for programmable buffers by editing the IBIS model and moving the
correct model to the top of the list in the [Model Selector] keyword.

Tips for Selecting Models for Differential Pair Pins

The steps for selecting a model for a differential IC driver or receiver are the same as those for a
non-differential IC, except for the following aspects:

• You select two models, one for each half of the differential pair
• For driver models, you invert the buffer state for the - or negative pin
You can assign any type of IC model to the two pins of a differential pair. However, IBIS files
containing differential pair definitions give extra information to ensure that BoardSim or
LineSim correctly identifies the two pins as a differential pair.

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In BoardSim, assigning IBIS differential models associates the nets on each half of the
differential pair. The IBIS pin names must match the pin names on the PCB to associate the
nets. You must assign an IBIS differential model to get flight times for differential signals in the
oscilloscope and Board Wizard reports. If you assign IBIS models that are not defined as a
differential pair, or assign .MOD or .PML models, the nets must have line-to-line termination to
force BoardSim to associate them, so that you can drive them differentially and apply
differential probes in the oscilloscope. Even then, no differential flight times will be calculated.

LineSim does not require differential IBIS models for net associations, but it is still necessary to
assign an IBIS differential model to get flight times from the oscilloscope.

With IBIS Differential Model - Pin Names Must Match PCB -

BoardSim
Net association automatically occurs with an IBIS model if the model contains differential-pin
information internally (i.e., tells which pins pair with which other pins), AND if you choose the
correct pin in the model for the PCB pin you're trying to simulate. For example, if you're using
an IBIS differential model that pairs pins 1-2, 3-4, and 7-8, and you choose the model for pin 1
and apply it to pin 7 on your board, BoardSim will not associate the other net in the differential
pair. If you correct the model choice to match pin 7 in the model with pin 7 on your board, then
proper association will occur and pin 6 will appear, as expected, in the Assign Models dialog
box.

How to Tell if an IBIS Model is Differential

If an IBIS model contains differential-pair information (i.e., tells which pins pair with which
other pins), the pictures in the Buffer area in the Assign Models dialog box and in the I/O Type
area in the Select IC Model dialog box clearly show a pair of drivers/receivers. If the pictures
for a particular model show only single drivers/receivers, then the model is not differential.

You can also look in the IBIS file itself, using the Visual IBIS Editor. Differential-pin pairings
(if they exist in a model) are described in a table that begins with a [Diff Pin] keyword. If there's
no such keyword and table in the model, then it's not a differential model.

Related topics
“Setting IC Buffer Direction-State” on page 477

“Assigning Power Supplies to ICs” on page 478

“Searching for Models” on page 505

“Copying Models” on page 480

“Removing Models” on page 483

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“About the Select IC Model Dialog Box” on page 499

“Default IC Model Direction and State” on page 501

Setting IC Buffer Direction-State

To set the direction/state of an IC buffer:

1. Open the Assign Models dialog box.

See also: “Opening the Assign Models Dialog Box” on page 468
2. If you have a MultiBoard project open, do the following:
a. Select the board ID from the Design File list.
If the selected net spans more than one board, you can assign models to selected net
pins located on other boards. The Pins list is empty if the selected net does not
connect to the board in the Design File list.
b. To apply the IC model selection or its driver settings to all instances of the selected
board, select the Apply To All Similar Boards check box.
This check box is displayed when more than one copy, that is, instance, of a board
exists in the MultiBoard project. For information about multiple instances and why
you might want to select or clear the check box, see “Saving Session Edits for
Multiple Board Instances”. The check box is automatically selected when you assign
the same model to all instances of a board.
3. If you are using an .EBD model, do the following to set the direction of the IBIS model
pin inside the .EBD model:
a. In the Design File list, select the reference designator representing the .EBD model,
for example EBD-J1.
b. In the Pins list, select the .IBS model pin, and then go to step 5.
4. In the Pins list, select the reference designator/pin for the IC driver or receiver pin to set
as a driver or receiver.
Result: The Select IC Model dialog box opens.
5. In the Buffer area, click an option.
For differential models, "Output" represents the positive or + pin and "Output Inverted"
represents the negative or - pin.
6. Repeat steps 2-5 as needed to select models for other driver or receiver pins.
7. Click Close.

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Related Topics
“Possible Buffer States” on page 491

Assigning Power Supplies to ICs

Use the Assign Models dialog box to assign power supplies to Vcc and Vss pins on ICs.

This topic contains the following:

• “Assigning Power Supplies to Vcc and Vss Pins on ICs” on page 478
• “How LineSim Configures External Power-Supply Nets” on page 479
• “How BoardSim Configures External Power-Supply Nets” on page 479
• “Importance of Power-Supply Pin Location in BoardSim EMC” on page 480

Assigning Power Supplies to Vcc and Vss Pins on ICs

This section describes how to assign power supplies to non-SPICE IC models. For SPICE
models, you can assign an external power-supply net to the IC model and manually edit the
power-supply voltage.

See also: “Interactively Selecting IC Models” on page 467

To assign power supplies to Vcc and Vss pin on ICs:

1. If you are using BoardSim, make sure the set of power-supply nets is complete before
assigning external power-supply nets to Vcc and Vss pins. If any power-supply nets are
missing, you can add them.
See also: “Editing Power-Supply Nets”
2. In the Pins list, select a Vcc or Vss pin on the driver or receiver IC.
3. In the Vcc pin list and the Vss pin list, select one of the following items:
• use model's internal values
• <external power-supply net>
Restriction: The Vcc pin and Vss pin lists contain only the "use model's internal values"
item if you enable the "When assigning a model to an IC pin, always use model's
internal values" option on the General tab on the Preferences dialog box.
See also: “Preferences Dialog Box - General Tab” on page 1818
In BoardSim, if several pins on the IC connect to the power-supply net you want to use,
assigning the power-supply to one of the pins assigns the power supply to all the pins

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connected to the same power-supply net. For example, if pins 18 and 52 connect to net
Vcc, assigning pin 18 to net Vt3 also assigns pin 52 to net Vt3.
You can set both the Vcc and Vss pins to use the model internal value. If you do this,
one of the pins is set to 0V. If the typical supply voltage is positive, then Vss = 0V. If the
typical supply voltage is negative, then Vcc = 0V.
4. Repeat steps 2-3 as needed.
5. Click OK.
6. If you connected the IC to a power-supply net, you can edit its voltage.
See also: “Editing Power-Supply Nets” (BoardSim) or “Editing Power-Supply Net
Properties” (LineSim)
If you set the Vcc or Vss voltage to a value other than the typical value specified in the IC
model, BoardSim/LineSim does not automatically correct the other parameters in the model to
reflect the new supply voltage. For example, any of the HyperLynx 3.3V .MOD CMOS models
can be made to run at VCC=2.5V, but the model slew rates, on impedances, and so on may no
longer be correct. The task of compensating the other parameters is left to you.

How LineSim Configures External Power-Supply Nets

If you assign an external power-supply net to the IC, LineSim assigns the Vcc and Vss power-
supply nets to the Vcc and Vss pins on the IC, and then changes the voltages on those nets to
match the voltages contained in the IC model.

When you add a new IC to the schematic and assign a model, or assign a new model to an IC,
LineSim compares the current Vcc and Vss voltages to the power-supply information contained
in the IC model you are adding. If the voltages do not match, LineSim asks you whether you
want it to change the Vcc and Vss voltages to match the power-supply information contained in
the IC model.

How BoardSim Configures External Power-Supply Nets

If you assign an external power-supply net to the IC, BoardSim identifies the Vcc and Vss pins
for ICs on the board by examining the connections between the power-supply nets and IC pins,
and then creating a set of power-supply nets. If an IC connects to only one non-ground power-
supply net, BoardSim finds the Vcc and Vss pins for all of the driver and receiver pins on the
IC.

If an IC does not connect to any power-supply net, BoardSim sets the voltage for its Vcc and
Vss pins as follows:

• For an IBS model, Vcc and Vss are set to the typical power-supply voltage contained in
the model.

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• For MOD and PML models, Vcc and Vss are set to the default power-supply voltage
contained in the model.
If the pins on an IC connect to multiple power supplies, for example some pins connect to one
power supply and the other pins connect to another power supply, BoardSim arbitrarily assigns
one of the power supplies to all of the IC pins. Because the selection is arbitrary, you probably
need to manually change the power supply for some pins.

Importance of Power-Supply Pin Location in BoardSim

EMC
The location of power supply pins on the board affects the amount of radiation generated by an
IC package. BoardSim EMC searches for power supply pins by looking at the nets to which pins
on each IC are connected. If an IC is not connected to power-supply nets, such as when the
board is only partially routed and the power supply connections have not been made, BoardSim
uses the pins located farthest away from the pin being simulated. In some cases, this may lead to
prediction of too much radiation.

In this case, we recommend that you not use the package as a radiation source and focus entirely
on the radiation being generated by trace segments on the net.

See also: “Setting Up the EMC Antenna or Current Probe” on page 906

Related Topics
“Interactively Selecting IC Models” on page 467

“Editing Power-Supply Net Properties” (LineSim)

“Editing Power-Supply Nets” (BoardSim)

Copying Models
Once you have interactively chosen a model for one IC pin, it may be convenient to quickly
copy the same model to other pins. This is particularly true of receiver models, and of .MOD
models generally since they are not pin-specific.

For example, suppose all the receivers on a net are 74ACxxx inputs. Once you have chosen a
model for one of the receivers, it is convenient to paste it immediately to the other receivers on
the net.

This topic contains the following:

• “Copying an Existing Model” on page 481

• “Pasting to Another IC Pin” on page 481

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• “Pasting to All Other IC Pins” on page 481

• “Creating Multiple Receivers and One Driver of the Same Type” on page 482

Copying an Existing Model

To make a copy of a model:

1. In the Assign Models dialog box, in the Pins list, select an IC pin that has been assigned
the model you want to copy.
2. In the Model to Paste area, click Copy.
Result: The Model to Paste area refreshes to display the copied model. Also, the Paste
and Paste All buttons become available.
If you select a different component pin in the Pins list, the information in the Model to
Paste area remains the same. The Model to Paste area is a storage buffer: it always
remembers the model you last copied.

Pasting to Another IC Pin

To paste the last-copied model to another IC pin:

1. Be sure that the model you want to paste is displayed in the Model to Paste area.
2. In the Assign Models dialog box, in the Pins list, select the IC pin to which you want to
copy the model.
3. Click Paste.
Result: After a brief pause (while the model data are loaded into memory):
• The Pins list updates with the new model assignment
• The model-information area updates; the fields display the new model’s name and
other data
If you have a MultiBoard project open, the paste behavior depends on the Apply To All
Similar Boards check box value. If the check box is selected, the model is pasted to all
instances. If the check box is cleared, the model is pasted to only the current instance.
A pasted model defaults to the buffer direction/state of the model that was copied.

See also: “Setting IC Buffer Direction-State” on page 477

Pasting to All Other IC Pins

To paste the last-copied model to all other IC pins:

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1. Be sure that the model you want to paste is displayed in the Model to Paste area.
2. Click Paste All.
Result: When the operation is complete, the Pins list updates with the new model
assignments.
If you have a MultiBoard project open, the paste behavior depends on the Apply To All Similar
Boards check box value. If the check box is selected, the model is pasted to all instances. If the
check box is cleared, the model is pasted to only the current instance.

A pasted model defaults to the buffer direction/state of the model that was copied.

See also: “Setting IC Buffer Direction-State” on page 477

If you have the BoardSim Crosstalk license and are running with crosstalk analysis enabled,
pasting a model may result in the contents of the Pins list changing. This is due to the fact that
aggressor nets are chosen based in part on the characteristics of the driver ICs on nearby nets; a
change in a driver IC may change how strongly a given net couples to the selected net, and
cause, e.g., that net to be dropped as an aggressor. If a net is dropped, then its pins will disappear
from the Pins list.

See also: “Effect of IC Models on Pins in the Assign Models Dialog Box” on page 1230

Creating Multiple Receivers and One Driver of the Same

Type
Sometimes it is convenient to make all of the ICs on one net use the same model, with one of the
pins set as a driver (i.e., an "output"), and the rest as receivers ("inputs"). The Paste All
command can be used to do this efficiently, as follows:

To set all pins on a net to the same model, with one pin as a driver:

1. Select the desired model for one pin on the net. In the Buffer Settings area, set the pin’s
direction/state to Input.
2. With the same pin still selected in the Pins list, click Copy.
3. Then click Paste All. All of the other ICs on the net are set to the same model, with
every pin’s direction/state set to Input.
If you have a MultiBoard project open, the paste behavior depends on the Apply To All
Similar Boards check box value. If the check box is selected, the model is pasted to all
instances. If the check box is cleared, the model is pasted to only the current instance.
4. Now select the pin that you wish to be the driver. In the Settings area, click Output.
If you set the initial pin to state Output before copying and pasting, all of the other pins
will also be set during the Paste operation to state Output. Since you actually want them

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to be Inputs, be sure to perform the copy operation with the pin set to Input, and change
it later (after the Paste) to Output.

Removing Models
Occasionally, you may want to interactively remove a previously selected IC model from a
component pin, so that the pin has no model. This is equivalent to "lifting" an IC pin from your
board.

In the Assign Models dialog box, when an IC pin is selected in the Pins list, a Remove button
appears near the Select button. The Remove button enables you to remove/unassign an
interactively-assigned model from the selected pin.

This topic contains the following:

• “Removing Interactively-Assigned Models” on page 483

• “Cannot Interactively Remove Automapping Assignments” on page 483
• “Deactivating IC Components in Cell-Based Schematics” on page 485

Removing Interactively-Assigned Models

The Remove button gives you a way to experiment to see how simulation results are affected by
the removal of one or more models.

The Remove button is only available when an IC pin is selected; you cannot remove a passive
component (e.g., resistor or capacitor) from a pin. To remove the effects of a passive
component, set its value to 0.0 or a large number (depending on whether it is in series or parallel
with the selected net).

To remove an IC model from a pin:

1. In the Assign Models dialog box, select in the Pins list the pin whose model you want to
remove.
2. Click Remove.
Result: The model previously assigned to the pin is removed, and the green driver or
receiver icon changes back into a red question mark.

Cannot Interactively Remove Automapping Assignments

An IC model that has been assigned by an automapping file (.REF and .QPL) cannot be
interactively removed from a pin. Clicking the Remove button has no effect in this case.

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However, for non-.EBD models, you can override the automapping assignment by interactively
selecting a different IC model for the pin. The .REF file assignment re-asserts itself if you
remove the interactively assigned IC model from the pin (similar to an editor's "undo"
behavior).

By contrast, you cannot interactively override an .EBD model assignment made by an

automapping file. To change the .EBD model assigned by an automapping file, you can do one
of the following:

• Edit the automapping file to change the model assignment.

• Edit the automapping file to delete the model assignment and then interactively assign
an IC model.
• Delete or rename the automapping file, reload the schematic, and then interactively
assign an IC model.
• For .QPL files only, in the Set Directories dialog box, clear the Use QPL file(s) to
assign models check box or delete the .QPL file from the Qualified Part File(s) edit box.
See also: “Set Directories Dialog Box” on page 1854, “Selecting Models and Values for Entire
Components”

Session-File Example
If you specify in a .REF file that U1 is model 74AC11XX:GATE; simulate with it on net FOO
and decide to interactively change the model to 74AC11X:LINE-DRV; close your board or
BoardSim and save your edits into a session file; then re-load your board, when you re-simulate
net FOO, the model 74AC11X:LINE-DRV will be loaded, since the model in the session
(.BUD) file takes precedence over that in the .REF file.

However, this override occurs only for net FOO, since the session file applies models pin-by-
pin, unlike the .REF file which works component-by-component. Other nets connected to other
pins on U1 will use the model specified in the .REF file.

You can "undo" the session file’s override by removing the 74AC11X:LINE-DRV model. This
will re-connect the pin on net FOO to the model specified by the .REF file.

Interactive Model Example

If you specify in a .REF file that U1 is model 74AC11XX:GATE; simulate with it on net FOO
and decide to interactively change the model to 74AC11X:LINE-DRV; simulate; edit your
.REF file and change U1 to yet another model (e.g., 74ALSXX:GATE); then re-select net FOO,
when you re-simulate, the model 74AC11X:LINE-DRV will still be loaded, since models that
are chosen interactively take precedence over models specified in the .REF file. In fact, after
you’ve interactively edited a particular IC pin, it will no longer load the model from the .REF
file, unless you remove the interactively selected model with the Remove button.

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Tip: This override occurs only for net FOO, since the interactive selection applies models
pin-by-pin, unlike the .REF file which works component-by-component. Other nets
connected to other pins on U1 will use the model specified in the .REF file.

Deactivating IC Components in Cell-Based Schematics

Restriction: This procedure applies to only the cell-based schematic editor.

To deactivate the IC component:

• Click the IC whose model you want to remove. The IC deactivates and disappears from
the schematic.
To reactivate the previously-assigned model, click the IC again.

Reference Information for Selecting Models

Interactively
This topic contains detailed information about using the Assign Models dialog box.

This topic contains the following:

• “About the Assign Models Dialog Box” on page 485

• “Using the Port-Mapping Spreadsheet” on page 495
• “About the Select IC Model Dialog Box” on page 499
• “Default IC Model Direction and State” on page 501
• “If Second Pin is Not Visible” on page 502

About the Assign Models Dialog Box

Use the Assign Models dialog box to interactively assign models to reference designators in the
schematic or board. In BoardSim, this dialog box has additional tabs enabling you to edit
passive component values, assign Quick Terminators, and to display series bus switch
connectivity.

This topic contains the following:

• “Pins List” on page 486

• “Models Area” on page 489
• “Buffer Area” on page 491

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• “Viewing Series Bus Switch Pin Connectivity” on page 492

• “Design File List in BoardSim” on page 494
• “Design File List in LineSim” on page 494
• “Apply to All Similar Boards Check Box” on page 495
• “Reference Designator and Pin Name Boxes” on page 495
See also:

• “Interactively Selecting IC Models” on page 467

• “Removing Models” on page 483
• “Copying Models” on page 480
• “Assigning Power Supplies to ICs” on page 478
• “Interactively Editing Rs - Ls - Cs”
• “Selecting Ferrite-Bead Models in BoardSim” on page 526
• “About Parasitics for ICs and Passive Components”

Pins List
The Pins list displays the reference designator, pin number, and model/value assignment status
for component pins in the circuit. In BoardSim, the Pins list displays information about pins on
the currently selected net and its associated nets. In LineSim, the Pins list displays information
about the pins in the schematic.

IC Reference Designators in BoardSim

In BoardSim, an IC has whatever reference designator you gave it when you designed your
board.

Pins are listed in the form:

<reference_designator>.<pin_name>

Examples: U1.2 means pin 2 on component U1. R100.A means pin A on R100.

For passive components (Rs, Cs, Ls, and ferrite beads), the Pins list displays only one pin per
component, since the second pin is redundant from the modeling standpoint. Both pins share a
component value, e.g., for a 100-ohm discrete resistor, both pin 1 and pin 2 have the value "100
ohms."

For resistors or capacitors that are packaged as a network (rather than discretely), the Pins list
shows one pin on every sub-component in the package.

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IC Reference Designators in LineSim

In LineSim, an IC’s reference designator is created automatically from the IC’s schematic-cell
label.

Example: The IC in cell A1 has reference designator "U(A1)". In the Assign IC Models dialog
box, its pin is also displayed as "U(A1)".

The default reference designators are suitable for use with most IC model types, however user-
defined reference designators are required for .EBD model assignments.

See also: “Creating User-Defined Reference Designators”

Pins List Icons

Each component pin is marked in the Pins list with an icon that shows the status of its model or
value. The icons allow you to easily see which components have models or valid values. You
can also easily determine which IC pins on the net are the drivers ("outputs") and which are
receivers ("inputs").

Table 10-2. Pins List Icons in Assign Models Dialog Box

Icon Name
Red question mark

The component is missing modeling information. The specific meaning of the red
question mark depends on the following component types:
• IC, connector—No model is selected. The component is treated as an electrical
open during simulation.
• Resistor—Invalid value.
• Capacitor—Invalid value.
• Inductor—Invalid value.
• Ferrite bead—No model is selected. The component is treated as an electrical
short during simulation.

You are not required to remove all red question marks before you can simulate,
though typically you would. Some possible situations:
• Complete simulation—Remove all red question marks, that is specify all IC
models and check all component values.
• Quick simulation—Specify a driver-IC model, check all resistor and capacitor
values, ignore receivers.
• Minimum requirement for simulation—Specify a driver-IC model.

ICs which have the red question-mark icon in the Pins list are named "????" in
LineSim's schematic editor.

See also: “Interactively Selecting IC Models” on page 467, Selecting Models and
Values for Entire Components

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Table 10-2. Pins List Icons in Assign Models Dialog Box (cont.)
Green driver (pin points to the right)

This icon appears if you either:

• Assign an IC model with an output-only buffer direction
• Set the IC model buffer state to Output, Output Inverted, Stuck High, or Stuck
Low

An R or Q appears near the symbol when the model is assigned by a .REF file (R) or
.QPL file. Only BoardSim supports .QPL files.

See also: “Setting IC Buffer Direction-State” on page 477

Green receiver (pin points to the left)

This icon appears if you either:

• Assign an IC model with an input-only buffer direction
• Set the IC model buffer state to Input, Output Hi-Z

An R or Q appears near the symbol when the model is assigned by a .REF file (R) or
.QPL file. Only BoardSim supports .QPL files.

See also: “Setting IC Buffer Direction-State” on page 477

Green checkmark (BoardSim only)

This icon applies to only resistors, capacitors, and inductors if a valid value for the
component exists in the board file or the session edit files (.BUD).

See also: BoardSim Session Files

If an invalid value exists, BoardSim sets the component value to a safe default
number, but marks the component with a red question mark to remind you to check
and, if necessary, modify the value.

The green check mark always applies to all pins on a passive component. For
example, if one pin on a resistor or resistor network has a check-mark icon, all of the
other pins on the component will have check marks too.
Connector

This icon marks connector pins for these conditions:

• A MultiBoard project is loaded into BoardSim
• An .EBD model is used in the schematic
Crosstalk aggressor/coupled net (BoardSim Crosstalk option only)

This icon distinguishes between pins on the victim net versus those on aggressor nets.
The aggressor/coupled-net icons appear to the right of the "pin type" icons described
here.

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Table 10-2. Pins List Icons in Assign Models Dialog Box (cont.)
Series bus switch

This icon identifies a pin on the net that is connected to a series bus switch, as
identified by an IBIS [Series Pin Mapping] keyword.

The Pins list highlights all series bus switch pins connected in series with the selected
pin.
Differential resistor Quick Terminator (BoardSim only)

This icon identifies a pin on the net that is connected to a differential resistor Quick
Terminator.

Models Area
The area to the right of the Pins list is called the "models area." When you select an IC pin in the
Pins list, the models area changes to show you the current status of the IC’s model.

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Component-Type Icons
The models area displays an icon that allows you to easily identify the kind of component you
have selected in the Pins list. There are different icons for each of the component types (IC, R,
C, L, and ferrite bead).

The component type for every pin is determined by the reference-designator mappings that were
in effect when you loaded your board. You cannot change component type in the Assign
Models dialog box.

See also: Edit Reference Designator Mappings Dialog Box

Component-Data Information
In addition to the component-type icons, the models area displays information about each model
or passive-component value. What information is displayed differs depending on which
component type is currently selected.

For example, if you have a resistor selected, you see an editable Value. If you have an IC
selected, you see a variety of model-related information.

For LineSim free-form schematics, you can specify Part Name information for IC symbols. This
is required for exporting constraint templates from LineSim. See “Exporting Constraint
Templates from LineSim” on page 1175.

See also: “Interactively Selecting IC Models” on page 467, “Interactively Editing Rs - Ls - Cs”
(BoardSim), “Editing Resistor - Capacitor - Inductor Values” (LineSim), “Selecting Ferrite-
Bead Models in BoardSim” on page 526

Additional Icons for Networked Resistors and Capacitors

If you select a pin on a resistor or capacitor that is packaged as a network (rather than
discretely), an additional "connectivity" icon may appear in the models area next to the
component-type icon.

The connectivity icon shows you how BoardSim believes the component’s package connects
the network internally. For details on changing a networked component’s package (and internal
connectivity), see “Choosing Resistor and Capacitor Packages”

Component-Type Tabs
At the top of the Assign Models dialog box is a series of tabs, labeled with the names of the
component types supported by BoardSim. The tab names also include "Quick Terminator," a
special type of "virtual" component.

See also: “About Quick Terminators”

When you click on a tab, the first component of that type (if any) is selected in the Pins list.

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Buffer Area

Possible Buffer States

IC models can have nearly any mixture of the following buffer states:

• Input—Indicates a receiving or input state. In this state, an I/O or bidirectional model’s

driver is turned off, and the pin is receiving. For input-only pins, this is the only
available state.
• Output Hi-Z—Indicates a passive, high-impedance state in which a driver or output
model has "turned off." This selection is available exclusively for output-only models
that have "tristate" capability; the high-impedance state of an I/O or bidirectional model
is selected with state "Input."
• Output—Indicates a driving or output state; the sense of the output is "true," meaning
that in the oscilloscope, the model will follow the sense of the Driver Waveform setting
(i.e., will fall on a falling edge and rise on a rising edge). If the oscilloscope is set to
waveform type "Oscillator," the model will start with a rising edge.
• Output Inverted—Indicates a driving or output state, but with inverted sense, meaning
that in the oscilloscope, the model will invert the sense of the Driver Waveform setting
(i.e., will rise on a falling edge and fall on a rising edge). If the oscilloscope is set to
waveform type "Oscillator," the model will start with a falling edge. This setting is most
useful for differential-driver pairs, where one pin’s model must be inverted relative to
the other.
• Stuck High—Indicates a driving or output state, but one in which the model stays high
and never switches. In the oscilloscope, the model will stay high regardless of the Driver
Waveform setting. This setting is useful for wired-OR or wired-AND buses for which
you want to investigate the effect of one driver switching while other drivers remain
static. It is also extremely important for crosstalk simulations, in which the driver on
"victim" net is usually simulated in a static, "stuck" state (see “Importance of Modeling
Drivers on Victim Nets as Stuck High or Stuck Low - BoardSim” for details).
• Stuck Low—Indicates a driving or output state, but one in which the model stays low
and never switches. In the oscilloscope, the model will stay low regardless of the Driver
Waveform setting. This setting is useful for wired-OR or wired-AND buses for which
you want to investigate the effect of one driver switching while other drivers remain
static. It is also extremely important for crosstalk simulations, in which the driver on
"victim" net is usually simulated in a static, "stuck" state (see “Importance of Modeling
Drivers on Victim Nets as Stuck High or Stuck Low - BoardSim” for details)
Which buffer states are available for any particular model is determined by the model’s internal
"type." In practice, no model can simultaneously have all of the buffer types described above.
For example, types "Input" and "Output Hi-Z" are mutually exclusive.

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Input Versus Output Hi-Z

Two buffer states—Input and Output Hi-Z—are similar to each other, but not quite the same.
Both generally refer to a state in which an IC pin is high-impedance and not actively driving the
net to which it is connected. The difference is that Input is available on either "pure" input pins
(pins that can never drive) or on I/O or bidirectional pins that can act as inputs when the output
or driving circuitry is shut off; whereas Output Hi-Z is available on pins that can only drive or
be turned "off," but have no receiver-input stage.

If you have an IC pin for which the data sheet refers to the "high-impedance" state, but when
you model it in BoardSim/LineSim there is no Output Hi-Z selection available, choose buffer
state Input instead. This means that the pin is actually I/O; when the data sheet refers to "high-
Z" it means that the driving circuitry is disabled and the pin is in a high-impedance receiving
(i.e., "input") state.

Threshold Voltages
The Buffer area also displays the input-receiver and/or output-driver switching thresholds
present in the IC model for the currently selected pin. Only the thresholds relevant to current
buffer-state choice are displayed, e.g., if for a bidirectional pin you set the buffer state to
"Input," the input thresholds Vih and Vil are shown; if you change the state to "Output," the
output-switching threshold "Vmeas" is displayed.

Thresholds are used by BoardSim’s batch simulation Wizard when it calculates timing delays.
For more information on thresholds and how they are used, see “Constraint Definitions”.

Viewing Series Bus Switch Pin Connectivity

Use the Bus Switch tab of the Assign Models dialog box to view the connections among series
bus switch pins. This information is available when a pin on the selected net is present in a
[Series Pin Mapping] keyword in the IBIS model assigned to the reference designator.

See Figure 10-1 on page 493. In the Pins list, when you select a pin connected to a series bus
switch, all the other pins in the series bus switch are also highlighted. If the series bus switch
contains more than one series pin pair, such as (6, 7) and (6, 11) in Figure 10-1, the
Connectivity area in the dialog box displays all of them.

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Figure 10-1. Series Bus Switch Connectivity

Table 10-3. Series Bus Switch Connectivity

Highlighted pins are connected to the series bus switch.

Pins 15 and 9 of the example [Series Pin Mapping] keyword (below) do

not appear in the Pins list because they are not part of the selected net.

Example IBIS model syntax:

[Series Pin Mapping] pin_2 model_name function_table_group

6 7 SWITCH1 1
6 11 SWITCH2 2
15 9 SWITCH1 1
Highlighted MOSFET identifies the source of signals, pins, and model
information.

Click another MOSFET drawn with red lines to display its signals, pins
and model information. You cannot display information for MOSFETs
drawn with black lines because they do not connect to the selected net.

Enabling Series Bus Switches for Simulation

The [Series Switch Groups] keyword determines which series bus switch is enabled in
simulation. The Assign Models dialog box does not provide a way to enable different series bus

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switches. To enable different series bus switches, edit the IBIS model to identify the active
series pin pairs in the [Series Switch Groups] keyword. See Table 10-4.

Table 10-4. Enabling Different Series Bus Switch Groups - Example 1

Enable group 1 [Series Switch Groups]
On 1 /
Off 2 /
Enable group 2 [Series Switch Groups]
On 2 /
Off 1 /

If the [Series Switch Groups] keyword contains multiple groups with the same members, then
simulation uses the first entry. See Table 10-5.

Table 10-5. Enabling Different Series Bus Switch Groups - Example 2

Enable groups 1, 2, 3, 4 [Series Switch Groups]
On 1 2 3 4 /
Off 1 2 3 4 /
Disable groups 1, 2, 3, 4 [Series Switch Groups]
Off 1 2 3 4 /
On 1 2 3 4 /

Related Topics
“Creating and Editing IBIS Models” on page 403

Design File List in BoardSim

The Design File list is displayed when you have loaded a MultiBoard project into BoardSim.
Use the Design File list to select the board to which you want to apply your interactive settings.

This list is also used in the Set Power Supply Voltages and Nets dialog box.

Design File List in LineSim

The Design File list is displayed when an .EBD model has been assigned to a user-defined
reference designator in your schematic. When present, the Design File list is positioned above
the Pins list.

The Design File list allows you to filter the set of reference designators displayed in the Pins
list. When you select "Schematic," the Pins list displays reference designators for the LineSim
schematic. When you select "EBD-**", where "**" is a user-defined reference designator, the
Pins list displays reference designators inside the .EBD model. For details about how LineSim
assigns .EBD models, see “Selecting Models Using the REF File”.

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Apply to All Similar Boards Check Box

Restriction: This check box is displayed only when a MultiBoard project has been loaded into
BoardSim.

The Apply to All Similar Boards check box indicates whether you want to propagate an
interactive setting to all copies (instances) of that board in your MultiBoard project. Its default
value is "selected." Clearing the check box is not recommended unless you are familiar with
how it works.

See also: “Saving Session Edits for Multiple Board Instances”

Clearing the "Apply to all similar boards" check box does not persist. The check box will be
selected the next time you open the dialog box.

This list is also used in the Set Power Supply Voltages and Nets dialog box.

Reference Designator and Pin Name Boxes

Restriction: This section applies to LineSim only. In BoardSim, reference designator and pin
name information is displayed only in the Pins list.

When a component is selected in the Pins list, its reference designator is displayed in the
Reference Designator text box and its pin name (if it has one) is displayed the Pin Name text
box. The Reference Designator and Pin Name text boxes are both positioned below the Pins list.

You can use the Reference Designator and Pin Name text boxes to:

• Assign .EBD models to your schematic

• Override default reference designators
See also: “Creating User-Defined Reference Designators”

Using the Port-Mapping Spreadsheet

Use the spreadsheet on the Assign Models dialog box to connect ports on a SPICE or
Touchstone model to the circuit.

This topic contains the following:

• “Connecting Model Ports to the Circuit” on page 496

• “Connection Types” on page 496
• “SPICE Output Characteristics” on page 497
• “Port-Mapping Example - Connecting Non-Differential SPICE Models” on page 498

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• “Port-Mapping Example - Connecting Differential SPICE Models” on page 499

Connecting Model Ports to the Circuit

To connect model ports to the circuit:

1. Click in the Circuit Connection cell for the model Port and select a connection type
from the list.
If you do not know the meaning of a Port value, for example it is an arbitrary number,
click the Edit Model File button to open the model file and see if the ports are
documented.
For differential SPICE models, you connect two or more pins in the circuit to an
instance of the model. The same spreadsheet is automatically used for each pin.
.IBS model ports are automatically mapped to nodes in the SPICE netlist.
2. For SPICE outputs, select a characteristic from the list below the spreadsheet, and then,
if needed, type a new value into the box to the right of the list.

Connection Types
The contents of the Circuit Connection cell list depends on the assigned model type and, for
SPICE models, the buffer direction specified in the Buffer area.

Table 10-6 contains descriptions of items in the Circuit Connection cell:

Table 10-6. SPICE Model Assignment - Contents of Circuit Connection Cell

List item Means
Stimulus Applies the stimulus from the oscilloscope.
Inverted stimulus Same as Stimulus, but has inverted polarity.

Use for the - or negative input for the

differential driver.
Delayed Stimulus Same as Stimulus, but the stimulus is offset by
the Stimulus Delay Time.
Delayed Inverted Stimulus Same as Delayed Stimulus, but has inverted
polarity.

Use for the - or negative input for the

differential driver.
<power supply> The list of available power-supply nets.

Examples: Vcc, Vee, Gnd, Vpullup

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Table 10-6. SPICE Model Assignment - Contents of Circuit Connection Cell

<reference designator and pin> An item in the Pins list.

Examples: U(A0) in LineSim, U1.2 in

BoardSim
NC Not connected to the circuit.
Alternative: Blank cell
Use for the output for the receiver.

SPICE Output Characteristics

When you assign a SPICE output, a list appears below the spreadsheet that enables you to
override the default characteristics for the output.

Table 10-7 contains descriptions of items in the SPICE output characteristic list:

Table 10-7. SPICE Model Assignment - Output Characteristic List

List item Means
Approx. Output Switching Time The driver rise or fall time. Use whichever is
faster. The time is based on how long it takes
the driver to switch between 10%-90% of its
overall voltage swing.

HyperLynx uses this information to create an

optimized transmission line netlist for efficient
simulation.

BoardSim also uses this information to identify

nets that exceed the crosstalk threshold and to
add them to the Pins list as associated nets.

See also: “Associated Nets“

Stimulus V high The logic-one stimulus voltage.
Stimulus V low The logic-zero stimulus voltage.

If you select Delayed Stimulus or Delayed Inverted Stimulus in the Circuit Connection cell,
additional list items become available. Some models with more than one input require different
stimulus characteristics for each input.

Table 10-8 contains descriptions of items in the SPICE delayed stimulus descriptions:

Table 10-8. SPICE Model Assignment - Delayed Stimulus Output

Characteristic List
List item Means

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Table 10-8. SPICE Model Assignment - Delayed Stimulus Output

Characteristic List (cont.)
Stimulus Delay Time The stimulus time offset.

The same stimulus delay is used for all pins

with Delayed Stimulus and Delayed Inverted
Stimulus.
Delayed Stimulus V high The logic-one delayed stimulus voltage.
Delayed Stimulus V low The logic-zero delayed stimulus voltage.

Port-Mapping Example - Connecting Non-Differential SPICE

Models
The SPICE model has the following ports: Vin, Vout, Vcc, and Gnd. The circuit consists of a
transmission line connecting driver pin U1.3 to receiver pin U2.3. In the following image, the
spreadsheet's SPICE Port names are inside the buffer symbols and the Circuit Connection
names are outside the buffer symbols:

Figure 10-2. Location of SPICE Ports and Circuit Connections

The spreadsheet for the driver pin resembles Table 10-9.

Table 10-9. Single-Ended Driver Spreadsheet Mapping

Port Circuit Connection
Vin Stimulus
Vout U1.3
Vcc Vcc
Gnd Gnd

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The spreadsheet for the receiver pin resembles Table 10-10.

Table 10-10. Single-Ended Receiver Spreadsheet Mapping

Port Circuit Connection
Vin U2.3
Vout NC
Alternative: Blank cell
Vcc Vcc
Gnd Gnd

Port-Mapping Example - Connecting Differential SPICE Models

The SPICE model has the following ports: Vin+, Vin-, Vout+, Vout-, Vcc, and Gnd. The circuit
consists of a transmission line connecting driver pin U1.1 to receiver pin U2.1 and another
transmission line connecting driver pin U1.2 to receiver pin U2.2.

An example image is not provided.

To connect differential SPICE model ports to the circuit, you use the same concepts illustrated
the topic “Port-Mapping Example - Connecting Non-Differential SPICE Models” on page 498,
except one driver is connected to Inverted Stimulus and the other driver is connected to
Stimulus.

The spreadsheet for the driver pins resembles Table 10-11.

Table 10-11. Differential Driver Spreadsheet Mapping
Port Circuit Connection
Vin+ Stimulus
Vin- Inverted stimulus
Vout+ U1.1
Vout- U1.2
Vcc Vcc
Gnd Gnd

About the Select IC Model Dialog Box

Use the Select IC Model dialog box to display the contents of IC model libraries, to find a
model in a library, and to assign a model to a reference designator in the design.

This topic contains the following:

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• “Information on Selected Device Area” on page 500

• “Select a Library Device and Signal-Pin Area” on page 500
• “Select By Area” on page 501
See also: “Interactively Selecting IC Models” on page 467

Information on Selected Device Area

This area contains basic information for the selected device, if available in the model, including
the following:

• Name of the library, device, signal, and pin

• I/O type, such as bidirectional, input-only, output-only, and so on
.MOD libraries do not contain lists of component pins/signals and always model both
driver (i.e., output) and receiver (input) functionality.
• Switching thresholds for inputs and outputs
These values are used in BoardSim to calculate timing delays and are currently unused
in LineSim.
This area also contains the Model Selector button, which is available when you select an IBIS
model with the [Model Selector] keyword. See “Selecting Models for Programmable Buffers”
on page 475.

The Notes box contains information supplied by the author of the model, such as who created
the model and when, how the model is copyrighted, revision history, and so on. Click the Notes
box to view all the information.

Select a Library Device and Signal-Pin Area

You use this area to display the available libraries and select a model for the pin.

See also: “Interactively Selecting IC Models” on page 467, “Supported SI Models and
Simulators” on page 1264

Filtering the Contents of the Libraries List

To filter the Libraries list:

• Click a library name.

Finding a Model in a Library

To search all libraries for a model:

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• Click Find Model.

See also: “Searching for Models” on page 505, “Set Directories Dialog Box” on page 1854,
“Select Directories for IC-Model Files Dialog Box” on page 1844

Shipping Libraries
BoardSim/LineSim ship with several libraries:

• .IBS—Contains family- or component-specific models created by the IC vendors or, in a

few cases, by Mentor Graphics.
• .PML—Contains vendor- or family-specific full package models, usually created by
Mentor Graphics. An example is 74AC.PML.
• .MOD—Contain vendor- or family-specific models, usually created by Mentor
Graphics. An example is IDT.MOD (IDT FCT devices).
• TECH.MOD—Contains generic models based on technology types and switching
times. Use this library when you cannot find an exact model for a device and do not have
time to create or search for one.
See also: “TECH-MOD Library” on page 503
• GENERIC.MOD—Contains HyperLynx’s models for a large number of standard-logic
families (all 74XX, ECL, and certain other miscellaneous models).
See also: “GENERIC-MOD Library” on page 504
BoardSim/LineSim does not ship with SPICE or Touchstone libraries.

See also: “IC-Model Formats” on page 507

Select By Area
The third column from the left, if available for the selected device, displays either signal or pin
information. Click the Pin or Signal option to specify the information type to display.

Default IC Model Direction and State

After you have chosen the model in the Assign IC Model dialog box, you return to the Assign
Models dialog box.

The model’s default direction and state depend on several factors:

• If the model is output-only, meaning it cannot be set to an input state, the default state is
Output
• If the model is input-only, meaning it cannot be set to an output state, the default state is
Input

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• If the model can be an input or an output, and there was previously a model specified for
the pin, then the default state matches the direction/state set for the previous model
• If the model can be an input or an output, and there was NOT previously a model
specified for the pin (that is, a red question mark), then the default state is Input

Related Topics
“Setting IC Buffer Direction-State” on page 477

If Second Pin is Not Visible

This topic applies only to BoardSim.

The second, or "opposite," pin in a differential-net pair actually resides on a different net than
the first pin. BoardSim must automatically detect that a second net is involved, and makes its
pin(s) available for model choosing and simulation (i.e., BoardSim must detect an "associated
net"; see “Associated Nets” for more details). This association occurs in the following possible
ways:

• There is a terminating component (e.g., a resistor) on the board connecting the two nets
• The IBIS model you assigned for the first pin in the differential pair has internal
information stating that a second pin is involved
• The coupling between the nets exceeds the crosstalk threshold.
For SPICE models, BoardSim does not automatically extract the switching time used for
crosstalk calculations and you must type the approximate switching time into the Assign
Models dialog box.

If a net you are simulating, or the model you choose for its pin meets none of the above
conditions, then the net association does not occur and you cannot simulate differentially.
Table 10-12 summarizes the possibilities.

Table 10-12. Differential Modeling Conditions

Terminator across Model type Can simulate
transmission lines? differentially?
yes any yes
no IBIS differential yes
no IBIS non-differential no
no MOD or .PML no

Note that if the conditions for net association and therefore differential simulation are not met,
you can still simulate the two nets in the pair individually, in a single-sided fashion.

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About the MOD Libraries

About the MOD Libraries

If you cannot find the models you need to simulate the design, you might find suitable models in
the MOD libraries that ship with BoardSim/LineSim.

This topic contains the following:

• “TECH-MOD Library” on page 503

• “GENERIC-MOD Library” on page 504
See also: “How to Create a Custom IC Model” on page 523

TECH-MOD Library
Sometimes you are in a hurry to simulate and don’t have an exact model for a device. In these
cases, when there is no time to obtain the appropriate model from the vendor or create one
yourself, use the TECH.MOD library to get an approximate model that will get you simulating,
and—in many cases—be sufficiently accurate to give good analysis results.

TECH.MOD is based on the fact that the two most-important parameters in a driver-IC model
are the basic technology type and the approximate switching time of the output buffer. If you
know those two basic facts about an IC, which are usually easy to glean from a data sheet, you
can choose a model from TECH.MOD. While the model may not be exactly perfect, it will
usually be sufficient to proceed with simulation.

You can access TECH.MOD directly from the Select IC Model dialog box.

See also: “About the Select IC Model Dialog Box” on page 499

Cannot Save Into TECH-MOD

You can edit a model in TECH.MOD, but you cannot save the edited model back into
TECH.MOD. You must save the edited model to a different library.

See also: “Editing IC Models” on page 513

If you modify a Mentor Graphics-supplied library, you should rename it first. If you do not
change the library’s name, your version of the library will be overwritten next time you receive
updated HyperLynx software.

Other Libraries
DIODES.MOD contains models for several generic types of clamp diode. If you are using
external clamp diodes for termination, for example, you might try one of the models in
DIODES.MOD. (Or start with a model in DIODES.MOD and modify it to match the diode
you’re using.)

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About the MOD Libraries

When you use a model in DIODES.MOD, be sure to set the model’s buffer state to Input rather
than Output. (Diodes are passive devices; they don’t "drive." The output sides of the models in
DIODES.MOD are completely "open.")

EASY.MOD is similar to TECH.MOD, but contains models for older technologies.

GENERIC-MOD Library
Most of LineSim’s/BoardSim's standard-logic models are contained in the library
GENERIC.MOD. There are exceptions; some families have their own, separate .MOD libraries

Model Names in GENERIC-MOD

In GENERIC.MOD, the format for most models’ names is

family:type

Examples of device families are:

• 74ACxx
• 74FCTxx
• 74BCTxx
• MACH
• 74Fxx
• DRAM
The device types and their meanings are:

• GATE: gates, with "normal" current drive and capacitance; e.g., 74AC00, 74F74
• LIN-DRV or BUS-DRV: line drivers, with enhanced current drive and extra
capacitance; e.g., 74F244, 74AC245
• OPEN-COL: open-collector; e.g., 7406
• OPEN-DRN: open-drain
• PLD: any PLD or FPGA
• FST/SLW: fast or slow edge of a device with programmable slew rate
The naming format is used especially to distinguish between the normal-output devices and the
line drivers in standard-logic families. It also identifies models with special driver output stages,
like open collector or fast/slow versions of devices with programmable output slew rate.

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Searching for Models

Other models—especially those for more-specialized devices—use only the common device
name, without specifically identifying the model "type." This is true, for example, of bus-driver
families which come only with line-driver outputs.

GENERIC.MOD contains two models — 74HCXX:GATE and 74HCTXX:GATE — that each

have two versions. The "-1" version has low- resistance clamp diodes, and the "-2" version has
high-resistance. These families come in two versions, depending on the manufacturer. The low-
resistance version clamps overshoot and undershoot more effectively. If you’re not sure which
version you’re using, check with the manufacturer.

Modeling Bidirectional Devices

This topic describes how to choose models for bidirectional devices when you are using a
.MOD library, especially GENERIC.MOD.

When you are modeling a driver with a high-current output, e.g., an 74xx244 or 74xx245
(where xx is any technology type, like "HC" or "F"), use the line-driver version of the model.

When you are modeling a receiver, if the device is bidirectional (i.e., a transceiver) and you are
modeling the case where the driver is tristated and the device is receiving, use the line-driver
version. (It correctly models the extra capacitance of the tristated driver.)

But if the device is not bidirectional and you are modeling one of the input pins, use the "gate"
model, not the line-driver. The input in this case is no different than a standard gate’s input (no
extra capacitance).

Correct choices for the 74xx24x series:

Table 10-13. Example of Modeling ICs with .MOD Models
Device Correct driver model Correct receiver model
74xx240 LIN-DRV GATE
74xx241 LIN-DRV GATE
74xx242 LIN-DRV LIN-DRV
74xx243 LIN-DRV LIN-DRV
74xx244 LIN-DRV GATE
74xx245 LIN-DRV LIN-DRV

Searching for Models

Use the IC Model Finder dialog box to find device models in libraries. You can search for
component names, models provided by a specific vendor, and so on. You can open this dialog
box by clicking the Find Model button from the Select IC Model dialog box, REF-File Editor,
and QPL-File Editor.

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About IC Models

The model finder reads in a database representing models that have shipped with HyperLynx. If
you add new models to the model library directory(ies), you can update the model-finding
database to include the new models. See “Set Directories Dialog Box” on page 1854.

To search for IC models:

1. Click Find Model.

You can resize the IC Model Finder dialog box.
2. To search for text in the spreadsheet, type text into the Search Text box and click
Search.
Result: All rows containing the text are moved to the top of the spreadsheet with a
check mark in the Srch column.
3. To sort spreadsheet columns, click the column header once to sort in an ascending order
and click the column header again to sort in a descending order.
Example: To find the most-recent models in the database, click the File Date columns
header to sort from oldest to newest (ascending order), and then click again to sort from
newest-to-oldest (descending order).
4. To assign a model directly from the model finder, click anywhere on the row containing
the model you want to assign and click OK.
Result: The IC Model Finder dialog box closes and the model is automatically selected
in the Select IC Model dialog box or the REF/QPL Editor.
Restriction: While the spreadsheet includes .EBD models, they must be assigned with a .REF
or .QPL automapping file. If you opened the IC Model Finder dialog box from the Select IC
Model dialog box, selecting an .EBD model from within the spreadsheet has no effect.

Related Topics
“Select Directories for IC-Model Files Dialog Box” on page 1844

“Selecting Models and Values for Entire Components”

About IC Models
When planning your board simulation project, you may want to know which IC model
properties are important for signal-integrity simulation, what IC formats HyperLynx supports,
how the capabilities of various IC formats compare, and detailed information about each format.

This topic contains the following:

• “How ICs are Modeled for Signal-Integrity Simulation” on page 507

• “IC-Model Formats” on page 507

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About IC Models

• “Obtaining IC Models from Semiconductor Vendors” on page 509

• “The MOD - Databook - Format” on page 509
• “The PML - Package Model Library - Format” on page 510
• “The IBIS Format” on page 511
• “The EBD - Electrical Board Description - Format” on page 512

How ICs are Modeled for Signal-Integrity Simulation

A major difference between modeling for digital simulation and modeling for signal-integrity
simulation is that for signal-integrity modeling, the simulator does not need to model the logical
function of the IC. Only the characteristics of the driver’s output stage or the receiver’s input
stage matter. This means that BoardSim/LineSim only needs models for every unique buffer
type, not for every unique IC. For standard-logic devices especially, this simplifies a signal-
integrity tool’s modeling libraries.

For example, a 74AC04, a 74AC74, and a 74AC161 all have the same output stage, so all three
behave the same in a signal-integrity simulation and can be described by a single model. But a
74AC240 has a different, higher-current output stage, so it requires a different model. Likewise,
many of the I/Os on a microprocessor share the same device model, regardless of their logical
functions.

On the other hand, the models in a signal-integrity library must be detailed analog
characterizations, not merely logical models.

The key parameters for a signal-integrity driver model are rise/fall time, "on" impedance or V-I
characteristic, the nature of the impedance change from "off" to "on" (and vice versa), and the
output capacitance.

For a receiver model, the key characteristics are the nature of the clamp diodes, input resistance,
and input capacitance.

IC-Model Formats
HyperLynx supports the following device model formats:

• IBIS, EBD—Industry-standard formats that are supported by a variety of simulation

and IC vendors. IC vendors can create detailed and accurate .IBS and .EBD models
without revealing proprietary information.
• SPICE—Developed by the University of California at Berkeley.
Restrictions:

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About IC Models

o HyperLynx can use SPICE models containing active elements (such as transistor and
diodes) only in fully-licensed ADMS and HSPICE simulations.
o IC vendors may encrypt their SPICE models to protect proprietary information.
Encrypted models can be simulated only by a specific simulator. For example, if the
SPICE models are encrypted for HSPICE, then ADMS cannot simulate them.
• Touchstone®—Series models used to model connectors and packages. These files can
describe S-parameters (scattering), Y-parameters (admittance), Z-parameters
(impedance), and other parameters. Supported by a variety of simulation vendors.
Restriction: HyperLynx can use Touchstone models only in ADMS and HSPICE
simulations.
• .MOD—A HyperLynx proprietary format that is based on databook parameters. Many
HyperLynx standard-logic models are in .MOD format.
• .PML—An extension to the .MOD format that adds component pin-outs and package
parasitics.

IC Model Comparison
Table 10-14 compares characteristics of the models (format types) supported by HyperLynx:

Table 10-14. IC Model Comparison

Characteristics .IBS .EBD SPICE Touchstone .MOD .PML
Cannot be chosen X
interactively
Cannot be chosen X X
with .REF/.QPL file
Edit in HyperLynx X
.MOD editor?
Edit in HyperLynx X X
Visual IBIS Editor?
View in HyperLynx X
Touchstone and
Fitted-Poles
Viewer?
Packages modeled? X X X X
Complicated X X
interconnection
modeled?
Includes min/max? X X X X

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Table 10-14. IC Model Comparison (cont.)

Signals/pins listed in X X X
model?
Model includes both X X
driver and receiver?
Easy for users to X
create?
Supported by other X X X X
simulators?
Contains detailed X X
vendor specs?

Related Topics
“Supported SI Models and Simulators” on page 1264

“Obtaining IC Models from Semiconductor Vendors” on page 509

Obtaining IC Models from Semiconductor Vendors

The .IBS and .EBD formats are specifically intended to allow IC and board vendors to supply
signal-integrity models directly to their customers. You are strongly encouraged to request .IBS
and .EBD models from your vendors. As paying customers of the vendors, you have greater
leverage in demanding models than do EDA suppliers.

If you speak with a vendor who needs information about or software tools for .IBS or .EBD
model development, please have them contact Mentor Graphics.

Many IC manufacturers now make IBIS models available directly from their World Wide Web
or FTP sites. While Mentor Graphics attempts to gather up and make available to customers as
many of these models as possible, some manufacturers do not allow their models to be shipped
with third-party products. Also, new and updated models are appearing constantly.

Accordingly, you are strongly encouraged to browse manufacturer sites yourself to see what
additional IBIS models are available to you.

The MOD - Databook - Format

MOD models are described in ASCII libraries with extension .MOD. The .MOD format is
HyperLynx-proprietary and has been supported since 1989. Many of LineSim’s/BoardSim’s
standard-logic models are in a library called GENERIC.MOD.

LineSim/BoardSim has a dialog-box editor for modifying .MOD models. (See “Editing IC
Models” on page 513 for details on editing models.) You might edit a .MOD model, for

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example, as a starting point for a new model. Modified .MOD models can be saved to a user
library.

Although .MOD files are ASCII, they are not keyword-based and the .MOD ASCII format is
not published. As a result, Mentor Graphics recommends against modifying them with a text
editor; use the .MOD model editor in BoardSim/LineSim instead.

.MOD files model the silicon portion of an IC plus the device-package capacitance; package
inductance is not modeled. If you need package inductance, use an IBIS or .PML model. Also,
.MOD files can model min/max device characteristics as well as typical, but do so through a
pair "global" scaling factors that modify up/down the parameters in all .MOD models in a
simulation, to give a best-case/worst-case effect. By contrast, .IBS models can contain detailed
min/typ/max data on a per-device basis.

.MOD files themselves model the silicon portion of an IC; you can use the parasitic modeling
capability in LineSim (if you own it) to separately model an IC’s package. You can also convert
a .MOD model to .PML and include package characteristics.

See also: “About Parasitics for ICs and Passive Components”

.MOD models usually represent an entire family of ICs. For example, the 74ACXX:GATE
model in GENERIC.MOD represents the output of any non-line-driver 74AC IC. .MOD models
do not contain lists of the specific devices or signals they represent.

.MOD models combine drivers and receivers into a single model. The 74ACXX:GATE model
has a driver and receiver; the receiver represents input pins on any 74AC non-line-driver device.
For certain devices which are input- or output-only (e.g., a clamp diode), the other "side" of the
model can be set to all "off" characteristics and ignored (e.g., for a clamp diode, the output side
could be set to all "open" and never used).

.MOD models are inherently per-pin because they contain only a single model. In BoardSim, If
you assign a .MOD model using an automapping file, the same model is assigned to all the
component pins.

The PML - Package Model Library - Format

The .PML format is an extension to the .MOD databook format that adds component pin-out
and package-parasitic information to .MOD models. The .PML—"Package Model Library"—
format was added to give .MOD models a more-equal footing with IBIS models.

The .PML format works by adding a new library-file type (with extension .PML) that defines
components in an IBIS-like syntax. .PML component definitions attach specific .MOD models
to each pin on an IC, and add directionality (input, output, bidirectional, etc.) to each pin. .PML
also defines a component’s package, and supplies parasitic R, L, and C values for each pin.

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.PML files do not themselves contain .MOD models. Rather, .PML files define component pin-
outs and point to the models in a .MOD file that actually define the pin’s analog behavior. Thus,
the .PML file is really just an extension of the .MOD format. A .PML model requires two files:
the .PML file and the .MOD file to which it points.

The IBIS Format

The .IBS models are described in ASCII libraries with the extension ".IBS." BoardSim/LineSim
ships with a collection of .IBS libraries.

The .IBS models can optionally include detailed package models (pin R,L,C) and min/max data.
BoardSim/LineSim automatically simulates packages if the data are present; you can specify
whether to use min, typ, or max data during simulation.

See also: “Setting IC Operating Parameters” on page 551

The .IBS models are arranged into components. Each .IBS library may contain multiple
components; each component has a list of signals; each signal has an associated model. Each
signal may be input, output, or I/O.

The .IBS model format is described in the IBIS specification.

IBIS - I-O Buffer Information Specification

The "I/O Buffer Information Specification" (IBIS) is an industry standard for signal-integrity IC
modeling. IBIS has been rapidly endorsed by all of the major CAE vendors and IC
manufacturers.

HyperLynx (now part of Mentor Graphics) is proud that its LineSim Pro program was the first
program in the industry to be declared "IBIS Certified." HyperLynx was a founding member of
the IBIS Open Forum, the industry committee that defines and maintains the IBIS standard.

IBIS is significant because it allows semiconductor vendors to provide accurate models without
giving away the proprietary details of their silicon. This removes a key barrier that previously
made models difficult to get, or completely unavailable.

The current version of the IBIS specification defines two model formats, .IBS and .EBD. The
.IBS format is used to model ICs and is discussed below. The .EBD format is used to model
components such as ICs in complex packages, sub-boards and modules.

Related Topics
“The EBD - Electrical Board Description - Format” on page 512

“IBIS Specification” on page 1327

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The EBD - Electrical Board Description - Format

The .EBD format is an extension of the IBIS specification that allows electrical descriptions of
complicated interconnection. It is intended to model advanced IC packages or modules for
which a simple RLC description is not sufficient. While the electrical properties are described in
an .EBD model, the physical properties of the interconnection (i.e., trace length, stackup) and
the coupling properties are not.

.EBD models can point to one or more .IBS models; the .IBS models describe the IC(s)
mounted on the interconnect structure described in the .EBD model.

Restriction: In this release, BoardSim/LineSim does not support .EBD models that point to
other .EBD models.

You can specify whether to use min, typ, or max data during simulation.

See also: “Setting IC Operating Parameters” on page 551

.EBD models are described in ASCII libraries with the extension ".EBD."

.EBD libraries are arranged into components. Each .EBD library may contain multiple
components; each component has a list of signals; each external pin may be connected to a
combination of IC models, passive component networks, and other external pins.

The .EBD model format is described in the IBIS specification.

See also: “IBIS Specification” on page 1327

The current IBIS specification does not provide the means to supply coupling properties in
.EBD models, so crosstalk analysis cannot be performed within a component mapped to a .EBD
model.

Supply and Non-Supply Mismatches for EBD Models and HYP

File
When you assign an .EBD model to a component in a board file, it is possible to connect a
supply pin to a non-supply pin.

This topic applies only to BoardSim.

Table 10-15 describes BoardSim behavior when supply/non-supply mismatches occur:

Table 10-15. .EBD Supply Mismatches

Case Description BoardSim Behavior

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Table 10-15. .EBD Supply Mismatches (cont.)

#1 Board power supply joins .EBD non- .EBD net becomes a power supply and its
supply voltage is assigned to the board power
supply's
#2 .EBD power supply joins board non- Board net becomes a power supply and its
supply voltage is assigned to the .EBD power
supply's.

However the .EBD supply's voltage may be

uncertain, so you should check the voltage
before continuing.
#3 Board power supply joins .EBD While both pins are already supplies, but their
power supply voltages may not agree. If they conflict,
BoardSim changes the .EBD supply's voltage
to match the board supply's voltage.
#4 Board non-supply joins .EBD non- Nothing to do because no supplies are
supply involved.
For example of case #1, if an .EBD model is loaded and if one of its non-supply external pins
connects to a +3.3V power supply in the board file, then BoardSim changes the .EBD model's
non-power-supply net into a power-supply and sets its voltage to 3.3V.

Editing IC Models
HyperLynx provides a .MOD model editor and an IBIS model editor.

This topic contains the following:

• “Editing MOD IC Models” on page 513

• “Editing IBIS IC Models” on page 522

Editing MOD IC Models

IC models created in the .MOD format can be edited directly inside BoardSim/LineSim, with
the .MOD model editor. If you are unfamiliar with the .MOD format or how it compares to the
IBIS modeling format, see “IC-Model Formats” on page 507. Another supported format, .PML,
is an extension of .MOD that adds component pin-out and package characteristics.

This topic contains the following:

• “The MOD Format and Editor” on page 514

• “MOD Model Parameters” on page 514
• “Editing a MOD Model” on page 519

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• “Creating a New MOD Model” on page 520

• “Saving a MOD Model” on page 521
• “Deleting a MOD Model” on page 522

The MOD Format and Editor

The .MOD format is an ASCII format first created by HyperLynx (now part of Mentor
Graphics) in 1989 for its LineSim Pro product, and supported now in BoardSim/LineSim.
Though .MOD models are saved into ASCII libraries, the format is not keyword-based and
therefore difficult to edit directly with a text editor.

Instead, BoardSim/LineSim includes a .MOD model editor that allows you to edit models in a
Windows dialog box. The editor allows you to modify existing models and create new ones;
new models can be saved into user-defined libraries. .MOD models are based on parameters
commonly found in IC databooks, to make the models as easy as possible to create and support.

MOD Model Parameters

This topic describes the parameters that make up the output-driver half of a .MOD model. To
see the input-receiver parameters, see “Input Receiver Parameters” on page 517.

You can edit all of the parameters. See “Editing a MOD Model” on page 519 for details on how
to change these parameters in the .MOD model editor.

Output versus Input

Every .MOD model contains both output driver and input receiver information. This allows a
single .MOD model to describe a typical output and input for an IC or family of ICs.

For ICs with multiple output buffer or input buffer types, multiple .MOD models can be saved
into one IC- or family-specific library. If you need to model only an output or only an input, the
other half of the model (e.g., the input if you are modeling the output) can be ignored.

Output Driver Parameters

This topic describes the parameters that make up the output-driver half of a .MOD model. See
“Editing a MOD Model” on page 519 for details on how to change these parameters in the
.MOD model editor.

Transistor Type
Transistor type describes the basic technology type of an output-stage transistor (e.g., Schottky-
clamped bipolar or CMOS FET). You can customize a transistor’s model further with other
parameters like "on" resistance and slew time.

Valid transistor types:

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• CMOS: a CMOS FET

• Silicon: a fully saturating bipolar transistor
• Schottky: a Schottky-clamped bipolar transistor
• ECL: an ECL emitter-follower; set both the high and low stages to this for an ECL
device, even though there is really only one stage (the emitter)
• Open: nothing, i.e., no transistor at all
• Ramp: a special construct for simplifying a driver model; a resistance only, which
switches between stages infinitely fast

Transistor On Resistance
Transistor "on" resistance describes the effective, fully-on impedance of the upper- or lower-
stage transistor.

This is the slope of the DC output-buffer V-I curve in the databook. It is NOT the resistance
implied by the guaranteed worst-case DC currents, i.e., Ioh and Iol; these values are usually
unrelated to the driver’s dynamic switching characteristics and yield much too large a
resistance.

Slew Time
Slew time specifies the 10%-90% switching time of the upper- or lower-stage transistor.

Offset Voltage for Drivers

Offset voltage describes the effective offset for the upper- or lower-stage transistors from the
rail voltage. It models the internal biasing of the driver.

Special Note About ECL

Even though ECL output buffers are actually referenced only to Vcc, the Low Offset Voltage is
still interpreted in the .MOD editor as being from the low rail, in this case Vee. So, for example,
to make an ECL driver switch to –1.55V when its Vee = -4.5, set the low-side offset voltage to
+2.95 V.

Clamp-Diode Types
Clamp-diode type specifies the technology type of the upper- or lower-stage output clamp
diode. You can customize a clamp diode’s model further with the "on" resistance parameter.

Valid diode types:

• Silicon: a silicon clamp diode

• Schottky: a Schottky clamp diode

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Clamp-Diode On Resistance for Drivers

Clamp-diode "on" resistance describes any resistance effectively in series with the upper- or
lower-stage clamp diode.

This is the slope of the clamp-diode DC V-I curve in the databook. Sometimes, this data are
found in a special section of the databook that covers ESD issues.

Capacitance for Drivers

The capacitance specifies the total output capacitance of the driver, including transistors and
clamp diodes.

Default Power Supply

In LineSim, Default power supply specifies the default non-ground supply voltage off of which
the driver is run. LineSim’s built-in Vcc and Vss power-supply nets are set to the default-
power-supply voltages when you load a driver IC model.

In BoardSim, default power supply specifies the default non-ground supply voltage off of which
the driver is run. The default value applies only if BoardSim cannot find any power-supply nets
connected to the driver’s IC or if you explicitly choose to run the model off the typical power-
supply values; otherwise, a driver’s supply voltage is determined by the voltages to which its
Vcc and Vss pins are connected.

See also: “Assigning Power Supplies to ICs” on page 478

Measurement Thresholds and Loads for Receivers

These parameters are used by the Board Wizard to calculate delay and related data. They do not
affect a driver model’s waveform, only how those waveforms are measured by the Board
Wizard. They are unused in LineSim.

Table 10-16 provides details about the parameters:

Table 10-16. Batch Simulation - Driver Measurement Thresholds and Loads

Parameter Explanation
Vmeasure Voltage at which the driver is considered
"switched," i.e., when it transitions past this
voltage, it has switched
Rload The pull-up/down resistor used in the IC
manufacturer’s standard driver-output test load
Vload The pull-up/down voltage used in the IC
manufacturer’s standard driver-output test load

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Table 10-16. Batch Simulation - Driver Measurement Thresholds and Loads

Cload The capacitance used in the IC manufacturer’s
standard driver-output test load
A model’s Vmeasure value is displayed in both the Select IC Model dialog box (in the I/O Type
area) and the Assign IC Models dialog box (in the Buffer Settings) area.

Most devices use standard values for these parameters (Vmeasure=1.5V, Rload=1000ohms,
Vload=0V, Cload=50pF). They do not normally need to be changed from these values unless
you are modeling ECL or a newer, low-voltage driver family like LVDS, GTL, etc. Vmeasure
can also sometimes be calculated as: (high input threshold + low input threshold) / 2.

Input Receiver Parameters

This topic describes the parameters that make up the input-receiver half of a .MOD model. See
“Editing a MOD Model” on page 519 for details on how to change these parameters in the
.MOD model editor.

Input Resistance
Input resistance describes the effective resistance of the receiver’s biased input stage.

Generally, you can neglect input resistance for signal-integrity simulation, since it is normally a
large value. The combination of input resistance and offset voltage should result in the input
current specified in the databook.
For CMOS, the input resistance is typically 1 Mohm or more; for signal-integrity simulation, 1
Mohm is sufficient.

Offset Voltage for Receivers

Offset voltage describes the equivalent voltage of the receiver’s input-stage biasing.

The offset voltage is the open-circuit voltage of the input pin. For CMOS, this is typically
Vcc/2.

Clamp-Diode Type
Clamp-diode type specifies the technology type of the upper- or lower-stage input clamp diode.
You can customize a clamp diode’s model further with the "on" resistance parameter.

Valid diode types:

• Silicon: a silicon clamp diode

• Schottky: a Schottky clamp diode

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Clamp-Diode On Resistance for Receivers

Clamp-diode "on" resistance describes any resistance effectively in series with the upper- or
lower-stage clamp diode.

This is the slope of the clamp-diode DC V-I curve in the databook. Sometimes, this data are
found in a special section of the databook that covers ESD issues.

Capacitance for Receivers

The capacitance specifies the total input capacitance of the receiver, including transistors and
clamp diodes.

Measurement Thresholds and Loads

These parameters are used in the Board Wizard to calculate delay and related data. They affect
only how receiver-input signals are measured by the Board Wizard. They are unused in
LineSim.

Table 10-17 provides details about the parameters:

Table 10-17. Batch Simulation - Receiver Measurement Thresholds
Parameter Explanation
Vih or Vih+ Receiver’s primary high-going threshold; receiver is guaranteed to have
recognized as a ‘1’ any rising-edge signal that crosses this value
Vih- Receiver’s secondary high-going threshold; for devices with hysteresis,
the high-going threshold backs down to this value after Vih+ is crossed;
if no hysteresis, disable Schmitt Trigger check box, or set this value =
Vih+
Vil+ Receiver’s secondary low-going threshold; for devices with hysteresis,
the low-going threshold backs up to this value after Vil- is crossed; if no
hysteresis, disable Schmitt Trigger check box, or set this value = Vil-
Vil or Vil- Receiver’s primary low-going threshold; receiver is guaranteed to have
recognized as a ‘0’ any falling-edge signal that crosses this value

As indicated in Table 10-17, only two of the threshold values (Vih+ and Vil-) are needed for
most devices; the other two (Vih- and Vil+) are important only for receiver inputs that exhibit
hysteresis. If a device has no hysteresis, you can hide the "secondary" thresholds from view, or
set them equal to the "primary" values.

Hiding the Secondary Thresholds

To hide the "secondary" thresholds for devices that do not have hysteresis (i.e., whose inputs are
not "Schmitts"):

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• In the Edit .MOD Model dialog box, in the Measurement Thresholds and Loads area,
clear the Schmitt Trigger check box.
A model’s input-threshold values are displayed in both the Select IC Model dialog box (in the
I/O Type area) and the Assign IC Models dialog box (in the Buffer Settings) area.

Most devices use standard values for these parameters (Vih+ = Vih- = 2.0V, Vil+ = Vil- =
0.8V). They do not normally need to be changed from these values unless you are modeling
ECL or a newer, low-voltage driver family like LVDS, GTL, etc.

Editing a MOD Model

To edit a .MOD model:

• Models menu > Edit Databook IC Models.

Choosing a MOD Model to Edit

The first step in editing a .MOD model is to choose the library and model.

To choose the model to be edited:

1. In the Library and Model area, in the Model Library list, select the library containing the
model you want to edit.
2. In the Device Model list, and select the model.
The libraries displayed in the combo box are the .MOD files in the directory(ies) pointed to by
the Model Library File Path directory setting. Only libraries in this directory can be accessed.

See also: “Select Directories for IC-Model Files Dialog Box” on page 1844

Choosing MOD Driver or Receiver

Once the model is chosen, you must choose whether to edit its output-driver or input-receiver
half.

To choose the output or input half of the model:

• In the Library and Model area, select Output or Input.

If you change the radio-button setting, the contents of the .MOD-model-editor dialog box
change to show different parameters.

Editing the MOD Model

To edit the model:

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1. Change the transistor types, diode types, and default power-supply voltage, if needed, by
choosing new values from the lists.
2. Change other parameters by typing new values into the boxes.

Editing Both Driver and Receiver

You can edit both halves of a model (output and input) by editing one half; clicking the opposite
radio button in the Library and Model area; then editing the other half.

Creating a New MOD Model

To create a new model, start with an existing one. If you can find a model in GENERIC.MOD
(or one of the other libraries that ships with LineSim or BoardSim) that is similar to the model
you want to create, choose that model and then edit it.

If you cannot think of a similar model in the supplied libraries, choose any model as a starting
point and completely change its parameters, if necessary.

Once you have created the new model, save it.

See also: “Saving a MOD Model” on page 521

TECH.MOD or GENERIC.MOD almost always contain a model which is a good starting point
for another, new model. Choose the closest match to the IC you’re modeling, and change some
parameters. As examples of starting with GENERIC.MOD, if the IC is CMOS and has an
output slew time faster than 2 ns, start with a 74AC line driver. If it’s CMOS with a slower slew
rate, start with 74HC. If it’s a bipolar IC, start with a 74AS line driver. If it’s an ECL IC, start
with 100K ECL.

Setting the Default Vcc or Vee Voltage

In LineSim, built-in Vcc and Vss power-supply nets are set to the default-power-supply
voltages when you load a driver IC model. In BoardSim, the default Vcc or Vss voltage applies
only if BoardSim cannot find any power-supply nets connected to the driver’s IC.

See also: “Assigning Power Supplies to ICs” on page 478

LineSim and BoardSim give you a number of choices for default Vcc/Vss voltage. (You must
use one of the pre-supplied choices; you cannot type your own value.) The second voltage in the
pair is always 0.0V. For example, if you choose 3.0V, VCC=3.0V and VSS=0.0V; if you
choose -5.2V, VCC=0.0V and VSS=-5.2V.

5.0V/0.0V are the default values for all non-ECL models; 0.0V/-4.5V and 0.0V/-5.2V are the
defaults for the appropriate ECL models.

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Saving a MOD Model

After you have edited a model, you must save it into a library.

If you are changing an existing model, save it back into the same library and under the same
model name as when you chose it. If you are creating a new model, save it into a different
library and/or under a different model name.

Saving to the Same Library and Model Name

To save a model to the same library and model name:

• In the .MOD-model-editor dialog box, click Save. After a brief pause, the library file is
updated.

Saving to a Different Library or Model Name

To save a model to a different library and/or model name:

1. In the .MOD-model-editor dialog box, click Save As.

2. If you are saving to a different library, in the Library Name list, select or type the library.
3. If you are saving to a different model name, in the Model Name box, type the model
name.
4. Click OK. After a brief pause, the library file is updated.

Cannot Save into GENERIC-MOD or TECH-MOD

You can edit a model in the BoardSim/LineSim-supplied libraries GENERIC.MOD and
TECH.MOD, but you cannot save the edited model back into either library; you must save to a
different library. The model editor will not write into GENERIC.MOD or TECH.MOD.

It often makes sense to edit a model in GENERIC.MOD or TECH.MOD as a starting point for
creating a new model. Once you have loaded and modified the model, save it into an existing
library of your own, or into a completely new library.

If you modify a Mentor Graphics-supplied library, you should rename it first. If you do not
change the library’s name, your version of the library will be overwritten next time you receive
updated HyperLynx software.

Creating a New Library

To create a new library:

• Follow the steps in “Saving to a Different Library or Model Name” on page 521, except
for the library name, type a completely new name.

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When you type the library’s name, the extension .MOD is optional; if you omit it, it is
automatically provided.

Deleting a MOD Model

You can delete models out of .MOD libraries. Before deleting a model, be certain that you never
want to use it again: it will be removed from the .MOD file and lost.

If a deleted model is recorded in a BoardSim session (.BUD) file, the pin that calls out the
deleted model will not have a model when the board is re-loaded. BoardSim intentionally does
not give warnings about models in the session file it cannot find, so that if a session file records
a large number of models that do not any longer exist, you can still load the board. For pins that
call out the missing models, you must re-choose models.

See also: BoardSim Session Files

To delete a .MOD model:

1. Models menu > Edit Databook IC Models.

2. In the .MOD-model-editor dialog box, in the Model Library list, select the library
containing the model you want to delete.
3. In the Device Model list, select the model.
4. Click Delete. BoardSim/LineSim asks if you are sure you want to delete the model;
click OK.

Deleting Models from GENERIC-MOD

You cannot delete a model in the BoardSim/LineSim-supplied libraries GENERIC.MOD or
TECH.MOD. If you try to, BoardSim/LineSim gives an error message.

You can delete models from other .MOD libraries (libraries other than GENERIC.MOD and
TECH.MOD) supplied with BoardSim/LineSim.

Editing IBIS IC Models

IC models created in the IBIS format can be edited directly inside LineSim or BoardSim, using
the Visual IBIS Editor. If you are unfamiliar with the IBIS format or how it compares to the
.MOD modeling format, see “IC-Model Formats” on page 507. Another supported format,
.PML, is an extension of .MOD that adds component pin-out and package characteristics.

See also: “Creating and Editing IBIS Models” on page 403

Because most IBIS models come directly from the semiconductor manufacturer with
guaranteed data, users do not typically edit them. You may want to create your own IBIS
libraries, however, to model custom devices, ASICs, etc. But before creating an IBIS model,

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consider whether the .MOD modeling format would meet your needs: it is simpler and easier to
create models with. See “IC-Model Formats” on page 507 for a comparison of the .MOD and
IBIS formats.

How to Create a Custom IC Model

Sooner or later, you will need an IC model which neither Mentor Graphics nor the silicon
vendor can immediately supply you. This might be for an ASIC, an obsolete IC, a brand-new
IC, etc. Fortunately, it is not difficult to create IC models in LineSim or BoardSim.

The first thing to decide is whether to model the IC with the .MOD or IBIS format. See “IC-
Model Formats” on page 507 for a detailed comparison of the formats.

It is generally easier to create a model with the .MOD format, because:

• BoardSim/LineSim includes a dialog-box editor for .MOD models, which creates model
libraries and files for you
See also: “Creating a New MOD Model” on page 520
• Less device data are required to create a .MOD model than to create an IBIS model
• There is almost always an existing, similar model to use as a starting point for a .MOD
model
On the other hand:

• IBIS is the new, emerging signal-integrity modeling standard; creating a model is a good
way of becoming familiar with IBIS
• An IBIS model is fairly easy to create using the HyperLynx Easy IBIS Wizard.
See also: “Creating IBIS Models with the Easy IBIS Wizard” on page 450
• IBIS models are portable to other simulators
In order to create a good .MOD model of a driver IC, you must have the following device data:

• The transistor technology (bipolar, Schottky bipolar, CMOS FET, etc.)

• The effective "on" resistance of the upper- and lower-stage output transistors
• The slew time of the low-to-high and high-to-low switching transitions
There are other parameters in the model, too, but the remainder are less critical; you can more
safely approximate them, if needed.

In order to create a good IBIS model of a driver IC, you must have:

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Editing IC Models

• At least an approximation of the upper- and lower-stage V-I output curves (although the
Easy IBIS Wizard will create a curve for you if you know only the driving impedance,
i.e., "on" resistance)
• the slew time of the low-to-high and high-to-low switching transitions
Thus the primary difference between the data requirements for a .MOD model and an IBIS
model of a driver IC is the level of detail with which you need to know the driver’s V-I output
characteristics. A .MOD model runs surprisingly well knowing only the transistor’s basic
technology (is it bipolar?, CMOS?, etc.) and the effective "on" resistance of the output stage; for
a good IBIS model, you need to know at least a few points on the V-I curve, or use the Easy
IBIS Wizard, which will create a curve for you from an "on" resistance.

To create an IBIS model but know only one V-I data point on an output stage’s curve, it is
critical to know where on the curve that point is. If the point is taken near the "knee" of the
curve, such that the driver current saturates beyond the point, then you can safely enter a two-
point table with entries 0,0 and V1,I1 in your IBIS table, or better yet, use the implied resistance
in the Easy IBIS Wizard. But if the point is taken at the beginning or in the middle of the curve,
such that the driver’s current keeps increasing beyond the point, the two-entry table is
erroneous.

Why? Because if a voltage is above or below the two points, BoardSim/LineSim holds a
driver’s current at the previous value in the table in an attempt to model the driver’s saturation.
If the largest current in your table is significantly lower than the driver’s actual maximum
current, your model will be erroneous.

MOD Example - Modeling an ASIC Driver

Suppose you need to model an output buffer on a CMOS ASIC. As far as you can tell, the
output buffer looks similar to an AC-standard-logic-family driver, but may have a different slew
rate, capacitance, and so forth. This example shows how you can create your own buffer model
using the .MOD format.

First, collect whatever data you can about the output driver; this may require going back to the
silicon vendor and requesting extra information. The most-critical data are for output V-I
characteristics and slew times. (Many vendors are starting to publish V-I curves in their data
sheets.)

To begin creating the model:

1. With no schematic created or loaded in LineSim, or with no board loaded in BoardSim,

click Models menu > Edit Databook IC Models.
2. In the Library and Model area, on the Model Library list, click GENERIC.MOD. A
model from this library often makes a good starting point for a new model.
3. In the Device Model list, select 74ACXX:GATE, since the ASIC output is somewhat
similar to the 74AC standard-logic family’s.

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4. Click Save As. In the Save .MOD Model As dialog box, type "ASIC.MOD" in the
Library Name box and "OUTPUT" in the Model Name box.
5. Click OK.
Result: This action saves the 74AC model into a separate model and library
(ASIC.MOD), which can now be edited to create the ASIC model.
To edit the model so it matches the ASIC output:

1. In the Output Drivers area of the Edit .MOD Model dialog box, on the Type list select
CMOS.
2. Calculate an effective "on" resistance for the ASIC buffer: find the "knee" point in the
upper stage’s curve (the point where the current starts to "roll off" or saturate) and the
zero-current point; calculate R_on =delta_V/delta_I; enter this in the high stage’s
Resistance box; repeat for the lower stage.
If you do not have this data, you can measure it using a sample IC, a resistor, and a
variable voltage supply. If you do not have time for even a simple measurement, then
guess! Your models do not need to be exact to get you a simulation that is at least "in the
ballpark." Probably, a CMOS ASIC output is not much different than a 74AC output if
the two are fabricated in similar geometries. But be conservative and make the ASIC run
"hotter," say, 5 ohms.
3. Enter the Slew Time for the upper and lower stages.
If you do not have this data, you can measure it with an oscilloscope. (But be sure that
you use a high-bandwidth scope, preferably 500-MHz or above. Otherwise, you may
measure only the scope’s response, not the true slew time.) If you do not have time for a
measurement, then guess! Again, the ASIC output probably is not much different than a
74AC output if the two are fabricated in similar geometries. But be conservative and
make the ASIC run "hotter," say, 1.0 ns instead of 2.0.
4. Leave the Offset Voltage and Clamp Diode data the same as in the 74AC model.
You could measure the effective diode resistance with a resistor and variable power
supply, but driver clamp diodes are usually insignificant in signal-integrity simulations
because the driver itself is such a low impedance.
5. If you know it, enter the driver output Capacitance.
If you do not know it, leave the data the same as in the 74AC model. (The difference
between, say, 5 pF and 7 pF is not terribly significant.)
To save the model:

• In the Edit .MOD Model dialog box, click Save. You now have a custom model
OUTPUT for your ASIC buffer, in a library called ASIC.MOD.

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Creating an IBIS Model

If you decide to create your own model in IBIS format, use Mentor Graphics' Easy IBIS
Wizard. This program interviews you about your buffer’s characteristics and then automatically
generates a syntactically correct, ready-to-simulate IBIS file from your data. The Easy IBIS
Wizard makes creating IBIS files relatively easy, even for novices.

See also: “Creating IBIS Models with the Easy IBIS Wizard” on page 450

Selecting and Creating Ferrite-Bead Models

This topic contains the following:

• “Selecting Ferrite-Bead Models in BoardSim” on page 526

• “About the Ferrite-Bead Models Supplied by Mentor Graphics” on page 527
• “Simulating Before a Ferrite-Bead Model is Chosen” on page 528
• “How Ferrite-Bead Models Display” on page 528
• “Creating Your Own Ferrite-Bead Models” on page 529
• “Example of User-Defined Bead Model Library File” on page 532

Selecting Ferrite-Bead Models in BoardSim

Ferrite beads require a model that is more complex than for other passive components, such as a
resistor. Other passive components are modeled with a single value, for example 100 ohms or
33 pF. By contrast, ferrite beads are modeled more like an IC, with a detailed model contained
in a library.

HyperLynx ships with a library of representative ferrite beads from several leading
manufacturers. If there is no model for the exact ferrite bead you want to simulate, you can also
create your own ferrite-bead models.

See also: “Creating Your Own Ferrite-Bead Models” on page 529

A ferrite-bead model applies to all the pins on the component. By contrast, when you
interactively assign an IC model to component, the assignment applies to a specific pin. In
BoardSim, you cannot use .REF and .QPL automapping files to assign ferrite-bead models to
components.

To select a ferrite-bead model:

1. If you are using BoardSim, do the following:

a. Select net > Select Component Models or Edit Values button .

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Or
Right-click over a ferrite bead pin and click Assign Model.
b. In the Pins list, select a pin on the ferrite bead for which you want to choose a model.
Make sure that the models area displays a bead icon for the pin.
c. Click Select.
Result: The Select Ferrite Bead Model dialog box opens.
d. Go to step 3.
2. If you are using LineSim, do one of the following over the ferrite-bead component:
• If you are using the free-form schematic editor, double-click.
• If you are using the cell-based schematic editor, right-click.
Result: The Select Ferrite Bead Model dialog box opens.
3. In the Vendors list, select the vendor for whom you want choose a model.
4. In the Part Numbers Lists, select the part matching the bead for which you want a model.
5. Click OK.
Alternative: Double-click the part number.
Result: The ferrite-bead model is assigned to all the pins on the component.
6. If you are using LineSim, click the Parasitics tab and edit the values, if needed.
For axially-leaded components, enter the sum of both leads' inductance, capacitance,
and resistance.
7. Repeat steps 1-6 as needed to select models for other ferrite beads.
8. If you are using BoardSim, click Close.

Related Topics
“Selecting and Creating Ferrite-Bead Models” on page 526

About the Ferrite-Bead Models Supplied by Mentor

Graphics
All of the models listed in the Select Ferrite Bead Model dialog box (unless you have created
additional models of your own) are contained in a Mentor Graphics-supplied library called
"BSW.FBD." This library contains a representative sampling of beads from several of the
leading manufacturers. Usually, even if the bead you’re using is not contained in the library,
you can find a close match to it in BSW.FBD.

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To create a bead model of your own, you can do so by creating a file called "USER.FBD." For
details on how to create your own bead models, and how LineSim/BoardSim models ferrite
beads generally, see “Creating Your Own Ferrite-Bead Models” on page 529.

Simulating Before a Ferrite-Bead Model is Chosen

If you run a simulation before a model is chosen for a ferrite bead (when it still displays with a
red question mark in the Pins list), the ferrite bead is modeled as a 0.0-ohm resistor. This is
equivalent to there being no bead present, or the bead being shorted out.

How Ferrite-Bead Models Display

This topic provides details about the information displayed in the Select Ferrite Bead Model
dialog box.

Model Values Area

For the currently selected vendor and part number, the Model Values area shows an equivalent
L-R-C model for the bead. These values are automatically synthesized from three of the bead’s
impedance-vs-frequency points.

Impedance versus Frequency Graph

Above the Model Values area and Vendor and Part Number list is a graph showing the
impedance of the currently selected bead versus frequency. It is this curve that determines how
a given bead responds on your board when terminating a signal.

If you are trying to find a model for a bead which is not specifically listed in BSW.FBD, look
through the Mentor Graphics-supplied models for the one whose impedance curve best matches
the curve for the bead you’re using. Key parameters are the peak impedance and the overall
shape of the curve (is it fairly flat, or sharply peaked?).

See also: “About the Ferrite-Bead Models Supplied by Mentor Graphics” on page 527

Ferrite-Bead data sheets normally show impedance-vs-frequency curves. If your data sheets
don’t include curves, contact your bead vendor and demand more information.

Ferrite beads are often described in terms of their impedance at a nominal frequency, usually
100 MHz. However, simply because two vendors’ beads are both called "120-ohm" (both have
approximately 120 ohms’ impedance at 100 MHz) does not mean they behave the same in-
circuit. Look at their complete impedance curves to determine how similar they actually are.

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Creating Your Own Ferrite-Bead Models

A ferrite bead, even though a passive component, requires a complex model that cannot be
summed up in simple numeric value (unlike a resistor or capacitor value). Accordingly,
LineSim/BoardSim includes a library of ferrite-bead models, much like it includes libraries of
IC models.

LineSim/BoardSim ships with a library of ferrite-bead models (BSW.FBD). However,

eventually you may want to model a bead not contained (or with no close equivalent) in the
program’s library. Fortunately, it is easy to add your own ferrite-bead models to the user-
defined bead library, USER.FBD.

When you first install LineSim/BoardSim, there is no file USER.FBD. You create it the first
time you need to add your own bead model.

Before you attempt to create your own definition, you should understand the .FBD file syntax
fully.

This topic contains the following:

• “How Ferrite Beads are Modeled” on page 529

• “Library File for User-Defined Bead Models - USER-FBD” on page 530
• “Syntax for Ferrite-Bead Models” on page 530
• “Creating a User-Defined Bead Model Library” on page 530
• “User-Defined Bead Model Library Example - Defining a Bead Model” on page 531
• “Saving User-Defined Bead Model Libraries” on page 532
See also: “FBD File Specification” on page 1268

How Ferrite Beads are Modeled

LineSim/BoardSim models a ferrite bead with an L-R-C model. (This is the same method as
used by several of the more-sophisticated SPICE packages.) However, the program does not
require the models’ creator to know the values of L, R, and C; these are complex and would
probably never be known even to the vendor of a particular ferrite bead.

Instead, LineSim/BoardSim synthesizes an equivalent ferrite-bead model from four pieces of

data that can be read from any basic ferrite-bead data sheet:

• the bead’s DC resistance (including package resistance), and

• three points of impedance versus frequency

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Even summary data sheets on a ferrite bead almost always give these values: a DC resistance
and a graph of impedance versus frequency. The three Z-vs-f data points can be read from the
graph.

Library File for User-Defined Bead Models - USER-FBD

LineSim/BoardSim ships with a library, BSW.FBD, that contains a representative sampling of
ferrite-bead models from several leading manufacturers. Usually, even if the exact bead you
want to simulate is not modeled in BSW.FBD, you can find a close substitute among the
shipping bead models.

See also: “Selecting Ferrite-Bead Models in BoardSim” on page 526

Still, if you are using a bead which is not in the Mentor Graphics-supplied library and for which
you want an exact model, you can create a custom model and store it in a library called
"USER.FBD." When you interactively model a ferrite bead in LineSim/BoardSim, the program
reads the models in BSW.FBD, and then, if USER.FBD exists, reads its models, too. In the
Select Ferrite Bead Model dialog box, the models from USER.FBD are promoted to the
beginning of the Vendor list, so that you see your custom models first.

Ferrite-bead (.FBD) library files must be stored in the root LineSim/BoardSim directory. This
differs from IC-model libraries (which are typically stored in the LIBS sub-directory under the
root directory).

Syntax for Ferrite-Bead Models

USER.FBD must be written in LineSim/BoardSim’s .FBD-file format, which is described in
“FBD File Specification” on page 1268. The BSW.FBD file contains a header which succinctly
describes the format. If you choose to look at BSW.FBD for a format definition (or even to use
it as a starting point for your own USER.FBD file), make a copy of the file first and edit the
copy; be careful not to edit or otherwise damage BSW.FBD itself.

Creating a User-Defined Bead Model Library

USER.FBD must be ASCII-only; create it in a text editor (like the HyperLynx File Editor), not
an editor that introduces non-ASCII formatting characters into the file. The file must be located
in LineSim’s/BoardSim’s root directory (i.e., the directory that BSW.EXE is installed in.)

You might want to copy a portion of BSW.FBD to USER.FBD to give yourself a "head start" on
creating the new library. Then you can modify existing bead models to create your own. Be
careful not to leave any bead-model names in USER.FBD that already exist in BSW.FBD,
where "names" means combinations of vendor and part-number names.

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User-Defined Bead Model Library Example - Defining a Bead

Model
Suppose you need to model a bead called "Matic19" from a vendor named "Bead-O-Matic."
Assume there is no model for this bead in BSW.FBD.

To create USER.FBD:

1. In a text editor (like the HyperLynx File Editor), begin editing a new file. Be sure you
use a text editor, not a word processor that inserts non-ASCII formatting characters into
the file.
2. At the top of the file, place these two lines:
{FBD}
{VERSION=1.0}

To enter the bead’s definition:

3. Immediately following the two header lines, add the definition of the new bead:
********************** My Ferrite Bead Models **********************
{MANUFACTURER=Bead-O-Matic}
{BEAD=Matic19
(R_DC=0.035)
(PT1=6.0MHZ, 4.0)
(PT2=100.0MHZ,19.0)
(PT3=500.0MHZ,27.0)
}
See “Where the Bead Data Came From” on page 531 for a description of how the bead-
model data was determined.
4. End the file with the line:
{END}

Where the Bead Data Came From

In the example model above, the DC resistance value and three impedance-versus-frequency
points are all taken directly from the bead’s data sheet. (It is standard practice that ferrite-bead
data sheets include Z-vs-f graphs.)

The only "trick" to creating a model is to know which three points to take from the impedance
graph. For detailed rules for choosing the three points, see “FBD File Specification” on
page 1268. In this case, the frequency points were at:

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• About 10% of the nominal frequency (100 MHz)

• The nominal frequency (since the resonant frequency was not available—off the graph)
• The highest frequency on the graph

Saving User-Defined Bead Model Libraries

To save USER.FBD:

• Save the file as USER.FBD, into LineSim’s/BoardSim’s root directory. (For example, if
the program is installed in
C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx, save the file as
C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx\USER.FBD).
The new bead model will be available in LineSim/BoardSim as soon as you load (or reload) a
board. (BSW.FBD and USER.FBD are read every time a board is loaded.)

Example of User-Defined Bead Model Library File

Below is a complete sample USER.FBD file, for two imaginary ferrite beads:

{FBD}
{VERSION=1.0}
********************** My Ferrite Bead Models **********************
{MANUFACTURER=Bead-O-Matic}
{BEAD=Matic19
(R_DC=0.035)
(PT1=6.0MHZ, 4.0)
(PT2=100.0MHZ,19.0)
(PT3=500.0MHZ,27.0)
}
*****************************************************************
{MANUFACTURER=Bead-O-Rama}
{BEAD=Bead120
(R_DC=0.42)
(PT1=2.0MHZ, 3.0)
(PT2=100.0MHZ,120.0)
(PT3=300.0MHZ,200.0)
}
{END}

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 Simulating Signal Integrity with the Oscilloscope
Preparing Designs for Interactive SI Simulation

Chapter 11
Simulating Signal Integrity with the
Oscilloscope

Use the oscilloscope to interactively simulate signal integrity and display the waveforms or eye
diagrams. In BoardSim, you simulate the selected net and its associated nets. In LineSim, you
simulate all the nets in the schematic that have an enabled driver.

You can measure simulation results automatically or manually. You can save simulation results
to a file for further analysis in another program or to share with others.

This topic contains the following:

• “Preparing Designs for Interactive SI Simulation” on page 533

• “Enabling SI Simulation Options” on page 536
• “Setting Up the Oscilloscope” on page 537
• “Running Interactive Signal-Integrity Simulations” on page 566
• “Measuring Waveforms and Eye Diagrams” on page 578
• “Saving and Loading Waveform Files” on page 596
• “Documenting Interactive Simulation Results” on page 599

Related Topics
“Simulations Overview - Pre-Layout Tasks”

“Simulations Overview - Post-Layout Tasks”

“Preferences Dialog Box - Oscilloscope Tab” on page 1824

“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

“Simulating Signal Integrity with Sweeps”

Preparing Designs for Interactive SI Simulation

This topic contains the following:

• “Minimum Simulation Requirements” on page 534

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Preparing Designs for Interactive SI Simulation

• “Editing Lossy Transmission-Line Properties” on page 534

Minimum Simulation Requirements

Before you simulate, you must have an electrically valid stackup and you must enable a driver
in the schematic (LineSim) or selected net (BoardSim).

The requirement to have a valid stackup applies in LineSim even if you have not modeled any
transmission lines in the schematic with the stackup method. However LineSim always starts a
new schematic with a valid default stackup, so this requirement is satisfied even if your
schematic has no stackup-based transmission lines.

See also: “Creating and Editing Stackups” on page 353, “Interactively Selecting IC Models” on
page 467

Editing Lossy Transmission-Line Properties

Use either the stackup editor or the Edit Transmission Line dialog box to edit lossy properties.

Editing Lossy Properties in the Stackup Editor

Use the stackup editor to set lossy properties when you use any of the following:

• BoardSim
• LineSim and the stackup transmission line type
• LineSim and the coupled stackup transmission line type
To set lossy properties using the stackup editor:

1. Load the board into BoardSim or load the schematic into LineSim.
2. On the toolbar click Edit Stackup .
3. Specify the following PCB stackup properties:
• Metal resistivity for all signal and plane layers.
• Loss tangent for all dielectric layers.
See also: “Editing Stackups” on page 371
4. Click OK.

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Editing Lossy Properties in the Edit Transmission Line Dialog

Box
Use the Edit Transmission Line dialog box if you are using LineSim and any of the following
transmission line types:

• Microstrip
• Buried microstrip
• Stripline
• Wire over ground
To set lossy properties using the Edit Transmission Line dialog box

1. Load the schematic into LineSim.

2. Do one of the following over the transmission line:
• If you are using the free-form schematic editor, double-click.
• If you are using the cell-based schematic editor, right-click.
Result: The Edit Transmission Line dialog box opens.
3. In the Uncoupled area, click one of the following transmission line types:
• Microstrip
• Buried Microstrip
• Stripline
• Wire Over Ground
Result: The Values tab automatically opens.
Lossy simulation is not available for the other transmission line types in the Uncoupled
area, such as Simple.
4. In the Loss tangent area, type the loss tangent for the dielectric material.
5. Click Advanced. The Advanced Impedance Preferences dialog box opens.
6. In the Bulk resistivity box, type the new value, in ohms-meter at 20 degrees Celsius.
7. Click OK twice.

Related Topics
“Simulating Signal Integrity with the Oscilloscope” on page 533

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Enabling SI Simulation Options

Enabling SI Simulation Options

You can include or exclude from signal-integrity simulation several types of electrical
properties.

This topic contains the following:

• “Enabling Crosstalk Simulation in BoardSim” on page 536

• “Enabling Crosstalk Simulation in LineSim” on page 536
• “Enabling Lossy Transmission-Line Modeling” on page 536
• “Enabling Via Modeling” on page 537

Enabling Crosstalk Simulation in BoardSim

Requirement: The Crosstalk license is required to enable crosstalk and differential-pair
simulation in BoardSim.

BoardSim automatically identifies as coupled differential pairs any nets driven by IBIS model
pins listed in a [Diff Pin] keyword. You can disable coupling for this type of differential pair by
disabling the “Always treat diff pairs as coupled” option on the Advanced tab of the Preferences
dialog box. Coupling for this type of differential pair is not affected by Setup menu > Enable
Crosstalk Simulation settings, by crosstalk threshold voltages, or whether you have checked out
a crosstalk license.

For other types of nets, BoardSim couples nets when you enable crosstalk simulation and set the
crosstalk threshold voltage to a value lower than the simulated crosstalk voltage.

See also: “Running Interactive Crosstalk Simulations in BoardSim”, “Installed Options Dialog
Box” on page 1766, “Preferences Dialog Box - Advanced Tab” on page 1792

Enabling Crosstalk Simulation in LineSim

Requirement: The Crosstalk license is required to create coupling regions in LineSim.

LineSim automatically simulates crosstalk among transmission lines that belong to the same
coupling region.

See also: “Adding Coupling to LineSim Schematics”

Enabling Lossy Transmission-Line Modeling

You enable lossy transmission-line modeling to take dielectric and metal losses into account
during simulation.

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Setting Up the Oscilloscope

Requirement: The Lossy Lines license is required to enable lossy transmission-line simulation.

To enable lossy transmission-line modeling:

• Enable Lossy Simulation .

Alternative: Setup menu > Enable Lossy Simulation.
Restriction: Surface roughness losses are enabled separately from dielectric losses. See
“Surface Roughness Dialog Box” on page 1871.

See also: “Editing Lossy Transmission-Line Properties” on page 534

Enabling Via Modeling

In BoardSim, you can toggle via modeling to perform "what if" experiments to see the effects of
various via modeling options on simulation results.

Requirement: The Via Models license is required to enable advanced via modeling.

To enable via modeling in BoardSim:

• Enable Via Modeling .

See also: “Select Method of Simulating Vias Dialog Box” on page 1849

In LineSim, you explicitly specify via properties in the schematic either by representing a via
with discrete passive components or with a via schematic symbol, which is available only in the
free-form schematic. You cannot toggle via modeling on and off in LineSim.

Related Topics
“Co-Simulation - Modeling Interactions Between Signal Vias and Transmission Planes” on
page 577

“Simulating Signal Integrity with the Oscilloscope” on page 533

“Preferences Dialog Box - Oscilloscope Tab” on page 1824

Setting Up the Oscilloscope

When the circuit is ready to simulate, use the oscilloscope to set up and run signal-integrity
simulations, and to display waveforms or eye diagrams.

This topic contains the following:

• “Opening the Oscilloscope” on page 538

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Setting Up the Oscilloscope

• “Setting Standard or Eye Diagram Mode” on page 538

• “Setting Up Driver Stimulus” on page 539
• “Setting IC Operating Parameters” on page 551
• “Setting Oscilloscope Probes” on page 554
• “Viewing Waveforms and Eye Diagrams” on page 558
• “Editing Eye Mask Properties” on page 564

Related Topics
“Running Interactive Signal-Integrity Simulations” on page 566

“Enabling SI Simulation Options” on page 536

“Preferences Dialog Box - Advanced Tab” on page 1792

“Simulating Signal Integrity with the Oscilloscope” on page 533

Opening the Oscilloscope

To open the oscilloscope:

• Run Interactive Simulation (SI Oscilloscope) button .

Alternative: Simulate SI menu > Run Interactive Simulation.
The oscilloscope can remain open while you return to the BoardSim/LineSim window and
modify your design in some way, such as assigning different models or adding a Quick
Terminator.

You can resize the Oscilloscope window with standard window controls, such as dragging an
edge of the window with the mouse.

Restriction: Only one oscilloscope may be open at a time.

Setting Standard or Eye Diagram Mode

To set the oscilloscope operation mode, click one of the following options in the Operation area:

• Standard—display waveforms over the full simulation time

• Eye Diagram—display waveforms over the bit interval by cutting up the waveform into
bit-interval lengths and overlaying them. Eye diagrams are a standard way of judging
communications channels.
Requirement: The Advanced Scope license is required to run eye diagram simulation.

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Setting Up the Oscilloscope

Related Topics
“About Eye Diagram Analysis” on page 571

“Running Standard Eye Diagram Analysis” on page 576

“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

“Preferences Dialog Box - Oscilloscope Tab” on page 1824

Setting Up Driver Stimulus

Use the oscilloscope to define one or more sets of driver stimulus (that is, driver waveforms)
and assign them to nets or pins on the board or schematic. You enable the driver IC pin to apply
the assigned stimulus during simulation.

The oscilloscope provides several types of built-in stimulus, including edge, pulse, PRBS
(pseudo-random bit sequence), 8B/10B, and USB 2.0. You can also define your own stimulus.

This topic contains the following:

• “About Global, Per-Net, and Per-Pin Stimulus” on page 539

• “Setting Up Global Stimulus for Standard Oscilloscope Operation” on page 540
• “Setting Up Global Stimulus for Standard-Eye Diagrams” on page 541
• “Setting Up Per-Net and Per-Pin Stimulus” on page 541
• “Assigning Stimulus to Specific Pins or Nets” on page 546
• “About Stimulus Types” on page 548
• “Setting Up Custom Bit Patterns” on page 548

Related Topics
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

“About Eye Diagram Analysis” on page 571

“Setting Up the Oscilloscope” on page 537

About Global, Per-Net, and Per-Pin Stimulus

Global stimulus is where you define a single driver waveform and the oscilloscope
automatically assigns it to all driver pins. In BoardSim, global stimulus is applied to all driver
pins on the selected net and its associated nets. In LineSim, global stimulus is applied to all
driver pins in the free-form or cell-based schematic.

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Per-net/pin stimulus is where you define multiple driver waveforms and manually assign them
to specific driver nets (BoardSim) or pins (LineSim).

Per-net/pin stimulus enables you to simulate timing relationships among nets/pins, such as the
following:

• Crosstalk investigations with different waveforms on aggressor nets, to help examine

the pattern dependency of crosstalk
• Source-synchronous signaling, such as DDRx and similar technologies, where one IC
transmits both the clock and data signals (as opposed to a master system clock, which is
transmitted by a different IC) with typically slightly different timing
Restriction: The oscilloscope supports per-net/pin stimulus for standard and eye diagram
operation modes. FastEye diagrams do not use per-net/pin stimulus.

LineSim saves stimulus assignments to the schematic file. BoardSim saves stimulus
assignments to the .PJH file (as opposed to the .BUD file) to ensure that a net spanning multiple
boards in a MultiBoard project has only one stimulus assignment.

Setting Up Global Stimulus for Standard Oscilloscope Operation

Use the oscilloscope to assign edge or oscillator stimulus to all drivers on the selected net
(BoardSim) or schematic (LineSim).

To set up an edge stimulus:

• In the Stimulus area, click Global, click Edge, and then click Rising edge or Falling
edge.
To see the results of both edges simultaneously, select the Previous Results check box,
set the edge direction one way, simulate, set the edge the opposite way, and then
simulate again.
To set up an oscillator or toggling stimulus:

1. In the Stimulus area, click Global and click Oscillator.

2. Type the frequency, in megahertz, into the MHz box.
3. Type duty cycle, in percentage, into the Duty box. The duty cycle value defines the
percentage of the period that the driver is high.
You can set the default driver waveform type, and default oscillator frequency and duty cycle,
that appears when you first open the oscilloscope. For information, see “Preferences Dialog
Box - Oscilloscope Tab” on page 1824. The oscilloscope saves oscillator frequency and duty
cycle data on a per-pin basis when you set their values interactively.

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Setting Up Global Stimulus for Standard-Eye Diagrams

Use the Stimulus tab on the Configure Eye Diagram dialog box to define stimulus for standard
eye diagrams and for all enabled drivers on the selected net (BoardSim) or schematic
(LineSim).

Requirement: The Advanced Scope license is required to run standard eye diagram analysis.

To set up global stimulus from the oscilloscope:

1. In the Operation area, click Eye Diagram.

2. In the Stimulus area, click Global.
3. In the Eye Diagram area, click Configure. The Configure Eye Diagram dialog box
opens.
4. Click the Stimulus tab.
5. Perform the procedures described in the following topics:
• “Opening, Saving, and Deleting Stimulus Files” on page 542
• “Specifying Stimulus Properties” on page 543

Related Topics
“Opening, Saving, and Deleting Stimulus Files” on page 542

“Running Standard Eye Diagram Analysis” on page 576

“Setting Up Driver Stimulus” on page 539

Setting Up Per-Net and Per-Pin Stimulus

Use the Edit Stimulus dialog box to define a driver waveform that you later assign to specific
nets/pins.

Stimulus is saved in ASCII-formatted .EDS files. You can use stimulus files located on the
computer or network, such as in a stimulus library for a design project.

This topic contains the following:

• “Opening the Edit Stimulus Dialog Box” on page 542

• “Opening, Saving, and Deleting Stimulus Files” on page 542
• “Specifying Stimulus Properties” on page 543

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Related Topics
“Assigning Stimulus to Specific Pins or Nets” on page 546

“Setting Up Driver Stimulus” on page 539

Opening the Edit Stimulus Dialog Box

To open the Edit Stimulus dialog box, do any of the following:

• Setup menu > Stimulus > Edit Stimulus.

In the free-form schematic editor, select an IC first.
• Assign Stimulus dialog box > Edit Stimulus button.
See also: “Assigning Stimulus to Specific Pins or Nets” on page 546
• BoardSim > Right-click IC pin > Edit Stimulus.
• BoardSim > Right-click trace segment > Edit Stimulus.
• LineSim (free-form schematic editor) > Right-click IC symbol > Edit Stimulus.

Opening, Saving, and Deleting Stimulus Files

To open an existing stimulus file, do either of the following:

• Click Open , browse to the stimulus file, and then click Open.
If you open a stimulus file located in a non-default folder, that folder is automatically
added to the Stimulus File Path(s) area of the Set Directories dialog box.
• In the Stimulus Name list, select the file from the list.
The list contains all the .EDS files contained in the folders specified in the Stimulus File
Path(s) area of the Set Directories dialog box. .EDS files contain wave shape and timing
information.
See also: “Set Directories Dialog Box” on page 1854
To save a new stimulus file or save an existing stimulus file to the same name and location:

• Click Save .
To save an existing stimulus file to a different name or location:

• Click Save As .
Using meaningful stimulus names, such as PRBS_128 or 250MHz_clock, can help you
to recognize the stimulus contents when assigning stimulus to specific pins or nets.
To permanently delete a stimulus file from the computer or network location:

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1. If needed, select the file from the Stimulus Name list.

2. Click Delete .

Specifying Stimulus Properties

1. In the Bit Pattern area, select the stimulus type. The set of available options depends on
the stimulus type you select. Edit the following properties as needed:
• In the Bit Order list, select the number of bits in the sequence. The number of bits is
2**<bit_order> - 1.
• In the Initial State list, select the initial state, which precedes bit zero.
• In the Direction list, select the edge direction.
See also: “About Stimulus Types” on page 548
2. If you selected <Custom> in step 1, load an existing bit stimulus file or create a new bit
pattern.
See also: “Setting Up Custom Bit Patterns” on page 548
3. Edit options in the Stimulus area. The set of available options depends on the stimulus
type you select in step 1. Edit the following properties as needed:
• Bit interval—Length of the unit interval, in ns. Editing this value also updates the Bit
Rate value.
When choosing between the Bit Interval and Bit Rate property, use the one that
provides the best accuracy. For example, to test the channel at 333 Mb/s, you can
specify a bit rate of 0.333 Gb/s instead of a bit interval of 3.00300300300 ns.
• Bit Rate—The number of bits transmitted through the channel, in gigabits per
second. Editing this value also updates the Bit Interval value.
• Duty cycle—Time, in percentage of the period, the stimulus is high
• Frequency—Frequency in megahertz. Editing this value also updates the Period
value.
• Period—Period in ns. Editing this value also updates the Frequency value.
• Pulse length—Length, in ns, of the pulse
• Sequence reps—Number of times to repeat the stimulus
4. Optionally, in the Jitter area, enable one or more of the following types of jitter:
• Gaussian—A normal distribution with no sigma limit. A histogram consisting of a
large number of Gaussian-distributed jitter values resembles a bell curve. See
“Gaussian Jitter” on page 1379.

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• Uniform—An even distribution. A histogram consisting of a large number of

uniform-distributed jitter values resembles a rectangle. See “Uniform Jitter” on
page 1383.
Uniform produces a worst-case distribution more quickly than Gaussian.
• Sine— See “Sinusoidal Deterministic Jitter” on page 1382.
If you are not sure what jitter distribution to use, enable only Gaussian and obtain the
combined driver and receiver jitter values (in sigma) from IC datasheets, design kit
documentation, and so on. See “Jitter Applications” on page 1386. You may have your
own reasoning on how to combine driver and receiver jitter values, by treating them
statistically independent or not.
If you enable multiple jitter distributions, the total jitter probability distribution function
(PDF) is a convolution of the individual jitter distributions.
Although eye diagrams are based on the channel response measured at the receiver input
pin, the goal is to find the eye diagram at the receiver decision point (which is beyond its
amplifiers, DFE, filters, and CDR circuitry). Because drivers and receivers are active
devices, they both contribute random jitter due to thermal and transistor device noise,
PLL (that is, CDR circuitry) behavior, and so on. This is why you should specify a jitter
distribution representing both driver and receiver jitter.
5. For each jitter type you enabled in step 4 (if any), select it from the Jitter Type list and
edit its properties. The set of available options depends on the jitter type you select. Edit
the following properties as needed.
• Gaussian jitter:
o Specify the jitter and units.
Specify the width (or magnitude) of the jitter at one standard deviation (that is,
one sigma). Specify this value as an absolute (for example, in nanoseconds) or as
a relative value (for example, a fraction of the unit interval set for the
simulation). See “Units for Gaussian and Uniform Jitter” on page 1386.
Increasing the value of sigma increases (on average) the deviation of the timing
of waveform transitions away from the ideal switching time.
You specify the width of one sigma and standard-eye diagrams derives the width
of other sigmas from it. The sigmas are equally spaced from one another.
If you want the maximum jitter value (on average) to exceed three sigma, the bit
sequence must contain at least 370 bits. This value is based on reference
information about the Gaussian distribution and its relationship to the confidence
interval. See Table 31-29 on page 1381.
o Advanced options—Type the median frequency and select the units.

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Jitter frequency is the rate at which the jitter offset varies. Median frequency is
the frequency that divides the jitter spread into two parts of equal area.
o To make the analysis results repeatable, select the For random jitter, generate
the same random number sequence in each simulation check box.
Enable this option if you make termination or topology changes and want to use
exactly the same jitter to compare results, or if you want to correlate your results
with another person.
• Uniform jitter:
o Specify the jitter magnitude and units. The magnitude represents the width of the
distribution. See Figure 31-49 on page 1384 and Figure 31-50 on page 1384. See
“Units for Gaussian and Uniform Jitter” on page 1386.
o Advanced options—Type the mean and units. The mean represents the center of
the possible jitter value range. A non-zero mean value offsets the center of the
distribution away from the ideal switching time.
o To make the analysis results repeatable, select the For random jitter, generate
the same random number sequence in each simulation check box.
Enable this option if you make termination or topology changes and want to use
exactly the same jitter to compare results, or if you want to correlate your results
with another person.
• Sine jitter:
o Specify the jitter magnitude and units.
o Advanced setting—Type the frequency value and select the units.
Jitter frequency is the rate at which the jitter offset varies.
o Advanced options—Type the initial phase of the sinusoidal jitter in degrees.
You can usually set this value to zero degrees. You might specify a non-zero
initial phase value for “short” simulations that are not long enough to contain
many periods of slowly-changing jitter. Sinusoidal jitter usually shifts slowly
relative to the bit rate.
See Figure 31-46 on page 1382 and Figure 31-47 on page 1383.
Note that sinusoidal jitter is always repeatable.

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Note
Do not specify the jitter produced by the following effects, unless you have a specific
reason to do so:

PCB layout effects—Such as impedance mismatches and signal dispersion

Data-dependent effects—Such as ISI, duty-cycle distortion, pseudo-random bit sequence

periodicity

6. Click OK.

Related Topics
“Assigning Stimulus to Specific Pins or Nets” on page 546

“Setting Up Driver Stimulus” on page 539

Assigning Stimulus to Specific Pins or Nets

Use the Assign Stimulus dialog box to assign stimulus to specific pins or nets in the design. In
BoardSim you can assign stimulus to individual pins or to a net (and all its pins). In LineSim
you can assign stimulus to individual pins.

You can sort the spreadsheet by clicking a column header.

To assign stimulus to specific nets or pins:

1. To open the Assign Stimulus dialog box, do any of the following:

• Oscilloscope > Per-Net/Pin > Assign button.
• Setup menu > Stimulus.
• BoardSim > Select net > Right-click IC pin or trace segment on selected net >
Assign Stimulus.
If you right-click an IC pin or trace segment for an unselected net, the Assign
Stimulus dialog box displays information for the selected net.
• LineSim (free-form schematic editor) > Right-click IC symbol > Assign Stimulus.
2. In BoardSim, in the Assign Stimulus By area, click one of the following:
• Net—Display all the nets in the board.
• Pin—Display all the pins on the selected net. This option is unavailable until you
select a net. If you have selected a net, this area displays pins only for that net. If you
right-clicked over an unselected net to open this dialog box, the pins for the
unselected net do not appear.

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If a MultiBoard project is loaded, the name of the board is added to the net or component
name. For example, U1_B02.14, where _B02 identifies the board.
3. To display the spreadsheet rows for specific nets or pins, type the filter string into the
Pin Filter or Net Filter box and click Apply.
Use the asterisk * wildcard to match any number of characters. Use the question mark ?
wildcard to match any one character. To display all spreadsheet rows, type asterisk * and
click Apply.
For example, to display pin names for U7, click Pin, type u7*, and then click Apply.
4. To create or edit custom stimulus, click Edit Stimulus.
See also: “Setting Up Per-Net and Per-Pin Stimulus” on page 541
5. Click in the Stimulus cell for a pin and select the name of the stimulus.
<default> represents a rising edge. You cannot edit the default stimulus.
The Stimulus cell displays stimulus names present in custom stimulus files located in the
HYP file folder or other stimulus file folders you specify.
See also: “Set Directories Dialog Box” on page 1854
6. To offset the stimulus from zero ns, click in the Initial Delay cell and type the delay in
ns.
If you type 0 ns, the Initial Delay cell automatically replaces it with a dash -. Dashes
make it easier to see non-zero delay values.
7. Click OK.

Related Topics
“Setting Up Driver Stimulus” on page 539

“Configuring the HyperLynx Environment”

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About Stimulus Types

Table 11-1 describes the types of stimulus supported by the oscilloscope. The oscilloscope
options you enable, such as global stimulus and standard eye diagrams, determine stimulus type
availability.

Table 11-1. Driver Stimulus Types

Type Oscilloscope Description
Operation
Availability
Oscillator Standard Repetitive clock waveform
Toggling Eye Diagram Helps to study the standing-wave effects of repetitive
stimulus.
Edge Standard Single rising or falling edge

Helps to isolate transmission-line effects because you can

study how a transition settles out, without the possibly
confusing effects of additional transitions.
Pulse Standard Single clock cycle
PRBS (pseudo Standard Pseudorandom binary sequence
random)
Eye Diagram Helps to study the effects of transmitting long bit streams.
8B/10B Standard Sequence of randomly-generated 8B/10B characters that
obey the signaling protocol
Eye Diagram
Helps to study the effects of transmitting long bit streams.
USB 2.0 Standard Sequence of USB 2.0 characters
compliance
Eye Diagram Helps to study the effects of transmitting long bit streams.
<Custom> Standard Bit sequence that you define or load from a bit stimulus
(.BIT) file
Eye Diagram

Related Topics
“Running Standard Eye Diagram Analysis” on page 576

“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

Setting Up Custom Bit Patterns

You can create a custom bit pattern and save it to an ASCII file so it can be used for future
simulation sessions or to share it with others.

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This topic contains the following:

• “Specifying Bit Patterns with a Text Editor” on page 549

• “Specifying Bit Patterns Numerically with the Bit-Pattern Editor” on page 549
• “Specifying Bit Patterns Graphically with the Bit-Pattern Editor” on page 550

Specifying Bit Patterns with a Text Editor

You can type the 1/0 bit pattern values into an ASCII text editor.

To create the bit pattern with a text editor:

1. Open the text editor.

2. Type in the bit sequence using 1 and 0 values.
You can separate bit values with any combination of spaces, commas, semicolons, and
carriage returns (new lines). However if you save the bit pattern from the Configure Eye
diagram dialog box, the separator characters are removed.
3. Save the file in ASCII format with the .bit file name extension.
Requirement: Save the file in the <design> folder. See “Set Directories Dialog Box” on
page 1854.
See also: “HyperLynx File Editor” on page 1666

Specifying Bit Patterns Numerically with the Bit-Pattern Editor

You can type the 1/0 bit pattern values in the Stimulus tab on the Configure Eye or Edit
Stimulus diagram dialog boxes.

To specify bit patterns with the bit-pattern editor:

1. Do any of the following:

• To open the Edit Stimulus dialog box, do any of the following:
o Setup menu > Stimulus.
o Assign Stimulus dialog box > Edit Stimulus button.
See also: “Select Directories for Stimulus Files Dialog Box” on page 1847
• To open the Configure Eye Diagram dialog box, do the following in the
oscilloscope:
i. In the Operation area, click Eye Diagram.
ii. In the Stimulus area, click Global.

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iii. In the Eye Diagram area, click Configure. The Configure Eye Diagram dialog
box opens.
iv. Click the Stimulus tab.
2. In the Sequence list, select <Custom>. The background color for the graphical bit
pattern display turns white to indicate the edit mode.
3. To edit an existing bit pattern, click Load, type or browse to the bit pattern file, and then
click Open. The bit pattern appears in the graphical editor.
4. In the Bit pattern area, click in the box just above the Sequence length label, and then
type 0 and 1 as needed.
The following keyboard shortcuts and keys can help you edit a bit pattern or help you
navigate within a bit pattern:
• To delete the current bit, press Delete. To delete the previous bit, press Backspace.
• To select multiple bits do any of the following: Drag the mouse, press Shift+End,
press Shift+Home, press Shift+<left arrow>, press Shift+<right arrow>.
• To navigate within the bit pattern do any of the following: Use the scroll bar, press
Home, press End, press <left arrow>, press <right arrow>.
5. To save the bit pattern, do the following:
a. Click Save.
b. Type or select the file name, and then click Save. The bit pattern is saved to an
ASCII file with a .bit file name extension.
When you save the bit pattern to a file, only the bit values are written. If you had
previously loaded into the Bit-Pattern Editor a bit pattern file with bit value
separators, such as spaces or carriage returns, the separator characters are not saved.

Specifying Bit Patterns Graphically with the Bit-Pattern Editor

You can use the mouse to graphically draw the bit pattern in the Stimulus tab of the Configure
Eye diagram dialog box.

To specify the bit pattern with the graphical editor:

1. In the Operation area of the Digital Oscilloscope dialog box, click Eye Diagram.
2. In the Eye diagram area, click Configure. The Configure Eye Diagram dialog box
opens.
3. Click the Stimulus tab.

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4. In the Configure Eye Diagram dialog box, select <Custom> from the Sequence list. The
background color for the graphical bit pattern display turns white to indicate the edit
mode.
5. To edit an existing bit pattern, click Load, type or browse to the bit pattern file, and then
click Open. The bit pattern appears in the graphical editor.
6. If this is a new bit pattern, move the pointer to the red square representing the logic state
you want for bit one (numbering starts at zero) .
If this is an existing bit pattern, move the pointer to the bit boundary following the last
bit .
7. To add a data bit, do one of the following:
• Move the pointer exactly over the bit boundary following the last bit so the pointer
shape resembles a hand and waveform (see below), drag (click and hold the mouse
button) the pointer up or down to set the logic state, and then drag the pointer to the
right to add a bit.
• Move the pointer to the right of the bit boundary following the last bit so the pointer
shape resembles an arrow and waveform (see below), move the pointer up or down
to set the logic state, move the pointer to the right to define a potential bit, and then
click to add the bit.
To remove data bits, move the pointer exactly over the bit boundary following the last
bit so the pointer shape resembles a hand and waveform, and then drag the pointer to the
left.
8. To use the bit pattern in a future oscilloscope session, do the following:
a. Click Save.
b. Type or select the file name, and then click Save. The bit pattern is saved to an
ASCII file with a .bit file name extension.
When you save the bit pattern to a file, only the bit values are written. If you had
previously loaded into the Bit-Pattern Editor a bit pattern file with bit value separators,
such as spaces or carriage returns, the separator characters are not saved.

Setting IC Operating Parameters

You can control from the oscilloscope whether the IC models in a simulation run with best-case,
typical, or worst-case operating parameters.

Restrictions:

• SPICE models use power-supply net voltage settings and do not use the oscilloscope IC
operating parameter settings.

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• Passive components inside EBD models, including IBIS models with [R Series]
keywords, do not use the oscilloscope IC operating parameter settings.
See also: “Editing Power-Supply Nets” (BoardSim), “Editing Power-Supply Net Properties”
(LineSim)

This topic contains the following:

• “What IC Operating Settings Mean” on page 552

• “Setting the Operating Conditions” on page 553
• “Does Not Affect IBIS Models With Only Typical Data” on page 553

What IC Operating Settings Mean

The IC operating settings are actually combinations of the min and max data in an IBIS model,
or scaled versions of a .MOD model (which itself contains only typical data). The combinations
are named Slow-Weak, Typical, and Fast-Strong, to be as descriptive as possible.

Table 11-2 defines the combinations for IBIS models.

Table 11-2. IC Operating Settings - IBIS Models

Parameter IBIS Keywords Fast-Strong Slow-Weak
driver current [Model] > [Pullup] and [Pulldown] max min
slew rate [Model] > [Rising Waveform] and max min
[Falling Waveform] or [Ramp]
clamp-diode current [Model] > [GND Clamp] and [Power max min
Clamp]
component capacitance [Model] > C_comp min max
package inductance [Component] > [Package] min max
package capacitance [Component] > [Package] min max
package resistance [Component] > [Package] min max

In addition, you can set IBIS model pull-up and power clamp voltage to vary with the IC
operating setting. For the oscilloscope, enable the When assigning a model to an IC pin, use a
power-supply net connected to the IC option in the Preferences Dialog Box - General Tab. For
batch SI simulation, enable the When simulating, vary voltage reference values with IC corners
option (see “Editing Driver and Receiver Options for Signal-Integrity Analysis”).

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Table 11-3 shows for IBIS models how pullup and power clamp voltages vary with IC
operating settings.

Table 11-3. Pullup and Power Clamp Voltages - IBIS Models

Parameter IBIS Keywords Fast-Strong Slow-Weak
pull-up voltage [Model] > [Voltage Range] or [Pullup max min
Reference]
power clamp voltage [Model] > [Voltage Range] or max min
[POWER Clamp Reference]

For .MOD models, all of the models in a simulation are scaled up or down from their typical
values by globally defined scaling factors to give Slow-Weak or Fast-Strong operation. (See
"Scaling .MOD Models for Best/Worst-Case Operation" below for details on the scaling.) Not
all parameters in a .MOD model are scaled; Table 11-4 shows for .MOD models how the
operating combinations are created.

Table 11-4. IC Operating Settings - .MOD Models

Parameter Fast-Strong Slow-Weak
driver slew time scaled down scaled up
driver output scaled down scaled up
impedance
driver/receiver I/O scaled down scaled up
capacitance

Setting the Operating Conditions

To set the IC operating parameters:

• In the IC modeling area, click the appropriate IC operating parameter.

You can display simulation results for multiple IC operating parameters.

See also: “Re-Simulating - Comparing Results” on page 594

Does Not Affect IBIS Models With Only Typical Data

Changing IC operating parameters only affects the IBIS IC models in your circuit that actually
contain min/max data. If you change the IC operating parameters but see no change in your
simulation waveforms, it is probably because the IBIS model(s) you are using do not have
min/max data. The IBIS format allows for min/typ/max data, but only requires typical.

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Setting Oscilloscope Probes

Use the probe spreadsheet in the oscilloscope to set up probes. Oscilloscope probes work like
real oscilloscope hardware probes: they enable you to see voltage waveforms (all simulators) or
current waveforms (native HyperLynx simulator only) at points in the circuit during simulation.

The oscilloscope automatically attaches probes to all pins in the circuit. In BoardSim, the
oscilloscope automatically attaches probes to all pins on the selected net and any associated
nets. In LineSim, the oscilloscope automatically attaches probes to all pins in the schematic. In
BoardSim, probe attachment takes place when you select the net. For differential pin pairs, the
oscilloscope attaches a differential probe in addition to the single-ended probe attached to the
individual pins, resulting in a total of three probes for the two differential pins.

In the schematic or board viewer, probes look like arrows pointing to the pins to which they
attach. The color of the probe indicates the color of the corresponding waveform in the
oscilloscope.

This topic contains the following:

• “Enabling and Disabling Probes” on page 554

• “About the Probe Spreadsheet” on page 555
• “Locating Probes at the Die or Pin” on page 555
• “Editing Waveform Colors” on page 556
• “Manually Attaching Differential Probes” on page 556
• “Swapping Differential Probe Polarity” on page 557
• “Probing SPICE Ports Not Connected to the Net” on page 557
• “Probing Where There is No Component - Signal Integrity” on page 557 (LineSim only)
• “Dead Probes in BoardSim” on page 558

Related Topics
“Identifying Design Pins for Waveforms” on page 559

“About Pin Names in the Cell-Based Schematic Editor”

Enabling and Disabling Probes

The effect of enabling and disabling probes depends on whether you enable standard or eye
diagram oscilloscope operation.

For standard oscilloscope operation, you enable/disable probes to show/hide waveforms. All
probes are simulated, whether or not they are enabled prior to simulation.

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For eye diagram oscilloscope operation, you enable/disable probes prior to simulation to choose
which probes to simulate (to conserve computer memory) and enable/disable probes after
simulation to show/hide waveforms. After eye diagram simulation, you cannot use grayed probe
check boxes to show/hide waveforms (because simulation data for those probes do not exist),
but you can select them to enable probes for the next simulation.

To enable a probe:

• In the probe spreadsheet, select the check box next to the probe name.
To enable or disable all probes:

• To the lower left of the probe spreadsheet, click the small right arrow button , and
then click Enable all probes or Disable all probes.

About the Probe Spreadsheet

Use the probe spreadsheet to enable/disable oscilloscope probes, edit the color of waveforms,
manually create differential probes, and so on.

If the reference designator or pin number is truncated, move the pointer over it to display the
name in a ToolTip.

If the probe spreadsheet is too small to use comfortably, click the plus sign + button to the left of
the standard spreadsheet to open a larger spreadsheet.

To expand spreadsheet rows, click the plus sign + or click in the cell and press <right arrow>.

For differential pin pairs, the spreadsheet displays the non-inverted probe to the left of the
inverted probe.

See also: “Editing Waveform Colors” on page 556, “Manually Attaching Differential Probes”
on page 556

Locating Probes at the Die or Pin

For components with IBIS models, you can specify whether to locate oscilloscope probes at the
die or pin.

For components with other model types, oscilloscope probes are located at the following
positions:

• MOD/PML—pin
• SPICE/S-parameter (Touchstone)—defined by external ports for model
To locate probes at the die or pin:

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• In the Show area, select the probe location from the Located list.
If you select "Per each IC model's setting," and the model contains the Timing_location
keyword, the probe is assigned to the model-specified location. If the model does not contain
the Timing_location keyword, the probe is assigned to the pin location.

The probe location in the oscilloscope is linked to wizard pages for FastEye Channel Analysis
and IBIS-AMI Channel Analysis. If you change the value in the oscilloscope, it changes on a
page in those wizards too.

Editing Waveform Colors

You can change the color of waveforms in the oscilloscope if you plan to print the waveforms
and want to use a color that is easy to see on white paper, or just prefer a different color.

To change the color of waveforms:

1. In the probe spreadsheet, double-click the color cell for the waveform.
2. Choose a color and click OK.
If the probe spreadsheet is too small to use comfortably, click the plus sign + button to
the left of the standard spreadsheet to open a larger spreadsheet.
To expand spreadsheet rows, click the plus sign +.

Manually Attaching Differential Probes

Differential probes display the voltage difference between two pins. You will probably use
differential probes if you use differential-signal technology, such as PCI Express, LVDS, and so
on.

If the oscilloscope does not automatically recognize differential pins and attach differential
probes to them, such as for SPICE models, you can attach them manually.

Restriction: You cannot manually attach differential probes to unconnected (NC) SPICE ports.

To manually attach differential probes:

1. In the bottom row of the probe spreadsheet, double-click <Insert diff probe>.
2. Select pins in the Positive Pin (+) and Negative Pin (-) lists, and then click OK.
Result: The new differential probe is added to the spreadsheet, near the bottom.
To delete a manually-attached differential probe, click its Pins cell, press Delete, and
then click Yes.

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Swapping Differential Probe Polarity

If the waveform produced by a differential probe has reversed polarity, meaning the inverted
pin is located to the left of the non-inverted pin in the probe spreadsheet, you can click one of
the pin names in the differential pair to swap the location of the differential probes.

Example: If the probe spreadsheet currently displays 3/2 to the right of the check box, where 3
is the inverted pin, click either 3 or 2 to swap the probes and display 2/3.

To swap differential probe polarity:

• Point to either pin number (to the right of the check box) in the differential pair, so that
pointer shape changes to a U-shaped arrow, and then click.

Probing SPICE Ports Not Connected to the Net

For SPICE models only, the oscilloscope attaches a single-ended probe to all the unconnected
(NC) ports of a SPICE model, even if they are not connected to the net or schematic. This
capability enables you to display waveforms for key signals that would otherwise be hidden
from view, such as the following:

• On a SPICE SERDES (serializer/deserializer) receiver model with a special port to

access the post-equalized signal, representing the "real" waveform seen by the receiver
• On a SPICE model that combines the silicon and package behaviors, but you want to
probe between the silicon and package. You can modify the SPICE model so that the
node(s) between silicon and package are brought out to external port(s).
Restriction: You cannot manually attach differential probes to unconnected (NC) SPICE ports.

Probing Where There is No Component - Signal Integrity

For LineSim schematics, you can probe a location without a component, such as between two
transmission lines, by adding an IC to the location but not assigning a model to it. An IC with no
model has no effect on the circuit.

Restriction: Only LineSim provides this probing capability. In BoardSim, probes can attach
only to component pins, not to trace segments, pads, or vias.

An alternative method is to add a 10K pull-up or pull-down resistor to the net. Such a large
resistor will have little or no effect on your circuit because it is a very small load, but it provides
a component pin at which you can probe. Its package parasitics will be present, however, and
for very-high-speed signals, you may want to reduce those to minimum values before
simulating.

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Dead Probes in BoardSim

If a probe is "dead" (displays no voltage when it should) in BoardSim, it means that the
component pin which is being probed is not validly connected to the routing metal which is
delivering the voltage. This can occur, for example, if the board file contains insufficient or bad
pad information. Another symptom of this problem is getting the error message "No driver on
net" (or similar) when you try to simulate, even though a driver has been enabled.

Related Topics
“Setting Up the Oscilloscope” on page 537

Viewing Waveforms and Eye Diagrams

The oscilloscope provides many controls to help you examine waveforms and eye diagrams by
zooming, changing voltage or time scales, displaying IC receiver threshold voltages, and so on.

While most of the controls do not affect how simulation runs, the Horizontal Scale and
Horizontal Delay controls do.

See also: “How Horizontal Scale and Delay Settings Affect Simulation” on page 561

This topic contains the following:

• “Identifying Design Pins for Waveforms” on page 559

• “Showing Voltage and Current Waveforms” on page 559
• “Zooming and Fitting to Window” on page 559
• “Showing IC Threshold Voltages” on page 560
• “Setting the Vertical Scale” on page 560
• “Setting the Vertical Position - Ground Marker Offset” on page 560
• “Setting the Horizontal Delay” on page 560
• “Setting the Horizontal Scale” on page 561
• “How Horizontal Scale and Delay Settings Affect Simulation” on page 561
• “Scrolling Vertically” on page 562
• “Scrolling Horizontally” on page 562
• “Overview Pane” on page 562
• “Settings Readout” on page 563

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Identifying Design Pins for Waveforms

To identify design pins for waveforms in the oscilloscope, do any of the following:

• Touch the oscilloscope waveform with the mouse pointer to display the design pin name
in a pop-up box.
• Match the color of the oscilloscope waveform to the color of the probe attached to the
design pin. See the following locations to identify the color of a probe for a design pin:
o The probe spreadsheet in the oscilloscope.
o The schematic or board viewer.

Showing Voltage and Current Waveforms

You can display voltage waveforms in the oscilloscope. If you use the native HyperLynx
simulator, you can also display current waveforms in the oscilloscope. Current waveforms can
help you investigate electromagnetic compatibility (EMC) behavior.

During eye diagram operation, only voltage data are stored. During standard operation, both
voltage and current data are stored so you can view both voltage and current data for a given
simulation.

To show voltage or current waveforms, in the Visibility area, click one of the following:

• Voltage—Plot voltage over time

• Current—Plot current over time
Restriction: The oscilloscope does not display current for nets with a series MOSFET
component.

Zooming and Fitting to Window

To examine an interesting region in a waveform more closely, you can zoom in on it. To display
the entire waveform once more, you can fit the waveforms to the window.

To zoom:

1. In the Zoom area, click Zoom .

2. Position the mouse pointer over one corner of the zoom box you want to create, drag to
define the other corner of the zoom box, and then release the mouse button.
Result: The contents of the zoom box fill the display area.
To fit the waveforms to the window:

• In the Zoom area, click Fit to Window .

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Showing IC Threshold Voltages

You can display in the oscilloscope lines representing Vinh, Vinl, or Vmeasure IC measurement
threshold voltages, as provided by IC models. The main and overview panes both display IC
threshold voltages.

Exception: SPICE models do not contain IC measurement threshold information.

To show IC measurement thresholds, in the Thresholds For list, do any of the following:

• Select a reference designator and pin.

• Select All IC pins.
To hide IC measurement thresholds:

• In the Thresholds For list, select <no pin selected>.

Setting the Vertical Scale

To set the vertical voltage scale, do any of the following:

• Type in the Vertical Scale box a value in volts / division.

• Click an arrow beside the Vertical Scale box.

Setting the Vertical Position - Ground Marker Offset

Use the vertical position option to shift the waveforms, and the 0.0 V ground position marker, in
the main screen up or down relative to the grid. By contrast, the vertical scroll bar moves the
grids, waveforms, and green ground marker up and down together.

The vertical position controls create a voltage offset by adding or subtracting voltage to or from
the simulation data. When changing the vertical position, the grids remain stationary while the
waveforms and ground marker move up and down.

To set the vertical position, do any of the following:

• Type in the Vertical Position box a value in volts.

• Click an arrow beside the Vertical Position box.
Restriction: The allowed vertical position range is plus/minus five divisions with a precision of
1/10 division.

Setting the Horizontal Delay

The Horizontal Delay option allows you to align a specific simulation time to the left edge of
the main oscilloscope screen when simulation completes. For example, if the horizontal delay

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Setting Up the Oscilloscope

was set to 25ns when you clicked the Start Simulation (or Start Sweeps) button, the waveforms
corresponding to the simulation time of 25ns are aligned to the left edge of the main
oscilloscope screen when simulation completes.

For standard oscilloscope operation, the Horizontal Delay control only affects the waveform
display for the next simulation; it has no effect on the latest waveform display.

For eye diagrams, you can use the Horizontal Delay control to center the eye in the oscilloscope.

To set the horizontal delay, do any of the following:

• Type in the Horizontal Delay box a value in nanoseconds.

• Click an arrow beside the Horizontal Delay box.
The overview pane displays the entire simulation, including the events prior to the horizontal
delay setting.

The allowed horizontal delay range is 0ns to 100 ns, with a precision of 1 ps.

See also: “How Horizontal Scale and Delay Settings Affect Simulation” on page 561

Setting the Horizontal Scale

To set the horizontal time scale, do any of the following:

• Type in the Horizontal Scale box a value in nanoseconds / division.

• Click an arrow beside the Horizontal Scale box.
See also: “How Horizontal Scale and Delay Settings Affect Simulation” on page 561

How Horizontal Scale and Delay Settings Affect Simulation

Simulation End-Stop Time

The horizontal scale and horizontal delay settings together determine the simulation end/stop
time. The oscilloscope instructs the simulator to generate data for ten horizontal time divisions
plus the horizontal delay that you specify.

For example, when the horizontal scale is set to 1ns/div and the horizontal delay is set to 0ns,
the simulator will generate data for 10ns of simulation time (e.g. 1ns/div times 10 divisions,
plus horizontal delay of 0ns, is 10ns). If you increase the horizontal scale to 5ns/div and increase
the horizontal delay to 3ns, the simulator will generate data for 53ns of simulation time.

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Memory Consumption for Simulation

When you click the Start Simulation or Start Sweeps button, the oscilloscope calculates the
number of data points the simulator will generate based partly on your horizontal scale and
horizontal delay settings. If your computer has insufficient memory to record the simulation
results, the oscilloscope will issue a warning and not start the simulation.

Simulation Timestep
The horizontal scale setting typically does not affect the simulation timestep because it is just
one of several factors used by BoardSim/LineSim to calculate the simulation timestep.
However, a very small horizontal scale value can decrease the simulation timestep.

The horizontal delay setting has no effect on the simulation timestep.

Scrolling Vertically
Use the vertical scroll bar to move the grids, waveforms, and ground line up and down together.
By contrast, the vertical position control shifts the waveforms in the main screen up or down
relative to the grid.

The vertical scroll bar is useful when you have zoomed in on the vertical scale and some portion
of the waveforms falls outside the main screen.

To scroll vertically:

• Drag the scroll bar located to the right of the main oscilloscope screen up or down.

Scrolling Horizontally
Use the horizontal scroll bar to move the grids and waveforms left and right together. The
horizontal scroll bar is useful when you have zoomed in on the horizontal scale and some
portion of the waveforms falls outside the main screen.

To scroll horizontally:

• Drag the scroll bar located below the main oscilloscope screen left or right.

Overview Pane
The overview pane may help you to visually relate the waveforms displayed in the main screen
to the entire simulation. The overview pane always shows the waveforms for the entire
simulation. The portion of the overall simulation displayed in the main screen is marked by a
green hatched pattern in the overview pane.

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For example, if you were to lose your place in the simulation while zooming in on a specific
portion of a waveform, the overview pane can help you navigate visually to the desired portion
of the waveform.

The overview pane is positioned below the main screen and has no grids or position controls.
The mouse cursor and measurement crosshairs marker positions in the overview pane are
reported in the Cursors area near the bottom of the oscilloscope dialog box. As a convenience,
you can show or hide the overview pane.

To show or hide the overview pane:

• In the Show area, select or clear Overview pane.

The overview pane is included when you document your simulation results using the Print or
Copy to Clip buttons in the oscilloscope. If you do not want to include the overview pane, clear
the Overview Pane check box. However, the overview pane is not included when you press the
Save As CSV button, even when the Overview Pane check box is selected.

Changing the Relative Size of the Main and Overview Panes

As a convenience, you may change the relative size of the main and overview panes using the
window splitter bar control that separates them. The overview pane cannot be made larger than
the main screen.

To change the relative size of the main and overview panes:

• Drag the splitter bar just above the overview pane up or down with the mouse. The
pointer shape will change to a double-arrow when it is over the splitter bar.

Settings Readout
For convenience, the horizontal scale, vertical scale, horizontal delay, and vertical offset values
are summarized and displayed on the main oscilloscope screen, in white text. You can disable
the settings readout to reduce clutter on the main oscilloscope screen.

To show or hide the oscilloscope settings readout:

• In the Show area, select or clear the Readout text check box.

Related Topics
“Setting Oscilloscope Probes” on page 554

“Measuring Waveforms and Eye Diagrams” on page 578

“Preferences Dialog Box - Oscilloscope Tab” on page 1824

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Setting Up the Oscilloscope

Editing Eye Mask Properties

Use the Eye Mask tab on the Configure Eye Diagram dialog box to edit eye mask properties for
eye diagram analysis. You can load existing eye masks from a library or save new eye masks
into a library.

To edit eye mask properties:

1. Do one of the following:

• If you are using the Digital Oscilloscope, do the following:
i. In the Operation area, click Eye Diagram.
ii. In the Eye diagram area, click Eye Mask or Configure (whichever is displayed).
The Configure Eye Diagram dialog box opens.
iii. Click the Eye Mask tab.
• If you are using the HyperLynx IBIS-AMI Sweeps Viewer, select Edit > Configure
Eye Mask.
• If you are using the FastEye Channel Analyzer, click Configure.
2. To load an existing eye mask, select it from the Mask Name list.
This list displays eye masks stored in the User.mask and BSW.mask files located in the
HyperLynx installation directory.
See also: “Description of Eye Masks in Default Mask Library” on page 565
3. Type voltage and time values into the eye mask boxes.
4. To scale the eye mask values in order to verify timing or voltage margins, type the
percentage values into the Time or Volt boxes.
The eye mask boxes are available only when the scaling values are 100%.
5. To change the eye mask position on the oscilloscope, type the time (ns) and voltage (V)
values in the Offset area.
These values also change if you drag the eye mask to a new position on the oscilloscope
screen.
6. If you are running IBIS-AMI sweep simulations, optionally edit the value in the BER
Threshold box. This value determines the pass/fail threshold for the Pass/fail eye mask
spreadsheet column in the HyperLynx SI Eye Density Viewer. You can enter values in
decimal or scientific notation, such as 1e-12.
7. To save the eye mask, click Save , type its name in the Save Mask As dialog box,
and then click OK.

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The eye mask library is saved in a file named User.mask located in the HyperLynx
installation directory.
To remove a mask from the eye mask library saved in the User.mask file, select the eye
mask from the Mask Name list, and then click Delete . You cannot remove eye
masks saved in the BSW.mask file.

Related Topics
“Running Standard Eye Diagram Analysis” on page 576

“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

Description of Eye Masks in Default Mask Library

Table 11-5 describes the eye mask families shipped with HyperLynx and stored in BSW.mask.

Table 11-5. Description of Eye Masks in BSW.mask File

Mask Family Means
FC Comply with Fibre Channel signaling requirements.

Specification is "Fibre Channel, Physical Interfaces, (FC-PI), Rev 13,

December 9, 2001."

Beta, delta, gamma refer to interoperability points in a TxRx connection,

that is, the measurement locations for transmit/receive signal path.
PCIE Comply with PCI Express signaling requirements.

Specification is "PCI EXPRESS BASE SPECIFICATION, REV. 1.0a."

SAS Comply with Serial Attached SCSI signaling requirements.

Specification is "Serial Attached SCSI Standard, T10/1562-D Revision 5."

SATA Comply with Serial ATA signaling requirements.

Specification is "Serial ATA, High Speed Serialized AT Attachment,

Revision 1.0a, January 7, 2003."
USB2.0 Comply with USB 2.0 signaling requirements.

Specification is "Universal Serial Bus Specification Revision 2.0."

XAUI Comply with Xilinx RocketIO signaling requirements.

Specification is "Signal Integrity Simulation Kit 3.0, User Guide, December

1, 2003."

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The BSW.mask file is located in the same folder as the HyperLynx application file bsw.exe
(Windows) or bsw (Linux). For example,
C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx\bsw.exe. In Windows, you can
learn the folder name by right-clicking over the "HyperLynx Simulation Software" Start menu
item, and then clicking Properties. The Target box contains the folder name.

Related Topics
“Editing Eye Mask Properties” on page 564

Running Interactive Signal-Integrity Simulations

Use the oscilloscope to run interactive signal-integrity simulation for pins on the net and display
results as waveforms or eye diagrams. By enabling options in the oscilloscope, you can simulate
with the native HyperLynx simulator or a SPICE simulator.

This topic describes the following:

• “Running Native HyperLynx Simulations” on page 566

• “Running SPICE Simulations” on page 567
• “About Eye Diagram Analysis” on page 571
• “Running Standard Eye Diagram Analysis” on page 576
• “Co-Simulation - Modeling Interactions Between Signal Vias and Transmission Planes”
on page 577

Related Topics
“Simulating Signal Integrity with the Oscilloscope” on page 533

“Supported SI Models and Simulators” on page 1264

“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

Running Native HyperLynx Simulations

This section describes how to run interactive simulation using the native HyperLynx simulator.

To run HyperLynx simulation:

1. In the oscilloscope, below the Start Simulation or Start Sweeps button, click
HyperLynx.
The Start Sweeps button replaces the Start Simulation button whenever the Sweep
Manager dialog box is open. See “Simulating Signal Integrity with Sweeps”.

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2. To enable highly-accurate signal-via models, which interact with transmission-plane

structures in the design, select the Simulate t-planes check box.
See “Co-Simulation - Modeling Interactions Between Signal Vias and Transmission
Planes” on page 577 and “About Transmission Planes” on page 1373.
Restriction: The Co-Simulation license is required to enable the Simulate T-Planes
check box.
3. Click Start Simulation or Start Sweeps.
The oscilloscope displays signal-integrity results.
If you enabled the Simulate T-Planes check box in step 2, the HyperLynx PI
PowerScope displays plane noise caused by energy radiating from signal vias in the
selected net.

Related Topics
“Running SPICE Simulations” on page 567

“Running Standard Eye Diagram Analysis” on page 576

Running SPICE Simulations

Use the Run Eldo/ADMS Simulation or Run HSPICE Simulation dialog box to specify SPICE
simulation options. Depending on which SPICE simulator you enabled in the Preferences
Dialog Box - Circuit Simulators Tab, one of these dialog boxes opens when you run SPICE
simulation from the oscilloscope.

You typically run SPICE simulation when you have assigned SPICE or Touchstone models to
pins on the net.

Tip: If you use the HSPICE simulator, it is possible that it cannot obtain licenses fast
enough for sweep simulations. Visit the Synopsys web site for a technical tutorial that
explains how to fix this problem by modifying the port used by the HSPICE license file.

Requirement: The Advanced Scope and SPICE Output licenses are required to run SPICE
simulation. The GHz option is required to run ADMS.

Settings in the Run Eldo/ADMS Simulation and Run HSPICE Simulation dialog boxes are
saved in the <design>.bud, <design>.tln, or <design>.ffs file.

This topic contains the following:

• “SPICE Simulation Restrictions” on page 568

• “Some Electrically-Small Features May Be Discarded” on page 568

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• “Procedure to Run SPICE Simulation” on page 568

• “About the SPICE Netlist and Run Files” on page 571
• “Warning About Running HSPICE on Nets with IBIS Models” on page 571

Related Topics
“Simulating Signal Integrity with the Oscilloscope” on page 533

SPICE Simulation Restrictions

• Batch simulation runs only with the HyperLynx Classic and HyperLynx SI-SPICE
simulators.
• SPICE models must be assigned interactively to pins and cannot be assigned
component-wide using the .REF or .QPL model automapping files.
• For HSPICE only, and if needed, you can edit the netlist and run files prior to
simulation.
The version of ADMS shipping with HyperLynx is somewhat limited and the
oscilloscope does not let you edit the netlist and run files prior to simulation.

Some Electrically-Small Features May Be Discarded

For best netlist extraction results, assign IC models to the net. HyperLynx uses IC models to
determine more wisely which possibly-electrically-small features to write to the SPICE netlist.
If the net contains a via, very small capacitors used to model the via are discarded before the
SPICE netlist is written. These very small capacitors can take a long time to simulate in SPICE.
By contrast, these very small capacitors may not be discarded when simulating with the native
HyperLynx simulator. As a result, it may be difficult to correlate between SPICE and native
HyperLynx simulations for nets with vias.

Very short transmission lines, such as when exporting electrically short vias, are not exported in
order to improve simulation performance.

Procedure to Run SPICE Simulation

Note
If you include SPICE files, set SPICE options, or set SPICE parameters, these settings are
stored in the <design>.bud, <design>.ffs, or <design>.tln file. This makes these settings
design dependent and not session dependent.

To run SPICE simulation:

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1. In the oscilloscope, below the Start Simulation or Start Sweeps button, click one of the
following:
• Eldo/ADMS
• HSPICE
Before starting simulation, the oscilloscope checks that the selected simulator supports
the types of models assigned to the net. If the simulator does not support a model type
assigned to the net, you are either prompted to switch to a different simulator (when
available) or are informed the net cannot be simulated.
See also: “Preferences Dialog Box - Circuit Simulators Tab” on page 1808
2. Click Start Simulation or Start Sweeps. A dialog box opens.
The Start Sweeps button replaces the Start Simulation button whenever the Sweep
Manager dialog box is open. See “Simulating Signal Integrity with Sweeps”.
3. To write the SPICE netlist and run files to a new directory, type or browse to the new
directory in the Output Path box.
4. To change the base name for SPICE netlist and related files, type the new name into the
Output Base Name box.
This capability enables you to retain files and results for several different simulations.
5. If you use HSPICE or a separately-licensed copy of ADMS, you can do any of the
following:
• Select the Regenerate check box to completely rewrite the netlist file and the run
file just prior to simulation. Selecting Regenerate ensures that any changes you have
made since the last simulation to the schematic, board, or power-supply voltage are
written to the files sent to the simulator.
• Clear the Regenerate check box and click Edit to the right of the appropriate box to
edit the netlist file or run file. The file opens in the HyperLynx text editor.
For ADMS, the oscilloscope always rewrites the netlist and run files just prior to
simulation. and the Regenerate check box is unavailable.
6. If you use HSPICE, you can include additional SPICE statements, such as library
include statements, in the run file by doing the following:
a. Create one or more ASCII files containing the SPICE statements you want to
include.
b. Save the file(s) into a model library directory, using a SPICE file name extension.
For information about specifying a model library directory, see “Set Directories
Dialog Box” on page 1854. For information about viewing existing SPICE file name
extensions, or defining new extensions, see “Preferences Dialog Box - Circuit
Simulators Tab” on page 1808.

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c. Click Add File(s). The Select SPICE Include File dialog box opens.
The list displays SPICE files located in the model library directory(ies) and with
SPICE file name extensions.
d. Select the file from the list and click OK.
e. Repeat steps a-d as needed to include the contents of additional files.
Restriction: Include files are unavailable for ADMS.
7. If you use ADMS (with a separate license) and want to edit the simulation step size, type
the value into the Step Size box. The Maximum Step label indicates the largest safe
simulation step size predicted by HyperLynx.
HyperLynx usually chooses a valid step size, but you might consider using a smaller
step size if you know the circuit being simulated has a very high Q factor, such as a
circuit representing an interconnection. Circuits with high Q are typically dominated by
inductance or capacitance, but not resistance, and transmit energy efficiently.
Restriction: The Step size box is unavailable for HSPICE because it uses a variable step
size.
8. If you use HyperLynx SI-SPICE, the top-level netlist cannot contain .include
statements. For convenience, you can specify .param and .option values by clicking Edit
Params or Edit Options, and then doing the following in the dialog box that opens:
a. Click Add. A dialog box opens.
b. Type statement/value pair values into the boxes and click Apply.
c. Click OK.
Statement/value pair information is written to the HyperLynx initialization file (bsw.ini)
and is available to all boards and schematics you simulate with ADMS-SI. Blue text on
the Edit Params and Edit Options buttons indicates the .INI file contains statement/value
pair information.
9. If you use HSPICE and want to override SPICE's initial conditions determination by
specifying your own initial conditions using a SPICE .IC statement, select the Use
initial conditions (.IC) statement check box.
We do not recommend using this option unless you have a specific need for it. You must
manually add the .IC statement to the run file or to an include file. For more information
about using the .IC statement, see the documentation provided with HSPICE.
Restriction: This check box is unavailable for ADMS.
10. Click OK to launch SPICE simulation.

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Result: For HSPICE, the SPICE simulator log window opens. For ADMS, a message
window opens and displays the elapsed time. When simulation finishes, the oscilloscope
displays the simulation waveforms.
See also: “About the SPICE Netlist and Run Files” on page 571
To view the simulation results written to the listing file, click View to the right of the
Listing File box. The View button is unavailable until simulation is complete.
If you are running two copies of HyperLynx, and are using HSPICE, simulation may or
may not begin, depending whether you are using node-locked or floating licensing.

About the SPICE Netlist and Run Files

When you launch SPICE simulation, the oscilloscope automatically creates the following files:

• Netlist—Contains the simulation model of the net and any associated net(s), B-element
calls (applies to IBIS models for HSPICE), IBIS netlists (applies to ADMS)
• Run—Contains oscilloscope settings such as stimulus, probe placement, IC operating
conditions (applies to IBIS models), SPICE buffer model calls, and Touchstone model
calls. The run file calls the netlist file as a sub-circuit.

Warning About Running HSPICE on Nets with IBIS Models

For nets with IBIS models using an external power-supply net (as opposed to using the model
internal value), HSPICE can crash when the external power-supply net voltage is much greater
than the IBIS model internal voltage. For example, the crash may occur if the IBIS model
internal voltage is 3V and the external power-supply net voltage is 5V.

The errors may resemble the following:

**error** Invalid external voltage : PowerClamp

where Card = b_io101

**error** Invalid external voltage : Pullup

where Card = b_io101

Related Topics
“Running Interactive Signal-Integrity Simulations” on page 566

About Eye Diagram Analysis

An eye diagram overlays large numbers of bit transitions at a receiver IC. Use eye diagram
analysis to predict signal-integrity degradation due to the effects of lossy lines (skin effect and
dielectric loss), inter-symbol interference (ISI), jitter, crosstalk, and the presence of vias. The
signal integrity of an individual data bit can also be influenced by the pattern of bits preceding it

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due to cumulative charge effects along the net. This capability is particularly important with
high-speed serial data streams, where the receiver re-generates the clock from the data stream.

Requirement: The Advanced Scope license is required to run eye diagram simulation.

This topic contains the following:

• “Reasons to Run Eye Diagram Analysis” on page 572

• “About Standard Eye Diagrams” on page 575
See also: “FastEye Channel Analysis Overview” on page 635

Reasons to Run Eye Diagram Analysis

Many telecommunication standards and high-speed bus standards contain waveform shape
requirements. You can run eye diagram analysis with the oscilloscope to help predict whether
the board's signaling conforms to the waveform shape requirements.

Eye diagram analysis can help determine whether inter-symbol interference (ISI) is present on
the board's signaling. ISI refers to the signal distortion that can spread the arrival time of
individual data bits in a data channel (set of drivers, receivers, and physical interconnections of
a net transmitting data) so much that the receiver cannot reliably distinguish the individual data
bits. ISI is a major concern in any high-speed design where the period is smaller than the
transmission line delay.

Figure 11-1 on page 573 shows a slow interface without ISI, where every the shape of the
waveform is identical for each cycle. Figure 11-2 on page 574 shows a fast interface with ISI,
where the shape of the waveform is different for each cycle.

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Figure 11-1. ISI Absent - Identical Cycle-to-Cycle Shapes

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Figure 11-2. ISI Present - Different Cycle-to-Cycle Shapes

Signal distortion related to ISI is typically caused by high-frequency signal attenuation and by
residual transient responses, such as crosstalk and reflections, to previous signal transitions on
the interconnect. In an eye diagram, ISI-related signal distortion can appear as jitter, voltage
overshoot or undershoot, and so on.

Figure 11-3 on page 574 shows potential ISI sources for SERDES channels.

Figure 11-3. ISI Sources - SERDES Channels

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In addition to ISI, low-frequency problems might not surface during high-frequency simulations
because of how long they take to appear in the simulation.

About Standard Eye Diagrams

The oscilloscope's standard eye diagram mode can do the following:

• Drive the selected net with a complex multiple bit stimulus over an extended period of
time. You can select a pre-defined bit pattern or define a custom bit pattern. You define
the bit interval (that is, the length of each bit) to determine the stimulus frequency.
• Display the simulation waveforms in an eye diagram format. To create the eye diagram,
the oscilloscope cuts the simulation waveforms into bit interval lengths, and then
displays all of the bit interval waveforms on top of each other. The operating principle is
similar to time-lapse photography, except the previous images do not disappear.
The waveform crossover points cluster around the bit interval boundaries, and the
overall visual effect vaguely resembles a human eye. Large eye openings indicate better
signal quality. See Figure 11-4 for an example of a centered eye diagram (where both
waveform crossover points are visible).

Figure 11-4. Example of Centered Eye Diagram

To provide a more complete view of the waveform crossover points, the oscilloscope extends
the current bit interval waveform with a small amount of the previous bit interval waveform and
a small amount of the following bit interval waveform. For non-Toggle stimulus, each extension
is 20% of the bit interval. For Toggle stimulus, each extension is 10% of the period.

• Place over the waveforms an eye diagram mask with "keep out" areas that waveforms
should avoid. See Figure 11-5 for an example of an eye diagram mask.

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Figure 11-5. Example of Eye Diagram Mask

If a waveform intrudes into the "eye perimeter" keep out, you can investigate factors that close
the eye, such as jitter. If a waveform intrudes into a "reference voltage" keep out, you can
investigate factors that caused the overshoot or undershoot.

Running Standard Eye Diagram Analysis

When editing eye diagram stimulus and mask properties in the oscilloscope, use the waveform
shape requirements from the signaling standard that the board is required to support.

Several features in the oscilloscope become unavailable when you run eye diagram analysis.
Because eye diagrams typically contain a very large amount of data, the oscilloscope displays
only the latest simulation and cannot save simulation data to a CSV file.

Requirement: The Advanced Scope license is required to run standard eye diagram analysis.

To run eye diagram analysis:

1. In the Operation area on the oscilloscope, click Eye Diagram.

2. Specify global or per-net/pin stimulus.
See also: “Setting Up Global Stimulus for Standard-Eye Diagrams” on page 541

3. In the probe spreadsheet, select the check box for the pins to simulate.
4. In the Eye diagram area, click Standard. and click Configure.
5. In the Configure Eye Diagram dialog box, define the eye mask properties, and click OK.
See also: “Editing Eye Mask Properties” on page 564
6. To display the eye mask, select the Eye mask check box in the Show area.
7. Click Start Simulation or Start Sweeps.
All displayed waveforms are automatically erased before simulation starts.

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The Start Sweeps button replaces the Start Simulation button whenever the Sweep
Manager dialog box is open. See “Simulating Signal Integrity with Sweeps”.
If you notice something strange in the eye diagram waveforms, you can examine the
waveforms for individual bit intervals by selecting Standard Operation mode. By
toggling from Eye Diagram mode to Standard mode, the oscilloscope unwraps the eye
diagram waveforms into the standard presentation format. You can restore the wrapping
by selecting Eye Diagram mode.
8. The oscilloscope assumes the crossover point at the beginning of the bit interval is at
time zero. If this is not true, do the following to set the leading crossover point time:
a. Point to the leading crossover point on the waveforms and note the Cursor time
value displayed in the Cursors area.
b. Type the time value into the Horizontal Delay box and press Enter.
In eye diagram mode, the horizontal delay setting has an immediate effect. This
behavior is the opposite of the standard mode behavior, where the horizontal delay
setting has no effect after simulation.
9. If the eye mask position is not centered within the bit interval, you can do any of the
following:
• Click the Adjust Mask button in the Cursors area, and then drag the eye mask to the
new position. The new timing offset values are automatically written to the Eye
Mask tab on the Configure Eye Diagram dialog box.
• Type the exact offset into the eye mask boxes on the Eye Mask tab on the Configure
Eye Diagram dialog box.
See also: “Editing Eye Mask Properties” on page 564

Related Topics
“About Eye Diagram Analysis” on page 571

“Simulating Signal Integrity with the Oscilloscope” on page 533

Co-Simulation - Modeling Interactions Between Signal

Vias and Transmission Planes
Run signal-integrity simulations with enhanced accuracy by enabling signal-via models that
interact with transmission-plane structures in the design. This capability is called “co-
simulation” because it uses both signal-integrity and power-integrity circuit modeling and
simulation engines. Co-simulation helps you account for the energy transferred from a signal
via to a transmission plane as a signal propagates through the signal via.

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When signals from IC driver pins propagate through vias that penetrate transmission planes, the
vias radiate and generate noise between the planes. This noise can reduce the quality of the
incident signal and produce crosstalk in nearby signal and stitching vias. The energy radiated by
the signal propagating through the via provides all plane-noise stimulus; co-simulation ignores
AC signal-integrity models. Co-simulation takes into account the sets of transmission planes
connected by stitching vias.

Before running co-simulation, you set up the design for both signal-integrity and power-
integrity simulations. See SI and PI Co-Simulation QuickStart - LineSim.

It is suggested, but not required, that you assign voltage-regulator module (VRM) power-
integrity models and obtain good decoupling performance from the power-distribution network
(PDN) before running co-simulation. PDNs with high impedance, especially at very low
frequencies when there is no VRM model, can cause exaggerated plane-noise results.

You enable co-simulation by enabling the “Simulate t-planes” option in the oscilloscope. See
“Running Native HyperLynx Simulations” on page 566.

Co-simulation displays signal-integrity results in the oscilloscope and power-integrity results

(plane noise) in the HyperLynx PI PowerScope.

Restrictions:

• The Co-Simulation license and native HyperLynx simulator are required to run co-
simulation.
• Co-simulation supports IBIS IC models and SPICE models for passive components. Co-
simulation does not support SPICE models that contain active components, such as
transistors and diodes.

Related Topics
“About Transmission Planes” on page 1373

Measuring Waveforms and Eye Diagrams

The oscilloscope provides several automatic and manual ways to measure waveforms and eye
diagrams.

This topic contains the following:

• “Measuring Waveforms and Eye Diagrams Automatically” on page 579

• “Measuring Waveforms and Eye Diagrams Manually” on page 591
• “Re-Simulating - Comparing Results” on page 594

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Related Topics
“Viewing Waveforms and Eye Diagrams” on page 558

“About Automatic Measurements in the Oscilloscope” on page 585

“Simulating Signal Integrity with the Oscilloscope” on page 533

Measuring Waveforms and Eye Diagrams Automatically

Use the oscilloscope to automatically perform voltage and timing measurements on voltage
waveforms or eye diagrams currently displayed. For the standard oscilloscope mode, automatic
measurements are available for single-edge transitions. The oscilloscope finds all possible
occurrences of the selected measurement and reports the worst- and best-case results as needed.
Automatic measurements are unavailable for current (as opposed to voltage) waveforms.

This topic contains the following:

• “Running Automatic Measurements” on page 579

• “Availability of Automatic Measurements” on page 580
• “Correlation Between Oscilloscope and Batch Simulation Measurements” on page 581
• “Editing Measurement Threshold Voltages” on page 582
• “Editing Eye Height Sampling Location” on page 582
• “Derating DDR2 Slew Rate Measurements” on page 583
See also: “About Automatic Measurements in the Oscilloscope” on page 585

Running Automatic Measurements

The basic automatic measurement process is to run a simulation, select the waveform to
measure, select the type of measurement, and then view the measurement results.

For restrictions and information about how the oscilloscope measures waveforms, see “About
Automatic Measurements in the Oscilloscope” on page 585.

To run an automatic measurement:

1. In the Measurements area, click one of the following options:

• Entire—Measure across the entire simulation
• Region—Measure within a range of time you specify

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To define the measurement region, position the mouse pointer at the start of the
region (any voltage), drag to define the end of the region, and then release the mouse
button.
If the circuit exhibits a behavior that can distort the measurement, such as a capacitor
charging during design power-up, specifying a waveform region enables you to
specify a valid measurement window.
Restriction: The Region measurement region option is unavailable for eye
diagrams.
2. Select the waveform to measure from the Waveform list.
Waveform names correspond to the names in the probe spreadsheet. Because the
oscilloscope can display latest, previous, and loaded versions of a waveform for non-eye
diagrams, waveform names in the Waveform list include the simulation version.
3. If a small arrow is located to the right of the measurement button, click it to review and
edit measurement options.
All timing-related measurements share the same set of measurement options.
4. Click a measurement button to display the results below the button.
You can copy the measurement results to the Windows clipboard by selecting the text
and pressing Ctrl+C.

Availability of Automatic Measurements

Table 11-6 shows the availability of measurement types for key oscilloscope conditions.

Table 11-6. Availability of Automatic Measurements

Oscilloscope Available Measurements Unavailable
Setting Measurements

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Table 11-6. Availability of Automatic Measurements

Standard mode Rising and falling overshoot Eye width
(non-eye diagram)
Peak-to-peak voltage Eye height

Rise and fall time

Rise and fall slew rate

Flight time (compensated)

Restriction: Flight time measurements are

available only for the latest simulation. This is
because previous and loaded results do not
provide information about the simulation
conditions that produced the waveform, such as
IC models (which contain Vmeas, Vih, and Vil).

DDR2 and DDR3 Slew Rate Derating

Standard eye All None
diagram mode
Restriction: Flight time measurements
(compensated) are available only for the latest
simulation. This is because previous and loaded
results do not provide information about the
simulation conditions that produced the
waveform, such as IC models (which contain
Vmeas, Vih, and Vil).
Current waveforms None All
visible (as opposed
to voltage
waveform)

Correlation Between Oscilloscope and Batch Simulation

Measurements
In some cases, oscilloscope and BoardSim batch simulation measurements may not match.
Batch simulation performs a separate DC simulation to determine the high/low level voltages.
By contrast, automatic measurements use only the waveforms displayed in the oscilloscope to
establish high/low level voltages.

See also: “High and Low Level Voltages - V_high and V_low” on page 585

Related Topics
“Simulating Signal Integrity with the Oscilloscope” on page 533

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“Measuring Waveforms and Eye Diagrams” on page 578

Editing Measurement Threshold Voltages

Use the Threshold Options dialog box to specify the voltage measurement range used to
measure timing properties, such as rise/fall time and slew rate. Edits in this dialog box apply to
all timing-related measurements.

See also: “Measurement Threshold Voltages - V_high_ref and V_low_ref” on page 587

The signaling technology implemented by the IC buffer typically determines the thresholds you
should use. For example, the 20% and 80% values are encouraged in IBIS models.

To edit measurement threshold voltages:

1. In the Oscilloscope, in the Measurements area, click the arrow to the right of the timing-
related measurement button, and then click Options.
2. Do one of the following:
• To specify relative measurement threshold voltages, click Relative thresholds, click
the appropriate option and, if needed, type values into the boxes.
• To specify absolute measurement threshold voltages, click Absolute thresholds and
type values into the boxes.
3. Click Close.

Related Topics
“Measuring Waveforms and Eye Diagrams” on page 578

Editing Eye Height Sampling Location

Use the Eye Height Sampling dialog box to specify the time within in the unit interval (UI) you
want to measure the height of the eye diagram. The sampling location you specify should match
when in the UI the receive circuitry actually samples the logic state of the waveform.

The eye height sampling location is also used to find high and low level voltages used by
automatic measurements for eye diagrams.

See also: “High and Low Level Voltages - V_high and V_low” on page 585

The sampling location represents an offset from the origin of the UI. The oscilloscope calculates
the UI origin by finding the midpoint of the innermost horizontal crossings, identifying that
time as 0.5 UI, and then subtracting UI / 2 to find 0.0 UI. See Figure 11-6.

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Figure 11-6. UI Origin for Eye Height Measurements

To edit eye height sampling locations:

1. Click the arrow to the right of the Eye Height measurement button.
Restriction: The Eye Height measurement button is unavailable unless you enable the
Eye Diagram option in the Operation area of the oscilloscope.
2. Type the value, in UI (unit interval, same as bit interval), in the box.
3. Click OK.

Related Topics
“Eye Height” on page 591

“Measuring Waveforms and Eye Diagrams” on page 578

Derating DDR2 Slew Rate Measurements

Use the DDR2 Slew Rate Derating dialog box to report derated slew rates for DDR2 data,
address, and control pins, and to report non-derated slew rates for DDR differential clock and
strobe pins. As part of filling out a timing budget spreadsheet for the DDR2 signal, you can use
the reported values to look up in datasheet tables the following derating values: delta tDS, and
delta tDH, delta tIS, delta tIH.

Derated slew rate measurements take into account the nominal slew rate of the waveform and
the slew rate of a tangent line for the waveform. The tangent line is plotted from the VREF DC
level to the input threshold voltage as specified in "DDR2 SDRAM SPECIFICATION."

See also: "Specific Note 8" and "Specific Note 9" sections in the "AC & DC operating
conditions" chapter of the JEDEC Standard "DDR2 SDRAM SPECIFICATION" (JESD79-2B).

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When this dialog box is open, the oscilloscope temporarily displays only the latest waveform
for the pin selected in the Waveform list. The oscilloscope hides the waveforms for other pins,
previous results, and loaded results, until you close this dialog box.

Any time two or more transitions exist in the waveform, such as using oscillator stimulus or
running eye diagram analysis, the oscilloscope reports the minimum and maximum slew rates
taken across all transitions.

Requirement: The Advanced Scope license is required to run derating functionality.

Measuring Derated DDR2 Slew Rates

To measure derated DDR2 slew rates:

1. In the Digital Oscilloscope dialog box, in the Measurements area, select the waveform to
measure from the Waveform list.
2. Click the Derate DDR2 button. The DDR2 Slew Rate Derating dialog box opens.
3. In the Speed Grade list, select the speed grade for the design.
4. Click any of the following to specify the type of measurement:
• Standard levels for Setup
• Standard levels for Hold
• Standard differential levels—Measure the slew rate and perform no derating
• Custom levels for Setup—Override the standard measurement voltages
• Custom levels for Hold—Override the standard measurement voltages
• Custom differential levels—Override the standard measurement voltages
Custom levels are discarded when you close the design.
5. If you selected a custom measurement type in the previous step, type new values in the
boxes.
Result: Slew rates appear in the Results area.
6. To measure additional waveforms with the same measurement conditions, select the
waveform names from the Waveform list and view the result.
7. Click Close.

Related Topics
“Measuring Waveforms and Eye Diagrams” on page 578

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About Automatic Measurements in the Oscilloscope

The oscilloscope can automatically perform several types of timing and voltage measurements
on waveforms or eye diagrams currently displayed. You can run automatic measurements on
single-edge transitions, all transitions in the simulation, including multiple-cycle waveforms, or
on transitions located in a region of simulation time that you define. The oscilloscope finds all
possible occurrences of the selected measurement and reports the worst- and best-case results as
needed.

Automatic measurements are based only on data waveforms or eye diagrams displayed in the
oscilloscope, just like a hardware oscilloscope. This means that additional information available
from IC models, such as Vcc and Gnd voltage levels, are not used for automatic measurements.
However, the compensated flight time measurement runs a separate simulation to obtain time-
to-Vmeas.

This topic contains the following:

• “High and Low Level Voltages - V_high and V_low” on page 585
• “Measurement Threshold Voltages - V_high_ref and V_low_ref” on page 587
• “Rising and Falling Overshoot” on page 588
• “Peak-to-Peak Voltage” on page 588
• “Rise and Fall Time” on page 588
• “Rise and Fall Slew Rate” on page 589
• “Compensated Flight Time” on page 589
• “Eye Width” on page 590
• “Eye Height” on page 591
Requirement: The Advanced Scope license is required to run eye diagram simulation.

See also: “Measuring Waveforms and Eye Diagrams Automatically” on page 579, “Derating
DDR2 Slew Rate Measurements” on page 583

High and Low Level Voltages - V_high and V_low

To measure overshoot, rise/fall time, and so on, the oscilloscope identifies voltages representing
the high level (V_high) and low level (V_low). The method it uses to identify high and low
levels depends on the shape of the waveform and whether you have enabled eye diagram
operation.

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Standard Operation - Non-Eye Diagram

The oscilloscope evaluates the shape of the waveform and determines whether significant flat
spots or plateaus exist between transitions.

When waveforms have significant flat spots or plateaus between signal transitions, the most-
common high and low voltages are assigned to the high and low levels. Figure 11-7 illustrates a
waveform containing plateaus.

Figure 11-7. Example of a Waveform with Plateaus

When waveforms do not have significant flat spots or plateaus between signal transitions, the
minimum and maximum voltages in the waveform are assigned as high and low levels.
Figure 11-8 illustrates a waveform without plateaus.

Figure 11-8. Example of a Waveform without Plateaus

On a waveform without plateaus, measured overshoot is zero volts because the oscilloscope
cannot establish high or low level voltages, which overshoot measurements reference.

Eye Diagram Operation

The oscilloscope calculates the average high and low voltages inside an eye aperture box. The
aperture box width is 20% of the bit interval and it is positioned at the UI value you specify in
the Eye Height Sampling dialog box.

See also: “Editing Eye Height Sampling Location” on page 582

Figure 11-9 illustrates an eye diagram with an eye aperture box.

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Figure 11-9. Example of Eye Aperture Box

Measurement Threshold Voltages - V_high_ref and V_low_ref

To perform timing-related measurements, such as rise/fall times, HyperLynx must know at
which voltages to start and stop the measurements. These start/stop threshold voltages are high
level reference voltage (V_high_ref) and low level reference voltage (V_low_ref).

The signaling technology used by IC models on the net determines threshold voltage values,
and whether to specify values based on the high and low level voltages or absolute voltages.

Figure 11-10 illustrates how HyperLynx calculates high/low level reference voltages.

Figure 11-10. Calculating High/Low Level Reference Voltages

where

• V_high and V_low represent high and low level voltages

• V_range represents the absolute value of V_high - V_low

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• V_high_ref represents either:

o a relative voltage V_low + (V_range * % High Reference Offset)
o an absolute high reference offset voltage
• V_low_ref represents either:
o a relative voltage V_low + (V_range * % Low Reference Offset)
o an absolute low reference offset voltage

Rising and Falling Overshoot

Overshoot voltage is measured separately for rising (positive) and falling (negative) transitions.
The worst-case value is reported.

Rising overshoot = V_max – V_high

Falling overshoot = V_low - V_min

where

V_max and V_min are the maximum and minimum voltages for the waveform.

On a waveform without plateaus, measured overshoot is zero volts because the oscilloscope
cannot establish high or low level voltages, which overshoot measurements reference.

See also: “High and Low Level Voltages - V_high and V_low” on page 585

Peak-to-Peak Voltage
Peak-to-peak voltage = V_max - V_min

where

V_max and V_min are the maximum and minimum voltages for the entire waveform.

Rise and Fall Time

The minimum, average, and maximum rise/fall times are reported.

Rise time (in ns) = T_high_ref - T_low_ref

Fall time (in ns) = T_low_ref - T_high_ref

where

T_high_ref is the time at which the waveform crosses V_high_ref.

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T_low_ref is the time at which the waveform crosses V_low_ref.

Only the first crossing within a bit interval is used. Any subsequent crossings, perhaps due to
ringing, are ignored.

Non-monotonic waveform behavior between thresholds is ignored.

Rise and Fall Slew Rate

The minimum, average, and maximum rise/fall slew rates are reported.

Rising slew rate (in V/ns) = (V_high_ref - V_low_ref) / Rise time

Falling slew rate (in V/ns) = (V_high_ref - V_low_ref) / Fall time

Non-monotonic waveform behavior between thresholds is ignored.

Compensated Flight Time

The oscilloscope and batch simulation measure compensated flight time in the same way. They
both obtain time-to-Vmeas from a separate simulation. Non-monotonic waveform behavior
between thresholds is ignored.

If the waveform contains multiple cycles, the oscilloscope reports best-case (minimum) and
worst-case (maximum) compensated flight times.

See also: “Flight-Time Compensation”

Restrictions:

• You can measure compensated flight time only on waveforms for receivers.
• The oscilloscope cannot measure compensated flight time when the receiver or driver
has a SPICE model. This type of model does not provide Vmeasure, Vih, and Vil
information required to perform flight time compensation.
• The receiver waveform can be associated with only one driver, that is, only one driver
can be enabled on the net during compensated flight time measurements.

Modeling Requirements for Compensated Flight Time Measurements on

Differential Pairs
The oscilloscope reports compensated flight time for a differential pair when you assign to the
driver a differential IBIS model that contains the Rref_diff sub-keyword but not the Cref_diff
sub-keyword. If the model contains Cref_diff, it must be commented out to enable differential
compensated flight time measurements. The availability of IBIS models containing Rref_diff or
Cref_diff keywords appears to be limited.

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If the required Rref_diff sub-keyword and the optional Rref or Cref sub-keywords are present,
they are all applied to both signals in the differential pair.

Figure 11-11 illustrates a combination of IBIS sub-keywords for the driver model that enables
the oscilloscope to treat the signals as a differential pair.

Figure 11-11. IBIS Sub-Keywords for Driver for Differential Flight Time
Measurements

See also: “Tips for Selecting Models for Differential Pair Pins” on page 475

Eye Width
Eye width represents the distance in time between the right and left sides of the inner boundary
of the eye diagram, as measured at the midpoint voltage, which is halfway between V_low and
V_high.

Figure 11-12. Eye Width Measurement

Figure 11-12 shows a symmetric eye diagram where the eye width is maximum at the midpoint
voltage. This is not always the case, and the eye width may be narrower at the midpoint voltage
than at another voltage.

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Measuring Waveforms and Eye Diagrams

Eye width measurements made by the oscilloscope do not include a guardband. By contrast,
hardware digital oscilloscopes may apply a guardband such as three sigma.

Eye Height
Eye height represents the distance in voltage between the top and bottom sides of the inner
boundary of the eye diagram, as measured at a location you specify within the unit interval (UI).
You probably want to measure eye height at the location you believe the receive circuitry
actually samples the state of the eye. Figure 11-13 illustrates a measurement location halfway
across the UI.

Figure 11-13. Eye Height Measurement

See also: “Editing Eye Height Sampling Location” on page 582

Eye height measurements do not include a guardband. Digital oscilloscopes may apply a
guardband, such as three sigma.

Related Topics
“Measuring Waveforms and Eye Diagrams” on page 578

Measuring Waveforms and Eye Diagrams Manually

You can perform precise time, voltage, current, and slew-rate measurements from the
oscilloscope screen using measurement crosshairs or simply by observing pointer position
information. The oscilloscope can also display measurement thresholds for all the IC model
pins on the net.

You can attach the measurement crosshairs to a waveform or position it manually. If you attach
the measurement crosshairs to a waveform, it automatically tracks the waveform's voltage or
current as you move the mouse horizontally.

When you place two measurement crosshairs on the oscilloscope screen, the oscilloscope
automatically displays delta voltage (or current), delta time, and slope (slew rate) information.
For example, you can use two measurement crosshairs to measure flight times or overshoot.

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Tip: Point to a waveform to display its pin name in a pop-up box.

This topic contains the following:

• “Using Measurement Crosshairs without Waveform Tracking” on page 592

• “Using Measurement Crosshairs with Waveform Tracking” on page 592
• “Performing Measurements Using the Pointer” on page 594
• “Displaying IC Measurement Thresholds” on page 594

Using Measurement Crosshairs without Waveform Tracking

When waveform tracking is disabled, you can place measurement crosshairs anywhere on the
oscilloscope screen.

To use measurement crosshairs with waveform tracking turned off:

1. If the Track Waveform button in the Cursors area (near the bottom of the dialog box)
appears recessed, click it to disable waveform tracking.
2. Click on the screen where you want to make a measurement.
Result: The first measurement crosshairs appears and its voltage (or current) and time
appear in the Cursors area next to Pt1.
3. To measure a delta voltage (or current), delta time, or slope, click on the screen where
you want to make a second measurement.
Result: The second measurement crosshairs appears. Its voltage (or current) and time
appear in the Cursors area next to Pt2. The time and voltage (or current) differences
between the two measurement crosshairs appear next to Delta V (or Delta A), Delta T,
and Slope.
4. To turn off the measurement crosshairs, do one of the following:
• Click over the screen a third time.
• Click Erase. Clicking Erase also erases the data displayed in the main and overview
panes.

Using Measurement Crosshairs with Waveform Tracking

When waveform tracking is enabled, you select a waveform and attach the measurement
crosshairs to it. Then, as you move the mouse horizontally, the measurement crosshairs tracks
the selected waveform's voltage or current.

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Restriction: Waveform tracking is unavailable in Eye Diagram oscilloscope operation.

To use measurement crosshairs with waveform tracking turned on:

1. If the Track Waveform button in the Cursors area (near the bottom of the dialog box)
does not appear recessed, click it to enable waveform tracking.
When you move the pointer over the waveform, the waveform turns white, indicating
that a mouse click selects the white waveform.
2. Click the waveform to attach the first measurement crosshairs. The white measurement
crosshairs is attached to the selected waveform and it tracks the waveform voltage or
current as you move the mouse horizontally.
3. Position the white measurement crosshairs exactly where you want to make a
measurement, and then click.
Result: The measurement crosshairs turns yellow, locks in place, and its voltage (or
current) and time appear in the Cursors area next to Pt1. A new white measurement
crosshairs appears and it is attached to the selected waveform.
4. To measure a delta voltage (or current), delta time, or slope, on the same waveform,
position the white measurement crosshairs exactly where you want to make a
measurement, and then click.
Or
To measure a delta voltage (or current), delta time, or slope, on another waveform, click
the Track Waveform button twice, click the second waveform to select and attach the
second measurement crosshairs, position the white measurement crosshairs exactly
where you want to make a measurement, and then click.
Results:
• The second measurement crosshairs turns yellow, locks in place, and its voltage (or
current) and time appear in the Cursors area next to Pt2.
• The time and voltage (or current) differences between the two measurement
crosshairs appear next to Delta V (or Delta A), Delta T, and Slope.
• A new white measurement crosshairs appears and it is attached to the selected
waveform.
5. To turn off the yellow measurement crosshairs, click in the screen one or more times
until they disappear.
Or
To turn off waveform tracking, click the Track Waveform button until it does not
appear recessed.

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Performing Measurements Using the Pointer

When you position the pointer over the oscilloscope screen, its voltage (or current) and time
position is displayed in the Cursor field in the Cursors area. You can use the pointer position as
an alternative method to measurement crosshairs to perform quick measurements. Simply point
to the waveform, hold the mouse steady, and then look at the Cursor field.

Displaying IC Measurement Thresholds

You can display in the oscilloscope lines representing Vinh, Vinl, or Vmeasure IC measurement
threshold voltages, as provided by IC models.

Restrictions:

• Thresholds are unavailable for current (as opposed to voltage) waveforms.

• SPICE models do not contain IC measurement threshold information.
To display IC measurement thresholds, do either of the following in the Thresholds For list in
the Show area:

• Select a reference designator and pin.

• Select All IC pins.
Result: The Thresholds for list contains the numeric threshold voltage(s) and the main
and overview panes display lines representing the threshold voltage(s).
To hide IC measurement thresholds:

• In the Thresholds for list, select <no pin selected>.

Related Topics
“Simulating Signal Integrity with the Oscilloscope” on page 533

“Viewing Waveforms and Eye Diagrams” on page 558

Re-Simulating - Comparing Results

You can simulate a given net multiple times to see the effects of opposite driver edges, different
IC models, IC operating parameters, and so on. Sometimes, you want to display the waveforms
one on top of the other, to make comparisons between the results; other times, you want to
display each result individually.

You can display waveforms from two or more standard simulations at the same time, however
you can display only one eye diagram at a time. Therefore you can compare waveforms from
standard simulation but cannot compare eye diagrams from eye diagram simulation.

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This topic contains the following:

• “Plotting the Latest Simulation” on page 595

• “Plotting the Previous Simulation” on page 595
• “Displaying Three Consecutive Simulations” on page 595
• “Erasing Simulations” on page 596
See also: “Saving and Loading Waveform Files” on page 596

Plotting the Latest Simulation

By default, if you run a series of simulations without closing the oscilloscope, the results of each
new simulation supersede the previous simulation results. For example, if you run with the IC
operating parameters set to Slow-Weak, you get one set of waveforms. If you then change
operating parameters to Fast-Strong and re-simulate, the Slow-Weak waveforms disappear and
the Fast-Strong set replaces them.

Plotting the Previous Simulation

For purposes of comparison, you can view the results of both the latest simulation and the next-
to-last, or previous, simulation simultaneously.

To display the results of the previous simulation:

• In the Show area, select the Previous Results check box.

As long as Previous Results is enabled, the oscilloscope continues to display results for both the
latest and previous simulations, even if the oscilloscope is closed and then re-opened.

Displaying Three Consecutive Simulations

When you run corner simulations, such as with IBIS IC models containing min/typ/max data,
you might want to run and compare three simulations: with the IC operating parameters set to
Slow-Weak, then Typical, then Fast-Strong.

To display the results of three consecutive simulations:

1. Select the Latest Results, Previous Results, and Loaded Results check boxes.
2. Run the first simulation.
3. Save the first simulation to a waveform file.
See also: “Saving and Loading Waveform Files” on page 596
4. Run the second simulation.

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Saving and Loading Waveform Files

5. Run the third simulation.

6. Load the waveform file representing the first simulation.
See also: “Saving and Loading Waveform Files” on page 596
Result: All three sets of waveforms are displayed together.

Erasing Simulations
You can erase all the waveforms in the oscilloscope.

To erase the oscilloscope screen:

• In the Digital Oscilloscope dialog box, click Erase.

This causes the loaded, previous, and latest simulation results to disappear.

Saving and Loading Waveform Files

Use the Load/Save Waveforms dialog box to load one or more previously-saved waveform files
into the oscilloscope/FastEye Channel Analyzer or to save the latest waveforms to a comma-
separated values (CSV) or a .LIS file with HyperLynx-specific formatting. Waveform files
contain both voltage versus time and, for the native HyperLynx simulator only, current versus
time data.

The capability to save and load waveform files enables you to do any of the following:

• View simulation results in other applications, such as a mathematics application

• View simulation results in the oscilloscope/FastEye Channel Analyzer at a later time
• Share simulation results with other people
Restriction: Eye diagrams cannot be saved.

This topic contains the following:

• “Saving Waveform Files” on page 597

• “Loading Waveform Files” on page 598
• “About Waveform Files in CSV Format” on page 598

Related Topics
“Opening the Oscilloscope” on page 538

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Saving and Loading Waveform Files

Saving Waveform Files

You can save waveforms from the latest simulation to files in either CSV or HyperLynx .LIS
format. The files do not contain information about the conditions that produced the simulation,
such as IC models, VCC settings, and so on. The oscilloscope can read in all the waveform file
formats that it writes.

Restriction: Eye diagrams cannot be saved.

To save oscilloscope waveform files:

1. In the oscilloscope, click Save/Load.

2. To save the file in CSV format, click CSV, click any of the following output format
options, and then specify the number of points to save:
• Microsoft Excel (w/ extended header)—Use this option if you plan to analyze the
waveforms using Microsoft Excel or another external application that can tolerate
the extra rows at the top of the file that document the simulation conditions and
waveform names.
Windows regional settings determine the decimal and column delimiter characters.
• Mentor Waveform Analyzer / EZWave—Use this option if you plan to display the
waveforms in Mentor Graphics Waveform Analyzer or EZWave.
The top row contains information about waveform names. To support file formatting
required by the Mentor Graphics viewers, decimal delimiting is made with a period .
and column delimiting is made with a comma , regardless of the Windows regional
settings.
• Generic (w/ simple header)—Use this option if you plan to analyze the waveforms
in a mathematics application, such as Matlab.
The top row contains information about waveform names. Windows regional
settings determine decimal and column delimiter characters.
Restrictions: The maximum number of data points is 2^20 (1,048,576). Microsoft
Excel 2003 and earlier supports 64K rows, so if you select the Microsoft Excel format,
the maximum number of data points is 2^16 (65536) minus the number of rows used by
header information. Alternatively, you can make a copy of the CSV file and use a text
editor delete the header rows to read in Excel the maximum number of data rows.
External applications implementing FFT algorithms can directly read files containing
data in quantity of powers of two.
3. To save the file in HyperLynx .LIS format, click HyperLynx .LIS. The oscilloscope
can read only HyperLynx-generated .LIS files.
4. Click Save As. The Save Oscilloscope Output dialog box opens.

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Saving and Loading Waveform Files

5. Specify the location and name of the file, and then click Save.
6. Click Close.

Loading Waveform Files

You can load one or more existing waveform files into the oscilloscope.

Note
On computers running Windows Vista, the oscilloscope cannot load .CSV files unless the
regional/language setting is the same for all three of the following tabs on the Regional
and Language Options dialog box: Formats, Location, Administrative.

You can open this dialog box by clicking Start menu > Control Panel > Control Panel
Home > Clock, Language, and Region > Regional and Language Options.

To load oscilloscope waveform files:

1. In the oscilloscope, click Save/Load.

2. Click Load. The Load Oscilloscope Probe Data dialog box opens.
3. Select CSV or LIS from the Files of Type list, browse to the waveform file, and then
click Load.
Restriction: The oscilloscope can read only HyperLynx-generated .LIS files.
Result: The loaded waveform is added to the probe spreadsheet.
4. Repeat steps 2-3 to load additional waveform files.

About Waveform Files in CSV Format

The time data in the file is in seconds; voltages are in volts; currents are in amps.

There can be a difference in how voltages and currents are measured in the CSV file. If you
choose to probe at the pin, voltages are measured outside the package, but currents are measured
inside. Thus, an oscilloscope probe that appears in the schematic to be outside of an IC is really
located inside the IC package for current measurements, but may be located outside the IC
package for voltage measurements.

The sign of the currents is defined in an unusual way and should be ignored! Large package
transmission-line values, such as 7pF and 8nH, can result in simulated current values with
polarity values opposite of what you may expect.

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Documenting Interactive Simulation Results

Some European versions of Microsoft Excel cannot open the CSV file from the Open menu,
possibly due to the use of commas as decimal indicators. A workaround is to open Windows
Explorer and double-click on the CSV file.

Data from the overview pane is not included when you save the CSV file.

Related Topics
“Simulating Signal Integrity with the Oscilloscope” on page 533

Documenting Interactive Simulation Results

You can document waveforms and eye diagrams by printing them or copying them to the
Windows clipboard.

You can also save waveforms as files in CSV (comma-separated values) and SPICE .LIS
formats. For information, see “Saving and Loading Waveform Files” on page 596.

This topic contains the following:

• “Entering a Comment” on page 599

• “Printing Simulation Results” on page 599
• “Copying Simulation Results to the Clipboard” on page 600

Entering a Comment
Use the comment box above the screen to enter a description or comment that is included when
you print, copy, or save your oscilloscope waveforms.

Printing Simulation Results

You can print your simulation results in order to document them.

BoardSim/LineSim supports color printers and simulation results sent to a color printer produce
waveforms in color.

For the oscilloscope, the overview pane is included when you print your simulation results and
the Overview Pane check box is selected. If you do not want to include the overview pane, clear
the Overview Pane check box.

To print simulation waveforms:

1. In the Digital Oscilloscope or FastEye Channel Analyzer dialog box, click Print.
2. In the Print dialog box, check your printer setup.

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Documenting Interactive Simulation Results

3. Click OK.

Copying Simulation Results to the Clipboard

You can copy your simulation results to the Windows Clipboard in order to paste them into
other Windows applications. The image sent to the Clipboard is formatted, and includes
information such as the name of the board file, the oscilloscope or FastEye Channel Analyzer
settings, and a time and date stamp.

To copy simulation waveforms to the Windows Clipboard:

• Click Copy to Clip.

BoardSim/LineSim writes to the Clipboard in Windows Enhanced Metafile format. The size of
the image may vary depending on which application you paste it into; resize as needed
(metafiles are vectorized and can be sized without damaging image quality).

For the oscilloscope, the overview pane is included when the Overview Pane check box is
selected. If you do not want to include the overview pane in the clipboard image, clear the
Overview Pane check box.

Related Topics
“Simulating Signal Integrity with the Oscilloscope” on page 533

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Simulating Signal Integrity with Sweeps

Use sweeps to automatically vary and simulate design property values over a range that you
specify. Sweeps enable you to study the effects of varying electrical and geometric design
properties, such as the following:

• Passive component values, such as terminators

• Stackup values, such as layer thickness, dielectric constant, and loss
• IC modeling, such as driver technologies, process corners, and IBIS model selectors
• Operating conditions, such as power-supply voltages
• Transmission lines, such as transmission line symbols (LineSim only)
• Unrouted trace segments, such as nets routed with Manhattan routing (BoardSim only).
See “Unrouted Trace Segment Sweeps in BoardSim” on page 606.
In a constrained design, sweeps can help identify a range of design property values that produce
acceptable signal-integrity. You can also use sweeps to understand the effects of manufacturing
tolerances on signal integrity.

Use the Sweep Manager to define the set of design property values (sweep range) to apply to a
design property during sweep simulations. You can sweep multiple design properties at a time,
although this can dramatically increase the number of sweep simulations, simulation run time,
and the amount of memory needed to hold simulation waveforms.

Use the oscilloscope to run a sweep simulation for each combination of design property values
that you specified in the Sweep Manager. Each sweep simulation produces its own waveform,
so the oscilloscope displays sweep results as a series of waveforms.

Tip: If you use the HSPICE simulator, it is possible that it cannot obtain licenses fast
enough for sweep simulations. Visit the Synopsys web site for a technical tutorial that
explains how to fix this problem by modifying the port used by the HSPICE license file.

This topic contains the following:

• “Sweep Simulation Restrictions” on page 602

• “Setting Up and Running Sweeps” on page 603
• “Calculating and Managing the Number of Sweep Simulations” on page 607

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Sweep Simulation Restrictions

Sweep Simulation Restrictions

This topic contains the following:

• “Sweeping IBIS and MOD Models Uses Internal Supply Values” on page 602
• “BoardSim Sweeps Do Not Support Electrical Crosstalk Thresholds” on page 602

Sweeping IBIS and MOD Models Uses Internal Supply

Values
When sweeping [Model Selector] values or IBIS or .MOD buffer models, the internal voltage
for the buffer is used instead of external or on-board values.

If you enabled the “When assigning a model to an IC pin, use a power-supply net connected to
the IC” option in the General tab of the Preferences dialog box, the option is temporarily
overridden during sweeps and restored when sweeps finishes. See “Preferences Dialog Box -
General Tab” on page 1818.

BoardSim Sweeps Do Not Support Electrical Crosstalk

Thresholds
If you enable crosstalk in BoardSim, you must use geometric crosstalk thresholds. If you start
sweep simulations with electrical crosstalk thresholds enabled, BoardSim displays a message
describing this requirement.

Sweeps requires the set of nets to simulate to remain constant and using geometric crosstalk
thresholds supports this requirement. By contrast, if you enable electrical crosstalk thresholds, it
is possible for BoardSim to identify different sets of aggressor nets from one sweep simulation
to another. For example, imagine sweeping (by decrementing) the dielectric thickness so much
that BoardSim finds a new aggressor net on a different metal layer.

For information about how BoardSim automatically identifies the set of aggressor nets to
include during crosstalk simulation based on the crosstalk thresholds you define, see “How
BoardSim Crosstalk Finds Aggressor Nets“.

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Setting Up and Running Sweeps

Setting Up and Running Sweeps

Use the Sweep Manager dialog box to set up sweeps and set the oscilloscope to sweep mode.

Use the Setup tab to define the set of design property values (sweep range) to apply to a design
property during sweep simulations.

Use the Simulation Cases tab to display the combination of design property values for each
sweep simulation, to optionally stop sweep simulations if a simulation fails, and to report failed
simulations.

Use the oscilloscope to run sweep simulations and display waveforms.

Sweeps have the same design set up prerequisites as interactive simulation using the
oscilloscope. See “Preparing Designs for Interactive SI Simulation” on page 533 and “Enabling
SI Simulation Options” on page 536.

Sweep values are saved in the schematic .TLN or .FFS file and in the board .BUD file.

Restrictions: If you enable crosstalk in BoardSim, the Sweep Manager dialog box does not
identify whether components, such as passive components and ICs, belong to the victim net or
an aggressor net. The Assign Models dialog box identifies pins on aggressor nets with a
symbol. See “Opening the Assign Models Dialog Box” on page 468.

This topic contains the following:

• “Procedure to Set Up and Run Sweep Simulations” on page 604

• “Copying Sweep Ranges” on page 605
• “Deleting Sweep Ranges” on page 605
• “Disabling Sweep Simulations” on page 605
• “Locking Sweep Ranges” on page 605
• “Stopping Sweep Simulations on an Error” on page 606
• “Highlighting Design Objects in LineSim Schematics” on page 606
• “Unrouted Trace Segment Sweeps in BoardSim” on page 606

Related Topics
“Sweep Simulation Restrictions” on page 602

“Calculating and Managing the Number of Sweep Simulations” on page 607

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Setting Up and Running Sweeps

Procedure to Set Up and Run Sweep Simulations

To set up and run sweep simulations:

1. In BoardSim, select a net. See “Selecting Nets for SI Analysis“.

2. In BoardSim, if you enable crosstalk, you must set geometric thresholds. See “BoardSim
Sweeps Do Not Support Electrical Crosstalk Thresholds” on page 602.
3. Click Run Swept Values Simulation or select Simulate SI > Run Simulation
Sweeps.
The Sweep Manager dialog box opens.
Opening the Sweep Manager sets the oscilloscope to sweep mode and renames the
“Start Simulation” button to “Start Sweeps.”
4. In the Setup tab, select the design property to sweep by expanding the tree and doing any
of the following:
• Double-click the design property.
• Select the design property and click Add Range or Edit Range (whichever is
displayed).
When a multiple-board project is loaded in BoardSim, the Setup tab displays the board
ID (such as B00) for each design property. See “About Board IDs”.
See also: “Unrouted Trace Segment Sweeps in BoardSim” on page 606
5. In the Sweeping Dialog Box, type or select sweep range values, and then click OK.
Result: The design property is automatically enabled for simulation in the Setup tab in
the Sweep Manager dialog box.
6. Repeat steps 4-5 as needed.
In the Sweep Manager dialog box, the total number of simulations is displayed next to
the Simulations Requested label, near the bottom of the dialog box.
7. In the Sweep Manager dialog box, click Run Sweeps.
The oscilloscope opens in sweep mode.
8. Click Start Sweeps, which is located near the upper-right corner of the dialog box.
9. When simulation completes do any of the following:
• Point to a waveform to display a ToolTip containing swept design property values.
Restriction: ToolTips are not displayed when you point to waveforms formatted as
eye diagrams.
• Use standard oscilloscope features to measure, save, and document the waveforms.

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Setting Up and Running Sweeps

Related Topics
“Measuring Waveforms and Eye Diagrams Automatically” on page 579

“Saving and Loading Waveform Files” on page 596

“Documenting Interactive Simulation Results” on page 599

Copying Sweep Ranges

You can copy the sweep range from one design property to another design property of the same
type. For example, sweeps prevents you from copying a value range from a capacitor to an
inductor.

To copy a sweep range:

1. In the Setup tab, expand the tree, select the design property with the sweep range to
copy, and then click Copy Range.
2. Select the design property to receive the copied sweep range and click Paste Range.

Deleting Sweep Ranges

To delete a sweep range:

• In the Setup tab, expand the tree, select the design property, and click Remove Range.
See also: “Deleting Locked Sweep Ranges” on page 606

Disabling Sweep Simulations

You can disable sweep simulation for a specific design property or tree branch, while
preserving sweep range values.

To disable a sweep simulation:

• In the Setup tab, expand the tree, clear the simulation enable check box for the design
property or an entire hierarchical branch.

Locking Sweep Ranges

You can synchronize sweep range values among design properties of the same type. After you
define the sweep range for the “reference” design property, you can lock the sweep range of
“dependent” design properties to it. During sweep simulations, dependent design properties
always have the same sweep values as the reference design property.

To lock a sweep range:

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Setting Up and Running Sweeps

1. In the Setup tab, expand the tree, select the reference design property, and then click
Copy Range.
2. Select the dependent design property and click Paste Range as a Lock.

Deleting Locked Sweep Ranges

If you delete the sweep range for a reference design property, the sweep ranges for its dependent
properties are also deleted.

Stopping Sweep Simulations on an Error

You can stop all sweep simulations if a simulation error occurs. This capability enables you to
investigate the failing simulation when it happens, instead of waiting for the remaining sweep
simulations to finish.

The spreadsheet in the Simulation Cases tab identifies a failing sweep simulation by displaying
an exclamation mark ! in the first column. Point to the exclamation mark ! to display a ToolTip
that contains either the specific error or a recommendation to interactively simulate the specific
sweep condition.

To stop sweep simulations on an error:

• In the Simulation Cases tab, select the Stop sweeping if error occurs check box.

Highlighting Design Objects in LineSim Schematics

You can use the mouse in LineSim schematics to highlight design properties in the Setup tab of
the Sweep manager dialog box. In free-form schematics, click a schematic symbol to highlight
the design property in the tree. In cell-based schematics, point to a schematic symbol to
highlight the design property in the tree. Highlighting ends when you point away from the
symbol.

You can also click an item in the Setup tab to position the highlight box in cell-based schematic
and select the symbol in free-form schematics.

Unrouted Trace Segment Sweeps in BoardSim

You can sweep unrouted trace segments that represent nets routed with Manhattan routing or
“simple” board-to-board connector models in a MultiBoard project.

Restriction: You cannot sweep routed trace segments unless you first reroute them with
Manhattan routing.

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Calculating and Managing the Number of Sweep Simulations

The Sweeps Manager displays the coordinates of the end points of the unrouted trace segments
in the board viewer. Figure 12-1 shows the end points of the dashed line for the unrouted trace
segment representing the “simple” board-to-board connector model.

Figure 12-1. Swept Unrouted Trace Segment Location in Board Viewer

Related Topics
“Simulating Unrouted Nets with Manhattan Routing“
“Defining Interconnect Electrical Characteristics“

Calculating and Managing the Number of Sweep

Simulations
It is easy to specify many sweep simulations, which can produce very long run times and
memory overloads. This can happen for very large numbers of individual sweep simulations
and for small numbers of individual sweep simulations with many probes.

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Calculating and Managing the Number of Sweep Simulations

Caution
It is possible to specify so many sweep simulations that all memory is consumed before
sweep simulations complete. If this happens, all sweep simulation waveforms that were
created prior to the memory overload are lost.

Although sweeps attempts to allocate sufficient memory prior to starting simulation, it

does not always accurately predict the memory needed by the simulator.

One workaround is to divide the sweeps you want to perform into two or more sessions.
One way to reduce the number of sweeps per session is to reduce the range of one of the
sweep variables.

This topic contains the following:

• “Calculating the Number of Sweep Simulations” on page 608

• “Managing the Number of Sweep Simulations” on page 609

Calculating the Number of Sweep Simulations

The Sweep Manager dialog box automatically calculates and reports the number of sweep
simulations, based on the number of design properties you sweep and the number of values for
each enabled sweep range.

If you sweep the value for one design property, the number of simulations is simply the number
of steps you define for that sweep range. For example, if you sweep the dielectric constant for a
specific stackup layer from 3.1 to 3.5, and specify a simulation count of three or an increment of
0.2, then the oscilloscope sets up and runs three simulations.

However, if you sweep the values for two or more design properties, the number of simulations
is the product of the following expression:

(# sweep values for property 1) x ... x (# sweep values for property N)

For example, if you were to sweep the dielectric constant of a specific dielectric layer across
three values and sweep the IC operating conditions across two values, the oscilloscope
automatically set ups and runs 3 x 2 = 6 simulations as illustrated by Table 12-1.

Table 12-1. Combination of Sweep Simulation Values - Independent Ranges

Value Dielectric Constant IC Operating
Combination for Stackup Layer Condition
DIELECTRIC_A
1 3.1 Fast-Strong
2 3.3 Fast-Strong

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Table 12-1. Combination of Sweep Simulation Values - Independent Ranges

Value Dielectric Constant IC Operating
Combination for Stackup Layer Condition
DIELECTRIC_A
3 3.5 Fast-Strong
4 3.1 Slow-Weak
5 3.3 Slow-Weak
6 3.5 Slow-Weak
An exception is where you synchronize, or “lock,” the range of values for a property to another
property. In this case, all properties with locked values collapse to one term in the expression
above. See “Locking Sweep Ranges” on page 605.

For example, if you were to sweep the dielectric constant across three values for stackup layer
DIELECTRIC_A, lock the sweep range for stackup layer DIELECTRIC_B to stackup layer
DIELECTRIC_A, and then sweep the IC operating conditions across two values, the
oscilloscope automatically sets up and runs 3 x 2 = 6 simulations as illustrated by Table 12-2.
Table 12-2. Combination of Sweep Simulation Values - Locked Ranges
Value Dielectric Constant Dielectric Constant for Stackup IC Operating
Combination for Stackup Layer Layer DIELECTRIC_B Condition
DIELECTRIC_A
1 3.1 3.1 (locked to DIELECTRIC_A) Fast-Strong
2 3.3 3.3 (locked to DIELECTRIC_A) Fast-Strong
3 3.5 3.5 (locked to DIELECTRIC_A) Fast-Strong
4 3.1 3.1 (locked to DIELECTRIC_A) Slow-Weak
5 3.3 3.3 (locked to DIELECTRIC_A) Slow-Weak
6 3.5 3.5 (locked to DIELECTRIC_A) Slow-Weak

Managing the Number of Sweep Simulations

To help you manage the number of sweep simulations, dialog boxes display the number of
simulations and provide ways to disable specific sweep simulations.

Displaying the Number of Sweep Simulations

The Sweep Manager dialog box displays the total number of sweep simulations next to the
Simulations Requested label near the bottom of the dialog box. In addition, the tree view shows
how many steps (that is, simulations), that individual initial/final and value/tolerance
assignments will generate.

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The Sweeping dialog box displays the number of simulations next to the Simulation Count label
located in each sweeping option area of the dialog box.

Disabling Specific Sweep Values Within a Range

If you specify sweep ranges by using the initial/final values or tolerance methods in the
Sweeping dialog box, sweep values are automatically displayed in the By List box.

You can disable specific sweep values within a range by enabling the By List sweep range
method and then removing values from the By List box.

Disabling Specific Sweep Simulations

After you assign a sweep range to a design property, the Sweep Manager dialog box adds
simulation check boxes for the item and its branch in the tree view. Clear a check box to disable
simulation for an item or an entire branch. This capability may be useful if you want to rerun
sweeps for only specific design properties.

Check boxes with a gray background indicate that some items lower in the branch are enabled
while others are disabled.

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Chapter 13
Simulating Signal Integrity with IBIS-AMI
Channel Analysis

Use the IBIS-AMI Channel Analyzer to simulate SERDES channels in the time domain with
millions of bits in a relatively short amount of time. IBIS-AMI channel analysis creates eye
diagrams and bit error rate (BER) plots to help you see how channel topology, jitter, and so on,
affect channel performance.

IBIS-AMI is an industry standard that uses algorithmic code to model the complex and non-
linear transformations of signal waveforms inside transmitters and receivers. Shared executable
library files (.DLL for Windows and .so for Linux) implement the algorithmic code and protect
intellectual property (IP). Typical AMI .DLL/.so files contain proprietary algorithms for
transmitter pre-emphasis, receiver equalization and DFE, and receiver clock and data recovery.

This topic contains the following:

• “IBIS-AMI Channel Analysis QuickStart” on page 612

• “IBIS-AMI Channel Analysis Overview” on page 617
• “IBIS-AMI Sweep Simulation Calculations” on page 626

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IBIS-AMI Channel Analysis QuickStart

IBIS-AMI channel analysis produces a bit error rate (BER) plot and an eye diagram for one
single-ended or differential channel at a time. Use these capabilities to investigate how channel
topology, Rx/Tx parameters, jitter, crosstalk, and so on, affect channel BER and eye closure.

The IBIS-AMI channel analysis engine can optionally do the following:

• Sweep AMI model parameters, such as transmitter strength and receiver equalization,
and display results in the HyperLynx IBIS-AMI Sweeps Viewer.
• Take into account crosstalk from aggressor nets on the selected victim channel. The
IBIS-AMI wizard can either automatically create the crosstalk files or use crosstalk files
that you created with hardware measurements or saved from a previous IBIS-AMI
channel analysis.
You can run IBIS-AMI channel analysis on pre- and post-layout designs. Perform “what if”
experiments on post-layout designs by exporting the channel from BoardSim to a free-form
schematic and editing it in LineSim. See “Exporting BoardSim Nets to LineSim” on page 1161.

Requirements
• The FastEye / AMI Support license is required to run IBIS-AMI channel analysis.
• The BoardSim PI Only or LineSim PI Only license cannot be checked out when you run
IBIS-AMI channel analysis.
• IBIS-AMI channel analysis supports the [Algorithmic Model] keyword, but not the
other keywords introduced by I/O Buffer Information Specification (IBIS) Version 5.0.
• The IBIS specification states “The combination of the transmitter’s analog back-end, the
serial channel and the receiver’s analog front-end are assumed to be linear and time
invariant.” IBIS-AMI channel analysis does not check for non-linear channels.
• Crosstalk analysis does not automatically run round robin simulations for primary
(victim) or aggressor channels with more than one transmitter. To run FastEye channel
analysis with different victim/aggressor pins driving the channel, you manually
enable/disable the appropriate model pins and run separate analyses.
• .DLL (Windows) and .so (Linux) files are executable files. Make sure the IBIS model
specifies .DLL/.so files for all the computer platforms you use to run simulations. Store
.DLL/.so files in the same folder as the IBIS model or in another folder displayed in the
Model-library file path(s) list in the Set Directories Dialog Box.

Tip: If you install the 64-bit version of HyperLynx on a Windows computer, but have a
.DLL that is 32 bit, you can run the 32-bit version of HyperLynx to run IBIS-AMI
channel analysis. On Windows, the Start menu contains separate items to open these
versions of HyperLynx. By contrast, Linux installations are 64-bit only or 32-bit only.

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Figure 13-1. IBIS-AMI Channel Analysis Task Flow

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Procedure
1. Optionally, use previously-saved (or externally-created) analog channel characterization
and crosstalk files and go to step 3. See “External Analog Channel Characterization
Files” on page 1621.
2. Set up the channel to simulate.
a. Set up the channel topology, which is the set of physical elements and geometries
used to implement the channel and includes trace segments, layer stackup, signal
vias, and so on.
b. Open a BoardSim board or create a new LineSim schematic.
• Select File > Open Board. See “Creating BoardSim Boards”.
You can also export signal nets from BoardSim to a LineSim free-form
schematic, to perform “what if” analysis. See “Exporting BoardSim Nets to
LineSim” on page 1161.
• Select File > New Free-Form Schematic | New Cell-Based Schematic. Define
the channel topology by adding symbols to the schematic. See “Creating New
LineSim Schematics”.

c. Verify the stackup layer thicknesses and material properties.

• Select Edit > Stackup > Edit. See “Creating and Editing Stackups” on
page 353.
d. Assign IC models to channel transmitters and receivers.
You can use any type of model supported by interactive SI simulation, including
IBIS AMI and SPICE. See “Selecting Models” - LineSim or “Setting Up Boards for
Signal-Integrity Simulation” - BoardSim.
e. Set IC model input/output modes.
For bidirectional IC buffers, interactively set the transmitter pin to the output
direction and set the receiver pin to the input direction. If you include crosstalk
during channel analysis, also do this on the aggressor nets.
Crosstalk analysis does not automatically run round robin simulations for victim or
aggressor channels with more than one transmitter. To see the effects of both far-end
crosstalk (FEXT) and near-end crosstalk (NEXT) on the channel analysis, transmit
the signal in both directions on aggressor nets. To run FastEye channel analysis with
different victim/aggressor transmitter pins set to output mode, manually
enable/disable the appropriate model pins and run separate analyses.
f. Optionally, set up signal net termination.
See “Optimizing Termination with the Terminator Wizard” on page 945.

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g. Set up signal-integrity simulation options, such as crosstalk threshold and lossy

transmission line modeling. See “Enabling SI Simulation Options” on page 536.
Requirement: In BoardSim, set the crosstalk threshold before opening the IBIS-
AMI Channel Analyzer wizard. You cannot change the crosstalk threshold from
within the wizard.
3. If you are using BoardSim, select the net to simulate. See “Selecting Nets for SI
Analysis”.
4. Set up IBIS-AMI channel analysis options and simulate.
a. Select Simulate SI > Run IBIS-AMI Channel Analysis or click . The IBIS-
AMI Channel Analyzer wizard opens.
b. Perform the steps in the wizard. Read the wizard page text and click Help for
additional information.
c. Optionally, save analog channel characterization files for future analyses from the
Channel Characterization Dialog Box. These files are stored in memory, but are
discarded when you close the wizard. Note that crosstalk files are automatically
stored to disk.
d. When done setting values in the wizard, click Save & Run.
The Run Eldo/ADMS Simulation dialog box opens. You normally do not need to
make any changes and can click OK.
Time-domain simulation runs to generate the impulse response for the channel. This
simulation does not happen if you manually ran channel characterization simulation
from the IBIS-AMI Channel Analyzer Wizard - Set Up Channel Characterizations
Page.
When channel characterization is complete, simulation runs and uses the AMI
executable models.
The wizard remains open after analysis completes, so you can re-run analysis for a
different channel with the same settings or for the same channel with different settings.
5. View results.
If you sweep AMI parameters, these results are available:
• Display eye density plots or bit error rate plots in the HyperLynx IBIS-AMI Sweeps
Viewer. BER plots help identify valid data sampling locations by reporting BER as a
function of the sampling location across the unit interval (UI, same as bit interval)
and voltage. The color of the contour indicates its BER.
You can re-open the sweep results by opening the HyperLynx IBIS-AMI Sweeps
Viewer and browsing to the .SDS (simulation data storage) file. The .SDS file is
located in a subfolder named AMI_Sweep_Results_<month>-<day>-
<year>_<hour>h-<minute>m located in the design folder.

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If you do not sweep AMI parameters, these results are available:

• Display eye density plots or bit error rate plots in the HyperLynx SI Eye Density
Viewer. BER plots help identify valid data sampling locations by reporting BER as a
function of the sampling location across the unit interval (UI, same as bit interval)
and voltage. The color of the contour indicates its BER.
• Display bathtub curves in the Bathtub Chart Dialog Box. Use this dialog box to
display and document bathtub curves. Bathtub curves help identify valid data
sampling locations by reporting the bit error rate (BER) as a function of the
sampling location across the unit interval (UI, same as bit interval) at several voltage
offsets.
• Display the Statistical Contour Chart Dialog Box. Use this dialog box to display a
nested series of eye opening contours and their bit error rate (BER). The color of the
contour indicates its BER. Like bathtub curves, statistical contours indicate the
quality of sampling locations across the unit interval (UI, same as bit interval). An
advantage of statistical contours over bathtub curves is that the inner-eye contours
display both sampling time and voltage information.
You can use the View buttons on the IBIS-AMI Channel Analyzer Wizard - View
Analysis Results Page to re-open dialog boxes that display results. The results are kept
in memory until you close the wizard or run a new analysis.

Related Topics
“Wizard Table of Contents Pane” on page 1410
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

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IBIS-AMI Channel Analysis Overview

I/O Buffer Information Specification (IBIS) version 5.0 introduced algorithmic modeling
interface (AMI) modeling with the [Algorithmic Model] keyword. This capability divides
channel simulation into electrical (that is, analog) and algorithmic components.

• Analog component—Provides channel behavior from the analog buffer for the
transmitter, through the passive interconnect, to the analog buffer for the receiver. The
transmitter and receiver analog buffers contain no signal-processing behaviors, such as
equalization. The IBIS-AMI channel analyzer automatically provides the analog
component by transmitting a short PRBS bit sequence through the channel and creating
a fitted-poles file (.PLS) that represents the analog channel characterization.
• Algorithmic component—Provides signal-processing behavior for the transmitter and
receiver. This includes transmitter pre-emphasis, receiver equalization and DFE,
receiver clock-recovery, and other behaviors produced by adaptive circuitry that
changes over time.
o IBIS-AMI .DLL (Windows) or .so (Linux) file—Contains signal waveform
transformation (that is, signal-processing) behaviors. This is an executable file that is
compiled for a specific computer platform.
o IBIS-AMI .AMI file —Contains parameter values. Each .DLL/.so file has one
companion .AMI file.
IBIS-AMI channel analysis runs much faster than standard-eye-diagram simulations when
simulating many bits.

Note
FastEye channel analysis runs many times faster than IBIS-AMI channel analysis. See
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629. FastEye
simulation does not support the [Algorithmic Model] keyword.

Figure 13-2 shows the main simulation steps and Table 13-1 on page 619 describes them.

Figure 13-3 shows the crosstalk simulation steps and Table 13-2 on page 624 describes them.

Requirement: The Crosstalk license is required to:

• Enable crosstalk and differential-pair simulation in BoardSim.

• Create coupling regions in LineSim.

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Figure 13-2. IBIS-AMI Channel Analysis Simulation Block Diagram - Main Flow

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Table 13-1. IBIS-AMI Channel Analysis Simulation Block Diagram - Main Flow
Item Description
Create new analog channel Choose Yes to automatically create a new analog channel
characterization file? characterization file.

Choose No to load an existing analog channel characterization

file from either of the following sources:
• Automatically created by the wizard and manually saved by
you.
• Created by hardware measurements or third-party software.
Assign .AMI and .DLL/.so Assign .AMI and .DLL (Windows) or .so (Linux) files to the
files channel transmitter and receiver.

See “IBIS-AMI Channel Analyzer Wizard - Configure AMI

Models Page” on page 1732.
Channel topography Set of physical elements that implement the channel. This
includes trace segments, layer stackup, signal vias, and so on.
Tx/Rx analog models IC models representing the transmitter analog back end and the
receiver analog front end.

You can use all model types supported by interactive SI

simulation, including IBIS AMI and SPICE. See “Selecting
Models” - LineSim or “Setting Up Boards for Signal-Integrity
Simulation” - BoardSim.

For bidirectional IC buffers, interactively set the transmitter pin

to the output direction and set the receiver pin to the input
direction.
IC model input/output For bidirectional IC buffers, interactively set the transmitter pin
settings to the output direction and set the receiver pin to the input
direction. If you include crosstalk during channel analysis, also
do this on the aggressor nets.

Crosstalk analysis does not automatically run round robin

simulations for victim or aggressor channels with more than one
transmitter. To see the effects of both far-end crosstalk (FEXT)
and near-end crosstalk (NEXT) on the channel analysis, transmit
the signal in both directions on aggressor nets. To run FastEye
channel analysis with different victim/aggressor transmitter pins
set to output mode, manually enable/disable the appropriate
model pins and run separate analyses.

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Table 13-1. IBIS-AMI Channel Analysis Simulation Block Diagram - Main Flow
Item Description
Analog channel Run simulation to create a fitted-poles file representing the
characterization analog channel and optionally the crosstalk effects from
aggressor nets.

Specify characterization properties with the “IBIS-AMI Channel

Analyzer Wizard - Set Up Channel Characterizations Page” on
page 1742 and Channel Characterization Dialog Box.
Saved file created by wizard An existing fitted-poles (.PLS) or S-parameter file (.S2P, .S4P)
or cascading that contains results from a previous channel characterization.
See Loaded Load.
Analog channel If you prefer to characterize channels only in the frequency
characterization in frequency domain, you can provide an S-parameter file to represent the
domain analog channel characterization.

Check the model quality before loading the file. See “Checking
S-Parameter Model Quality” on page 1082.

You might create the S-parameter model by measuring PCB

hardware or by exporting a BoardSim or LineSim net as an S-
parameter model. See “Exporting Nets to S-Parameter Models”
on page 1152.
.AMI file The parameter file. This file is located in a models folder named
in the Set Directories Dialog Box.

IBIS-AMI Channel Analysis wizard does not modify this file.

.DLL/.so file The file containing Tx and Rx signal processing functions.
Receiver .DLL/.so files may additionally contain clock and data
recovery functions. This file is located in a models folder named
in the Set Directories Dialog Box.

Note that .DLL/.so files are executable files. Make sure the IBIS
model specifies .DLL/.so files for all the computer platforms you
use to run simulations. Store .DLL/.so files in the same folder as
the IBIS model or in another folder displayed in the Model-
library file path(s) list in the Set Directories Dialog Box.

If you install the 64-bit version of HyperLynx on a Windows

computer, but have a .DLL that is 32 bit, you can open the 32-bit
version of HyperLynx to run IBIS-AMI channel analysis. On
Windows, the Start menu contains separate items to open these
versions of HyperLynx. By contrast, Linux installations are 64-
bit only or 32-bit only.

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Table 13-1. IBIS-AMI Channel Analysis Simulation Block Diagram - Main Flow
Item Description
Edit .AMI parameters Opens the IBIS AMI Parameter Editor, which you use to set
parameter values. The editor saves your changes into a new
.AMI file named <original_file_name>_settings.ami. This
behavior preserves the contents of the original .AMI file.
Fitted-poles file New or previously-saved fitted-poles file created by the wizard.

This file represents the analog channel characterization as

network parameter data in fitted-poles format. See “About
Touchstone and Fitted-Poles Models” on page 1066.

The file is in memory only unless you manually save it to disk

from the Channel Characterization Dialog Box.
S-parameter file See Analog channel characterization in frequency domain.

This file represents the analog channel characterization as

network parameter data in Touchstone format. See “About
Touchstone and Fitted-Poles Models” on page 1066.
Analog channel Fitted-poles or S-parameter file that represents the analog
characterization file channel characterization.

IBIS-AMI channel analysis automatically combines the analog

channel characterization files with the optional Crosstalk files.
.DLL/.so input string The wizard sets certain .DLL/.so model values, based on values
you set in the IBIS AMI Parameter Editor. The .DLL/.so input
string contains only "In" and "InOut" usage types.
_settings .AMI file The original .AMI file plus any parameter changes you make in
the IBIS AMI Parameter Editor.

This file is usually named <original_file_name>_settings.ami

and located in the design folder. See “About Design Folder
Locations” on page 1391.

Note: You can use the IBIS AMI Parameter Editor to save this
file to other locations. You can use the AMI File Assignment
Dialog Box to load this file from other locations.
Include crosstalk from Optionally, choose Yes to take into account the response at the
aggressors? victim receiver from crosstalk caused by aggressor nets driving a
step transition. The IBIS-AMI wizard can either automatically
create the crosstalk files or use crosstalk files that you created by
measuring PCB hardware.
Go to crosstalk flow See “From main flow” symbol in Figure 13-3 on page 624.

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Table 13-1. IBIS-AMI Channel Analysis Simulation Block Diagram - Main Flow
Item Description
From crosstalk flow See “Go to main flow” symbol in Figure 13-3 on page 624.
Crosstalk files Files representing the crosstalk measured at the receiver of the
selected/victim net and caused by an aggressor driving a step
transition.

Each aggressor has a separate file. To see the effects of both far-
end crosstalk (FEXT) and near-end crosstalk (NEXT) on the
channel analysis, transmit the signal in both directions on
aggressor nets.

FastEye channel analysis automatically combines the crosstalk

files with the Analog channel characterization file.
Stimulus, report types, and Options you set in various wizard pages.
other wizard settings
IBIS-AMI channel analysis The IBIS-AMI channel analysis engine, which manages the
overall simulation process. It performs many tasks, including:
• Convolving bits from the bit sequence with waveforms
provided by the .DLL/.so file.
• Calculating worst-case bit sequences.
• Applying jitter to bits in the bit sequence
• And so on.

Note the bidirectional transactions between the .DLL/.so file and

IBIS-AMI channel analysis engine. For example, the analysis
engine requests a waveform and the .DLL/.so provides it.
Crosstalk files Optional files representing the response at the victim receiver
from crosstalk caused by aggressor nets driving a step transition.
Eye density and BER plots Statistical simulation results.
Process plots Format simulation results.

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Table 13-1. IBIS-AMI Channel Analysis Simulation Block Diagram - Main Flow
Item Description
BER and eye density plots Display bit error rate (BER) and eye density plots in either:
• HyperLynx SI Eye Density Viewer—when you do not run
AMI model parameter sweeps
• HyperLynx IBIS-AMI Sweeps Viewer—when you run AMI
model parameter sweeps

BER plots help identify valid data sampling locations by

reporting BER as a function of the sampling location across the
unit interval (UI, same as bit interval) and voltage. The color of
the contour indicates its BER.

Eye density plots display the density of traces in an eye diagram.

For sweeps, .SDS (simulation data storage) files map individual

BER and eye density plots (.TPS files) to specific swept
parameter values. The .SDS file name is of form
<reference_designator.pin>_(<probe_location>). .TPS file
names are partially random. Both types of files are written to a
sub-folder in the design folder. The subfolder name takes the
form “AMI_Sweep_Results_<month>-<day>-<year>_<hour>h-
<minute>m. See “About Design Folder Locations” on
page 1391. For example,
<design_folder>\AMI_Sweep_Results_Nov-10-2011_9h-
27m\U2.1_(at_pin).sds.
Statistical contours Display bit error rate (BER) in the Statistical Contour Chart
Dialog Box.
Bathtub curves Display bathtub curve in the Bathtub Chart Dialog Box.

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Figure 13-3. IBIS-AMI Channel Analysis Simulation Block Diagram - Crosstalk

Flow

Table 13-2. IBIS-AMI Channel Analysis Simulation Block Diagram - Crosstalk

Flow
Item Description
From main flow See “Go to crosstalk flow” symbol in Figure 13-2 on page 618.
Create new crosstalk files? Choose Yes:
• To automatically create new crosstalk files.
• If you changed the channel topology, such as editing stackup
layer properties, or enable different transmitter pins on
aggressor nets.
Channel topography Set of physical elements that implement the channel. This
includes trace segments, layer stackup, signal vias, and so on.

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Table 13-2. IBIS-AMI Channel Analysis Simulation Block Diagram - Crosstalk

Flow (cont.)
Item Description
Tx/Rx analog models IC models representing the transmitter analog back end and the
receiver analog front end.

You can use all the types of models supported by interactive SI

simulation, including IBIS AMI and SPICE. See “Selecting
Models” - LineSim or “Setting Up Boards for Signal-Integrity
Simulation” - BoardSim.
Selected aggressor nets Use the IBIS-AMI Channel Analyzer Wizard - Set Up Channel
Characterizations Page to select the aggressor nets to include in
the Crosstalk simulation.
IC model input/output For bidirectional IC buffers, interactively set the transmitter pin
settings to the output direction and set the receiver pin to the input
direction. If you include crosstalk during channel analysis, also
do this on the aggressor nets.

Crosstalk analysis does not automatically run round robin

simulations for victim or aggressor channels with more than one
transmitter. To see the effects of both far-end crosstalk (FEXT)
and near-end crosstalk (NEXT) on the channel analysis, transmit
the signal in both directions on aggressor nets. To run FastEye
channel analysis with different victim/aggressor transmitter pins
set to output mode, manually enable/disable the appropriate
model pins and run separate analyses.
Crosstalk settings Set up crosstalk modeling. See “Enabling SI Simulation
Options” on page 536.

Requirement: In BoardSim, set the crosstalk threshold before

opening the FastEye Channel Analyzer wizard. You cannot
change the crosstalk threshold from within the wizard.
Saved victim receiver Saved files containing the response at the victim receiver from
responses to aggressor nets crosstalk caused by Selected aggressor nets driving a step
transition.
Crosstalk simulation Measure the response at the victim receiver from crosstalk
caused by aggressor nets driving a step transition.
.LIS files Waveform file in .LIS format that is created by any of the
following:
• FastEye crosstalk simulation. The file is in memory only
unless you manually save it to disk from the Channel
Characterization Dialog Box.
• HyperLynx oscilloscope
• SPICE simulation

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Table 13-2. IBIS-AMI Channel Analysis Simulation Block Diagram - Crosstalk

Flow (cont.)
Item Description
Fitted-poles files Network parameter data in fitted-poles (.PLS) format. See
“About Touchstone and Fitted-Poles Models” on page 1066.
S-parameter files Network parameter data in Touchstone format. See “About
Touchstone and Fitted-Poles Models” on page 1066.

If you prefer to characterize channels only in the frequency

domain, you can provide an S-parameter file to represent the
crosstalk between the selected/victim and aggressor channels.
You might create the S-parameter model by measuring PCB
hardware. See “External Analog Channel Characterization Files”
on page 1621.

Check the model quality before loading the file. See “Checking
S-Parameter Model Quality” on page 1082.
Crosstalk files Files representing the crosstalk measured at the receiver of the
selected/victim net and caused by an aggressor driving a step
transition.

There is a separate file for each aggressor. To see the effects of

both far-end crosstalk (FEXT) and near-end crosstalk (NEXT)
on the channel analysis, transmit the signal in both directions on
aggressor nets.

FastEye channel analysis automatically combines the crosstalk

files with the Analog channel characterization file.
Go to main flow See “From crosstalk flow” symbol in Figure 13-2 on page 618.

Related Topics
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611
“HyperLynx SI Eye Density Viewer” on page 1721
“HyperLynx IBIS-AMI Sweeps Viewer” on page 1667

IBIS-AMI Sweep Simulation Calculations

The number of simulations included in the sweep is based on the IBIS-AMI model parameters
you sweep and the number of values in each enabled sweep range. When you sweep the values
for two or more model parameters, the number of simulations is the product of the following
expression:

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(# sweep values for parameter 1) x ... x (# sweep values for parameter N)

For example, if you sweep the transmitter strength across five values and sweep the receiver
equalization across three values, IBIS-AMI channel analysis set ups and runs 5 x 3 = 15
simulations.

An exception is when you synchronize or lock the range of values for a model parameter to
another model parameter. In this case, the locked model parameters do not consume additional
simulations and their sweep values can be deleted from the above expression. See “Paste Range
as a Lock” on page 1755.

Caution
It is easy to specify many sweep simulations, which can produce very long run times and
memory overloads. It is possible to specify so many sweep simulations that all memory is
consumed before sweep simulations complete.

One workaround is to divide the sweeps you want to perform into two or more sessions.
One way to reduce the number of sweeps per session is to reduce the range of the sweep
variables.

The IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model Settings Page displays the
number of simulations near the bottom of the page.

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Chapter 14
Simulating Signal Integrity with FastEye Channel
Analysis

Use the FastEye™ Channel Analyzer to create eye diagrams, bit error rate (BER) plots, bathtub
curves, worst-case bit stimulus, and optimum tap weight values for pre-emphasis and decision-
feedback equalization (DFE) circuits. Use these capabilities to investigate how channel
topology, jitter, crosstalk, and so on, affect channel BER and eye closure.

The FastEye Channel Analyzer characterizes channel behavior by analyzing analog channel
characterization waveforms and optional aggressor/victim crosstalk waveforms. It can
automatically create these waveforms or extract them from waveforms that you create with
other software.

This topic contains the following:

• “FastEye Channel Analysis QuickStart” on page 630

• “FastEye Channel Analysis Overview” on page 635
• “FastEye Diagram Measurements” on page 645

Related Topics
“Preparing Designs for Interactive SI Simulation” on page 533

“Enabling SI Simulation Options” on page 536

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FastEye Channel Analysis QuickStart

FastEye Channel Analysis QuickStart

FastEye channel analysis produces a bit error rate (BER) plot, bathtub curve plot, and an eye
diagram for one single-ended or differential channel at a time. Use these capabilities to
investigate how channel topology, jitter, crosstalk, and so on, affect channel BER and eye
closure.

The FastEye channel analysis engine can optionally take into account the selected/victim
channel receiver response due to crosstalk from an aggressor net driving a step transition. The
FastEye wizard can either automatically create the crosstalk files or use crosstalk files that you
create by measuring PCB hardware.

You can run FastEye channel analysis on pre- and post-layout designs. Perform “what if”
experiments on post-layout designs by exporting the channel from BoardSim to a free-form
schematic and editing it there. See “Exporting BoardSim Nets to LineSim” on page 1161.

Requirements
The FastEye / AMI Support license is required to run FastEye channel analysis.

The BoardSim PI Only or LineSim PI Only license cannot be checked out when you run
FastEye channel analysis.

The Crosstalk license is required to run crosstalk simulation.

Crosstalk analysis does not automatically run round robin simulations for victim or aggressor
channels with more than one transmitter. To run FastEye channel analysis with different
victim/aggressor pins driving the channel, you manually enable/disable the appropriate model
pins and run separate analyses.

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FastEye Channel Analysis QuickStart

Figure 14-1. FastEye Channel Analysis Task Flow

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FastEye Channel Analysis QuickStart

Procedure
1. Optionally, use previously-saved (or externally-created) analog channel characterization
and crosstalk files and go to step 3. See “External Analog Channel Characterization
Files” on page 1621.
2. Set up the channel to simulate.
a. Set up the channel topology, which is the set of physical elements and geometries
used to implement the channel and includes trace segments, layer stackup, signal
vias, and so on.
Open a BoardSim board or create a new LineSim schematic.
• Select File > Open Board. See “Creating BoardSim Boards”.
You can also export signal nets from BoardSim to a LineSim free-form
schematic, to perform “what if” analysis. See “Exporting BoardSim Nets to
LineSim” on page 1161.
• Select File > New Free-Form Schematic | New Cell-Based Schematic. Define
the channel topology by adding symbols to the schematic. See “Creating New
LineSim Schematics”.

Verify the stackup layer thicknesses and material properties.

• Select Edit > Stackup > Edit. See “Creating and Editing Stackups” on
page 353.
b. Assign IC models to channel transmitters and receivers.
You can use any type of model supported by interactive SI simulation, including
SPICE. See “Selecting Models” - LineSim or “Setting Up Boards for Signal-
Integrity Simulation” - BoardSim.
c. Set IC model input/output modes.
For bidirectional IC buffers, interactively set the transmitter pin to the output
direction and set the receiver pin to the input direction. If you include crosstalk
during channel analysis, also do this on the aggressor nets.
Crosstalk analysis does not automatically run round robin simulations for victim or
aggressor channels with more than one transmitter. To see the effects of both far-end
crosstalk (FEXT) and near-end crosstalk (NEXT) on the channel analysis, transmit
the signal in both directions on aggressor nets. To run FastEye channel analysis with
different victim/aggressor transmitter pins set to output mode, manually
enable/disable the appropriate model pins and run separate analyses.
d. Optionally, set up signal net termination.
See “Optimizing Termination with the Terminator Wizard” on page 945.

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3. Set up signal-integrity simulation options, such as crosstalk threshold and lossy

transmission line modeling. See “Enabling SI Simulation Options” on page 536.
Requirement: In BoardSim, set the crosstalk threshold before opening the FastEye
Channel Analyzer wizard. You cannot change the crosstalk threshold from within the
wizard.
4. If you are using BoardSim, select the net to simulate. See “Selecting Nets for SI
Analysis”.
5. Set up FastEye channel analysis options and simulate.
a. Click Run FastEye Channel Analysis or select Simulate SI > Run FastEye
Channel Analysis. The FastEye Channel Analyzer wizard opens.
b. Perform the steps in the wizard. Read the wizard page text and click Help for
additional information.
c. Optionally, save analog channel characterization files for future analyses from the
Channel Characterization Dialog Box. These files are stored in memory, but are
discarded when you close the wizard. Note that crosstalk files are automatically
stored to disk.
d. When done setting values in the wizard, click Save & Run.
The wizard remains open after analysis completes, so you can re-run analysis for a
different channel with the same settings or for the same channel with different settings.
6. View results.
Display eye density plots or bit error rate plots in the HyperLynx SI Eye Density
Viewer. BER plots help identify valid data sampling locations by reporting BER as a
function of the sampling location across the unit interval (UI, same as bit interval) and
voltage. The color of the contour indicates its BER.
Display bathtub curves in the Bathtub Chart Dialog Box. Use this dialog box to display
and document bathtub curves. Bathtub curves help identify valid data sampling
locations by reporting the bit error rate (BER) as a function of the sampling location
across the unit interval (UI, same as bit interval) at several voltage offsets.
Display the Statistical Contour Chart Dialog Box. Use this dialog box to display a nested
series of eye opening contours and their bit error rate (BER). The color of the contour
indicates its BER. Like bathtub curves, statistical contours indicate the quality of
sampling locations across the unit interval (UI, same as bit interval). An advantage of
statistical contours over bathtub curves is that the inner-eye contours display both
sampling time and voltage information.
You can use the View buttons on the FastEye Channel Analyzer - View Analysis
Results Page to re-open dialog boxes that display results. The results are kept in memory
until you close the wizard or run a new analysis.

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FastEye Channel Analysis QuickStart

Related Topics
“FastEye Channel Analysis Overview” on page 635
“Wizard Table of Contents Pane” on page 1410
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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FastEye Channel Analysis Overview

FastEye Channel Analysis Overview

FastEye channel analysis is based on frequency-domain analytical modeling and simulation
methods that are valid only for nets, or channels, with linear or nearly linear behavior.

As the name implies, FastEye channel analysis runs much faster than standard-eye-diagram
simulations when simulating many bits. In fact, FastEye channel analysis runs so fast that in
some cases an overnight analysis can produce results approaching (in statistical accuracy) those
recorded at a test bench using real design hardware and a BER (bit error rate) tester. This
capability is needed by signaling protocols that require low MTBF.

However, FastEye channel analysis does not always run more quickly than standard-eye
diagrams. The time required to check channel linearity and create complex-pole models can
take several minutes, which is comparable to running a standard-eye diagram with relatively
few bits. For an introduction to standard-eye diagrams, see “About Eye Diagram Analysis” on
page 571.

This topic contains the following:

• “FastEye Channel Analysis Simulation Flow” on page 635

• “Checking Channels for Linear and Time-Invariant Behavior” on page 642
• “Worst-Case Bit Patterns Overview” on page 643
• “Model Channel Frequency Response with Complex-Pole Models” on page 644
• “Bit Sequence for Automatic Channel Characterization” on page 645

Related Topics
“Simulating Signal Integrity with the Oscilloscope” on page 533
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

FastEye Channel Analysis Simulation Flow

Figure 14-2 shows the main simulation steps and Table 14-1 on page 636 describes them.

Figure 14-3 shows the crosstalk simulation steps and Table 14-2 on page 640 describes them.

Requirement: The Crosstalk license is required to:

• Enable crosstalk and differential-pair simulation in BoardSim.

• Create coupling regions in LineSim.

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FastEye Channel Analysis Overview

Figure 14-2. FastEye Channel Analysis Simulation Block Diagram - Main Flow

Table 14-1. FastEye Channel Analysis Simulation Block Diagram - Main Flow
Item Description
Create new analog channel Choose Yes:
characterization file? • To automatically create a new analog channel
characterization file.
• If you changed the channel topology, such as editing stackup
layer properties, or probe location.

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Table 14-1. FastEye Channel Analysis Simulation Block Diagram - Main Flow
Item Description
Include crosstalk from Optionally, choose Yes to take into account the response at the
aggressors? victim receiver from crosstalk caused by aggressor nets driving a
step transition. The FastEye wizard can either automatically
create the crosstalk files or use crosstalk files that you created by
measuring PCB hardware.
Channel topography Set of physical elements that implement the channel. This
includes trace segments, layer stackup, signal vias, and so on.
Tx/Rx analog models IC models representing the transmitter analog back end and the
receiver analog front end.

You can use many the types of models supported by interactive

SI simulation, including SPICE. See “Selecting Models” -
LineSim or “Setting Up Boards for Signal-Integrity Simulation”
- BoardSim.
IC model input/output For bidirectional IC buffers, interactively set the transmitter pin
settings to the output direction and set the receiver pin to the input
direction. If you include crosstalk during channel analysis, also
do this on the aggressor nets.

Crosstalk analysis does not automatically run round robin

simulations for victim or aggressor channels with more than one
transmitter. To see the effects of both far-end crosstalk (FEXT)
and near-end crosstalk (NEXT) on the channel analysis, transmit
the signal in both directions on aggressor nets. To run FastEye
channel analysis with different victim/aggressor transmitter pins
set to output mode, manually enable/disable the appropriate
model pins and run separate analyses.
Analog channel Run simulation to create a fitted-poles file representing the
characterization analog channel and optionally the crosstalk effects from
aggressor nets.

Specify characterization properties with the FastEye Channel

Analyzer - Set Up Channel Characterizations Page and Channel
Characterization Dialog Box.
Saved file created by wizard The wizard automatically creates the analog channel
characterization file when you run analysis to completion. You
can also manually create the file from the Channel
Characterization Dialog Box. In both cases, the file is in memory
only unless you manually save it to disk.

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FastEye Channel Analysis Overview

Table 14-1. FastEye Channel Analysis Simulation Block Diagram - Main Flow
Item Description
Analog channel If you prefer to characterize channels only in the frequency
characterization in frequency domain, you can provide an S-parameter file to represent the
domain analog channel characterization.

Check the model quality before loading the file. See “Checking
S-Parameter Model Quality” on page 1082.

You might create the S-parameter model by measuring PCB

hardware or by exporting a BoardSim or LineSim net as an S-
parameter model. See “Exporting Nets to S-Parameter Models”
on page 1152.
Go to crosstalk flow See “From main flow” symbol in Figure 14-3 on page 640.
Fitted-poles file New or previously-saved fitted-poles file created by the wizard.

This file represents the analog channel characterization as

network parameter data in fitted-poles format. See “About
Touchstone and Fitted-Poles Models” on page 1066.

The file is in memory only unless you manually save it to disk

from the Channel Characterization Dialog Box.
S-parameter file See Analog channel characterization in frequency domain.

This file represents the analog channel characterization as

network parameter data in Touchstone format. See “About
Touchstone and Fitted-Poles Models” on page 1066.
Analog channel Fitted-poles or S-parameter file that represents the analog
characterization file channel characterization.

FastEye channel analysis automatically combines the analog

channel characterization files with the optional Crosstalk files.
From crosstalk flow See “Go to main flow” symbol in Figure 14-3 on page 640.
Stimulus, report types, and Options you set in various wizard pages.
other wizard settings
FastEye channel analysis The simulation engine.

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Table 14-1. FastEye Channel Analysis Simulation Block Diagram - Main Flow
Item Description
Crosstalk files Files representing the crosstalk measured at the receiver of the
selected/victim net and caused by an aggressor driving a step
transition.

There is a separate file for each aggressor. To see the effects of

both far-end crosstalk (FEXT) and near-end crosstalk (NEXT)
on the channel analysis, transmit the signal in both directions on
aggressor nets.

FastEye channel analysis automatically combines the crosstalk

files with the Analog channel characterization file.
Eye density and BER plots Statistical simulation results.
Waveforms Waveform simulation results.
Process plots Format simulation results in useful ways.
Process waveforms Format simulation results in a useful way.
BER plot bit error rate (BER) displayed in the HyperLynx SI Eye Density
Viewer.

BER plots help identify valid data sampling locations by

reporting BER as a function of the sampling location across the
unit interval (UI, same as bit interval) and voltage. The color of
the contour indicates its BER.
Statistical contours bit error rate (BER) displayed in the Statistical Contour Chart
Dialog Box.
Bathtub curves bathtub curve displayed in the Bathtub Chart Dialog Box.
Eye diagram eye diagram displayed in the FastEye Viewer.
Synthesized taps Optimum decision-feedback equalization (DFE) tap weight
values that you can save to a file.
Worst-case bit stimulus Bit values that close the eye the most.

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FastEye Channel Analysis Overview

Figure 14-3. FastEye Channel Analysis Simulation Block Diagram - Crosstalk

Flow

Table 14-2. FastEye Channel Analysis Simulation Block Diagram - Crosstalk

Flow
Item Description
From main flow See “Go to crosstalk flow” symbol in Figure 14-2 on page 636.
Create new crosstalk files? Choose Yes:
• To automatically create new crosstalk files.
• If you changed the channel topology, such as editing stackup
layer properties, or enable different transmitter pins on
aggressor nets.
Saved victim receiver Saved files containing the response at the victim receiver from
responses to aggressor nets crosstalk caused by aggressor nets driving a step transition.

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Table 14-2. FastEye Channel Analysis Simulation Block Diagram - Crosstalk

Flow (cont.)
Item Description
Crosstalk simulation Measure the response at the victim receiver from crosstalk
caused by aggressor nets driving a step transition.

Select aggressor(s) on the FastEye Channel Analyzer - Set Up

Channel Characterizations Page.
Channel topography Set of physical elements that implement the channel. This
includes trace segments, layer stackup, signal vias, and so on.
Tx/Rx analog models IC models representing the transmitter analog back end and the
receiver analog front end.

You can use many of the types of models supported by

interactive SI simulation, including SPICE. See “Selecting
Models” - LineSim or “Setting Up Boards for Signal-Integrity
Simulation” - BoardSim.
Selected aggressor nets Use the FastEye Channel Analyzer - Set Up Channel
Characterizations Page to select the aggressor nets to include in
the Crosstalk simulation.
IC model input/output For bidirectional IC buffers, interactively set the transmitter pin
settings to the output direction and set the receiver pin to the input
direction. If you include crosstalk during channel analysis, also
do this on the aggressor nets.

Crosstalk analysis does not automatically run round robin

simulations for victim or aggressor channels with more than one
transmitter. To see the effects of both far-end crosstalk (FEXT)
and near-end crosstalk (NEXT) on the channel analysis, transmit
the signal in both directions on aggressor nets. To run FastEye
channel analysis with different victim/aggressor transmitter pins
set to output mode, manually enable/disable the appropriate
model pins and run separate analyses.
Crosstalk settings Set up crosstalk modeling. See “Enabling SI Simulation
Options” on page 536.

Requirement: In BoardSim, set the crosstalk threshold before

opening the FastEye Channel Analyzer wizard. You cannot
change the crosstalk threshold from within the wizard.

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Table 14-2. FastEye Channel Analysis Simulation Block Diagram - Crosstalk

Flow (cont.)
Item Description
.LIS files Waveform file in .LIS format that is created by any of the
following:
• FastEye crosstalk simulation. The file is in memory only
unless you manually save it to disk from the Channel
Characterization Dialog Box.
• HyperLynx oscilloscope
• SPICE simulation
Fitted-poles files Network parameter data in fitted-poles (.PLS) format. See
“About Touchstone and Fitted-Poles Models” on page 1066.
S-parameter files Network parameter data in Touchstone format. See “About
Touchstone and Fitted-Poles Models” on page 1066.

If you prefer to characterize channels only in the frequency

domain, you can provide an S-parameter file to represent the
crosstalk between the selected/victim and aggressor channels.
You might create the S-parameter model by measuring PCB
hardware.

Check the model quality before loading the file. See “Checking
S-Parameter Model Quality” on page 1082.
Crosstalk files Files representing the crosstalk measured at the receiver of the
selected/victim net and caused by an aggressor driving a step
transition.

There is a separate file for each aggressor. To see the effects of

both far-end crosstalk (FEXT) and near-end crosstalk (NEXT)
on the channel analysis, transmit the signal in both directions on
aggressor nets.

FastEye channel analysis automatically combines the crosstalk

files with the Analog channel characterization file.
Go to main flow See “From crosstalk flow” symbol in Figure 14-2 on page 636.

Checking Channels for Linear and Time-Invariant

Behavior
FastEye channel analysis technology supports channels with linear and time-invariant (LTI)
behavior, which consists of the following characteristics:

• Driver output buffer can have a non-linear I-V characteristic, but not a large non-linear
capacitance characteristic

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• Driver output buffer must have a unique and unchanging response to any given stimulus
sequence
• Driver output buffer can have asymmetric rise and fall transitions, as long as you do any
of the following in the Channel Characterization Dialog Box:
o If you characterize the channel automatically, enable PRBS in the Characterization
type area.
o If you characterize the channel manually and provide step/pulse waveforms, enable
Pulse and step waveforms (recommended).
o If you characterize the channel manually, provide PRBS waveforms.
• Interconnect between driver and receiver must be linear, which is not a problem with
passive interconnects (metal, dielectric)
• The receiver input stage must present a linear load (for example, no diode clamping)
If the channel has LTI behavior (“linear” from now on), FastEye channel analysis results match
or nearly match standard (time domain) eye diagram results for the same channel.

FastEye channel analysis checks the linearity of the channel by comparing the energy in the
actual pulse response to the energy in the calculated pulse response, where the calculated pulse
response is the difference between the actual step response and the actual step response negated
and delayed.

Non-linear channel behavior is usually produced by the attached ICs and not the
interconnections, which are usually passive. The behavior of the driver usually affects channel
linearity most. The I/V curve in the operation region must be linear or have exactly the same
response to any given stimulus sequence.

Tip: Even if you use non-linear driver/receiver models, you might be able to use FastEye
channel analysis to evaluate the intrinsic properties of the bare channel by temporarily
assigning linear IC models. This capability enables you to see whether changing the net
topology or interconnection structures, such as vias, opens or closes the eye.

Worst-Case Bit Patterns Overview

The FastEye Channel Analyzer can create the worst-case bit sequence that closes the eye the
most. However, if the buffer is non-linear, the worst-case bit pattern may not close the eye the
most in absolute terms.

If the driver or receiver models are not sufficiently linear to produce accurate results in FastEye
channel analysis, you can still use the worst-case bit pattern to run standard-eye diagram
simulation in the oscilloscope. You can also use the worst-case bit pattern as stimulus for

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simulators and analysis software not supported by the oscilloscope. You are responsible for
reformatting the worst-case bit pattern file for use by other simulators and analysis software.

The FastEye Channel Analyzer can create the following types of worst-case bit patterns:

• Pseudo-random bit sequence (PRBS)—Sequence of bits

• 8B/10B—Sequence of characters that complies with the encoding protocol
You can calculate the length of a worst-case bit pattern using this formula:

<checks_per_UI> x ISI x 2
Where:

• <checks_per_UI> — the number of locations in the bit interval at which a donor worst-
case bit sequence is determined. The FastEye Channel Analyzer calculates the final
sequence from the several donor sequences. See “Checks Per UI” on page 1610.
• ISI — the inter-symbol interference history length
• 2 — indicates the overall sequence consists of the worst-case sequence and an inverted
version of it
You specify the value of these parameters in the FastEye Channel Analyzer - Define Stimulus
Page.

Model Channel Frequency Response with Complex-Pole

Models
FastEye channel analysis uses channel-response waveforms to create a model of the channel
frequency-domain behavior. A proprietary complex-pole fitting (CPF) algorithm creates a
complex-pole model, in the pole-residue form, to represent the frequency dependency of the
channel.

FastEye channel analysis uses the complex-pole model to create the FastEye diagram and to
display the results in the time domain. The complex-pole model exists in memory and is not
stored as an external file.

CPF has the following advantages over alternative simulation technologies, such as convolution
and equivalent circuits:

• Simulates much faster

• Is more accurate—Especially for long simulations, where errors accumulate due to
truncation of unit step and pulse responses (also known as local truncation error)
• Is more stable— Circuit passivity may be violated by truncation and (possibly) coarse
time step of convolution and equivalent circuit methods

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• Automatically enforces causality

FastEye channel analysis also supports convolution. For a comparison of the strengths of CPF
and convolution, see Table 33-22 on page 1603.

Bit Sequence for Automatic Channel Characterization

If you enable the Automatically characterize channel and PRBS options on the Channel
Characterization Dialog Box, FastEye channel extraction automatically defines the bit sequence
in Figure 14-4. This overall bit sequence consists of the following parts:

• Warmup bit sequence — The number of bits matches the value you specify in the
Number of warmup bits before the Tx/channel are stable box. The bit sequence consists
of the last n bits of the PRBS bit sequence plus zero or more full PRBS bit sequences.
FastEye channel extraction automatically chooses a PRBS bit sequence with a bit order
that is longer than the ISI for the channel. Zero full PRBS bit sequences are needed
when the number of skipped bits is less than the full PRBS bit sequence length.
• PRBS bit sequence — FastEye channel extraction automatically chooses a PRBS bit
sequence with a bit order that is longer than the channel ISI, and then applies it twice.

Figure 14-4. Bit Sequence for Automatic Channel Characterization

FastEye Diagram Measurements

Use the FastEye Viewer to display and measure FastEye diagrams created by the FastEye
Channel Analyzer. The FastEye Viewer is a special version of the Digital Oscilloscope that
contains only the features needed to display and measure FastEye diagrams.

This topic contains the following:

• “Measuring FastEye Diagrams” on page 645

• “Zooming and Examining FastEye Diagrams” on page 649

Related Topics
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

Measuring FastEye Diagrams

You can use automatic and manual methods to measure FastEye diagrams.

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This topic contains the following:

• “Measuring FastEye Diagrams Automatically” on page 646

• “Measuring FastEye Diagrams Manually” on page 647
• “Adding an Eye Mask to FastEye Diagrams” on page 648

Measuring FastEye Diagrams Automatically

The FastEye Channel Analyzer automatically reports FastEye diagram measurements.

Procedure
1. In the Show area, select the waveform to measure from the Pins spreadsheet.
Waveform names correspond to the probe you specified in the FastEye Channel
Analyzer - Set Up Channel Characterizations Page
If you re-run FastEye channel analysis on the same pin, a new row at the bottom of the
Pins spreadsheet corresponds to the latest results. A value in parentheses is appended to
the probe name. For example, if the differential probe name for the first simulation is
named “U2.2_(at_pin)_U2.1_(at_pin)”, the probe name for the second simulation is
“U2.2_(at_pin)_U2.1_(at_pin)(2)”.
2. Measurement results are displayed near the lower-left corner of the dialog box.
To copy measurement results to the Windows clipboard, select the text and press
Ctrl+C.
See also: “About Automatic FastEye Diagram Measurements” on page 646

About Automatic FastEye Diagram Measurements

Maximum eye opening—The maximum distance in voltage between the top and bottom sides
of the inner boundary of the eye diagram. See Figure 14-5.

Figure 14-5. Eye-Diagram Height

Eye height measurements do not include a guardband. By contrast, test bench oscilloscopes may
apply a guardband, such as three sigma.

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Eye width—The distance in time between the right and left sides of the inner boundary of the
eye diagram, as measured at the midpoint voltage, which is halfway between V_low and
V_high. See Figure 14-6. For information about V_low and V_high, see Figure 11-10 on
page 587.

Figure 14-6. Eye-Diagram Width

Eye width is reported in units of both time and unit interval (UI). You specify the UI length in
the FastEye Channel Analyzer - Define Stimulus Page.

Eye width measurements do not include a guardband. By contrast, test bench oscilloscopes may
apply a guardband, such as three sigma.

Period that makes the smallest eye opening—Identifies which period, in the sequence of
periods that make up the overall simulation, has the narrowest eye width. This information
enables you to examine the waveforms and bit stimulus preceding the named period. You can
display detailed FastEye waveforms by enabling the All traces option on the FastEye Channel
Analyzer - View Analysis Results Page (prior to analysis) and enabling standard operation in
the FastEye Channel Analyzer (when analysis completes).

To calculate the offset in the simulation for the start of the period with the smallest eye opening,
use the following expression: (period # - 1) * bit interval. The period number starts at 1.

Example: If the period # is 10 and the bit interval is 3.3 ns, then (10 - 1) * 3.3 ns = 29.7 ns.

Measuring FastEye Diagrams Manually

You can perform precise time, voltage, current, and slew-rate measurements from the FastEye
Channel Analyzer screen using measurement crosshairs or simply by observing pointer position
information.

This topic contains the following:

• “Using Measurement Crosshairs” on page 648

• “Performing Measurements with the Mouse Pointer” on page 648

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FastEye Diagram Measurements

Using Measurement Crosshairs

You can place measurement crosshairs anywhere on the FastEye Channel Analyzer screen.
When you place two measurement crosshairs, the viewer automatically displays delta time
information.

Procedure
1. Click on the screen where you want to make a measurement.
Result: The first measurement crosshairs appears and its voltage and time appear in the
Cursors area next to Pt1.
2. To measure a delta voltage or delta time, click on the screen where you want to make a
second measurement.
Result: The second measurement crosshairs appears. Its voltage and time appear in the
Cursors area next to Pt2. The time and voltage differences between the two
measurement crosshairs appear next to Delta V, Delta T, and Slope.
3. To turn off the measurement crosshairs, do one of the following:
• Click over the screen a third time.
• Click Erase. Clicking Erase also erases the FastEye data.

Performing Measurements with the Mouse Pointer

When you position the pointer over the FastEye Viewer screen, its voltage and time position is
displayed in the Cursor field in the Cursors area. You can use the pointer position as an
alternative method to measurement crosshairs to perform quick measurements. Simply point to
the waveform, hold the mouse steady, and then look at the Cursor field.

Adding an Eye Mask to FastEye Diagrams

The FastEye Viewer enables you to overlay the FastEye diagram with a mask that displays the
“keep out” regions the eye diagram must avoid.

Procedure
• In the Show area, select the Eye mask check box.
You can select an eye mask from a library of popular communication protocols, or create your
own eye mask and add it to the library.

See also: “Editing Eye Mask Properties” on page 564

If the eye mask position is not centered within the bit interval, you can do any of the following:

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• Click the Adjust Mask button in the Cursors area, and then drag the eye mask to the
new position. The new timing offset values are automatically written to the Eye Mask
tab on the Configure Eye Diagram dialog box.
• Type the exact offset into the eye mask boxes on the Eye Mask tab on the Configure Eye
Diagram dialog box.

Zooming and Examining FastEye Diagrams

You can use any of the controls in Table 14-3 to help examine FastEye diagrams.

Table 14-3. Examination Controls for FastEye Diagrams

Control Type Procedure
Zoom Click Zoom , position the mouse pointer over one corner of the zoom box
you want to create, drag to define the other corner, and then release the mouse
button.
Fit to window Click Fit to Window
Voltage offset Type a value in volts in the Vertical Position box or click an arrow next to the
box.

Use the vertical position option to shift the waveforms, and the 0.0 V ground
position marker, in the main screen up or down relative to the grid. By contrast,
the vertical scroll bar moves the grids, waveforms, and green ground marker up
and down together.

The vertical position controls create a voltage offset by adding or subtracting

voltage to or from the data. When changing the vertical position, the grids
remain stationary while the waveforms and ground marker move up and down.

The available vertical position range is plus/minus five divisions with a

precision of 1/10 division.
Voltage scale Type a value in millivolts per division in the Vertical Scale box or click an
arrow next to the box.
Time offset Click an arrow next to the Horizontal Delay box.

Use this control to center the eye in the screen.

The available horizontal delay range is 0ns to 100.000ns, with a precision of

1ns.
Time scale Click an arrow next to the Horizontal Scale box.
Scroll Drag the scroll bar to the right or bottom of the screen to move the grids, eye
diagram, and eye mask (if it is enabled) as a group.

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Table 14-3. Examination Controls for FastEye Diagrams

Control Type Procedure
Settings Select or clear the Readout text check box.
readout
The horizontal scale, vertical scale, horizontal delay, and vertical offset values
are displayed near the top of the screen. Disable the readout to reduce clutter.

Related Topics
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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Simulating SI for Entire Boards or Multiple
Nets

Use generic batch simulation to evaluate signal-integrity for an entire board or group of nets.
This capability enables you to screen an entire board for problems, simulate in detail a group of
critical nets, or verify that design revisions have not introduced problems on critical nets.

This topic contains the following:

• “Batch Simulation Flow” on page 651

• “Getting to Know Batch Simulation” on page 652
• “Preparing the Board for Batch Simulation” on page 655
• “Running the Batch Simulation Wizard” on page 663
• “Viewing Batch SI Simulation Reports” on page 663
• “Reference Information for Batch Simulation” on page 683
• “Batch Simulation Wizard Dialog Box Help” on page 723

Related Topics
“About Importing Constraints from CES” on page 721

“Simulating DDRx Memory Interfaces” on page 773

Batch Simulation Flow

You can use batch simulation to evaluate the board and report nets with excessive delay,
overshoot/undershoot, crosstalk, radiated emissions (EMC), poor termination, and so on. All
results are recorded textually in report files. With this information, you can identify the nets you
want to investigate further.

Running batch simulation includes the following basic steps:

1. “Getting to Know Batch Simulation” on page 652—Understand the following:

• Quick analysis and detailed simulation options
• Ways to use batch simulation

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• Restrictions
2. “Preparing the Board for Batch Simulation” on page 655—Set up the board for the
most-accurate batch simulation results.
3. “Running the Batch Simulation Wizard” on page 663—Open the batch simulation
wizard, select options, and start batch simulation.
4. “Viewing Batch SI Simulation Reports” on page 663—Review the content and
formatting of the batch simulation report files.

Getting to Know Batch Simulation

Because batch simulation can take multiple hours to run on a large board, understanding its
capabilities and limitations can help to use your time efficiently.

This topic contains the following:

• “Quick Analysis and Detailed Simulation Options” on page 652

• “Ways to Use Batch Simulation” on page 653
• “Generic Batch Simulation Restrictions” on page 654
• “Driver Logic State Switching” on page 655

Quick Analysis and Detailed Simulation Options

Batch simulation offers two simulation methods: quick analysis and detailed simulation. You
can use the quick analysis and detailed simulation options together or independently, so you can
use them in a way that fits your needs.

Table 15-1 compares the quick analysis and detailed simulation options:

Table 15-1. Batch Simulation - Comparing Quick Analysis and Detailed

Simulation
Quick analysis Detailed simulation
Accuracy Approximate Same as interactive simulation

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Table 15-1. Batch Simulation - Comparing Quick Analysis and Detailed

Simulation (cont.)
Run time Short Long

On some very large boards quick Detailed simulation runs the same
analysis may take multiple hours to kinds of simulations you run
run, but on average-sized boards interactively using the oscilloscope
the run time is usually much or spectrum analyzer, and it may
shorter. run for multiple hours for large
numbers of nets.
The various ERROR FLAGS
sections in the standard report file
prominently mark nets that violate
the constraints. This enables you to
scan the standard report file for nets
you might want to further
investigate with detailed
simulation.
IC model setup Optional Required

Ways to Use Batch Simulation

Because batch simulation can simulate the entire board, you can use the following strategies to
find problems and possibly guide corrective efforts using interactive simulation:

• “Using Batch Simulation as an Initial Screening Tool” on page 653

• “Using Batch Simulation as a Sanity Check” on page 654
• “Using Batch Simulation as a Regression Test” on page 654

Using Batch Simulation as an Initial Screening Tool

If you are unsure which nets on the board to simulate, or where on the board signal integrity or
crosstalk problems may exist, run quick analysis to scan the entire board. Quick analysis
generates a report containing termination problems/solutions and a list of nets sorted by
estimated crosstalk strengths. By reviewing the report, you can identify the problem nets to
further investigate using detailed simulation.

Tip: It may be more efficient to interactively simulate known problem nets because batch
simulation reports problems without discrimination. It does not know which nets are
critical and will report all errors.

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Using Batch Simulation as a Sanity Check

If you already know which nets to simulate, and already ran interactive simulations on them,
you may still want to run quick analysis as a final automated check.

Using Batch Simulation as a Regression Test

Suppose that you solved all the critical high-speed problems on the design, but you or others
have revised the board layout to fix another problem, such as mechanical, logical, or cost
reduction. In this case, you might run generic batch simulation to see if the new layout has
introduced problems on any of the critical nets.

Generic Batch Simulation Restrictions

• Batch simulation cannot simulate nets with SPICE or S-parameter models.
• Detailed simulation is not performed on nets that have IC pins with no model assigned to
them.
See also: “Detailed Analysis Rules for Assigning IC Models and Enabling IC Driver
Pins” on page 659, “Editing Batch Simulation Audit and Reporting Options” on
page 742
• Automatic flight-time compensation is available for IC pins with test fixture
information, such as Vref and Cref.
Batch simulation reports flight time for a differential pair as one of the following:
o Both pins as a differential pair—The IBIS model contains the Rref_diff sub-
keyword but not the Cref_diff sub-keyword. If the model contains Cref_diff, it must
be commented out to enable differential compensated flight time measurements. If
the required Rref_diff sub-keyword and the optional Rref or Cref sub-keywords are
present, they are all applied to both signals in the differential pair. See “Modeling
Requirements for Compensated Flight Time Measurements on Differential Pairs” on
page 589.
o Each pin as a single-ended signal—The IBIS model either does not contain the
Rref_diff sub-keyword or contains both Rref_diff and Cref_diff sub-keywords.
• Licensing requirements:
o The BoardSim Crosstalk license is required to run crosstalk simulation.
o The BoardSim EMC license is required to run EMC simulation.
o The BoardSim Lossy license is required to run lossy simulation.
o The BoardSim Via Models license is required to run advanced via simulation.

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• EMC is not simulated for MultiBoard projects because MultiBoard projects do not
contain board-to-board geometric information.
• Nets with multiple terminators are not analyzed by the Terminator Wizard running
within batch simulation. This means Quick Analysis options using the Terminator
Wizard do not apply to nets with multiple terminators. You specify Quick Analysis
options on the Overview page of the batch simulation Wizard.
If you interactively run the Terminator Wizard on the net, you can select the specific terminator
to analyze.

Driver Logic State Switching

When running interactive simulation, you use the Assign Models dialog box to specify driver
and receiver ICs on nets. When running batch simulation, however, batch simulation
automatically specifies the logic state of driver and receiver ICs on all simulated nets in the
following ways:

• Signal integrity—The driver IC is automatically toggled.

If you enable the high-accuracy simulation mode, which includes coupled traces, driver
ICs on aggressor nets are automatically stuck low.
• Crosstalk simulations—The driver ICs on aggressor nets are automatically toggled.
The driver ICs on victim nets are automatically stuck low or high (or both—your
choice).
• EMC simulations—The driver is automatically toggled at the central frequency and
duty cycle you specify.
See also: “Driver IC Behavior During Batch Crosstalk Simulation” on page 718

Related Topics
“Batch Simulation Flow” on page 651

Preparing the Board for Batch Simulation

The set up for batch simulation depends on which batch simulation features you plan to use. For
example if you plan to run only quick analysis, the only required preparation is to verify that
BoardSim recognizes all power-supply nets.

This topic contains the following:

1. “Verifying BoardSim Recognizes All Power-Supply Nets” on page 656

2. “Editing Crosstalk Threshold Voltage” on page 656 (optional for quick analysis)
3. “Assigning IC Models” on page 657 (optional for quick analysis)

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4. “Enabling IC Driver Pins for Detailed Crosstalk Simulation” on page 661

Requirement: The BoardSim Crosstalk license is required to run crosstalk simulation.

Verifying BoardSim Recognizes All Power-Supply Nets

Verify that none of the power-supply nets on the board are identified as signal nets. If nets look
too complicated or seem to connect to incorrect nets, you probably have undetected power-
supply nets. If a power-supply net is incorrectly identified as a signal net and it connects to
many other nets through components such as resistors and capacitors, batch simulation run time
increases substantially.

See also: “Editing Power-Supply Nets” on page 281

Editing Crosstalk Threshold Voltage

When BoardSim runs crosstalk simulation, or any simulation involving coupled/aggressor nets,
it must judge which other nets are coupled with the selected victim net. As described in “How
BoardSim Crosstalk Finds Aggressor Nets” on page 1220, the interactive crosstalk threshold
voltage determines which aggressor nets appear in the board viewer and the Assign Models
dialog box for a given selected net. If you set the interactive crosstalk threshold high, you may
see few or no aggressor nets. If you set the interactive crosstalk threshold low, you may see
many aggressors.

Tip: If you plan to interactively assign IC models, edit the crosstalk threshold for
interactive simulation so that it is the same value you will use for batch simulation.

If you set the interactive crosstalk threshold to a value larger than the batch simulation value,
some of the aggressor nets that you want to evaluate in batch simulation will not appear in the
Assign Models dialog box. Consequently, you cannot interactively assign IC models to the
aggressor nets in preparation for batch simulation, and the contribution of aggressor nets to the
victim net crosstalk is excluded.

See also: “How to Set the Crosstalk Threshold” on page 1223

Interactive Versus Batch Simulation Crosstalk Thresholds

The crosstalk threshold voltage is specified independently for interactive simulation and batch
simulation. In batch simulation, only detailed simulations for crosstalk analysis use crosstalk
thresholds.

For interactive simulation, one value is used by all nets. For batch simulation, you can specify a
unique value for each net. If you plan to use several different values during batch simulation, it
is recommended that you set the interactive value to the lowest of the batch simulation values.

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The batch simulation crosstalk threshold serves the following purposes for detailed simulations
for crosstalk analysis:

• Crosstalk limit—Batch simulation creates a warning in the report file if the amount of
induced voltage on the victim net exceeds the crosstalk threshold.
• Electrical crosstalk threshold—Batch simulation includes aggressor nets in detailed
simulations if they induce a voltage on the victim net that exceeds the crosstalk
threshold.
Batch simulation supports only electrical crosstalk thresholds. In interactive simulation, you can
choose between using electrical or geometric crosstalk thresholds, even though it is
recommended you use electrical crosstalk thresholds. Therefore, when you set the interactive
crosstalk threshold to match what you plan to use in batch simulation, be sure to choose an
electrical value rather than a geometric value.

Assigning IC Models
For quick analysis, assigning IC models improves accuracy but it is optional. If you do not
assign IC models, batch simulation uses a set of default IC properties that you can edit.

For detailed simulation, IC models must be assigned for all the nets you select for simulation,
including associated and coupled nets. If IC models are missing on coupled nets, detailed
simulation refuses to simulate the selected net and reports the condition in the report file.

This topic contains the following:

• “Assigning IC Models to Pins” on page 657

• “Methods for Quickly Assigning IC Models” on page 658
• “Importing IC Model Assignments from CES” on page 658
• “Assigning IC Models to Connectors” on page 659
• “How Batch Simulation Chooses IC Properties for Aggressor Nets” on page 659
• “Detailed Analysis Rules for Assigning IC Models and Enabling IC Driver Pins” on
page 659
• “MOD Models May Inadvertently Increase Round Robin Simulations” on page 661

Assigning IC Models to Pins

If you plan to simulate only a subset of the board nets, there is no need to assign models to all
the ICs on the board. Instead, assign models only to the nets and associated aggressor nets that
you want to simulate.

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The easiest way to assign a small number of models to pins is to interactively assign IC models
to individual pins. For your convenience, the Assign Models dialog box automatically displays
the aggressor nets for the selected victim net.

The easiest way to assign a large number of models to pins is to create a .REF file to map an IC
model to a reference designator, or to create a .QPL file to map an IC model to a part number.

You can use all model assignment methods when preparing for batch simulation. However
models assigned interactively take precedence over assignments made by .REF or .QPL files.

See also: “Interactively Selecting IC Models” on page 467, “Selecting Models and Values for
Entire Components” on page 296, “Importing Model Assignments from CES to REF Files” on
page 304

Methods for Quickly Assigning IC Models

Sometimes you are in a hurry to simulate and don’t have an exact model for a device. In these
cases, when there is no time to obtain the appropriate model from the vendor or create one
yourself, use the TECH.MOD library to get an approximate model that will get you simulating,
and—in many cases—be sufficiently accurate to give good analysis results.

If most or all of the ICs switch at the same rate, that is they have approximately the same
switching time, you may use one type of model for all ICs. In the Assign Models dialog box,
you can use the Copy and Paste All buttons to copy the IC model assignment for one pin to all
pins on the selected and associated nets.

Importing IC Model Assignments from CES

You can import component-wide IBIS .IBS and .EBD IC/module model assignments from a
CES project into the .REF automapping file.

Restrictions:

• The capability to import model assignments from CES into the REF file is unavailable
when a LineSim schematic or MultiBoard project is loaded. CES does not define
constraints for multiple-board projects.
• You cannot import the values of discrete Rs, Ls, and Cs.
If you plan to import constraints from CES into the net spreadsheets for batch simulation, you
first import model assignments from CES to the .REF automapping file. This sequence
minimizes the likelihood of CES and BoardSim disagreeing on the set of nets in the design.

See also: “Importing Model Assignments from CES to REF Files” on page 304, “Importing
Constraints from CES to the Batch Simulation Spreadsheet” on page 685

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Assigning IC Models to Connectors

Batch simulation does not simulate nets unless all pins, including connector pins, have IC
models assigned to them. To model the connector pin as electrically open, assign to it the
OPEN-CIRCUIT model from the OPEN.MOD library.

If you load a MultiBoard project, batch simulation automatically follows the net through the
connection between boards and finds IC models on the net on the other board.

How Batch Simulation Chooses IC Properties for Aggressor Nets

Table 15-2 shows how batch simulation chooses IC properties for aggressor nets:

Table 15-2. Batch Simulation - IC Properties for Aggressor Nets

Case IC properties provided by
You have assigned one output or IC model
bidirectional IC model to aggressor net
You have assigned two or more output or Fastest IC model
bidirectional IC models to aggressor net
You have assigned only input IC models to Default IC model
aggressor net
Or See also: “Editing Default IC Model
You have not assigned any IC models to Properties” on page 736
aggressor net

Requirement: Detailed simulations for crosstalk analysis require models on aggressor nets to
be assigned.

Detailed Analysis Rules for Assigning IC Models and Enabling IC

Driver Pins
Table 15-3 shows what happens when IC models are missing or enabled incorrectly when you
run detailed analysis:
Table 15-3. Batch Simulation - Missing or Incorrectly Enabled ICs
Case Detailed analysis Result
simulation type
No IC models assigned to Any No simulation and error is
victim net written to report file
Missing IC models on net Signal integrity No detailed crosstalk
simulation and error is
written to report file

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Table 15-3. Batch Simulation - Missing or Incorrectly Enabled ICs (cont.)

IC models assigned to Any If round robin (see “round
victim net, but no IC driver robin” on page 1965) is
pin is enabled disabled, no simulation and
error is written to report file

If round robin is enabled,

detailed crosstalk
simulation runs and batch
simulation automatically
enables driver pins on
victim net
No IC models assigned to Signal integrity Simulation runs—
aggressor nets aggressors are not included
Or in signal integrity
IC models assigned to simulation anyway
aggressor nets, but no IC
Signal integrity—high Simulation runs, but
driver pin is enabled on
accuracy warning is written to report
each net
file
Crosstalk Warning is written to report
file

If no aggressor net has an

enabled IC driver pin,
simulation results are 0/NA

If only some aggressor nets

have enabled IC driver pins,
crosstalk amounts may be
too low
Multiple IC drivers are Any If the IC drivers are
enabled on victim net bidirectional, three-state,
open-drain, or open-
collector, batch simulation
assumes they are
deliberately tied together (or
ganged)

If the IC drivers are NOT

bidirectional, three-state,
open-drain, or open-
collector, no simulation and
error is written to report file

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Table 15-3. Batch Simulation - Missing or Incorrectly Enabled ICs (cont.)

Multiple IC drivers are Signal integrity Simulation runs—
enabled on each aggressor aggressors are not included
net in signal integrity
simulation anyway
Signal integrity—high Simulation runs with all
accuracy aggressor drivers stuck low
simultaneously—may result
in driver conflicts
Crosstalk Simulation runs with all
aggressor drivers switching
simultaneously—may result
in driver conflicts
See also: “High-Accuracy Signal-Integrity Simulations” on page 719

MOD Models May Inadvertently Increase Round Robin

Simulations
If you enable round robin (see “round robin” on page 1965), batch simulation runs a simulation
for each .MOD model on the net because all .MOD models are bidirectional. This case may
produce unexpectedly long batch simulation run times. If it does, you might assign .MOD
models only to pins you use as bidirectional drivers.

Exception: Round robin does not treat the OPEN-CIRCUIT model from the OPEN.MOD
library as a bidirectional pin.

Enabling IC Driver Pins for Detailed Crosstalk Simulation

For each net that you want to simulate with detailed crosstalk simulation, one IC driver pin must
be enabled on the net and on its coupled nets. When batch simulation simulates a net that does
not have an enabled driver IC pin, it refuses to simulate and writes an error to the report file.

On nets with two or more bidirectional, open drain, or three-state ICs, indicate which IC drives
the net by enabling one of the IC drivers to an output mode. However enabling an IC driver is
unnecessary if either the model is output-only and does not have a high-impedance state or if the
net contains only one driver IC.

See also: “Detailed Analysis Rules for Assigning IC Models and Enabling IC Driver Pins” on
page 659

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Automatically Enabling IC Driver Pins on Selected-Victim Nets-

Round Robin
Use round robin to automatically set IC pins on selected nets (signal integrity simulation) and
victim nets (crosstalk simulation) to output mode. Round robin reduces your set up effort while
providing separate simulation results for each IC driver driving the net. However run time can
increase significantly with the number of additional simulations run by round robin.

Key round robin behaviors:

• Round robin does not automatically enable drivers on aggressor nets coupled to the
selected net.
• Round robin does not automatically enable drivers inside .EBD models.
• If you manually enable two or more IC pins on a net, round robin assumes they must be
enabled and disabled together and so does not create separate simulations for them. This
behavior supports "ganged" pins that drive simultaneously to provide extra current.
• If all drivers on the net are manually disabled, round robin includes this condition when
checking the number of simulations against the maximum number of simulations limit.
Note that the “all drivers disabled” condition is not simulated, even though it is counted
against the limit.
See also: “round robin” on page 1965, “Editing Driver and Receiver Options for Signal-
Integrity Analysis” on page 733

Manually Enabling IC Driver Pins

Use the Assign Models dialog box to manually set an IC pin to output mode. The output, output
inverted, stuck high, and stuck low states are all acceptable, because batch simulation
automatically changes the driver state on aggressor nets from driving to stuck, or vice versa,
during simulation.

After enabling IC driver pins is a good time to run interactive simulation on the selected net.
After interactive simulation, leave the driver pin in any of the Output, Output Inverted, Stuck
High, and Stuck Low states because batch simulation automatically changes output state during
simulation.

See also: “Interactively Selecting IC Models” on page 467

Related Topics
“Running the Batch Simulation Wizard” on page 663

“Getting to Know Batch Simulation” on page 652

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Running the Batch Simulation Wizard

Use the batch simulation wizard to specify the options you want to use when running batch
simulation.

To run the batch simulation wizard:

1. Run Generic Batch Simulation button .

Alternative: Simulate SI menu > Run Generic Batch Simulation.
2. Edit options and values as needed, and then click Next.
Batch simulation becomes slower as you enable more analysis options. Some wizard
pages display a fast/slow performance status bar to indicate the relative effect that
individual options have on the overall run time.
3. Repeat step 2 as needed to continue through the wizard.
4. In the last page, click Finish.

Related Topics
“Editing Primary Batch Simulation Options” on page 724

“Batch Simulation Wizard Dialog Box Help” on page 723

“Getting to Know Batch Simulation” on page 652

Viewing Batch SI Simulation Reports

Textual reports provide the results of batch SI simulation and the pre-simulation audit. The
standard report file, comma separated value (CSV) report file, native Excel XLS report file,
standard delay format (SDF) file, and audit file have different contents and formatting.

All report files are always created, except for the optional audit file. You can specify which
reports to open automatically on the Select Reporting Options wizard page.

All report files are written to the same folder and have the same base file name. By default, the
file is written to the <design> folder and has the same name as the design. See “About Design
Folder Locations” on page 1391. You can specify a different folder and file base name on the
Select Reporting Options wizard page.

This topic contains the following:

• “Standard Report” on page 664

• “CSV and XLS Reports” on page 667

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• “SDF File” on page 682

• “Audit File” on page 683

Related Topics
“Editing Batch Simulation Audit and Reporting Options” on page 742

“Batch Simulation Flow” on page 651

Standard Report
The sections included in the standard report file depend on which batch simulation options you
enabled. Table 15-4 describes all of the available sections:

Table 15-4. Batch Simulation - Format of Standard Report

Section Contents
START TIME Date and time batch simulation started.
GENERAL INFORMATION Board name, board statistics, simulation
temperature, and default IC model properties.
STACKUP Physical properties of the board stackup. If you
edited the stackup using the stackup editor,
changes are reported.
CHANGED PASSIVE-COMPONENT Manual edits you made to resistor and capacitor
VALUES values.
NEW TERMINATING COMPONENTS Quick Terminators, and their values, that you
added to the board.

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Table 15-4. Batch Simulation - Format of Standard Report (cont.)

CROSSTALK REPORT-QUICK Maximum estimated crosstalk that could occur
ANALYSIS on each net. Nets are sorted by most possible
crosstalk to least possible crosstalk.

The results for an individual net are formatted

in the following order:
1. Net name
2. List of nets electrically connected to the net
See also: “Associated Nets” on page 272
3. List of aggressor nets and their individual
contribution to crosstalk on the victim net
4. Summed crosstalk voltage from the two
strongest aggressors on victim net
5. If the summed crosstalk voltage exceeds the
crosstalk threshold value, a warning is
written
See also: “Preparing the Board for Batch
Simulation” on page 655

Crosstalk estimates are generally conservative

and, for specific situations, may be in error by a
factor of three or four. This conservatism
attempts to ensure that the Quick Crosstalk
Analysis does not miss any nets that might
experience significant crosstalk.

While the absolute value of the crosstalk

estimates may not be completely accurate, the
ranking of the nets in the report is usually quite
meaningful. The ranked crosstalk estimates can
help you efficiently direct your detailed
simulation investigation.

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Table 15-4. Batch Simulation - Format of Standard Report (cont.)

NET INFORMATION Names of nets electrically connected to the net.

See also: “Associated Nets” on page 272.

Names of nets coupled to the selected net

during crosstalk simulation.

Names of nets coupled to the selected net

during high-accuracy signal integrity
simulation.

Signal integrity simulation results for the

selected net.

See also: “Contents of Signal-Integrity

Simulation Results Tables” on page 716

The longest simulation time required for the

net. Indicates the longest simulation time
required for the net. Extremely long simulation
times, such as hundreds of nanoseconds, may
indicate an IC model problem.

EMC simulation results for the selected net.

Counts of various elements that comprise the
selected net.

Interconnection statistics for the selected net,

including total delay, impedance, inductance,
capacitance, and resistance. Warning for
completely unrouted nets. Statistics for
associated nets are listed separately.

Signal integrity statistics for the selected net,

including total receiver capacitance, effective
impedance, and termination information.
Detailed termination violations for each net.

Nets appear only once. A net might appear only

in the associated net list for another net.

Power-supply nets are not listed.

END TIME Date and time batch simulation finished.

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CSV and XLS Reports

CSV and XLS reports provide many more details than Standard Reports. CSV reports, in
comma-separated value ASCII format, enable you to parse detailed batch simulation results
with external scripts. XLS reports, in binary format, can highlight errors in red if you enable a
formatting option.

Opening the CSV or XLS file with Microsoft Excel enables you to sort the data by any column,
such as the following:

• By maximum delay, crosstalk, overshoot, and so on

• In descending order on any of the violations columns. This brings all of the nets with
violations to the top of the list.

Note
Columns for margins, limits, and thresholds are excluded from the spreadsheet when you
disable the Report limits and margins option on the Select Audit and Reporting Options
page. See “Opening Reports Automatically” on page 743.

Table 15-5 shows the contents of the CSV and XLS reports, in alphabetic column order.

Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically

Column Description
Comments Various status and warning messages.

The "** Warning **" and "** Warning(Severe)

**" message can help identify set up problems.

Contains differential crossover measurement

results for receivers with IBIS models with
Vcross_high and Vcross_low sub-parameters.
Coupled Net(s) List of aggressor nets coupled to the victim net.
Diff Meas [Yes/No] Yes indicates the receiver has a differential
model and most measurements are based on
differential waveforms. See “Differential
Measurements in Batch Simulation” on
page 682.

Note that single-ended waveforms are used for

the following types of measurements:
• Static and dynamic rail overshoot
• Differential crossover for receivers with IBIS
models with Vcross_low and Vcross_high
sub-parameters. The Comments column
contains crossover results.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Driver Meas [Pin/Die] The probe location at the driver pin. The value is
“at pin” unless an IBIS model is assigned to the
component pin and the [Timing_location] sub-
parameter value is Die.

This information can be useful if you are trying

to correlate between detailed batch simulation
results and interactive simulation results.
Driver Model File Name of the driver model library file.

The file is located in a model folder that you

specify with the Select Directories for IC-Model
Files Dialog Box.
Driver Model Name Name of the driver model. For an IBIS model,
the value comes from the [Model] keyword.
Driver(s) [RefDes.Pin] Reference designator and pin for the driver.
Fall Closest Ringback [mV] Maximum ringback voltage measured at the
receiver. See Min. Fall Ringback.

In Figure 15-17 on page 710, the Violation label

indicates the closest measured ringback voltage.
Fall Closest Ringback Limit [mV] Value of the Min. Fall Ringback constraint you
specified in the Net Selection spreadsheet.

Restriction: This column is excluded from the

spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.
Fall Closest Ringback Margin [mV] margin = (threshold - measurement) - limit

Where:
• margin is for a falling-edge transition
• threshold is Vil from the receiver IC and
reported in Fall Closest Ringback Threshold
[mV].
• measurement is the closest ringback voltage.
In Figure 15-17 on page 710, the Violation
label indicates the closest measured ringback
voltage.
• limit is Fall Closest Ringback Limit [mV]
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Fall Closest Ringback Threshold [mV] The value source depends on the model type:
• IBIS models—The [Model] keyword, Vinl
subparameter provides the threshold unless it
is overridden by the [Receiver Thresholds]
keyword, Vinl_dc subparameter.
• .MOD models—Vil.

Restriction: This column is excluded from the

spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.
Fall Dynamic Rail Overshoot Limit [mV] Value can come from the following sources,
which are sorted from high to low priority:
1. D_overshoot_low sub-keyword in an IBIS
model assigned to the pin.
2. Value of the Max. Fall Dyn. Rail Overshoot
constraint you specified in the Net Selection
spreadsheet.
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.
Fall Dynamic Rail Overshoot Margin [mV] margin = limit - overshoot

Where:
• margin is for a falling-edge transition
• limit is Max. Fall Dyn. Rail Overshoot
• overshoot is Fall Rail Overshoot [mV],
overshoot = power rail - measurement

Where:
• overshoot is for a falling-edge transition
• power rail is the low rail voltage
• measurement is the minimum voltage at the
receiver
In Figure 15-13 on page 705, the waveform
enclosed by the box indicates the measured
overshoot.

Restriction: This column is excluded from the

spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Fall Dynamic Rail Overshoot Time [ps] The amount of time the waveform spends below
the minimum acceptable static voltage. The
measurement starts when the falling-edge
transition first crosses the minimum acceptable
static voltage and ends when the waveform
returns above the minimum acceptable static
voltage.

In Figure 15-13 on page 705, this column reports

the amount of time the waveform is enclosed by
the shaded window.
Fall Dynamic Rail Overshoot Time Limit Value can come from the following sources,
[ps] which are sorted from high to low priority:
1. D_overshoot_time sub-keyword in an IBIS
model assigned to the pin. The
D_overshoot_low sub-keyword must also be
assigned to the pin.
2. Value of the Max. Dyn. Rail Overshoot Time
constraint you specified in the Net Selection
spreadsheet.
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.
Fall Dynamic Rail Overshoot Time Margin margin = limit - measurement
[ps]
Where:
• margin is for a falling-edge transition
• limit is Fall Dynamic Rail Overshoot Time
Limit [ps]
• measurement is Fall Dynamic Rail Overshoot
Time [ps]
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.
Fall Max Delay [ns] delay = receiver time - driver time

Where:
• delay is for a falling-edge transition
• receiver time is the final crossing of Vil at the
receiver
• driver time is the crossing of Vmeas at the
driver
See Figure 15-18 on page 711.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Fall Min Delay [ns] delay = receiver time - driver time

Where:
• delay is for a falling-edge transition
• receiver time is the first crossing of Vih at the
receiver
• driver time is the crossing of Vmeas at the
driver
See Figure 15-19 on page 712.
Fall Rail Overshoot [mV] overshoot = power rail - measurement

Where:
• overshoot is for a falling-edge transition
• power rail is the low rail voltage
• measurement is the minimum voltage at the
receiver
See Figure 15-11 on page 703.
Fall Rail Overshoot [Pass/Fail] Indicates whether Fall Rail Overshoot [mV]
passed or failed the Max. Fall Static Rail
Overshoot limit you set in the Net Selection
spreadsheet.
Fall Rail Overshoot Threshold [mV] The low voltage rail, or GND or VSS, for the
receiver.

The value is 0 V unless it overridden by either of

the following:
• IBIS models—Non-zero value from
[Pulldown Reference] keyword.

IBIS ECL-type models reference both pullup

and pulldown structures to the high voltage
rail, and involve some further rules that are
not describe in the documentation.
• .MOD models—Non-zero value from Vss.

Restriction: This column is excluded from the

spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.parameter.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Fall Ref Time-to-Vmeas [ns] Falling-edge switching delay at the driver,
simulated at the reference load.

For single-ended signals, it is measured from the

time simulation begins to when the falling-edge
transition crosses Vmeas.

For differential pairs assigned to an IBIS model,

it is measured from the time simulation begins to
when the falling-edge transition for the
differential signal crosses zero.

The value is NA when the model does not

provide Vmeas (single ended) or test fixture
information.
Fall SI Overshoot [mV] overshoot = steady state - measurement

Where:
• overshoot is for a falling-edge transition
• steady state is the steady-state DC voltage at
the receiver
• measurement is the minimum voltage at the
receiver
See Figure 15-15 on page 708.
Fall SI Overshoot [Pass/Fail] pass if (Max. Fall SI Overshoot - Fall SI
Overshoot [mV]) > 0
Fall Static Rail Overshoot Limit [mV] Value can come from the following sources,
which are sorted from high to low priority:
1. S_overshoot_low sub-keyword in an IBIS
model assigned to the pin.
2. Value of the Max. Fall Static Rail Overshoot
constraint you specified in the Net Selection
spreadsheet.
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Fall Static Rail Overshoot Margin [mV] margin = limit - overshoot

Where:
• margin is for a falling-edge transition
• limit is Fall Static Rail Overshoot Limit [mV]
• overshoot is Fall Rail Overshoot [mV],
overshoot = power rail - measurement

Where:
• overshoot is for a falling-edge transition
• power rail is the low rail voltage
• measurement is the minimum voltage at the
receiver
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.
Flight Time Comp. [Yes/No] Flight time compensation status. Value is No if
you did not enable flight time compensation or
there is an error in the time to Vmeas calculation.

The following conditions can cause a calculation

error:
• The model does not contain Vmeas or test
fixture information.
• A differential pair drives the nets and the
IBIS model either does not contain the
Rref_diff sub-keyword or it contains BOTH
the Rref_diff and Cref_diff sub-keywords.
Net(s) Name of the simulated net and any of the
following:
• List of nets electrically connected to it
See also: “Associated Nets” on page 272
• Other half of a differential pair
Overview [Pass/Fail] Overall pass or fail status. Value is Fail if any
other column value is Fail.
Receiver [RefDes.Pin] Reference designator and pin of receiver IC.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Receiver Meas [Pin/Die] Probe location at the receiver pin. The value is
“at pin” unless an IBIS model is assigned to the
component pin and the [Timing_location] sub-
parameter value is Die.

This information can be useful if you are trying

to correlate between detailed simulation results
and interactive simulation results.
Receiver Model File Name of the receiver model library file.

The file is located in a model folder that you

specify with the Select Directories for IC-Model
Files Dialog Box.
Receiver Model Name Name of the receiver model. For an IBIS model,
the value represents the name in the [Model]
keyword that was used.
Ringback [Pass/Fail] Indicates whether both rising and falling
ringback measurements passed. The value is Pass
if both Fall Closest Ringback Margin [mV] and
Rise Closest Ringback Margin [mV] are greater
than zero.
Ringback Delay [ps] Specifies the Ringback Delay value you set in the
Net Selection spreadsheet. See Figure 15-16 on
page 709 and Figure 15-17 on page 710.
Rise Closest Ringback [mV] Minimum ringback voltage measured at the
receiver. See Min. Rise Ringback.

In Figure 15-16 on page 709, the Violation label

indicates the closest ringback voltage.
Rise Closest Ringback Limit [mV] Value of the Min. Rise Ringback constraint you
specified in the Net Selection spreadsheet.

Restriction: This column is excluded from the

spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Rise Closest Ringback Margin [mV] margin = (measurement - threshold) - limit

Where:
• margin is for a rising-edge transition
• measurement is the minimum ringback
voltage measured at the receiver. In
Figure 15-16 on page 709, the Violation label
indicates the closest measured ringback
voltage.
• threshold is Vih from the receiver IC
See “Rise Closest Ringback Threshold [mV]”
on page 675.
• limit is Rise Closest Ringback Limit [mV]
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.
Rise Closest Ringback Threshold [mV] The value source depends on the model type:
• IBIS models—The [Model] keyword, Vinh
subparameter provides the threshold unless it
is overridden by the [Receiver Thresholds]
keyword, Vinh_dc subparameter.
• .MOD models—Vih.
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.
Rise Dynamic Rail Overshoot Limit [mV] Value can come from the following sources,
which are sorted from high to low priority:
1. D_overshoot_high sub-keyword in an IBIS
model assigned to the pin.
2. Value of the Max. Rise Dyn. Rail Overshoot
constraint you specified in the Net Selection
spreadsheet.
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Rise Dynamic Rail Overshoot Margin [mV] margin = limit - overshoot

Where:
• margin is for a rising-edge transition
• limit is Max. Rise Dyn. Rail Overshoot
• overshoot is Rise Rail Overshoot [mV],
overshoot = measurement - power rail

Where:
• overshoot is for a rising-edge transition
• measurement is the maximum voltage at
the receiver
• power rail is the high rail voltage
In Figure 15-12 on page 704, the waveform
enclosed by the box indicates the measured
overshoot.

Restriction: This column is excluded from the

spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.
Rise Dynamic Rail Overshoot Time [ps] The amount of time the waveform spends above
the maximum static overshoot voltage. The
measurement starts when the rising-edge
transition first crosses the maximum static
overshoot voltage and ends when the waveform
returns below the maximum static overshoot
voltage.

In Figure 15-12 on page 704, this column reports

the amount of time the waveform is enclosed by
the shaded window.
Rise Dynamic Rail Overshoot Time Limit Value can come from the following sources,
[ps] which are sorted from high to low priority:
1. D_overshoot_time sub-keyword in an IBIS
model assigned to the pin. The
D_overshoot_high sub-keyword must also be
assigned to the pin.
2. Value of the Max. Dyn. Rail Overshoot Time
constraint you specified in the Net Selection
spreadsheet.
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Rise Dynamic Rail Overshoot Time Margin margin = limit - measurement
[ps]
Where:
• margin is for a rising-edge transition
• limit is Rise Dynamic Rail Overshoot Time
Limit [ps]
• measurement is Rise Dynamic Rail
Overshoot Time [ps]

Restriction: This column is excluded from the

spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.
Rise Max Delay [ns] delay = receiver time - driver time

Where:
• delay is for a rising-edge transition
• receiver time is the final crossing of Vih at
the receiver
• driver time is the crossing of Vmeas at the
driver
See Figure 15-18 on page 711.
Rise Min Delay [ns] delay = receiver time - driver time

Where:
• delay is for a rising-edge transition
• receiver time is the first crossing of Vil at the
receiver
• driver time is the crossing of Vmeas at the
driver
See Figure 15-19 on page 712.
Rise Rail Overshoot [mV] overshoot = measurement - power rail

Where:
• overshoot is for a rising-edge transition
• measurement is the maximum voltage at the
receiver
• power rail is the high rail voltage
See Figure 15-10 on page 702.
Rise Rail Overshoot [Pass/Fail] Indicates whether Rise Rail Overshoot [mV]
passed or failed the Max. Rise Static Rail
Overshoot limit you set in the Net Selection
spreadsheet.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Rise Rail Overshoot Threshold [mV] The high voltage rail, or VCC, for the receiver.

The value source depends on the model type:

• IBIS models—The [Voltage Range] keyword
provides VCC unless the [Pullup Reference]
keyword overrides it.

IBIS ECL-type models reference both pullup

and pulldown structures to the high voltage
rail, and involve some further rules that are
not describe in the documentation.
• .MOD models—Vcc.

Restriction: This column is excluded from the

spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.parameter.
Rise Ref Time-to-Vmeas [ns] Rising-edge switching delay at the driver,
simulated at the reference load.

For single-ended signals, it is measured from the

time simulation begins to when the rising-edge
transition crosses Vmeas.

For differential pairs assigned to an IBIS model,

it is measured from the time simulation begins to
when the rising-edge transition for the
differential signal crosses zero.

The value is NA when the model does not

provide Vmeas (single ended) or test fixture
information.
Rise SI Overshoot [mV] overshoot = measurement - steady state

Where:
• overshoot is for a rising-edge transition
• measurement is the maximum voltage at the
receiver
• steady state is the steady-state DC voltage at
the receiver
See Figure 15-14 on page 707.
Rise SI Overshoot [Pass/Fail] The value is Pass if (Max. Rise SI Overshoot -
Rise SI Overshoot [mV]) > 0

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Rise Static Rail Overshoot Limit [mV] Value can come from the following sources,
which are sorted from high to low priority:
1. D_overshoot_high sub-keyword in an IBIS
model assigned to the pin.
2. Value of the Max. Rise Static Rail Overshoot
constraint you specified in the Net Selection
spreadsheet.
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.
Rise Static Rail Overshoot Margin [mV] margin = limit - overshoot

Where:
• margin is for a rising-edge transition
• limit is Rise Static Rail Overshoot Limit
[mV]
• overshoot is Rise Rail Overshoot [mV],
overshoot = measurement - power rail

Where:
• overshoot is for a rising-edge transition
• power rail is the high rail voltage
• measurement is the maximum voltage at
the receiver
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Rise/Fall Crosstalk [mV] crosstalk = measurement - steady state

Where:
• crosstalk is for both rising- and falling-edge
transitions
• measurement is the absolute maximum of
either the positive crosstalk voltage or the
negative crosstalk voltage for rising- and
falling-edge transitions. See Figure 15-20 on
page 713.
• steady state is the steady-state DC voltage at
the victim receiver
Negative numbers result when the victim net
voltage is decreased from its original value, due
to crosstalk from the aggressor net.

Example: If during a stuck-high simulation,

where the steady-state DC voltage on the victim
net is 3.3 V, the noisiest receiver on the victim
net peaks at 3.6 V and 3.1V (the maximum
induced voltage is 3.6 V - 3.3 V = 0.3 V). If
during stuck-low simulation, where the steady-
state DC voltage on the victim is 0.0 V, the
noisiest receiver peaks at 0.7 V and -0.8 V (the
maximum induced voltage is -0.8 V - 0 V= -0.8
V. The maximum crosstalk is 0.8 V because you
take the absolute value of the difference.
Rise/Fall Crosstalk [Pass/Fail] Indicates whether Rise/Fall Crosstalk [mV]
passed or failed the Max. Rise/Fall Crosstalk
limit you set in the Net Selection spreadsheet.
Rise/Fall Crosstalk Limit [mV] The Max. Rise/Fall Crosstalk value you set in the
Net Selection Spreadsheet.

Restriction: This column is excluded from the

spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Rise/Fall Crosstalk Margin [mV] margin = limit - measurement

Where:
• margin is for both rising- and falling-edge
transitions
• limit is Rise/Fall Crosstalk Limit [mV]
• measurement is Rise/Fall Crosstalk [mV]
Restriction: This column is excluded from the
spreadsheet when you disable the Report limits
and margins option on the Select Audit and
Reporting Options page.
Rise/Fall Delay Error [Pass/Fail] Indicates a delay limit violation. The value is Fail
if any of the following events happen:
• Fall Max Delay [ns] > Max. Rise/Fall Delay
• Rise Max Delay [ns] >Max. Rise/Fall Delay
• Fall Min Delay [ns] < Min. Rise/Fall Delay
• Rise Min Delay [ns] < Min. Rise/Fall Delay
Rise/Fall Monotonic [Pass/Fail] Indicates non-monotonic behavior at the receiver.
The value is Fail if the rising- or falling-edge
transition reverses direction while between
receiver thresholds.

Figure 15-16 on page 709 shows a non-

monotonicity that is not reported in this column
because it does not occur between Vih and Vil.

If the result is Fail, glitches may have occurred.

Rise/Fall Multi Cross [Pass/Fail] Indicates whether the rising- or falling-edge
transition has crossed the receiver Vih or Vil
threshold more than once. The value is Fail if it
has.

If the result is Fail, extra clocks may have

occurred.
Rise/Fall Threshold [Pass/Fail] Indicates the failure of the waveform to cross the
far receiver threshold. The value is Fail for either
of following conditions:
• The falling-edge transition fails to cross Vil
for the receiver
• The rising-edge transition fails to cross Vih
for the receiver

If the result is Fail, a bad DC bias may exist.

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Table 15-5. CSV/XLS Report Format - Columns Sorted Alphabetically (cont.)

Simulation Corner Simulation corner identifier. See “What IC
Operating Settings Mean” on page 552.
Total Net Length Sum of the trace segments lengths for the net(s)
listed in Net(s).

Related Topics
“Constraint Definitions” on page 700

Differential Measurements in Batch Simulation

For differential pairs, the following measurements are made on differential signals:

• Fall Closest Ringback [mV]

• Fall Max Delay [ns]
• Fall Min Delay [ns]
• Fall SI Overshoot [mV]
• Fall SI Overshoot [Pass/Fail]
• Rise Closest Ringback [mV]
• Rise Max Delay [ns]
• Rise Min Delay [ns]
• Rise SI Overshoot [mV]
• Rise SI Overshoot [Pass/Fail]
• Rise/Fall Crosstalk [mV]
• Rise/Fall Delay Error [Pass/Fail]
• Rise/Fall Monotonic [Pass/Fail]
• Rise/Fall Multi Cross [Pass/Fail]
• Rise/Fall Threshold [Pass/Fail]

SDF File
The SDF file is useful for transferring batch simulation results to other applications, such as
timing analysis and digital simulation programs. SDF file formatting is industry standard and is
not described in this Help.

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Reference Information for Batch Simulation

Audit File
The audit file reports set up problems, such as missing IC models or no enabled drivers, that
prevent detailed simulation for selected nets. The report contains a list of errors that would
occur if batch simulation was run to completion. This capability provides a way to find and fix
set up errors before launching a multiple-hour batch simulation run.

Audit files are in ASCII file format with comma-separated value data (CSV) format. You can
open audit files in spreadsheet applications, such as Excel, and sort the data by the Overview
column to bring failing nets to the top of the spreadsheet. The Net(s) column contains nets and
their associated nets. The Comment column contains error messages, if audit errors exist.

See also: “Associated Nets” on page 272

Reference Information for Batch Simulation

This topic provides detailed information about certain aspects of running batch simulation.

This topic contains the following:

• “Batch Simulation Spreadsheet” on page 683

• “Flight-Time Compensation” on page 693
• “Constraint Definitions” on page 700
• “Scope of Constraints” on page 715
• “Contents of Signal-Integrity Simulation Results Tables” on page 716
• “Driver IC Behavior During Batch Crosstalk Simulation” on page 718
• “High-Accuracy Signal-Integrity Simulations” on page 719
• “About Importing Constraints from CES” on page 721
• “Miscellaneous Errors” on page 723

Batch Simulation Spreadsheet

Use the batch simulation spreadsheet to specify the nets to analyze and to specify constraints or
EMC stimulus properties.

This topic contains the following:

• “Importing Constraints from CES to the Batch Simulation Spreadsheet” on page 685
• “Exporting and Importing Spreadsheet Contents” on page 687
• “Managing Batch Simulation Net Rules” on page 688

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• “Reporting Approximate Switching Times” on page 689

• “Column Descriptions” on page 690
• “Sorting Rows” on page 691
• “Filtering by Net Name” on page 691
• “Editing Individual Cells” on page 691
• “Editing All Cells in a Column” on page 692
• “Enabling and Disabling Many Nets” on page 692
• “Editing the Value of a Range of Cells” on page 692

Related Topics
“Selecting Nets and Editing Constraints for Signal-Integrity Simulation” on page 727

“Selecting Nets and Editing Constraints for EMC Simulation” on page 730

“Selecting Nets for Quick Analysis” on page 732

“Importing Constraints from CES to BoardSim” on page 1177

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Importing Constraints from CES to the Batch Simulation

Spreadsheet
Use the Import Constraints from CES dialog box to select the CES project containing the
constraints you want to import into the net constraint spreadsheets. Constraints for specific nets
go to the signal integrity net constraint spreadsheets for batch simulation. Constraints for
constraint classes go to the Net Rules Manager, which makes them available for assignment in
the net constraint spreadsheets. No constraints go to the EMC spreadsheet.

If CES and BoardSim identify different sets of nets, BoardSim reports the nets for which
constraint importing has failed.

See also: “About Importing Constraints from CES” on page 721

The net constraint spreadsheet does not permit blank cell values. By contrast, CES uses blank
constraint values as a way to disable specific constraints. If there is no constraint value in CES,
the import process writes 9,999.0 (for a CES maximum cell) and -1.0 (for a CES minimum cell)
to the appropriate cell in the net constraint spreadsheet. These values serve as a way to disable
the constraints in BoardSim.

Prerequisites
To minimize the likelihood of CES and BoardSim disagreeing on the set of nets in the design,
import model assignments from CES to the .REF automapping file.

See also: “Importing Model Assignments from CES to REF Files” on page 304

Procedure
1. Select Simulate SI > Run Generic Batch Simulation to open the Batch Mode Setup
Wizard.
2. In the Batch Mode Setup Wizard, click next until you get to the Batch Mode Setup -
Select Nets and Constraints for Signal-Integrity Simulation page and click SI Nets
Spreadsheet. Batch Mode Setup - Net-Selection Spreadsheet dialog box opens.
3. Click Import from CES. The Import Constraints from CES dialog box opens.
Restrictions:
• The Import from CES button is unavailable when a MultiBoard project is loaded
because CES does not define constraints for multiple-board projects.
• The Import from CES button is unavailable when the spreadsheet displays EMC
constraints.
• The Import from CES button is unavailable when you run the 64-bit version of
HyperLynx. On Windows, use the 32-bit version of HyperLynx (which is also
installed when you install the 64 bit version) to import data from CES. Select Start >

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All Programs > Mentor Graphics SDD > HyperLynx <release> 32-bit > HyperLynx
Simulation Software. By contrast, Linux installations are 64-bit only or 32-bit only.
4. Open the CES project file by doing any of the following:
• Click Browse, navigate to the CES project file (.PRJ), and then click Open.
• Select a previously-opened CES project by selecting it from the list.
• Type the path to the CES project file (.PRJ).
5. In the Flow Type area, click one of the following:
• Schematic—Import data from the schematic copy of the design database (iCDB).
• Layout—Import data from the layout copy of the design database (iCDB).
6. Select the design name from the Design list. The CES project file (.PRJ) provides the set
of available design names.
7. Click OK.

Related Topics
“Batch Simulation Spreadsheet” on page 683

“Importing Constraints from CES to BoardSim” on page 1177

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Reporting Nets Without Constraints

The Physical Nets Without Constraints dialog box automatically opens to display the names of
nets that do not belong to same set of nets in both BoardSim and CES.

Related Topics
“Importing Constraints from CES to the Batch Simulation Spreadsheet” on page 685

“About Importing Constraints from CES” on page 721

“Batch Simulation Spreadsheet” on page 683

Exporting and Importing Spreadsheet Contents

You export the contents of the spreadsheet to a comma-separated-value (CSV) file to edit the
contents of the spreadsheet with spreadsheet software, such as Microsoft Excel. Excel offers
features such as advanced sorting that are unavailable in the batch simulation spreadsheet
editor.

Exporting Spreadsheet Contents

When you export the spreadsheet, BoardSim writes both signal integrity and EMC information
to the CSV file. If you did not specify signal integrity or EMC information, default spreadsheet
values are exported. For example, the default SI Enable and EMC Enable spreadsheet cell value
in the CSV file is zero.

To export spreadsheet contents:

1. In the batch simulation spreadsheet, click Export to CSV.

Restriction: This button is unavailable when the spreadsheet displays nets for Quick
Analysis.
2. Type or browse to the CSV file you want to create, and then click Save.
Result: The contents of both spreadsheets are written to the CSV file.

Importing Spreadsheet Contents

When you import the CSV file, the contents of the CSV file are automatically loaded into the SI
Nets Spreadsheet and the EMC Nets Spreadsheet. Each spreadsheet automatically displays only
the relevant information. For example, the SI Nets Spreadsheet does not display EMC
information.

To import spreadsheet contents:

1. In the batch simulation spreadsheet, click Import from CSV.

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2. Select the CSV file you want to import and click Open.
Microsoft Excel prompts you to save the file into a fixed folder, rather than the folder from
which you opened the file. Be careful to save the edited CSV file to your board file folder, if that
is where you want it to be.

Result: The spreadsheet displays the relevant information from the CSV file.

Related Topics
“Batch Simulation Flow” on page 651

Managing Batch Simulation Net Rules

Use the Manage Rules dialog box to add, edit, delete, import, and export batch simulation net
rules.

This topic contains the following:

• “About Net Rules” on page 688

• “Adding, Editing, and Deleting Net Rules” on page 688
• “Exporting and Importing Net Rules” on page 689

About Net Rules

Net rules are an alternative way to specify constraint values in the Net-Selection Spreadsheet.
Instead of specifying values one-by-one in the spreadsheet, you create a net rule containing all
the constraint values, give it a name, save it to a file that can contain several sets of rules, and
then for a net specify the net rule name to fill in the constraint columns.

Net rules enable you to do the following:

• Save time when assigning constraints to many nets

• Share and reuse net rules among designs or co-workers
• If you expect to edit the constraints, such as during “what if” analysis, it can be faster to
edit the net rule, or create/assign a new net rule, instead of editing the constraint columns
for individual nets.

Adding, Editing, and Deleting Net Rules

To add, edit, and delete net rules:

1. In the Net-Selection Spreadsheet dialog box, click Net Rules.

2. To add a new net rule, click Add, click in the new Rule Name cell, and then type the net
rule name.

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Restriction: Net rule names cannot contain semicolons ; or exactly one dash -.
3. To edit a value, click the cell and type.
4. To delete net rules, do one of the following:
• To delete an individual ruleset, click any cell in the ruleset row and click Delete.
• To delete all rulesets, click Clear All.
5. Click OK.

Exporting and Importing Net Rules

You can share net rules among designs by exporting and importing them from the Batch Mode
Setup - Manage Rules dialog box.

To export net rules:

• Click Export, specify the folder and name of the rule file, and then click Save.
Net rules are stored in an ASCII file named <design_name>_NetRules.CSV, which is
located in the <design> folder. See “About Design Folder Locations” on page 1391.
While this is an ASCII file, you should not edit it directly because its syntax is not based
on keywords.
To import net rules:

• Click Import, browse to the <design_name>_NetRules.CSV, and then click Open.

Related Topics
“Batch Simulation Flow” on page 651

Reporting Approximate Switching Times

You can view the approximate driver edge times in the Approx. Switching Time column by
clicking the Estimate Slews button. This data enables you to sort nets by fastest driver edges,
which can produce nets with signal-integrity problems. Note that single-ended data is provided
for members of a differential pair.

Reported driver switching times are based on the following IC model and net properties:

• For IBIS models, the following data are used:

o If V-t tables exist, then the switching times are extracted from them. If multiple
tables exist per switching edge, the fastest time is used.
o If V-t tables do not exist, then the Ramp keyword is used in the following way:
switching time = typical power-supply range / Ramp value. It is assumed the driver

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switches rail to rail because it is typically the older devices that do not have V-t
tables.
• For .MOD and .PML models, the model data directly provide the switching time.
• For devices with asymmetric rising and falling times, the faster time is reported.
• For nets with more than one driver, the fastest rising or falling time of any possible
driver is reported.
• For nets with no driver, the default driver characteristics value from the General tab of
the Preferences dialog box is reported.
• For nets with no IC models, “no model(s)” is reported.

Column Descriptions
The three left-most columns contain read-only information for signal nets in the design. The
Width and Length columns are useful for sorting nets in an electrically meaningful order, such
as displaying the longest nets at the top of the spreadsheet. For nets made up of trace segments
of varying widths, the Width column displays the widest width.

When you are setting up signal-integrity analysis, the Approx. Switching Time column contains
the fastest edge of any possible driver on the net. To fill the column with switching times, click
the Estimate Slews button above the spreadsheet. If you are uncertain about which nets to
simulate, you can sort on this data and bring to the top of the spreadsheet the nets that are driven
the fastest and probably have the worst signal-integrity problems.

See also: “Reporting Approximate Switching Times” on page 689

The Net Rule column, shows the name of the net rule group the net belongs to. After you create
net rules, click the cell to assign the net to a net rule group. One dash - indicates the net belongs
to no group.

See also: “Managing Batch Simulation Net Rules” on page 688

The SI/EMC/QA Enable column specifies which nets you want to analyze.

The contents of the remaining columns depend on whether you are setting up signal-integrity or
EMC analysis:

• For signal-integrity or crosstalk analysis, you specify constraints for each net.
See also: “Constraint Definitions” on page 700
• For EMC analysis, you specify stimulus properties for each net to analyze.
• For Quick analysis, no more columns exist.

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Sorting Rows
You can sort the rows in the spreadsheet by clicking the header button for the column you want
to sort by. Click the column header button once to sort in ascending order and click again to sort
in descending order.

If you are unfamiliar with the board and do not have a good understanding of the critical nets,
sorting by length or switching time will bring to the top of the spreadsheet some candidates for
analysis. Sorting nets by length or switching time can be a valuable exercise. On high-speed
boards the longest nets often have the worst signal-quality problems, which is a basic
consequence of transmission-line theory. Similarly, nets driven by the fastest edge rates may
also have signal-integrity problems.

Sorting nets by the SI/EMC/QA Enable column helps you quickly see which nets you have
selected.

Filtering by Net Name

You can show and hide rows in the spreadsheet by filtering by net name. This capability can
help you quickly find specific groups of nets or individual nets of interest.

To filter by net name:

• Type the filter string in the Filter box and click Apply.
Use the asterisk * wildcard to match any number of characters. Use the question mark ?
wildcard to match any one character.

Group operations, such as enable/disable all, reporting approximate switching times, and so on,
are applied to the nets that remain after filtering.

See also: “Editing All Cells in a Column” on page 692, “Reporting Approximate Switching
Times” on page 689, “Enabling and Disabling Many Nets” on page 692

Editing Individual Cells

To edit a numeric value, click in the cell and type the new value.

To select a net for detailed simulation, select the check box.

If you select a net for detailed simulation, the spreadsheet automatically selects its conductively
associated nets. Similarly, if you deselect a net, the spreadsheet automatically deselects its
associated nets. This behavior is required because selected nets and associated nets are
simulated as a group.

Restriction: Values are read-only if the enable check box is cleared or if you have assigned a
net rule.

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See also: “Associated Nets” on page 272.

Editing All Cells in a Column

To edit all cells in a column:

1. Right-click over the column header.

2. Type the value or select the check box.
3. Click OK.
Restriction: Constraint values are read-only if you have assigned a net rule to the net.

Enabling and Disabling Many Nets

To enable or disable a range of nets:

1. In the SI/EMC/QA Enable column, select the range of cells by dragging from one row to
another.
2. Right-click over the selection. The Set Selection in Column dialog box opens.
3. Do one of the following and click OK.
• To enable the nets, select the Enable Selection check box.
• To disable the nets, clear the Enable Selection check box.
To enable or disable all nets, do one of the following:

• Click Enable All.

• Click Disable All.

Editing the Value of a Range of Cells

You can edit the value of a range, or block, of cells in the same column.

To edit the value of a range of cells:

1. In the column containing the values you want to change, select the range of cells by
dragging from one row to another.
2. Right-click over the selection. The Set Selection in Column dialog box opens.
3. In the New Value box, type the value or select the net rule name, and then click OK.
Restriction: You cannot override values set by a net rule.

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Flight-Time Compensation
As signal and clock speeds increase, and driver edge rates get faster, the routing segments on a
printed circuit board become transmission lines. The routing on the board often contributes
more to the delay than the capacitance of the receiver IC does. Therefore, modeling the load as
a fixed capacitance does not provide good delay prediction on a printed circuit board or multi-
chip module. In addition, I/O buffers and logic delays are often modeled and simulated
separately, making it difficult for you to create a consistent timing model.

You must correct the fixed timing delays (obtained from the data book) to get the actual values
after layout is complete, because the flight time of the signal down the routed nets is usually
comparable to the delay through the integrated circuits. Once you have compensated for this
“flight time”, you can verify timing constraints such as setup and hold times. The compensation
calculation starts with the data book delay under fixed loading conditions, and then arrives at a
corrected delay for the actual board load (including the wire routing and the receiver) by using
signal integrity simulation software such as HyperLynx.

This topic contains the following:

• “Measuring Flight Time” on page 693

• “Main Elements of System-Level Delays” on page 695
• “Effect of Measurement Loads on Driver-Switching Times” on page 695
• “Effect of Measurement Loads on System-Level Delay Calculations” on page 697
• “Performing Flight-Time Compensation” on page 699
This topic shows measurements and calculations for only one condition. Actual delay
measurements and timing budget calculations include rising-edge transitions, falling-edge
transitions, various Vcc and IC strength values, data setup and hold constraints, and so on.

Batch simulation can automatically perform flight-time compensation. See “Editing Delay and
Transmission-Line Options for Signal-Integrity Analysis” on page 734.

Measuring Flight Time

Flight time is the time it takes for a signal to propagate from a driver, through the interconnect,
to a receiver. Flight time starts when the signal passes through Vmeas at the driver, and ends
when the signal passes through Vih (for a rising edge) or Vil (for a falling edge) at the receiver.
See Figure 15-1.

Note that for differential signals, the flight time starts when the driver differential voltage
crosses 0 V and ends when the receiver differential voltage crosses Vdiff. See Figure 15-2.

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Figure 15-1. Single-Ended Flight-Time Measurement

Figure 15-2. Differential Flight-Time Measurement

If the signal passes through Vih/Vil (or Vdiff) multiple times, for example due to ringing, the
flight-time measurement ends the last time the signal passes through Vih/Vil (or Vdiff). See
“Measuring Delay and Overshoot on Waveforms” on page 1390.

Flight time minimum and maximum measurements may be needed. A synchronous design
timing budget might use the minimum flight time to calculate clock hold time margin and the
maximum flight time to calculate clock set up time margin calculations. Measurement details
depend on whether the signal is single-ended or differential:

• Single-ended signals—The minimum flight time measurement ends when the signal at
the receiver reaches the nearer input threshold voltage, such as Vih for a falling
transition. The maximum flight time measurement ends when the signal reaches the
farther input threshold voltage, such as Vil for a falling transition.
• Differential signals—The minimum flight time ends when the signal at the receiver
reaches the near crossing of Vdiff, and the maximum flight time ends when the signal
reaches the farther crossing of Vdiff.

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Main Elements of System-Level Delays

When calculating delays for system-level signals, you sum component and interconnect delays
(flight times). You typically obtain component delays from datasheets supplied by component
vendors. You obtain interconnect delays from signal-integrity simulation software, such as
BoardSim.

Figure 15-3 shows a system-level signal path consisting of component delay for U1 (pins A, B)
and interconnect delay (pins B, C). Component delay for U1 includes clocked logic and I/O
buffers.

This topic describes how to calculate flight-time compensation only for the signal path from pin
A to pin C. Additional signal path elements, such as component U2 and other objects connected
to pins A and C, are not described.

Figure 15-3. System-Level Signal Passing from Pin A to Pin C

Effect of Measurement Loads on Driver-Switching Times

Component and interconnect delays are generally measured with different loads. IC vendors
measure component delays with a test fixture. See Figure 15-4 and Figure 15-5. BoardSim
measures interconnect delays with loads extracted from interconnections in the PCB layout. See
Figure 15-6.

Figure 15-4. Test (datasheet) Single-Ended Load

The red arrow indicates an oscilloscope probe.

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Figure 15-5. Differential Load

Note
When calculating flight time compensation for differential signals, you must specify
Rref_diff for the load. Cref_diff is prohibited. If the simulation sees Cref_diff, all load
circuitry is ignored. The optional Rref or Cref sub-keywords, if they exist, are applied to
both signals in the differential pair.

Figure 15-6. Interconnect (PCB) Load

The blue and black arrows indicate oscilloscope probes.

The propagation delay value in a component datasheet can be decomposed into the following
parts:

• The time it takes for the signal to propagate internally through the output stage of the
component.
• The time it takes for the driver to switch from T=0 to Vmeasure or V. We define this
time as Tswitch.
The value of Tswitch measured with the PCB interconnect load can be significantly different
than the value measured with the test load. We define Tswitch_test as the time it takes the driver
to switch into the test load and define Tswitch_interconnect as the time it takes the driver to
switch into the interconnect load.

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Figure 15-7 shows waveforms for a driver switching into test and interconnect loads. The colors
of the waveforms match the oscilloscope probe colors, as indicated by the arrows in Figure 15-4
and Figure 15-6.

Figure 15-7. Tswitch_test and Tswitch_interconnect

Effect of Measurement Loads on System-Level Delay

Calculations
To illustrate the effect of different Tswitch_test and Tswitch_interconnect values on system-
level delay calculations, refer to the signal path between pins A and C in Figure 15-3. Assume
that pin B changes in response to a rising edge on pin A.

Figure 15-8 shows waveforms representing a portion of system-level delay from pin A to pin C.
Tswitch_test and Tswitch_interconnect, both circled in red dashed lines, are measured at pin B.
Notice how the different loads affected the delay between pins A and C. In this example, where
the interconnect load is much less than the test load, Tdelay_test is greater than
Tdelay_interconnect.

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Figure 15-8. Effect of Tswitch_test and Tswitch_interconnect on System-level

Delay Calculations

To save space, Figure 15-8 omits waveforms representing "Tswitch_interconnect (interconnect

load >> test load)" depicted by Figure 15-7.

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Performing Flight-Time Compensation

Flight-time compensation is the set of measurements and calculations used to adjust
interconnect delays for the difference between the time it takes the driver to switch into the
datasheet load (Tswitch_test) and switch into the PCB interconnect load
(Tswitch_interconnect).

The propagation delay value in a component datasheet is the sum of the internal propagation
delay and Tswitch_test. Since you probably use the datasheet delay value directly in a timing
budget spreadsheet, leave that value unchanged and adjust the interconnect delay value to
account for the difference between Tswitch_test and Tswitch_interconnect.

You can reduce the number of measurements and calculations by summing

Tswitch_interconnect and flight time to define a new term called Tswitch_int_plus_flight_time.
See Figure 15-9.

Figure 15-9. Measurements for Flight-time Compensation

Note
The ideas in this topic also apply to differential signals, which use +Vdiff and -Vdiff
instead of Vih and Vil. See Figure 15-2 on page 694.

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Steps to Perform Flight-Time Compensation

To perform flight-time compensation:

1. Measure Tswitch_test.
You can use LineSim to model and simulate the circuit representing the test load.
Measure timing at the component driver pin.
You can reuse Tswitch_test for all signals driven by the same component driver.
2. Measure Tswitch_int_plus_flight_time.
3. Calculate Flight_time_compensated by subtracting Tswitch_test from
Tswitch_int_plus_flight_time.

Flight_time_compensated = Tswitch_int_plus_flight_time - Tswitch_test

Use Flight_time_compensated in timing budget spreadsheets.
Tprop_test plus Flight_time_compensated equals Tdelay_interconnect. See Figure 15-8.
4. Repeat steps 1-3 for other signals in the timing budget.

Related Topics
“Editing Delay and Transmission-Line Options for Signal-Integrity Analysis” on page 734
(BoardSim batch simulation)

“About Automatic Measurements in the Oscilloscope” on page 585

Constraint Definitions
When setting up batch simulation, use the Batch Mode Setup - Net Selection Spread Sheet
dialog box to specify constraints for each net you specify for signal integrity and EMC analysis.

You can enter NA to disable reporting any of the following measurements: Max. Rise SI
Overshoot, Max. Fall SI Overshoot, Max. Rise Dyn. Rail Overshoot, Max. Fall Dyn. Rail
Overshoot, Min. Rise Ringback, Min. Fall Ringback.

This topic contains the following:

• “Max. Rise Static Rail Overshoot” on page 701

• “Max. Fall Static Rail Overshoot” on page 702
• “Max. Rise Dyn. Rail Overshoot” on page 703
• “Max. Fall Dyn. Rail Overshoot” on page 704
• “Max. Dyn. Rail Overshoot Time” on page 706

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• “Max. Rise SI Overshoot” on page 706

• “Max. Fall SI Overshoot” on page 707
• “Min. Rise Ringback” on page 708
• “Min. Fall Ringback” on page 709
• “Ringback Delay” on page 710
• “Max. Rise/Fall Delay” on page 710
• “Min. Rise/Fall Delay” on page 711
• “Max. Rise/Fall Crosstalk” on page 712
• “EMC Clk Freq.” on page 713
• “EMC Clk Duty Cycle” on page 713
• “Dynamic Overshoot Pass and Static Overshoot Fail Scenario” on page 714
• “Rail Voltage Value Sources” on page 714
• “Timing Threshold Voltage Value Sources” on page 715

Related Topics
“CSV and XLS Reports” on page 667

“Mapping Constraints Between CES and BoardSim” on page 722

“Scope of Constraints” on page 715

“CSV and XLS Reports” on page 667

“Differential Measurements in Batch Simulation” on page 682

Max. Rise Static Rail Overshoot

Specifies the maximum acceptable amount of voltage by which the signal can go above the high
rail voltage for the receiver. Figure 15-10 shows a waveform that fails this constraint.

The maximum static rail overshoot limit for a rising-edge transition is an offset from the high
voltage rail:

maximum static rail rising overshoot limit = maximum acceptable static voltage - high
voltage rail
For example, if the high voltage rail is 1.8 V and the maximum acceptable voltage is 2.3 V, the
maximum rising rail overshoot value is 500 mV:

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500 mV = 2.3 V - 1.8 V

Figure 15-10. Max. Rise Static Rail Overshoot

This constraint applies to all receivers on the net.

For differential pairs, measurements are made on single-ended waveforms for the positive and
negative pins.

You cannot enter NA to disable this constraint.

Caution
Your specified value is ignored for each receiver assigned to an IBIS model with a
[Model Spec] keyword and S_overshoot_high subparameter.

Related Topics
“Rail Voltage Value Sources” on page 714

Max. Fall Static Rail Overshoot

Specifies the maximum acceptable amount of voltage by which the signal can go below the low
rail voltage for the receiver. Figure 15-11 shows a waveform that fails this constraint.

Note
Falling overshoot is sometimes called undershoot.

The maximum static rail overshoot limit for a falling-edge transition is an offset from the low
voltage rail:

maximum static rail falling overshoot limit = low voltage rail - minimum acceptable
static voltage
For example, if the low voltage rail is 0 V and the minimum acceptable voltage is -0.5 V, the
maximum rising rail overshoot value is 500 mV:

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500 mV = 0 V - (-0.5 V)

Figure 15-11. Max. Fall Static Rail Overshoot

This constraint applies to all receivers on the net.

For differential pairs, measurements are made on single-ended waveforms for the positive and
negative pins.

You cannot enter NA to disable this constraint.

Caution
Your specified value is ignored for each receiver assigned to an IBIS model with a
[Model Spec] keyword and S_overshoot_low sub-parameter.

Related Topics
“Rail Voltage Value Sources” on page 714

Max. Rise Dyn. Rail Overshoot

Specifies a limit for both of the following measurements:

• The maximum acceptable amount of voltage by which the signal can go above the
maximum acceptable static voltage for the receiver for a limited time. The measurement
window starts when the rising waveform first crosses the maximum static voltage for the
receiver and ends at Max. Dyn. Rail Overshoot Time.
• The maximum acceptable amount of voltage the rising waveform can reach.
The maximum dynamic rail overshoot limit for a rising-edge transition is an offset from the
maximum static voltage:

maximum rising dynamic rail overshoot limit = maximum dynamic overshoot voltage -
maximum static overshoot voltage

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For example, if the maximum dynamic overshoot voltage is 2.6 V and the maximum static
overshoot voltage is 2.3 V, the maximum dynamic rail rising overshoot limit is 300 mV:

300 mV = 2.6 V - 2.3 V

Figure 15-12 shows a waveform that passes this constraint because it crosses only the bottom
edge of the shaded window. The waveform fails the constraint if it crosses either the top or right
edges of the shaded window.

Figure 15-12. Max. Rise Dyn. Rail Overshoot

The waveform in Figure 15-12 passes the static rail overshoot measurement because the
dynamic rail overshoot measurement has higher priority within the shaded window. See
“Dynamic Overshoot Pass and Static Overshoot Fail Scenario” on page 714.

This constraint applies to all receivers on the net.

For differential pairs, measurements are made on single-ended waveforms for the positive and
negative pins.

Enter NA to disable this constraint.

Caution
Your specified value is ignored for each receiver assigned to an IBIS model with a
[Model Spec] keyword and D_overshoot_high and D_overshoot_time subparameters.

Related Topics
“Rail Voltage Value Sources” on page 714

Max. Fall Dyn. Rail Overshoot

Specifies a limit for both of the following measurements:

• The maximum acceptable amount of voltage by which the signal can go below the
minimum static voltage for the receiver for a limited time. The measurement window

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starts when the falling waveform first crosses the minimum static voltage for the
receiver and ends at Max. Dyn. Rail Overshoot Time.
• The minimum acceptable amount of voltage the falling waveform can reach.

Note
Falling overshoot is sometimes called undershoot.

The maximum dynamic rail overshoot limit for a falling-edge transition is an offset from the
minimum static voltage:

maximum falling dynamic rail overshoot limit = minimum static overshoot voltage -
minimum dynamic overshoot voltage
For example, if the minimum static overshoot voltage is -0.3 V and the minimum dynamic
overshoot voltage is -0.6 V, the maximum dynamic rail falling overshoot limit is 300 mV:

300 mV = -0.3 V - 0.6 V

Figure 15-13 shows a waveform that passes the constraint because it crosses only the top edge
of the shaded window. The waveform fails the constraint if it crosses either the bottom or right
edges of the shaded box.

Figure 15-13. Max. Fall Dyn. Rail Overshoot

The waveform in Figure 15-13 passes the static rail overshoot constraint because the dynamic
rail overshoot constraint has higher priority within the shaded window. See “Dynamic
Overshoot Pass and Static Overshoot Fail Scenario” on page 714.

This constraint apples to all receivers on the net.

For differential pairs, measurements are made on single-ended waveforms for the positive and
negative pins.

Enter NA to disable this constraint.

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Caution
Your specified value is ignored for each receiver assigned to an IBIS model with a
[Model Spec] keyword and D_overshoot_low and D_overshoot_time subparameters.

Related Topics
“Rail Voltage Value Sources” on page 714

Max. Dyn. Rail Overshoot Time

Specifies the width of the time window for Max. Rise Dyn. Rail Overshoot and Max. Fall Dyn.
Rail Overshoot. The window width in Figure 15-12 and Figure 15-13 indicates this time. The
origin of the window is one of the following:

• Falling-edge transition: When the waveform crosses the minimum static voltage for the
receiver.
• Rising-edge transition: When the waveform crosses the maximum static voltage for the
receiver.
This constraint applies to all receivers on the net.

You cannot enter NA to disable this constraint.

Caution
Your specified value is ignored for each receiver assigned to an IBIS model with a
[Model Spec] keyword and D_overshoot_low, D_overshoot_time, and S_overshoot_low
subparameters.

Max. Rise SI Overshoot

Specifies the maximum acceptable amount of voltage by which the waveform can go above the
final DC value on a rising-edge simulation. For devices which run from a fairly wide-spaced set
of power-supply voltages but swing between a smaller set of high/low voltages, this
measurement can detect signal-quality problems, such as ringing, missed by Max. Rise Static
Rail Overshoot.

The maximum SI overshoot limit for a rising-edge transition is an offset from the high final DC
voltage:

maximum rising SI overshoot limit = maximum SI overshoot voltage - high final DC

voltage
For example, if the maximum SI overshoot voltage is 1.4 V and the high final DC voltage is 1.2
V, the maximum dynamic rail rising overshoot limit is 200 mV:

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200 mV = 1.4 V - 1.2 V

Figure 15-14 shows a waveform that fails this constraint.

Figure 15-14. Max. Rise SI Overshoot

This constraint applies to all receivers on the net.

For differential pairs, measurements are made on the differential waveform for the positive and
negative pins.

Enter NA to disable this constraint.

Max. Fall SI Overshoot

Specifies the maximum acceptable amount of voltage by which the waveform can go below the
final DC value on a falling-edge simulation. For devices which run from a fairly wide-spaced
set of power-supply voltages but swing between a smaller set of high/low voltages, this
measurement can detect signal-quality problems, such as ringing, missed by Max. Fall Static
Rail Overshoot.

Note
Falling overshoot is sometimes called undershoot.

The maximum SI overshoot limit for a falling-edge transition is an offset from the low final DC
voltage:

maximum falling SI overshoot limit = low final DC voltage - minimum SI overshoot

voltage
For example, if the low final DC voltage is 0.6 V and the minimum SI overshoot voltage is 0.4
V, the maximum dynamic rail falling overshoot limit is 200 mV:

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200 mV = 0.6 V - 0.4 V

Figure 15-15 shows a waveform that fails this constraint.

Figure 15-15. Max. Fall SI Overshoot

This constraint applies to all receivers on the net.

For differential pairs, measurements are made on the differential waveform for the positive and
negative pins.

Enter NA to disable this constraint.

Min. Rise Ringback

Specifies how far the rising waveform is allowed to “fall back” or “rebound” after first passing
through the receiver logic high timing threshold. Excessive ringback can cause unwanted
switching at the receiver, because the waveform passes through the timing threshold more than
once.

The minimum ringback limit for a rising-edge transition is an offset from the logic high timing
threshold:

minimum rising ringback limit = maximum rising ringback voltage - logic high timing
threshold
For example, if the logic high timing threshold is 2.0 V and the rising waveform is allowed to
fall back to 2.1 V, the minimum falling ringback value is 100 mV.

100 mV = 2.1 V - 2.0 V

Tiny non-monotonicities located soon after the waveform first crosses the receiver logic high
timing threshold can cause misleading measurements. Use Ringback Delay to delay the start of
the measurement until some time after the first timing threshold crossing.

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Figure 15-16 shows the application of Ringback Delay. The non-monotonicity is not reported as
a rising ringback failure because it is located between the first crossing of the logic high
threshold and the ringback delay. A constraint failure/violation occurs the second time the
waveform falls below the minimum rising ringback voltage because it happens after the
ringback delay has ended.

Figure 15-16. Min. Rise Ringback

This constraint applies to all receivers on the net.

For differential pairs, measurements are made on the differential waveform for the positive and
negative pins.

Enter NA to disable this constraint.

Min. Fall Ringback

Specifies how far the falling waveform is allowed to “rise back” or “rebound” after passing
through the receiver logic low timing threshold. Excessive ringback can cause unwanted
switching at the receiver, because the waveform passes through the timing threshold more than
once.

The minimum ringback limit for a falling-edge transition is an offset from the logic low timing
threshold:

minimum falling ringback limit = logic low timing threshold - maximum falling
ringback voltage
For example, if the logic low timing threshold is 0.8 V and the falling waveform is allowed to
rise back to 0.7 V, the minimum falling ringback value is 100 mV.

100 mV = 0.8 V - 0.7 V

Tiny non-monotonicities located soon after the waveform first crosses the receiver logic low
timing threshold can cause misleading measurements. Use Ringback Delay to delay the start of
the measurement until some time after the first timing threshold crossing.

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Figure 15-17 shows the application of Ringback Delay. The non-monotonicity is not reported as
a rising ringback failure because it is located between the first crossing of the logic low
threshold and the ringback delay. A constraint failure/violation occurs the second time the
waveform rises above the minimum falling ringback voltage because it happens after the
ringback delay has ended.

Figure 15-17. Min. Fall Ringback

This constraint applies to all receivers on the net.

For differential pairs, measurements are made on the differential waveform for the positive and
negative pins.

Enter NA to disable this constraint.

Ringback Delay
Specifies how long to delay the ringback measurement, starting from the first time the
waveform crosses the logic threshold. See Figure 15-17 on page 710 and Figure 15-16 on
page 709.

This constraint applies to all receivers on the net.

This constraint has no effect if you specify NA for both Min. Rise Ringback and Min. Fall
Ringback.

You cannot enter NA to disable this constraint.

Max. Rise/Fall Delay

Specifies the maximum acceptable delay to any receiver on the net for both of the following
conditions:

• Rising waveform—The measurement begins when the driver waveform crosses

Vmeasure and ends when the receiver waveform crosses the logic high threshold for the
final time.

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• Falling waveform—The measurement begins when the driver waveform crosses

Vmeasure and ends when the receiver waveform crosses logic low threshold for the final
time.
Figure 15-18 shows the receiver waveform crossing each logic threshold twice. Measuring
delays at the final crossing of the logic thresholds provides the most pessimistic delay values.

Figure 15-18. Max. Rise/Fall Delay

For driver ICs, Vmeasure specifies the voltage at which the driver is considered to be switched.

For receiver ICs, logic high and logic low thresholds specify the lowest and highest voltage at
which the receiver recognizes a state change.

If you run batch simulation with all three IC model corners, all delays are calculated from the
smallest driver switching times. This provides the most conservative results.

For differential pairs, measurements are made on the differential waveform for the positive and
negative pins.

Related Topics
“Timing Threshold Voltage Value Sources” on page 715

Min. Rise/Fall Delay

Specifies the minimum acceptable delay to any receiver on the net for both of the following
conditions:

• Rising waveform—The measurement begins when the driver waveform crosses

Vmeasure and ends when the receiver waveform crosses the logic low threshold for the
first time.

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• Falling waveform—The measurement begins when the driver waveform crosses

Vmeasure and ends when the receiver waveform crosses logic high threshold for the
first time.
Figure 15-19 shows the receiver waveform crossing each logic threshold once.

Figure 15-19. Min. Rise/Fall Delay

For driver ICs, Vmeasure specifies the voltage at which the driver is considered to be switched.

For receiver ICs, logic high and logic low thresholds specify the lowest and highest voltage at
which the receiver recognizes a state change.

If you run batch simulation with all three IC model corners, all delays are calculated from the
largest driver switching times. This provides the most conservative results.

For differential pairs, measurements are made on the differential waveform for the positive and
negative pins.

Related Topics
“Timing Threshold Voltage Value Sources” on page 715

Max. Rise/Fall Crosstalk

Restriction: You must have the BoardSim Crosstalk license to measure maximum crosstalk
constraint results.

Specifies the maximum acceptable amount of voltage, positive or negative, that can be induced
on the victim net by signal switching on aggressor nets. For the selected victim net and its
associated nets only, not its aggressor nets, find the maximum peak voltage excursion away
from the DC voltage for the net, positive or negative, at any receiver IC. The magnitude, that is
absolute value, of this excursion is the maximum crosstalk. If both stuck high and stuck low
simulations are run, use the maximum crosstalk observed in either simulation.

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Figure 15-20 shows a rising waveform on an aggressor net that causes both positive and
negative crosstalk on the victim net. The crosstalk on the victim net does not fail the constraint.
The spreadsheet reports only the larger of the positive and negative crosstalk values.

Figure 15-20. Max. Rise Crosstalk

For differential pairs, measurements are made on the differential waveform for the positive and
negative pins.

Max. Rise/Fall Crosstalk Also Sets Crosstalk Electrical Threshold

This constraint also specifies the electrical threshold for crosstalk simulations, which is used to
find aggressor nets that are coupled to the selected net.

See also: “How BoardSim Crosstalk Finds Aggressor Nets” on page 1220

Technically, every net on the design couples to the select net, but from a practical viewpoint
only a small number of other nets couple strongly enough to generate any significant crosstalk.
The noise budget for the design determines the minimum amount of crosstalk that you should
report as a violation.

You can specify different threshold voltages for individual nets you enable for crosstalk
simulation. However, for simplicity, you will probably use the same value for all nets.

EMC Clk Freq.

Specifies the center frequency of a clock signal.

EMC Clk Duty Cycle

Specifies the duty cycle of a clock signal. Enter the percentage of time the waveform is in the
logic high state. See “How Duty Cycle Affects EMC Simulation” on page 903.

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Dynamic Overshoot Pass and Static Overshoot Fail Scenario

The dynamic overshoot window is a one shot window. Figure 15-21 shows the waveform rising
above the static overshoot voltage two times. Batch simulation does not report an error for the
first event because it happens within the dynamic overshoot voltage and time range (the shaded
window). Batch simulation reports a static overshoot error for the second event.

Figure 15-21. Secondary Dynamic Overshoot Scenario

Rail Voltage Value Sources

The rail voltage valued used by waveform measurements comes from the receiver IC model or a
power supply net. Table 15-6 maps the IC model type to the available rail voltage sources.

Table 15-6. Mapping IC Model Types to Rail Voltage Sources

Receiver IC Model Type Rail Voltage Source
IBIS—non-ECL models High rail voltage (highest priority first):
1. [Power Clamp Reference] keyword
2. [Pullup Reference] keyword
Low rail voltage:
1. [GND Clamp Reference] keyword
2. [Pulldown Reference] keyword
3. 0 V
IBIS—ECL models High rail voltage (highest priority first):
1. [Power Clamp Reference] keyword
2. [Pullup Reference] keyword
Low rail voltage:
1. [GND Clamp Reference] keyword
2. High rail voltage - 5 V
MOD High rail voltage (highest priority first):
1. Power-supply net voltage
2. Default power-supply voltage in model
Low rail voltage:
1. Power-supply net voltage
2. Default power-supply voltage in model

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Timing Threshold Voltage Value Sources

The Vih, Vil, and Vmeasure values used by waveform measurements come from the receiver IC
model. Table 15-6 maps the IC model types to the available sources of timing measurement
threshold information.

Table 15-7. Mapping IC Model Types to Timing Threshold Voltage Sources

Receiver IC Model Type Timing Threshold Voltage Source
IBIS - single ended Vih - logic high threshold (highest priority first):
1. [Receiver Thresholds] keyword, Vinh_ac subparameter
2. [Model Spec] or [Model] keyword, Vinh subparameter

Vil - logic low threshold:

1. [Receiver Thresholds] keyword, Vinl_ac subparameter
2. [Model Spec] or [Model] keyword, Vinl subparameter

Vmeasure:
1. Rising-edge transition - [Vmeas_rising] or [Vmeas_falling]
subparameter
2. [Vmeas] subparameter
IBIS - differential • [Receiver Thresholds] keyword, Vdiff_ac subparameter
• [Diff Pin] keyword, Vdiff subparameter
MOD All values supplied by model.

Scope of Constraints
Constraints apply to all detailed simulations. For example, if you enable crosstalk simulation for
the victim net stuck both low and high, Board Wizard will actually run the following four
simulations:

• Victim stuck low, aggressors switching high

• Victim stuck low, aggressors switching low
• Victim stuck high, aggressors switching high
• Victim stuck high, aggressors switching low
"Stuck" means the driver is enabled and set to the low or high logic state.

However the crosstalk constraint is checked against all of these simulations, and the worst-case
crosstalk that occurs in any of them is reported.

Constraints also apply to nets associated to the selected net. A change made to the rules for any
net in a group of associated nets changes the rules for the entire group.

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Related Topics
“Associated Nets” on page 272

“Selecting Nets and Editing Constraints for Signal-Integrity Simulation” on page 727

“About Importing Constraints from CES” on page 721

“Batch Simulation Spreadsheet” on page 683

Contents of Signal-Integrity Simulation Results Tables

The standard report file contains a signal-integrity SIMULATION RESULTS table for each net
you select for detailed simulation. The tables are located in the NET INFORMATION section
of the report file.

Table 15-8 describes the content of the signal-integrity SIMULATION RESULTS table:

Table 15-8. Batch Simulation - Signal-Integrity Simulation Results Table

Column Indicates
Driver Device.Pin Name of IC pin driving the net, of form
<reference_designator>.<pin_name>.

Pin may be on selected or associated net.

Receiver Device.Pin Name of IC pin being probed during simulation, of
form <reference_designator>.<pin_name>.

Pin may be on selected or associated net.

Rnd Rbn "NA" if round robin is not enabled. Count of the
drivers if round robin is enabled.
Rise Delay Min Minimum delay from the driver to any receiver on the
net, for a rising-edge transition.

Measured at each receiver from the time the driver

switches until the receiver’s nearer threshold is
crossed for the first time.

If the model does not provide Vmeas or test fixture

information, or the simulation fails for some reason, the
value is NA.

For an image illustrating how delay is calculated, see

Figure 15-19 on page 712.

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Table 15-8. Batch Simulation - Signal-Integrity Simulation Results Table

Rise Delay Max Maximum delay from the driver to any receiver on the
net, for a rising-edge transition.

Measured at each receiver from the time the driver

switches until the receiver’s farther threshold is
crossed for the final time.

If the model does not provide Vmeas or test fixture

information, or the simulation fails for some reason, the
value is NA.

For an image illustrating how delay is calculated, see

Figure 15-18 on page 711.
Fall Delay Min Same as Rise Delay Min, except data result from a
falling-edge transition on the driver.

For an image illustrating how delay is calculated, see

Figure 15-19 on page 712.
Fall Delay Max Same as Rise Delay Max, except data result from a
falling-edge transition on the driver.

For an image illustrating how delay is calculated, see

Figure 15-18 on page 711.
Overshoot Rise Maximum overshoot beyond the steady DC state for a
rising-edge transition.
Overshoot Fall Same as Overshoot Rise, except data result from a
falling-edge transition on the driver.
Crosstalk Rise Maximum crosstalk voltage induced on the selected net
for a rising-edge transition on the driver. See
Figure 15-20 on page 713.
Crosstalk Fall Same as Crosstalk Rise, except data result from a
falling-edge transition on the driver.
ERROR FLAGS Constraint violations.

For information about what each column means, see

the note near the top of the report file.

Related Topics
“Viewing Batch SI Simulation Reports” on page 663

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Driver IC Behavior During Batch Crosstalk Simulation

This topic contains the following:

• “Aggressor Versus Victim nets” on page 718

• “Importance of Victim Net Stuck State” on page 718
• “Buffer Inversion Affects Stuck State” on page 719
• “Aggressor Net Driver ICs Switch Together” on page 719
• “Crosstalk Simulation Uses Fast-Strong Drivers” on page 719
Requirement: The BoardSim Crosstalk license is required to run crosstalk simulation.

Aggressor Versus Victim nets

In crosstalk simulation, any net that is intentionally driven by a switching IC output buffer, and
is therefore a potential source of crosstalk on other nets, is called an aggressor. Any net that
potentially receives unwanted crosstalk from an aggressor is called a victim.

For calculating crosstalk, victim nets are driven to a static high or low state while a nearby
aggressor switches and induces an unwanted signal on the victim. See Figure 15-22. Because of
reflection effects, the state of the victim trace’s static driver is an important factor in the
crosstalk waveforms that actually appear on the victim trace.

Figure 15-22. Aggressor and Victim Trace

Importance of Victim Net Stuck State

Requirement: Crosstalk simulation must include non-switching, that is stuck, driver ICs on
each victim net because victim nets on real PCBs do have drivers. If stuck-high or stuck-low IC
drivers were absent on victim nets during simulation, the crosstalk results would be much
different than if the IC drivers were present. The results difference occurs because driver ICs are
typically low impedance and will reflect, rather than absorb, crosstalk signals.

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As long as there is a driver IC identified on the victim net, batch simulation automatically sets
the IC driver to the proper stuck-high or stuck-low.

Buffer Inversion Affects Stuck State

If the IC driver is interactively set to output inverted instead of output in the Assign Models
dialog box, then its stuck state is reversed during crosstalk simulation. For example, if you
specify that IC drivers on victim nets are stuck low during crosstalk simulation, any IC drivers
that are interactively set to output inverted are stuck high during crosstalk simulation. Recall
that output inverted is required to simulate differential IC drivers.

Aggressor Net Driver ICs Switch Together

If multiple aggressor nets are present for a crosstalk simulation, batch simulation automatically
switches all of the aggressor ICs together, simultaneously. First, all aggressor-net driver ICs
switch low, then all aggressor drivers switch high. There is no skew between the aggressor-net
switching times. Using this method, the crosstalk that appears on the victim net is the worst-case
and summed effect of all the aggressor nets acting together.

Crosstalk Simulation Uses Fast-Strong Drivers

Since some aspects of crosstalk worsen with faster driver-IC switching times, maximum
crosstalk is almost always produced by the fastest possible aggressor-net switching. Therefore
batch simulation automatically sets aggressor-net ICs to their fast-strong corner, to get the
fastest possible edges.

The forward component of crosstalk is roughly proportional in amplitude to driver slew rate,
that is, a faster driver will generate more forward crosstalk.

See also: “Setting IC Operating Parameters” on page 551, “Details of Forward Crosstalk” on
page 1351

Related Topics
“Editing Crosstalk Analysis Options” on page 737

“Running the Batch Simulation Wizard” on page 663

“Getting to Know Batch Simulation” on page 652

High-Accuracy Signal-Integrity Simulations

During high-accuracy signal integrity simulation, batch simulation includes all nets coupled to
the selected net. By contrast, normal-accuracy batch simulation includes only the selected net
and its associated nets during regular signal integrity simulation. High-accuracy simulations run
more slowly than normal-accuracy simulations.

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Neighboring coupled nets may affect simulation results, especially on boards where routing
density is high or net-to-net coupling is strong for other reasons. Simulations including these
coupled nets are generally more accurate than simulations that exclude coupled nets.

See also: “Associated Nets” on page 272, “Editing Delay and Transmission-Line Options for
Signal-Integrity Analysis” on page 734

Requirement: The BoardSim Crosstalk license is required to run high-accuracy signal integrity
simulation.

This topic contains the following:

• “Mandatory for Differential Signals-Unless Weakly Coupled” on page 720

• “Optional for Non-differential Nets-Runs Slower but May Increase Accuracy” on
page 720
• “Consider Running High-Accuracy Only on Differential Nets” on page 721
• “Driver IC Behavior During High-Accuracy Simulation” on page 721

Mandatory for Differential Signals-Unless Weakly Coupled

Generally speaking, simulate differential trace pairs in high-accuracy mode, because they are
usually coupled significantly to each other. If you simulate a differential pair without enabling
the high-accuracy option, each trace in the pair is modeled with its uncoupled impedance to
ground and the other trace in the pair is not accounted for.

Exception: If you know that your differential pairs are weakly coupled, such as by using
LineSim Crosstalk or the BoardSim Crosstalk coupling-region viewer, you may disable high-
accuracy simulation so that simulations run faster.

See also: “Opening the Coupling-Region Viewer” on page 1240

If a differential IBIS IC model drives the pair, batch simulation includes both traces in
simulation, whether or not you enable high-accuracy simulation. This occurs because BoardSim
considers the traces in a pair to be electrically associated with each other and coupling is not
required to draw the second trace into simulation. However, if high-accuracy simulation is not
enabled, the electromagnetic coupling between the pairs will be ignored.

Optional for Non-differential Nets-Runs Slower but May Increase

Accuracy
For non-differential traces, high-accuracy signal-integrity simulation is optional. For boards that
are not dense or that have been carefully designed to minimize crosstalk and coupling, the
added benefit of high-accuracy mode may be quite small. On the other hand, for dense boards,
or boards that are likely to suffer from a lot of coupling, high-accuracy mode may be worth

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running. In general, the trace impedances used in high-accuracy mode are more accurate than
those used in regular simulation.

Consider Running High-Accuracy Only on Differential Nets

A possible strategy is to break batch simulations into two groups: simulation of differential
pairs (and/or other nets strongly affected by coupling), and simulation of non-differential nets.
Table 15-9 contains the key settings for the batch simulation runs:

Table 15-9. Batch Simulation - Possible Strategy for Running High-Accuracy

High-accuracy Nets to enable in SI
simulation option Nets Spreadsheet
Batch run #1 Enable differential
Batch run #2 Disable non-differential

Driver IC Behavior During High-Accuracy Simulation

In high-accuracy simulations, driver ICs have the following behavior:

• On the victim net, the driver IC is toggled low and high

• On the aggressor net, driver ICs are stuck low (unless inverted; then stuck high)
Note that in this type of simulation, the term aggressor is really used to refer to neighboring nets
that are coupled to the net being simulated. Strictly speaking, these nets are not aggressors
because their drivers are stuck during simulation and cannot generate crosstalk. This has the end
result of including the impedance effects of the neighboring traces in the simulation, but not the
crosstalk-generating effects.

Related Topics
“Editing Delay and Transmission-Line Options for Signal-Integrity Analysis” on page 734

About Importing Constraints from CES

You can import net constraints from Constraint Editor System (CES) to BoardSim. Constraints
for specific nets go to the signal integrity net constraint spreadsheets for batch simulation.
Constraints for constraint classes go to the Net Rules Manager, which makes them available for
assignment in the net constraint spreadsheets. No constraints from CES go to the EMC
spreadsheet.

This topic contains the following:

• “Mapping Nets Between CES and BoardSim” on page 722

• “Mapping Constraints Between CES and BoardSim” on page 722

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Related Topics
“Importing Constraints from CES to the Batch Simulation Spreadsheet” on page 685

Mapping Nets Between CES and BoardSim

BoardSim can import constraints for electrical nets and differential pairs in CES. An electrical
net in CES consists of one or more physical (layout) or CAD (schematic or CES) nets that are
connected by a differential IC model, resistor package model, or an IBIS EBD model. A
differential pair in CES consists of two or more nets that you automatically define (for example,
by model assignments or net-name conventions) or manually define as a differential pair.

It is possible for CES and BoardSim to identify different sets of nets for the same design. For
example, if you assign different models in CES than in BoardSim, then different sets of
electrical nets or differential pairs can exist in those design databases. This scenario can lead to
constraint-mapping ambiguity and BoardSim does not import constraints for nets belonging to a
different set of electrical nets or differential pairs in CES. BoardSim reports the nets for which
constraint importing has failed.

Mapping Constraints Between CES and BoardSim

Table 15-10 on page 722 maps the constraint column names for the spreadsheets in CES and
BoardSim. CES supports many more types of constraints than BoardSim does, and so only a
subset of the available CES constraints are imported.

Restriction: EMC constraints are not imported from CES projects.

Table 15-10. Mapping CES and BoardSim Constraint Columns

CES Constraint Column BoardSim Batch BoardSim Constraint
Simulation Column
Spreadsheet
Static High Overshoot Max SI Nets Max. Rise Static Rail
Overshoot
Restriction: CES does not support Max. Rise
SI Overshoot, which is measured relative to the
final DC voltage of the waveform.
Static Low Overshoot Max SI Nets Max. Fall Static Rail
Overshoot
Restriction: CES does not support Max. Fall SI
Overshoot, which is measured relative to the
final DC voltage of the waveform.
Dynamic Low Overshoot Max SI Nets Max. Fall Dyn. Rail
Overshoot
Max. Dyn. Rail Overshoot
Time

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Table 15-10. Mapping CES and BoardSim Constraint Columns (cont.)

CES Constraint Column BoardSim Batch BoardSim Constraint
Simulation Column
Spreadsheet
Dynamic High Overshoot Max SI Nets Max. Rise Dyn. Rail
Overshoot
Max. Dyn. Rail Overshoot
Time
Ringback Margin High Min SI Nets Min. Rise Ringback
Ringback Delay
Ringback Margin Low Min SI Nets Min. Fall Ringback
Ringback Delay
Simulated Delay—Max; SI Nets Max. Rise/Fall Delay
• if unavailable, then TOF Delay—Max;
• if unavailable, then no value
Simulated Delay—Min; SI Nets Min. Rise/Fall Delay
• if unavailable, then TOF Delay—Min;
• if unavailable, then no value
Crosstalk - Max SI Nets Max. Rise/Fall Crosstalk

Miscellaneous Errors
If batch simulation reports “Could not analyze SI; DC operating points not valid; check model
thresholds”, note that one possible source of the error is that a required model threshold is
contained only in the [Model Spec] keyword. While DDRx batch simulation supports portions
of this keyword, generic batch simulation does not.

Batch Simulation Wizard Dialog Box Help

This section contains the Help topics for the individual batch simulation Wizard dialog boxes.
You will most likely access the topics by clicking the Help button in a Wizard dialog box.

This topic contains the following:

• “Editing Primary Batch Simulation Options” on page 724

• “Selecting Nets and Editing Constraints for Signal-Integrity Simulation” on page 727
• “Selecting Nets and Editing Constraints for EMC Simulation” on page 730
• “Selecting Nets for Quick Analysis” on page 732
• “Editing Driver and Receiver Options for Signal-Integrity Analysis” on page 733

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• “Editing Delay and Transmission-Line Options for Signal-Integrity Analysis” on

page 734
• “Editing Default IC Model Properties” on page 736
• “Editing Crosstalk Analysis Options” on page 737
• “Editing Quick Analysis Interconnect Statistics Options” on page 740
• “Editing Terminator Wizard Reporting Options” on page 741
• “Editing Batch Simulation Audit and Reporting Options” on page 742
• “Running Simulation and Showing Results” on page 745

Related Topics
“Batch Simulation Spreadsheet” on page 683

Editing Primary Batch Simulation Options

Use the Overview page in the batch simulation wizard to select the primary batch simulation
options. Options you enable on this page determine the main types of analysis to run and which
other wizard pages to display. You can also display results from the previous batch simulation
from this page.

This topic contains the following:

• “Viewing Previous Batch Simulation Results” on page 724

• “Selecting Detailed Simulation Options” on page 725
• “Selecting Quick Analysis Options” on page 725

Viewing Previous Batch Simulation Results

You can open report files from the most recent batch simulations directly from the Overview
page. This capability enables you to open report files for the current design without having to
remember their locations.

To view previous report files:

• Click the Open button next to the type of report file you want to open.
If the computer is running under Windows, batch simulation opens the XLS or CSV file in
Excel or another program associated with these types of files.
If the computer is running under Solaris, batch simulation opens the CSV file in the HyperLynx
File Editor.

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Selecting Detailed Simulation Options

Detailed simulation runs the same kinds of simulations that you run interactively, on nets that
you select. If you select large numbers of nets for detailed simulation, batch simulation may
take multiple hours to complete.

Requirement: Before running detailed simulation, assign IC models for each net you want to
simulate and its associated nets.

To select detailed simulation options:

• In the Detailed Simulations area, select the check boxes for any of the options you want.
Restriction: EMC simulations are unavailable if a MultiBoard project is open in BoardSim.

You select nets for detailed simulation in a wizard page that appears later.

See also: “Associated Nets” on page 272

Selecting Quick Analysis Options

Quick analysis runs on all signal nets on the board. Quick analysis results are approximate, but
the runtime is shorter than running interactive simulations and no IC model set up is required.
You can improve quick analysis accuracy by assigning IC models.

To select quick analysis options:

• In the Quick Analysis area, select the check boxes for any of the options you want.
Restriction: The Show Signal-Integrity Problems Caused By Line Lengths and the Suggest
Termination Changes And Optimal Values options are unavailable if a MultiBoard project is
loaded in BoardSim.

Summary of Quick Analysis Options

Table 15-11 describes the quick analysis options:

Table 15-11. Batch Simulation - Quick Analysis Options

Option Means
Show signal-integrity Uses the Terminator Wizard to identify nets with problems
problems caused by line such as long stub lengths, improper terminator placement, and
lengths so on.
Suggest termination Uses the Terminator Wizard to calculate optimal values for
changes and optimal values existing terminators and recommend terminator type and
values for unterminated nets that are too long.

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Table 15-11. Batch Simulation - Quick Analysis Options (cont.)

Show crosstalk strength Estimates the maximum crosstalk that could occur on each net
estimates and creates a list of nets sorted from the most possible
crosstalk to the least.

Crosstalk estimates are generally conservative and, for specific

situations, may be in error by a factor of three or four. This
conservatism attempts to ensure that the Quick Crosstalk
Analysis does not miss any nets that might experience
significant crosstalk.

You can obtain accurate crosstalk results by running

interactive simulation or detailed simulations in batch
simulation.

The algorithm for estimating crosstalk is proprietary. It is

based on the weak coupling theory of crosstalk, which yields a
set of closed-form prediction equations that can run quickly.
The resulting capability is sufficient to make reasonable
guesses as to how much crosstalk each possible aggressor net
can generate on a victim net.

However, of necessity, any such approximation algorithm has

limitations. For nets with clean linear routing, which run
parallel to each other for a medium distance, the aggressor-
finding algorithm is quite accurate. As the routing topology
becomes more complex, then the results become more
approximate.
Show component changes Reports the manual edits you made to passive component
values. This information records the changes you make to
terminators to improve simulation results.

You can provide this information to the layout designer or

service bureau as a record of changes you want to make to the
board. You can also use this information when updating the
schematic.

For a concise record of changes that you can hand back to the
layout designer or service bureau, create a design change
summary. See “Reporting Design Changes” on page 338.
Show net changes Reports nets that have been unrouted or rerouted with
Manhattan routing in BoardSim.

See also: “Simulating Unrouted Nets with Manhattan

Routing” on page 921

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Table 15-11. Batch Simulation - Quick Analysis Options (cont.)

Show new components Report the Quick Terminators, and their values, that you added
to the board.

You can provide this information to the layout designer or

service bureau as a record of changes you want to make to the
board. You can also use this information when updating the
schematic.

For a concise record of changes that you can hand back to the
layout designer or service bureau, create a design change
summary. See “Reporting Design Changes” on page 338.
Show stackup Reports the physical properties of the board stackup. If you
have edited the stackup using the stackup editor, any changes
are reported.

You can provide this information to the PCB manufacturer.

See also: “Documenting Stackups” on page 399
Show interconnect statistics Reports detailed electrical statistics for each net including total
delay, minimum/maximum/average impedance, inductance,
capacitance, and resistance.

The interconnect statistics data can consume a large portion of

the report file. If you do not need this data, clear the check box
to reduce the clutter.
Show counts Reports the layout numeric statistics for each net including the
number of segments that make up the net, driver ICs, receiver
ICs, resistors, capacitors, vias, and so on.

The counts data can consume a large portion of the report file.
If you do not need this data, clear the check box to reduce the
clutter.

Related Topics
“Batch Simulation Flow” on page 651

Selecting Nets and Editing Constraints for Signal-

Integrity Simulation
Use the Select Nets and Constraints for Signal-Integrity Simulation page in the batch simulation
wizard to select the nets to simulate, define the constraints for each net, and define maximum
run time per net.

This topic contains the following:

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• “Selecting Nets and Editing Constraints in SI Nets Spreadsheet” on page 728

• “Analyzing Every Net is Not Recommended” on page 729
• “How Batch Simulation Uses Constraints” on page 729

Selecting Nets and Editing Constraints in SI Nets Spreadsheet

Use the SI Nets Spreadsheet to specify the nets you want to simulate and to specify net-specific
constraints.

See also: “Batch Simulation Spreadsheet” on page 683

To select nets and edit constraints:

1. Click SI Nets Spreadsheet.

2. In the SI Enable column, select the check box for each net you want to analyze.
You can edit the value for all cells in a column or a range of cells in a column.
To sort spreadsheet rows, click the column header.
3. Edit constraint values by doing any of the following:
• Click in a cell and type a new value.
You can edit the value for all cells in a column or a range of cells in a column.
• Click in the Net Rule cell and select a net rule name. Values from the net rule are
also applied to the EMC spreadsheet and override any previous values.
4. Click OK to close the spreadsheet and return to the wizard page.
5. In the Maximum run-time per net box, type the value in minutes. If the simulation time
on a specific net exceeds the limit, batch simulation abandons simulation of the net and
simulates the next net.
This option is mostly useful in round-robin and crosstalk simulations. For crosstalk,
potentially large numbers of nets are simulated simultaneously, including the selected
net and its aggressor nets. For signal-integrity and EMC simulations, any reasonable
time limit is unlikely to be exceeded. However if a power-supply net is not correctly
identified, batch simulation tries to simulate it and may very well exceed the simulation
run-time limit.
See also: “round robin” on page 1965

Related Topics
“Analyzing Every Net is Not Recommended” on page 729

“Managing Batch Simulation Net Rules” on page 688

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“How Batch Simulation Uses Constraints” on page 729

Analyzing Every Net is Not Recommended

It is recommended that you run detailed simulation on only the nets whose signal quality you
are truly concerned about. Of course, especially in some high-speed designs, it is possible that
nearly every net is critical and that you should run detailed simulation on all nets. However,
many boards have only a subset of nets whose signal quality is worth analyzing in detail.

If you run detailed simulation on all nets, rather than only the critical nets, the following
consequences occur:

• Detailed simulation runs for a longer time

• You must set up more IC models
• The report files are longer and more difficult to read
You can save yourself effort in both set up and ease of interpreting results if you spend a small
amount of time up-front thinking about which nets on your board are truly critical, and choosing
only them for detailed simulation.

See also: “Getting to Know Batch Simulation” on page 652

How Batch Simulation Uses Constraints

Batch simulation creates the following two kinds of information for every net you select for
detailed simulation:

• A numerical result of the simulation, including pin-to-pin delays and overshoot

• Optionally, a warning whenever the numerical result exceeds the constraints you define,
such as maximum allowed delay or overshoot. Warnings make it easier to scan the
report file and identify offending nets. You can investigate offending nets further with
interactive simulation, the Terminator Wizard, and so on.
See also: “Simulating Signal Integrity with the Oscilloscope” on page 533, “Optimizing
Termination with the Terminator Wizard” on page 945

Default constraints are set to reasonable values. If you want different values, you can edit them
for each net. You edit constraints in the spreadsheet that opens when you click the SI Nets
Spreadsheet button.

See also: “Constraint Definitions” on page 700

Some constraint measurements can be disabled by entering NA as the constraint value. The
following constraints behave this way: Max. Rise SI Overshoot, Max. Fall SI Overshoot, Max.

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Rise Dyn. Rail Overshoot, Max. Fall Dyn. Rail Overshoot, Min. Rise Ringback, Min. Fall
Ringback.

Some constraint measurements cannot be disabled, but you can make it unlikely for violations
to occur by setting rules to extreme values. For example, use 10 V for an overshoot constraint,
use 1000 ns for a maximum delay, use -5 ns for a minimum delay, and so on.

Related Topics
“Batch Simulation Flow” on page 651

Selecting Nets and Editing Constraints for EMC

Simulation
Use the Select Nets and Constraints for EMC Simulation page in the batch simulation wizard to
select the nets to simulate for radiated emissions (EMC) and specify EMC simulation options.

This topic contains the following:

• “Selecting Nets and Editing EMC Stimulus” on page 730

• “Selecting Simulation Options” on page 731
• “Selecting Regulatory Constraints” on page 732

Selecting Nets and Editing EMC Stimulus

Use the EMC Nets Spreadsheet to specify the nets you want to simulate and to specify net-
specific EMC stimulus.

Recommendation: Do not analyze every net. EMC simulations are inherently time consuming
and running detailed simulation on every net on the board would take a prohibitively long time.
It is recommended that you run detailed simulation on only the nets whose EMC you are truly
concerned about, such as periodic signals that generate sharply peaked amounts of radiation. By
contrast random signals generally distribute radiated energy in a wider, less peaked, manner.

See also: “Radiation from Periodic Versus Random Signals” on page 892

You can save yourself effort in both set up and ease of interpreting results if you spend a small
amount of time up-front thinking about which nets are critical, and choosing only them for
batch-mode EMC analysis.

See also: “Batch Simulation Spreadsheet” on page 683

To select nets to simulate for EMC:

1. Click EMC Nets Spreadsheet.

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2. In the EMC Enable column, select the check box for each net you want to analyze.
You can edit the value for all cells in a column or a range of cells in a column.
To sort spreadsheet rows, click the column header.
3. Edit clock frequency or duty cycle values by doing any of the following:
• Click in a frequency or duty cycle cell and type a new value.
You can edit the value for all cells in a column or a range of cells in a column.
• Click in the Net Rule cell and select a net rule name. Values from the net rule are
also applied to the signal-integrity spreadsheet and override any previous values.
4. Click OK to close the spreadsheet and return to the wizard page.

Related Topics
“Analyzing Every Net is Not Recommended” on page 729

“Managing Batch Simulation Net Rules” on page 688

Selecting Simulation Options

Use options in the Simulation Options area to specify the IC model corner, select the sources of
radiation on the board you want to monitor, and specify the distance between the board and
antenna.

To select simulation options:

1. Click an IC corner option to specify the IC model corner.

For worst-case EMC simulation, the Simulate Nets Using Fast-Strong IC Models option
usually generates the largest currents and radiation.
2. Select the check box for any radiation source on the board that you want to monitor.
On some modern boards, component packages radiate as much or more than board
traces, especially IC packages.
The Multipath From Earth Ground check box should almost always be selected. For
information, see “Enabling Multipath Correction” on page 911.
3. Select the distance between the board and antenna.
If you plan to test the board in an EMC lab, you may want to select the same distance
that you plan to use in the lab testing.
Restriction: Batch simulation does not support the current probe, which is available in
interactive simulation.

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Selecting Regulatory Constraints

Use options in the Regulatory Constraints area to select standard or user-defined EMC limits.

See also: “Choosing Regulatory Limits” on page 905, “Defining User EMC Limits” on
page 905

To select regulatory constraints:

1. Select the check boxes for any regulatory types and classes you want to test against.
2. If you selected the User-Defined check box in the previous step, do the following:
a. Click Define Limits. The Edit User-Defined Limits dialog box opens.
b. Specify the limits you want to test against by typing the values into the boxes.
c. Click OK.

Related Topics
“Batch Simulation Flow” on page 651

Selecting Nets for Quick Analysis

Use the Quick Analysis Nets Spreadsheet to specify the nets on which to run Quick Analysis.

Quick Analysis takes only a few moments to run on small boards. However it may take several
minutes to run on very large boards with many nets. To exclude some nets from Quick Analysis,
you can sort the spreadsheet to help identify uninteresting nets. For example, to exclude very
short nets during Quick Analysis, you can sort by net length.

1. Click Quick Analysis Nets Spreadsheet.

2. In the QA Enable column, select the check box for each net you want to analyze.
You can edit the value for all cells in a column or a range of cells in a column.
To sort spreadsheet rows, click the column header.
3. Click OK to close the spreadsheet and return to the wizard page.

Related Topics
“Batch Simulation Spreadsheet” on page 683

“Batch Simulation Flow” on page 651

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Editing Driver and Receiver Options for Signal-Integrity

Analysis
Use the Set Driver/Receiver Options for Signal-Integrity Analysis page in the batch simulation
wizard to specify various IC driver and receiver options.

To set driver/receiver options:

1. For nets with multiple drivers, if you want each driver to take a turn driving the net in a
separate simulation, select the Driver "round robin" check box.
If you plan to run crosstalk simulation, note that round robin does not automatically
enable drivers on aggressor nets coupled to the selected net. To automatically enable
drivers on aggressor nets, enable the Exhaustive Round-Robin Method option on the Set
Options for Crosstalk Analysis page.
If you enable round robin, nets with multiple bidirectional, three-state, open-drain, or
open-collector IC pins are simulated multiple times, once for each driver driving the net.
See also: “round robin” on page 1965, “Editing Crosstalk Analysis Options” on
page 737
2. In the IC corners area, select the check box for any of the IC model strengths you want
to use.
The IC corner options correspond to the IC operating parameters in the oscilloscope. For
information about the set of IC model parameters used for each corner, such as driver
currents and package parasitics. See “Setting IC Operating Parameters” on page 551.
If you are interested in the best-case and worst-case corner simulations, select the check
boxes for the fast-strong IC and slow-weak IC options because it is unlikely the typical
IC results will exceed the corner results. To save time and need only approximate
results, select the typical IC corner option.
This setting does not apply to crosstalk simulations, which always use the fast-strong
corner. See “Crosstalk Simulation Uses Fast-Strong Drivers” on page 719.
3. In the IC-model voltage references area, click one of the following:
• Always use model's internal values—Always use the internal voltage specified in
the IC model.
• Automatically use a power-supply net connected to the IC—BoardSim
automatically finds and assigns the Vss and Vcc power-supply nets for the IC pin.
Restriction: This option has no effect on IC pins whose Vcc or Vss pins you
specified, in the Assign Models dialog box, to "Use model's internal values."
Use the power-supply editor to specify power-supply net voltage.

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See also: “Assigning Power Supplies to ICs” on page 478, “Editing Power-Supply
Nets” on page 281
4. To vary power supply voltages with the IC corners you enabled in step 2, select the
When simulating, vary voltage references values with IC corners check box. See
“What IC Operating Settings Mean” on page 552.

Related Topics
“Batch Simulation Flow” on page 651

Editing Delay and Transmission-Line Options for Signal-

Integrity Analysis
Use the Set Delay and Transmission-Line Options for Signal-Integrity Analysis page in the
batch simulation wizard to specify delay and impedance calculation options for signal integrity
analysis.

This topic contains the following:

• “Enabling Flight-Time Compensation” on page 734

• “Including the Effects of Coupled Neighboring Nets” on page 735
• “Specifying Global Crosstalk Threshold Voltage” on page 735

Enabling Flight-Time Compensation

A portion of the pin-to-pin delay specified in an IC model, such as from clock to output,
includes the duration of the signal transition between T=0 and Vmeasure as it switches into the
test fixture load specified by the IC model. However the PCB interconnect load rarely matches
the test fixture load, so the duration of the signal transition between the start of simulation and
Vmeasure is different during PCB simulation and system operation than predicted by the IC
model.

Batch simulation can automatically produce delay times from driver IC pins to receiver IC pins
(flight times), that compensate for the difference between the test fixture load and the PCB
interconnect load. You can use compensated flight times in spreadsheets used to manage timing
budgets for system-level signals.

Restriction: If the IC model does not contain test fixture load and Vmeasure information, batch
simulation cannot calculate flight time and reports this condition in the report file.

Enable Flight-Time Compensation

To enable flight-time compensation:

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• Select the Flight-time compensation check box.

See also: “Flight-Time Compensation” on page 693

Including the Effects of Coupled Neighboring Nets

You can include coupled nets in signal integrity simulations. For information about high-
accuracy signal integrity mode and when you might want to enable it, see “High-Accuracy
Signal-Integrity Simulations” on page 719.

To include the effects of coupled neighboring nets:

• Select the Include coupling to neighbor nets when calculating t-line impedances and
delays check box.
Restriction: The BoardSim Crosstalk license is required for this option.

Specifying Global Crosstalk Threshold Voltage

Use the edit box to specify the crosstalk threshold used for Quick Analysis and high-accuracy
signal integrity simulations.

Batch simulation uses the crosstalk threshold value to:

• Determine which aggressor nets to consider for each victim.

• Identify, with a warning, victim nets that exceed the value.
The crosstalk threshold value determines how data are reported in the Crosstalk Report-Quick
Analysis section of the standard report. The lower you set the threshold, the more aggressor nets
will be listed for each victim net. The crosstalk threshold value also acts as a warning threshold.
If the total induced voltage on the victim net contributed by the strongest aggressor nets exceeds
the crosstalk threshold value, the victim net is reported as a violator in the report file.

You might want to increase the crosstalk threshold value:

• If there is a large number of aggressor nets listed for each victim net and you prefer to
list only the strongest aggressors.
• If too many nets are flagged with violations warnings.
You might want to decrease the crosstalk threshold value:

• If the design has an unusually tight crosstalk noise budget.

• The driver IC voltage swing is very low.
• If previous batch simulation results show little crosstalk and you simply want to see
more data in the report.

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To specify global crosstalk threshold voltage:

• In the For Quick Analysis Or High-Accuracy SI Simulations, Include Nets With

Coupled Voltages Greater Than box, type a value (in mV).
This value does not apply to detailed crosstalk simulations.

Related Topics
“High-Accuracy Signal-Integrity Simulations” on page 719

“Batch Simulation Flow” on page 651

Editing Default IC Model Properties

Use the Default IC Model Settings page in the batch simulation wizard to define the IC model
properties for quick analysis to use when simulating nets without driver ICs. For example if the
board has ten nets and you specify driver IC models for two of the nets, then quick analysis uses
IC model properties defined on this page when simulating the remaining eight nets.

When simulating crosstalk in detailed simulation, batch simulation uses the default IC model
properties to make judgements about whether neighboring nets with missing IC models are
coupled to the selected net, and should be simulated as aggressor nets.

Requirement: The BoardSim Crosstalk license is required to run crosstalk simulation.

This topic contains the following:

• “Specifying Default IC Model Settings” on page 736

• “Tips on Setting Default Rise-Fall Time” on page 736
• “Tips on Setting Other Parameters” on page 737

Specifying Default IC Model Settings

To specify default IC model settings:

• Type values into the boxes.

The values you set for batch simulation are independent from the values you set for interactive
crosstalk simulation (Setup menu > Crosstalk Thresholds > Change Default IC Model button).
However, for simplicity, you probably will use the same values in both places.

Tips on Setting Default Rise-Fall Time

The most important default IC model setting is rise/fall time.

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• Use a switching time that represents the switching time for the worst-case driver IC that
is most commonly used on the board.
Example: If the board has many ICs with rise/fall times of 2-3 nanoseconds, just a few
ICs with rise/fall times of 5-10 nanoseconds, and just a few ICs with rise/fall times of
0.5-1 nanoseconds, then a good value would be two nanoseconds.
• Use the rise/fall times representing the 0%-100% voltage points of the switching
waveforms. Do not use the 10%-90% or 20%-80% voltage points.
• You can run quick analysis for each important subset of IC switching times.
Example: If you have an important set of nets with ICs that switch in three nanoseconds
and another important set of nets with ICs that switch in one nanosecond, run quick
analysis twice, once with each switching time. Note that if you do run batch simulation
twice, be sure to save each report with a different file name.
• If the faster-switching ICs on the board have asymmetric rise/fall times, such as the
falling edge is consistently faster than the rising edge, use the time representing the
faster edge. The faster edge will nearly always constrain the signal-integrity problems
for the board.

Tips on Setting Other Parameters

If you know good approximate values for the non-rise/fall time parameters, then use them.
Otherwise you may want to use the values provided in the Hints area in the dialog box.

Related Topics
“Batch Simulation Flow” on page 651

Editing Crosstalk Analysis Options

Use the Set Options for Crosstalk Analysis page in the batch simulation wizard to specify
options related to crosstalk analysis.

This topic contains the following:

• “Editing Detailed Crosstalk Analysis Options” on page 738

• “Specifying Nets to Include in Crosstalk Report-Quick Analysis” on page 739
• “Calculating the Number of Round Robin Simulations” on page 739
Requirement: The BoardSim Crosstalk license is required to run crosstalk simulation.

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Batch Simulation Wizard Dialog Box Help

Editing Detailed Crosstalk Analysis Options

In a preceding wizard page you specified in a spreadsheet the nets to simulate and their crosstalk
threshold voltages. During batch simulation, the specified net automatically becomes the victim
and neighboring nets that are coupled to it become aggressors. Batch simulation holds the driver
IC on the victim net low or high (the victim net does not switch) while toggling driver ICs on
aggressor nets high and low to generate crosstalk.

Use the options in the Crosstalk Analysis - Detailed Simulations area to enable crosstalk
simulation for specified nets, to specify whether to use manual or round robin driver-enable
settings on aggressor nets, and to report crosstalk on specified nets that exceed the value in the
Max Crosstalk column of the signal-integrity spreadsheet.

To edit detailed crosstalk analysis options:

1. Select the Crosstalk simulation check box to enable detailed crosstalk simulations and
to enable the other options in this procedure.
2. To hold the victim net at the low or high state while aggressor nets toggle, enable any of
the following options:
• Selected nets as victims, stuck low—Run simulation with the selected/victim net
stuck low and drive neighboring aggressor nets high, then low.
• Selected nets as victims, stuck high—Run simulation with the selected/victim net
stuck high and drive neighboring aggressor nets low, then high.
Recommendation: If you enable only one of the two stuck options, enable stuck low.
For most driver ICs, the impedance of the low stage is lower than or equal to the
impedance of the high stage; therefore worst-case reflections of crosstalk signals come
from the low stage. Simulating both stuck states increases the batch simulation run time.
The Max Crosstalk column in the signal-integrity spreadsheet determines which
aggressor nets to include in crosstalk simulation. The Max Crosstalk value is used both
to identify aggressor nets and as a reporting trigger (observed crosstalk above the value
is written to the report file).
3. For aggressor nets with more than one driver, enable one of the following driver-
enabling options:
• By user settings (one case)—Before starting the batch simulation wizard, you
interactively enable the driver on aggressor nets.
• Exhaustive round-robin method—Batch simulation automatically enables drivers
on aggressor nets, one driver at a time and in separate simulations, up to the number
specified in the Max box.
If you manually enable two or more drivers on a net, round robin assumes they must
be enabled and disabled together, and does not create separate crosstalk simulations
for them.

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See also: “round robin” on page 1965, “Calculating the Number of Round Robin Simulations”
on page 739, “Driver IC Behavior During Batch Crosstalk Simulation” on page 718

Specifying Nets to Include in Crosstalk Report-Quick Analysis

You can specify which nets to write to the Crosstalk Report-Quick Analysis section of the
standard report file.

To specify nets to include, click one of the following options:

• Only nets whose crosstalk exceeds the electrical threshold

• All nets

Calculating the Number of Round Robin Simulations

The number of simulations needed to run round robin (see “round robin” on page 1965) in batch
simulation depend on the number of drivers on the selected net and the following round robin
options that you enable:

• You instruct round robin to enable drivers on the selected net (signal integrity
simulation) or victim net (crosstalk simulation).
See also: “Automatically Enabling IC Driver Pins on Selected-Victim Nets-Round
Robin” on page 662
• You instruct round robin to enable drivers on aggressor nets (exhaustive round-robin
crosstalk simulation option) and specify the value in the Max box.
See also: “Editing Detailed Crosstalk Analysis Options” on page 738
Because the above options can be enabled independently, use Table 15-12 to calculate the
number of simulations needed for round robin.

Table 15-12. Calculating the Number of Round Robin Simulations

Enable Drivers Enable Drivers Equations
on Selected Net on Aggressor
or Victim Net Nets
Yes No Equation 1: (number of drivers on selected/victim net) x (1
+ number of enabled victim stuck options in step 2)

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Table 15-12. Calculating the Number of Round Robin Simulations (cont.)

Enable Drivers Enable Drivers Equations
on Selected Net on Aggressor
or Victim Net Nets
No Yes Equation 2: Whichever is fewer:

• [(number of drivers on aggressor net 1) x ... x (number

of drivers on aggressor net N)] x (number of enabled
victim stuck options in step 2), where N is the number
of aggressor nets.
• Value in the Max box

Examples:
• If three aggressor nets exist, each with two drivers, and
you enable both victim stuck low and victim stuck high
options, the number of crosstalk simulations for the
selected victim net is [2 x 2 x 2] x 2 = 16.
• If four aggressor nets exist, each with four bidirectional
pins, and you enable only the victim stuck low option in
step 2, the number of simulations needed is [4x4x4x4] x
1 = 256. But if you set Max to 100, batch simulation will
not run 156 of the possible simulations for that net.
Yes Yes (Equation 1) x (Equation 2)

Related Topics
“Driver IC Behavior During Batch Crosstalk Simulation” on page 718

“Batch Simulation Flow” on page 651

Editing Quick Analysis Interconnect Statistics Options

Use the Quick Analysis Interconnect Statistics page in the batch simulation wizard to select the
interconnection statistics that you want written to the report file. If you are not interested in
some types of statistics, you can reduce clutter in the report file by not selecting them.

While the meaning of each option label is largely self evident, the Total Trace Delay option
needs some further explanation. If you select this option, quick analysis reports the summed
propagation delay for all trace segments. You run detailed simulations, however, to get driver-
to-receiver delay, which includes net topology, possible reflections and ringing, receiver
thresholds, and so on.

To select interconnect statistics:

• Select the check boxes for the types of statistics you want written to the report file.

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Related Topics
“Batch Simulation Flow” on page 651

Editing Shared Signal-Integrity and Crosstalk Analysis

Options
Use the Set Options for Signal-Integrity and Crosstalk Analysis page in the batch simulation
wizard to specify whether to include the effects of transmission-line loss, and via L and C,
during detailed simulation.

Requirement: The BoardSim Lossy Lines and Via Models licenses are required to run lossy
and advanced via simulation.

To edit lossy, and via L and C, detailed simulation options:

1. To simulate conductor and dielectric loss, including skin effect, select the Simulate loss
check box.
2. To include the effects of via L/C during simulation, select the Include via L and C
check box.
If you do not have the Via Models license, you can enabled lumped C simulation by selecting
the Include via C check box.

Related Topics
“Batch Simulation Flow” on page 651

Editing Terminator Wizard Reporting Options

Use the Terminator Wizard page in the batch simulation wizard to specify the types of
information created by the Terminator Wizard that you want to include in the standard report.
You can suppress information you do not plan to use to reduce clutter in the report.

To edit Terminator Wizard reporting options, select or clear the check box for any of the
following options:

• Total IC input capacitance

• Effective trace impedance—The nominal characteristic impedance of a trace whose
value has been adjusted to account for the presence of lumped IC capacitance loading.
• Termination length violations—Normally you would enable the Termination Length
Violations option because that is a primary benefit of the Terminator Wizard.
• Do not report length violations if any resistors found on net—Report length
violations only if net connects to <350 ohm resistor.

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Restrictions:

• The Total IC Input Capacitance and Effective Trace Impedance options are unavailable
if the Suggest Termination Changes and Optimal Values check box is cleared on the
Overview (first) page of the wizard.
• The Termination Length Violations and Do Not Report Length Violations If Any
Resistors Found On Net options are unavailable if the Show Signal-Integrity Problems
Caused by Line Lengths check box is cleared on the Overview (first) page of the wizard.

Recognizing Resistors as Terminators

The Terminator Wizard considers a net to be terminated if it connects to a resistor with a value
of less than 350 ohms. The reason for this resistance value is that some nets have high-
impedance pullups, such as 10,000 ohms. Without this 350 ohm threshold, the Terminator
Wizard would treat the 10,000 ohm pullup as a DC parallel terminator with a bad value, and
then attempt to recommend a better value for it.

Since the pullup is not really intended to function as a terminator, the Terminator Wizard
ignores the pullup entirely.

To enable the Terminator Wizard to consider a net to be terminated if it connects to a resistor of

any value, select the Do Not Report Length Violations if Any Resistors Found on Net check
box.

Related Topics
“Batch Simulation Flow” on page 651

Editing Batch Simulation Audit and Reporting Options

Use the Select Audit and Reporting Options page in the batch simulation wizard to specify the
report file name and location, IC model audit options, and report display options.

This topic contains the following:

• “Editing Report File Name and Path” on page 742

• “Editing Audit Options” on page 743
• “Opening Reports Automatically” on page 743
• “Saving Waveform Files From Generic Batch Simulation” on page 744

Editing Report File Name and Path

To edit the batch simulation report file name and path, do any of the following:

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• To change just the file name, type the new name into the box.
• To change the path, either type the fully-qualified path or relative path.
The <design> folder is the reference location for relative paths. See “About Design Folder
Locations” on page 1391.

Examples:

• DEMO is equivalent to
C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx\HypFiles\DEMO.RPT.
• ..\DEMO is equivalent to
C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx\DEMO.RPT.

Editing Audit Options

Detailed signal-integrity, EMC, and crosstalk simulations can run for hours on large boards with
many nets. To use your time efficiently, batch simulation can report common set up problems
prior to running detailed simulations. Examples of set up problems that can prevent running
detailed simulations include missing IC models, no enabled driver on net selected for
simulation, and IC model syntax errors.

To edit audit options:

1. Click any of the following:

• Run batch simulation only (no audit)
• Run audit only (no batch simulation)
• Run both audit and batch simulation
2. To run DC simulation during audit, select the Include DC simulation in audit check
box.
This option provides the most robust audit reports, but DC simulation can take several
minutes to complete for large boards with many nets.

Opening Reports Automatically

Batch simulation can automatically open some types of report files upon completion of
simulation. All report files are always created, except for the optional audit file, regardless of
which automatic report opening options you enable.

To open batch simulation reports automatically:

1. Select any of the following check boxes:

• ... audit report file

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• ... summary report file

• ... detailed *.XLS file—XLS is the native format for Microsoft Excel
If the computer is running under Windows and no applications are associated with XLS
files, then batch simulation does not open the XLS file.
2. If you enable the XLS option, select either of the following check boxes:
• If opening *.XLS , auto-format and show errors in red
• Report limits and margins—Add columns that contain limits and margins data.
See Figure 15-23.

Figure 15-23. Generic Batch Simulation - Example Limits and Margins Columns

Saving Waveform Files From Generic Batch Simulation

You can save simulation waveforms to comma-separated value (CSV) files so you can view
them at a later time with the oscilloscope.

To save waveform files:

1. Select the Save waveforms check box.

2. Type the location of the saved waveform files.
Batch simulation writes waveform files to the Batch_Results folder at the location you
specify.
The initial Save To Directory box value comes from the option you enable in the top box
in the Set Directories dialog box. See “Set Directories Dialog Box” on page 1854.

Related Topics
“Loading Waveform Files” on page 598

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“Viewing Batch SI Simulation Reports” on page 663

“Batch Simulation Flow” on page 651

Running Simulation and Showing Results

Use the Run Simulation and Show Results page in the batch simulation wizard to start batch
simulation.

This topic contains the following:

• “Starting Batch Simulation” on page 745

• “Searching the Standard Report for Signal-Integrity Violations” on page 745
• “Stopping Batch Simulation Before it Completes” on page 746

Starting Batch Simulation

To start batch simulation:

• Click Finish.

Searching the Standard Report for Signal-Integrity Violations

If you selected the Open the Summary Report File option on the Select Reporting Options page,
batch simulation automatically opens the report file in the HyperLynx File Editor.

If a net, or any associated net, violates a constraint you specified for detailed signal integrity or
EMC simulation, a warning and description of the problem is written to the report. Two classes
of warnings exist: warnings and severe warnings. While either type of warning merits attention,
severe warnings may indicate particularly troubling problems.

For signal integrity results, stub-length violations are classified as severe warnings because they
indicate problems in the layout that are extremely difficult to fix unless the lengths themselves
are reduced. Examples include series-terminator-driver-to-resistor lengths or AC-terminator-
resistor-to-capacitor lengths that are too long.

For EMC results, a warning is generated if the worst-case excess frequency exceeds a limit by
less than or equal to 6 dBuv/m (a linear factor of two). A severe warning is generated if the
result exceeds a limit by more than 6 dBuv/m. If you enable multiple test limits, the warning
contains information about the worst case violation, such as the radiation level at the frequency
that most exceeds the smallest limit.

Searching for Signal-Integrity Violations

To search for signal integrity violations using the HyperLynx File Editor:

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• Find Warning button or Find Warning Severe button .

The Find Warning and Find Warning Severe buttons appear only when batch simulation opens
the HyperLynx File Editor.

To search for signal integrity violations, using another text editor:

• Search for either "** Warning **" or "** Warning(Severe) **".

Stopping Batch Simulation Before it Completes

You can force batch simulation to stop running before it completes. For example, you may
remember that you set up something incorrectly, or batch simulation is taking longer to
complete than you expected.

To stop batch simulation:

• Click Cancel.

Result: Batch simulation prompts you to save your settings, finishes analysis of the
current net, and then opens the report file.

Related Topics
“Viewing Batch SI Simulation Reports” on page 663

“Batch Simulation Flow” on page 651

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 Chapter 16
Simulating Multiple-Board Designs

Welcome to the HyperLynx MultiBoard option. This add-on to the base BoardSim product
extends the capabilities of BoardSim to include signal-integrity analysis of multiple board
designs.

With the MultiBoard option, you can:

• Simulate signal integrity and crosstalk on nets that span two or more boards
• Run generic batch simulation on all the boards in your multiple board design
• Simulate DDRx memory interfaces
• Use the current probe on a net that spans two or more boards
Restrictions:

• The MultiBoard license is required to run MultiBoard simulations.

• The Advanced MultiBoard license is required to assign advanced interconnect models.
• The GHz license bundle is required to simulate advanced interconnect models with
Touchstone files assigned to them.
• The DDRx Wizard license is required to run DDRx simulation.
• You cannot include CADCAM Professional (.CCE) files in MultiBoard projects.
• Power-integrity simulation is unavailable when a MultiBoard project is loaded.
This topic contains the following:

• “Getting Started with MultiBoard” on page 748

• “MultiBoard Project Limitations” on page 748
• “Modeling Board-to-Board Interconnections” on page 750
• “MultiBoard Project Wizard Overview” on page 752
• “Creating or Editing MultiBoard Projects” on page 758
• “Dialog Box Help for MultiBoard” on page 758
• “Saving Session Edits for Multiple Board Instances” on page 769

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Getting Started with MultiBoard

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

Getting Started with MultiBoard

Before you can load your multiple board design into BoardSim, you run the MultiBoard Project
Wizard to create a MultiBoard project file (.PJH) that contains the following information:

• Names of the boards in your multiple board design

• Board-to-board interconnection mapping
• Electrical characteristics for board-to-board interconnections
As BoardSim loads the MultiBoard project, it automatically loads all the boards in your
multiple board design, the board-to-board interconnection mapping, and the interconnection
electrical characteristics. When loading is complete, all the boards are displayed in the board
viewer. BoardSim is now ready to analyze your MultiBoard project.

The next time you want to analyze your MultiBoard project, you will load the MultiBoard
project file (.PJH) directly into BoardSim. To edit your MultiBoard project, load it into
BoardSim and open the wizard.

Requirement: If you copy a MultiBoard project file from Windows to Solaris, replace all DOS
carriage return characters with UNIX end-of-line (eol) characters. The HyperLynx File Editor
File can save files with UNIX formatting.

MultiBoard Project Limitations

This topic contains the following:

• “Unavailable Features” on page 748

• “Maximum Number of Boards” on page 749

Unavailable Features
Table 16-1 summarizes the features that are not available when a MultiBoard project is loaded
into BoardSim:.

Table 16-1. MultiBoard - Unavailable Features

Unavailable Feature Comments

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Table 16-1. MultiBoard - Unavailable Features (cont.)

EMC radiated emissions The radiated emissions antenna probe for EMC analysis is not
analysis available for your MultiBoard project. The reason is that
BoardSim does not know the physical orientation or position
of the boards in your MultiBoard project relative to each other.

However the spectrum analyzer current probe for EMC

analysis is available to identify nets with high current flow
(which is the ultimate source of radiation from your board).

See also: “Reasons to Use the Current Probe” on page 907

Terminator Wizard
Back annotation
Saving edits to .REF file BoardSim automatically re-creates the MultiBoard .REF file
every time you load the MultiBoard project, which means that
you will lose any edits you make in the REF-File Editor while
the MultiBoard project is loaded.

To make .REF file changes, edit the .REF file for individual
boards by loading them into BoardSim one at a time.

Maximum Number of Boards

Table 16-2 lists the factors that can limit the number of boards in a MultiBoard project:
Table 16-2. MultiBoard - Maximum Number of Boards
Resource Resource Consumption Details
Physical memory on your A MultiBoard project consumes the physical memory needed
computer to run BoardSim (before loading a board), plus the memory to
load all the individual boards in your MultiBoard project into
BoardSim at the same time.
Metal layers available to a The number of metal stackup layers (e.g,. signal, plane)
MultiBoard project is 252 consumed by all the boards in your MultiBoard project cannot
exceed 252.

If a board is used more than once in your MultiBoard project,

the metal stackup layers for only one copy (i.e., instance) of
the board are consumed. For example, if a memory module
with five metal layers were used four times in your MultiBoard
project, only five metal layers would be consumed (not 20).

The number of dielectric stackup layers is not limited.

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Modeling Board-to-Board Interconnections

Modeling Board-to-Board Interconnections

MultiBoard projects include the electrical properties of board-to-board interconnections, which
may be implemented as card edge connectors, multiple conductor cables, or other connection
types.

This topic contains the following:

• “Types of Board-to-Board Interconnection Models” on page 750

• “Mated and Unmated Electrical Characteristic Values” on page 751
• “Nets are Associated by Interconnect Models” on page 751

Related Topics
“Defining Interconnect Electrical Characteristics” on page 763

Types of Board-to-Board Interconnection Models

You can represent the electrical properties of an interconnection with any of the following
models:

• Short—Electrically short together the pins on different boards. This model effectively
removes the connector from the circuit.
Use this model for “what if” investigations by seeing how simulation results are affected
by including and excluding the effects of the interconnect.
• Simple—Use the interconnection model built into BoardSim and specify either of the
following sets of values:
o RLC
o R, Z, delay
See “About Simple Interconnection Models” on page 750.
• Advanced—Use a SPICE or S-parameter model.

About Simple Interconnection Models

Two transmission lines connected by a resistor comprise the simple interconnection model, as
illustrated by Figure 16-1.

Figure 16-1. Electrical Model of MultiBoard Interconnection Model

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When defining the transmission line model for the interconnection, you can specify electrical
characteristics in either of the following forms:

• R, L, C
• R, Delay, Z0
where:

The electrical characteristics you specify for a simple interconnection model in the MultiBoard
wizard are distributed evenly between the two transmission lines in Figure 16-1.

Connector vendors typically specify electrical characteristics as a set of R, L, C values. By

contrast, cable vendors typically specify electrical characteristics as a set of R, Delay, and Z0
values. When you enter one set of values, the wizard automatically calculates and displays the
values for the other set. For example, if you were to enter R, L, C data for your connector, the
wizard automatically displays the equivalent Delay and Z0 values.

Mated and Unmated Electrical Characteristic Values

The electrical characteristic value of an interconnection depends on whether it is mated or
unmated with its other half. Connector and cable vendors typically supply mated electrical
characteristic values.

Special Case - Edge Connector

BoardSim automatically takes the PCB trace into account during simulation. If data are
available, enter the unmated electrical characteristic values for the non-PCB side of the edge
connector into the appropriate MultiBoard wizard page.

Nets are Associated by Interconnect Models

The Simple interconnect model contains a resistor and the net on one side of the interconnection
is conductively associated with the net on the other side of the interconnection. This
connectivity enables Boardsim to find nets on all boards associated with the selected net. When
you select a net connected to a Simple interconnect model, BoardSim also selects its associated
nets on all boards.

The Advanced interconnect model, such as an S-Parameter or SPICE model, does not provide
port-to-port connectivity information that BoardSim can use. When you select a net connected
to an Advanced interconnect model, BoardSim selects all nets connected to the model. For large
connectors, potentially very many nets are selected for simulation, but you can disable
simulation for unwanted nets by disabling probes in the oscilloscope.

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Related Topics
“Defining Interconnect Electrical Characteristics” on page 763

“Associated Nets” on page 272

MultiBoard Project Wizard Overview

Use the MultiBoard wizard to create the MultiBoard project file (.PJH). The wizard consists of
a series of pages where you enter information about your multiple board design. After you
complete information entry, the wizard writes the information into the MultiBoard project file
(.PJH). As a convenience, the wizard also loads the MultiBoard project into BoardSim and
displays it in the board viewer when you click Finish in the last page.

After you save the MultiBoard project, you can load it directly (that is, without using the
wizard) from the File menu.

This topic contains the following:

• “About Board IDs” on page 752

• “Mapping a HYP File to a Board ID” on page 753
• “Interconnection Mapping Options” on page 754
• “Inserting New Board Files” on page 756
• “Deleting Interconnected HYP Files” on page 756
• “Inserting New Interconnection Mappings” on page 757
• “Edit Box Tips for the MultiBoard Project Wizard” on page 757

Related Topics
“Opening MultiBoard Projects” on page 60

“Creating or Editing MultiBoard Projects” on page 758

About Board IDs

Board IDs are used to identify individual boards in your MultiBoard project to BoardSim. The
board ID value (such as B01) is set when you choose board files for your MultiBoard project
using the MultiBoard wizard. To see how boards are added to the MultiBoard project and when
board IDs are assigned, “Choosing Board Files for the MultiBoard Project” on page 760.

You will specify a board ID when selecting nets, placing oscilloscope probes, editing stackups,
and other analysis setup operations. Similarly, BoardSim uses board IDs to identify oscilloscope

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probe placement in the board viewer, reporting batch simulation results, and in many dialog
boxes.

Use the "Design File" list to select a board ID when setting up your analysis. The Design File
list is displayed in the dialog boxes when a MultiBoard project is loaded into BoardSim.

Mapping a HYP File to a Board ID

The wizard assigns a unique board ID to each board file in your MultiBoard project. The board
ID, not the board file name, is used by BoardSim's dialog boxes and board viewer to identify a
particular board.

The board ID values start with "B00" and increment by one (e.g. B00, B01, B02). The board ID
values are contiguous, so there are no gaps in the sequence. If you delete (or add) boards from
your MultiBoard project using the wizard, the subsequent board ID values automatically
decrement (or increment).

Multiple copies (i.e. instances) of a board file are assigned different board IDs. For example, if a
board file for a memory module is used four times in your MultiBoard project, the wizard
assigns each instance a different board ID.

To lookup the board ID to board file mapping, edit the MultiBoard project to bring up the
wizard page that contains the board file names and their board IDs. Click Cancel to preserve the
.PJH file. See “Creating or Editing MultiBoard Projects” on page 758 for details.

Depending on the BoardSim dialog box, the board ID is used to display data for a particular
board or is used to identify which board a net or component is associated with.

To change the list of board files in your MultiBoard project, see “Choosing Board Files for the
MultiBoard Project” on page 760.

Board IDs Used to Display Data for a Particular Board

In some dialog boxes, the board ID is used to display data for a particular board (i.e. data for
other boards are filtered out). The Design File list is used to select a board ID from within a
BoardSim dialog box. The Design File list is absent when a MultiBoard project is not loaded.

This behavior allows you to select nets or components by the names that you are familiar with
and will reduce the quantity of nets to choose from at one time. For example, the Select Net by
Name dialog box displays only the nets for the board selected by the Design File list.

Other dialog boxes, and the board viewer, embed the board ID into the net or component name.
See "Board IDs Embedded into Net and Component Names" below in this topic.

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Board IDs Embedded into Net and Component Names

The board ID is embedded into net and component names for the BoardSim dialog boxes, and
the board viewer, which display data from several boards in a single display area.

The board ID may be added to the net or component name as a suffix, or embedded into the
name, depending on the dialog box. For example, the board viewer appends the board ID to
every component name (e.g. U3_B02). By contrast, probe names in the Probe Enable area of the
Digital Oscilloscope have the board ID embedded into them (e.g., U3_B02.12).

Other dialog boxes display data only for a particular board. See "Board IDs Used to Display
Data for a Particular Board" above in this topic.

Interconnection Mapping Options

Interconnection mapping for may be assigned on a component-to-component or on a pin-to-pin
basis. In addition, you may combine the component-to-component and pin-to-pin styles, or
leave a connector open by not mapping it.

Restriction: Advanced connector models can be assigned only on a component-to-component

basis.

This topic contains the following:

• “Component-to-Component Mapping” on page 754

• “Pin-to-Pin Mapping” on page 755
• “Combination of Mapping Styles” on page 755
• “No Mapping” on page 755
• “Special Case Example - Connectors with Different Quantity of Pins” on page 755

Related Topics
“Defining Board-to-Board Interconnection Mapping” on page 761

Component-to-Component Mapping
Component-to-component mapping occurs when you map one reference designator to another
reference designator (e.g., connector B00_J1 to connector B01_J3).

For simple connector models, all the pins between these reference designators are automatically
mapped and the same interconnect characteristic values are used for all the pins.

For advanced connector models, you manually map model ports to connector pins.

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Pin-to-Pin Mapping
Pin-to-pin mapping occurs when you map an individual pin to another individual pin. For
example, to map pin 1 for connector J1 on board B00 to pin 1 for connector J3 on board B03,
enter "B00:J1.1" and "B03:J3.1" in the interconnection mapping page. Unlike component-to-
component mapping, where all pins are automatically assigned the same interconnect
characteristic values, you can assign unique interconnect characteristic values for each pin
mapped on a pin-to-pin basis.

For simple connector models, pin-to-pin grouping (e.g., B00_J1.1-3 or B00_J1.1,2,3) is not
supported.

For advanced connector models, pin-to-pin mapping happens when you manually map model
ports to connector pins. The connector model provides interconnect characteristic values for
each pin.

Combination of Mapping Styles

A combination of component-to-component and pin-to-pin mapping styles is allowed only for
simple connector models.

For example, if you want to assign unique electrical characteristics for only the end pins for a
connector with a single row of pins, follow these steps:

1. Define component-to-component mapping to map all the connector pins.

2. Define pin-to-pin mapping for the end pins.
3. Enter electrical characteristics for the connectors mapped on a component-to-component
basis.
4. Enter electrical characteristics for the end pins mapped on a pin-by-pin basis.

No Mapping
To analyze your board with an open connector, you can map that component to the "Don't
connect" value in the right Design File list in the electrical characteristics wizard page.

Special Case Example - Connectors with Different Quantity of

Pins
To further illustrate how pin-to-pin interconnection mapping may be used, here's an example
where three small connectors (J1, J2, J3) on one board plug into a backplane connector (J4) on
another board. Please refer to Figure 16-2. Assume that J4 is part of board B00 and J1/J2/J3 are
part of board B01.

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Figure 16-2. Three Small Connectors Plugging Into One Large Connector

One valid pin-to-pin interconnection mapping for Figure 16-2 might be:

Table 16-3. Pin-to-Pin Interconnection Mapping for Previous Figure

Left Right
B00:J4.1 B01:J1.1
B00:J4.2 B01:J1.2
B00:J4.3 B01:J2.1
B00:J4.4 B01:J2.2
B00:J4.5 B01:J3.1
B00:J4.6 B01:J3.2

Table 16-3 is formatted to resemble the spreadsheet in the wizard page. See “Defining Board-
to-Board Interconnection Mapping” on page 761.

Inserting New Board Files

By default, new board files are added at the bottom of the list in the Files In This Project area in
the file selection wizard page. For convenience, you can insert a board file below a selected row
by clicking a cell in the row, or clicking the row's board ID number, then clicking the Insert
button. After the board insertion, the subsequent board ID values will automatically increment.
The wizard preserves interconnect mapping among the previous boards by automatically
adjusting the board IDs used by the mapping.

See also: “Choosing Board Files for the MultiBoard Project” on page 760

Deleting Interconnected HYP Files

The wizard will issue a warning if you delete a board that has been connected to another board.
If you proceed to delete the board, the interconnection mapping(s) associated with it will also be
deleted.

If you delete a board, any board IDs that follow it decrement by one. The wizard preserves
interconnect mapping among the remaining boards by automatically adjusting the board IDs
used by the mapping.

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See also: “Choosing Board Files for the MultiBoard Project” on page 760

Inserting New Interconnection Mappings

By default, new interconnection mappings are added at the bottom of the list in the
Interconnection List area in the interconnect mapping wizard page. For convenience, you can
insert a mapping below a selected row by clicking the row's board ID number to select the entire
row, then clicking the Insert button.

See also: “Defining Board-to-Board Interconnection Mapping” on page 761

Edit Box Tips for the MultiBoard Project Wizard

Table 16-4 provides some tips for changing the edit box values in the MultiBoard wizard board
file selection and interconnect mapping wizard pages.

Table 16-4. MultiBoard - Edit Box Tips

User input Edit operation
Click text character Activates the text box for editing and positions the
cursor at the pointer location.
Click board ID number Selects the entire row. To delete a row, it must be
selected first. A new row is inserted after the selected
row.
Change column width (temporary) The column width may be temporarily changed in the
Files In This Project and the Interconnection List areas
by dragging the splitter bar left or right. The default
column widths are restored when you leave the wizard
page.
Press ESC Warning! Pressing ESC will generally cancel the
wizard and discard changes to all of the dialog boxes.

However, pressing ESC will simply discard your

modifications when the mouse cursor is in an edit box
in either of these two wizard pages:
• List of board files in your project
• List of board-to-board interconnect mapping

If you press ESC in the interconnect electrical

characteristics page, even when the mouse cursor is in
an edit box, the wizard closes and all changes in the
wizard pages are lost.

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Creating or Editing MultiBoard Projects

Creating or Editing MultiBoard Projects

Use the MultiBoard wizard to create and edit MultiBoard projects.

To create a new MultiBoard project, perform the following steps:

1. “Creating MultiBoard Projects” on page 758

2. “Choosing Board Files for the MultiBoard Project” on page 760
3. “Defining Board-to-Board Interconnection Mapping” on page 761
4. “Defining Interconnect Electrical Characteristics” on page 763
To edit an existing MultiBoard project, perform the following steps:

1. “Editing an Existing MultiBoard Project” on page 759

2. “Choosing Board Files for the MultiBoard Project” on page 760
3. “Defining Board-to-Board Interconnection Mapping” on page 761
4. “Defining Interconnect Electrical Characteristics” on page 763

Dialog Box Help for MultiBoard

This section contains the Help topics for individual MultiBoard wizard pages. You will most
likely access the topics by clicking the Help button in a wizard page.

This topic contains the following:

• “Creating MultiBoard Projects” on page 758

• “Editing an Existing MultiBoard Project” on page 759
• “Choosing Board Files for the MultiBoard Project” on page 760
• “Defining Board-to-Board Interconnection Mapping” on page 761
• “Defining Interconnect Electrical Characteristics” on page 763
• “Assign Package / Connector Model Dialog Box” on page 767

Creating MultiBoard Projects

To create a new MultiBoard project:

1. Click New MultiBoard Project .

Alternative: Select File > New MultiBoard Project.

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2. In the MultiBoard wizard, type the project name into the Project File Name field. The
MultiBoard .PJH file is written to the <design> directory. See “About Design Folder
Locations” on page 1391.
Click the Browse button to specify a new directory or project name. When the Save As
dialog box opens, type or select the new MultiBoard .PJH file name and directory, and
click Save.

Caution
If you specify a MultiBoard project name with the same name as an existing .PJH file, the
wizard will ask whether you want to overwrite the old .PJH file. We advise caution
because BoardSim and LineSim automatically create a (non-MultiBoard) .PJH file for
each .HYP, .CCE, .FFS, and .TLN file. These .PJH files contain miscellaneous program
settings. Before overwriting an existing .PJH file, check whether it is associated with a
.HYP, .CCE, .FFS, or .TLN file. If so, consider choosing another MultiBoard project
name to avoid losing BoardSim or LineSim settings.

3. Click Next.

Caution
Data you enter in the wizard are saved only in memory until you click Finish on the last
page, when the data are written to the .PJH file. If you click Cancel within the wizard,
your new or changed data are lost.

Related Topics
“Simulating Multiple-Board Designs” on page 747

“Post-Layout Workflow” on page 49

Editing an Existing MultiBoard Project

To edit a MultiBoard project:

1. Select Edit > MultiBoard Project.

2. In the Open MultiBoard Project File dialog box, select a MultiBoard project and click
Open.

Caution
Data you enter in the wizard are saved only in memory until you click Finish on the last
page, when the data are written to the .PJH file. If you click Cancel within the wizard,
your new or changed data are lost.

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Related Topics
“Simulating Multiple-Board Designs” on page 747

Choosing Board Files for the MultiBoard Project

Use this page to manage the list of board files for your MultiBoard project.

When your multiple board design contains more than one copy (i.e., instance) of a particular
board, we generally recommend that you create a unique board file for each instance before
adding it to your MultiBoard project.

See also: “Saving Session Edits for Multiple Board Instances” on page 769

About Relative HYP File Paths

The wizard records a relative file path (e.g., ".\") in the Directory text box when you add board
files stored in the <design> directory to the MultiBoard project. See “About Design Folder
Locations” on page 1391.

Otherwise the wizard records the fully qualified file path (e.g., c:\project1\hypfiles). The
relative file path value allows you to move your MultiBoard project files (i.e. .PJH and board) to
another directory and open your MultiBoard project without having to specify the new fully
qualified file path in the PROJECT_SUB_FILES section of the MultiBoard project file (.PJH).

Choosing a Board File

To choose the board files:

1. To add a board file to the MultiBoard project, click Insert.

2. Double-click the board file you want to add to the MultiBoard project.
Alternatives:
• Select one or more board files and click Open. Select multiple board files by
pressing CTRL+Click to select an additional board file or by pressing SHIFT+Click
to select a range of board files.
• Type in the board file name and click Open.
See also: “Inserting New Board Files” on page 756
3. Optionally, type a comment into the Comment box to help you associate the board ID
with your board. The comment will appear beside the board ID and interconnection
mappings in subsequent wizard pages. If you leave the Comment text box blank, the
board file name (without the extension) becomes the default Comment value.
4. If needed, type a new value into the Design File or Directory boxes.

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Click the file folder icon in the Design File column. When the Open BoardSim File
dialog box opens, select the new file name or directory.
5. To delete a file, click the board ID to select the entire row, and then click the Delete
button. The wizard will display a warning if you delete a board that is connected to
another board.
See also: “Deleting Interconnected HYP Files” on page 756
6. Repeat steps 1-5 as needed.
7. Click Next.

Related Topics
“Simulating Multiple-Board Designs” on page 747

Defining Board-to-Board Interconnection Mapping

Use this page to specify the interconnection mapping between your boards. The electrical
characteristics for the interconnections mapped in this page are defined in the next page.

Available interconnect mapping styles:

• Component-to-Component
• Pin-to-Pin
• Combination of Component-to-Component and Pin-to-Pin
• No Mapping (open connector)
See also: “Interconnection Mapping Options” on page 754

Defining Connections Between Boards

Refer to Figure 16-3 in the procedure below.

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Figure 16-3. Defining Connections Between Boards

To define connections between boards:

1. Select a board in the Design file #1 list.

2. Below the Design file #1 list, select a component from the Reference Designator list.
3. Select a board in the Design file #2 list.
Select "Don't connect" to leave a component unconnected. The text
"NOT_CONNECTED" will appear on the right side of the new row in the
Interconnection List area. Skip ahead to step 5.
4. Below the Design file #2 list, select a component from the Reference Designator list.
If you had selected "Don't connect" in the previous step, the Reference Designators area
will be empty.
5. Click Insert to add the component-to-component interconnect mapping.
See also: “Inserting New Interconnection Mappings” on page 757
6. If you plan to define pin-to-pin interconnection mapping using the simple
interconnection model on the next page, you may click Insert several times to generate
several identical rows that you can edit to add pin-to-pin mapping information.
If you click Insert too many times, it is easy to delete the extra rows (see step 8).

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As a reminder, pin-by-pin interconnection mapping allows you to specify unique

electrical characteristics for each pin in the next page.
7. To define pin-to-pin interconnection mapping, append a period and the pin number (i.e.,
".1") to the reference designator in the Left and Right text boxes in the Interconnection
List area. When you define a pin value in one column, you must also define a pin value
in the other column.
If a board ID comment exists, be sure to insert the pin number before the comment (e.g.,
"B00:J1 SDRAM" becomes "B00:J1.1 SDRAM").
Restriction: Advanced connector models (assigned on the next page) do not support
pin-to-pin interconnection mapping defined on this page.
8. To delete an interconnect mapping, click the interconnection ID in the left column to
select the entire row, and then click Delete.
9. Repeat steps 1-8 as needed.
10. Click Next.

Related Topics
“Simulating Multiple-Board Designs” on page 747

Defining Interconnect Electrical Characteristics

Use this page to model the electrical characteristics for interconnections between boards.

Clicking the Finish button on this page generates the MultiBoard .PJH file, loads the
MultiBoard project into BoardSim, and opens the board viewer.

Caution
If you click Cancel, new or changed data (for all wizard pages) are lost.

Restriction: The Advanced MultiBoard license is required to assign advanced interconnect

models.

This topic contains the following:

• “About Board-to-Board Interconnection Models” on page 764

• “Assigning Shorted Interconnect Models” on page 764
• “Assigning Simple Interconnect Models” on page 764
• “Assigning, Editing, and Removing Advanced Interconnection Models” on page 765

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• “Graphically Managing Advanced Interconnect Models” on page 766

Related Topics
“Assign Package / Connector Model Dialog Box” on page 767

“Modeling Board-to-Board Interconnections” on page 750

“Simulating Multiple-Board Designs” on page 747

About Board-to-Board Interconnection Models

You can use any of the following types of models to represent the electrical characteristics of
board-to-board interconnections:

• Short—Electrically short together the pins on different boards. This model effectively
removes the connector from the circuit.
Use this model for “what if” investigations by seeing how simulation results are affected
by including and excluding the effects of the interconnect.
• Simple—Use the interconnection model built into BoardSim and specify either of the
following sets of values:
o RLC
o R, Z, delay
• Advanced—Use a SPICE or S-parameter model.

Assigning Shorted Interconnect Models

To assign electrically-shorted interconnect models:

• In the Interconnection List area, click the reference-designator pair for the connector,
and then click Short.

Assigning Simple Interconnect Models

To assign simple interconnect models:

1. In the Interconnection List area, select the reference designator for the connector and
click Simple.
2. Type values into either of the following sets of boxes:
o Resistance, Inductance, Capacitance (RLC)
o Resistance, Impedance, Delay (R, Z, delay)
See “About Simple Interconnection Models” on page 750.

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Assigning, Editing, and Removing Advanced Interconnection Models

To assign advanced interconnect models:

1. In the Interconnection List area, select the reference designator pair for the connector
and click Advanced.
2. Do any of the following:
• Click Assign.
• Click Connection Editor. In the Connection Editor dialog box, right-click over a
blank area of the picture, and then click New Model.
The Assign Package / Connector Model dialog box opens.
3. Perform the procedure described in “Assign Package / Connector Model Dialog Box” on
page 767.
To edit previously-assigned advanced models:

1. Do one of the following:

• In the Interconnection List area, in a row below the reference designator for the
connector, select the model name and click Edit.
A plus sign + at the left end of the reference designator row indicates that a
connector model row is not displayed. Double-click the row to display the model(s).
• Click Connection Editor and do any of the following:
o Double-click the connector model.
o Right-click a blank area of the model in the picture area and click Edit Model.
The Assign Package / Connector Model dialog box opens.
2. Perform the procedure described in “Assign Package / Connector Model Dialog Box” on
page 767.
To remove advanced models:

1. In the Interconnection List area, in a row below the reference designator for the
connector, select the model name and click Edit.
A plus sign + at the left end of the reference designator row indicates that a connector
model row is not displayed. Double-click the row to display the model(s).
2. Click Remove.

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Graphically Managing Advanced Interconnect Models

Use the Connection Editor dialog box to assign, edit, and remove advanced interconnect models
for the interconnection selected in the Interconnection list.

You can switch interconnections displayed in the Connection Editor dialog box by selecting a
different interconnection in the Interconnection list.

You can resize this dialog box by dragging any of its corners.

Restriction: This dialog box can also display “Short” and “Simple” connector models, but
cannot edit them.

To assign models:

1. Right-click over a blank area and click New Model.

2. In the Assign Package / Connector dialog box, assign the model, make any number of
pin connections (including zero), and click OK.
See “Assign Package / Connector Model Dialog Box” on page 767.
3. Do any of the following:
• Drag a connector pin to make or edit a connector-to-model mapping.
• To move a model port from one side to another, do any of the following:
o Double-click the port.
o Right-click the port and click Change Port Side.
• To copy the model and insert it below the existing model assignments, right-click
the model to copy and click Copy Model.
To edit models:

1. Do any of the following:

• Double-click the model.
• Right-click the model to edit and click Edit Model.
2. In the Assign Package / Connector dialog box, edit the model or pin connections, and
click OK.
See “Assign Package / Connector Model Dialog Box” on page 767.
To delete models:

• Right-click the model and click Remove Model.

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Assign Package / Connector Model Dialog Box

Use the Assign Package / Connector Model dialog box to assign passive SPICE and S-
parameter (Touchstone) models to package/connector symbols used to model series board-to-
board interconnections in a MultiBoard project.

Requirement: The BoardSim GHZ license is required to simulate S-parameter or SPICE

models.

To assign models to board-to-board connectors:

1. To filter the Libraries list, use the Model Type list to select the type of model(s) to
display.
2. Select the file containing the model to assign from the Libraries list.
3. Select the model from the Devices list.
4. To assign model ports to connector pins, do one of the following:
• To create a new mapping, in the Ports spreadsheet, do the following for each row:
i. Click the Board cell to assign the port to a board and connector instance.
ii. Click the Connection cell to assign the port to a connector reference designator,
power-supply net, or as NC (not connected).
iii. Click the Pin cell to assign the port to a connector pin.
Restriction: This cell is unavailable for ports assigned to power-supply nets or
NC.
If the connector has a large number of pins, it may be faster to use the Connection
Editor dialog box to map model ports to connector pins by graphically dragging
connector pins to model ports. See “Graphically Managing Advanced Interconnect
Models” on page 766.
To copy the contents of a spreadsheet cell to other rows, select the rows containing
both the cells to copy from and paste to, right-click over the cell to copy from, and
then click Apply to Selection.
To select multiple rows, click, press Ctrl+click, press Shift+click, or drag over the
numbered row headers.
• To import model port to connector pin mapping from an existing MultiBoard project
file (.PJH) that contains mapping that is compatible with the connector model that
you selected in step 3, click Load from PJH, type or browse to the .PJH file, and
then click Open. In the Choose Model for Copying dialog box, select the row
containing the connector model that exists in the current MultiBoard project and
click OK.

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The imported port-to-pin mapping is compatible with the selected connector model
when all of the following are true:
o The selected model and the model specified in the .PJH file have identical port
names and quantity of ports.
o The model specified in the .PJH file maps to power-supply nets and connector
pins that exist on boards on each side of the connection.
In the Choose Model for Copying dialog box, you can change the direction of the
interconnection model (by swapping the contents of the Left and Right spreadsheet
columns), by clicking Swap Boards. This function is available if the same set of
power-supply nets and pins exists on the boards on both sides of the connection.
5. To display the model file contents, click Edit Model File.
6. To pass parameters to the simulator, click Edit Parameters and specify the parameter-
value pairs.
If you use the ADMS simulator, use the Eldo CPF simulation method, and have assigned
to the port a Touchstone model that you know is strictly passive, we recommend that
you set the FORCE_PASSIVITY parameter to 1. When enforcing passivity, ADMS
tries to detect and eliminate modelling discrepancies that can lead to instability or non-
physical behavior.
If you know the model is not symmetric, we recommend that you set the SYMMETRY
parameter to 0 to avoid potentially wrong simulation results. Symmetrical models
typically contain resistance, inductance, capacitance, and inductive capacitance models,
but do not contain controlled sources.
For information about setting the CPF simulation method, see “Preferences Dialog Box
- Circuit Simulators Tab” on page 1808.
7. To update the model library path, in order to add the folder(s) containing the advanced
interconnect model, click Library Path. See “Select Directories for IC-Model Files
Dialog Box” on page 1844.
8. Click OK.

Related Topics
“Defining Interconnect Electrical Characteristics” on page 763

“Nets are Associated by Interconnect Models” on page 751

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Saving Session Edits for Multiple Board Instances

Saving Session Edits for Multiple Board

Instances
Your multiple board design may use multiple copies (instances) of a particular board, for
example several identical memory modules that plug into a PC motherboard. BoardSim's
MultiBoard project supports multiple instances of a board.

You can make the same interactive changes to all instances of a board or make unique
interactive changes to an individual instance. For example, you might interactively assign an IC
model to all instances. By contrast, you might make an unique interactive change to an
individual instance for the following reasons:

• To simulate a data bus connecting multiple memory module instances, set data bus pins
on one instance to the output direction and set data bus pins on the other instances to the
input direction.
• To configure a SCSI bus termination, add terminators only to pins on an instance
positioned at the end of the bus.
This topic contains the following:

• “Saving Changes for Each Instance or for a Selected Instance” on page 769
• “Selecting a Board Instance to Load” on page 772
• “Copying a Set of Interactive Changes to All Instances” on page 772

Related Topics
“BoardSim Session Files” on page 56

“Simulating Multiple-Board Designs” on page 747

Saving Changes for Each Instance or for a Selected

Instance
You can save the interactive changes into session edit files to make them available to future
BoardSim sessions. When saving the interactive changes for a MultiBoard project containing
multiple instances, you can save the changes for each instance or save the changes for only the
selected instance. Table 16-5 summarizes the available session edit save methods.

Table 16-5. MultiBoard - Saving Changes for Multiple Instances of a Board

Save Method Generated Session Edit File Re-opening the MultiBoard
Project

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Table 16-5. MultiBoard - Saving Changes for Multiple Instances of a Board

Each instance BoardSim creates a unique BoardSim applies the interactive
session edit file for each changes from the unique session
instance. edit file to the corresponding
instance.
Selected instance BoardSim creates a session BoardSim applies the session
edit file for only the selected edits for the selected instance to
instance. all the instances.

Session edits for the unselected

instances are not saved.
For information about the steps to save your interactive changes, see “Steps to Save Session
Edits for Multiple Board Instances” on page 770.

About Session Edit File Names When Saving Changes for Each
Instance
When you save interactive changes for all instances, the session edit files are named
<board>.XXX, where <board> is the board file name and XXX is "BUD" for the first instance
and is the board ID for additional instances. For example if two instances of the board named
MEM.HYP were assigned board ID values of B02 and B03 in the wizard, BoardSim creates
session edit files named MEM.BUD and MEM.B03. Naming the first instance session edit file
<board>.BUD allows you to open the board directly in BoardSim, outside of the MultiBoard
project.

BoardSim creates backup session edit files when you save your session edits and session edit
files already exist. When you save interactive changes for all instances, backup session edit files
are named <board>.XXX, where <board> is the board file name and XXX is "bbd" for the first
instance and is U plus the numerical part of the board ID for additional instances. For example if
two instances of the board named MEM.HYP were assigned board ID values of B02 and B03 in
the wizard, BoardSim creates backup session edit files named MEM.BBD and MEM.U03.

About the Session Edit File Name When Saving Changes for a
Selected Instance
When you save interactive changes for a selected instance, the session edit file is named
<board>.BUD, where <board> is the board file name.

Steps to Save Session Edits for Multiple Board Instances

When the MultiBoard project contains multiple instances of a board, you decide between saving
the changes for each instance and saving the changes for only a selected instance.

To save MultiBoard session edits:

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1. File menu > Save BoardSim Session File.

2. In the Save MultiBoard Session Edits dialog box, in the How to Save cell, select the way
to save session edits.
3. If you select Common File For All Instances, select from the Selected Instance list the
instance with the interactive changes you want to save.
The session edits for the non-selected instances are not saved when you select Common
File For All Instances.
4. Repeat steps 2-3 for each multiple-instance board.
5. Click OK.

Related Topics
“BoardSim Session Files” on page 56

Propagating Interactive Changes to All Instances

You can apply the interactive changes you make for one board instance to all instances or to
only the selected instance. For example you might want to apply an IC model assignment to all
instances, but apply a buffer direction assignment to only the selected instance.

The Apply To All Similar Boards check box is available from several dialog boxes when your
MultiBoard project contains multiple board instances. Select the check box to copy the
interactive change to all instances. Clear the check box to copy the interactive change to only
the selected instance.

For information about how interactive changes are saved for multiple board instances, see
“Saving Session Edits for Multiple Board Instances” on page 769.

The Apply To All Similar Boards check box is available in the dialog boxes named in
Table 16-6.

Table 16-6. MultiBoard - Scope of Apply to All Similar Boards Check Box
Interactive change type Dialog box name
IC model assignment Assign Models
Passive component value Assign Models
Quick Terminator Assign Models
Power supply voltage and nets Edit Power-Supply Nets (uses “Apply to
all instances of board” check box)
Manhattan routing Connect Nets with Manhattan routing
Unrouting Unroute Routed Nets

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Stackup and Trace Width Edits

Stackup edits and trace width edits are always copied to all instances. BoardSim does not allow
you to change the stackup or trace width for a specific instance without changing all the
instances.

In the Edit Stackup dialog box, all instances of a board are grouped together on the same row in
the Design File list (e.g., B00,B01,B02).

In the Change Trace Widths dialog box, all instances of a board are grouped together on the
same row in the Traces on Boards list (e.g., B00,B01,B02).

Selecting a Board Instance to Load

The Select the Instance dialog box opens when you have previously saved interactive changes
for each board instance in a MultiBoard project and then open the board directly with BoardSim
(that is, outside of the MultiBoard project). Use this dialog box to select the interactive edits to
apply to the board.

To select the instance to load:

• Select the instance and click OK.

Copying a Set of Interactive Changes to All Instances

If you have saved interactive changes for each instance, but now want to apply the changes for
one instance to all instances, you can copy the interactive changes made to one instance to all
the instances when you load the board.

To copy a set of interactive changes to all instances:

1. Select the instance with the interactive changes you want to copy.
The interactive changes you made to the other instances will be overwritten by the
selected instance's changes.
2. Select the check box near the bottom of the dialog box.
3. Click OK. The next time you open the MultiBoard project, the same set of interactive
changes is applied to all instances.

Related Topics
“Saving Session Edits for Multiple Board Instances” on page 769

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Simulating DDRx Memory Interfaces

Use DDRx batch simulation to analyze the standard DDR, DDR2, DDR3, LPDDR, or LPDDR2
memory interface between a memory controller device and its memory devices. Simulation
automatically reports the following timing for signal pairs in the memory interface: setup, hold,
strobe-to-clock skew, and minimum/maximum delays. Setup and hold timing measurements
include slew-rate derating for DDR2 and DDR3 designs. With this information, you can fill out
a timing budget spreadsheet and identify nets with unsatisfactory timing to investigate further.

DDRx batch simulation performs timing measurements and slew-rate derating adjustments
between pairs of signals for every cycle in the simulation. This cycle-by-cycle approach takes
into account the effects of noise or intersymbol interference (ISI) on individual waveform
transitions.

Note
Timing measurements and derating adjustments require thousands of simulations.
Running DDRx batch simulation can take tens of minutes (few measurements enabled) to
hours (all measurements enabled).

Before simulating the complete DDRx interface, you should verify the design set up by
running both interactive and DDRx batch simulation on a small subset of nets in the
DDRx interface. This sequence enables you to identify and fix set up problems more
quickly than if you immediately simulated the complete DDRx interface. See “Verifying
the Design Setup for DDRx Simulation” on page 795.

Requirements:

• The DDRx Wizard license is required to run DDRx simulation.

• The MultiBoard license is required if the DDRx interface is implemented across
multiple boards.
• The GHz license bundle is required if the DDRx interface is implemented across
multiple boards and you have assigned a Touchstone file to an advanced connector
model.
Running DDRx batch simulation includes the following main steps:

1. Preparing Designs for DDRx Batch Simulation— Gather information about the design
for the simulation. Obtain IBIS models for the controller and memory ICs. SPICE
models are not supported for DDRx simulation.

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2. Running DDRx Batch Simulation—Use the DDRx wizard to set up and run simulation.
The wizard creates a setup file that contains all the information needed to run DDRx
simulation. Advanced users can manually create or edit the setup file and load it into the
wizard. Run simulation from the last page of the wizard.
3. Analyzing DDRx Batch Simulation Results—View spreadsheets, report files, waveform
files, and so on. Spreadsheets contain timing and signal-integrity measurements. The
oscilloscope can display waveform files.

Related Topics
“DDRx Background Information” on page 797

“DDRx Batch-Mode Wizard Dialog Box” on page 847

“Simulating SI for Entire Boards or Multiple Nets” on page 651

Preparing Designs for DDRx Batch Simulation

Setting up the design for DDRx batch simulation is a mixture of general and DDRx-specific set
up tasks.

This topic contains the following:

• “DDRx Batch Simulation Requirements” on page 774

• “Gathering Information About Your DDRx Memory Interface and Design” on page 776
• “DDRx Topologies” on page 777
• “Setting Up HyperLynx for DDRx Simulation - Design Files and Models” on page 782
• “Creating Controller and DRAM Timing Models” on page 786
• “Verifying the Design Setup for DDRx Simulation” on page 795

Related Topics
“HyperLynx Timing Model Format” on page 1270

“HyperLynx DDRx Wizard Setup File Format” on page 1307

“Simulating DDRx Memory Interfaces” on page 773

DDRx Batch Simulation Requirements

• One DDRx memory interface per setup file and simulation.

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Some designs might have more than one memory interface. For example, some desktop
computer motherboards have four DIMM (dual inline memory module) slots and two
memory interfaces. If you have more than one memory interface, plan to create separate
setup files and run separate simulations.
• IBIS models with [Model Spec], [Receiver Thresholds], and [Model Selector]
keywords.
The [Model Spec] and [Receiver Thresholds] keywords provide voltage threshold and
other measurement information.
The [Model Selector] keyword identifies the on-die termination (ODT) component
model to use for DDR2 and DDR3 (but not DDR, which does not use ODT) simulation.
If the model you receive from the DRAM or controller IC vendor does not contain the
[Model Selector] keyword, you can manually add it by using the procedure in the topic
“Adding Model Selector Keywords to IBIS Models” on page 793.

Note
SPICE buffer models are not supported for DDRx simulation because they do not provide
the information supplied by the IBIS [Model Spec], [Receiver Thresholds], and [Model
Selector] keywords.

• Timing model requirements:

o Timing models must be formatted in the HyperLynx timing model format. See
“HyperLynx Timing Model Format” on page 1270.
o Default timing models are located in the Libs folder. For example,
C:\MentorGraphics\<release>\SDD_HOME\hyperlynx\Libs.
o Timing models support the timing provided by memory and controller IC datasheets.
Timing models for memory and controller ICs ship with HyperLynx. See “Creating
Controller and DRAM Timing Models” on page 786.
• Memory interfaces that conform to the following JEDEC specifications:
o DDR — JESD79E, Double Data Rate (DDR) SDRAM Specification
o DDR2 — JESD79-2F, DDR2 SDRAM Specification, JEDEC standard UDIMMs
and RDIMMs
o DDR3— JESD79-3D, DDR3 SDRAM Specification, JEDEC standard UDIMMs
and RDIMMs
o LPDDR — JESD209A
o LPDDR2 — JESD209-2B

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Specifications are available from www.jedec.org. JEDEC stands for Joint Electron
Device Engineering Council, which is an international standards organization that
governs many electrical-engineering specifications.
Use a .REF or .QPL automapping file to map IBIS and EBD models to controller and DRAM
components and optionally PLL and register components for registered DIMMs (RDIMMs).

Gathering Information About Your DDRx Memory

Interface and Design
Answer the following questions before setting up the DDRx Wizard:

• Are the DRAMs (dynamic random access memory) on main board or on DIMMs (dual
in-line memory module)?
You need to create a multi-board project in HyperLynx for designs with DIMMs.
• Are the DIMMs RDIMM or UDIMM?
• Identify the different combination of DIMM types, for example, dual rank module in
both slots or dual rank in slot1 and single-rank DIMM in slot 2).
• How many DDRx channels are on your main board?
Each DDRx channel has to be simulated separately. For example, you might have two
separate DDRx channels A and B, interfaced from one or two separate controllers. In
either case, those two channels have to be set up and simulated separately from each
other. It is also helpful to have net names in your design differentiated for each channel,
for example, DQ0_CHA, DQ0_CHB)
• How many ranks are in each DDRx channel?
Find out how many chip select signals the design has. Usually, each chip select signal
represents a rank in your design.
• What is the reference designator of the memory controller?
Tip: Open the main board in HyperLynx, select a DDRx net and find out the reference
designator for the controller from the Assign Models dialog box.
• What are the reference designators of the DRAMs that make up each rank?
Open the DIMM board in HyperLynx, select a DDRx address net and write down the list
of reference designators of DRAMs from the Assign Models dialog box.
• What is the data rate that you want to run? Make sure that the model rating supports the
required data rate.
• What is the frequency of the strobe and clock for the data rate that you are running?

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• What kind of timing are you going to use for address and command signals, for example,
1T or 2T?
• For the DDR2 interface, are you going to use the DQS signals as single-ended or
differential?
• Which ODT (on-die termination) models are you going to use to optimize the design?
• Are you including crosstalk or loss in the simulation?
• How much time is available to run the simulation?
• How much data do you want to sort through at one time?
• Which clock or strobe signal is referenced by each signal group? Identify the signal
group that you want to simulate by its function at one time (data, address, clock, and
control).
Each byte of data references to a strobe signal, for example, DQ 0-7 references to
DQS0). Table 17-1 shows the four main signal groups in a DDR2 interface.

Table 17-1. DDR2 Signal Grouping

Group Contents
Data Data Strobe DQS[8:0], Data Strobe Complement DQS#[8:0],
Data Mask DM[8:0], Data DQ[63:0], and Check Bits CB[7:0]
Address and Command Bank Address BA[2:0], Address A[15:0], and Command Inputs
RAS#, CAS#, and WE#.
Control Chip Select S[3:0]#, Clock Enable CKE[3:0], and On-die
Termination ODT[3:0]
Clock Differential Clocks CK[5:0] and CK#[5:0].

Related Topics
“DDRx Batch Simulation Requirements” on page 774

“Data Flow for DDRx Batch Simulation” on page 799

“DDRx Topologies” on page 777

“Setting Up HyperLynx for DDRx Simulation - Design Files and Models” on page 782

DDRx Topologies
This topics contains a list of common DDRx topologies and provides information about what is
supported by the DDRx Batch-Mode Wizard Dialog Box.

This topic contains the following:

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• Topology for JEDEC Standard UDIMM - DDR, DDR2, DDR3

• Topology for JEDEC Standard RDIMM - DDR and DDR2
• Topology for JEDEC Standard RDIMM - DDR3
• Topology for Non-JEDEC Standard DDRx - Register Only or PLL Only

Topology for JEDEC Standard UDIMM - DDR, DDR2, DDR3

Figure 17-1 shows the most common DDRx topology. The data, strobes, clocks, address,
command, and control signals are connected directly from the memory controller to the
SDRAMs.

DDRx Wizard Simulation Setup

• Data Bus — Simulate as a UDIMM interface.
• Address, Command, Control (Add/Cmd/Ctrl) Bus — Simulate as a UDIMM interface.
• CLK to DQS Skew — Simulate as a UDIMM interface.

Figure 17-1. JEDEC Standard UDIMM — DDR, DDR2, DDR3

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Topology for JEDEC Standard RDIMM - DDR and DDR2

Figure 17-2 shows the most common RDIMM DDR2 topology. The data and strobe signals
connect directly from the memory controller to the SDRAMs. The address, command, and
control signals connect through the register(s) to the SDRAMs. The clock signals connect
through a PLL component and are distributed to the SDRAMs.

DDRx Wizard Simulation Setup

• Data Bus — Simulate as a UDIMM or RDIMM interface. If simulated as an RDIMM
interface, the wizard still treats this bus as a UDIMM interface because the data bus is
not registered.
• Add/Cmd/Ctrl Bus from controller to Reg/PLL — Simulate as an RDIMM interface.
• CLK to DQS Skew — Simulate as an RDIMM interface.

Note
The DDRx Batch-Mode Wizard Dialog Box simulates the clock, address, command, and
control signals from the memory controller to the register/PLL device. Contact the
HyperLynx Customer Support team if you want to simulate from the register/PLL device
to the SDRAMs.

Figure 17-2. JEDEC Standard RDIMM — DDR and DDR2

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Topology for JEDEC Standard RDIMM - DDR3

Figure 17-3 shows the most common RDIMM DDR3 topology. The data and strobe signals
connect directly from the memory controller to the SDRAMs. The clock, address, command,
and control signals connect through a combined register/PLL device to the SDRAMs.

DDRx Wizard Simulation Setup

• Data Bus — Simulate as a UDIMM or RDIMM interface. If simulated as an RDIMM
interface, the wizard still treats this bus as a UDIMM interface because the data bus is
not registered.
• Add/Cmd/Ctrl Bus from controller to Reg/PLL — Simulate as an RDIMM interface.
• CLK to DQS Skew — Simulate as an RDIMM interface.

Note
The DDRx Batch-Mode Wizard Dialog Box simulates the clock, address, command, and
control signals from the memory controller to the register/PLL device. Contact the
HyperLynx Customer Support team if you want to simulate from the register/PLL device
to the SDRAMs.

Figure 17-3. JEDEC Standard RDIMM — DDR3

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Topology for Non-JEDEC Standard DDRx - Register Only or PLL

Only
Figure 17-4 shows a variation of the standard RDIMM topology. The data, strobe, and clock
signals connect directly from the memory controller to the SDRAMs. The address, command,
and control signals connect through a register to the SDRAMs.

DDRx Wizard Simulation Setup for Register Only Topology

• Data Bus — Simulate as a UDIMM interface.
• Add/Cmd/Ctrl Bus — Simulate as an RDIMM interface. You must define and model the
register as a combined PLL and register device for the simulation to work in the DDRx
wizard. Note that the PLL timing parameters will not be used from the Register/PLL
timing model for this simulation.
• CLK to DQS Skew — Simulate as a UDIMM interface.

Figure 17-4. Non-JEDEC Standard — REGISTER Only

Figure 17-5 shows a variation of the standard DDRx topology. The data, strobe, address,
control, and command signals connect directly from the memory controller to the SDRAMs.
The clock signal from the controller is distributed through a PLL to the SDRAMs.

Note
Contact HyperLynx Customer Support if you want to simulate the address, command, or
control buses or the CLK to DQS skew.

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DDRx Wizard Simulation Setup for PLL Only Topology

• Data Bus — Simulate as a UDIMM interface.
• Add/Cmd/Ctrl Bus — Contact HyperLynx Customer Support.
• CLK to DQS Skew — Contact HyperLynx Customer Support.

Figure 17-5. Non-JEDEC Standard — PLL Only

Setting Up HyperLynx for DDRx Simulation - Design Files

and Models
The design files and models you need for simulation depend on the questions you answered in
the Gathering Information About Your DDRx Memory Interface and Design topic. You need to
complete the steps below before running the DDRx wizard.

Prerequisites
Answer the questions in the Gathering Information About Your DDRx Memory Interface and
Design topic.

Procedure
1. Collect design files (HYP).
• Design with all DRAMs on main board (no DIMMs) — You need only the HYP file
for the main board that contains the DRAMs.
• Design with DIMMs — You must create a MultiBoard project that contains at least
two HYP files. One for the main board with slots and one for the DIMM. If you have
more than one same DIMM in your design, you can instantiate the same DIMM

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board file multiple times but for clarity, it is recommended that you use two copies
of the same board file. If you have two different configurations of DIMMs, for
example 1-rank and 2-rank DIMMs, you will absolutely need two separate board
files of the DIMMs.
2. Assign controller, SDRAM, and resistor pack models.
a. Validate that the [Pins] section of your IBIS/EBD models for the controller and
DRAMs match the pin-outs on the package your design uses.
b. For DDR2 and DDR3 designs, validate that the IBIS/EBD models have the [Model
Selector] keyword listing the models so you can assign ODT models. See “Adding
Model Selector Keywords to IBIS Models” on page 793.

DDRx Batch simulation uses the [Model Selector] keyword to know which On-Die
Termination - ODT model to use for data pins. When running the DDRx batch
simulation wizard, you specify [Model Selector] names to use for data pins during
memory read/write operations, such as when ODT is enabled or disabled. If the
vendor-supplied memory or controller IC model does not contain [Model Selector]
keywords, you can edit the model to add them.
c. Use the [Diff Pin] keyword in your IBIS/EBD models to identify differential pairs
for the Controller and DRAMs and make sure the connecting pins have the same
polarity. “Adding Model Selector Keywords to IBIS Models” on page 793
d. Assign IBIS or EBD models to the reference designators for the memory controller
and SDRAM ICs. Use a .REF or .QPL automapping file to map the IBIS models to
the entire component. The DDRx wizard can automatically map specific DDRx
interface functions (such as data, clock, and strobe) to nets on the board if the signal
names in the IBIS models follow standard conventions, for example, CK, DQ, DQS,
DM, RAS, CAS, ODT, and so on. See “Selecting Models and Values for Entire
Components” on page 296.

Note: DDRx batch simulation automatically enables drivers on the memory

controller and memory ICs, using the round-robin method; you do not have to
manually enable IC drivers on the memory interface nets before running DDRx
batch simulation. See “Round Robin for DDRx Batch Simulation” on page 818.
3. Gather or create controller and DRAM timing models.

Controller and DRAM timing models are required to run the DDRx analysis
successfully. Each timing model specifies timing requirements for the signals.
HyperLynx timing models are based on the Verilog programming language, and contain
a few extensions added to facilitate the specification of timing models. For more
information on the timing model format, see “HyperLynx Timing Model Format” on
page 1270.

Default timing models are included in the HyperLynx installation. An example of that

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path is C:\MentorGraphics\<release>HL\SDD_HOME\hyperlynx\Libs. Separate

models for each DDRx interface for both controller and DRAMs are included in the
folder. For example, ddr3_ctl.v is the timing model for the DDR3 controller and
ddr3_dram.v is the timing model for the DRAMs.

In most cases, the DRAM timing models are standard, since JEDEC specifies the timing
requirements at the DRAMs. For the memory controllers, the requirements can vary
from manufacturer to manufacturer and chip to chip. You can use the default controller
timing models as a starting point to do your analysis, but you might need to create your
own timing model if the parameters of your controller differ from the default controller
timing model. To create your own controller timing model, you will need to familiarize
yourself with the required parameters from the data sheet, understand how they are
defined, and interpret them to create a model using the DDRx Controller Timing Model
Wizard (Models > Run DDRx Controller Timing Model Wizard). See “Creating
Controller and DRAM Timing Models” on page 786.
4. Optional, MultiBoard Projects only: If you have or want to include advanced
connector models, set up Connector Models.
a. Select Edit > MultiBoard Project and clicking Next twice to get to the
Interconnection List page of the Multiboard Project Wizard.

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b. For each connector, select the connector and from the Connector model area, select
one of the following and click Assign:
• Short — Electrically short the pins together on different boards. This model
effectively removes the connector from the circuit. This option does not require
any additional setup.
• Simple — Use the interconnection model built into BoardSim and specify the R,
Z, and delay. You can usually obtain these values from a .SLM (single-line-
model) of the connector.
• Advanced — Use a SPICE or S-Parameter model. You must do the following if
you select this option:
a. Select a SPICE model that is linear, meaning that it can contain only passive
components. S-Parameter models are linear in nature.
b. Click Connection Editor and perform port mapping.
c. Click Finish to close the wizard.
5. DDR3 Simulation only—Create the write leveling delay file. See Write Leveling for
DDR3 and Creating DDR3 Write-Leveling Delay Files.

To create a write-leveling delay file, run the DDRx Wizard, which has been set up
correctly, with only the Clock-to-strobe skew option enabled from the DDRx Wizard -
Nets to Simulate Page. The wizard creates the DDR3Delays_autogenerated.txt file and
places it in the same directory as the design. To include these delays in the simulation,
you will import delays from this DDR3Delays_autogenerated.txt file from the DDRx
Wizard - Write Leveling Page and run the simulation again.

You can also enter those write leveling delays manually from the DDRx Wizard - Write
Leveling Page. These delays can be from another simulator or manufacturer’s
recommended values.
6. Verify the design setup, see “Verifying the Design Setup for DDRx Simulation” on
page 795.
7. Set up the DDRx Batch Mode Wizard for simulation, see “Running DDRx Simulation
for the First Time” on page 820 and “Procedure to Run DDRx Batch Simulation” on
page 821.

Tip: SupportNet provides additional information about setting up and running DDRx
batch simulation, in the form of technical notes, movies, and so on. Select Help >
Support. From the InfoHub. select the Support & Training tab and click View How-to
and Tutorial movies on SupportNet.

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Related Topics
“Creating Controller and DRAM Timing Models” on page 786

“Adding Model Selector Keywords to IBIS Models” on page 793

Creating Controller and DRAM Timing Models

DRAM and Controller timing models are required by the DDRx Wizard to specify the timing
requirements at both ends for the interfacing signals. The DDRx Wizard uses the parameters
from the timing models for deriving the final timing margins. These timing parameters include
skew, delay, and setup and hold time requirements on signals with respect to their associated
strobe or clock signal. The DRAM timing models are quite standardized since the timing
specifications at the DRAMs are specified by the JEDEC standards. In the case of the
controllers, it is very likely that the timing requirements are different from vendor to vendor.

Default timing models for memory and controller ICs ship with HyperLynx, and are located in
the Libs folder. For example, C:\MentorGraphics\<release>\SDD_HOME\hyperlynx\Libs.

If the shipping timing models do not accurately describe the behavior of the controller and
memory ICs in the design, you can use the following methods to create new or edited models:

• To create a new controller timing model, use the HyperLynx Timing Model Wizard:
o Models menu > Run DDRx Controller Timing Model Wizard.
You can also import an existing timing model into the wizard, to edit it or see its
contents in the context of the wizard pages.
HyperLynx does not provide a wizard to create memory controller models.
• To manually edit a controller or memory controller timing model, use the HyperLynx
Timing Model Editor by doing any of the following:
o Models menu > Edit DDRx Timing Models.
o DDRx Wizard - Timing Models Page — Select spreadsheet row header and click
Edit.

Tip: See AppNote 10706 on SupportNet for more information on creating memory
controller timing models. To access SupportNet, from HyperLynx, select Help >
Support. This opens the InfoHub — Support & Training tab. Click View How-to and
Tutorial movies on SupportNet and search for AppNote 10706.

Related Topics
“HyperLynx Timing Model Format” on page 1270

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Required Controller Timing Parameters

This section describes the controller timing parameters the DDRx Wizard and HyperLynx
Timing Model Wizard require as inputs. A Memory Controller timing model should include the
timing relationships in Table 17-2 - Table 17-10 in the specify block for the model (signal edge
qualifiers will be ignored). Note that parameter tDQDQS and parameters tDS/tDH are
complementary methods of describing the DQ-to-DQS timings during read cycles; only one of
the two methods should be specified in the timing model file.

Table 17-2. tCKAC(min) and tCKAC(max)

Description Model File Relationship Active
Cycle
The minimum and maximum delay between the address $delay(ck, addr_cmd, min, Read/
and command output signals, transitioning to valid before max); Write
the rising edge of the output clock (CK). See Table 17-6.
• Applicable to address (A) and command (BA, RAS,
CAS, and WE) signals on both read and write cycles.
• Supports both 1T and 2T timing on signals. If the delay
between a valid transition of the Address and
Command signals and the rising edge of the clock is
more than one clock cycle, it is referred to as 2T
timing.

Figure 17-6. tCKAC

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Table 17-3. tCKCTL(min) and tCKCTL(max)

Description Model File Relationship Active
Cycle
The minimum and maximum delay between the control $delay(ck, ctl, min, max); Read/
output signals transitioning to valid before the rising edge Write
of the output clock. See Table 17-7.
• Applicable to control signals (CS, CKE, and ODT) on
both read and write cycles.
• Supports only 1T timing on these signals.

Figure 17-7. tCKCTL

Table 17-4. tCKDQS(min) and tCKDQS(max)

Description Model File Relationship Active
Cycle
The minimum and maximum skew between the rising edge $fullskew(dqs, dq, min, Write
of the output data strobe (DQS) and the rising edge of the max);
output clock (CK). See Table 17-8.
• Applicable to CK and DQS signals during the WRITE
cycle.

Figure 17-8. tCKDQS

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Table 17-5. tDQSDQ(min) and tDQSDQ(max)

Description Model File Relationship Active
Cycle
The minimum and maximum delay between the data and $delay(dqs, dq, min, Write
data mask output signals transitioning to valid and the max);
associated output data strobe edge (either rising or falling).
See Table 17-9.
• Applicable to data(DQ) and data mask (DM ) signals
and its associated DQS signal during the WRITE cycle

Figure 17-9. tDQSDQ

Table 17-6. tDS and tDH

Description Model File Relationship Active
Cycle
Data setup (tDS) and hold (tDH) window relative to $setup(dq, dqs, tDS); Read
associated DQS. See Table 17-10. $hold(dqs, dq, tDH);
• During a read cycle, the DRAMs output the transitions
of the DQS signal approximately aligned with the Or
transitions of the DQ signals. The controller captures
the DQ signals by typically phase shifting the DQS $setuphold(dqs, dq, tDS,
signal internally by about 1/4 clock period. tDH);
• Specify whether the "setup" and "hold" parameters are
measured at the controller pins (phase shift=0) (Figure
10) or after an internal 90˚ phase shift (Figure 11).
• Setup values are positive if DQ must be valid before
DQS (negative if after); Hold values are positive if DQ
must remain valid until after DQS (negative if before).
Applicable to data(DQ) signals and its associated DQS
signal during the READ cycle.

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Figure 17-10. tDS and tDH

Related Topics
“Creating Controller and DRAM Timing Models” on page 786

“HyperLynx Timing Model Format” on page 1270

Review of DDRx Timing Relationships

This section reviews the DDRx specific timing relationships between signals at the controller
during read and write operations.

In the DDRx memory interface, there are four main groups of signals:

• Address and Command Signals (A[15:0], BA[2:0], RAS#, CAS# & WE#)
• Control Signals (CS[3:0], CKE[3:0], & ODT[3:0])
• Data, Data Mask, and Strobe signals (DQ[63:0], DM[8:0], CB[7:0], DQS/#DQS[8:0])
• Clock Signals (CK/CK#[5:0])

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Table 17-7. Summary of DDRx Timing Relationships at the Controller

Operation Signals Reference Reference Clocked Typical Signal Timing
Signal Signal Edge at Prelaunch
Frequency Receiver Delay Relative
to CK or DQS
Read/Write Addr/Cmd CK+/- 0.5*DataRate Rise 0.5*tCK 1T or 2T
Read/Write Ctl CK+/- 0.5*DataRate Rise 0.5*tCK 1T
Write DQ/DM DQS+/- 0.5*DataRate Rise & Fall 0.25*tCK NA
Write DQS+/- CK+/- 0.5*DataRate Rise & Fall 0 NA
Read DQ/DM DQS+/- 0.5*DataRate Rise & Fall 0 NA

To determine the timing relationships between signals at the controller, first, the operating
frequency of the clock signal must be determined. The DDRx interface is usually specified by
notation DDRx–<speed-grade>, for example DDR-400, DDR2-533 or DDR3-800. The speed-
grade unit is in MT/s (mega-transfer per second). This topic uses DDR3-800 as an example
throughout. For a DDR3-800 interface, the speed-grade is 800MT/s and the operating frequency
is half of the speed-grade; 400MHz. The DDRx Wizard needs the bit period for
address/command/control and data signals.

The address, command, and control signals are output only signals, but both read and write
operations use them. The address, command, and control signals reference an associated clock
(CK) signal. The address and command signals allow 1T or 2T timing, the control signals allow
only 1T. Typically, the controller outputs these signals approximately aligned with a falling
clock edge. To achieve this, the address/command/control signal is launched half the clock
period earlier than the clock. This timing is referred to as 1T timing. For 2T timing, the address
/command signal is launched one and a half period earlier than the clock so that there is more
setup time at the receiver. The shortest available setup time for the address signal for 1T timing
is one clock period and for 2T timing, it is 2 clock periods. Figure 17-11 is the timing diagram
for the timing relationships explained above. The gray windows are the uncertainties you need
to account for in the real operation.

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Figure 17-11. DDRx Address, Command, and Control Signal Timing at the
Controller

The data, data mask, and strobe signals are bi-directional signals: outputs during the write
operation and inputs on the read operation. Each data byte lane references a DQS signal. During
the write operation, DQ and DM signals are launched a quarter of the clock period earlier than
the DQS signal for each byte lane so that both rising and falling edges of the strobe are centered
in the valid data bit window. Since the data and data mask signals can be clocked in at every
strobe edge, the bit period for these signals is half of the clock period. Figure 17-12 shows this
timing relationship. The gray windows are the uncertainties that you need to account for in real
operation.

Figure 17-12. DDRx DQ/DM Signal Timing at the Controller During Write

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During the write operation, the controller also needs to meet the delay timing relationship
between the clock signals (CK) and strobe signals (DQS). Figure 17-13 shows this relationship.

Figure 17-13. DDRx CK and DQS Timing at the Controller

During the read operation, the DRAMs send both DQ signals and DQS signals to the controller,
edge aligned. At the controller, these signals must meet certain setup and hold requirements.
You can specify the setup and hold requirements at the controller two ways: at the pins or at the
internal registers. If you specify the timing requirements are at the pins, DQ/DM signals and
DQS signals are edge aligned. If you specify the timing requirements at the internal registers,
you need information on how the controller captures the data internally. Typically, the ideal
phase shift is one quarter of the clock cycle. Figure 17-14 shows these timing relationships.

Figure 17-14. DDRx DQ/DM Signal Timing at the Controller During Read

Related Topics
“Creating Controller and DRAM Timing Models” on page 786

Adding Model Selector Keywords to IBIS Models

To add [Model Selector] keywords to IBIS models:

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1. Create a [Model Selector] keyword containing all the [Model] names needed to simulate
the pin for all the buffer strength and ODT conditions (see Figure 17-16 on page 803)
you plan to simulate.
Syntax:
[Model Selector] <model_selector_name>
<programmable_buffer_model_name> <comment_to_end_of_line>
Example:
[Model Selector] DQ
DQ_DRVFULL_ODTOFF Full-strength driver with disabled ODT
DQ_DRVHALF_ODT50 Half-strength driver with 50 Ohm ODT
DQ_DRVHALF_ODT100 Half-strength driver with 100 Ohm ODT

2. In the [Pin] keyword, find a data pin used by the memory interface and assign the
appropriate <model_selector_name> defined in step 1.
Syntax:
[Pin] signal_name model_name R_pin L_pin C_pin
<pin_name> <signal_name> <model_name>
Example:
[Pin] signal_name model_name R_pin L_pin C_pin
DQ5 DQ5 DQ
JEDEC specifications JESD79-2* and JESD79-3* refer to data pins as data (DQ), data
mask (DM), check bit (CB), and data strobe (DQS). The pin names in the IBIS model
might be different, making it harder for you to map the model-specific data pin names to
the generic names in the specifications.
3. Repeat step 2 as needed to update the [Pin] keyword for all data pins in the DDR2 or
DDR3 memory interface.
4. Check the model syntax with the Visual IBIS Editor. See “Checking IBIS File Syntax”
on page 428.

Related Topics
“IBIS Specification” on page 1327

“Mapping DDRx Interface Signals to Nets in the Design” on page 800

“Simulating DDRx Memory Interfaces” on page 773

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Verifying the Design Setup for DDRx Simulation

After you have performed all the above suggested steps, you now need to verify that you have
done all the steps correctly and all nets are ready for simulation. Before running the DDRx
Wizard on multiple nets, it is advised that you check some of the nets interactively.

Prerequisites
Complete the steps in the Setting Up HyperLynx for DDRx Simulation - Design Files and
Models topic.

Procedure
1. Ensure that model library paths to all needed IBIS models, SPICE/S-parameter
connector models, and timing models for the controller and DRAM are set using the Set
Directories Dialog Box (Setup > Options > Directories).
2. Select a net from each signal function group (Data, Address & Command, Clock, and
Control) to make sure that there is a proper connectivity and models assigned to all
buffers. The Pins section of Assign Models dialog box should show in green buffer
symbols indicating that there are models assigned for those buffers. See “Assigning
Models to Pins” on page 467.
3. If you have series resistors that are resistor packs, ensure that each resistor pack is
assigned with the correct .PAK model. View the following movie to familiarize with the
procedure:

http://supportnet.mentor.com/reference/tutorials/tutorial_10165.cfm

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4. Open the Model Selector dialog box for the controller and a DRAM to make sure that
the models are listed as defined in the IBIS file. The following diagram shows how to
get to the Model Selector dialog box:

5. Interactively, select a differential pair net, such as a DQS or a CLK, to ensure that both
nets of the differential pair get selected. This ensures that the [Diff Pin] keywords for
those pins are defined properly.
6. Using the Digital Oscilloscope, simulate a few random nets (DQ, DQS, address, and
clock) to ensure that you are getting the expected simulation waveforms. If the signal is
bi-directional, it is suggested that you simulate both directions. If the signal is
differential, you should see proper both single-ended and differential waveforms at the
receiver of interest.

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7. If you have a SPICE/S-parameter connector model in a MultiBoard project, ensure that

there is proper connectivity. The best way to test is to select the net and inspect the
connectivity.

Related Topics
“Gathering Information About Your DDRx Memory Interface and Design” on page 776

“DDRx Topologies” on page 777

“Setting Up HyperLynx for DDRx Simulation - Design Files and Models” on page 782

“Running DDRx Batch Simulation” on page 820

“DDRx Batch-Mode Wizard Dialog Box” on page 847

DDRx Background Information

Use the information in this section to learn about data flow, mapping nets in the design to DDRx
interface signals, on-die termination (ODT), how to derate setup and hold measurements, and so
on.

This section contains the following topics:

• “Data Flow for DDRx Batch Simulation” on page 799

• “Mapping DDRx Interface Signals to Nets in the Design” on page 800
• “Pairing DDRx Interface Signals” on page 802
• “Supported IBIS Model Spec and Receiver Threshold Keywords” on page 802
• “On-Die Termination - ODT” on page 803
• “Derating DDR2 and DDR3 Setup and Hold Times” on page 804
• “Physical Basis of DDR2 and DDR3 Slew-Rate Derating” on page 813
• “Effects of Delay Ranges on Setup and Hold Measurements” on page 814
• “Write Leveling for DDR3” on page 817
• “Round Robin for DDRx Batch Simulation” on page 818
• “About Measuring DDRx Signals with Eye Diagrams” on page 819

Related Topics
“Preparing Designs for DDRx Batch Simulation” on page 774

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“Running DDRx Batch Simulation” on page 820

“DDRx Batch Simulation Results” on page 824

“DDRx Batch-Mode Wizard Dialog Box” on page 847

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Data Flow for DDRx Batch Simulation

Figure 17-15 on page 799 shows the main data inputs and outputs for DDRx batch simulation.

Figure 17-15. DDRx Data Flow

Table 17-8. DDRx Folders Legend

<design> folder.

See “About Design Folder Locations” on page 1391.

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Table 17-8. DDRx Folders Legend (cont.)

<model_library> folder. For example:

C:\MentorGraphics\<release>\SDD_HOME\hyperlynx\Libs.

Shipping timing models are located in the

C:\MentorGraphics\<release>\SDD_HOME\hyperlynx\Libs folder, but you can open
them from other locations.

You can open IBIS models from other locations. See “Select Directories for IC-Model
Files Dialog Box” on page 1844.
<design>\DDR_Results folder.

<design>\DDR_Results\<waveform_folders> folders.

One sub-folder contains waveforms measured at driver pins and the other sub-folder
contains waveforms measure at receiver pins.

Related Topics
“DDRx Batch Simulation Results” on page 824

Mapping DDRx Interface Signals to Nets in the Design

The DDRx wizard automatically maps nets in the design to DDRx interface signal functions,
such as data, clock, and strobe.

Prerequisites
1. Assign IBIS models to the reference designators associated with the memory controller
and DRAM ICs. Use a .REF or .QPL automapping file to map IBIS models to entire
components. See “Selecting Models and Values for Entire Components” on page 296.
Signal names in the DRAM models usually observe a naming convention that makes it
possible for the wizard to identify which pins map to specific DDRx interface functions.
2. In the DDRx wizard, identify the reference designators for the memory controller and
DRAM ICs.
See “DDRx Wizard - Controller Page” on page 852 and “DDRx Wizard - DRAMs
Page” on page 854.

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Note
Even if you provide the above information, incomplete connectivity information can
prevent the DDRx wizard from mapping all the signals in the DDRx interface.

For example, if the net passes through a resistor package, a .PAK model must be assigned
to the reference designator for the DDRx wizard to know the connectivity among resistor
package pins. Note that this resistor package model assignment is also required to
interactively simulate the net with the oscilloscope, and is not unique to DDRx
simulation. See “Choosing Resistor and Capacitor Packages” on page 322.

Algorithm to Map Nets to DDRx Interface Signal Functions

The algorithm to automatically map nets to DDRx interface function consists of the following
main steps:

1. Map DRAM IBIS model pins to DDRx interface functions.

For each unique IBIS model assigned to a DRAM, use signal names from the [Pin]
keyword to map model pins to DDRx functions (Clock, Data Strobe, Data Mask, Data
Bit, Address/Command, and Control).
For differential signals, the first pin in the [Diff Pin] keyword is the positive signal.
You identify DRAM reference designators on the DRAMs wizard page. See “DDRx
Wizard - DRAMs Page” on page 854.
2. Identify the signal nets for the controller.
Create a list containing all the signal nets directly connected to the memory controller.
You identify the memory controller reference designator on the DDRx Wizard -
Controller Page.
3. Identify the signal nets connecting the DRAMs to the controller.
For each DRAM component pin, follow the signal path topology to create a list
containing the signal nets directly connecting the DRAM to the controller. This is a
subset of the list created in step 2.
4. Map DRAM component pins to controller nets with specific DDRx functions.
Map the function groups created in step 1 to signal nets connecting the DRAM to the
controller identified in step 3.
5. Build and refine a wizard database mapping signal nets to DDRx functions.
In addition to containing information obtained in step 4, other signal net to DDRx
function mapping occurs. Examples:
• Map Data Mask and Data nets for a specific DRAM to the Data Strobe net.

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• If the DDR2 DRAM has eight data bits (x8), the Data Mask input pin can act as a
redundant data strobe output pin (RDQS). This feature enables the memory-system
designer to reduce loading on the DQS signals in cases where x4 DRAM devices are
mixed with x8 DRAM devices, and is selected through an internal mode register.
The automatic net-mapping algorithm always assumes these pins are used in a Data
Mask function. You can reassign these pins as RDQS outputs by manually
reassigning them on the Data Strobes and Data Nets pages.
6. User confirmation of automatic mapping.
You can edit automatic mapping assignments on the following wizard pages: Data
Strobes, Data Nets, Clock Nets, Addr/Cmd Nets, and Control Nets.

Related Topics
“Preparing Designs for DDRx Batch Simulation” on page 774

“Running DDRx Batch Simulation” on page 820

“DDRx Batch-Mode Wizard Dialog Box” on page 847

Pairing DDRx Interface Signals

DDRx is a source-synchronous technology, meaning that instead of one master clock that
applies to the entire memory interface, multiple strobes and clocks are used for sub-portions of
the interface. To set up timing measurements on a specific data, address, command, or control
signal, the DDRx wizard automatically pairs it to its clock or strobe signal. Setup, hold, and
other measurements on a data, address, command, or control signal are made relative to its
clock or strobe signal. Signal pairing also exists between strobe and clock signals.

Supported IBIS Model Spec and Receiver Threshold

Keywords
HyperLynx supports the set of sub-keywords needed to measure DDRx signals for the [Model
Spec] and [Receiver Threshold] keywords in IBIS models.

Supported sub-keywords for [Model Spec]:

• Vinl, Vinh—min/typ/max operating values
• Vmeas—min/typ/max operating values
• Vref—min/typ/max operating values
Supported sub-keywords for [Receiver Thresholds]

• Single-ended buffers

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o Vth, Vth_min, Vth_max

o Vinh_ac, Vinh_dc
o Vinl_ac, Vinl_dc
o Threshold_sensitivity
o Reference_supply
• Differential buffers
o Vcross_low, Vcross_high
o Vdiff_ac, Vdiff_dc

On-Die Termination - ODT

Data and data strobe signal circuits in DDR2 and DDR3 designs include ODT to improve signal
integrity during read and write operations. Figure 17-16 shows an ODT circuit that consists of
voltage-dividers that can be enabled independently to provide a range of resistance values, or be
disabled completely.

Figure 17-16. Example ODT Circuit

ODT can change the receiver characteristics so much that you need separate models to represent
the termination enabled/disabled behaviors. IBIS models use the [Model Selector] keyword to
control which model within a component to use during simulation. The DDRx wizard helps you
specify models for enabled/disabled termination behaviors.

While ODT switches on and off dynamically in the actual design, ODT settings cannot change
within a specific DDRx batch simulation. ODT settings can change between simulations.

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Derating DDR2 and DDR3 Setup and Hold Times

To obtain setup and hold timing values for timing budget spreadsheets for DDR2 and DDR3
interfaces (but not DDR), you adjust (derate or prorate) the raw setup and hold timing
measurements with the multiple-step process described briefly in this topic. For detailed
derating instructions, see JEDEC specification JESD79-2* or JES72-3*.

Note that DDRx batch simulation automatically performs all the steps described in this topic.
Also note the oscilloscope can derate waveforms for DDR2 only. See “Derating DDR2 Slew
Rate Measurements” on page 583.

Obtaining derated DDR2 and DDR3 setup and hold times includes the following main steps:

• “Step 1 - Measuring Raw Setup and Hold Timing” on page 805

• “Step 2 - Obtaining Slew Rates for Derating Tables” on page 807
• “Step 3 - Calculating Derated Setup and Hold Times” on page 812

Related Topics
“Physical Basis of DDR2 and DDR3 Slew-Rate Derating” on page 813

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Step 1 - Measuring Raw Setup and Hold Timing

The receiver voltage thresholds used to measure setup and hold timing depends on whether the
clock or strobe is differential or single-ended.

Most signals in the DDR2 and DDR3 interface are always differential or single-ended. By
contrast, data strobes can be differential ( DQS, DQS , RDQS, RDQS , LDQS, LDQS ,
UDQS, UDQS ) or single-ended (DQS, RDQS, LDQS, UDQS).

Setup and Hold Measurements - Differential Clock or Strobe

This topic shows how to measure setup and hold times for differential clocks or strobes. To
simplify the details, Figure 17-17 uses DQS, DQS to represent the differential clock or strobe
and uses DQ to represent the input signal.

Figure 17-17. Setup and Hold Timing with Differential Clock or Strobe

Table 17-9. Setup and Hold Timing with Differential Clock or Strobe
tDS for the rising edge of DQ is measured from when DQ last crosses VIH(ac)min to the
voltage where DQS, DQS cross.
tDH for a falling edge of DQ is measured from the voltage where DQS, DQS cross to
when DQ last crosses VIH(dc)min.
tDS for a falling edge of DQ is measured from when DQ last crosses VIL(ac)max to the
voltage where DQS, DQS cross.
tDH for a rising edge of DQ is measured from the voltage where DQS, DQS cross to
when DQ last crosses VIL(dc)max.

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Setup and Hold Measurements - Single-Ended Clock or Strobe

This topic shows how to measure setup and hold times for single-ended strobes. To simplify the
details, Figure 17-18 uses DQS to represent the single-ended strobe signal and uses DQ to
represent the input signal.

Figure 17-18. Setup and Hold Timing with Single-Ended Clock or Strobe

Table 17-10. Setup and Hold Timing with Single-Ended Clock or Strobe
tDS for a rising edge of DQ is measured from when DQ crosses VIH(ac)min to when the
falling edge of DQS last crosses VIH(dc)min.

If DQS was rising (not illustrated), measure to when DQS last crosses VIL(dc)max.
tDH for a falling edge of DQ is measured from when DQS last crosses VIL(ac)max to
when the falling edge of DQ last crosses VIH(dc)min.

If DQS was rising (not illustrated), measure to when DQS last crosses VIL(dc)max.
tDS for a falling edge of DQ is measured from when DQ last crosses VIL(dc)max to when
the rising edge of DQS last crosses VIL(dc)max.

If DQS was falling (not illustrated), measure to when DQS last crosses VIH(dc)min.
tDH for a rising edge of DQ is measured from when the rising edge of DQS last crosses
VIH(ac)min to when DQ last crosses VIL(dc)max.

If DQS was falling (not illustrated), measure to when DQS last crosses VIH(dc)min.

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Step 2 - Obtaining Slew Rates for Derating Tables

This topic shows how to obtain the slew rates for both signals in a setup or hold measurement.
You use the slew rates to look up derating times in DDR2 or DDR3 derating tables, such as
Figure 17-23 on page 813. Setup and hold measurements use different slew-rate line and
measurement threshold voltages.

To obtain slew rates for use with derating tables:

1. Plot the waveforms.

2. Plot nominal and tangental slew-rate lines over the waveforms.
See also: “Plotting Nominal Slew-Rate Lines for Setup Measurements” on page 808,
“Plotting Nominal Slew-Rate Lines for Hold Measurements” on page 809,
“Plotting Tangental Slew-Rate Lines for Setup Measurements” on page 810,
“Plotting Tangental Slew-Rate Lines for Hold Measurements” on page 811
3. Use the following criteria to identify which slew-rate line to use when calculating the
slew rate:
• Setup measurement
o If the waveform is always earlier than the nominal slew-rate line (for voltages
within the end points of the line segment), use the nominal slew-rate line.
o If the waveform is ever later than the nominal slew-rate line (for voltages within
the end points of the line segment), use the tangental slew-rate line.
• Hold measurement
o If the waveform is always later than the nominal slew-rate line (for voltages
within the end points of the line segment), use the nominal slew-rate line.
o If the waveform is ever earlier than the nominal slew-rate line (for voltages
within the end points of the line segment), use the tangental slew-rate line.
4. Obtain the slew rate to use with the derating table by using one of the following
expressions with the slew-rate line chosen in step 3:
• Setup slew rate, rising edge = (VIH(ac)min - VREF(dc)) / ∆TR
where ∆TR = (time signal crosses VREF(dc) - time signal crosses VIH(ac)min
• Setup slew rate, falling edge = (VREF(dc) - VIL(ac)max) / ∆TF
where ∆TF = (time signal crosses VIL(ac)max) - time signal crosses VREF(dc)
• Hold slew rate, rising edge = (VREF(dc) - VIL(dc)max) / ∆TR
where ∆TR = (time signal crosses VIL(dc)max - time signal crosses VREF(dc)
• Hold slew rate, falling edge = (VIH(dc)min - VREF(dc)) / ∆TF

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where ∆TF = (time signal crosses VREF(dc) - time signal crosses VIH(dc)min
For an illustration of ∆TR and ∆TF , see Figure 17-19 on page 808.

Plotting Nominal Slew-Rate Lines for Setup Measurements

This topic shows how to plot nominal slew-rate lines (line segments) over a waveform for setup
measurement derating.

Figure 17-19. Plotting Nominal Slew-Rate Lines for Setup Time Derating

Table 17-11. Plotting Nominal Slew-Rate Lines for Setup Time Derating
Nominal slew-rate line for rising edge—Plot a line from the last crossing of VREF(dc)
to the first crossing of VIH(ac)min.
Rising edge time— ∆TR

Nominal slew-rate line for falling edge—Plot a line from the last crossing of VREF(dc)
to the first crossing of VIL(ac)max.
Falling edge time— ∆TF

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Plotting Nominal Slew-Rate Lines for Hold Measurements

This topic shows how to plot nominal slew-rate lines (line segments) over a waveform for hold
measurement derating.

Figure 17-20. Plotting Nominal Slew-Rate Lines for Hold Time Derating

Table 17-12. Plotting Nominal Slew-Rate Lines for Hold Time Derating
Nominal slew-rate line for rising edge—Plot a line from the last crossing of
VIL(dc)max to the first crossing of VREF(dc).
Rising edge time— ∆TR

Nominal slew-rate line for falling edge—Plot a line from the last crossing of
VIH(dc)min to the first crossing of VREF(dc).
Falling edge time— ∆TF

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Plotting Tangental Slew-Rate Lines for Setup Measurements

This topic shows how to plot tangental slew-rate lines (line segments) over a waveform for
setup measurement derating. Tangental slew-rate lines are not needed if the waveform is always
earlier than the nominal slew rate line for voltages from VREF(dc) to VIH(ac)min (rising edge) or
VIL(ac)max (falling edge).

Figure 17-21. Plotting Tangental Slew-Rate Lines for Setup Time Derating

Table 17-13. Plotting Tangental Slew-Rate Lines for Setup Time Derating
Nominal slew-rate line for rising edge—Plot a line from the last crossing of VREF(dc)
to the first crossing of VIH(ac)min.
Tangental slew-rate line for rising edge—Plot a line from where the waveform crosses
VIH(ac)min, running tangental to the waveform, to VREF(dc).
Rising edge time for tangental slew-rate line— ∆TR

Nominal slew-rate line for falling edge—Plot a line from the last crossing of VREF(dc)
to the first crossing of VIL(ac)max.
Tangental slew-rate line for falling edge—Plot a line from where the waveform
crosses VIH(ac)min, running tangental to the waveform, to VREF(dc).
Falling edge time for tangental slew-rate line— ∆TF

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Plotting Tangental Slew-Rate Lines for Hold Measurements

This topic shows how to plot tangental slew-rate lines (line segments) over a waveform for hold
measurement derating. Tangental slew-rate lines are not needed if the waveform is always later
than the nominal slew rate line for voltages from VREF(dc) to VIH(ac)min (rising edge) or
VIL(ac)max (falling edge).

Figure 17-22. Plotting Tangental Slew-Rate Lines for Hold Time Derating

Table 17-14. Plotting Tangental Slew-Rate Lines for Hold Time Derating
Tangental slew-rate line for rising edge—Plot a line from where the waveform crosses
VIL(dc)max, running tangental to the waveform, to VREF(dc).
Nominal slew-rate line for rising edge—Plot a line from the last crossing of VREF(dc)
to the first crossing of VIL(dc)max.
Rising edge time for tangental slew-rate line— ∆TR

Tangental slew-rate line for falling edge—Plot a line from where the waveform
crosses VIH(dc)min, running tangental to the waveform, to VREF(dc).
Nominal slew-rate line for falling edge—Plot a line from the last crossing of VREF(dc)
to the first crossing of VIH(dc)min.
Falling edge time for tangental slew-rate line— ∆TF

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Step 3 - Calculating Derated Setup and Hold Times

Use the following basic calculations to produce derated setup and hold times:

• Derated setup time = Measured setup time + Derating setup time ( ∆tDS )
• Derated hold time = Measured hold time + Derating hold time ( ∆tDH )
where:
Measured setup/hold time is the raw measurement for the signal pair.
Derating times come from a derating table that uses the slew rates of both signals in the
measurement. Figure 17-23 shows a fragment of a table from JEDEC specification
JESD79-2D. Multiple tables exist to provide derating values for the various DRAM
speed grades and for signals, such as data strobes ( DQS, DQS ), that are single-ended or
differential.
For example, to obtain ∆tDS from Figure 17-23 when the slew rate for DQS, DQS is
1.8 V/ns and the slew rate for DQ is 0.8 V/ns, use the value (-1 ps) in the cell located at
the intersection of the highlighted column and row.
Derating tables are built into DDRx batch simulation. These tables are based on the
JEDEC JESD79* specifications.
DRAMs use the JEDEC derating tables unless a custom table is defined in the timing
model.
Controllers do not use derating tables unless a custom table is defined in the timing
model, or unless the timing model explicitly specifies that the JEDEC DRAM derating
table is to be used.

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Figure 17-23. Table Fragment from JEDEC Specification JESD79-2D

Physical Basis of DDR2 and DDR3 Slew-Rate Derating

An input buffer used in the DDR2 or DDR3 memory interface may not always switch when the
signal at its pin crosses the threshold voltage. This is because the internal capacitance of the
input buffer takes time to charge or discharge, and can delay switching.

When characterizing silicon behavior to produce input buffer datasheet specifications, test
bench equipment applies a nominal slew rate of 1 V/ns for data/command/address signals and
2V/ns for clock signals.

If the slew rate of the signal is faster than the nominal slew rate, less switching time is available
(compared to test bench characterization) to charge/discharge the internal capacitance and the
input threshold voltage is effectively higher for a rising edge and lower for a falling edge. This
means the derating table usually contains a “derating” value to apply to the measured setup or
hold time.

If the slew rate of the signal is slower than the nominal slew rate, more switching time is
available (compared to test bench characterization) to charge/discharge the internal capacitance
and the input threshold voltage is effectively lower for a rising edge and higher for a falling
edge. This means the derating table usually contains a “prorating” value to apply to the
measured setup or hold time.

See Figure 17-24. Each of the triangles have the same area, representing the amount of internal
capacitance to charge or discharge.

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DDRx Background Information

Figure 17-24. DDRx Slew-Rate Derating

Effects of Delay Ranges on Setup and Hold

Measurements
The delay for some signals is specified in JEDEC specification JESD79* as a range of values.
To simplify the explanation of how delay ranges affect DDRx batch simulation set up and hold
measurements, this topic discusses only strobe timing.

The JEDEC specification JESD79* indicates that a strobe signal can switch over the range
defined by tDQSCKMIN to tDQSCKMAX. See Figure 17-25. This reflects the fact that strobe
timing can vary, relative to the clock, in system operation.

Under ideal conditions, simulation would reproduce system operation by running numerous
simulations, each with different strobe timing. This approach, however, is impractical from a
run time perspective, and so DDRx batch simulation applies to the strobe net a driver stimulus
with a constant delay for each simulation.

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Figure 17-25. tDSQCK Timing Parameter

To account for the range of strobe timing on setup and hold measurements, DDRx batch
simulation uses the following algorithm:

1. Identify the reference strobe or clock net associated with the measured net.
2. Assign strobe driver delay to the average delay, (delay_maximum + delay_minimum)/2.
If tDQSCKMAX= 225 ps and tDQSCKMIN = -225 ps, the average strobe delay is 0 ps.
3. Run simulation using the average strobe delay defined in step 2, and measure timing by
doing the following:
a. For the reference strobe/clock net, find one of the following:
• Single-ended strobe—Find the time of each reference crossing.
• Clock or differential strobe—Find the time of each crossing of Vdiff=0.
b. For the measured net, find the time of each falling/rising crossing of the DC and AC
thresholds that are “opposite” of the current level.
For example, if the waveform is currently a logic state 1, then find the times of the
next crossing of thresholds Vinl_dc and Vinl_ac.
c. For every relevant switching time found for the reference strobe/clock net in step a,
find for the measured net the time back to the previous crossing of the AC threshold,
and the time forward to the next crossing of the DC threshold. These times represent
the base setup and hold times for that cycle of the strobe/clock.

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d. Obtain worst-case timing measurements by subtracting half the strobe delay range,
(delay_maximum - delay_minimum)/2, from the measurement.
If tDQSCKMIN = -225 ps and tDQSCKMAX= 225 ps, half the strobe delay range is
225 ps.
If the measured setup margin is 500 ps, the worst-case setup margin is 500 ps minus
225 ps, which equals 275 ps.

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Write Leveling for DDR3

To improve signal integrity at higher data transfer operations, DDR3 introduced “fly-by”
routing topology for the [clock, address, command, control] signal group (see the black traces in
Figure 17-26). By contrast, the [data, strobe, mask] signal group is are typically routed (by byte
lanes) more or less directly to a specific DRAM. Fly-by topology reduces the quantity and
length of stubs, and is easy to terminate. For a description of the fly-by routing topology, see the
JESD79-3B, DDR3 SDRAM Specification.

“Fly-by” routing topology for [clock, address, command, control] and “direct” routing topology
[data, strobe, mask] signal groups introduces skew into signal timing. When the controller
drives the [data, strobe, mask] signals, the nominal arrival times at memory pins are
independent of DRAM placement on the DIMM. By contrast, when the controller drives the
[clock, address, command, control] signals, the nominal arrival times at memory pins are
dependent on DRAM placement on the DIMM.

See Figure 17-26. The black traces transmit [clock, address, command, control] signals. The red
arrows show the relative flight-time delays for these signals, where the top DRAM has the
shortest flight-time delay and the bottom DRAM has the longest flight-time delay.

Figure 17-26. DDR3 Fly-By Routing Topology

To compensate for this intrinsic skew between [clock, address, command, control] and [data,
strobe, mask] signal groups, DDR3 memory controllers support “write-leveling delays”, where

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DDRx Background Information

the controller inserts a byte-lane-specific delay to individual [data, strobe, mask] signal circuitry
during memory-write cycles. Specific byte-lane delay values are usually determined
dynamically during hardware initialization within the controller, using a special “write-
leveling” mode in DRAM components where data (DQ) pins indicate the status of the alignment
between strobe (DQS) and clock (CK) pins. More specifically, the controller sweeps the delay
for the strobe (DQS) pin while monitoring the alignment status on the data (DQ) pin. Also, the
controller can usually identify unique delays for strobe (DQS) pins located in different slots.

The DDRx wizard accepts write-leveling delays for strobe signals, but not for data and data
mask signals. The timing analysis process measures the skew and setup/hold relationships at the
DRAMs between the strobe and the clock during write cycles. Timing relationships between
the data and mask signals relative to the strobes are not dependent on this strobe-to-clock
relationship.

Note
You probably must assume the controller has sufficient capability to implement the write-
leveling delays that you identify by running your own simulations. It is somewhat
unlikely the memory controller vendor or designer will publish the range and resolution
of write-leveling delays supported by the controller.

The DDRx batch simulation can automatically create a file containing writing-leveling delays.
See “Creating DDR3 Write-Leveling Delay Files” on page 822.

Note
DDRx batch simulation creates ideal write-leveling delays, and does not take into
account min/typ/max delay conditions.

“Read-leveling” behaviors also exist within the DDR3 memory interface. However, the
implications of read leveling are largely transparent and irrelevant to the types of analysis
performed by DDRx batch simulation, and no wizard page exists to receive read-leveling delay
values.

Round Robin for DDRx Batch Simulation

DDRx batch simulation creates round robin simulations based on the type of net being
simulated. Even though both DDRx and generic batch simulation automatically create “round
robin” simulations, they use different algorithms.

Round robin for generic batch simulation does not take into account how nets function in the
system. Instead, it creates a simulation for every driver on the net, by enabling one driver per
simulation. See “round robin” on page 1965.

By contrast, DDRx batch simulation uses information about the type of net to set up round robin
simulations for it. Table 17-15 summarizes the basic driver-enabling rules for DDRx round

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robin. Note that Table 17-15 provides an incomplete description of driver-enabling rules,
because it omits details about data/data strobe nets in DDR2/DDR3 interfaces that need
multiple cases for some driver pins (to allow for varying ODT positions).

Table 17-15. Driver-Enabling Rules for DDRx Round Robin

Net Type Enabled Pins on the Net
Data (DQ) All pins; the memory controller pin is enabled during a
Data strobe (DQS) write and one DRAM pin at a time is enabled during a read
Redundant data strobe (RDQS-
DDR2 only)
Check bits (CB)
Clocks Controller pins

Clocks are driven only by the controller; all DRAM pins

are always receivers.
Data mask (DM) Controller pins

Data mask bits are unused during read operations

Address (A) Controller pins
Bank address (BA)
Command (RAS, CAS, WE) Address/command/control bits are driven only by the
Chip select (CS) controller; all DRAM pins are always receivers.
Clock enable (CKE)
On-die termination (ODT)

About Measuring DDRx Signals with Eye Diagrams

Measuring signal pairs cycle-by-cycle in DDRx batch simulation may provide less pessimistic
results than eye diagrams, which potentially pair data and strobe waveforms that do not occur in
the same cycle. This pessimism increases if the clock waveforms contain a significant amount
of jitter. This pessimism can lead to overly conservative designs that do not take advantage of
all the available timing margin.

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Running DDRx Batch Simulation

Running DDRx Batch Simulation

Use the DDRx batch simulation wizard to setup and run simulation. The wizard creates a batch
simulation setup file (.DDR) that contains all the information needed to simulate and measure
DDRx memory interface signals. The setup file stores all the wizard page options and values
you set, and is saved when you close the wizard. The setup file is written to the <design> folder
and is named <project_name>.ddr. See “About Design Folder Locations” on page 1391.

The setup file maps reference designators to DDRx controller and DRAM ICs, sets [Model
Selector] values for ODT, maps DRAM IC reference designators to slots and ranks, sets
stimulus bit sequences, simulation options, and so on.

The setup file can provide a starting point for simulating new or related designs, or different
configurations of the current design (such as using a different DRAM speed grade). You can
import a setup file from a previous DDRx simulation, or one that you manually created. You
can also use the setup file as a way to share simulation settings with other people.

This topic contains the following:

• “Running DDRx Simulation for the First Time” on page 820

• “Procedure to Run DDRx Batch Simulation” on page 821
• “Creating DDR3 Write-Leveling Delay Files” on page 822

Related Topics
“HyperLynx DDRx Wizard Setup File Format” on page 1307

Running DDRx Simulation for the First Time

After setting up a complex multiple-board representation of a DDRx interface (especially if it
involves connector models between boards), you should simulate a few representative nets
interactively, before proceeding to a complete, long-running batch simulation.

The recommended progression follows:

1. Interactive simulation—Simulate just a few nets in the DDRx interface and fix any set
up problems.
2. DDRx batch simulation (partial)—Simulate just a few nets in the DDRx interface and
fix any set up problems.
3. DDRx batch simulation (complete)—Only when the results of steps 1 and 2 are
satisfactory, simulate many or all DDRx interface nets.

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Procedure to Run DDRx Batch Simulation

The initial run in the DDRx Wizard should include one net from each signal group to ensure that
you are getting the expected results in the results folder. If everything looks as expected, you
might want to enable more nets to simulate. You can run the data write and data read
simulations separately. You can also run the address and command signal simulations
separately from the data nets to place the results in separate folders.

Note
If the design uses DDR3, and you want to specify write-leveling delays (recommended),
plan to run DDRx batch simulation twice. See “Creating DDR3 Write-Leveling Delay
Files” on page 822.

Prerequisites
• Answer the questions in the “Gathering Information About Your DDRx Memory
Interface and Design” on page 776 topic.
• Review the “Preparing Designs for DDRx Batch Simulation” on page 774 section.
• Create timing models, see “Creating Controller and DRAM Timing Models” on
page 786.
• Review the “Running DDRx Simulation for the First Time” on page 820 topic.

Procedure
1. Click Run DDRx Batch Simulation or select Simulate SI > Run DDRx Batch
Simulation.
The DDRx Batch Simulation Wizard opens.
2. On each wizard page, edit options and values as needed, and click one of the following:
• Back/Next—Go to the previous/next page.
• <wizard_page_name> in the table of contents pane—Jump directly to the named
page. See “Creating DDR3 Write-Leveling Delay Files” on page 822.
• Cancel—Close the wizard.
• Finish—Go to the Simulate page.
This capability is useful if you have already run the wizard to completion, have
edited simulation values on one or more pages, and want to reuse the values already
present on the other pages.

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Tip: To compare measurement values in spreadsheets to waveforms, enable the option to

save waveforms on the Report Options page of the DDRx Wizard. See “DDRx Wizard -
Report Options Page” on page 884.

3. To run DDRx batch simulation, on the Simulate page, click Run Batch Simulation.
This opens the DDRx Batch Mode - Run Simulation dialog box.
To quickly open the Simulate page in the wizard, click its name in the table of contents
pane or click the Finish button on most wizard pages.
4. Click Run to start the simulation.
5. To view simulation results, use Windows Explorer or another file manager to navigate
to the reports folder, and open the report files. See “DDRx Batch Simulation Results” on
page 824.

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

“DDRx Batch-Mode Wizard Dialog Box” on page 847

Creating DDR3 Write-Leveling Delay Files

If the design has a DDR3 memory interface, you probably should run the following two DDRx
batch simulations:

• First pass—Simulation creates a file containing write-leveling delays. Note the first pass
also creates measurement results, but they do not contain the deskew adjustments and
probably should not be used.
You may only have to create the write-leveling file once, but you should re-create the
file if you modify any of the following:
o Board-to-board connector models in a MultiBoard project
o IBIS or timing models
o Data rate
o Component speed grades
• Second pass—Simulation applies the delay values contained in the file to deskew the
[data, strobe, mask] signal groups, in order to obtain final measurement values.

Procedure
1. Run DDRx batch simulation as normal except, on the DDRx Wizard - Nets to Simulate
Page, enable only the Clock-To-Strobe-Skew option.

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Enabling only this option minimizes the simulation run time. Also, make sure there are
no pre-existing delays specified on the DDRx Wizard - Write Leveling Page.
2. The write-leveling delay file is written to the <design> folder and is named
DDR3Delays_autogenerated.txt. See “About Design Folder Locations” on page 1391.
This file is automatically generated every time you run a DDR3 simulation.
3. To preserve the contents of the write-leveling delay file, so it is not overwritten by a
future DDRx simulation, rename it to something else.
4. Run DDRx batch simulation again and do the following:
a. On the DDRx Wizard - Nets to Simulate Page, enable the options you want.
b. On the DDRx Wizard - Write Leveling Page, import
DDR3Delays_autogenerated.txt or the file name you assigned in step 3.

Related Topics
“Write Leveling for DDR3” on page 817

“DDRx Wizard - Write Leveling Page” on page 880

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DDRx Batch Simulation Results

Each DDRx batch simulation creates a new subfolder in the <design> folder to contain the
results files. The subfolder name is of form:

DDR_Results_<month>-<day>-<year>_<hour>h-<minute>m
Example: <design>\DDR_Results_Nov-30-2008_11h-33m
See “Data Flow for DDRx Batch Simulation” on page 799.

Note
Waveform measurements described in this document are at the pin of the device by
default. If the IBIS model includes the parameter “Timing_location = die”, the
measurements for that device will be done on the die waveforms.

Use Windows Explorer or another file manager to access the report files. You manually delete
obsolete report folders and files.

This topic contains the following:

• “DDRx Results Spreadsheets” on page 824

• “DDRx Waveform Files” on page 843
• “DDR3 Write-Leveling Delay Files” on page 845
• “DDRx Log File” on page 845
• “DDRx Audit Spreadsheet” on page 846

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Results Spreadsheets

DDRx results spreadsheets contain measurement values and pass/fail status, and are in
Microsoft Excel (.XLS) format. Spreadsheet rows contain measurements for one write or read
cycle.

Tip: Spreadsheet cells with a red background indicate measurements that violate timing
model requirements. Spreadsheet cells with a yellow background indicate a minimum
setup or hold time margin.

This topic contains the following:

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• “DDRx Data Spreadsheets” on page 826

DDR_report_data_*.xls
• “DDRx Address Spreadsheets” on page 831
DDR_report_address_*.xls
• “DDRx Skew Spreadsheets” on page 835
DDR_report_skew_*.xls
• “DDRx SI Spreadsheets” on page 840
DDR_report_SI_measurements_*.xls
• “DDRx Wizard Pages Affecting Spreadsheet Contents” on page 843

Stimulus Offset and Initial Delay Delta

Each of the simulation results spreadsheets mentions a quantity called Initial Delay Delta. This
is a timing number that the DDRx Wizard uses to minimize the actual number of simulations
that it needs to run. The wizard simulates the individual signals with an offset built in to the
stimulus pattern. The Stimulus Offset is described below. The wizard calculates the offsets of
the different signal types based on the appropriate timing models that you specifies on the
DDRx Wizard - Timing Models Page. For example, the controller timing model specifies
tDQSDQ, the DQ pre-launch delay relative to DQS, with a minimum and maximum value. The
DDRx wizard must check timing margin at the minimum and maximum skews, but instead of
simulating both conditions, the wizard simulates once and then mathematically adjusts for the
minimum and maximum corners. In order to do just one simulation, the wizard calculates the
average of the minimum and maximum of the skew and calls this delay the typical delay. This
value is used in the stimulus offset calculations that drive the actual simulations. The simulation
waveforms then have a typical timing delay that the wizard measures between different signals
such as DQS to DQ. In order to calculate timing margins, the DDRx wizard must compare
timing differences at the worst cases. The worst case at the driver is when the delay is at the
minimum or maximum. Because the typical delay was calculated to be the midpoint between
the minimum and maximum delays, the difference from the typical value to either the minimum
or maximum is one half of the difference between the minimum and maximum. This difference
from the typical to either the minimum or maximum is called the Initial Delay Delta. The initial
delay delta is subtracted from the calculation of both setup and hold margin because the margin
equations are constructed such that positive margin is good and negative margin is a violation.
The initial delay delta diminishes the margin in both cases.

Stimulus Offset
Stimulus offset is calculated from the typical delays between the different groups of signals as
shown in Figure 17-27 on page 826. The calculations use the last rising clock edge in the
diagram as the reference point, t=0. In Figure 17-27, this point coincides with the typical DQS
delay and so is labeled “DQS(typ).” The stimulus delays reported in the results spreadsheets are

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relative to this clock edge and so are usually reported as negative numbers. The simulation of
the data and strobe signals in a read operation are separate and the stimulus offset is dependent
on just the typical delay between DQ and DQS output from the DRAM. The diagram also
shows that the typical delays used in stimulus offset are the midpoints between the respective
minimum and maximum values. The typical value is calculated internally, but is not shown in
the timing model viewer. The diagram in Figure 17-27 shows the case of 2T timing where the
ADDR/CMD signals are output 1 clock period before the CTL signals. In the case of 1T timing
the ADDR(typ) delay is close to or equal to the CTL(typ) delay shown in the diagram. In DDR3
simulations, the stimulus offset for each DQS signal and its associated DQ group can be
specified independently. These different stimulus offsets are reported in the data signal results
spreadsheet.

Figure 17-27. Stimulus Offset is Calculated from Typical Delays

Related Topics
“Effects of Delay Ranges on Setup and Hold Measurements” on page 814

DDRx Data Spreadsheets

These spreadsheets report setup and hold measurements for the following types of signals in the
DDRx interface:

• Data and data mask—Data nets are measured relative to strobes. Report file name is of
form:
DDR_report_data_[violations | worstcases | allcases]_[Typ | Fast | Slow].xls
where:

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violations contains only nets that violate timing-model requirements.

worst cases contains all nets and their worst-case measurements.

allcases contains all nets and all measurements (for each cycle in the simulation).

Typ, Fast, Slow represent IC model corners.

Tip: In the data spreadsheets there are two rows for each signal. The first row for a signal
contains setup measurements and the second row for a signal contains hold
measurements.

Table 17-17 defines spreadsheet column headings.

Table 17-16. DDRx Data Spreadsheet Column Definitions

Column Name Definition
Net Name Name of the measured net. For multiple-board projects,
the net name does not include the board ID. See “About
Board IDs” on page 752.
Pass/Fail “Fail” if any measurements fail, based on timing model
limits. If either the setup margin in (O) or the hold
margin in (U) is less than 0ps, this column will be Fail,
will be shaded red, and the negative margin will be
shaded red in its respective cell. It can also be Fail
when measurements could not be performed for this
edge. In this case all numerical cells are empty and in
the Comments column there should be a description of
the issue.
Operation Indicates whether the DDRx interface is writing to slot
1-2 or reading from rank 1-4. Slot 1 corresponds to
ranks 1-2 and slot 2 corresponds to ranks 3-4, and so
on.
Driver Comp Ref Des & Pin Name Driver component reference designator and pin name
for the measured net. For multiple-board projects, the
net name contains the board ID. See “About Board
IDs” on page 752.

You can use this information to find the related

waveform file, if you enabled the save waveform files
option on the Report Options wizard page.

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Table 17-16. DDRx Data Spreadsheet Column Definitions (cont.)

Column Name Definition
Receiver Comp Ref Des & Pin Name Receiver component reference designator and pin name
for the measured net. For multiple-board projects, the
net name contains the board ID. See “About Board
IDs” on page 752.

You can use this information to find the related

waveform file, if you enabled the save waveform files
option on the Report Options wizard page.
Associated Clk/Strobe Net Name Name of the strobe net paired with the measured net.
Associated Clk/Strobe Driver Comp Driver component reference designator and pin name
Ref Des & Pin Name for the strobe net paired with the measured net.
Associated Clk/Strobe Receiver Receiver component designator and pin name for the
Comp Ref Des & Pin Name strobe net paired with the measured net.
Clk/Strobe Crossing Threshold Time, Time in the simulation when the strobe waveforms
[ns] cross zero (differential) or VREF (single-ended).

Setup/hold times are measured before/after this time.

You can investigate measurement results by viewing

waveform files (if you enable saving waveform files)
and using this time.
Setup Time (From Sim), tDS, [ps] The measured data and strobe setup time, prior to
derating.

Measurements start when the data waveform either:

• First crosses the AC threshold after the last crossing
of the DC threshold.
• Last crosses the AC threshold (in the case where the
model does not provide a DC threshold or the DC
and AC thresholds are the same).

Measurements end when the corresponding strobe

waveform crosses zero (differential) or VREF (single-
ended).

The measured setup time is based on the “average”

driver delay. See “Effects of Delay Ranges on Setup
and Hold Measurements” on page 814.

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Table 17-16. DDRx Data Spreadsheet Column Definitions (cont.)

Column Name Definition
Min Setup Time, tDS(min) = tDS - Setup time obtained by shifting data waveforms to the
Initial Delay Delta, [ps] right, within the specified range of initial delays. This
represents the worst setup time that can be obtained by
varying the initial delay.

The calculation is (Setup Time (From Sim), tIS, [ps])

minus (Initial delay delta), where:

Initial delay delta—(((Maximum initial delay for DQS

and CK) minus (Minimum initial delay for DQS and
CK))/2).

See “Stimulus Offset and Initial Delay Delta” on

page 825.
Base Setup Time, tDS(base), [ps] The setup limit whose value is defined in the timing
model.
Setup Derate Time Delta d(tDS), [ps] The setup derating value obtained from derating tables
built into DDRx batch simulation or contained in the
timing model. Values can be positive or negative.

The log file contains derating calculation details, such

as slew rates for data and strobe nets. See “DDRx Log
File” on page 845.

See also: “Derating DDR2 and DDR3 Setup and Hold

Times” on page 804
Required Setup Time, tDS(req) = The adjusted setup limit, where the value from the
tDS(base) + d(tDS), [ps] timing model is adjusted by the setup derating value.

The calculation is (Base Setup Time, tIS(base), [ps])

plus (Setup Derate Time Delta d(tIS), [ps]).
Setup Time Margin, tDS(margin) = The margin (or slack) remaining after subtracting the
tDS(min) - tDS(req), [ps] slew-rate-adjusted setup limit from the measured setup
time. Negative values produce errors.

The calculation is (Min Setup Time, tIS(min) = tIS -

Initial Delay Delta, [ps]) minus (Required Setup Time,
tIS(req) = tIS(base) + d(tIS), [ps]).

Tip: Spreadsheet cells with a yellow background

indicate a minimum setup time margin.

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Table 17-16. DDRx Data Spreadsheet Column Definitions (cont.)

Column Name Definition
Hold Time (From Sim), tDH, [ps] The measured data hold time, prior to derating.

Measurements start when the strobe waveform crosses

zero (differential) or VREF (single-ended).

Measurements start when the data waveform either:

• First crosses the AC threshold after the last crossing
of the DC threshold.
• Last crosses the AC threshold (in the case where the
model does not provide a DC threshold or the DC
and AC thresholds are the same).

The measured hold time is based on the “average”

driver delay. See “Effects of Delay Ranges on
Setup and Hold Measurements” on page 814.
Min Hold Time, tDH(min) = tDH - Hold time obtained by shifting data waveforms to the
Initial Delay Delta, [ps] left, within the specified range of initial delays. This
represents the worst hold time that can be obtained by
varying the initial delay.

The calculation is (Hold Time (From Sim), tIH, [ps])

minus (Initial delay delta), where:

Initial delay delta—(((Maximum initial delay for DQS

and CK) minus (Minimum initial delay for DQS and
CK))/2).
Base Hold Time, tDH(base), [ps] The hold limit whose value is defined in the timing
model.
Hold Derate Time Delta d(tDH), [ps] The hold derating value obtained from derating tables
built into DDRx batch simulation. Values can be
positive or negative.

The log file contains derating calculation details, such

as slew rates for data and strobe nets. See “DDRx Log
File” on page 845.

See also: “Derating DDR2 and DDR3 Setup and Hold

Times” on page 804
Required Hold Time, tDH(req) = The adjusted hold limit, where the value from the
tDH(base) + d(tDH), [ps] timing model is adjusted by the hold derating value.

The calculation is (Base Hold Time, tIH(base), [ps])

plus (Hold Derate Time Delta d(tIH), [ps]).

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Table 17-16. DDRx Data Spreadsheet Column Definitions (cont.)

Column Name Definition
Hold Time Margin, tDH(margin) = The margin (or slack) remaining after subtracting the
tDH(min) - tDH(req), [ps] slew-rate-adjusted hold limit from the measured hold
time. Negative values produce errors.

The calculation is (Min Hold Time, tIH(min) = tIH -

Initial Delay Delta, [ps]) minus (Required Hold Time,
tIH(req) = tIH(base) + d(tIH), [ps]).

Tip: Spreadsheet cells with a yellow background

indicate a minimum hold time margin.
Stimulus Offset, [ns] The timing offset between drivers on the data and
strobe nets, when the initial strobe delay is average.

See also: “Effects of Delay Ranges on Setup and Hold

Measurements” on page 814 and “Stimulus Offset and
Initial Delay Delta” on page 825.
% of Cycles With Failures Percentage of waveform measurements with either of
the following properties:
• The measured value fails the limit value
• The measurement itself failed for some reason
Restriction: Only the violations spreadsheets contain
this column.
Comments Displays error or other measurement problem
information.

DDRx Address Spreadsheets

These spreadsheets report setup and hold measurements for the following types of signals in the
DDRx interface:

• Address, control, and command—Address, command, and control nets are measured
relative to clocks. Report file name is of form:
DDR_report_address_[violations | worstcases | allcases]_[Typ | Fast | Slow].xls
where:

violations contains only nets that violate timing-model requirements.

worst cases contains all nets and their worst-case measurements.

allcases contains all nets and all measurements (for each cycle in the simulation).

Typ, Fast, Slow represent IC model corners.

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Table 17-17 defines spreadsheet column headings.

Table 17-17. DDRx Address Spreadsheet Column Definitions

Column Name Definition
Net Name Name of the measured net. For multiple-board projects,
the net name does not include the board ID. See “About
Board IDs” on page 752.
Pass/Fail “Fail” if any measurements fail, based on timing model
limits.
Operation Indicates whether the DDRx interface is writing to slot
1-2 or reading from rank 1-4.
Driver Comp Ref Des & Pin Name Driver component reference designator and pin name
for the measured net. For multiple-board projects, the
net name contains the board ID. See “About Board
IDs” on page 752.

You can use this information to find the related

waveform file, if you enabled the save waveform files
option on the Report Options wizard page.
Receiver Comp Ref Des & Pin Name Receiver component reference designator and pin name
for the measured net. For multiple-board projects, the
net name contains the board ID. See “About Board
IDs” on page 752.

You can use this information to find the related

waveform file, if you enabled the save waveform files
option on the Report Options wizard page.
Associated Clk/Strobe Net Name Name of the clock net paired with the measured net.
Associated Clk/Strobe Driver Comp Driver component reference designator and pin name
Ref Des & Pin Name for the clock net paired with the measured net.
Associated Clk/Strobe Receiver Receiver component designator and pin name for the
Comp Ref Des & Pin Name clock net paired with the measured net.
Clk/Strobe Crossing Threshold Time, Time in the simulation when the clock waveforms cross
[ns] zero.

Setup/hold times are measured before/after this time.

You can investigate measurement results by viewing

waveform files (if you enable saving waveform files)
and using this time.

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Table 17-17. DDRx Address Spreadsheet Column Definitions (cont.)

Column Name Definition
Setup Time (From Sim), tIS, [ps] The measured address and clock setup time, prior to
derating. Measurements start when the address
waveform last crosses the AC threshold and end when
the corresponding clock waveform crosses zero.

The measured setup time is based on the “average”

driver delay. See “Effects of Delay Ranges on Setup
and Hold Measurements” on page 814.
Min Setup Time, tIS(min) = tIS - Setup time obtained by shifting address waveforms to
Initial Delay Delta, [ps] the right, within the specified range of initial delays.
This represents the worst setup time that can be
obtained by varying the initial delay.

The calculation is (Setup Time (From Sim), tIS, [ps])

minus (Initial delay delta), where:

Initial delay delta—(((Maximum initial delay for DQS

and CK) minus (Minimum initial delay for DQS and
CK))/2).

See “Stimulus Offset and Initial Delay Delta” on

page 825.
Base Setup Time, tIS(base), [ps] The setup limit whose value is defined in the timing
model.
Setup Derate Time Delta d(tIS), [ps] The setup derating value obtained from derating tables
built into DDRx batch simulation or specified in the
timing model. Values can be positive or negative.

The log file contains derating calculation details, such

as slew rates for data and strobe nets. See “DDRx Log
File” on page 845.

See also: “Derating DDR2 and DDR3 Setup and Hold

Times” on page 804
Required Setup Time, tIS(req) = The adjusted setup limit, where the value from the
tIS(base) + d(tIS), [ps] timing model is adjusted by the setup derating value.

The calculation is (Base Setup Time, tIS(base), [ps])

plus (Setup Derate Time Delta d(tIS), [ps]).

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Table 17-17. DDRx Address Spreadsheet Column Definitions (cont.)

Column Name Definition
Setup Time Margin, tIS(margin) = The margin (or slack) remaining after subtracting the
tIS(min) - tIS(req), [ps] slew-rate-adjusted setup limit from the measured setup
time. Negative values produce errors.

The calculation is (Min Setup Time, tIS(min) = tIS -

Initial Delay Delta, [ps]) minus (Required Setup Time,
tIS(req) = tIS(base) + d(tIS), [ps]).

Tip: Spreadsheet cells with a yellow background

indicate a minimum setup time margin.
Hold Time (From Sim), tIH, [ps] The measured address and clock hold time, prior to
derating. Measurements start when the address
waveform crosses the DC threshold and end when the
clock waveform crosses zero. If the IBIS model does
not contain the DC threshold, the AC threshold is used
instead.

The measured hold time is based on the “average”

driver delay. See “Effects of Delay Ranges on Setup
and Hold Measurements” on page 814.
Min Hold Time, tIH(min) = tIH - Hold time obtained by shifting address waveforms to
Initial Delay Delta, [ps] the left, within the specified range of initial delays. This
represents the worst hold time that can be obtained by
varying the initial delay.

The calculation is (Hold Time (From Sim), tIH, [ps])

minus (Initial delay delta), where:

Initial delay delta—(((Maximum initial delay for DQS

and CK) minus (Minimum initial delay for DQS and
CK))/2).
Base Hold Time, tIH(base), [ps] The hold limit whose value is defined in the timing
model.
Hold Derate Time Delta d(tIH), [ps] The hold derating value obtained from derating tables
built into DDRx batch simulation. Values can be
positive or negative.

The log file contains derating calculation details, such

as slew rates for data and strobe nets. See “DDRx Log
File” on page 845.

See also: “Derating DDR2 and DDR3 Setup and Hold

Times” on page 804

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Table 17-17. DDRx Address Spreadsheet Column Definitions (cont.)

Column Name Definition
Required Hold Time, tIH(req) = The adjusted hold limit, where the value from the
tIH(base) + d(tIH), [ps] timing model is adjusted by the hold derating value.

The calculation is (Base Hold Time, tIH(base), [ps])

plus (Hold Derate Time Delta d(tIH), [ps]).
Hold Time Margin, tIH(margin) = The margin (or slack) remaining after subtracting the
tIH(min) - tIH(req), [ps] slew-rate-adjusted hold limit from the measured hold
time. Negative values produce errors.

The calculation is (Min Hold Time, tIH(min) = tIH -

Initial Delay Delta, [ps]) minus (Required Hold Time,
tIH(req) = tIH(base) + d(tIH), [ps]).

Tip: Spreadsheet cells with a yellow background

indicate a minimum hold time margin.
Stimulus Offset, [ns] The timing offset between drivers on the address and
clocknets, when the initial clock delay is average.

See also: “Effects of Delay Ranges on Setup and Hold

Measurements” on page 814 and “Stimulus Offset and
Initial Delay Delta” on page 825.
% of Cycles With Failures Percentage of waveform measurements with either of
the following properties:
• The measured value fails the limit value
• The measurement itself failed for some reason
Restriction: Only the violations spreadsheets contain
this column.
Comments Displays error or other measurement problem
information.

DDRx Skew Spreadsheets

These spreadsheets report skew measurements for clocks and strobes in the DDRx interface.
Skew is produced by routing, crosstalk, and other factors. DDRx batch simulation does not
introduce random jitter.

File names are of form:

DDR_report_skew_[violations | worstcases | allcases]_[Typ | Fast | Slow].xls

where:

violations contains only nets that violate timing-model requirements.

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worst cases contains all nets and their worst-case measurements.

allcases contains all nets and all measurements (for each cycle in the simulation).
Typ, Fast, Slow represent IC model corners.
The timing model provides limits. You can graphically display tDQSS, tDSS, and other timing
model parameters, see “DDRx Wizard - Timing Models Page” on page 876. JEDEC
specification JESD79* defines timing model parameters.

Table 17-18 defines spreadsheet column headings.

Note
Measurements in Table 17-18 are based the “average” driver delay, unless specified
otherwise. See “Effects of Delay Ranges on Setup and Hold Measurements” on page 814.

Table 17-18. DDRx Skew Spreadsheet Column Definitions

Column Name Definition
Net Name Name of the measured net. For multiple-board projects,
the net name does not include the board ID. See “About
Board IDs” on page 752.
Pass/Fail “Fail” if any measurements fail, based on timing model
limits.
Operation Indicates whether the DDRx interface is writing to slot
1-2 or reading from rank 1-4.
Driver Comp Ref Des & Pin Name Driver component reference designator and pin name
for the measured net. For multiple-board projects, the
net name contains the board ID. See “About Board
IDs” on page 752.

You can use this information to find the related

waveform file, if you enabled the save waveform files
option on the Report Options wizard page.
Receiver Comp Ref Des & Pin Name Receiver component reference designator and pin name
for the measured net. For multiple-board projects, the
net name contains the board ID. See “About Board
IDs” on page 752.

You can use this information to find the related

waveform file, if you enabled the save waveform files
option on the Report Options wizard page.

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Table 17-18. DDRx Skew Spreadsheet Column Definitions (cont.)

Column Name Definition
Associated Clk/Strobe Net Name Name of the clock or strobe net paired with the
measured net.

Associated Clk/Strobe Driver Comp Driver component reference designator and pin name
Ref Des & Pin Name for the clock or strobe net paired with the measured net.

Associated Clk/Strobe Receiver Receiver component reference designator and pin name
Comp Ref Des & Pin Name for the clock or strobe net paired with the measured net.
Clk Launch Time (From Sim), [ns] Time at driver when the differential clock signals cross
zero.
Clk Arrival Time (From Sim), [ns] Time at receiver when the differential clock signals
cross zero.
Clk Delay Time, [ps] The calculation is (Clk Launch Time (From Sim), [ns])
minus (Clk Arrival Time (From Sim), [ns]).
Strobe Launch Time (From Sim), [ns] Time at driver when the strobe crosses zero
(differential) or VREF (single-ended).
Strobe Arrival Time (From Sim), [ns] Time at receiver when the strobe crosses zero
(differential) or VREF (single-ended).
Strobe Delay Time, [ps] The calculation is (Strobe Launch Time (From Sim),
[ns]) minus (Strobe Arrival Time (From Sim), [ns]).
Launch Skew Time (min), [ps] Difference between Strobe Launch Time (From Sim),
[ns] and Clk Launch Time (From Sim), [ns] when the
initial strobe/clock delay for the strobe and clock
signals is minimum.

The calculation is (Launch Skew Time (typ), [ps])

minus (Initial delay delta), where:

Initial delay delta—(((Maximum initial strobe/clock

delay) minus (Minimum initial strobe/clock delay))/2).
Launch Skew Time (typ), [ps] Difference between Strobe Launch Time (From Sim),
[ns] and Strobe Launch Time (From Sim), [ns] when
the initial strobe/clock delay for DQS and CK is
average.

The calculation is (Strobe Launch Time (From Sim),

[ns]) minus (Clk Launch Time (From Sim), [ns]).

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Table 17-18. DDRx Skew Spreadsheet Column Definitions (cont.)

Column Name Definition
Launch Skew Time (max), [ps] Difference between Strobe Launch Time (From Sim),
[ns] and Clk Launch Time (From Sim), [ns] when the
initial strobe/clock delay for the strobe and clock
signals is maximum.

The calculation is (Launch Skew Time (typ), [ps]) plus

(Initial delay delta), where:

Initial delay delta—(((Maximum initial strobe/clock

delay) minus (Minimum initial strobe/clock delay))/2).
tDQSS Skew Time (early), [ps] Difference between Strobe Arrival Time (From Sim),
[ns] and Clk Arrival Time (From Sim), [ns] when the
initial strobe/clock delay is minimum.

The calculation is (tDQSS Skew Time (typ), [ps])

minus (Initial delay delta), where:

Initial delay delta—(((Maximum initial strobe/clock

delay) minus (Minimum initial strobe/clock delay))/2).
tDQSS Skew Time (typ), [ps] Difference between Strobe Arrival Time (From Sim),
[ns] and Clk Arrival Time (From Sim), [ns] when the
initial strobe/clock delay is average.

The calculation is (Strobe Arrival Time (From Sim),

[ns]) minus (Clk Arrival Time (From Sim), [ns]).

The value is zero when the strobe and clock are

aligned.
tDQSS Skew Time (late), [ps] Difference between Strobe Arrival Time (From Sim),
[ns] and Clk Arrival Time (From Sim), [ns] when the
initial strobe/clock delay is maximum.

The calculation is (tDQSS Skew Time (typ), [ps]) plus

(Initial delay delta), where:

Initial delay delta—(((Maximum initial strobe/clock

delay) minus (Minimum initial strobe/clock delay))/2).

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Table 17-18. DDRx Skew Spreadsheet Column Definitions (cont.)

Column Name Definition
tDSS Setup Time (From Sim), [ps] Difference between the clock arrival time (current
cycle) and the strobe arrive time (previous cycle) when
the initial strobe/clock delay is maximum (that is, a late
strobe).

The calculation is (Clk Arrival Time (From Sim), [ns])

minus (Strobe Arrival Time (From Sim), [ns]).

Value is “N/A” when tDQSS Skew Time (late), [ps] is

a negative value. The ideal value is one bit time.
tDSH Hold Time (From Sim), [ps] Difference between the strobe arrival time (next cycle)
and the clock arrival time (current cycle) when the
initial strobe/clock delay is minimum (that is, an early
strobe).

The calculation is (Strobe Arrival Time (From Sim),

[ns]) minus (Clk Arrival Time (From Sim), [ns]).

Value is “N/A” when tDQSS Skew Time (early), [ps] is

a positive value. The ideal value is one bit time.
Negative tDQSS Limit, [ps] Value from DRAM timing model. See “DDRx Wizard
- Timing Models Page” on page 876.
Positive tDQSS Limit, [ps] Value from DRAM timing model. See “DDRx Wizard
- Timing Models Page” on page 876.
tDSS Limit, [ps] Value from DRAM timing model. See “DDRx Wizard
- Timing Models Page” on page 876.
tDSH Limit, [ps] Value from DRAM timing model. See “DDRx Wizard
- Timing Models Page” on page 876.
tDQSS (early) Time Margin = The calculation is (tDQSS Skew Time (early), [ps])
tDQSS(early) - tDQSS(negative minus (Negative tDQSS Limit, [ps]).
limit), [ps]
Value is negative when it exceeds the limit.

Tip: Spreadsheet cells with a yellow background

indicate a minimum tDQSS margin.
tDQSS (late) Time Margin = The calculation is (Positive tDQSS Limit, [ps]) minus
tDQSS(positive limit) - tDQSS(late), (tDQSS Skew Time (late), [ps]).
[ps]
Value is negative when it exceeds the limit.

Tip: Spreadsheet cells with a yellow background

indicate a minimum tDQss margin.

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Table 17-18. DDRx Skew Spreadsheet Column Definitions (cont.)

Column Name Definition
tDSS Time Margin = tDSS - The calculation is (tDSS Limit, [ps]) minus ((tDSS
tDSS(limit), [ps] Setup Time (From Sim), [ps]).

Value is negative when it exceeds the limit.

tDSH Time Margin = tDSH - The calculation is (tDSH Limit, [ps]) minus (tDSH
tDSH(limit), [ps] Hold Time (From Sim), [ps]).

Value is negative when it exceeds the limit.

Stimulus Offset, [ps] The timing offset between the drivers on the clock and
strobe nets, when the initial strobe/clock delay is
average.

See “Stimulus Offset and Initial Delay Delta” on

page 825.
% of Cycles With Failures Percentage of waveform measurements with either of
the following properties:
• The measured value fails the limit value
• The measurement itself failed for some reason
Restriction: Only the violations spreadsheets contain
this column.
Comments Displays error or other measurement problem
information.

DDRx SI Spreadsheets
These spreadsheets report signal-integrity measurements for all nets in the DDRx interface. File
names are of form:

DDR_report_SI_measurements_[Typ | Fast | Slow].xls

where:

Typ, Fast, Slow represent IC model corners

Table 17-19. DDRx SI Spreadsheet Column Definitions
Column Name Definition
Net Name Name of the measured net. For multiple-board projects,
the net name does not include the board ID. See “About
Board IDs” on page 752.
Pass/Fail “Fail” if any measurements fail, based on IBIS model
requirements or requirements built into DDRx batch
simulation.

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Table 17-19. DDRx SI Spreadsheet Column Definitions (cont.)

Column Name Definition
Operation Indicates whether the DDRx memory interface is
writing to slot 1-2 or reading from rank 1-4.
Driver Comp Ref Des & Pin Name Driver component reference designator and pin name
for the measured net. For multiple-board projects, the
net name contains the board ID. See “About Board
IDs” on page 752.

You can use this information to find the related

waveform file, if you enabled the save waveform files
option on the Report Options wizard page.
Receiver Comp Ref Des & Pin Name Receiver component reference designator and pin name
for the measured net. For multiple-board projects, the
net name contains the board ID. See “About Board
IDs” on page 752.

You can use this information to find the related

waveform file, if you enabled the save waveform files
option on the Report Options wizard page.
Rise Min Delay, [ps] Minimum delay from the driver to the receiver on the
net, measured from the time the rising waveform
crosses VMEAS at the driver to the first time it crosses
VILac at the receiver.

This is an uncompensated flight-time delay.

Rise Max Delay, [ps] Delay from the driver to the receiver, measured from
the time the rising waveform crosses VMEAS at the
driver to the last time it crosses VIHac at the receiver.

This is an uncompensated flight-time delay.

Fall Min Delay, [ps] Delay from the driver to the receiver on the net,
measured from the time the falling waveform crosses
VMEAS at the driver to the first time it crosses VIHac at
the receiver.

This is an uncompensated flight-time delay.

Fall Max Delay, [ps] Delay from the driver to the receiver, measured from
the time the falling waveform crosses VMEAS at the
driver to the last time it crosses VILac at the receiver.

This is an uncompensated flight-time delay.

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Table 17-19. DDRx SI Spreadsheet Column Definitions (cont.)

Column Name Definition
Rail Overshoot, [mV] Maximum voltage above the power rail, for a rising-
edge transition at the receiver.

The area of the overshoot region is not measured.

Rail Undershoot, [mV] Minimum voltage below the ground rail, for a falling-
edge transition at the receiver.

The area of the overshoot region is not measured.

Rail Overshoot/Undershoot “Fail” if the waveform at the receiver passes more than
[Pass/Fail] a threshold beyond the power/ground rail. You can edit
the threshold on the Simulation Options page. See
“DDRx Wizard - Simulation Options Page” on
page 883.
Monotonic [Pass/Fail] “Fail” if the waveform at the receiver reverses direction
while between VILac and VIHac.
DC Thresholds Multi Cross “Fail” if the waveform at the receiver has either of the
[Pass/Fail] following conditions:
• The rising waveform crosses VIHdc more than
once.
• The falling waveform crosses VILdc more than
once.
Vref Threshold Multi Cross “Fail” if the rising or falling waveform at the receiver
[Pass/Fail] passes through VREF more than once.
Max Slew Time, [ps] The maximum time the waveform at the receiver takes
to pass between VILac and VIHac.

“N/A” if the IBIS model does not specify [Receiver

Thresholds] with sub-parameters Tslew_ac for single-
ended signals and Tdiffslew_ac for differential signals.
Max Slew Time [Pass/Fail] “Fail” if the waveform at the receiver has excessive
slew time.

“N/A” if the IBIS model does not specify [Receiver

Thresholds] keywords with sub-parameters Tslew_ac
for single-ended signals and Tdiffslew_ac for
differential signals.

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Table 17-19. DDRx SI Spreadsheet Column Definitions (cont.)

Column Name Definition
Differential Crossover Limits “Fail” if the differential waveforms at the receivers
[Pass/Fail] cross outside the limits.

“N/A” if the IBIS model does not specify [Receiver

Thresholds] keywords with sub-parameters
Vcross_low and Vcross_high values.

“N/A” if the net is single-ended.

General measurement rules when signal has multiple

crossings:
• For data/address/command/control nets crossing an
AC threshold, use the last crossing.
• For data/address/command/control nets crossing a
DC threshold, use the first crossing.
For strobe/clock nets crossing the reference or
differential threshold, use the first crossing.

DDRx Wizard Pages Affecting Spreadsheet Contents

The following wizard pages affect the measurements and results reported by spreadsheets:

• Nets to Simulate—Choose which portions of the memory interface to simulate. This

page determines the nets displayed on the Disable Nets page.
• Disable Nets—Choose individual nets to not simulate.
• Simulation Options—Choose which IC model corners to simulate.
• Report Options—Choose whether to highlight errors in cells with a red background.

DDRx Waveform Files

You typically use waveform files to investigate measurements reported in spreadsheets. Many
waveform files are created when you simulate all or many memory interface nets.

Each waveform is written to comma-separated values (CSV) format. You can display waveform
files in the oscilloscope or by third-party software.

DDRx Waveforms - Sub-folders

The DDR_Results* folder contains additional sub-folders that contain optional waveform files.
To help you manage the large number of waveform files, sub-folders sort the waveform files by
drive/receive modes and IC model corner values. The waveform subfolder names are of form:

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[DRV | RCV]_Waveforms_[Fast | Typ | Slow]

where:

Typ, Fast, Slow represent IC model corners.

Example: <design>\DDR_Results_Nov-30-2008_11h-33m\DRV_Waveforms_Slow

DDRx Waveforms - Files

Each waveform file contains data for one pin.

Driver waveform file names are of form:

net-<net_name>;drv-<refdes>.<pin1>&<pin2>;<operation>_[after | before]_shift.csv
Receiver waveform file names are of form:

net-<net_name>;drv-<refdes>.<pin1>&<pin2>;rcv-<refdes>.<pin1>&<pin2>;
<operation>_[after | before]_shift.csv
where:

<net_name> is the name of the net

<refdes> is the reference designator and board name of the of the component
<pin1> is the pin name. For a differential signal, it is the positive pin.
<pin2> is the pin name of the negative pin of a differential signal. It is absent for single-
ended signals. “&” separates <pin1> and <pin2>.
<operation> is W for write, R for read, number for rank number (1 = slot1/rank1)
_[after | before]_shift is for strobe signals. It is absent for non-strobe signals.
The “before_shift” waveform is what you would see at the controller pin with an
oscilloscope at a test bench.
The “after_shift” waveform is what you see inside the controller, after it is shifted by
controller circuitry. Setup and hold measurements use this measurement.
Example:

net-RDSQ0;drv-U123_B00.DQS0+&DQS0-;drv-U321_B01.A0&A1;
R1_after_shift.csv
Waveform files contain either a sampling or all data created by simulation:

• Save a sampling of all data points to conserve disk space. The sampling rate is one in
ten, meaning that every tenth data point from simulation is written to the waveform file.

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• Save all data points.

Use the Report Options page to choose between waveforms containing sampled and all
data points. See “DDRx Wizard - Report Options Page” on page 884.

Related Topics
“Loading Waveform Files” on page 598

DDR3 Write-Leveling Delay Files

DDR3Delays_autogenerated.txt contains byte-lane specific delays for data signals during
memory-write cycles. This file is located in the <design> folder. See “About Design Folder
Locations” on page 1391.

You should not edit this file directly. See “Creating DDR3 Write-Leveling Delay Files” on
page 822. To manually specify delays, use the spreadsheet in the DDRx Wizard - Write
Leveling Page.

Related Topics
“Write Leveling for DDR3” on page 817

DDRx Log File

DDR_log{<DDRx_setup_file_name>}.txt contains simulation/measurement progress and
messages for DDRx batch simulation. This file is also used to report audit results. You can view
this file to investigate results or simulation failures.

The log file contains the following:

• Names of simulated nets and driver/receiver configuration

• For ODT, model selector values for specific simulations
• Initial delay applied to the driver
• Errors and warnings from simulation and measurements
• Measurement details
• Names of nets coupled by crosstalk, if required
• General errors for each net
• Total run time

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DDRx Audit Spreadsheet

DDR_audit{<DDRx_setup_file_name>}.xls contains information about simulation setup
problems for all pins in the DDRx interface. This is an optional file that is written only when
you enable the audit feature.

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DDRx Batch-Mode Wizard Dialog Box

DDRx Batch-Mode Wizard Dialog Box

To access: Simulate SI > Run DDRx Simulation (DDRx Batch-Mode Wizard)

This section contains the Help topics for the DDRx Batch-Mode Wizard.

You can navigate directly to a wizard page by clicking its name in the table of contents pane,
which is located near the left side of each wizard dialog box. However, you cannot jump ahead
to a page if required information is missing on a previous page.

The list of wizard pages is variable and can change depending on options you set. For example,
the ODT Models page is displayed only if you enable the DDR2 or DDR3 interface option in
the Initialization page. Similarly, if you disable the “Address, Command, and Control Timing”
option on the Nets to Simulate page, the Addr/Comm Nets and Control Nets pages are not
displayed.

The color of a non-highlighted page name indicates the following:

• White—Visited page, even if you did not edit any values on it

• Red—Unvisited page
• Gray—Unavailable page until you specify required data or settings on a previous page
This topic contains the following:

• “DDRx Wizard - Introduction Page” on page 848

• “DDRx Wizard - Initialization Page” on page 850
• “DDRx Wizard - Controller Page” on page 852
• “DDRx Wizard - DRAMs Page” on page 854
• “DDRx Wizard - PLLs and Registers Page” on page 861
• “DDRx Wizard - IBIS Models Page” on page 863
• “DDRx Wizard - Nets to Simulate Page” on page 863
• “DDRx Wizard - DRAM Signals Page” on page 864
• “DDRx Wizard - Data Strobes Page” on page 865
• “DDRx Wizard - Data Nets Page” on page 866
• “DDRx Wizard - Clock Nets Page” on page 868
• “DDRx Wizard - Address and Command Nets Page” on page 869
• “DDRx Wizard - Control Nets Page” on page 871
• “DDRx Wizard - Disable Nets Page” on page 872

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• “DDRx Wizard - IBIS Models Selectors Page” on page 873

• “DDRx Wizard - ODT Models Page” on page 874
• “DDRx Wizard - ODT Behavior Page” on page 874
• “DDRx Wizard - Timing Models Page” on page 876“DDRx Wizard - Write Leveling
Page” on page 880
• “DDRx Wizard - Stimulus and Crosstalk Page” on page 881
• “DDRx Wizard - Simulation Options Page” on page 883
• “DDRx Wizard - Report Options Page” on page 884
• “DDRx Wizard - Simulate Page” on page 885
• “DDRx Batch Mode - Run Simulation Dialog Box” on page 886
• “Selecting Spreadsheet Rows in the DDRx Wizard” on page 849

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Introduction Page

To access: Simulate SI > Run DDRx Simulation (DDRx Batch-Mode Wizard)

This page summarizes the capabilities and usage of the DDRx batch simulation wizard. All
pages in the wizard provide abundant on-screen information to help you set up batch simulation
for designs with DDR, DDR2, DDR3, LPDDR, or LPDDR2 interfaces.

Caution
Timing measurements and derating adjustments require thousands of simulations. On a
computer with a modern CPU and abundant RAM, running DDRx batch simulation can
take tens of minutes (few measurements enabled) to hours (all measurements enabled).

Before simulating the complete DDRx interface, you should verify the design set up by
running both interactive and DDRx batch simulation on a small subset of nets in the
DDRx interface. This sequence enables you to identify and fix set up problems more
quickly than if you immediately simulated the complete DDRx interface. See “Running
DDRx Simulation for the First Time” on page 820.

To hide this page when starting the wizard, clear the Always show this page when starting the
Wizard check box. You can always display this page by clicking its name in the table of
contents pane.

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Tip: See the DDRx Wizard tutorial on SupportNet for more information on creating
memory controller timing models. To access SupportNet, from HyperLynx, select Help >
Support. This opens the InfoHub — Support & Training tab. Click View How-to and
Tutorial movies on SupportNet and search for Simulating with DDRx Wizard.

Selecting Spreadsheet Rows in the DDRx Wizard

The spreadsheets use familiar mouse and key commands to select one or more rows.

All commands operate on the first (left-most) column. For example, to select one row, you click
the first column on that row.

Figure 17-28. Selecting Spreadsheet Rows in the DDRx Wizard

Tip: For differential signaling, select only the positive net within the differential pair.

To select a single row:

• Click the row.

To select a block of rows:

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• Drag over the rows.

• Click the first row and press Shift+click over the last row.
To select multiple non-adjacent rows:

• Press Ctrl+click over each row.

Related Topics
“Creating DDR3 Write-Leveling Delay Files” on page 822

“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Initialization Page

Use this page to manage DDRx setup files and to specify the type of DDRx interface.

DDRx setup files (.DDR) contain the settings needed to set up DDRx batch simulation. Once
the setup file is saved, you can import it in a future wizard session to do any of the following:

• Re-run simulation on the same design.

• Run simulation on a variation of the same design, such as with a different number of
DRAM ICs. To preserve settings for the original simulation, you should copy and
rename the setup file, and then open the renamed setup file.
• Run a simulation that someone else has set up for the same design.
Setup files are located in the <design> folder. See “About Design Folder Locations” on
page 1391.

Table 17-20. DDRx Batch Mode Wizard - Initialization Page Contents

Option Description
Setup File When you first open the wizard in a new BoardSim session, the Setup
File box is empty and you create a new DDRx setup file by
proceeding through the rest of the wizard. The wizard automatically
records data as you step through its pages. When you finish or close
the wizard, you are prompted to save the data to a setup file. The
wizard also writes to the setup file comments that provide advice and
examples. If a setup file is associated with the design, the filename
displays in this field.

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Table 17-20. DDRx Batch Mode Wizard - Initialization Page Contents (cont.)
Option Description
Edit Click to modify and existing file. This opens the file in the
HyperLynx File Editor and disables the Edit button until you close
the setup file.

Review or edit the file, and then close the HyperLynx File Editor.

Restriction: The DDRx wizard always removes manually-inserted

comments and restores “standard” comments when it saves the setup
file. Persistent manually-inserted comments may be placed in the
"Notes" section of the setup file.

For syntax information, see “HyperLynx DDRx Wizard Setup File

Format” on page 1307.
Verify Use this to validate an existing setup file.
Import Import a setup file into the wizard to display its contents in context of
the wizard pages.

This page-by-page review may help you find non-syntax errors, such
as incorrect net names or reference designator assignments.

Restriction: You can import a setup file from any location on the
computer or network, but the wizard always saves it to the <design>
folder. See “About Design Folder Locations” on page 1391.
Reset Click to clear data from the wizard and create a new setup file.

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Table 17-20. DDRx Batch Mode Wizard - Initialization Page Contents (cont.)
Option Description
This DDR interface is Use the pull-down menus to specify the DDRx interface type:

1. Select one of the following:

• DDR
• DDR2
• DDR3
• LPDDR
• LPDDR2
2. Select one of the following:
• Unbuffered
• Registered—A registered DIMM (RDIMM) contains registers
and a phase-lock-loop (PLL) to buffer the following types of
signals in the DDRx interface: Address, control, and clock. The
idea is to reduce the load of these pins on driver buffers on the
controller or another IC in the design.

Note: The DDRx Wizard supports simulation of systems with

registered DIMMs (RDIMMs) only where the register and PLL
are separate components or a single component on the
RDIMM.
DDRx Data Rate Specify the data rate, in MT/s (megatransfers per second), select one
of the following from the list:
• <standard_data_rate>, such as 800.
• <custom>, and then type the data rate in the box that appears.

Changing the data rate also changes the value on the Timing
Models page. See “DDRx Wizard - Timing Models Page” on
page 876.

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Controller Page

Use this page to specify the reference designator of the memory controller IC.

Caution
The components within an EBD are available for selection. The EBD displays as if it
were a "board" in a MultiBoard project in the "Board" drop-down list. Do not select an
EBD component as a controller, DRAM, clock buffer, or RDIMM register.

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Tip: Right-click on the Ref Des or Part Name columns in the spreadsheet to view the
connected net topologies for any device on the Controller page.

Right-click a Model cell to display the model path in a ToolTip.

Double-click the Model cell to open the model in the Visual IBIS Editor.

Figure 17-29. DDRx Batch Mode Wizard - Controller Page

Table 17-21. DDRx Batch Mode Wizard - Controller Page Contents

Option Description
Board If you have a multiple-board project loaded, select the board the
memory controller is located on.

See also: “About Board IDs” on page 752

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Table 17-21. DDRx Batch Mode Wizard - Controller Page Contents (cont.)
Option Description
Memory Controller Click the row header in the spreadsheet to select the reference
Reference Designator designator for the memory controller and click to make the
Selector Spreadsheet initial assignment or overwrite an existing assignment.

Filter By Select the type of object to filter the spreadsheet by.

Filter Type the filter string.

Tip: Use the asterisk * wildcard to match any number of characters.

Use a single asterisk * or delete all filter characters to remove
filtering. Use the question mark ? wildcard to match any one
character.
Apply Apply the filter.
Assignment Arrow Assigns the selected memory controller.

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - DRAMs Page

Use this page to specify the reference designators and locations of DRAM ICs. Use slot and
rank numbers to indicate DRAM locations within the DDRx interface, as shown by
Figure 17-30 and Figure 17-32. DDRx simulation supports the following DRAM
configurations:

• The memory controller and DRAM components are located on the same board.
• The memory controller and DIMMs are located on different boards in a multiple-board
design.

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Figure 17-30. Slot and Rank Landmarks for DDRx - Looking Down on DIMMs

If the memory controller and DRAMs are located on the same board, as opposed to a multiple-
board project where DIMMs plug into a board with the memory controller, learn which DRAM
instances work together during a memory operation in order to assign them to slots and ranks. A
rank is a group of DRAMs that are controlled by single, unique, chip select signal. The number
of chip select signals on the memory controller determines the supported number of memory
ranks. Ranks comprise of 64 (non-ECC) or 72 (ECC) bits.

DDRx batch simulation supports one DDRx interface at a time. If the design has more than one
DDRx interface, you setup and run a separate DDRx batch simulation for each interface.

Tip: To display the DDRx-related nets for a reference designator or part name, right-click
a ref des or part name in the spreadsheet.

Note
The DDRx Wizard supports the use of stacked-die DRAMs if you have EBD models that
define them and point to IBIS models. The DDRx Wizard does not support the use of
EBD models that point to other EBD models. For more information, see “Specifying
Locations for Stacked-Die DRAMs” on page 858.

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Figure 17-31. DDRx Batch Mode Wizard - DRAMs Page

Table 17-22. DDRx Batch Mode Wizard - DRAMs Page Contents

Option Description
Slots Number of slots. If the design implements stacked-die DRAM, see
the detailed procedure in “Specifying Locations for Stacked-Die
DRAMs” on page 858.

Tip: For on-board memory designs (no DIMMs), either set the
number of slots to zero and then set the total number of DRAM ranks,
or treat the on-board memory as residing within virtual slots.

Note: You can specify more slots than are actually used and leave
unused slots empty.
Ranks per Slot For stacked-die DRAMs, set the number of ranks to the number of
dies that are stacked. For example, a stacked quad-die DRAM, has 4
ranks, see “Specifying Locations for Stacked-Die DRAMs” on
page 858.

Note: It is OK to specify more ranks per slot than are actually used
and to leave unused ranks empty.
DRAM Reference Designators area

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Table 17-22. DDRx Batch Mode Wizard - DRAMs Page Contents (cont.)
Option Description
Board If a multiple-board project is loaded, select the board that contains the
DRAMs to map to a rank. See also: “About Board IDs” on page 752.

Note: When you specify the DRAM reference designators, include

that ECC DRAM in the selection.

For stacked-die DRAMs, select the EBD model that contains the
DRAMs to map to a die. Each EBD model contains information for
one set of dies. You must manually load and assign a model for each
die in each rank, see “Specifying Locations for Stacked-Die
DRAMs” on page 858.
Spreadsheet 1. Click the row header(s) in the spreadsheet to select the reference
designator for the DRAM(s) to map.

See also: “Selecting Spreadsheet Rows in the DDRx Wizard” on

page 849
2. Select the row header for the slot or rank you want to map the
reference designator to.
3. Click to perform the mapping.

To replace existing assignments with the selected row(s), press

Ctrl+ .

DRAMs displayed in the right-side boxes are removed from the

spreadsheet.
Tip: You can also select items from the left by clicking and dragging
the mouse in the "RefDes" column. Similarly, you can select a
particular rank by clicking in a cell in the "DRAMs" column on the
right.
Filter By Select the type of object to filter the spreadsheet by.
Filter Type the filter string.

Tip: Use the asterisk * wildcard to match any number of characters.

Use a single asterisk * or delete all filter characters to remove
filtering. Use the question mark ? wildcard to match any one
character.
Apply Apply the filter.
DRAM to Rank Assignments area

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Table 17-22. DDRx Batch Mode Wizard - DRAMs Page Contents (cont.)
Option Description
Slot and Rank 1. Select the row header for the slot and rank you want to map the
Name reference designator in the spreadsheet to.
2. Click to perform the mapping.
3. To replace existing assignments with the selected row(s), press
Ctrl+ .

DRAMs displayed in the right-side boxes are removed from the

spreadsheet.
Tip: You can also select items from the left by clicking and
dragging the mouse in the "RefDes" column. Similarly, you can
select a particular rank by clicking in a cell in the "DRAMs"
column on the right.
Remove Selected Click to remove the selected assignments.

Specifying Locations for Stacked-Die DRAMs

The DDRx Wizard supports the use of stacked-die DRAMs if you have EBD models that define
them and point to IBIS models. The DDRx Wizard does not support the use of EBD models that
point to other EBD models.

For designs that have stacked-die DRAMs, you will have one rank for each set of dies. If you
have four stacked dies, you have four ranks.

Figure 17-32. Slot and Rank Landmarks for DDRx - Stacked Dual-Die DRAM

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Figure 17-33. Specifying DRAM Locations for a Stacked Dual-Die DRAM

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Procedure
Table 17-23. Specifying DRAM Locations for a Stacked Dual-Die DRAM
Step in Figure 17-33 Description
Select the number of slots.

Tip: If you don’t have DIMMs, set the number of slots to 1.

Select the number of ranks per slot, for example, 2 ranks per slot for
dual-die DRAM, 4 ranks per slot for quad-die DRAM).

From the Board list, select the EBD model for the first DRAM.

From the DRAM to Rank Assignments area, click the row header to
select the Slot 1, Rank 1 row.

From the spreadsheet area, click the row header to select the Ref Des
for each DRAM in rank 1 (U0).

Note: When you specify the DRAM reference designators, include that
ECC DRAM in the selection.
Click to assign the IBIS model to the DRAM.

From the DRAM to Rank Assignments area, click the row header to
select the Slot 1, Rank 2 row.

From the spreadsheet area, select the IBIS model for the DRAM at rank
2 (U2).

Click to assign the IBIS model to the DRAM.

10 Select the next EBD model from the Board list and repeat steps 4-9.
Continue doing this until you have assigned all DRAM models.

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

“DDRx Wizard - DRAM Signals Page” on page 864

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DDRx Wizard - PLLs and Registers Page

Use this page to specify the locations and reference designators of the PLLs and registers used
by RDIMM ICs. Use slot numbers to indicate locations within the DDRx interface, as shown by
Figure 17-30 on page 855. The RDIMM contains registers for address and control signals for
buffering and a PLL (phase lock loop) for the clock signals for clock distribution.

Restrictions

• This page is available only if you select Registered from the This DDR interface is
pull-down on the DDRx Wizard - Initialization Page.
• The DDRx Wizard supports simulation of systems with registered DIMMs (RDIMMs)
only where the register and PLL are separate components or a single component on the
RDIMM.

Caution
The DDRx Wizard does not support hybrid RDIMM interfaces the do not have a PLL or
a Register.

If the memory controller and RDIMMs are located on the same board, as opposed to a multiple-
board project where RDIMMs plug into a board with the memory controller, then learn which
RDIMM instances work together during a memory operation in order to assign them to slots and
ranks. Use slot and rank numbers to indicate DRAM locations within the DDRx interface, as
shown by Figure 17-30. A rank is a group of RDIMMs that are controlled by single, unique,
chip select signal. The number of chip select signals on the memory controller determines the
supported number of memory ranks. Ranks comprise of 64 (non-ECC) or 72 (ECC) bits.

DDRx batch simulation supports one DDRx interface at a time. If the design has more than one
DDRx interface, you setup and run a separate DDRx batch simulation for each interface. For
example, if a desktop computer motherboard has four RDIMMs, that means two DDRx
interfaces exist and you setup and run two DDRx batch simulations.

Tip: To display the DDRx-related nets for a reference designator or part name, right-click
a spreadsheet row.

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Table 17-24. DDRx Batch Mode Wizard - PLLs and Registers Page Contents
Option Description
Effective PLL Clock Specify the typical interconnect delay between the output pin of the
Input to PLL component and the clock input pin for the DRAM or register
DRAM/Register component.
Clock Input Delay
Enter the typical delay value and the plus/minus tolerance value into
the fields.
PLL/Register Reference Designators area
Board If a multiple-board project is loaded, select the board that contains the
PLL or Register to map. See also: “About Board IDs” on page 752.
Spreadsheet Click the row header(s) in the spreadsheet to select the reference
designator for the PLL or register to map.
Filter By Select the type of object to filter the spreadsheet by.
Filter Type the filter string.

Tip: Use the asterisk * wildcard to match any number of characters.

Use a single asterisk * or delete all filter characters to remove
filtering. Use the question mark ? wildcard to match any one
character.
Apply Apply the filter.
RLL/Register to Slot Assignments area
PLLs See “Mapping PLL and Registers to Slots” on page 862.
Registers See “Mapping PLL and Registers to Slots” on page 862.
Remove Selected Removes assignments for selected slot.

Mapping PLL and Registers to Slots

1. In the left-side spreadsheet (PLL/Register Reference Designators area), click one or
more row headers to select PLL or register reference designators.

See also: “Selecting Spreadsheet Rows in the DDRx Wizard” on page 849
2. In the right-side spreadsheet (RLL/Register to Slot Assignments area), click the row
header to select the slot.
3. To add PLL reference designators to the right-side spreadsheet, click PLL .
4. To add register reference designators to the right-side spreadsheet, click Register
.

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To replace existing assignments with the selected row(s), press Ctrl+ .

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - IBIS Models Page

Use this page to review memory controller and DRAM model assignments.

If an IBIS model is missing or incorrect, edit the .REF or .QPL automapping file to assign IBIS
or EBD models to reference designators.

Restriction: This page is unavailable until you have assigned controller and DRAM ICs on
previous wizard pages.

Table 17-25. DDRx Batch Mode Wizard - IBIS Models Page Contents
Option Description
Assigned IBIS Models Red text indicates previously-assigned models that are now missing.
spreadsheet Fixing this problem can be as easy as closing the wizard and adding
the folder(s) containing the models to the model library file search
path. See “Set Directories Dialog Box” on page 1854.

Right-click the IBIS File cell to display the folder name in a ToolTip.

Double-click the IBIS File cell to open the model in the Visual IBIS
Editor.
Assign Component Select to assign memory controller and DRAM models. This opens a
Models file editor. Close the editor when you are finished.

See also: “Editing REF Files” on page 300

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Nets to Simulate Page

Use this page to select the types of nets in the DDRx interface to simulate and to select the type
of timing measurement voltage thresholds to use. Use the DDRx Wizard - Disable Nets Page to
disable simulation for individual nets.

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DDRx Batch-Mode Wizard Dialog Box

Table 17-26. DDRx Batch Mode Wizard - Nets to Simulate Page Contents
Option Description
Data timing (relative Select to simulate one of the following:
to strobes) • Both Read and Write Cycles
• Read Cycles Only
• Write Cycles Only
Clock-to-strobe skew --
timing
Address, Command, • 1T timing — indicates the memory controller can issue a memory
and Control timing command on the rising edge of every clock.
(relative to clocks) • 2T timing — indicates that memory commands can be issued on
the rising edge of every second clock. 2T is usually needed when
the address bus capacitance is too high, such as when most of the
slots/ranks are populated with DRAMs.
Note: These options are not available for LPDDR2 analysis.
Type of timing Select the type of timing measurement voltage threshold to use:
measurement voltage • Use all four receiver AC/DC thresholds
threshold to use • Use only the Vtt threshold
• For differential signals, the Vtt threshold is zero volts.
• For signal-ended signals, the Vtt threshold is
(VIH(ac)+VIL(ac))/2 volts.

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - DRAM Signals Page

Use this page to review or assign memory interface nets connected to each DRAM and to report
the DRAM organization. If spreadsheet errors exist, you can fix them in later wizard pages. You
can also display, in a tree view, the topology of controller nets.

The read-only spreadsheet is initially blank, unless you opened a setup file (in the wizard or File
page) containing this information. The wizard can automatically fill the spreadsheet, or override
existing assignments, if the following requirements are met:

• IBIS models have been assigned to the controller and DRAM ICs
• The design contains net circuits that permit signal-path tracing (such as topologies with
well-defined connector and passive series connectivity)
You can right-click a signal name cell to display its associated nets. When an automatically-
mapped net has an arbitrary name, such as $123, and one of its associated nets has a meaningful

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name with respect to the DDRx interface, displaying associated nets provides a way to help you
confirm the correctness of the automatic net assignment. See “Associated Nets” on page 272.

Double-right-click a signal name to view the topology of the net in a popup window.

See also: “Mapping DDRx Interface Signals to Nets in the Design” on page 800

Restriction: This page is unavailable until you have specified the reference designators for the
memory controller and at least one DRAM IC.

Table 17-27. DDRx Batch Mode Wizard - DRAM Signals Page Contents
Option Description
Perform Automatic Automatically fill the spreadsheet.
Net Mapping
Undo Automatic Net Restore the previous contents of the spreadsheet.
Mapping
View Controller Net Opens the Controller Signal Paths dialog box and displays the
Topology topology of controller nets.

Expand and collapse the tree as needed to view how a net connects to
component pins and other nets.

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Data Strobes Page

Use this page to specify data strobe nets in the memory interface, and whether they are single-
ended or differential. Running AutoNet selection on the DRAM Signals page automatically fills
the data strobe nets spreadsheet on this page.

Review the contents of the data strobe nets spreadsheet and add/remove nets as needed. The
controller nets spreadsheet contains the nets you can add to the data strobe nets spreadsheet.

You can right-click a cell in the Net Name column to display its associated nets. When an
automatically-mapped net has an arbitrary name, such as $123, and one of its associated nets
has a meaningful name with respect to the DDRx interface, displaying associated nets provides
a way to help you confirm the correctness of the automatic net assignment. See “Associated
Nets” on page 272.

Double-right-click a cell in the Net Name column to view the topology of the net in a popup
window.

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Restriction: This page is unavailable unless you have identified a memory controller IC on the
Controller page and have enabled simulation involving data timing on the Nets to Simulate
page.
Table 17-28. DDRx Batch Mode Wizard - Data Strobes Page Contents
Option Description
My data strobes are For DDR2 interfaces, specify whether data strobes are:
• Single-ended
• Differential
Controller Nets Select the rows containing the data strobe nets.

Tip: Enter a string in the Filter field and click Apply to filter the net
list.

Use the asterisk * wildcard to match any number of characters. Use a

single asterisk * or delete all filter characters to remove filtering. Use
the question mark ? wildcard to match any one character.
Add selected nets to Click to add selected data strobe nets from the Controller Nets
Strobes spreadsheet to the Data Strobe Nets spreadsheet.

Press Ctrl+ to remove all existing data strobe nets from the
right-side spreadsheet, and then add the selected data strobe nets to
the right-side spreadsheet.

Nets displayed in the right-side spreadsheet are removed from the

left-side spreadsheet, to prevent accidental re-assignments.

For differential signaling, select only the positive net within the
differential pair. See also: “Selecting Spreadsheet Rows in the DDRx
Wizard” on page 849
Data Strobe Nets List of data strobe nets.
Remove Selected Removes selected nets from Data Strobe Nets spreadsheet.

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Data Nets Page

Use this page to specify the data and data mask nets in the memory interface. Strobe nets in the
right-side spreadsheet are defined in the previous (Data Strobes) page.

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When measuring timing, DDRx batch simulation reports the delay between the strobe and
data/data mask nets. Data mask nets are only simulated for write operations and are grouped
separately from data nets.

Restriction: This page is unavailable unless you have identified a memory controller IC on the
Controller page and have identified data strobes on the Data Strobes page. This page does not
appear in the table of contents pane unless you have enabled simulation involving data timing
on the Nets to Simulate page.

Table 17-29. DDRx Batch Mode Wizard - Data Nets Page Contents
Option Description
Controller Nets Select the row(s) containing the data or data mask nets to map. For
differential signaling, select only the positive net within the
differential pair.
Tips:
• Right-click a cell in the Net Name column to display its
associated nets. When an automatically-mapped net has an
arbitrary name, such as $123, and one of its associated nets has a
meaningful name with respect to the DDRx interface, displaying
associated nets provides a way to help you confirm the
correctness of the automatic net assignment. See “Associated
Nets” on page 272.
• Double-right-click a cell in the Net Name column to view the
topology of the net in a popup window.
See also: “Selecting Spreadsheet Rows in the DDRx Wizard” on
page 849
Filter Enter a string in the Filter field and click Apply to filter the net list.

Use the asterisk * wildcard to match any number of characters. Use a

single asterisk * or delete all filter characters to remove filtering. Use
the question mark ? wildcard to match any one character.
Data Adds selected nets from the Controller Nets spreadsheet to the Data
column of the Data/Mask Nets to Strobe Assignments spreadsheet
without removing existing nets.
Data Mask Adds selected nets from the Controller Nets spreadsheet to the Data
Mask column of the Data/Mask Nets to Strobe Assignments
spreadsheet without removing existing nets.

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DDRx Batch-Mode Wizard Dialog Box

Table 17-29. DDRx Batch Mode Wizard - Data Nets Page Contents (cont.)
Option Description
Data/Mask Nets to Lists the Data and Mask nets assignments.
Strobe Assignments
spreadsheet Replace existing assignments by pressing and holding the Ctrl key
while doing any of the above mappings. For example, if you press
Ctrl+double-click, existing nets are replaced by the selected net(s).

The Data column displays nets in bus syntax from the least-
significant bit (LSB) to the most-significant bit (MSB). Examples:
DQ0..7, DQ[0:7], DQ(0:7).

Nets displayed in this spreadsheet are removed from the Controller

Nets spreadsheet, to prevent accidental re-assignments.
Remove Selected Removes assignments for selected rows in the Data/Mask Nets to
Strobe Assignments spreadsheet.

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Clock Nets Page

Use this page to specify the clock nets in the memory interface.

You can right-click a cell in the Net Name column to display its associated nets. When an
automatically-mapped net has an arbitrary name, such as $123, and one of its associated nets
has a meaningful name with respect to the DDRx interface, displaying associated nets provides
a way to help you confirm the correctness of the automatic net assignment. See “Associated
Nets” on page 272.

Double-right-click a cell in the Net Name column to view the topology of the net in a popup
window.

Restriction: This page is unavailable unless you have identified a memory controller IC on the
Controller page. This page does not appear in the table of contents pane unless you have
enabled simulation involving address/command/control timing on the Nets to Simulate page.

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DDRx Batch-Mode Wizard Dialog Box

Table 17-30. DDRx Batch Mode Wizard - Clock Nets Page Contents
Option Description
Controller Nets Select the row(s) containing the clock nets to map. For differential
signaling, select only the positive net within the differential pair.
Tips:
• Right-click a cell in the Net Name column to display its
associated nets. When an automatically-mapped net has an
arbitrary name, such as $123, and one of its associated nets has a
meaningful name with respect to the DDRx interface, displaying
associated nets provides a way to help you confirm the
correctness of the automatic net assignment. See “Associated
Nets” on page 272.
• Double-right-click a cell in the Net Name column to view the
topology of the net in a popup window.
See also: “Selecting Spreadsheet Rows in the DDRx Wizard” on
page 849
Filter Enter a string in the Filter field and click Apply to filter the net list.

Use the asterisk * wildcard to match any number of characters. Use a

single asterisk * or delete all filter characters to remove filtering. Use
the question mark ? wildcard to match any one character.
Add selected nets to Adds selected nets from the Controller Nets spreadsheet to the Clock
Clocks Nets spreadsheet without removing existing nets.

Tip: Press Ctrl+ to overwrite existing assignments.

Clock Nets Nets displayed in the Clock Nets spreadsheet are removed from the
Controller Nets spreadsheet.
Remove Selected Click to remove selected nets from the Clock Nets spreadsheet.

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Address and Command Nets Page

Use this page to specify address and command nets in the memory interface.

You can right-click a cell in the Net Name column to display its associated nets. When an
automatically-mapped net has an arbitrary name, such as $123, and one of its associated nets
has a meaningful name with respect to the DDRx interface, displaying associated nets provides
a way to help you confirm the correctness of the automatic net assignment. See “Associated
Nets” on page 272.

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DDRx Batch-Mode Wizard Dialog Box

Double-right-click a cell in the Net Name column to view the topology of the net in a popup
window.

Restriction: This page is unavailable unless you have identified a memory controller IC on the
Controller page. This page does not appear in the table of contents pane unless you have
enabled simulation involving address/command/control timing on the Nets to Simulate page.

Table 17-31. DDRx Batch Mode Wizard - Addr/Comm Nets Page Contents
Option Description
Controller Nets Select the row(s) containing the address and command nets to map.
For differential signaling, select only the positive net within the
differential pair.
Tips:
• Right-click a cell in the Net Name column to display its
associated nets. When an automatically-mapped net has an
arbitrary name, such as $123, and one of its associated nets has a
meaningful name with respect to the DDRx interface, displaying
associated nets provides a way to help you confirm the
correctness of the automatic net assignment. See “Associated
Nets” on page 272.
• Double-right-click a cell in the Net Name column to view the
topology of the net in a popup window.
See also: “Selecting Spreadsheet Rows in the DDRx Wizard” on
page 849
Filter Enter a string in the Filter field and click Apply to filter the net list.

Use the asterisk * wildcard to match any number of characters. Use a

single asterisk * or delete all filter characters to remove filtering. Use
the question mark ? wildcard to match any one character.
Add selected nets to Adds selected nets from the Controller Nets spreadsheet to the
Clocks Address and Command Nets spreadsheet without removing existing
nets.

Tip: Press Ctrl+ to overwrite existing assignments.

Address and Displays the address and command nets. Nets displayed in this
Command Nets spreadsheet are removed from the Controller Nets spreadsheet.
Remove Selected Click to remove selected nets from the Address and Command Nets
spreadsheet.

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

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DDRx Batch-Mode Wizard Dialog Box

DDRx Wizard - Control Nets Page

Use this page to specify control nets in the memory interface.

You can right-click a cell in the Net Name column to display its associated nets. When an
automatically-mapped net has an arbitrary name, such as $123, and one of its associated nets
has a meaningful name with respect to the DDRx interface, displaying associated nets provides
a way to help you confirm the correctness of the automatic net assignment. See “Associated
Nets” on page 272.

Double-right-click a cell in the Net Name column to view the topology of the net in a popup
window.

Restriction: This page is unavailable unless you have identified a memory controller IC on the
Controller page. This page does not appear in the table of contents pane unless you have
enabled simulation involving address/command/control timing on the Nets to Simulate page.

Table 17-32. DDRx Batch Mode Wizard - Control Nets Page Contents
Option Description
Controller Nets Select the row(s) containing the control nets to map. For differential
signaling, select only the positive net within the differential pair.
Tips:
• Right-click a cell in the Net Name column to display its
associated nets. When an automatically-mapped net has an
arbitrary name, such as $123, and one of its associated nets has a
meaningful name with respect to the DDRx interface, displaying
associated nets provides a way to help you confirm the
correctness of the automatic net assignment. See “Associated
Nets” on page 272.
• Double-right-click a cell in the Net Name column to view the
topology of the net in a popup window.
See also: “Selecting Spreadsheet Rows in the DDRx Wizard” on
page 849
Filter Enter a string in the Filter field and click Apply to filter the net list.

Use the asterisk * wildcard to match any number of characters. Use a

single asterisk * or delete all filter characters to remove filtering. Use
the question mark ? wildcard to match any one character.
Add selected nets to Adds selected nets from the Controller Nets spreadsheet to the
Clocks Control Nets spreadsheet without removing existing nets.

Tip: Press Ctrl+ to overwrite existing assignments.

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DDRx Batch-Mode Wizard Dialog Box

Table 17-32. DDRx Batch Mode Wizard - Control Nets Page Contents (cont.)
Option Description
Address and Displays the control nets. Nets displayed in this spreadsheet are
Command Nets removed from the Controller Nets spreadsheet.
Remove Selected Click to remove selected nets from the Control Nets spreadsheet.

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Disable Nets Page

Use this page to exclude nets from simulation. You might do this to run “what if” simulations
on specific nets with problems. Alternatively, you might run an initial screening simulation on a
subset of nets for a byte lane, before running exhaustive simulation on all nets. See “Running
DDRx Simulation for the First Time” on page 820.

Restriction: This page does not appear in the table of contents pane unless you have enabled
simulation involving data or address/command/control timing on the Nets to Simulate page.

Table 17-33. DDRx Batch Mode Wizard - Disable Nets Page Contents
Option Description
Nets to Simulate and Analyze Spreadsheet
Simulate? Selected — nets are simulated
Cleared — nets are not simulated
Net Type --
Net Name • Right-click a cell in the Net Name column to display its
associated nets. When an automatically-mapped net has an
arbitrary name, such as $123, and one of its associated nets has a
meaningful name with respect to the DDRx interface, displaying
associated nets provides a way to help you confirm the
correctness of the automatic net assignment. See “Associated
Nets” on page 272.
• Double-right-click a cell in the Net Name column to view the
topology of the net in a popup window.
Select All Enables simulation for all nets displayed in the spreadsheet. This
button is unavailable if all nets are already selected.

Tip: The Select All buttons acts only on nets displayed by the
spreadsheet.

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Table 17-33. DDRx Batch Mode Wizard - Disable Nets Page Contents (cont.)
Option Description
Unselect All Disables simulation for all nets displayed in the spreadsheet. This
button is unavailable if all nets are already deselected.

Tip: The Unselect All button acts only on nets displayed by the
spreadsheet.
Show Data and Data --
Mask Nets
Show Data Strobe --
Nets
Show Address, --
Command, and
Control Nets

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - IBIS Models Selectors Page

Use this page to specify IBIS [Model Selector] keyword values for DDRx signals that do not
use on-die termination (ODT).

Table 17-34. DDRx Batch Mode Wizard - IBIS Model Selectors Page Contents
Option Description
List Items By IBIS Component — Display all devices with the same IBIS
component in the same row. This enables you to quickly assign the
same [Model Selector] keyword value to all devices using the same
IBIS component.
Device Reference Designator — Display each device in its own row.
This enables you to assign unique [Model Selector] keyword values
to individual devices.
Non-ODT IBIS Model Click in the Model cell and select the [Model Selector] keyword
Selectors value.

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

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DDRx Batch-Mode Wizard Dialog Box

DDRx Wizard - ODT Models Page

Use this page to specify on-die termination (ODT) models for data, data strobe, and data mask
nets. DDRx batch simulation runs with one ODT model at a time, although ODT models can
change between simulations.

The spreadsheet displays “<no [Model Selector] found” when the IBIS model for the controller
or DRAM component does not contain the [Model Selector] or [Model] keyword for the pins.

Table 17-35. DDRx Batch Mode Wizard - ODT Models Page Contents
Option Description
ODT IBIS Model Select a model for all cells in a spreadsheet row. Cells are read-only
Selectors spreadsheet when the IBIS model assigns the pin to a [Model Selector] keyword
with one model or to a [Model] keyword.

Tip: To copy ODT settings from one DRAM to all the other DRAMs
of the same IBIS component type, click its row header in the
spreadsheet and click Apply These Settings to Similar DRAMs.

Related Topics
“On-Die Termination - ODT” on page 803

“Adding Model Selector Keywords to IBIS Models” on page 793

“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - ODT Behavior Page

Use this page to verify that the ODT enable/disable settings are correct for the memory
controller and DRAMs for all the possible read/write operations.

The “DRAM Configuration” label displays the number of slots and ranks in the memory
interface. The values are of form <slot_1_config_value>/<slot_2_config_value>.

where slot_#_config_value can be any of the following:

2R—DRAMs populate both ranks of the DIMM. R means “rank.”

1R—DRAMs populate one rank of the DIMM. R means “rank.”
<empty>—The slot is empty.
Example: “DRAM Configuration: 2R/2R” means that DIMMs populate both slots and that
DRAMs populate both ranks of the DIMMs.

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Tip: “Rank” represents a specific location in the memory interface. DRAM components
in the same rank function together during read and write operations. Ranks comprise of
64 (non-ECC) or 72 (ECC) bits.

The spreadsheets display ODT settings during read and write operations for the controller and
for DRAMs functioning together in each rank. The number of populated slots (from the
DRAMs page) determines the number of spreadsheet rows. Disabled/Enabled cell values map
to the IBIS models that you specified on the ODT Models page. The IBIS models and routing
impedance together determine the overall impedance for enabled/disabled ODT settings.

ODT is enabled on the basis of which slot is being written to, not which rank is being written to.
This means that separate simulations are not needed for every write operation. For example,
consider a 2R/2R system, in which DIMMs populate both slots and DRAMs populate both
ranks of each DIMM. When slot 1 is written to (either side 1 or side 2), ODT is enabled on the
front side of slot 2. This means that one simulation can be run to produce waveforms for the
receiver pins on both ranks on the DIMM in slot 1. There is no need to simulate write operations
separately for slot 1/rank 1 and slot 1/rank 2 because the ODT enable setting is the same for
both operations.

Table 17-36. DDRx Batch Mode Wizard - ODT Behavior Page Contents
Option Description
ODT for Write To override default ODT enable/disable behaviors, click the
Operations spreadsheet cell and select Enabled or Disabled. The cell displays
“Empty” when the location is unpopulated.
ODT for Read To override default ODT enable/disable behaviors, click the
Operations spreadsheet cell and select Enabled or Disabled. The cell displays
“Empty” when the location is unpopulated.
Use Defaults Restores default behavior.

Note: This button is available only when you override a default

spreadsheet value.

Related Topics
“On-Die Termination - ODT” on page 803

“Simulating DDRx Memory Interfaces” on page 773

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DDRx Batch-Mode Wizard Dialog Box

DDRx Wizard - Timing Models Page

Use this page to specify the memory interface data rate and the device speed grade and timing
models for the memory controller and DRAM devices. You can also use this page to display,
edit.

Timing models contain the maximum or minimum setup and hold times for each type of
receiver pin (such as data and address) relative to the associated strobe/clock, maximum skew
between certain pin pairs, signal launch delay of one pin relative to another, and so on.

Timing models are located in the Libs folder. For example,

C:\MentorGraphics\<release>\SDD_HOME\hyperlynx\Libs. If you need to create a new timing
model, you can copy and edit one of the timing models (.v) that ship with HyperLynx. If you
provide your own timing models, they must define the same parameters used by the shipping
timing models.

Requirement: All DRAMs must have the same timing requirements and use the same timing
model.

Figure 17-34. Default and User-Defined Speed Grade Assignments

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Table 17-37. DDRx Batch Mode Wizard - Timing Models Page Contents
Option Description
DDRx Data Rate Specifies the data rate for the DDRx interface. Select one of the
(MT/s) following from the list:
• <standard_data_rate>, such as 800, in MT/s (megatransfers per
second).
• <custom>, and then type the data rate in the box that appears.

See also: “Mapping Custom Data Rates to Standard JEDEC

Derating Tables” on page 879

Note: If you change the data rate using this option, all devices
using the default speed grade (indicated in the spreadsheet by
angle brackets < >) automatically change to the new data rate.
Similarly, if you change the DDRx interface type (for example,
DDR2 and DDR3) on the Initialization page, all devices using the
default timing model automatically change to the default timing
model for the new interface type.

Changing the data rate also changes the value on the Controller
page. See “DDRx Wizard - Controller Page” on page 852.

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Table 17-37. DDRx Batch Mode Wizard - Timing Models Page Contents (cont.)
Option Description
Timing Models The Timing Models spreadsheet uses angle brackets < > to identify
Spreadsheet default speed grade and timing model assignments.
• Speed — To specify a non-default speed grade for an individual
device, click the Speed cell and select the speed in MT/s
(megatransfers per second). You normally specify a speed grade
that is greater than or equal to the data rate.

To restore the default speed grade, click the Speed cell and select
the item enclosed by angle brackets < >.

• Model File — To specify a non-default timing model for an

individual device, click the Model File cell and do one of the
following:
• To specify a new model, click <Browse>, select the timing
model file (.v), and click Open.
• To specify a model you previously assigned to another device,
click its name.

To restore the default timing model, click Model File cell and
select the item enclosed by angle brackets < >.

Right-click the Model File cell to display the folder name in a

ToolTip.

Examples:
In Figure 17-34 on page 876, the top and middle Speed cells display
the default speed grade, based on the value from the DDR2 Data Rate
list. The bottom Speed cell displays a user-defined speed grade that
was selected from the list that appears when you click the cell.

In Figure 17-34 on page 876, the top and middle Model File cells
display the default timing models, based on the interface type you
selected on the Initialization page. The bottom Model File cell
displays a custom timing model.
Apply Settings to Copies the data rate and timing model values from one DRAM to all
Similar DRAMs the other DRAMs, click its row header in the spreadsheet and click
Apply Settings to Similar DRAMs.

Tip: DRAMs in a design typically use the same settings. After you
set up one DRAM, you can apply its settings to all the DRAMs.

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DDRx Batch-Mode Wizard Dialog Box

Table 17-37. DDRx Batch Mode Wizard - Timing Models Page Contents (cont.)
Option Description
View Graphically displays the selected timing model in the Timing Model
dialog box. You can also double-click the row header or any read-
only cell in the row to display the timing model.

Some parameters exist in the DRAM timing model or in the

controller timing model, but not in both timing models. Some
parameters exist in both DRAM and controller timing models, which
are likely to specify different values for the same parameter
(depending on whether the measurement is performed on a read or
write cycle).
Edit Click to edit the selected timing model with the HyperLynx Timing
Model Editor.

See “Creating Controller and DRAM Timing Models” on page 786.

Verify Verifies the timing model syntax and loads parameter values into the
wizard for the selected device.

Note: The spreadsheet displays the timing model names in red text if
you have not verified the specific combination of data rate, speed
grade, and timing model file values.
Verify All Verifies the timing model syntax and loads parameter values into the
wizard for all devices.
TM Wizard Click to open the Timing Model Wizard. This wizard assists you in
creating a simple timing model for a DDRx memory controller.

Mapping Custom Data Rates to Standard JEDEC Derating Tables

For DDR2 and DDR3 designs, the data rate value on this wizard page determines which built-in
derating table to use. If you specify a standard data rate, the matching derating table is used
from JEDEC specification JESD79*. If you specify a custom data rate, see the sections below to
see how it maps to the standard JEDEC derating tables.

DDR2 - Mapping Custom Data Rates to Standard Derating Tables

Clock nets and related nets; differential strobe nets and related nets:

• < 400 MHz, > 400 MHz to < 533 MHz—400/533 MHz table
• > 533 MHz—667/800/1066 MHz table
Single-ended strobe nets and related nets:

• < 400 MHz—400 MHz table

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• > 400 MHz to < 533 MHz—533 MHz table

• > 533 MHz—667 MHz table

DDR3 - Mapping Custom Data Rates to Standard Derating Tables

Clock nets and related nets:

• Any custom frequency—800/1066/1333/1600 MHz table

Differential strobe nets and related nets:

• Any custom frequency—800/1066 MHz table

Related Topics
“Creating Controller and DRAM Timing Models” on page 786

“HyperLynx Timing Model Format” on page 1270

“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Write Leveling Page

Use this page to specify write-leveling delays for each DDR3 byte lane. You can import the
write-leveling delay file created by a previous DDRx batch simulation run or you can type the
delay values into the spreadsheet.

To have DDRx batch simulation automatically create the write-leveling delay values, see
“Creating DDR3 Write-Leveling Delay Files” on page 822.

Restrictions: This page is available only if you enable both of the following:

• The DDR3 interface in the DDRx Wizard - Initialization Page

• Enable "Clock-to-strobe skew" simulations on the DDRx Wizard - Nets to Simulate
Page

Table 17-38. DDRx Batch Mode Wizard - Write Leveling Page Contents
Option Description
Import Delays Import delays from an existing write-leveling delay file. Click
Import Delays and open the write-leveling delay file created by a
previous DDRx batch simulation.

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Table 17-38. DDRx Batch Mode Wizard - Write Leveling Page Contents (cont.)
Option Description
Use DDR3 Delays Select to do either of the following:
file, if available • When running DDRx simulation for the first time, create an initial
write-leveling delay file. See “Creating DDR3 Write-Leveling
Delay Files” on page 822.
• Use the contents of an existing write-leveling delay file.
Data Strobes and Type write-leveling delay values, in picoseconds, into the
Write Leveling Delays spreadsheet.
(pSec) Spreadsheet
The spreadsheet accepts write-leveling delays for strobe signals, but
not for data and data mask signals. Write-leveling delays are only
useful when performing write cycle clock-to-strobe skew and
setup/hold measurements. Write cycle data and data mask setup/hold
measurements are made relative to the strobe and not the clock, so the
write-leveling delays are not relevant for those timing analyses.

Related Topics
“Write Leveling for DDR3” on page 817

“DDR3 Write-Leveling Delay Files” on page 845

“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Stimulus and Crosstalk Page

Use this page to specify stimulus and crosstalk options.

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DDRx Batch-Mode Wizard Dialog Box

Table 17-39. DDRx Batch Mode Wizard - Stimulus and Crosstalk Page
Contents
Option Description
Non-strobe/clock nets Choose the type of stimulus to use:
use... • PRBS stimulus — PRBS stimulus is commonly used, specify the
bit order. specify the bit order.
PRBS stands for pseudorandom binary sequence. Bit order
specifies the number of bits in the sequence. The number of bits is
2**<bit_order> - 1.
Large bit order numbers can produce very long simulation run
times, but can also produce statistically more meaningful
simulation results, especially with regard to exploring the effects
of inter-symbol interference (ISI).

• Custom stimulus — Provide custom stimulus that produces

worst-case results. One way to automatically create worst-case
stimulus is to run the FastEye-Diagram Wizard and save the
worst-case stimulus to a file. See “FastEye Channel Analyzer -
View Analysis Results Page” on page 1628.

For information creating custom stimulus files (.EDS), see

“Setting Up Per-Net and Per-Pin Stimulus” on page 541. These
files are located in the <design> folder. See “About Design Folder
Locations” on page 1391.

Simulation automatically applies toggling stimulus to clock and

strobe nets, using half the data rate you specified on the Controller
and Data Rate page. For example, if the data rate is 800 MT/s
(megatransfers per second), the period of the toggling stimulus is 2.5
ns (800 MT/s / 2 = 400 Mbps, assume Mbps = MHz, 1/400 MHz =
2.5 ns).

Stimulus delays are derived from signal relationships defined in the

timing model.
Include crosstalk Select to include the effects of crosstalk among various signals in the
effects in simulations memory interface.

Aggressor nets for signals that are not in the memory interface are
simulated and driven with a PRBS stimulus, using the same bit order
you specify for non-strobe and non-clock nets.

Caution: Simulating crosstalk can substantially increase simulation

times.

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Table 17-39. DDRx Batch Mode Wizard - Stimulus and Crosstalk Page
Contents (cont.)
Option Description
Set Crosstalk Opens the Set Crosstalk Thresholds dialog box.
Thresholds
See also: How to Set the Crosstalk Threshold

Related Topics
“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Simulation Options Page

Use this page to specify various simulation options.

Requirement: The BoardSim Lossy Lines and Via Models licenses are required to run lossy
and advanced via simulation.

Table 17-40. DDRx Batch Mode Wizard - Simulation Options Page Contents
Option Description
Select IC model Select one or more of the following IC model corner conditions:
corners • Fast-strong
• Typical
• Slow-weak
When simulating, vary Selected — Applies the IC voltage to passive termination
voltage reference components.
values with IC
corners.
Simulate loss Selected — Simulate conductor and dielectric loss, including skin
effect.
Include via L and C Selected — Include via inductance and capacitance. This setting is
independent of the settings made by clicking Setup menu > Via
Simulation Method.
Maximum To specify your own overshoot/undershoot voltage thresholds, clear
overshoot/undershoot the Use JEDEC Default Value check box and type a value into the
Maximum Overshoot/Undershoot box.
Use JEDEC Default --
Value

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DDRx Batch-Mode Wizard Dialog Box

Table 17-40. DDRx Batch Mode Wizard - Simulation Options Page Contents
Option Description
Maximum run-time The maximum number of minutes to simulate a specific net.
per net
Long simulation run times for a net can result when many nets couple
to it, possibly because of low crosstalk thresholds or many nets routed
nearby.
Initial transitions to To not perform measurements at the beginning of the simulation,
ignore when the circuit may still be stabilizing, type or select the number of
transitions to ignore.

Related Topics
“What IC Operating Settings Mean” on page 552

“About Lossy Transmission-Line Modeling” on page 1388

“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Report Options Page

Use this page to specify IC model audit options, report display options, and simulation
waveform storage options.

Table 17-41. DDRx Batch Mode Wizard - Report Options Page Contents
Option Description
For simulation, run DDRx memory interface simulations can run for hours when you
enable many nets for simulation. To use your time efficiently, batch
simulation can report common set up problems prior to running
simulations. Examples of set up problems that can prevent running
detailed simulations include missing IC models and IC model syntax
errors.

Select the type of simulation to run:

• batch simulation only (no audit)
• audit only (no batch simulation)
• both audit and batch simulation—If audit errors occur, batch
simulation is not started.
If opening *.XLS, Selected — Display errors with red text.
auto-format and
show errors in red

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Table 17-41. DDRx Batch Mode Wizard - Report Options Page Contents
Option Description
Save all DDRx Selected:
simulation • Clear Save all simulated points in waveforms to save about one
waveforms to disk in ten simulation waveform data points.
• Select Save all simulated points in waveforms to save all
simulation waveform data points. Enabling this option can
produce very large CSV files.
Saving simulation waveforms to CSV files enables you to investigate
results by displaying the waveform files in the oscilloscope.

Related Topics
“DDRx Batch Simulation Results” on page 824

“Data Flow for DDRx Batch Simulation” on page 799

“Loading Waveform Files” on page 598

“Simulating DDRx Memory Interfaces” on page 773

DDRx Wizard - Simulate Page

Use this page to exit the wizard and open the DDRx Batch Mode - Run Simulation and Show
Results dialog box, which you use to launch simulation.

When you reach this page, you should have specified all the information needed to write a
complete setup file.

By exiting the wizard and saving any changes, you write the setup file to disk.

Table 17-42. DDRx Batch Mode Wizard - Simulate Page Contents

Option Description
Setup Issues That May Use the Setup Issues That May Affect Batch Simulations area to
Affect Batch view any issues that exist with your setup.
Simulations area
Save Log Saves the contents of the Setup Issues That May Affect Batch
Simulations area to a file.
Run Batch Simulation Exit the wizard and open the DDRx Batch Mode - Run Simulation
dialog box
Save Setup Data Exit the wizard and not run simulation.

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Related Topics
“DDRx Batch Mode - Run Simulation Dialog Box” on page 886

“Simulating DDRx Memory Interfaces” on page 773

DDRx Batch Mode - Run Simulation Dialog Box

To access: Click Run Batch Simulation on the DDRx Wizard - Simulate Page.

Use this dialog box to load a DDRx setup file and launch simulation.

Table 17-43. DDRx Batch Mode - Run Simulation Dialog Box Contents
Option Description
Setup The path to the DDRx setup file.
Browse Click to load a DDRx setup file.
Run Starts the simulations.
Cancel Stops the simulation. The current simulation runs to completion
before simulation stops. Also, completed simulation results are
written.

Related Topics
“DDRx Batch Simulation Results” on page 824

“Simulating DDRx Memory Interfaces” on page 773

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EMC Simulation Limitations and Special Conditions

Chapter 18
Simulating EMC with the Spectrum Analyzer

Use the Spectrum Analyzer to run interactive electromagnetic compatibility (EMC) simulation
on the selected net.

This topic contains the following:

• “EMC Simulation Limitations and Special Conditions” on page 887

• “About LineSim EMC and BoardSim EMC” on page 890
• “Preparing the Board or Schematic for EMC Simulation” on page 900
• “Setting Up the Spectrum Analyzer” on page 901
• “Running EMC Simulations” on page 914
• “Examining EMC Simulation Results” on page 916
• “Documenting EMC Simulation Results” on page 919

Related Topics
“Showing Voltage and Current Waveforms” on page 559

EMC Simulation Limitations and Special

Conditions
Before running EMC simulation, you should determine whether any of the following limitations
or special conditions apply to your work:

• EMC simulation does not support differential pairs.

• EMC simulation supports one enabled driver on the selected net.
• EMC simulation using the antenna probe is not available for MultiBoard projects
because the MultiBoard project does not contain information about the relative positions
of the individual boards. However, you can use the current probe to run EMC simulation
for MultiBoard projects.
• The EMC simulator cannot simulate nets with SPICE models.
This topic contains the following:

• “About Radiation Prediction in LineSim EMC” on page 888

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• “EMC Simulation with Serpentined Traces” on page 889

• “Changing the EMC-Algorithm Short-Segment Threshold” on page 889

About Radiation Prediction in LineSim EMC

This section discusses the types of schematic components do and do not provide sufficient
physical information to predict radiation.

Which Transmission-Line Types Radiate

In LineSim EMC, radiation can be predicted for only those transmission-line types for which
exact-enough physical information exists.

Specifically, radiation is predicted for:

• Stackup-based transmission lines

• Microstrips
• Buried microstrips
• Striplines
Radiation is not predicted for:

• "Simple" electrical transmission lines

• Cables (e.g., ribbon cable)
• Connectors
• Wires over ground
If you construct a schematic that contains only elements from the "not predicted for" list, and
simulate it, you will see no radiation in the spectrum analyzer's output.

How to Simulate Lines Types That Do Not Radiate

For transmission-lines types for which LineSim EMC doesn’t predict radiation (due to lack of
physical information), you can still perform meaningful simulations: use the current probe
rather than the antenna. The current probe shows you the frequency content of the current in
your schematic (at whatever component pin you attach it); that current in turn, is what generates
radiation.

Using the current probe, you can reduce your design’s radiation by making changes that reduce
the current shown by the probe, or that re-distribute in a more-optimal way the frequencies at
which the current has energy.

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Additional LineSim EMC Caveats

LineSim EMC has two other important limitations:

• LineSim EMC cannot predict IC-package radiation

• LineSim EMC places all transmission-line segments physically at the origin, with the
same angular orientation
Neither of these limitations exist in BoardSim EMC, where detailed package footprints and
routing information exist.

See also: “Limitations to EMC Simulations” on page 894

EMC Simulation with Serpentined Traces

Some PCB autorouters have a feature that artificially increases the length of a net if the user
provides a "minimum length" or "minimum delay" constraint. (This is often done in an attempt
to reduce clock skew, by equalizing the lengths of two or more nets.) The increase is
implemented by "serpentining or tromboning" the trace through a series of tight, repeated turns
that significantly increases the length of the net compared to a straight route.

When BoardSim EMC simulates the radiation from a trace, it calculates the radiation from each
individual metal segment on the trace. However, in an effort to improve simulation speed, trace
segments shorter than a certain threshold length are omitted from the calculations (since their
contributions to the overall radiation levels should be low).

Requirement: The BoardSim EMC license is required to run EMC simulation.

But if a trace is composed of nothing but short segments, the omission of short segments will
cause the predicted radiation levels to be too low. To work around this, the short-segment
threshold is available as a user-definable parameter. If you have nets (like the "serpentine" cases
discussed above) that are composed mostly of short segments, decrease the threshold so that
most or all of the segments on your nets are included in analysis.

Changing the EMC-Algorithm Short-Segment Threshold

You should only change this parameter if you truly need to; otherwise you're simply wasting
simulation time. Also, if you reduce the threshold for a particular board or group of traces, you
should set it back to the default value (100 mils) afterward so that you don't waste simulation
time in the future.

To change the EMC-algorithm short-segment threshold:

1. Setup menu > Options > General > Advanced tab.

2. Click Yes when prompted.

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About LineSim EMC and BoardSim EMC

3. In the BoardSim area, in the For EMC Ignore Traces Shorter Than box, type the new
length threshold value in mils.

About LineSim EMC and BoardSim EMC

The EMC Analysis option to BoardSim and LineSim adds to either program a spectrum
analyzer. The spectrum analyzer predicts (one net at a time) the radiated emissions from your
board's or schematic's nets and presents results in the frequency domain (as compared to
LineSim's/BoardSim's oscilloscope, which displays in the time domain). You can compare the
predicted radiation levels at every frequency to government limits (U.S. FCC, European CISPR,
or Japanese VCCI) and decide if design changes are required.

When you add the EMC Analysis option to LineSim, the result is called "LineSim EMC."
Similarly, adding to BoardSim results in "BoardSim EMC." The EMC versions of the programs
retain all of the signal-integrity features of the basic programs, and add additional EMC-related
features.

This topic contains the following:

• “A Better Approach to EMC Problems” on page 890

• “Radiated Emissions and Signal Integrity” on page 891

A Better Approach to EMC Problems

Traditionally, EMC problems have been found only near the end of the design cycle, after a
prototype is built and can be taken to an EMC laboratory for measurements. The drawback to
this approach is obvious: if problems are found, it's so late in the design cycle that fixes are very
expensive. Clearly, if EMC problems could be identified and fixed before layout, significant
savings would result. Finding problems early also avoids another aspect of the traditional
approach to EMC: "band-aiding" a product by adding shielding and other expensive "kludges"
rather than solving radiation problems at their source.

With BoardSim EMC and LineSim EMC, you can:

• Find out before you build a board whether EMC problems are likely to exist
• Reduce costly revisions by fixing problems before building prototype boards
• Avoid failing an emissions test, at the last minute, after the product is built
• Determine how to fix potential EMC problems, with methods like termination and
stackup changes
• If a failure does occur, quickly isolate the signals responsible for the measured radiation
peaks
• Learn more about radiated emissions—how it is caused and how you can prevent it

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Radiated Emissions and Signal Integrity

In addition to focusing purely on EMC effects, LineSim EMC/BoardSim EMC also
demonstrates the important link between signal-integrity problems and radiated emissions.
Differential-mode radiation from a PCB is caused by current flow in the unintended antennas
formed by a board’s traces. Traces that suffer from signal-integrity problems (e.g., ringing or
long settling times) harbor excess currents and therefore generate excess radiation. Correcting
these integrity problems can reduce a trace’s radiated emissions at critical frequencies by as
much as 20 dB.

Yet determining whether a proposed change on a board increases or decreases the radiation at a
particular frequency is difficult without frequency-domain tools like LineSim EMC and
BoardSim EMC. For example, if you change a net's driver IC from one technology to another
with a similar switching speed, will the net's radiation increase or decrease? If you want to
terminate a net in order to decrease its radiation, should you use an end-of-line method or a
series terminator? Determining the effects of such changes from a signal-integrity standpoint (in
the time domain) is one matter; determining the effects from an EMC viewpoint (in the
frequency domain, and for radiation) is another.

This topic contains the following:

• “Brief EMC Technical Background” on page 891

• “Limitations to EMC Simulations” on page 894
• “Brief Description of EMC Algorithms” on page 897
• “Outline of HyperLynx Trace-Radiation Algorithm” on page 897
• “Assumptions of Core Radiation Algorithm” on page 898
• “Outline of HyperLynx Package-Radiation Algorithm” on page 899
• “Assumptions of Package Radiation Algorithm” on page 899
• “How Maximum Radiation is Found” on page 900

Related Topics
“Simulating EMC with the Spectrum Analyzer” on page 887

Brief EMC Technical Background

This topic describes what kinds of radiation effects LineSim EMC/BoardSim EMC simulates,
and gives some brief technical background about the subject of EMC and radiated emissions.

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Why Radiation Occurs

The traces on a PCB form unintended antennas that can generate electromagnetic radiation and
cause EMC problems. Radiation is generated when currents flow in the trace antennas; the more
and longer the current flows, the greater the risk of excess radiation being produced. There are
basically two ways to reduce the radiation generated by a net: diminish the effectiveness of the
antenna that the trace forms, or reduce the current that flows in the antenna.

Differential-mode Versus Common-mode Radiation

Differential-mode radiation is generated when a current and an equal-but-opposite current flow
in close proximity to each other. On PCBs with ground/power planes, the current in a trace has
exactly this configuration: as the current flows down the trace, an "image" current immediately
above or below the trace returns to the driving source.

Even though the oppositely directed currents tend to cancel each other's radiation, the
cancellation is not perfect because of the non-zero spatial and temporal (time) separation
between them. The residual, differential-mode radiation is what LineSim EMC/BoardSim EMC
predicts.

Common-mode radiation is generated when a current flows without a nearby current to oppose
it. Under these circumstances, the radiation generated can be much larger than typical
differential-mode radiation. In real digital systems, common-mode currents tend to result from
system-level conditions, for example, poorly designed cables (without adequate ground returns)
or compromised/missing ground planes (One classic way of "compromising" a ground plane is
to cut it and allow signals to pass over the cut.) Double-sided PCBs (boards with no ground
planes) produce inherently non-differential radiation, because no pathways are provided for
tight differential-mode return currents.

LineSim EMC/BoardSim EMC predicts differential-mode radiation.

Far-Field Versus Near-Field Radiation

The radiation generated by a PCB trace is complex. Near the trace, for example, the electric
field includes a radial (outward-directed) component; further away, the E-field's radial
component diminishes. EMC labs typically take measurements designed to measure far-field
radiation: the sensing antenna is located 3, 10, or 30 meters away from the PCB under test, so
that (except for at the lowest frequencies), only far-field radiation is sampled.

LineSim EMC/BoardSim EMC predicts far-field radiation.

Radiation from Periodic Versus Random Signals

The data content of a digital signal greatly affects the way in which it radiates. Periodic signals
(like clocks or regularly repeating control signals like RAS or CAS) have their energy
"bunched" into tight peaks with large amplitudes. Random signals (like a data line) have their

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energy spread broadly and tend to have no peaks. Therefore, except in unusual cases, it is the
periodic signals on a PCB that cause radiated-emissions failures.

LineSim EMC/BoardSim EMC is designed to show the frequency content of periodic signals.
Before you run a simulation, you specify the frequency and duty cycle of the driving ICs'
waveforms.

See also: “Choosing the Driver Waveform for EMC” on page 902

Radiation from Component Packages

The radiation generated by a PCB comes not only from the board's traces, but also from the ICs
and other components on the board. In fact, on many modern boards, the IC packages (i.e., the
IC die and the package’s lead frame, bond wires, and pins) produce more radiation than the
signal traces. This occurs because as currents leave and enter the IC packages, the package’s
and die’s structures also act as antennas, and often as antennas that have less-favorable
differential-mode behavior than do board traces.

One of the major strengths of BoardSim EMC is that it is able to predict radiation from not only
PCB traces, but also component packages. And it does so without requiring the user to input any
modeling information about the components' packages.

Requirement: The BoardSim EMC license is required to run EMC simulation.

Note
LineSim EMC cannot predict package radiation because, unlike BoardSim EMC, it does
not have any information about the physical packages of the ICs it is simulating.

Effect of System Components and Enclosures

In practice, PCBs are almost always packaged in some manner before being deployed for real
use. A computer motherboard, for example, may be tested for radiated emissions as a bare
board, but in real use will reside in a case (i.e., an enclosure). (It will also be surrounded by
additional electronics, e.g., a power supply and perhaps several plug-in cards.) Additional
system components like a package or enclosure may have a significant effect on the radiation
actually observed outside the unit.

LineSim EMC/BoardSim EMC predicts only the radiation produced by a single PCB. It does
not attempt to predict what happens when multiple boards are interconnected, or when a board
is enclosed in a case.

Governmental EMC Regulations

Ultimately, the reason designers are forced to be concerned about EMC and radiated emissions
is that governmental bodies throughout the world require that electronic products not generate
excessive amounts of radiation. EMC standards vary from country to country. The most

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important sets of regulations are FCC (applicable in the United States), CISPR (throughout
Europe Community), and VCCI (Japan). Other, similar regulations apply in other markets. If a
product generates radiation in excess of one of these standards, it may not be allowed for sale in
the target market.

Within each standard, distinctions are made between two classes of products: "Class A" for
industrial products, and "Class B" for commercial (or consumer) products. The standards are
more-stringent for commercial products.

Limitations to EMC Simulations

LineSim EMC/BoardSim EMC's radiation-prediction algorithms are designed to offer a careful
balance between accuracy, performance, and affordability. The following sections provide some
useful information about the what HyperLynx's EMC algorithms can—and can't—do.

Planes are Assumed to be Whole

LineSim EMC/BoardSim EMC's radiation-prediction algorithms assume that a board being
analyzed has at least one properly functioning ground plane. Specifically, this means that:

• The board must have at least one ground plane

• The plane must not be seriously compromised, e.g., must not be cut without regard for
digital signals that pass over the cut
Strictly speaking, LineSim EMC/BoardSim EMC does not require that a ground plane not be
cut or split. But the program does assume that for any signal being analyzed, there is a tight
return path for the signal's current in a nearby plane layer. This means that if you have a PCB
with a split ground plane and attempt to analyze signals that pass over the ground-plane gap,
LineSim EMC/BoardSim EMC will give erroneously optimistic results. On the other hand, if
you analyze only nets that remain above or below their section of the ground plane, the analyses
will be valid.

It is ironic that PCB-layout tools are finally making it fairly easy to split plane layers, at exactly
the time in the history of PCB development when—thanks to increasing IC switching times and
frequencies—it is becoming critical not to compromise plane layers. Cutting gaps in a plane
layer forces return currents flowing in the layer to deviate wildly from the paths they would
otherwise take. These deviant return-current paths, in turn, severely increase the loop area of the
differential-mode antennas on the board, causing big jumps in radiation levels. You should
avoid compromising your boards' plane layers at nearly all costs—unless EMC and signal
integrity are not important to you.

Only Differential-Mode and Component-Package Radiation is Predicted

There are numerous means by which a PCB can radiate. LineSim EMC/BoardSim EMC
predicts the two most unavoidable types of board radiation: the differential-mode radiation that
comes from signal traces traveling over ground and power planes, and the radiation that is

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generated by component packages. However, there are plenty of other mechanisms by which a
PCB can radiate, and if your board allows these other means, LineSim EMC/BoardSim EMC
will predict lower radiation levels than the PCB will actually generate.

For example, LineSim EMC/BoardSim EMC does not attempt to predict common-mode
radiation. See “Brief EMC Technical Background” on page 891 for an explanation of the
difference between differential- and common-mode radiation. If you add a poorly designed
cable to your board, for example, it may radiate very strongly, more so than the entire PCB.
Common-mode problems can also result from improperly designed systems which have
unopposed currents flowing through their ground structures.

However, well-designed boards and systems tend to be dominated by differential-mode trace

radiation, and the radiation that comes from component packages. LineSim EMC/BoardSim
EMC accurately predicts these effects.

BoardSim EMC Does Not Predict Radiation for Crosstalk Aggressor Nets
BoardSim EMC predicts radiation only for those nets that are "associated," i.e., electrically
connected to, the selected net. If you own BoardSim’s Crosstalk option, and are running
simulations with crosstalk enabled, any aggressor nets in the simulation (nets coupled to the
selected net) are NOT included in the radiation analysis.

Table 18-1 gives more detail.

Table 18-1. EMC - Types of Nets Includes in Radiation Prediction

Type of net in BoardSim EMC Included in radiation prediction?
selected net yes
nets associated through a resistor, capacitor, or any yes
other passive component
differentially associated nets, i.e., nets associated yes
through a differential IC model
aggressor nets, i.e., coupled nets included in no
crosstalk analysis that are NOT connected to the
selected net by a passive component or differential
IC

About Accuracy
It is mathematically more difficult to predict radiated-emissions levels than to predict signal-
integrity effects. Therefore, EMC analysis tends to be somewhat less precise than signal-
integrity simulation. However, HyperLynx has carefully implemented its radiation-prediction
algorithms so that they give results as close as practically possible to actual lab measurements
(and better than some other commercially available programs that are much more expensive).

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HyperLynx's evaluations show that LineSim EMC/BoardSim EMC is accurate to within 5-10
dBuV/m. More importantly, you can always rely on LineSim EMC/BoardSim EMC to
accurately tell you whether a net will be a source of EMC trouble, and whether proposed fixes
(like termination or a different driver IC) will improve or worsen results.

See also: “Brief EMC Technical Background” on page 891

The best EMC labs are not able to measure radiated emissions to better than +-3 dBuV/m
accuracy.

Special Limitations in LineSim EMC

LineSim EMC differs significantly from BoardSim EMC in that it does not have access to all
the physical information that BoardSim EMC does. For example, whereas in BoardSim EMC
the exact physical positioning of trace segments is known, in LineSim EMC, the schematic does
not contain this information. Also, in BoardSim EMC, the physical footprint of a component's
package is known; it is not in LineSim EMC. Accordingly, several limitations to radiated-
emissions prediction exist in LineSim EMC:

• LineSim EMC cannot predict component-package radiation; you cannot enable package
radiation in the user interface
• LineSim EMC places all transmission lines at the origin, with the same angular
orientation; the effect of differently oriented segments cannot be analyzed
• When you simulate differential traces in LineSim EMC (i.e., a differential pair), because
LineSim does not have physical information about the separation between the traces, the
traces are assumed NOT to be separated. This results in better field cancellation than the
traces will actually exhibit; hence, LineSim EMC's differential-pair simulations are
"optimistic."
Regarding placement of all transmission lines at the origin, more specifically, the left end of all
lines in the schematic are placed at location 0,0, and the right ends extend rightward from 0,0.
This means that you can get different radiation results depending on how you draw a schematic:
two transmission lines stretched horizontally in one row will radiate differently than the same
two lines laid out in a "U turn" fashion in two rows but only one column. This occurs because
the left end of the second trace is at the junction of the lines in the first case, but at the far end of
the trace run in the second. When these left ends are placed at location 0,0, the radiation results
will differ.

Note
If you find the preceding caveat confusing, you may want to limit your LineSim EMC
simulations to single-trace cases.

When you simulate differential traces in LineSim EMC (i.e., a differential pair), because
LineSim does not have physical information about the separation between the traces, the traces
are assumed NOT to be separated. This results in better field cancellation than the traces will

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actually exhibit; hence, LineSim EMC's differential-pair simulations are "optimistic." This
restriction applies in the current version of the program even if the transmission lines in
the trace pair are coupled and have their separation specified in a coupling region.

Brief Description of EMC Algorithms

This topic briefly describes the algorithms used by HyperLynx to predict differential-mode
radiation.

Types of Radiation-Prediction Algorithms

HyperLynx predicts differential-mode radiation using a 3-D radiation prediction algorithm
developed by experts in computational electromagnetics at the University of Washington. This
algorithm provides a good balance between techniques that are excessively intense
computationally (resulting in poor simulation speed) and methods that are purely quantitative
(e.g., exclusively rules-based, and therefore very approximate).

More specifically, the following techniques have been used in various EDA tools to predict
differential-mode radiation. The methods are listed in order from least to most quantitative:

Rules-based—No calculation; provides a rough estimate based on driver slew rate, trace length,
board cross section; fast, but simplistic

First-order calculated—Simple calculation; assumes driver is a linear ramp when calculating

frequency-domain characteristics; does not use real currents and may miss the effect of
terminators

HyperLynx method—Detailed calculation; uses full non-linear driver model and accounts for
terminations; analyzes currents found from time-domain signal-integrity simulation

"Full wave" or "method of moments"—Intense calculation; solves for current densities at the
same time as predicting radiation; may run slowly and may exceed the limits/tolerances of the
problem being modeled.

Related Topics
“Outline of HyperLynx Package-Radiation Algorithm” on page 899

Outline of HyperLynx Trace-Radiation Algorithm

HyperLynx’s "detailed calculation" algorithm is incorporated in its EMC simulations of PCB
traces as follows:

"Flow" of the HyperLynx trace-radiation algorithm:

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1. User chooses trace to analyze. Software "pulls in" chosen net plus any non-power-
supply nets connected by components (resistors, capacitors, differential driver ICs,
ferrite beads).
2. User specifies EMC-measurement-antenna characteristics: distance; automatic scanning
for maximum radiation versus manual positioning; sensitive to package radiation or not.
3. User specifies trace’s repetition frequency and duty cycle; also chooses IC models;
clicks "Start" button. Time-domain (signal-integrity) analysis runs. Software
automatically runs for as many cycles as needed for a valid conversion to frequency
domain.
4. Time-domain data are tightly filtered in preparation for conversion to frequency domain
(anti-aliasing).
5. Fast Fourier Transform (FFT) is run on time-domain data, so that currents’ components
are known at every frequency of interest.
6. Path-delay algorithm runs to determine time delay between driver IC(s) and each metal
segment comprising the net(s) being simulated.
7. For each metal segment on the net(s) and for each frequency at which any significant
energy exists, and accounting for the segment’s delay from driver IC(s), electric-field-
intensity vector is calculated ("E," measured in units of volts/meter) for specified
antenna characteristics.
8. Repeat step 7 for each metal segment on trace.
9. Vectorially sum all segments’ contributions together, and display results in spectrum-
analyzer screen or board report.

Related Topics
“Assumptions of Core Radiation Algorithm” on page 898

Assumptions of Core Radiation Algorithm

The "core" differential-mode radiation-prediction algorithm (used segment-by-segment) is a
powerful, general 3-dimensional radiation predictor. However, in order to maintain reasonable
calculation speed, it makes several assumptions:

• There are no large, grounded metal objects near the trace(s) being analyzed (e.g.,
enclosure walls or grounded heat sink)
• The antenna is sufficiently distant that the radiation is far-field only
The far-field assumption precludes the antenna’s being any nearer than 3 meters from the board
being simulated. (This restriction—far-field prediction only—may be removed in future
versions of the software.)

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Related Topics
“Outline of HyperLynx Package-Radiation Algorithm” on page 899

Outline of HyperLynx Package-Radiation Algorithm

On many modern boards, the component packages themselves (especially IC packages)
generate significant amounts of radiation. In order to better match actual lab results, BoardSim
EMC automatically creates a radiation model for the package of each component attached to the
trace being simulated (not available in LineSim EMC). This modeling is performed
automatically so as not to burden the user with extra modeling requirements.

It should be noted that prediction of package radiation is necessarily more approximate than
prediction of trace radiation. For this reason, modeling package radiation is always optional in
BoardSim EMC; it can be turned on or off at the user’s discretion. Nevertheless, HyperLynx
believes it has a very good automated method for creating package radiation models, described
as follows:

"Flow" of the HyperLynx package-radiation algorithm:

1. User chooses trace to analyze. Software "pulls in" every component attached to trace.
2. Each component package footprint is analyzed. Footprint information is combined with
knowledge of component’s type (IC, resistor, etc.) to allow automatic matching to
physical package type (e.g., DIP, SOIC, 1206 discrete, etc.)
3. Two "active" pins on each component automatically determined: "input" and "output"
pin for series passive component (e.g., resistor), or I/O pin and matching power-supply
pin for IC.
4. Active pins are modeled as radiators standing vertically on a conducting plane (with
multiple dielectric boundaries); opposing current directions in two pins gives differential
effect.
Radiation from component pins is added to trace radiation during simulation.

Related Topics
“Assumptions of Package Radiation Algorithm” on page 899

Assumptions of Package Radiation Algorithm

Several simplifying assumptions are built into the package-radiation algorithm (listed below). If
any of these is substantially violated by a particular component (e.g., a microprocessor with
sophisticated package), the user may wish to disable package radiation and concentrate
exclusively on trace radiation.

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Preparing the Board or Schematic for EMC Simulation

• Packages are referenced to the nearest power/ground plane in the PCB stackup, and lack
any significant internal grounding
• Current out of an IC is sourced by (or current into an IC is sunk by) the nearest
appropriate power-supply pin; ICs do not have multiple power rails
• ICs are not socketed, i.e., they stand off of the PCB by their intrinsic package height
only

How Maximum Radiation is Found

In general, the fields around a real PCB are not symmetric: they have "lobes" that cause the
radiation to be stronger in certain directions from the PCB than from others. In EMC lab testing,
then, the PCB is rotated and the sensing antenna raised and lowered to find the positions of
maximum radiation.

LineSim EMC/BoardSim EMC automatically finds the position of maximum radiation for each
frequency at which there is significant radiation. The software’s method closely matches that of
a real testing lab: the PCB is rotated through 360 degrees in small increments and the antenna is
raised from the plane of the PCB up to 45 degrees elevation (again incrementally), all as the
radiation is constantly recalculated in search of a maximum.

Preparing the Board or Schematic for EMC

Simulation
Before you simulate, you must have an electrically valid stackup and you must select a driver IC
for the selected net.

The requirement to have a valid stackup applies in LineSim even if you have not modeled any
transmission lines in the schematic with the stackup method. However LineSim always starts a
new schematic with a valid default stackup, so this requirement is satisfied even if your
schematic has no stackup-based transmission lines.

Additional Requirements for Simulating Differential Nets

If you are simulating a pair of differential-signal nets, you must do the following:

• Use an IBIS differential model for the driver-IC pin pair; if you use a non-IBIS model
(.MOD or .PML) or a non-differential IBIS model, the spectrum analyzer will not run
and display the error message "too many drivers."
• Set one side of the differential model to state Output and the other to state Output
Inverted, to ensure that the canceling effect of the opposed differential currents is
properly modeled.

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Related Topics
“Creating and Editing Stackups” on page 353

“Assigning Models to Pins” on page 467

“Simulating EMC with the Spectrum Analyzer” on page 887

Setting Up the Spectrum Analyzer

When the circuit is ready to simulate, open the spectrum analyzer, set up the antenna or current
probe, and adjust spectrum analyzer settings.

This topic contains the following:

• “Opening the Spectrum Analyzer” on page 901

• “Choosing the Driver Waveform for EMC” on page 902
• “How Duty Cycle Affects EMC Simulation” on page 903
• “Setting IC-Model Operating Parameters” on page 903
• “Setting the Central Frequency and Bandwidth” on page 904
• “Choosing Regulatory Limits” on page 905
• “Defining User EMC Limits” on page 905

Opening the Spectrum Analyzer

To open the spectrum analyzer:

• Run Interactive EMC Simulation (Spectrum Analyzer) button .

Alternative: Simulate SI menu > Run Interactive EMC Simulation.
The spectrum analyzer may remain open while you return to the BoardSim/LineSim window
and modify your design in some way, such as assigning different models or adding a Quick
Terminator.

You can resize the Spectrum Analyzer window with standard window controls, such as
dragging an edge of the window with the mouse. As you resize the window, the main screen
will expand or contract and the overview pane height remains constant.

Restriction: Only one spectrum analyzer may be opened at a time.

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Resizing the Display Panes

As a convenience, you may change the relative size of the mini oscilloscope and spectrum panes
using the window splitter bar control that separates them.

To change the relative size of the mini oscilloscope and spectrum panes:

• Drag the splitter bar just above the spectrum pane up or down with the mouse. The
pointer shape will change to a double-arrow when it is over the splitter bar.

Choosing the Driver Waveform for EMC

LineSim EMC/BoardSim EMC predicts radiation for clocked signals, i.e., nets that carry a
regular, periodic signal. (Aperiodic signals rarely cause EMC problems; see “Brief EMC
Technical Background” on page 891 for details.) Therefore, before you simulate, you must
specify the frequency and duty cycle of the driver switching waveform.

To specify the frequency:

• In the Stimulus area, type a value (in megaHertz) into the Freq box.
To specify the duty cycle:

• In the Stimulus area, type a value (in percentage) into the Duty Cycle box.
The duty cycle value defines the percentage of time that the driver spends high.

If you enter a perfect 50%-50% duty cycle, LineSim EMC/BoardSim EMC reminds you that
perfectly balanced duty cycles almost never exist in a real system. You can simulate with the
duty cycle set to 50%, but LineSim EMC/BoardSim EMC defaults to a slightly asymmetric duty
cycle.

See also: “How Duty Cycle Affects EMC Simulation” on page 903

About Non-Clock Signals

It is periodic signals, i.e., signals with a regular repeating pattern, that cause EMC problems.
The reason is that periodic signals have most of their energy "bunched" at frequencies that are
multiples of the signal's base frequency, i.e., at harmonics. Aperiodic (non-repeating) signals,
by contrast, have their energy spread out over a wide range of frequencies. It is the high
concentrations of energy at harmonic frequencies that usually cause EMC failures.

This does not mean that only clock signals should be simulated in LineSim EMC/BoardSim
EMC, however. Any signal, regardless of its logic function, that regularly repeats is a candidate
to be simulated. In addition to clocks, you may also want to consider:

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• Strobe and control lines with regular patterns (e.g., RAS and CAS in a DRAM
subsystem)
• Low-order address lines (e.g., A0—A3)
For these kinds of repeating but non-clock signals, adjust the frequency and duty cycle to best
match the shape of the expected waveform.

How Duty Cycle Affects EMC Simulation

EMC simulations are very sensitive to a signal's duty cycle. This is particularly true when
comparing results from a simulation run with a perfect 50%-50% duty cycle to results from a
simulation with a non-ideal duty cycle, e.g., 48%-52%. If you set the duty cycle to exactly 50%-
50%, the signal's even-harmonic radiation may be low or non-existent (depending on how
"clean" the net is from a signal-integrity standpoint; recall that are perfect square wave has only
odd harmonics). Since real signals are rarely perfectly balanced, you may want to simulate at a
duty cycle that is slightly off of perfect (like 49%-51%), to remind yourself that even-harmonic
radiation may exist in your system.

When you enter a duty cycle in LineSim EMC/BoardSim EMC, you enter only a single number:
the percentage of time that you want the signal to spend in its high state.

Setting IC-Model Operating Parameters

If there are IC models in your simulation, you can control from the spectrum analyzer whether
the models run with best-case, typical, or worst-case operating parameters.

What IC Operating Settings Mean - EMC

The IC operating settings are actually combinations of the min and max data in an IC model.
The combinations are named Slow-Weak, Typical, and Fast-Strong, to be as descriptive as
possible. Table 18-2 shows how the combinations are defined.

Table 18-2. IC Operating Settings

Parameter for Fast-Strong/for Slow-Weak
driver current: max/min
slew rate: max/min
clamp-diode current: max/min
component capacitance: min/max
package inductance: min/max
package capacitance: min/max
package resistance: min/max

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For more details on IC modeling formats, see “IC-Model Formats” on page 507.

Setting the Operating Conditions - EMC

To set the IC operating parameters:

• In the IC Modeling area, click an option.

Setting the Central Frequency and Bandwidth

Both the center frequency and horizontal scale (MHz/div) settings for the spectrum analyzer are
set in the Horizontal area. The two settings are independent.

Setting the Central Frequency

To set the central frequency:

• Type a value (in megaHertz) into the Central Freq box or click an arrow button beside
the Central Freq box.
Alternatives:
• Rotate the Central Freq knob by dragging it with the mouse.
• Click the Central Freq knob and press Page Up/Page Down (coarse change).

Setting the Horizontal Scale - EMC

To set the horizontal scale (MHz/div):

• Click an arrow button beside the Scale box.

Alternatives:
• Rotate the Scale knob by dragging it with the mouse.
• Click the Scale knob and press Page Up/Page Down.
The spectrum analyzer’s frequency-scale increments are logarithmic (1,2,5,10,...).

Red Display if the Center Frequency is Not Valid

It is possible to set a combination of center frequency and horizontal scale such that the
specified center frequency cannot be displayed (i.e., some other frequency has to be at the
center of the display in order to avoid showing negative frequencies). When this occurs, the
frequency value in the Center Freq box turns red.

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Choosing Regulatory Limits

LineSim EMC/BoardSim EMC allows you to check your EMC simulation results against
government regulations, so you can see whether or not your nets' radiation exceeds those limits.
The spectrum analyzer displays the appropriate limits directly on its display, so you can do easy
visual comparisons.

You can choose between the following regulatory limits:

• FCC—United States
• CISPR—European Community
• VCCI—Japan
• USER—your own custom limits
For each type of limit, you can choose either or both product "classes":

• Class A—for industrial products

• Class B—for consumer products
The user limits allow you to create your own specification to check against. You might have a
rule, for example, that you want no single net on your board to exceed 70% of the FCC or
CISPR limits. You could use the user limits to define this requirement.

Steps to Choose Limits

To choose one or more limits to check against:

1. In the Regulations area, select one or more of the regulation types (FCC, CISPR, VCCI,
user).
2. In the Class area, select one or both of the class selections.
The limits are plotted in the spectrum-analyzer display as soon you enable them. Each type of
limit (FCC, CISPR, etc.) has its own color, so you can display several sets of regulations
simultaneously.

Related Topics
“Defining User EMC Limits” on page 905

Defining User EMC Limits

To define your own custom "user" EMC limits:

1. Do one of the following:

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• If you are using the Spectrum Analyzer, in the Regulations area, click USER.
• If you are using the batch simulation wizard, in the Regulatory Constraints area of
the wizard page, click Define Limits.
2. In the Class A Limits and Class B Limits areas, type frequency and electric-field-
strength values that define your desired custom limits. Enter values that define your
limits at a distance of 3 meters; LineSim/BoardSim EMC will scale the values if you
simulate at other distances.
3. Click OK.

Rules for Defining Limits

• Define limits for an antenna distance of 3 meters.
• All data boxes must be filled, even if you do not need all of them to define your limits.
• Limit 1 sets the testing level for frequencies between the Start Frequency and Frequency
2; Limit 2 sets the level between Frequency 2 and Frequency 3; and so forth.
• If you do not need all four limit levels, fill the unused data boxes with the value of the
last-used frequency and limit. For example, if the last boxes you need are Frequency 4 =
1000 MHz and Limit 3 = 40 dBuV/m, and then set the End Frequency also to 1000 and
Limit4 to 40.
• LineSim/BoardSim EMC will not accept your values if the frequencies do not increase
or stay the same as you move from Start to End frequency. For example, if Frequency 4
is 1000 MHz and you enter 0 MHz for End Frequency, LineSim/BoardSim EMC will
give an error and force you to correct the values.
To employ your user limits:

• In the Spectrum Analyzer dialog box, in the Regulations area, select the USER check
box and then select the Class A/Class B check boxes (one or both).
You can also check against user limits automatically, in batch simulation.

See also: “Selecting Nets and Editing Constraints for EMC Simulation”

Setting Up the EMC Antenna or Current Probe

In LineSim EMC/BoardSim EMC, the "probe" means either an antenna or a current probe. The
antenna is used to measure electric-field strength like you would in an EMC lab. The current
probe gives you a way of viewing the current flowing at a point in your circuit. For the antenna,
you specify a distance from the board; for the current probe, you specify a component pin on the
net(s) you are simulating. The spectrum analyzer supports a single antenna or current probe.

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Current probing is used rather than voltage because radiation is generated by current flow.
Antenna probing accounts for both the source currents on the net and how effective the net is as
a radiator (i.e., its unintended antenna characteristics); the antenna measures electric-field
strength directly. The current probe measures only the source current, but displays it in the
frequency domain, so you can see how much current is present at various frequencies of
interest. Normally, you will use the antenna; in certain cases where you want to focus directly
on current and reducing it, you might use the current probe.

This topic contains the following:

• “Choosing Between Antenna and Current Probes” on page 907

• “Setting Up the Antenna” on page 908
• “Attaching the Current Probe to a Pin” on page 911
• “Probing Where There is No Component - EMC” on page 913
• “How EMC Probes Display” on page 914

Choosing Between Antenna and Current Probes

To choose between the antenna and a current probe:

1. Simulate SI menu > Attach Spectrum Analyzer Probe.

Alternative: With the spectrum analyzer open, in the Probe area, click Set.
2. In the Probe Type area, click Antenna or Current. The Probe Type area displays your
selection.
Restriction: The antenna probe is not available for MultiBoard projects because the
MultiBoard project does not contain information about the physical relationship among the
individual boards. However, you can run EMC simulation using the current probe for
MultiBoard projects.

Units for Radiation Measurement

If you choose LineSim EMC/BoardSim EMC's antenna as a probe, measurements are made and
displayed in dBuV/m, i.e., microvolts/meter (the unit of electric-field strength) on a logarithmic
decibel scale.

If you choose a current probe, measurements are made in mA, on a logarithmic scale.

Reasons to Use the Current Probe

Since currents flowing in nets are ultimately the source of radiation from your board, one
approach to EMC design/analysis is to focus only on those currents, and reducing them or re-
distributing where their energy lies. If this is the way you prefer to do EMC design, then the

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current probe is valuable. Switching to the antenna adds the additional element of weighting the
source currents by the antenna characteristics of the trace segments on the board, and predicting
actual electric-field strengths off-board.

Another advantage to the current probe is increased simulation performance. Radiation

prediction is mathematically complex, so running with the antenna enabled entails additional,
time-consuming mathematical steps. Turning on the current probe instead eliminates the
radiation-prediction steps and so produces faster results.

The disadvantage of the current probe is that its results do not compare directly to EMC-lab
measurements (i.e., current is measured instead of electric-field strength). The current probe is
valuable as a way of understanding the frequency composition of your signals, but direct
correlation to radiation levels is not easy to make.

Setting Up the Antenna

There are several aspects to setting up LineSim EMC's/BoardSim EMC's antenna: setting its
distance; choosing its position; and deciding to which radiation sources it will be sensitive
(traces, component packages).

To set up the antenna, first open the Set Spectrum Analyzer Probing dialog box:

• Simulate SI menu > Attach Spectrum Analyzer Probe.

Alternative: With the spectrum analyzer open, in the Probe area, click Set.
Then, follow the steps in the topics below.
• “Choosing Antenna Distance” on page 908
• “Setting the Antenna and Board Position” on page 909
• “Choosing From Which Sources to Measure Radiation” on page 909
• “Enabling Trace Radiation” on page 910
• “Enabling Multipath Correction” on page 911

Choosing Antenna Distance

In an EMC lab, you typically have the choice of making measurements at one of several
standard distances (usually measured in meters). Your results are compared to the appropriate
government regulations, with the limits scaled for the distance you choose. The most-typical
distances are 3 meters, 10 meters, and 30 meters. As the popularity of anechoic (shielded)
chambers increases, the 3-meter distance is becoming most-common, since building a large
chamber is prohibitively expensive.

To set the antenna distance:

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• In the Antenna Probe area, on the Distance from Antenna to PCB list, select 3, 10, or 30
meters.
The distance you choose is arbitrary. If you plan to perform real EMC-lab measurements on
your board, you may want to use the same distance you will later use in the lab.

Setting the Antenna and Board Position

In an EMC lab, the board under test is rotated and the measurement antenna raised and lowered
so that the maximum radiation at each frequency is found. In LineSim EMC/BoardSim EMC,
this positioning is performed automatically for you — or you can disable it and fix the board's
and antenna's positions. The advantage to a fixed position is that simulations run faster. The
advantage to checking all positions is that the maximum radiation at each frequency is found
automatically.

See also: “How Maximum Radiation is Found” on page 900

Finding Maximum Radiation Automatically

To have the maximum radiation at each frequency found automatically:

• In the Antenna and Board Position area, select the Automatically Find Positions for
Maximum Radiation check box.

Manually Setting Antenna and Board Position

To use a fixed antenna and board position:

1. In the Antenna and Board Position area, clear the Automatically Find Positions for
Maximum Radiation check box. The Antenna Height and PCB Rotation Angle
selections become active.
2. In the Antenna Height box, type the value in meters of the antenna's elevation.
3. In the PCB Rotation Angle box, type the value in degrees of the board's rotation angle.
The antenna height is measured from the plane of the board (i.e., it measures how much higher
than the board the antenna is set). Typical values range from 0 to 3 meters. PCB rotation
specifies the rotation angle of the board measured in its own plane. Maximum radiation may
occur at any angle between 0 and 360 degrees.

Choosing From Which Sources to Measure Radiation

The radiation from a PCB comes not only from the board's traces, but also from the ICs on the
board. On many modern boards, the ICs may radiate as much or more than the PCB's traces.
BoardSim EMC is able to predict component-package radiation.

See also: “Brief EMC Technical Background” on page 891

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Enabling Package-Radiation Measurement

To enable measurement of the radiation from a board's component packages:

• In the Include Radiation From area, select Component Packages.

Requirement: The BoardSim EMC license is required to run EMC simulation.

One of BoardSim EMC's strengths is that it is able to predict the radiation emanating from
component packages. It does so without requiring you to enter any special information about the
packages; all the required modeling data are determined automatically from an examination of
your PCB.

When to Turn Package Radiation On and Off

You can toggle package radiation on and off to see the contribution that your components'
packages (especially ICs) are making to a net's radiation levels. For example, start with package
radiation enabled and run a simulation; then disable package radiation and re-simulate; then
compare the two sets of results. (See “Re-Simulating - Comparing EMC Results” on page 918
for details on how to compare.) Generally, the radiation levels will be significantly higher with
package radiation enabled than without.

Package Radiation not Available in LineSim EMC

LineSim EMC is not able to predict package radiation, because there is no physical information
available about the ICs in a LineSim schematic. Radiation is from the stacked-up traces in the
schematic only.

Quick Terminators and EMC Simulations

You can add a Quick Terminator to a net for which you are running EMC simulations, to see
whether adding the terminator to your board would improve the net's radiation profile.
However, be aware that unlike real passive components (components that are actually included
in your layout), Quick Terminators do not contribute any package radiation to the spectrum
analyzer's results. This occurs because BoardSim EMC does not have any information about a
Quick Terminator's physical package or its orientation on your board.

Requirement: The BoardSim EMC license is required to run EMC simulation.

Enabling Trace Radiation

To enable measurement of the radiation from a board's traces:

• In the Include Radiation From area, select the Printed Circuit Traces check box.
Normally, you would always leave trace radiation enabled, unless you want to completely
isolate a net's package radiation.

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Enabling Multipath Correction

The government EMC standards (e.g., FCC and CISPR) require that tests be performed at a site
with an earth-grounded metal floor. The reason is that a grounded floor is non-absorbing, i.e., it
will reflect back up to the sensing antenna radiation that emanates from the bottom of the board
under test. The ability to measure radiation that travels both directly and indirectly to the
antenna is called "multipath" sensing.

If you test a board in an open-field chamber, odds are high that an actual grounded floor will be
present. If you test in an anechoic chamber, there may not be a grounded floor, but if not, the
measured results will usually be corrected with software to compensate.

To enable multipath-sensing capability:

• In the Include Radiation From area, select the Multipath from Earth Ground check
box.
Normally, you would always leave multipath sensing enabled, so that LineSim EMC/BoardSim
EMC shows you results as if a grounded floor was present ("non-absorbing"). Turn multipath
off only if you're interested in seeing how large a difference it makes ("absorbing").

Attaching the Current Probe to a Pin

In most cases, you will use the antenna probe in LineSim EMC/BoardSim EMC, so that the
spectrum analyzer measures electric-field strength directly. However, you can optionally use a
current probe instead. The current probe requires you to choose a particular component pin for
probing. By contrast, the antenna makes measurements remotely.

You can probe in the schematic where there is no component.

See also: “Pin Names in LineSim EMC” on page 912

This topic discusses the following current probe assignment methods:

Table 18-3. Current Probe Assignment Methods
Method When to use
“Attaching Probe by Pin Name” on You know the name of the pin you want to
page 911 probe
“Attaching Probe by Pin Location in You can see the pin you want to probe
BoardSim” on page 912

Attaching Probe by Pin Name

To attach a current probe by pin name:

1. Simulate SI menu > Attach Spectrum Analyzer Probe.

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Alternative: In the Spectrum Analyzer dialog box, in the Probe area, click Set.
2. In the Probe type area, click Current.
3. In the Pins list, select the pin to which you want attach the probe.
In BoardSim, all pins have names of the form <reference_designator>.<pin_name>.
See also: “Pin Names in LineSim EMC” on page 912
4. Click Close.

Attaching Probe by Pin Location in BoardSim

To attach a current probe by pin location:

1. If the net you want to simulate is not already selected, right-click over the pin you want
to probe and click Select Net.
2. Right-click again over the pin you want to probe and click Attach Spectrum Analyzer
Probe.
3. In the Probe type area, click Current.
4. In the Pins list, select the pin to which you want attach the probe.
In BoardSim, all pins have names of the form <reference_designator>.<pin_name>.
See also: “Pin Names in LineSim EMC” on page 912
5. Click Close.

Pin Names in LineSim EMC

Passive Components
Pins on passive components have names of the form:

<component_type>(XY).<pin_number>

where <component_type> is:

• RP for a pull-up resistor

• RD for a pull-down resistor
• C for a capacitor
• RS for a series resistor
(XY) is the component’s cell label in the schematic, and <pin_number> is "1" or "2".

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Pin Numbers
Terminating-component pin numbers are assigned as follows:

• For pull-up and pull-down resistors, and capacitors:

• Pin 1 is the side farthest from the power-supply net
• Pin 2 is the side attached to the power-supply, or nearest to it
• For series resistors:
• Pin 1 is the left side
• Pin 2 is the right side

ICs
Pins on ICs have names of the form:

U(XY)
where (XY) is the IC’s cell label in the schematic. Unlike with passive components, there is no
explicit pin number (i.e., "1" or "2").

Related Topics
“Probing Where There is No Component - EMC” on page 913

Probing Where There is No Component - EMC

In LineSim EMC, To probe current at a location in your schematic where there is no
component, such as between two transmission lines, use the following "trick."

Restriction: This probing capability is available only in LineSim. In BoardSim EMC, you can
probe only at component pins.

To probe current at a location where there is no component:

1. Do one of the following:

a. Modify the schematic to add an IC component to the location you want to probe, but
do not assign an IC model to it.
For cell-based schematics only, if an IC model had been previously assigned to the cell,
the model is restored when the IC is activated. In this case remove the IC model by
right-clicking over the IC, clicking Assign Models if available, and then removing the
model.
See also: “Removing Models” on page 483

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b. Add a 10K pull-up or pull-down resistor to the net.

Such a large resistor will have little or no effect on your circuit because it is a very small
load, but it provides a component pin at which you can probe. Its package parasitics will
be present, however, and for very-high-speed signals, you may want to reduce those to
minimum values before simulating.
2. In the Spectrum Analyzer dialog box, in the Probe area, click Set.
3. In the Probe Type area, click Current.
4. In the Pins list, double-click the component pin you want to probe.

How EMC Probes Display

In LineSim EMC with the Current Probe Attached

In LineSim EMC, if you're using the current probe, when you exit the Attach Spectrum
Analyzer Probe dialog box the schematic editor updates to show the probe location. The probe
is displayed in the editor as a colored, circled arrow labeled with the pin to which it is attached.
The circle around the arrow distinguishes it from oscilloscope probes.

In BoardSim EMC with the Antenna Probe Attached

In BoardSim EMC, if you're using the antenna probe, an "antenna" icon appears in the corner of
the board viewer as a reminder. The icon shows an antenna shape and a readout of the antenna's
distance setting.

See also: “Setting Up the Antenna” on page 908

In BoardSim EMC with the Current Probe Attached

In BoardSim EMC, if you're using the current probe, when you exit the Attach Spectrum
Analyzer Probe dialog box the board viewer updates to show the probe location on the currently
selected net. The probe is displayed in the viewer as a colored, circled arrow labeled with the
pin to which it is attached. The circle around the arrow distinguishes it from oscilloscope
probes.

Running EMC Simulations

Use the spectrum analyzer to run interactive EMC simulations on the net.

This topic contains the following:

• “Running an EMC Simulation” on page 915

• “EMC Simulation Display” on page 916

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See also: “Setting Up the Spectrum Analyzer” on page 901

Running an EMC Simulation

To run a simulation:

• In the Spectrum Analyzer dialog box, click Start Simulation.

Result: The Simulation Status dialog box opens, and simulation begins.

Transient Steps - EMC

When the pre-transient steps are completed, LineSim EMC/BoardSim EMC begins its time-
domain transient simulation. The results of the time-domain simulation are not displayed until
after the entire simulation is complete, including conversion of data to the frequency domain
and radiation analysis. The transient simulation make take some time to complete, as the
simulator needs multiple clock cycles on which to base its analysis.

Anti-Aliasing Filter
Before converting the transient data to the time domain, LineSim EMC/BoardSim EMC runs a
sharp, 36-dB/octave low-pass filter to ensure that no aliasing occurs when the data are
converted to the frequency domain. The cut-off point of the filter is determined automatically
by the simulator.

Time-to-Frequency-Domain Conversion
After the time-domain simulation is complete, LineSim EMC/BoardSim EMC converts the
time-domain results to the frequency domain, using a Fast Fourier Transform.

Radiation Simulation Using the Antenna Probe

If you are using the antenna probe, after conversion to the frequency domain, LineSim
EMC's/BoardSim EMC's radiation-prediction algorithms run. These perform a sophisticated 3-
dimensional field analysis to determine, at every point in space for which they're called, what
radiation levels are generated by the net or schematic being simulated. Radiation prediction is a
mathematically intense process, and may take a considerable amount of time to run. The
Simulation Status dialog box advises you of the program's status.

Percent Done and Status Messages - EMC

The Simulation Status box displays the completion percentage during each phase of the
simulation. The dialog box also displays text messages from the simulator telling you what
steps are currently being run, etc.

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Simulating EMC with the Spectrum Analyzer
Examining EMC Simulation Results

EMC Simulation Display

LineSim EMC/BoardSim EMC shows two views of the simulation:

• Near the top, a Mini oscilloscope display, showing a time-domain current waveform at
the driver IC.
• Near the bottom, a spectrum display, showing the frequency-domain results of the
simulation.
If you point to a yellow reading in the spectrum display, a ToolTip displays the maximum
predicted value at that frequency.

The program automatically determines how to create the time-domain data needed for a valid
frequency analysis. The Mini oscilloscope display may help you understand why you're seeing
in the frequency domain the results you are. Note that the waveform is of driver current (not
voltage).

Hatched Bandwidth-Limitation Zone

As you change the settings in the spectrum analyzer's Horizontal area, you may see a hatched
region on the right side of the analyzer's display. The hatching covers the frequency area in
which the spectrum analyzer's response has fallen by 3 dB or more, so that data there is not
valid. The bandwidth of the spectrum analyzer is automatically controlled by LineSim
EMC/BoardSim EMC.

Examining EMC Simulation Results

Use the spectrum analyzer examine graphical EMC results, view numerical EMC results, or to
perform “what if” experiments by comparing graphical EMC results for different design
parameters (such as IC models).

This topic contains the following:

• “Setting the Vertical Offset” on page 916

• “Setting Auto Scale” on page 917
• “Viewing Numeric EMC Simulation Results” on page 917
• “Re-Simulating - Comparing EMC Results” on page 918
• “Erasing a Simulation” on page 918

Setting the Vertical Offset

You can change the vertical offset in the Spectrum display to view data of any amplitude.

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 Simulating EMC with the Spectrum Analyzer
Examining EMC Simulation Results

To set the spectrum analyzer's vertical offset:

• Click an arrow button beside the Offset box.

Alternatives:

• Rotate the Offset knob by dragging it with the mouse.

• Click the Offset knob and press Page Up/Page Down.
The vertical offset units depend on whether you select an antenna or current probe. If you select
the antenna probe, the display is measured vertically in dBuV/m (a decibel measurement of
electric-field strength), and the offset increment is 10 dBuV/m. If you select the current probe,
the display is measured vertically in mA, and the offset increment is in decades (e.g., 10mA,
100mA, 1A, etc.).

See also: “Choosing Between Antenna and Current Probes” on page 907

Setting Auto Scale

Auto Scale automatically adjusts the vertical offset to display the maximum radiated-emissions
reading in the Spectrum display.

To set auto scale:

• Click Auto Scale.

Auto Scale does not adjust the horizontal scale. If you selected Auto Scale and no radiated-
emissions readings are visible, try increasing the horizontal scale.

Viewing Numeric EMC Simulation Results

Use the ToolTips and View Points functions to view numeric EMC simulation results from
within the spectrum analyzer. These functions help you quickly view numeric EMC simulation
results without having to export the simulation data to a .CSV file.

To display maximum radiated-emissions readings using ToolTips:

• In the Spectrum display, position the pointer anywhere over a yellow radiated-emissions
reading to display a ToolTip containing the maximum value at that frequency.
To display all radiated-emissions readings using View Points:

• Click View Points. The File Editor opens and displays the simulation results.

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Examining EMC Simulation Results

Re-Simulating - Comparing EMC Results

You can simulate a given board or schematic multiple times to see the effects of different IC
models, line terminations, and so forth.

Displaying the Previous Results

For purposes of comparison, you can switch between the results of both the current simulation
and the previous simulation (subject to certain caveats; see "When Previous Results Cannot be
Displayed" below for details).

To display the results of the previous simulation:

• In the Spectrum Analyzer dialog box, select Show Previous.

To return to the results of the current simulation:

• In the Spectrum Analyzer dialog box, select Show New.

When Previous Results Cannot be Displayed

The results of the previous simulation cannot always be displayed. In particular, any change that
adds or subtracts transmission lines to/from the simulator's circuit model may change the
simulator's internal timebase and preclude displaying the previous results. This occurs if a new
net is selected, for example, or sometimes when a Quick Terminator is added to the previous
simulation's net.

To save the results of a previous simulation that cannot be displayed:

1. Before closing the spectrum analyzer after the previous simulation, on the spectrum
analyzer, click Copy to Clip. This copies the results to the Windows Clipboard.
2. Paste the clipped results into any Windows program that allows Clipboard pasting, e.g.,
Word or any Windows picture viewer.
3. Compare subsequent simulations to the clipped results.

Erasing a Simulation
You can erase the current simulations from the spectrum analyzer screen. Previous simulations
are not erased.

To erase current simulations in the spectrum analyzer:

• Click Erase.

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 Simulating EMC with the Spectrum Analyzer
Documenting EMC Simulation Results

Documenting EMC Simulation Results

You can record EMC simulation results in order to share them with other people, to record
EMC results for a specific design configuration, or to examine them in another application by
exporting data in a CSV file.

This topic contains the following:

• “Entering Spectrum-Analyzer Comments” on page 919

• “Printing EMC Simulations” on page 919
• “Copying EMC Simulations to the Clipboard” on page 919
• “Exporting EMC Simulation Data to Another Application - CSV File” on page 920

Entering Spectrum-Analyzer Comments

The Spectrum Analyzer dialog box includes an area above the screen labeled "Comment." The
Comment box allows you to enter a description or comment that prints or is copied to the
Windows Clipboard with your spectrum-analyzer results.

To enter a printable comment in the spectrum analyzer:

• In the Comment box above the screen, type the description or comment.

Printing EMC Simulations

You can print your simulation results in order to document them.

LineSim EMC and BoardSim EMC support color printers; simulation results sent to a color
printer are output with colored waveforms.

To print simulation waveforms:

1. In the Spectrum Analyzer dialog box, click Print.

2. In the Print dialog box, check your printer setup, and then click OK.

Copying EMC Simulations to the Clipboard

You can copy your simulation results to the Windows Clipboard in order to paste them into
other Windows applications. The image sent to the Clipboard is formatted, and includes
information such as the name of the board or schematic file and a time and date stamp.

To copy simulation results to the Windows Clipboard:

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Simulating EMC with the Spectrum Analyzer
Documenting EMC Simulation Results

• In the spectrum analyzer, click Copy to Clip.

Exporting EMC Simulation Data to Another Application -

CSV File
Occasionally, you may want to export the EMC simulation data displayed in the spectrum
analyzer to another application, like Excel or Mathcad. To facilitate this need, the spectrum
analyzer can output a comma-separated-values (.CSV) file containing all the data displayed in
the spectrum analyzer window for the present simulation. .CSV files can be read directly by
Excel (and most other spreadsheet programs), and are easily read by an input routine in
mathematical programs like Mathcad.

To write a .CSV file representing the results of the present simulation:

1. Click Save As CSV.

2. Choose a directory and name for the .CSV file.
3. Click Save.
Data from the Mini oscilloscope display is not included when you save the .CSV file.

Some European versions of Microsoft Excel cannot open the .CSV file from the Open menu,
possibly due to the use of commas as decimal indicators. A workaround is to open Windows
Explorer and double-click on the .CSV file.

Format of the CSV File

When the antenna probe is used, the .CSV file contains columns representing frequency versus
radiated emission data. When the current probe is used, the .CSV file contains columns
representing frequency versus current data.

The frequency data in the file is in megaHertz; voltages are in microvolts/meter; currents are in
milliamps.

The .CSV file will open directly in programs like Microsoft Excel (in Excel, use File/Open or
double-click in the Windows Explorer on the .CSV file). If you are reading the file with a
mathematics-package program and do not want the header information at the top (creation date,
etc.), you can remove it using any text editor.

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 Chapter 19
Simulating Unrouted Nets with Manhattan
Routing

Early in the PCB layout process, after components have been placed, you may want to analyze
nets that have not yet been routed (i.e. unrouted nets). Or perhaps you have identified previously
routed nets that have not met your signal timing, signal integrity, crosstalk, or EMI goals.

Fortunately, BoardSim can create Manhattan routing for unrouted nets or for nets that you want
to re-route. BoardSim's Manhattan routing capability allows you to perform "what if"
experiments to predict the effects of routing, re-routing, or component repositioning.

When you might use BoardSim's Manhattan routing in the PCB layout process:

• Immediately after placement and before routing begins

• After only some critical nets have been routed, but while the remainder of the board is
still unrouted
• After existing routing or component placement yield poor analysis results
This topic contains the following:

• “About Manhattan Routing in BoardSim” on page 922

• “How Manhattan Routing is Modeled” on page 922
• “Creating Manhattan Routing” on page 923
• “Saving and Restoring Session Edits for Manhattan Routing” on page 927
• “About Unrouting Nets” on page 927
• “Unrouting Nets” on page 928
• “Viewing Manhattan Routing and Unrouted Nets” on page 930
• “Reporting Manhattan Routing and Unrouting Changes” on page 930
• “Connect Nets with Manhattan Routing Dialog Box” on page 931
• “Unroute Routed Nets Dialog Box” on page 934

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About Manhattan Routing in BoardSim

About Manhattan Routing in BoardSim

BoardSim's Manhattan routing mimics real routing by generating the physical parameter values
(e.g., net length, trace width) required for simulation. BoardSim can create Manhattan routing
for unrouted, partially routed, or fully routed nets. BoardSim re-routes partially routed and fully
routed nets by first completely unrouting them, then re-routing them with Manhattan routing.

If you have loaded a MultiBoard project into BoardSim, note that Manhattan routing is created
only for the selected board ID (i.e. Manhattan routing stops at the board's external connector).

Both signal and power-supply nets may be routed with Manhattan routing. Manhattan routing
can be created for nets with any number of pins, vias, or pads.

How Manhattan Routing is Modeled

To analyze the selected net, BoardSim generates Manhattan routing to represent the physical
parameter values required for simulation. You can control the values of the physical parameters
(e.g., net length, trace width, etc.) used to route the net with Manhattan routing, see “Creating
Manhattan Routing” on page 923 for details.

This topic contains the following:

• “Key Points From the Manhattan Routing Algorithm” on page 922

• “How Simulation Length for Manhattan Routing is Calculated” on page 923
• “Why Crosstalk is not Supported for Manhattan Routing” on page 923

Key Points From the Manhattan Routing Algorithm

• BoardSim calculates the net's simulation length (which you can override)
• You set the Manhattan routing's trace width
• For the selected net(s), Manhattan routing takes place on only one stackup layer (no vias
are created)
• You select the stackup layer used to route the selected nets with Manhattan routing
• Different groups of nets may have different physical parameter values
• A simple daisy chain connects the pins on a net; there are no branches or tees
• BoardSim sets the pin connection order for the net
• In a MultiBoard project, Manhattan routing takes place on one board at a time

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 Simulating Unrouted Nets with Manhattan Routing
Creating Manhattan Routing

How Simulation Length for Manhattan Routing is

Calculated
BoardSim automatically calculates the Manhattan routing's simulation length for all the nets
you choose to re-route.

To determine the simulation length for a re-routed net, BoardSim multiplies the net's Calculated
Net Length by a Manhattan multiplier:

simulation length = Calculated Manhattan Length x Manhattan multiplier

Where:

• Calculated Manhattan Length—refers to the sum of all pin-to-pin segment lengths for
the net, where BoardSim calculates the Manhattan length for each segment.
• Manhattan length—refers to the shortest connection than can be made between two
points on a board, while using only the board’s X-Y routing tracks (i.e. no diagonal
traces). The Manhattan length is the sum of the segment's X length and Y length, where
X length = abs(X1 – X2) and Y length = abs(Y1 – Y2). For nets with several pins or
pads, the Manhattan length is calculated for each segment, which is then summed into
the Calculated Manhattan length.
• Manhattan multiplier—a factor used to compensate for non-ideal routing (i.e. routing
that avoids collisions with other board elements) or to compensate for 45-degree routing
segments. You may increase or decrease the Manhattan multiplier to take these factors
into account.

Why Crosstalk is not Supported for Manhattan Routing

Manhattan routing has insufficient physical information for crosstalk analysis. For example,
Manhattan routing connects pins by a simple daisy chain and the Manhattan routing path
between pins is undefined. By contrast, crosstalk analysis requires trace-to-trace proximity
information that can be derived only from full routing information.

Signal integrity and EMC analysis can be performed on nets with Manhattan routing.

Creating Manhattan Routing

Use the Connect Nets with Manhattan Routing dialog box to route unrouted nets or reroute
routed nets with Manhattan routing.

This topic contains the following:

• “Opening the Connect Nets with Manhattan Routing Dialog Box” on page 924
• “Creating Manhattan Routing for All Unrouted Nets” on page 924

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Creating Manhattan Routing

• “Creating Manhattan Routing for Selected Nets Only” on page 925

• “Creating Manhattan Routing for Selected Nets and Associated Nets” on page 926

Opening the Connect Nets with Manhattan Routing Dialog

Box
Manhattan routing can be created at board load times or after your board has been loaded.

At Board-Load Time
When you load your board, if any completely unrouted nets exist and Manhattan routing
information for them has not been saved to the .BUD file, or restored from the .BUD file (using
the Restore Session Edits dialog box), BoardSim asks whether you want to connect them using
Manhattan routing:

• If you click "Yes," the Connect Nets With Manhattan Routing dialog box opens and you
can proceed to create Manhattan routing before the board has been loaded. See
“Creating Manhattan Routing” on page 923 for instructions to create Manhattan routing.
• If you click "No," the board is loaded and no Manhattan routing is created.

After the Board has been Loaded

To open the Connect Nets With Manhattan Routing dialog box after your board has been
loaded:

• Edit menu > Connect Nets with Manhattan Routing.

Creating Manhattan Routing for All Unrouted Nets

To create Manhattan routing for all unrouted nets (except power supplies):

1. Edit menu > Connect Nets with Manhattan Routing.

2. For a MultiBoard project, select the board ID in the Design File list.
Manhattan routing can be created for one board at a time.
3. In the Nets To Connect With Manhattan Routing area, click All unrouted nets (except
power supplies).
Power-supply nets are excluded when you choose to route all unrouted nets with
Manhattan routing. One reason is that signal nets and power planes/nets often use
different stackup layers with different thickness. You must manually select the power-
supply net to route it with Manhattan routing. See “Creating Manhattan Routing for
Selected Nets Only” on page 925.

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Creating Manhattan Routing

4. In the Routing Criteria area, type the new Manhattan multiplier value into the Multiplier
box. The valid value range is 0.1 to 10.
5. Select the stackup layer from the Layer list.
6. Type the trace width into the Width box.
Restriction: The width must not be zero.
7. Click Connect Net(s).
Result: After a brief pause, the net name area is refreshed (the net length values may be
updated). The dialog box remains open, ready for your next command.
8. If you have loaded a MultiBoard project into BoardSim and want to route nets on
another board, repeat steps 2-7.
9. Click Close.
To undo a Manhattan routing operation, reload the board file to restore the routing that existed
prior to the Manhattan routing operation.

Creating Manhattan Routing for Selected Nets Only

To create Manhattan routing for selected nets only:

1. Edit menu > Connect Nets with Manhattan Routing.

2. For a MultiBoard project, select the board ID in the Design File list.
Manhattan routing can be created for one board at a time.
3. In the Nets To Connect With Manhattan Routing area, click Selected nets only.
4. Select one or more nets to which you want a common set of routing criteria applied. See
“The Nets to Connect with Manhattan Routing Area” on page 932 for net selection tips.
5. Do one of the following:
• Click Specify Manhattan multiplier and type the new value into the box in the
Routing Criteria area. The valid value range is 0.1 to 10.
• Click Specify length and type the Manhattan routing length into the Length box.
See also: “How Simulation Length for Manhattan Routing is Calculated” on page 923
6. Select the stackup layer from the Layer list.
7. Type the trace width into the Width box.
Restriction: The width must not be zero.
8. Click Connects Net(s).

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Creating Manhattan Routing

Result: The net name selection is cleared, the net length values may be updated, and any
unrouted/partially-routed icons are removed for the nets that you just routed. The dialog
box remains open, ready for your next command.
9. To route additional nets on this board, repeat steps 4-8.
10. If you have loaded a MultiBoard project into BoardSim and want to route nets on
another board, repeat steps 2-9.
11. Click Close.
To undo a Manhattan routing operation, reload the board file to restore the routing that existed
prior to the Manhattan routing operation.

Creating Manhattan Routing for Selected Nets and

Associated Nets
Selecting the Selected Nets And Associated Nets radio button causes Manhattan routing to be
created for non-power-supply nets associated with the selected nets. To create Manhattan
routing for power-supply nets, select the power-supply nets directly.

Nets can be conductively associated to other nets by passive components such as resistors, or
can be logically associated by an IBIS IO buffer model as differential pin pairs.

See also: “Associated Nets” on page 272

To create Manhattan routing for selected nets and associated non-power-supply nets:

1. Edit menu > Connect Nets with Manhattan Routing.

2. For a MultiBoard project, select the board ID in the Design File list.
Manhattan routing can be created for one board at a time.
3. In the Nets To Connect With Manhattan Routing area, click Selected nets and
associated nets.
4. Select one or more nets to which you want a common set of routing criteria applied. See
“The Nets to Connect with Manhattan Routing Area” on page 932 for net selection tips.
5. In the Routing Criteria area, type the new Manhattan multiplier value into the Multiplier
box. The valid value range is 0.1 to 10.
See also: “How Simulation Length for Manhattan Routing is Calculated” on page 923
6. Select the stackup layer from the Layer list.
7. Type the trace width into the Width box.
Restriction: The width must not be zero.

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 Simulating Unrouted Nets with Manhattan Routing
Saving and Restoring Session Edits for Manhattan Routing

8. Click Connects Net(s).

Result: The net name selection is cleared, the net length values may be updated, and any
unrouted/partially-routed icons are removed for the nets that you just routed. The dialog
box remains open, ready for your next command.
9. To route additional nets on this board, repeat steps 4-8.
10. If you have loaded a MultiBoard project into BoardSim and want to route nets on
another board, repeat steps 2-9.
11. Click Close.
To undo a Manhattan routing operation, reload the board file to restore the routing that existed
prior to the Manhattan routing operation.

Saving and Restoring Session Edits for

Manhattan Routing
Manhattan routing data are stored in the BoardSim User Data (.BUD) file when you save your
BoardSim session edits. As you load a board with Manhattan routing, you can choose to restore
(or ignore) the Manhattan routing data in the .BUD file by selecting (or clearing) the Manhattan
Routes check box in the Restore Session Edits dialog box. See “Restore Session Edits Dialog
Box” on page 1838.

By contrast, unrouting changes are not saved in the .BUD file. For example, if you unroute a net
without re-routing it, the unrouting changes will be absent when you reload your board.

The Manhattan Routes check box is dimmed (i.e. unavailable) in the Restore Session Edits
unless the Stackup check box is selected. Because you can interactively add a stackup layer and
then use it for Manhattan routing, it is only safe to restore Manhattan routing when the stackup
session edits are also restored.

About Unrouting Nets

Unrouting a net in BoardSim is similar to lifting all the pins on the selected net(s) from the
board; BoardSim will ignore the physical routing parameter values stored in the board file for
the unrouted net during analysis.

Unrouted nets are not stored in the session edits file (BoardSim User Data .BUD). The original
routing will be restored the next time you load your board, unless you have rerouted the nets
using Manhattan Routing and saved your session edits.

Unrouting is performed automatically when you create Manhattan routing for a net. However,
to unroute a net and leave it unrouted for analysis, follow the steps described in the topic
“Unrouting Nets” on page 928. For example, unrouting might be useful during crosstalk

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Unrouting Nets

analysis to identify an aggressor net by unrouting it and seeing whether crosstalk on the victim
net persists.

Key points from the unrouting algorithm:

• Vias are deleted during the unrouting process and will not be displayed in the board
viewer for a selected unrouted net.
• Unrouting stops at a connector, if present on the selected net(s).
• For MultiBoard projects, unrouting is performed on one board at a time.

Related Topics
“Unroute Routed Nets Dialog Box” on page 934

“Unrouting Nets” on page 928

Unrouting Nets
BoardSim can unroute:

• Fully or partially routed nets

• Signal nets or power-supply nets
• In a MultiBoard project, nets on one board at a time (unrouting stops at the connector)
• Nets routed with Manhattan routing
When you create Manhattan routing for a net, BoardSim automatically unroutes the net before it
creates the Manhattan routing. Vias for the selected nets are deleted during the unrouting
process. See “Creating Manhattan Routing” on page 923 for the steps to re-route nets.

However, if you want to unroute a net and leave it unrouted for analysis, follow the steps
described in the topic “Unrouting Nets” on page 928. For example, unrouting might be useful
during crosstalk analysis to identify an aggressor net by unrouting it and seeing whether
crosstalk on the victim net persists.

For details about how unrouting affects simulation, see “About Unrouting Nets” on page 927.

If you highlight a net and then unroute it, the associated nets will continue to be displayed after
unrouting is complete. Clear the Include Associated Nets check box if you do not want to
highlight the unrouted net's associated nets, see “Highlight Net Dialog Box” on page 1641.

To undo an unrouting operation, you must reload the board file to restore the routing that
existed before the unrouting operation took place.

For the steps to unroute nets, and leave them unrouted, see the following topics:

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Unrouting Nets

• “Unroute Routed Nets Dialog Box” on page 934

• “Unrouting All Routed Nets - Except Power Supplies” on page 929
• “Unrouting Selected Nets or Selected Nets and Associated Nets” on page 929

Unrouting All Routed Nets - Except Power Supplies

BoardSim excludes power-supply nets when you choose to unroute all routed nets. You must
manually select the power-supply net to unroute it. See “Unrouting Selected Nets or Selected
Nets and Associated Nets” on page 929.

To unroute all nets (except power supplies):

1. Edit menu > Unroute Routed Nets.

2. For a MultiBoard project, select the board ID in the Design File list. Unrouting can be
performed for one board at a time.
3. Click All Nets (Except Power Supplies).
4. Click Unroute.
Result: All the non-power-supply net names are removed from the net name area. The
dialog box remains open, ready for your next command.
Power-Supply nets must be unrouted individually. See “Unrouting Selected Nets or
Selected Nets and Associated Nets” on page 929.
5. If you have loaded a MultiBoard project into BoardSim, repeat steps 2-4 as necessary
for each board.
6. Click Close.

Unrouting Selected Nets or Selected Nets and Associated

Nets
To unroute selected nets or selected nets and associated nets:

1. Edit menu > Unroute Routed Nets.

2. For a MultiBoard project, select the board ID in the Design File list. Unrouting can be
performed for one board at a time.
3. Click Selected Nets Only or Selected Nets and Associated Nets.
Nets can be conductively associated to other nets by passive components such as
resistors, or as differential pin pairs specified by an IBIS IO buffer model. See
“Associated Nets” on page 272.

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Viewing Manhattan Routing and Unrouted Nets

Use the Selected Nets Only option to unroute power-supply nets. Associated power-
supply nets are not unrouted when you select the Selected Nets and Associated Nets
radio button.
4. Select one or more nets.
See “The Nets to Connect with Manhattan Routing Area” on page 932 for net selection
tips.
5. Click Unroute.
Result: The selected net names (and associated net names, when appropriate) are
removed from the net name area. The dialog box remains open, ready for your next
command.
6. To unroute additional nets on this board, repeat steps 4-5.
7. If you have loaded a MultiBoard project into BoardSim, repeat steps 2-6 as necessary
for each board.
8. Click Close.

Viewing Manhattan Routing and Unrouted Nets

When you select a net that has been routed with Manhattan routing, it is displayed in the board
viewer as a series of dashed lines making point-to-point connections. The color of the selected
net corresponds to the stackup layer used by the Manhattan routing.

When you select a net that has been unrouted, and not re-routed with Manhattan routing, the
board viewer displays only the pins or pads associated with the net (recall that vias are deleted
when a net is unrouted). See “About Unrouting Nets” on page 927.

Reporting Manhattan Routing and Unrouting

Changes
Manhattan routing and unrouting changes are documented in the Design Change Summary
report. The report lists the names of the nets that have been routed with Manhattan routing or
unrouted.

To view a summary of Manhattan routing and routing changes:

1. Select Export > Reports > Design Change Summary.

2. Click Finish. The HyperLynx File Editor opens.
3. Press Ctrl+F. The Find dialog box opens.
Alternative: Select Edit > Find.

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 Simulating Unrouted Nets with Manhattan Routing
Connect Nets with Manhattan Routing Dialog Box

4. In the Find What box, type "CHANGED NETS".

The search is case sensitive if the Match Case check box is selected.
5. Click OK.

Connect Nets with Manhattan Routing Dialog

Box
Use the Connect Nets With Manhattan Routing dialog box to route an unrouted net with
Manhattan routing, or to unroute a routed net and then immediately re-route it with Manhattan
routing. This section introduces the layout of the dialog box and provides tips on using its
features.

See also: “Creating Manhattan Routing” on page 923, “About Manhattan Routing in
BoardSim” on page 922

If you have loaded a MultiBoard project into BoardSim, note that Manhattan routing is created
only for the selected board ID (i.e. Manhattan routing stops at the board's external connector).

You can open this dialog box after your board has been loaded, but it opens automatically at
board-load time when all of the following are true:

• The board contains any number of completely unrouted nets

• Manhattan routing information for the completely unrouted nets has not been saved to
the .BUD file, or restored from the .BUD file using the Restore Session Edits dialog box.
See “Restore Session Edits Dialog Box” on page 1838.
• You click "Yes" when BoardSim asks whether you want to create Manhattan routing at
board-load time
The dialog box is divided into two areas:

1. The area on the left, the Nets To Connect With Manhattan Routing area, is used to select
the nets that you want to route with Manhattan routing.
2. The area on the right, the Routing Criteria area, is used to specify the physical parameter
values (e.g., net length, trace width) for the Manhattan routing to be created for the
selected nets.

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Connect Nets with Manhattan Routing Dialog Box

The Nets to Connect with Manhattan Routing Area

Radio Button Selection Tips
Selecting one of the three radio buttons in the Connect Nets With Manhattan Routing area
determines which features are available in the Routing Criteria area. Features in the Routing
Criteria area are dimmed if they are not appropriate for the selected radio button.

For example, if you select the All Unrouted Nets radio button, the Specify Length radio button
in the Routing Criteria area is dimmed. This behavior prevents you from accidentally rerouting
your entire board with nets of the same length.

If you had really wanted to re-route your entire board with nets of the same length, you could
use the following workaround: Select the Selected Nets Only radio button, select all the nets in
the net name area above the Design File list, select the Specify Length radio button, and then
specify the Length value.

Net Selection Tips

The net name selection area (above the Design File list) is available when the Selected Nets
Only or Selected Nets And Associated Nets radio button is selected. Use the scrollbar to bring
net names outside the selection area into view.

Net name selection methods:

Table 19-1. Manhattan Routing - Net Selection Tips
Net name selection area mouse/keyboard Function
input
Click a net name Only that net is selected
Click a net name, then shift-click another net A contiguous block of nets is selected
name
Ctrl-click a net name Select the net and leave any previous net
selections intact

Icons in the Net Selection Area

Icons are used in the net name selection area to identify unrouted nets, partially routed nets, and
power-supply nets. The icons appear to the left of the net length and name information. Icons
are not displayed for routed nets (i.e., physically routed, or routed with Manhattan routing),
unless they are also power-supply nets.
Table 19-2. Manhattan Routing - Icons in Net Selection Area
Icon Description

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 Simulating Unrouted Nets with Manhattan Routing
Connect Nets with Manhattan Routing Dialog Box

Table 19-2. Manhattan Routing - Icons in Net Selection Area (cont.)

Unrouted net; the net has no routing segments.
Partially-routed net; the net has one or more routing segments but is not
completely routed.
Net status is unknown; the length and routing segment status are unknown for nets
that have not been cleaned. Select the net name to "clean" the net and display valid
net information.

For details about the clean-up of nets with redundant metal, see the “Remove
redundant metal from a board's nets as the board is loaded“ option in “Preferences
Dialog Box - BoardSim Tab” on page 1804.
Power-supply net.

The Design File List

If you have loaded a MultiBoard project into BoardSim, the Design File list is displayed below
the pin selection area. Use the Design File list to select the board on which you want to analyze
using Manhattan routing. Nets on only one board at a time may be re-routed using Manhattan
routing.

The Apply To All Similar Boards Check Box

The "Apply to all similar boards" check box is displayed only when a MultiBoard project has
been loaded into BoardSim. It is used to propagate your Manhattan routing selection to all
copies (i.e., instances) of that board in your MultiBoard project.

Its default value is "selected." Clearing the check box is not recommended unless you have read
“Saving Session Edits for Multiple Board Instances” on page 769. Clearing the "Apply to all
similar boards" check box does not persist. The check box will be selected the next time you
open the dialog box.

The Routing Criteria Area

The Routing Criteria area is used to specify the physical parameter values (e.g. routing length,
trace width, etc.) used by BoardSim to create Manhattan routing for the selected nets.

The set of features available (e.g. enabled) in this area is determined by the options you enable
in the Nets To Connect With Manhattan Routing area. See “Radio Button Selection Tips” on
page 932.

For an explanation for "Manhattan multiplier," and its effects on the Manhattan routing's
simulation length, see “How Simulation Length for Manhattan Routing is Calculated” on
page 923.

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Unroute Routed Nets Dialog Box

Related Topics
“Simulating Unrouted Nets with Manhattan Routing” on page 921

Unroute Routed Nets Dialog Box

Use the Unroute Routed Nets dialog box to unroute a routed net, partially routed net, or a net
routed with Manhattan routing. The Nets To Unroute area is used to select the nets that you
want to unroute. The appearance and functionality of the Nets to Unroute area is identical to the
Nets to Connect with Manhattan Routing area in the Connect Nets with Manhattan Routing
dialog box. See “The Nets to Connect with Manhattan Routing Area” on page 932 for more
information.

For the steps to unroute routed nets, see “Unrouting All Routed Nets - Except Power Supplies”
on page 929 and “Unrouting Selected Nets or Selected Nets and Associated Nets” on page 929.

For a description of how unrouting works in BoardSim, “About Unrouting Nets” on page 927.

Related Topics
“Simulating Unrouted Nets with Manhattan Routing” on page 921

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 Chapter 20
Terminating Nets

One of your key weapons in fighting poor signal quality and EMC problems (and sometimes
even crosstalk) is terminators. Among BoardSim’s primary benefits is helping you to find
proper termination schemes for the "problem" nets on your boards.

BoardSim offers several major features directed specifically at termination:

• The ability to interactively change the values of the terminating components on your
board and re-simulate with them, until you are satisfied with your waveforms
• The Terminator Wizard, a "smart" tool which automatically recommends optimal
terminating-component values
• Quick Terminators, a feature which allows you to add "virtual" terminating components
that are not actually present in your PCB layout
• The Design Change Summary, a convenient report summarizing the terminating-
component changes you’ve made
This topic contains the following:

• “About Quick Terminators” on page 935

• “Adding a Quick Terminator” on page 936
• “Editing Quick Terminator Values” on page 938
• “Removing a Quick Terminator” on page 941
• “Removing the Effect of a Real Terminator to Try a Quick Terminator” on page 942
• “Keeping a Record of Quick Terminators” on page 942

Related Topics
“Optimizing Termination with the Terminator Wizard” on page 945

“Interactively Editing Rs - Ls - Cs” on page 319

About Quick Terminators

BoardSim’s "Quick Terminator" feature allows you to add to your board terminating
components (resistors and capacitors) that are not actually present in the board's layout. This
allows you to experiment with terminations not currently in your design.

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Adding a Quick Terminator

When to Use Quick Terminators

Quick Terminators are useful whenever you find a signal-integrity or EMC problem on a net
that is unterminated, and you want to see if termination fixes the problem. You can also use
Quick Terminators to experiment with different termination types on nets that are already
terminated with another type (e.g., a DC parallel terminator whose effects you don’t like, so you
want to try series termination instead).

The Terminator Wizard also uses Quick Terminators, in two ways. First, if one or more Quick
Terminators are present on a net, then the Wizard treats them exactly like "real" components,
recommending values for them, etc. Second, if a net is unterminated but the Wizard is
recommending a termination, it uses Quick Terminators (when you click the Apply Value
button) to create the necessary components.

Quick Terminators and EMC Simulations

You can add a Quick Terminator to a net for which you are running EMC simulations, to see
whether adding the terminator to your board would improve the net's radiation profile.
However, be aware that unlike real passive components (components that are actually included
in your layout), Quick Terminators do not contribute any package radiation to the spectrum
analyzer's results. This occurs because BoardSim EMC does not have any information about a
Quick Terminator's physical package or its orientation on your board.

Requirement: The BoardSim EMC license is required to run EMC simulation.

Quick Terminators and the Terminator Wizard

The Terminator Wizard works with Quick Terminators just like it does with real terminators.
This means you can add a Quick Terminator, then run the Terminator Wizard to get
recommended component value(s) for it. The Terminator Wizard also uses Quick Terminators
to create terminations it is recommending on nets that are unterminated in your board’s actual
layout.

See also: “Optimizing Termination with the Terminator Wizard” on page 945

Adding a Quick Terminator

You can add terminating components to the currently selected net and its associated nets. You
can add components regardless of what other components are already present on the net.

This topic contains the following:

• “Where Quick Terminators Can be Placed” on page 937

• “Types of Quick Terminators” on page 937

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 Terminating Nets
Adding a Quick Terminator

• “Adding Quick Terminators” on page 937

Where Quick Terminators Can be Placed

You can add Quick Terminators at any IC pin on the net. This gives you the flexibility to place
a resistor at a driver IC (series termination), a resistor and capacitor at the last receiver IC (AC
parallel termination), and so forth.

You can add terminators at as many IC pins as you like. For example, if a net has two branches
and you want to parallel terminate at the end of each branch, you can place terminators at the
two last-IC positions.

In addition, for series resistor terminators and differential resistors, you can specify a stub
length distance from the driver IC. For information, see “Series or Differential Resistor Stub”
on page 939.

Restriction: Quick Terminators cannot be placed inside an .EBD model.

Types of Quick Terminators

Quick Terminators support the following termination types:

• Series resistor (with one stub transmission line)

• Single parallel DC resistor
• Pull-up / pull-down parallel DC resistors
• Parallel AC termination (resistor + capacitor)
• Parallel capacitor
A parallel capacitor is an unusual choice for termination, but is occasionally used, for
example at a driver IC as a way of slowing down the driver’s output.
• Differential resistor (with two stub transmission lines)
The Quick Terminator feature does not support ferrite beads.

Adding Quick Terminators

To add a Quick Terminator:

1. Do any of the following:

• Models menu > Assign Quick Terminator.
• Add Quick Terminator button .

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Terminating Nets
Editing Quick Terminator Values

• In the board viewer, right-click over a pin on the selected net, and then click Add
Quick Terminator.
Result: The Assign Models dialog box opens, with the Quick Terminator tab selected.
2. In the Quick Terminator Location list, select the IC pin at which you want to add a
terminator.
3. In the Terminator Style area, select the terminator type you want to add.
Result: A picture of the terminator appears to the left, and boxes for the terminator's
component values appear below. A small resistor icon appears next to the selected pin in
the Quick Terminator Location list.
4. In the Terminator Values area, type or select the component values.
The new values are shown in the picture. For parallel DC terminators, the values include
selectable pull-up and pull-down voltages.
5. If you selected R differential in the Terminator Style area, make sure the name of the
second pin of the differential pair is displayed in the Opposite Pin box. If the pin name is
incorrect or absent, do one of the following:
• In the Opposite Pin box, type the opposite pin's <reference designator>.<pin> value,
for example, U1.5.
• Click Browse, select the other pin using the Select Second Pin dialog box, and then
click OK.
6. To add a terminator to another pin, repeat steps 2-5.
7. Click Close or click another tab at the top of the Assign Models dialog box, to edit other
kinds of models.
The Quick Terminator resistor icon appears in the Pins list next to the pin with the terminator, as
a reminder that a Quick Terminator has been applied. This icon is visible regardless of which
Assign Models tab has been clicked (IC, Resistor, etc.).

Related Topics
“Editing Quick Terminator Values” on page 938

Editing Quick Terminator Values

To edit the value of a Quick Terminator:

1. Do any of the following:

• Models menu > Assign Quick Terminator.
• Add Quick Terminator button .

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Editing Quick Terminator Values

• In the board viewer, right-click over a pin on the selected net, and then click Add
Quick Terminator.
Result: The Assign Models dialog box opens, with the Quick Terminator tab selected.
2. In the Quick Terminator Location list, select the IC pin whose Quick Terminator values
you want to change.
3. In the Terminator Values area, type new values in the appropriate boxes, and then click
Close.
The component values for each Quick Terminator type are listed below:

• Series resistor—resistance, stub layer, stub length, stub width. For details, see “Series or
Differential Resistor Stub” on page 939.
• Parallel AC (R+C)—resistance, capacitance
• Parallel DC resistor—resistance, pull-up or pull-down voltage
• Parallel split DC resistor—pull-up resistance, pull-up voltage, pull-down resistance,
pull-down voltage
• Parallel capacitor—capacitance
• Differential resistor—resistance, stub layer, stub length, stub width, opposite pin name.
For details, see “Series or Differential Resistor Stub” on page 939.

Single DC Resistor can be Pull-up or Pull-down

The single, parallel DC resistor Quick Terminator is drawn as a pull-up resistor, but since the
voltage to which it is tied can be set to any value (e.g., 5V, or 3.3V, or 0.0V, etc.), this
terminator can really be either a pull-up or pull-down. For example, if you tie the resistor to
Vcc, it is a pull-up; if you tie it to 0.0V, it becomes a pull-down.

Series or Differential Resistor Stub

If you add a series-resistor Quick Terminator or a differential resistor Quick Terminator, you
can also specify what kind of interconnect separates the resistor from the driver or receiver IC.
This interconnection is called the series-resistor or differential resistor "stub."

The stub allows you to see what effect separating a resistor from the IC has on the effectiveness
of the terminator. In any real PCB layout, the resistor cannot be exactly at the IC, as it ideally
would. Varying the stub length shows you how far away the resistor can be before the
terminator begins to fail.

Generally, the maximum allowable stub length depends on the switching speed of the driver IC.
For slow-switching ICs, a long stub is acceptable; for faster-switching ICs, the maximum-
allowable stub length shrinks.

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Editing Quick Terminator Values

Specifying Series-Resistor Stub Values

To specify the series-resistor stub interconnect:

1. Add a series-resistor Quick Terminator (see “Adding a Quick Terminator” on page 936
for details).
2. In the Terminator values area, on the Layer list, select the stackup layer for the stub.
3. Type values in the Length and Width boxes.

Specifying Differential Resistor Stub Values

This is a two-step process; first you specify stub values for the selected pin and then you specify
stub values for the opposite pin. The selected and opposite pins represent the differential pins
terminated by the differential resistor.

To specify the differential resistor stub values:

1. Add a differential resistor Quick Terminator (see“Adding a Quick Terminator” on

page 936 for details).
2. In the Terminator values area, on the Layer list, select the stackup layer for the stub.
The upper half of the diagram shows stub values for the selected pin and the lower half
of the diagram shows the stub values for the opposite pin, if the opposite pin has been
defined.
3. Type values in the Length and Width boxes.
4. To identify the opposite pin, do one of the following:
• In the Opposite Pin box, type the opposite pin's <reference designator>.<pin> value,
for example, U1.5.
• Click Browse, select the other pin using the Select Second Pin dialog box, and then
click OK.
5. To specify the resistor stub values for the opposite pin, select the opposite pin from the
Quick-terminator location list and repeat steps 2-3.

Default Stub Values

The layers in the Layer list match those in your board’s stackup. To view the stackup or edit it,
use the stackup editor.

The stub parameters default as follows:

• Layer—to whatever layer the actual trace touching the IC pin is on

• Length—to a default short distance

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Removing a Quick Terminator

• Width—to the width of the actual trace that touches the IC pin
Because the stub layer and width default to match the layer and width of the portion of your
board’s actual routing that touches the IC, you usually do not need to change layer and width.

The units used for stub length and width default to those used for measuring lengths everywhere
on your board.

See also: “Setting Measurement Units” on page 401

Stub Adds to Existing Routing

BoardSim simulates the stub by adding a transmission line between the IC and the existing
routing on your board. This method is used for simplicity; it avoids the complexity of forcing
you to specify how to break apart your existing routing to insert the series resistor.

Related Topics
“Quick Terminators and EMC Simulations” on page 936

Removing a Quick Terminator

To remove a Quick Terminator:

1. Do any of the following:

• Add Quick Terminator button .
• Models menu > Assign Quick Terminator.
• In the board viewer, right-click over a pin on the selected net, and then click Add
Quick Terminator.
Result: The Assign Models dialog box opens, with the Quick Terminator tab selected.
2. In the Quick Terminator Location list, select the IC pin whose Quick Terminator you
want to remove.
3. In the Terminator Style area click None.
4. Click Close.
Result: The terminator's effect in subsequent simulations is removed. Also, the Quick
Terminator resistor icon disappears from the Pins list in the Assign Models dialog box.

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Removing the Effect of a Real Terminator to Try a Quick Terminator

Removing the Effect of a Real Terminator to Try

a Quick Terminator
Sometimes, you may want to replace a real terminator (one physically present on your PCB)
with a Quick Terminator. For example, you might want to remove a DC parallel terminator on
your board whose effects you don’t like, and try a Quick Terminator series resistor instead.

To do this, use the Assign Models dialog box to change the real terminator's component values
such that the terminator no longer has any effect in the circuit. (For details on editing
component values, see “Interactively Editing Rs - Ls - Cs” on page 319.) Then, add the Quick
Terminator as described in “Adding a Quick Terminator” on page 936.

Example values to use for "removing" a real terminator:

• Parallel DC resistor 1000 ohms or greater

• Parallel AC terminator 1000 ohms or greater and 0 pF
• Series resistor 0 ohms

Keeping a Record of Quick Terminators

As you find unterminated nets that need termination and "fix" them by adding Quick
Terminators in BoardSim, you may want to keep a record of the new terminators that should be
added to your board layout. For example, a list of Quick Terminators might be useful for
handing back to your PCB-layout department or service bureau, so they can incorporate the new
terminators into a new board revision.

Quick Terminators and the Design Change Summary

BoardSim can create a special report called the "Design Change Summary" which records,
among other items, the Quick Terminators you add to your board and their component values.

See also: “Reporting Design Changes” on page 338

To create a Design Change Summary, which includes a list of Quick Terminators:

1. Export menu > Reports > Design Change Summary.

2. Click Finish.
Result: The HyperLynx File Viewer opens to show the contents of the Design Change
Summary. The report is written to a file called <board_file_name>.TXT, where
<board_file_name> is the name of board file.

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Keeping a Record of Quick Terminators

Selecting Second Pin for Differential Quick Terminator

Use the Select Second Pin dialog box to select the opposite pin for a differential Quick
Terminator.

To select the second pin for differential Quick Terminator:

1. In the Reference Designators list, select the reference designator of the component
connected to the second pin.
2. In the Pin Names list, select the name of the second pin, and then click OK.
Alternative: Double-click the pin name.
Result: The reference designator and pin name information appears in the Opposite Pin
box in the Quick Terminator tab on the Assign Models dialog box.

Related Topics
“Adding a Quick Terminator” on page 936

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Keeping a Record of Quick Terminators

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 Optimizing Termination with the Terminator Wizard
About the Terminator Wizard

Chapter 21
Optimizing Termination with the Terminator
Wizard

Use the Terminator Wizard to help improve signal integrity and EMC properties for nets by
finding optimal termination component values.

This topic contains the following:

• “About the Terminator Wizard” on page 945

• “Terminator Wizard Limitations” on page 946
• “Running the Terminator Wizard” on page 950
• “Terminator Wizard Results” on page 951
• “Running the Terminator Wizard on the Entire Board” on page 961

Related Topics
“About Quick Terminators”

About the Terminator Wizard

BoardSim/LineSim includes a "smart" Terminator Wizard to help you find optimal values for
the terminating components on your boards (BoardSim) or in your schematics (LineSim).
"Terminating components" include resistors and capacitors, both series and parallel; "optimal
values" means resistances and capacitances that give the best waveforms from a signal-integrity
and EMC standpoint. In BoardSim, the Terminator Wizard can also work with Quick
Terminators ("virtual terminators" that BoardSim allows you to place on a net that doesn’t have
any termination in its actual layout; see “About Quick Terminators” for details), and with nets
that have multiple terminators in their layout.

Terminated Versus Unterminated Nets

You can run the Terminator Wizard interactively, any time you choose, on the currently
selected net and its associated nets (in BoardSim) or on the current schematic (in LineSim). The
Wizard works in one of two ways depending on whether the net it’s running on is terminated or
not.

If the net is terminated already, the Wizard bases its analysis on the terminating components
present on the net, suggesting, if possible, optimal component values. The terminating

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Terminator Wizard Limitations

components can be actual components present in your board’s layout, or Quick Terminators
added in BoardSim. This feature works on any net with a single termination type (e.g., AC or
series), and with a number of useful topologies involving multiple terminators.

See also: “About Quick Terminators”, “Results for Nets with Multiple Terminators” on
page 954

If the net is not terminated, and the Wizard thinks the net is too long to be unterminated, the
Wizard will attempt to suggest a termination strategy—both a type of termination and optimal
component value(s).

Terminator Wizard Limitations

The models, topology, and termination type of a net determine Terminator Wizard limitations.

This topic contains the following:

• “Terminator Wizard Unavailability” on page 946

• “Differential Line-to-Line Termination” on page 946
• “No Placement Checks for Differential Terminators” on page 947
• “Some Combinations of Multiple Terminators Not Supported” on page 948
• “Multiple Drivers Not Supported - Except for Differential IBIS Models” on page 948
• “Ferrite Beads Not Supported” on page 948
• “How the Wizard Recognizes Branched Topologies” on page 948
• “Recognizing Terminator Types” on page 948
• “Terminator Wizard Requires Driver IC Model” on page 949
• “Supported Termination Types and Net Topologies” on page 949

Terminator Wizard Unavailability

The Terminator Wizard is not available in BoardSim when a MultiBoard project is loaded, or
when you select a net containing a pin with an .EBD model assigned to it.

The Terminator Wizard is not available in LineSim whenever an .EBD model has been assigned
to the schematic.

Differential Line-to-Line Termination

The Terminator Wizard recognizes differential termination when the circuit meets all of the
following conditions:

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 Optimizing Termination with the Terminator Wizard
Terminator Wizard Limitations

• The selected net and the other net are connected to driver pins in an IBIS model.
And
• A [DIFF PAIR] keyword in the IBIS model associates the driver pin on the selected net
to the driver pin on the other net.
And
• A resistor directly connects the selected net to the other net. The resistor can be native to
the design or added to the design as a differential resistor Quick Terminator.
Or
The selected net and the other net connect to driver pins with the same reference
designator.
For LineSim, you can use the Assign Models dialog box to assign a reference designator
and pin name to the driver ICs.
See also: “Selecting Models Using the REF File”
Requirement: The Crosstalk license is required to use this feature.

Generally, the Wizard does not support nets (or groups of nets) with multiple drivers present.
However, since differential pairs require two drivers for proper circuit operation, an exception is
made for them when the differential nets are connected in one of the circuit configurations listed
above.

To predict an optimal value for such a terminator, the Wizard needs access to
LineSim/BoardSim Crosstalk’s field solver. Accordingly, recommendations for differential-
terminator values are available only if you are licensed for Crosstalk analysis.

Restriction: .MOD and .PML models do not support the concept of differential pin pairs. IBIS
models do; the Terminator Wizard automatically identifies differential pairs that use differential
IBIS IC models.

No Placement Checks for Differential Terminators

The current version of the Terminator Wizard does not check for proper positioning of a
differential terminator, e.g., whether a line-to-line terminator has excessive stub length or is
otherwise mis-placed. Use interactive simulation to gauge the effectiveness of a differential
terminator’s location.

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Terminator Wizard Limitations

Some Combinations of Multiple Terminators Not

Supported
The Wizard also does not support some complex termination schemes based on multiple
terminators. See “Supported Termination Types and Net Topologies” on page 949 any
combinations not specifically described in the table are probably not supported.

In situations where the Wizard cannot recognize a complex termination type, use interactive
simulation instead of the Wizard to choose optimal component values.

Multiple Drivers Not Supported - Except for Differential

IBIS Models
Except for the case of a trace pair driven by an IBIS differential IC model, the Wizard will also
not analyze any net that has more than one driver actively selected. In order to analyze such a
net (provided it is not differential), change all but one of the drivers into a receiver (or remove
the other driver models entirely).

Ferrite Beads Not Supported

The Wizard does not support ferrite-bead terminators. Use interactive simulation to find an
optimal ferrite bead.

See also: “Selecting Ferrite-Bead Models in BoardSim” on page 526

How the Wizard Recognizes Branched Topologies

The Wizard supports termination schemes in which a "star-routed" net has each of its branches
terminated by a separate series resistor. However, in order to recognize such a topology and
make useful component-value recommendations for it, the Wizard must be able to
automatically judge whether a given net is actually routed as a valid star.

To make a topological judgment about star routing, the Wizard uses a path-tracing algorithm. If
a net has multiple series resistors, it is considered to be a valid star route only if one end of each
resistor traces back only to the driver IC, and the other end traces only to receiver ICs.

Recognizing Terminator Types

If there is a driver IC present on the net being analyzed, the Terminator Wizard performs an
analysis to determine how the net is terminated, and to find the optimal terminating-component
values.

See also: “Terminator Wizard Requires Driver IC Model” on page 949

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Terminator Wizard Limitations

If there are terminating components present on the net, the analysis can succeed only if the
Wizard is able to automatically determine from the components (either "real" or BoardSim
Quick Terminators) what type of termination you are using (e.g., series resistor or AC parallel).
To determine the termination type, the Wizard examines:

• What resistor and capacitor components are present

• What nets are connected to each component (e.g., two signal nets or a signal net and an
AC ground?)
• Where the components are placed, especially relative to the driver IC
• Other topological details of the net’s routing
If the termination type can be identified, the result is displayed in the Terminator Analysis area,
in the Termination Type field. If the type cannot be identified, the Termination Type is left as
"unknown" (red question mark) and a warning appears in the Messages area; the Wizard then
cannot make a recommendation on component values.

Terminator Wizard Requires Driver IC Model

In order for the Terminator Wizard to run a complete analysis and recommend component
values, you must have a model selected for the driver IC on the current net. The presence of a
driver model is critical because many of the driver’s properties have a profound effect on
terminating-component values. Important driver properties include:

• Slew time
• Output impedance
• Physical position on the net
If you run the Wizard without a driver model selected, LineSim/BoardSim gives a warning in
the Messages area; even if a termination is present on the net, the Wizard lists the Termination
Type as "unknown" (with a red question mark). Some of the statistics about the net are
displayed, but no recommendation is made for terminating-component values.

Supported Termination Types and Net Topologies

If the Terminator Wizard finds terminating components already on the net being analyzed (any
mixture of "real" components and Quick Terminators), it attempts to identify the termination
type and determine optimum values for the components. Table 21-1 lists the termination types
currently recognized by the Terminator Wizard. See the topics following the table for additional
details.

Table 21-1. Terminator Wizard - Supported Terminations and Net Topologies

Termination/topology type Comments

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Running the Terminator Wizard

Table 21-1. Terminator Wizard - Supported Terminations and Net Topologies

Single series R

Single DC parallel R (pull-up or pull-

down)

Single DC parallel pull-up/pull-down

combination

Single AC parallel R+C

Multiple series Rs, each terminating one "Star" route means a topology in which an
branch of a "star" route IC drives multiple trace branches in
parallel, with the branch point close to the
driver
Multiple parallel terminators, of any "Any mixture of types" means any mix of
mixture of types DC parallel R, DC parallel pull-up/pull-
down combo, and AC parallel R+C
Single series R + multiple parallel The Wizard cannot recognize series R +
terminators of the same type multiple parallel terminators of differing
types (e.g., one pull-up R + one AC
terminator)
Differential trace-to-trace R, if the two Values are recommended in BoardSim
traces are driven by an IBIS differential IC Crosstalk only
model or by the differential resistor Quick
Terminator See also: “Differential Line-to-Line
Termination” on page 946

Running the Terminator Wizard

Use the Terminator Wizard dialog box display information about current and recommended
termination for a net. You can also apply the recommend termination, using Quick Terminators,
from this dialog box.

To run the Terminator Wizard:

1. Verify that a driver model has been chosen for the net you want analyzed.
See also: “Terminator Wizard Requires Driver IC Model” on page 949
2. Simulate SI menu > Optimize Termination.
Alternative: On the toolbar, click Run Terminator Wizard.
3. In LineSim only, if there are multiple nets in the schematic, the Select Net for
Terminator Wizard dialog box opens. In the Select a Device Pin list, double-click on an
IC pin attached to the net you want to analyze. The dialog box closes.

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Terminator Wizard Results

See also: “About Multiple Nets in LineSim” on page 951

4. The Terminator Wizard dialog box opens and displays results in the Terminator
Analysis area.
If you are running BoardSim, the analysis is for the selected net and any nets attached
directly to it through series components (or a set of differential pins on a driving IC). If
you are running LineSim, the analysis is for the current schematic.
5. To specify component tolerance, select the tolerance from the Apply Tolerance list.
By default, the Terminator Wizard calculates exact terminating-component values,
without regard for the values you could actually purchase and install on a board.

About Multiple Nets in LineSim

Nets in a LineSim schematic are not explicitly named. However, internally, as you draw a
schematic, LineSim keeps track of whether there is one or multiple nets in your drawing. There
are two conditions that cause multiple nets to exist:

• You’ve drawn two or more completely independent circuits; each is completely isolated
conductively from the other(s)
• You’ve drawn one circuit, but it contains one or more series components that cause the
circuit to be divided into multiple nets
If the schematic contains multiple nets then, before presenting its analysis, the Wizard opens a
dialog box asking which net to analyze. You choose the net by selecting an IC pin that’s on the
net.

If the schematic contains only one net, then the Wizard’s analysis is immediate (no need to
choose an IC pin).

Related Topics
“Terminator Wizard Results” on page 951

“Optimizing Termination with the Terminator Wizard” on page 945

Terminator Wizard Results

This topic contains the following:

• “Results Overview” on page 952

• “Component Values and Recommendations” on page 952
• “Signal-Integrity Checks and Warnings” on page 958

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Terminator Wizard Results

• “Pin-to-Pin Physical Lengths” on page 960

Results Overview
When you run the Terminator Wizard, its analysis results include information about:

• What components were found on the net(s)

• The electrical characteristics of the net’s driver IC (driving impedance and slew time)
• The physical and electrical characteristics of the net(s) (total length, nominal impedance,
and "effective" impedance including IC-loading effects)
If the net has any terminating components, the Wizard also displays:

• What kind of termination it found (e.g., series or parallel AC)

• Recommendations for optimal termination values
• Information about the physical placement of the terminating components
• Warnings about any component values that seem problematic
• Warnings about any component placements that seem problematic
If the net does not have any terminating components, and the Wizard believes the net is too long
to be unterminated, the Wizard displays:

• What kind of termination it recommends

• Recommendations for optimal termination values
The component-value recommendations and the recommended "best" termination type (at the
bottom of the Terminator Analysis area) are the Wizard’s most-important benefit. The Wizard’s
warnings about improper component values and placement are also very useful.

See also: “Component Values and Recommendations” on page 952, “Signal-Integrity Checks
and Warnings” on page 958

At the bottom of the dialog box, in the Messages area, the Wizard displays warning/error
messages and hints about improving the net’s signal quality. See the following topics for details
on what kinds of messages may appear.

Component Values and Recommendations

For a terminated net, the optimal component values are often not trivial to find, particularly
since the loading effect of IC capacitances effectively alters a net’s characteristic impedance.
The Terminator Wizard accounts for all of the IC models currently on the net and its associated
nets, factoring the models’ capacitances into an effective characteristic-impedance calculation.

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Terminator Wizard Results

This topic contains the following:

• “Effective Z0 Value” on page 953

• “Results for Nets with Single Terminators” on page 953
• “Results for Nets with Multiple Terminators” on page 954
• “Results for Nets With No Terminators” on page 956
• “Results for Nets Inside EBD Models” on page 958

Effective Z0 Value
One of the net-statistic values that the Wizard displays is Effective Z0. The "effective Z0" is a
figure that attempts to show by how much the selected net’s actual characteristic impedance is
effectively lowered by the presence of IC capacitance along the net and associated nets. This
value can be used as a guide when choosing termination resistances, since for nets that are
significantly loaded by IC capacitance, the proper termination value is almost always lower than
suggested by the net’s actual Z0.

Results for Nets with Single Terminators

For nets with a single terminator already in place (composed either of "real" component(s) or a
Quick Terminator), the Wizard attempts to identify the termination type; if the identification
succeeds, then the Wizard calculates an optimal value for the terminating component(s).

Recommended Terminating-Component Values

The Terminator Wizard displays its recommended resistor and/or capacitor values at the bottom
of the Terminator Analysis area. If the currently selected net uses series or DC parallel
termination, only one or more resistor values are recommended; if it uses AC parallel
termination, resistor and capacitor values are suggested.

If there are multiple resistors or capacitors on a net, then the Wizard’s recommended values are
identified per-component in the following manner:

<component_type> <reference_designator.pin> suggested: <value>

where <component_type> is the type of component ("resistor" or "capacitor");

<reference_designator.pin> specifies the component’s reference designator and a pin on the
component; and <value> is the recommended value.

If you make changes to the net being analyzed—for example, change any of its IC models or
alter the board’s or schematic’s stackup—re-run the Wizard to see how the recommended
termination values may have changed in response. The series-resistor value, for example, is
strongly dependent on your current choice of driver IC.

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Terminator Wizard Results

Applying Recommended Termination Values

If the Terminator Wizard recommends resistor and/or capacitor values for a terminated net, you
can easily apply the recommended values to the components on your board (or to a Quick
Terminator), then re-simulate to see the resulting waveforms.

To apply component values recommended by the Terminator Wizard to the components on your
board or a BoardSim Quick Terminator:

1. Run the Terminator Wizard. Verify that the Wizard is able to identify the termination
type, and recommends component values.
See also: “Running the Terminator Wizard” on page 950
2. Click Apply Values.
The recommended component values are exported to the components on your board (or to the
BoardSim Quick Terminator components you’ve added).

To re-simulate using the recommended values:

1. Click OK to close the Terminator Wizard.

2. Open the oscilloscope, and re-simulate.

Results for Nets with Multiple Terminators

If a net has multiple terminators, the Wizard behaves similarly to how it does when only a single
terminator is present. However, there is now an additional challenge: the Wizard must also
determine which of the terminating strategies it thinks is best, and give you a way to get
recommended values for whichever type you prefer to use.

See also: “Results for Nets with Single Terminators” on page 953

Reasons to Use Multiple Terminators

Why use multiple terminator types on a single net? If you have enough time before layout to
analyze your critical nets with HyperLynx’s tools, there should be no need to do this. However,
some designers, under heavy pressure to get a PCB into layout and "figure the details out later,
in parallel" resort to the strategy of placing multiple terminators on critical nets, then deciding
later, after layout, which terminating components to actually stuff.

Restriction: This capability is available only in BoardSim.

Choosing Between Multiple Terminators

When you run the Wizard on a net with multiple terminators, the Wizard first examines the net
to see if the multiple-component configuration is one that it can identify and "understand."

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Terminator Wizard Results

See also: “Running the Terminator Wizard” on page 950, “Supported Termination Types and
Net Topologies” on page 949

If the terminating scheme is successfully identified, the Wizard displays the combination of
components in the Termination Type field, in the Terminator Analysis area (e.g., "series, AC,
pull-up"). If not, the Wizard marks the Termination Type with a red question mark, and cannot
proceed with analysis.

Assuming the Type has been correctly identified, the Wizard then displays in the Preferred
Choice area (on the right side of the dialog box) a set of radio buttons that normally (with
single-terminator or unterminated nets) is not displayed. The buttons offer several choices for
which terminator type to recommend values for: "Best" (meaning let the Wizard choose what it
thinks is the most-optimal of the terminator types it found on the net), and two or more
selections that specify exactly which terminator type to use.

For example, if a net has three terminators in its layout, series, AC parallel, and DC pull-up, the
Wizard will:

• Identify the net as having terminator type "Series, AC, pull-up"

• Present radio buttons in the Preferred Choice box for:
o Best (= let the Wizard recommend the best termination type to use)
o Series Termination (= force analysis of the series terminator)
o AC Termination (= force analysis of the AC terminator)
o DC Termination (= force analysis of the DC pull-up terminator)
To tell the Terminator Wizard on which type of terminator you want analysis:

• In the Preferred Choice area, select the appropriate terminator.

After you make your choice, the Wizard immediately shows its recommended value for that
termination type. If you choose "Best," the Wizard will make a recommendation for the
terminator type it thinks will best suit your net; the Wizard’s choice is listed in the Terminator
Analysis area as the "Suggested Termination."

When you select a new net for analysis, the Wizard does not save your choice of preferred
terminator type for the previous net. If you return to the previous net to analyze it again, you
must re-choose your preferred type.

Simulating With a Particular Terminator

To simulate with a particular terminator that you chose (or the Wizard recommended) during
analysis:

• In the Termination Suggestions area, click Apply Values.

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Terminator Wizard Results

The recommended termination values are automatically placed in your circuit. You can now
close the Wizard and open the oscilloscope or spectrum analyzer to simulate and see an actual
waveform.

How Unused Termination Components Are Treated

When you set the component values of your preferred type of terminator using the Apply
Values buttons, the Wizard must also set the values for the "unused" terminating components in
such a way that they do not interfere with the simulation of the preferred terminator. This is
accomplished as follows:

• Unused series resistors are set to 0.0 ohms

• In an unused AC terminator, the resistor value is set to 1 Mohm
(the capacitor is unchanged)
• In an unused DC pull-up/down terminator, the resistor value is set to
1 Mohm

Results for Nets With No Terminators

If you run the Terminator Wizard on a net that has no terminating components, the Wizard first
runs an analysis to determine if the net’s signal integrity is likely to be acceptable without
termination.

If the Wizard believes that the net does not need termination, then in the Terminator Analysis
area, the Termination Type is set to "No termination found"; no termination is suggested; and
Apply Values button is grayed out.

On the other hand, if the Wizard concludes that the net is too long to be left unterminated, it will
attempt to recommend a termination type, and optimal values for the terminator’s components.
The algorithms used to determine the optimal terminator type are complex; they take into
account the positions of driver and receiver ICs along the net, the topology of the net’s routing
(e.g., daisy-chained versus star-routed), comparison of driver versus net impedance, etc. Part of
the process of recommending a terminator is to also recommend its position on the net, since
location is often just as important as component values.

For nets with complex routing schemes (e.g., complicated, "non-obvious" branching), the
Wizard can sometimes not find an optimal termination scheme. (You may not be able to either.)
Generally, The Terminator Wizard works best on nets that are single-receiver, or daisy-chained,
or cleanly star-routed ("cleanly" meaning "with clearly identifiable branches").

Applying Recommended Terminators in BoardSim

If the Terminator Wizard recommends a terminator for an unterminated net, you can easily
create the terminator and apply the recommended values to the components, then re-simulate to
see the resulting waveforms. The new terminator will be created as a Quick Terminator.

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Terminator Wizard Results

To create a recommended terminator as a Quick Terminator, and apply the Wizard’s suggested
values:

1. Run the Terminator Wizard. Verify that the Wizard thinks the net needs termination, and
recommends a terminator type and component values.
See also: “Running the Terminator Wizard” on page 950
2. Click Apply Values.
The recommended terminator is created automatically as a Quick Terminator, and the Wizard’s
suggested component values are exported to the terminator.

To re-simulate using the new terminator:

1. Click OK to close the Terminator Wizard.

2. Open the oscilloscope, and re-simulate.

Manually Adding Terminators to Unterminated Nets

If a net on your board has no terminator, and you want to experiment manually with adding one
(rather than automatically creating one based on the Terminator Wizard’s recommendation),
add your own terminating components wherever desired using the Quick Terminator feature.
Then run the Wizard to get component-value recommendations, and the oscilloscope to see the
effectiveness of the termination.

Applying Recommended Terminators in LineSim

The Terminator Wizard cannot automatically modify a schematic to implement a terminator
recommended for an unterminated net. Instead, you need to add the recommended components
yourself, manually.

To try a terminator recommended by the Wizard for an unterminated net:

1. Note the terminator recommended by the Wizard. Then click OK to close the Wizard
dialog box.
2. In the schematic, add the component(s) recommended by the Wizard.
3. Re-open the Terminator Wizard.
4. Click Apply Values. The recommended value(s) are written into the component(s) you
just added.
5. Click OK to close the Wizard. Proceed with simulation.

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Terminator Wizard Results

Results for Nets Inside EBD Models

The Terminator Wizard can recommend quick terminators for nets inside an .EBD model. Nets
inside an .EBD model will have an "EBD" prefix. If you are developing an .EBD model, you
can use this information to modify your .EBD model to accommodate the board being
simulated. If you are using an .EBD file from a vendor, you may try to place a terminator at the
.EBD connector.

Signal-Integrity Checks and Warnings

In addition to recommending component values and types, the Terminator Wizard
automatically runs various signal-integrity checks against the currently selected net. If a
violation is found, it is reported in a red font in the Terminator Analysis area, usually in the
messages sub-area.

The checks fall into two broad categories: searching for problematic component values (e.g.,
resistors that are too large or small), and searching for problematic component placement (e.g.,
a series resistor located too far from the driver it terminates).

Table 21-2 lists the signal-integrity checks currently run by the Terminator Wizard. Following
topics (see list below) provide additional details.

Table 21-2. Terminator Wizard - Types of Signal-Integrity Checks

Type of Check Description
Unterminated-net length For unterminated nets, checks if the net’s
length is too long to have no termination;
suggests a solution, if possible
Component value non-optimal If a terminating component’s value is more
than 25% different from the value the
Wizard thinks is optimal, the Wizard issues
a warning; this makes it easy to find
components that probably need "fixing"
Driver-to-series-resistor length For series-resistor terminators, checks if
the distance from driver to resistor is too
long for effective termination
AC-terminator resistor-to-capacitor length For AC parallel terminators, checks if the
distance between resistor and capacitor is
too long for effective termination
Pull-up/pull-down combo resistor-to- For DC parallel pull-up/pull-down combo
resistor length terminators, checks if the distance between
the two resistors is too long for effective
termination

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Terminator Wizard Results

Table 21-2. Terminator Wizard - Types of Signal-Integrity Checks (cont.)

Receiver-IC stub length For each receiver IC, checks if its stub
length (i.e., distance from the "main" trace
routing) is too long
Resistor placement relative to receiver ICs For any non-series type of terminating
resistance, checks for improper placement
relative to receiver ICs on the net; e.g., will
flag a DC parallel resistor that is located
too far from a receiver IC
Driver impedance exceeding net’s For each driver, issues a warning if the
impedance driver’s impedance exceeds the net’s
impedance, i.e., if the driver intrinsically
over-terminates the net
Driver impedance large enough to cause For each driver, issues a warning if the
bad DC levels or excessive tolerance driver impedance is large enough to cause
variation in the driver itself any of the following problems:
• Likelihood of invalid DC levels (when
DC termination used)
• Likelihood of an excessive portion of
series termination residing in the driver
itself and therefore subject to excessive
tolerance variations
If the Terminator Wizard issues a warning based on one or more of its signal-integrity checks, it
does not necessarily mean that your termination won’t work. It may help explain, however, why
the waveform you see in the oscilloscope is less than perfect, even if you are using the
component values recommended by the Terminator Wizard. The Wizard cannot compensate,
for example, for improper component placement (e.g., a series resistor located too far from the
driver IC) or poor routing topology.

Driver-IC Impedance
The Terminator Wizard runs several types of signal-integrity checks having to do with the
impedance of the driver IC relative to the characteristic impedance of the net being driven. This
topic describes why.

One problem that can occur if a driver IC has a higher impedance than the driven net is over-
termination. Over-termination means that the driver IC by itself has more than enough
impedance to series terminate the net it’s driving. This implies first of all that there’s no point in
adding more series resistance to the driver externally; and second, that the driver may be
delivering too small a step into the net to make series termination even work. In cases such as
this, it may be necessary to use a different driver with lower impedance, or to increase the
impedance of the driven net.

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Terminator Wizard Results

Tip: To quickly see what a driver’s impedance is, open the Terminator Wizard and look
in the Terminator Analysis area. Driver impedance is one of the listed statistics.

Another set of problems may occur when the driver impedance is lower than net’s impedance,
but still greater than about 20% of the net’s Z0. Now, series termination is possible; however, a
significant portion (20% or more) of the terminating impedance is present in the driver IC itself,
and this portion impedance has a wide range of values that depends on the IC’s manufacturing
tolerance. Such inexactness in the overall series-resistance value may make it difficult to
reliably terminate the net.

Also, if the net is DC parallel terminated, the relatively large driver impedance will cause the
DC levels on the nets to be shifted noticeably away from the normal, unloaded levels. This may
cause threshold-crossing problems.

Driver Models Versus Default Slew Rate

When determining if there are signal-integrity violations for a particular net, the Terminator
Wizard examines the slew time of the net’s driver-IC model. If there is no driver model
specified for the net, the Wizard uses a default rise/fall time for its analysis. (This same
parameter is used for nets without models when the Board Wizard runs.)

In many cases, lack of a known driver–IC position will prevent detailed analysis. So even
though the Wizard can "fall back" on the default slew-time value, it may not be able to provide
much meaningful information if it doesn’t have a specific driver-IC model to look at.

To set the default driver rise/fall time:

1. From inside the Terminator Wizard dialog box, click Preferences.

2. Click the General tab.
3. In the Rise/Fall Time box, type the value in nanoseconds.
4. Click OK.
See also: “Preferences Dialog Box - General Tab” on page 1818

Related Topics
“No Placement Checks for Differential Terminators” on page 947

Pin-to-Pin Physical Lengths

One additional feature of the Terminator Wizard is a list of the physical lengths between
component pins. This data can be useful if you’re trying to debug Wizard warnings about

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Running the Terminator Wizard on the Entire Board

improper component placement, or generally as a way of seeing exactly how far various
component pins are from each other.

The pin-to-pin length distance is displayed at the bottom of the Terminator Analysis area (scroll
down to see it, if needed).

Running the Terminator Wizard on the Entire

Board
In addition to running the Terminator Wizard interactively, net-by-net, you can also use it in
conjunction with BoardSim batch simulation to scan your entire PCB. This allows you, for
example, to get a report of the how many nets on the entire board are too long to be
unterminated, or to get component recommendations for all of the terminators on your PCB.

See also: “Simulating SI for Entire Boards or Multiple Nets“

BoardSim’s "Quick Terminator" feature allows you to add to your board terminating
components (resistors and capacitors) that are not actually present in the board’s layout. This
allows you to experiment with terminations not currently in your design.

Quick Terminators are useful whenever you find a signal-integrity or EMC problem on a net
that is unterminated, and you want to see if termination fixes the problem. You can also use
Quick Terminators to experiment with different termination types on nets that are already
terminated with another type (e.g., a DC parallel terminator whose effects you don’t like, so you
want to try series termination instead).

The Terminator Wizard also uses Quick Terminators, in two ways. First, if one or more Quick
Terminators are present on a net, then the Wizard treats them exactly like "real" components,
recommending values for them, etc. Second, if a net is unterminated but the Wizard is
recommending a termination, it uses Quick Terminators (when you click the Apply Value
button) to create the necessary components.

See also: “Results for Nets With No Terminators” on page 956

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Running the Terminator Wizard on the Entire Board

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 Chapter 22
Simulating DC Voltage Drop

DC drop simulation reports IR drop (voltage drop) and current density across power-supply
nets. These capabilities help you see the effects of IC and connector pins drawing large amounts
of current through power-supply nets at DC operating conditions.

Excessive voltage drop, sometimes known as “rail collapse”, can cause the power-supply IC pin
to fall below the recommended minimum voltage. This can cause the IC to malfunction
(because it is operating in an unspecified condition) and its performance is no longer
guaranteed.

Excessive current density in voltage island neckdowns can generate excessive heat in the
power-supply net, which can cause board failures such as PCB delamination and fusing.
Excessive current density in stitching vias can lead to via failures, such as an opened
connection. DC drop simulation does not translate current density to temperature because it
does not model how the heat spreads away from the regions with high current density. However
it does show regions in the design with concentrated current flow that, depending on design
details, can lead to excessive heat.

You can simulate DC drop on pre- and post-layout designs. Perform “what if” experiments on
post-layout designs by exporting the PDN from BoardSim (you do not have to select a signal
net) to a free-form schematic and editing it in the PDN Editor.

Use batch DC drop simulation in BoardSim to screen the entire board for power-supply nets
with excessive DC drop. You specify whether to simulate all or some of the power-supply nets.
You also specify thresholds that indicate excessive voltage drop, current density, and via
current.

Note
Use DC drop and thermal co-simulation to include the effects of metal resistivity changes
due to heating on DC drop measurements. Co-simulation takes into account the heating
caused by current flowing between VRM and IC power-supply pins.

Use interactive DC drop simulation to simulate one power-supply net (BoardSim) or all the
power-supply nets with source and sink models in the free-form schematic (LineSim).

Restrictions:

• The DC Drop license is required to run DC drop simulation or DC drop and thermal co-
simulation.

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• DC drop simulation is unavailable when a MultiBoard project is loaded.

This topic contains the following:

• “DC Drop QuickStart - BoardSim” on page 965

• “DC Drop QuickStart - LineSim” on page 972
• “DC Drop Background” on page 976
• “Setting Up Designs for Power-Integrity Simulation” on page 341
• “Running DC Drop Batch Simulation” on page 995
• “Running DC Drop Interactive Simulation - BoardSim” on page 997
• “Running DC Drop Interactive Simulation - LineSim” on page 1001
• “Example DC Drop Simulation Results” on page 1002

Related Topics
“QuickStart - Power Integrity“

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DC Drop QuickStart - BoardSim

DC Drop QuickStart - BoardSim

DC drop simulation reports IR drop (voltage drop) and current density across power and ground
nets. These capabilities help you see the effects of IC and connector pins drawing large amounts
of current through power-supply nets at DC operating conditions.

DC Drop simulation helps you find the following design problems:

• Not enough voltage getting to ICs from power supplies that can lead to ICs operating at
unspecified conditions
• High current densities in voltage island neckdowns that can lead to overheating and
board failures, such as dielectric breakdown
• Too much current in stitching vias connecting voltage islands that can lead to via failure
(disconnected power)

Requirements
• The DC Drop license is required to run DC drop simulation or DC drop and thermal co-
simulation.
• DC drop is unavailable when a MultiBoard project is loaded.

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DC Drop QuickStart - BoardSim

Figure 22-1. DC Drop - BoardSim Task Flow

Procedure
1. Open a BoardSim board.
• Select File > Open Board. See “Creating BoardSim Boards“.
2. Identify power-supply nets.
• Select Setup > Power Supplies. The Edit Power-Supply Nets dialog box opens. See
“Identifying Power-Supply Nets - BoardSim” on page 345.

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DC Drop QuickStart - BoardSim

Verify that BoardSim has correctly identified all the power-supply nets. The automatic
identification algorithm can miss power-supply nets with arbitrary names and few
capacitor connections. This verification requirement includes both power and ground
nets.
3. Set up stackup layer thicknesses and material properties.
• Select Edit > Stackup > Edit | Import. See “Creating and Editing Stackups” on
page 353 or “Exporting and Importing Stackups” on page 1177.
4. Optionally set up resistors, inductors, and ferrite beads that are connected in series
between portions of the power-supply net so they are included in the analysis:
• Series resistor set up:
i. If the reference designator prefix is other than the default reference designator
mapping (R, RN, and RP), map the other prefix as a resistor using the Edit
Reference Designator Mappings Dialog Box (Setup > Options > Reference
Designator Mappings).
ii. If the resistor has more than two pins, you must assign the correct resistor pack
model to it using the steps below:
a. Select Setup > Options > Reference Designator Mappings. This opens the
Edit Reference Designator Mappings Dialog Box.
b. Verify that the reference designator used for Resistor Packs is listed correctly
as a prefix and linked to type resistor/resistor pack.
c. If you made a change to the Edit Reference Designator Mappings Dialog
Box, re-open the HYP file.
d. Select Select > Net by Reference Designator and pick one of the Resistor
Pack components.
e. Select Models > Assign Models/values by Net and select Resistor tab and
the Resistor Pack.
f. Change the value and connectivity as needed in the Assign Models dialog
box.
iii. Assign series resistor values to establish the series connection between portions
of the power-supply net. You can assign the values interactively from the Assign
Power Integrity Models Dialog Box - Supply-Net Resistors Tab (Model >
Assign Power Integrity Models) or by using a REF file. The resistor value must
be less than the maximum series power resistor value set in the DC Drop Options
section of the Preferences Dialog Box - Power Integrity Tab (Setup > Option >
General).
• Series inductor set up:

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o For a two-pin inductor, if the reference designator prefix is other than the default
inductance (L), assign it as an inductor using the Edit Reference Designator
Mappings Dialog Box (Setup > Options > Reference Designator Mappings).
iv. If the inductor has more than two pins, assign the reference designator as an IC
and map the series pins from Assign Power Integrity Models Dialog Box - Other
Supply-Net Components Tab (Models > Assign Power Integrity Models) Enter
a small resistance value in the Resistance field for this series inductor.
v. Assign a value for inductors to establish the series connection between portions
of the power-supply net. You can assign the values interactively from the Assign
Power Integrity Models Dialog Box - Supply-Net Inductors Tab (Model >
Assign Power Integrity Models) or by using a REF file. HyperLynx assumes a
small resistance value during the DC drop analysis.
• Series ferrite bead set up:
vi. For a ferrite bead, you must assign its reference designator as an IC using the
Edit Reference Designator Mappings Dialog Box (Setup > Options >
Reference Designator Mappings).
vii. Map the series pins from the Assign Power Integrity Models Dialog Box - Other
Supply-Net Components Tab (Models > Assign Power Integrity Models). You
can model a ferrite bead as a small resistance in the DC drop analysis. Enter the
DC resistance value of the device in the Resistance field.
5. Assign VRM models.
a. Select Models > Assign Power Integrity Models. The Assign Power Integrity
Models Dialog Box - IC Tab opens. See “Edit AC Power Pin Model Dialog Box” on
page 1547.
b. To filter the spreadsheet contents, to make it easy to find key power-supply nets or
reference designators, do any of the following:
• Type a string in the Reference Designator field and click Apply.
• Type a string in the Power-Supply Net field and click Apply.
• Select an item in the Component Types list.
The filter boxes support wildcard characters. Use the asterisk * wildcard to match
any number of characters. Use the question mark ? wildcard to match any one
character.
c. Select one or more spreadsheet rows containing pins that you want to assign a VRM
model to.
To select a block of rows, drag over the row headers. To select non-adjacent rows,
press Ctrl+Click over the row headers.
d. In the VRM Model area, click Assign. The Assign VRM Model Dialog Box opens.

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• Type voltage and internal resistance values, and click OK. You do not need to
specify an inductance for DC drop analysis.
e. If you want to automatically assign reference nets, in the Reference Nets area, click
Assign and associate a reference net with the VRM pin. You must do this if you
want to simulate both the selected and reference power-supply nets. See “DC Drop
Simulation Circuit - Simulate Selected and Reference Power-Supply Nets” on
page 981.
6. Assign DC sink models.
a. Select Models > Assign Power Integrity Models. The Assign Power Integrity
Models Dialog Box - IC Tab opens.
b. To filter the spreadsheet contents, to make it easy to find key power-supply nets or
reference designators, do any of the following:
• Type a string in the Reference Designator field and click Apply.
• Type a string in the Power-Supply Net field and click Apply.
• Select an item in the Component Types list.
The filter boxes support wildcard characters. Use the asterisk * wildcard to match
any number of characters. Use the question mark ? wildcard to match any one
character.
c. Select one or more spreadsheet rows containing IC power-supply pins that you want
to assign a DC sink model to.
To select a block of rows, drag over the row headers. To select non-adjacent rows,
press Ctrl+Click over the row headers.
d. In the DC Sink Model area, click Assign. The Edit DC Power Pin Model Dialog Box
opens.
i. In the Apply Current To list, select Each Sink to apply current to or Whole
Group to average the total current drawn across all selected pins.
ii. In the Current field, type the current for the individual supply pins (Each Sink) or
the current to average across all selected supply pins (Whole Group).
iii. Optionally enter a resistance value. For DC drop analysis, this number is not
crucial.
7. Simulate.
Run any of the following types of simulations:
• Interactive (one net at a time) - Select Simulate PI > Run DC Drop Simulation.
The DC Drop Analysis dialog box opens. See “Running DC Drop Interactive
Simulation - BoardSim” on page 997.

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i. In the Power/Ground Net to Analyze area, select a power-supply net.

ii. Optionally, simulate reference net(s) by selecting the Include Reference Net(s)
check box. You identify reference nets when assigning VRM models to power-
supply pins on the selected net in step 5.
iii. Verify the model assignments in the Assigned Models area. If you need to
modify something, click Assign, and then perform the instructions in steps 5 or
6.
iv. Optionally verify the accuracy of the geometries in the display pane.
Right-click in the display pane to zoom, pan, and so on.
Click a stackup layer name in the Display Areas list to highlight in the display
pane the geometries located on that layer.
Click the Pre-Process Geometry button to display anti-pads and anti-segments in
the display pane.
v. Click Simulate.
• Batch (a group of nets) - Select Simulate PI > Run DC Drop Batch Simulation or
Simulate Thermal > Run PI/Thermal Co-Simulation.
Use DC drop and thermal co-simulation to include the effects of metal resistivity
changes due to heating on DC drop measurements. Co-simulation takes into account
the heating caused by current flowing between VRM and IC power-supply pins.
The Batch DC Drop Simulation dialog box opens. See “Running DC Drop Batch
Simulation” on page 995.
vi. Select each power-supply net you want to simulate and specify its constraints.
vii. Optionally, simulate reference net(s) by selecting the Include Reference Nets
check box and clicking Assign to open the Assign Power Integrity Models dialog
box and assign reference nets. You identify reference nets when assigning VRM
models to power-supply pins on the selected net in step 5.
viii. If you want to see graphical results, select the Create PowerScope Data check
box. Note that creating HyperLynx PI PowerScope data requires significantly
more simulation run time than textual results. If you have a large board with
many power-supply nets, you may want to first run batch simulation without
creating HyperLynx PI PowerScope data, and then use the textual results to
determine which power-supply nets to examine graphically.
ix. Click Run.
8. View results.

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• The Reporter Dialog Box displays voltage and current information at each power
source, load, and via. It also contains active links to via coordinates. Click a link to
display the corresponding via or pin in the board viewer.
• The HyperLynx PI PowerScope Dialog Box displays graphical simulation results in
both 2-D and 3-D views. It displays DC drop voltage using color coding to indicate
areas of higher and lower voltage drop, DC current distribution, and DC current
density. Click Save to save the plots.
9. Export the selected net and board info to LineSim to fix problems.
a. Select Export > Net to > Free-Form Schematic. The Export to LineSim Free-Form
Schematic dialog box opens.
b. Select the Export to PDN Editor checkbox.
c. From the Supply list, select the power-supply nets to export.
d. Click Export. The exported net along with PDN information opens in LineSim.
e. Make changes in the PDN Editor and re-run the analysis. See “DC Drop QuickStart
- LineSim” on page 972.

Related Topics
“Simulating DC Voltage Drop” on page 963
“Setting Up Designs for Power-Integrity Simulation” on page 341

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DC Drop QuickStart - LineSim

DC drop simulation reports IR drop (voltage drop) and current density across power and ground
nets. These capabilities help you see the effects of IC and connector pins drawing large amounts
of current through power-supply nets at DC operating conditions.

DC Drop simulation helps you find the following design problems:

• Not enough voltage getting to ICs from power supplies that can lead to ICs operating at
unspecified conditions
• High current densities in voltage island neckdowns that can lead to overheating and
board failures, such as dielectric breakdown
• Too much current in stitching vias connecting islands that can lead to via failure
(disconnected power)
Use interactive DC drop simulation to simulate all the power-supply nets with source and sink
models in the free-form schematic.

Prerequisites
• The DC Drop license is required to run DC drop simulation.

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Figure 22-2. DC Drop - LineSim Task Flow

Procedure
1. Create the power-distribution network (PDN) layout.
a. Select File > New Free-Form Schematic. The PDN Editor and Free-Form
Schematic Editor windows open.
Restriction: If you do not have a power-integrity license, the PDN Editor does not
appear when you create a new free-form schematic.

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You can also export power-supply nets from BoardSim, to automatically create PDN
geometries and electrical connections. See “Exporting BoardSim Nets to LineSim”
on page 1161.
b. Set up stackup layer thicknesses and material properties.
• Select Edit > Stackup > Edit. See “Creating and Editing Stackups” on
page 353.
c. Set up the PDN using the PDN Editor. Make sure it contains the exact geometries for
the PDN layout. See Defining the Power-Distribution Network.
2. Add VRM pins.
a. Click Add VRM or DC to DC Converter . The Add/Edit VRM or DC to DC
Converter Dialog Box opens.
b. Type the reference designator and pin name.
c. Specify the location by typing values in the Location area or by clicking in the PDN
Editor. Note that clicking the PDN Editor fills the X/Y boxes in the dialog box, but
does not display a landmark right away.
d. From the Connected/Reference Layers area, select the following:
i. Assign a power plane connection to the Conn column.
ii. Assign a reference plane connection to the Ref column.
iii. From the Net list, select the power-supply net. For information about the <auto>
net, see “Power-Supply Nets - PDN Editor”.
iv. From the Ref Net list, select the power-supply net. For information about the
<auto> net, see “Power-Supply Nets - PDN Editor”.
v. From the IC is on list, select the side of the board (top or bottom) the supply pin
resides on.
vi. Assign a padstack. Optionally, click Edit to view or modify the padstack.
e. In the Electrical Models area, type values into the boxes.
f. Click OK.
3. Add IC pins.
a. Click Add IC Power Pin(s) . The Add IC Power Pin(s) dialog box opens.
b. Type the reference designator and starting pin name.
c. From the Place list, select one of the following:
• Single—Place an individual IC power-supply pin. See “Add/Edit IC Power
Pin(s) Dialog Box” on page 1421.

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• Array—Place a group of IC power-supply pins. See “Adding a Group of

Symbols to the PDN Editor”.
d. Specify the location by typing values in the Location area or by clicking in the PDN
Editor. Note that clicking the PDN Editor fills the X/Y boxes in the dialog box, but
does not display a landmark.
e. From the Connected/Reference Layers area, select the following:
i. Assign a power plane connection to the Conn column.
ii. Assign a reference plane connection to the Ref column.
iii. From the Net list, select the power-supply net. For information about the <auto>
net, see “Power-Supply Nets - PDN Editor”.
iv. From the Ref Net list, select the power-supply net. For information about the
<auto> net, see “Power-Supply Nets - PDN Editor”.
v. From the IC is on list, select the side of the board (top or bottom) the supply pin
resides on.
vi. Assign a padstack. Optionally, click Edit to view or modify the padstack.
f. From the Electrical Models area, select the DC Model check box and click Edit to
assign the model. See “Edit DC Power Pin Model Dialog Box” on page 1551.
g. Click OK.
4. Simulate.
• Select Simulate PI > Run DC Drop Simulation.
5. View results.
• The Reporter Dialog Box displays voltage and current information at each power
source, load, and via.
• The HyperLynx PI PowerScope Dialog Box displays graphical simulation results in
both 2-D and 3-D views. It displays DC drop voltage using color coding to indicate
areas of higher and lower voltage drop, DC current distribution, and DC current
density. Click Save to save the plots.

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Related Topics
“Simulating DC Voltage Drop” on page 963
“Setting Up Designs for Power-Integrity Simulation” on page 341
“Defining the Power-Distribution Network”

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This topic contains the following:

• “Current Flow For DC Drop” on page 977

• “DC Drop Conceptual Circuits” on page 979
• “PowerScope Hides Some Shapes for DC Drop” on page 985
• “Design Factors Contributing to DC Drop” on page 987
• “Limitations of DC Drop Simulation” on page 990
• “Data Flow for DC Drop - Interactive Simulation” on page 991
• “Data Flow for DC Drop - Batch Simulation” on page 993

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Current Flow For DC Drop

Current flowing between a voltage provider (source) and its current consumers (sinks) traverses
the power-supply net with some current density and voltage drop. Figure 22-3 shows the current
flow between a voltage source and current sink.

For visual clarity, Figure 22-3 shows current flowing only horizontally across a single metal
stackup layer. To see an example of current flowing vertically through vias, see Figure 22-4 on
page 978.

Figure 22-3. DC Drop Current Flow - Current Density

Table 22-1. DC Drop Current Flow - Current Density

Voltage source, such as a voltage-regulator module (VRM), which is a type
of DC-to-DC converter

Current sink, such as IC power-supply pins

Current flowing between the voltage source and current sink

Current density—Everywhere on the metal, some current density J

(mA/mil^2 or A/mm^2) and some associated voltage drop

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Table 22-1. DC Drop Current Flow - Current Density (cont.)

Metal stackup layer—A single layer of metal of a certain material and
thickness.

Current always flows in a loop, so the total current flowing in a power net also flows in the
ground net (but with a different distribution). See Figure 22-4.

Figure 22-4. DC Drop Current Flow - Current Loop

Table 22-2. DC Drop Current Flow - Current Loop

Voltage source, such as a voltage-regulator module (VRM), which is a type
of DC-to-DC converter

Current sink, such as IC power-supply pins

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DC Drop Conceptual Circuits

This topic provides conceptual circuits to help you understand how current flows from a VRM
model, through a power-supply net, to a current sink model. The information helps map circuit
elements to terms used in the GUI and numerical report files.

This topic contains the following:

• “DC Drop Simulation Circuit - Simulate One Power-Supply Net” on page 979
• “DC Drop Simulation Circuit - Simulate Selected and Reference Power-Supply Nets”
on page 981
• “Mixed Source/Sink Vias or Pads” on page 984
• “Other Vias” on page 984

DC Drop Simulation Circuit - Simulate One Power-Supply Net

Figure 22-5 shows the power-integrity models and main circuit elements used for DC drop
simulation.

Figure 22-5. DC Drop Circuit - Simulate One Power-Supply Net

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Table 22-3. DC Drop Circuit - Simulate One Power-Supply Net

Object Description
VRM model—Voltage source implemented in the design by voltage-regulator
modules (VRMs), which is a type of DC-to-DC converter. The figure below shows
the simulation circuit for a VRM.

Negative polarity indicates current flow out of the pin.

VRM pins often connect to the power-supply net through one or more of the
following: surface-mount pads, component-pin vias, trace segments, and so on.
DC sink model—DC current sink implemented in the design as IC power-supply
pins and perhaps other components. The figure below shows the simulation circuit
for a DC sink.

Positive polarity indicates current flow into the pin.

DC sink pins often connect to the power-supply net through one or more of the
following: surface-mount pads, component-pin vias, trace segments, and so on.
Point where current enters a metal area, usually by a via or pad.

Note: A point where current enters a routed trace is reported in the Other vias
section of the numerical report. See Figure 22-9 on page 985.
Point where current exits a metal area, usually by a via or pad.

Note: A point where current exits a routed trace is reported in the Other vias section
of the numerical report. See Figure 22-9 on page 985.
Stitching via that connects the DC sink to a metal area on another stackup layer.

Stitching via that connects the VRM to a metal area on another stackup layer.

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Figure 22-6 maps the objects in Figure 22-5 and Table 22-3 to the numerical simulation results
displayed in the Reporter Dialog Box.

Figure 22-6. DC Drop Numerical Simulation Results - Simulate One Power-

Supply Net

DC Drop Simulation Circuit - Simulate Selected and Reference

Power-Supply Nets
BoardSim batch and interactive DC drop simulations can simulate the set of power and
reference (ground) nets that form a DC current loop and report simulation results. To do this,
select Include reference net(s) in either the Batch DC Drop Simulation dialog box or the DC
Drop analysis dialog box. BoardSim then automatically assigns VRM and DC sink models to
pins on the reference net(s). This capability saves you setup time and ensures the selected
power-supply net and reference nets use the same amount of overall DC current.

Note
If you manually assign VRM or DC sink models to pins on a reference net, the automatic
DC drop model assignments temporarily override them. DC drop simulation restores
your assignments when simulation completes.

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Figure 22-5 shows the VRM and DC sink models and main circuit elements used for running
DC drop simulation on a pair of selected and reference power-supply nets.

Figure 22-7. DC Drop Simulation Circuit - Simulate Selected and Reference

Power-Supply Nets

Table 22-4. DC Drop Simulation Circuit - Simulate Selected and Reference

Power-Supply Nets
Circuit Description
This circuit shows DC sink and VRM models assigned to pins 2 and 3.

When assigning the VRM and DC sink models, 1.8V was identified as the
“connected” net.

When assigning the VRM model, GND was identified as the “reference” net.

This circuit shows pins 1 and 4 with no assigned models.

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Table 22-4. DC Drop Simulation Circuit - Simulate Selected and Reference

Power-Supply Nets (cont.)
Circuit Description
This circuit shows that you have used the DC Drop Analysis dialog box to do the
following:
1. Select the 1.8V net for simulation.
2. Select Include Reference Net(s), which is the GND net in this example.

When you start simulation, BoardSim automatically assigns models to power-

supply pins on the reference net and on the same components. See “BoardSim
Algorithm to Assign PI Models to Reference Nets” on page 983. Pins 1 and 4
show this automatic and temporary model assignment.

BoardSim Algorithm to Assign PI Models to Reference Nets

BoardSim uses the following algorithm to determine the properties of the automatically-
assigned DC sink and VRM models from the properties of the DC sink and VRM models that
you manually assign to the selected power-supply net:

• On components with DC sink models on the selected net, automatically assign VRM
models with 0 V to pins on the reference net(s).
• On components with VRM models on the selected net, automatically assign DC sink
models to pins on the reference net(s).
The sum of sink current assigned to the selected net is distributed evenly and separately
for DC sink models on the reference nets. The current polarity is the opposite,
effectively causing the DC sink models on the reference net(s) to act as DC source
models.
For example, let us say you assign ten DC sink models set to 0.1 A to the selected net
(for a total of 1 A). That causes -1 A to be distributed evenly to DC sink models for pins
on the component with the VRM model and on the reference net. If two pins connect to
the reference net, BoardSim assigns each of them a DC sink model of -0.5 A (negative
polarity means current flows out of the pin).

Requirements
• For each pin on the selected net with a VRM model, assign a reference net. The
reference net assignment enables BoardSim to identify the set of power-supply nets that
form a DC current loop.
• Assign a DC sink model to one or more pins on the selected net, see “Assign Power
Integrity Models Dialog Box - IC Tab” on page 1456. You do not need to assign
reference nets to pins that have DC sink models assigned.
• Components with DC sink and VRM models have pins that connect directly to the
selected net and at least one reference net.

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If intermediate nets connect the pin to the reference net through resistors or inductors,
they must be identified as power-supply nets. This scenario might happen on VRMs that
connect to the selected or reference net through a network of trace segments and passive
components. See “Editing Power-Supply Nets”.

Mixed Source/Sink Vias or Pads

Figure 22-8 shows a routed trace connected to both a VRM and DC sink. The via connecting the
routed trace to the metal area is reported as a DC port in the Mixed source/sink vias (or pads)
area of the numerical simulation results report.

Current from pin 3 flows partly through the routed trace to pin 2 and partly through the via and
metal area to pin 1. If pins 1 and 2 sink 100 mA each, then pin 3 sources 200 mA. However only
100 mA flows through the DC port and that is the value reported in the Mixed source/sink vias
(or pads) area of the numerical simulation results report.

Figure 22-8. DC Drop Circuit - Mixed Source/Sink Vias

Other Vias
Figure 22-9 shows a routed trace that connects the DC sink to a via that connects to a metal area
and VRM pin. The via connecting the routed trace to the metal area is reported in the Other vias
section of the numerical simulation results report. The Other vias section also reports vias that
connect two routed traces.

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Figure 22-9. DC Drop Circuit - Other Via

PowerScope Hides Some Shapes for DC Drop

The HyperLynx PI PowerScope hides some shapes that do not conduct current during DC drop
simulation. This means it may display a subset of the PDN shapes that are displayed in the
board viewer and PDN Editor.

Figure 22-10 shows example PDN shapes and Table 22-5 describes whether or not the
PowerScope displays them for DC drop.

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Figure 22-10. PowerScope Hides Some Shapes for DC Drop

Table 22-5. PowerScope Hides Some Shapes for DC Drop

Shape Displayed or Hidden?
Displayed because DC current flows between the VRM and DC sink
models.

Displayed because this shape merges with shape 1. If a shape without

VRM and DC sink models connects to a shape with those models, the
shapes merge. The PowerScope will not show a voltage drop across this
shape.
Displayed because this shape merges with shape 2, which merges with
shape 1. If a shape without a VRM or DC sink model connects to a shape
with those models, the shapes merge. The PowerScope will not show a
voltage drop across this shape.

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Table 22-5. PowerScope Hides Some Shapes for DC Drop (cont.)

Shape Displayed or Hidden?
Hidden because a trace (which is not a metal shape) with an open end is
not merged with shape 1. A trace is not displayed if one end does not
connect to a metal shape, VRM model, or DC sink model.
Hidden because the metal shape does not conduct DC current and is not
merged with a shape that conducts DC current.

Design Factors Contributing to DC Drop

Performance constraints may produce PCB designs with numerous power-supply nets that are
implemented as small isolated regions and trace segments. This trend is driven by any of the
following performance requirements:

• Reduce power consumption by doing any of the following:

o Using the smallest VCC value at which the IC meets specifications and by running
each major section of an IC at an optimized value. Independent power-supply nets
can be biased to very similar voltages, such as 1.0V and 1.1V.
o Powering-down idle circuity by shutting off voltage to isolated power-supply nets.
• Reduce the propagation of noise from the power-distribution network (PDN) for one
part of an IC to other parts of the IC.
Cost constraints may produce PCB designs with few stackup layers, causing an individual
stackup layer to contain a mixture of power-supply and signal nets, or multiple power-supply
nets.

IC packaging and off-board connectors may produce PCB designs with highly-perforated metal
regions. This condition is especially true for ball grid arrays (BGAs) where interior pins usually
connect to the PCB through vias, whose antipads can perforate power-supply nets. See
Figure 22-13 on page 989.

Tip: Do ground nets have as many DC drop problems as power nets? It depends on the
design. On the one hand, ground nets may have fewer cutouts/perforations because PCB
designers often deliberately try to carry and preserve AC return currents on them. On the
other hand, areas under BGAs could be a problem, depending on the stackup, because the
ground net could be perforated by antipads to make room for vias.

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Example PCB Geometries That Restrict DC Current Flow

Figure 22-11 on page 988 shows narrow trace segments.

Figure 22-11. DC Current Flow Restriction - Narrow Trace Segments

Figure 22-12 on page 988 shows vertical current flow through vias.

Figure 22-12. DC Current Flow Restriction - Vias

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Table 22-6. DC Current Flow Restriction - Vias

Voltage source—Implemented in the design by voltage-
regulator modules (VRMs), which are a type of DC-to-DC
converter.
Current sink—Implemented in the design as IC power-supply
pins and perhaps other components.

Current flowing between the voltage source and current sink.

When current flows vertically through vias, it is likely that
the vias contain the highest current density.

Figure 22-13 on page 989 shows current flowing horizontally through a field of BGA via
antipads. Connectors can also produce arrays of via antipads.

Figure 22-13. DC Current Flow Restriction - BGA Antipads

Table 22-7. DC Current Flow Restriction - BGA Antipads

Current flow

Pads and antipads (vias not displayed)

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Table 22-7. DC Current Flow Restriction - BGA Antipads

Pin connected to plane

Requirements
• Assign a reference net to each pin on the selected net with a VRM model. The reference
net assignment enables BoardSim to identify the set of power-supply nets that form a
DC current loop.
• Assign a DC sink model to one or more pins on the selected net, see “Assign Power
Integrity Models Dialog Box - IC Tab” on page 1456. You do not need to assign
reference nets to pins that have DC sink models assigned.
• Components with DC sink and VRM models should have pins that connect directly to
the selected net and at least one reference net.
If intermediate nets connect the pin to the reference net through resistors or inductors,
they need to be identified as power-supply nets. This scenario might happen on VRMs
that connect to the selected or reference net through a network of trace segments and
passive components. See “Editing Power-Supply Nets“.

Related Topics
“Running DC Drop Batch Simulation” on page 995
“Running DC Drop Interactive Simulation - BoardSim” on page 997

Limitations of DC Drop Simulation

• BoardSim translators released prior to HyperLynx 8.0 do not write sufficient geometric
details to the .HYP file to simulate power integrity. For a list of translator versions that
support power integrity, see “Translators That Support Power-Integrity Simulation”.
• DC drop is unavailable when a MultiBoard project is loaded.
• DC drop simulation does not report temperatures due to current density. However, you
can display current density for metal regions (as opposed to trace routing) and see where
current is concentrated.
• Limitations of sink and source models
o Sink and source models cannot be saved to a library.
o SPICE sink and source models are not supported.
o Model topology cannot be edited. Figures in the model-assignment dialog boxes
show the supported model topology.

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Data Flow for DC Drop - Interactive Simulation

Figure 22-14 on page 991 shows the main data inputs and outputs for DC drop interactive
simulation.

Figure 22-14. DC Drop Data Flow - Interactive Simulation

Table 22-8. DC Drop Folders Legend - Interactive Simulation

<design> folder. See “About Design Folder Locations” on page 1391.

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Table 22-9 provides the names, locations, and contents of the output files for DC drop
interactive simulation.

Table 22-9. Output Files for DC Drop - Interactive Simulation

File Description
Net-specific results (textual)—DC_Drop.txt Textual simulation results for a specific net.

The label <REFERENCE NETS> identifies

reference net information, such as automatic
model assignments and measurements. See “DC
Drop Simulation Circuit - Simulate Selected and
Reference Power-Supply Nets” on page 981.

Pseudo-XML format. Can be displayed by the

Reporter Dialog Box.
Net-specific results (spreadsheet)— Textual simulation results for a specific net.
<design>.xls or <design>.csv
Microsoft Excel or comma-separated values
format. Can be displayed by Microsoft Excel and
other spreadsheet software.
Net-specific results (graphical)— Graphical simulation results for a specific net.
<design> <stackup_layer_name(s)>.tps
Binary format. Can be displayed by the
This file is NOT automatically saved. You HyperLynx PI PowerScope Dialog Box.
manually save the file from the HyperLynx
PI PowerScope.

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Data Flow for DC Drop - Batch Simulation

Figure 22-15 on page 993 shows the main data inputs and outputs for DC drop batch simulation.

Figure 22-15. DC Drop Data Flow - Batch Simulation

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Table 22-10. DC Drop Folders Legend - Batch Simulation

<design> folder. See “About Design Folder Locations” on page 1391.

<design>\DCDROP(<date>-<time>) folder. For example:

C:\MentorGraphics\<release>\SDD_HOME\hyperlynx\HypFiles\DCDROP(<date>-
<time>), where <date>_<time> is of form <yyyy-mm-dd>-<hh-mm-ss>.

You manually delete obsolete report folders and files.

Table 22-11. Output Files for DC Drop - Batch Simulation

File Description
Batch settings—<design>.DCS Simulation settings. You can choose to save the
session settings from the batch DC Drop
Folder: <design> Simulation dialog box. See “Running DC Drop
Batch Simulation” on page 995.

ASCII format. Can be displayed by a text editor,

but it is not intended to be manually edited.
Power map—Thermal_<net>.txt For each net you select in the spreadsheet in the
Batch DC Drop Simulation dialog box, DC drop
Folder: <design> simulation writes a file containing power
dissipation results. You can import power map
files import into Mentor Graphics FloTHERM®
product for advanced thermal analysis.
Net-specific results (spreadsheet)— Textual simulation results for a specific net.
DCDROP_<net>.xls or
DCDROP_<net>.csv Microsoft Excel or comma-separated values
format. Can be displayed by Microsoft Excel and
other spreadsheet software.

Spreadsheets do not report current-density

measurements.

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Table 22-11. Output Files for DC Drop - Batch Simulation (cont.)

File Description
Net-specific results (textual)— Textual simulation results for a specific net.
DCDROP_<net>.txt
The label <REFERENCE NETS> identifies
Folder: <design>\DCDROP(<date>-<time>) reference net information, such as automatic
model assignments and measurements. See “DC
Drop Simulation Circuit - Simulate Selected and
Reference Power-Supply Nets” on page 981.

Pseudo-XML format. Can be displayed by the

Reporter Dialog Box.
Net-specific results (graphical)— Graphical simulation results for a specific net.
DCDROP_<net>.tps
Binary format. Can be displayed by HyperLynx
Folder: <design>\DCDROP(<date>-<time>) PI PowerScope Dialog Box.
Overall results—report.txt Textual simulation results for all nets.

Folder: <design>\DCDROP(<date>-<time>) Pseudo-XML format. Can be displayed by the

Reporter dialog box. See “Reporter Dialog Box”
on page 1834.

Running DC Drop Batch Simulation

Use the Batch DC Drop Simulation dialog box to simulate DC drop in BoardSim for multiple
power-supply nets at a time. This capability enables you to simulate all power-supply nets on
the board and find problem nets that need further investigation. Simulating several power-
supply nets with complex topologies can take hours to run and consume a lot of memory.

For information about input/output file locations and contents, see “Data Flow for DC Drop -
Batch Simulation” on page 993.

Prerequisite
Verify the design setup and model assignments. See “Setting Up Designs for Power-Integrity
Simulation” on page 341.

Procedure:
1. Do any of the following:
• Select Simulate PI > Run DC Drop Batch Simulation
• Select Simulate Thermal > Run PI/Thermal Co-simulation

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Use DC drop and thermal co-simulation to include the effects of metal resistivity
changes due to heating on DC drop measurements. Co-simulation takes into account
the heating caused by current flowing between VRM and IC power-supply pins.
The Batch DC Drop Simulation dialog box opens.
2. To optionally load settings saved from a previous simulation, click Load. In the dialog
box that opens, browse to the DC drop batch session file (.DCS) and click Open.
3. Enable specific power-supply nets for simulation by doing any of the following:
• To enable/disable individual nets, select/clear their check boxes in the spreadsheet.
• To enable all nets, click Check All.
• To disable all nets, click Uncheck All.
To filter the spreadsheet, type text and optional wildcards into the Filter box and click
Apply. Use the asterisk * wildcard to match any number of characters. Use the question
mark ? wildcard to match any one character. To display all spreadsheet rows, type
asterisk * and click Apply.
4. Type the voltage drop threshold, in mV, into cells in the Max Voltage Drop column.
Measurements greater than this value are reported as errors.
5. Type the current density threshold, in mA/mil^2 (English) or A/mm^2 (Metric), into
cells in the Max Current Density column. Measurements greater than these threshold
values are reported as errors.
6. Type the via current threshold, in mA, into cells in the Max Via Current column.
Measurements greater than these threshold values are reported as errors.
7. To assign source and sink models, click Assign Models. See “Assigning Power-
Integrity Models - BoardSim”.
8. Optionally, simulate reference net(s) by selecting the Include Reference Nets check
box. See “DC Drop Simulation Circuit - Simulate Selected and Reference Power-Supply
Nets” on page 981.
This option requires that you assign both a VRM model and a reference net to one or
more pins on the selected net.
This option usually increases simulation run time, but can reduce the number of models
to assign. It also ensures the selected and reference nets sink the same amount of overall
DC current.
Restriction: This option is always selected when running thermal/DC drop co-
simulation.
9. To create graphical simulation results to .TPS files that can be displayed in the
HyperLynx PI PowerScope Dialog Box, select the Create PowerScope Data check
box.

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10. To save results to a spreadsheet, select the Create Spreadsheet Reports check box and
click either of the following:
• Microsoft Excel (.XLS)
• Comma-separated (.CSV)
Spreadsheets do not contain current-density measurements.
Restriction: This option is unavailable when running thermal/DC drop co-simulation.
11. To save power dissipation results to files that you can import into Mentor Graphics
FloTHERM or HyperLynx Thermal, select Write power-map files for FloTHERM.
You might do this to run thermal analysis.
Result: For each net you select in the spreadsheet, DC drop simulation writes a file
containing power dissipation results. The file name is of form Thermal_<net_name>.txt
and is written to the design folder. See “About Design Folder Locations” on page 1391.
Restriction: This option is always selected when running thermal/DC drop co-
simulation.
12. To save the settings to the DC drop batch session file (.DCS), click Save.
13. Click Run.
The Reporter Dialog Box displays links to detailed textual and optional graphical
results, and displays links to vias in the display area.
See also: “Example DC Drop Simulation Results” on page 1002

Related Topics
“Simulating DC Voltage Drop” on page 963

Running DC Drop Interactive Simulation -

BoardSim
Use the DC Drop Analysis dialog box to simulate DC drop in BoardSim for power-supply nets.

To make it easy to simulate power-supply nets that form a current loop, such as power and
ground, you can optionally simulate reference nets for the selected power-supply net. See “DC
Drop Simulation Circuit - Simulate Selected and Reference Power-Supply Nets” on page 981.

For information about output file locations and contents, see “Data Flow for DC Drop -
Interactive Simulation” on page 991.

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Prerequisite
Verify the design setup and model assignments. See “Setting Up Designs for Power-Integrity
Simulation” on page 341.

Procedure
The main steps include selecting a power-supply net to simulate, optionally include reference
power-supply nets in simulation, verifying or assigning source and load models, setting
constraint values, and launching simulation.

To run DC drop interactive simulation in BoardSim:

1. Click Run DC Drop Simulation or select Simulate PI > Run DC Drop

Simulation.
The DC Drop Analysis dialog box opens.
The HyperLynx PI PowerScope Dialog Box opens if you have previously run DC drop
simulation in the current BoardSim session.
2. In the Power/Ground Net to Analyze list, select a power-supply net.
The following areas display information about the selected power-supply net:
• Connected Nets—Power-supply nets are considered connected (or associated) if
either of following conditions are true:
o The resistance of the passive elements connecting the nets does not exceed the
threshold value specified by the “Separate nets if resistor exceeds” option in the
Power Integrity tab of the Preferences dialog box. See “Preferences Dialog Box -
Power Integrity Tab” on page 1829.
o You enable the “Include Reference Net(s)” option in step 3 and assign both a
VRM model and reference net to one or more pins on the selected net.
Connected/associated power-supply nets are included in DC drop simulation.
Series components can be resistors, inductors, and “other” components, such as
power-FETs.
• Assigned Models—Displays DC sink or VRM model assignments. The label
“<ref>” identifies models assigned to reference nets.
• Display Areas—Displays stackup layers containing metal areas and trace segments
connected to the selected power-supply net.
Click a stackup layer to highlight its geometries in the display pane.
If the stackup area contains multiple areas, expand the tree and click an area to
highlight its geometries in the display pane.

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• Display Pane—Displays the geometry of the selected power-supply net. See “DC
Drop Analysis Display Pane” on page 1000.
3. Optionally, simulate reference net(s) by selecting the Include Reference Net(s) check
box. See “DC Drop Simulation Circuit - Simulate Selected and Reference Power-Supply
Nets” on page 981.
This option requires that you assign both a VRM model and a reference net to one or
more pins on the selected net.
This option usually increases simulation run time, but can reduce the number of models
to assign. It also ensures the selected and reference nets sink the same amount of overall
DC current.
4. Click Assign to assign source and sink models to pins on the selected net. The Assign
Power Integrity Models dialog box opens. See “Assigning Power-Integrity Models -
BoardSim”.
5. To display pins without model assignments in the Assigned Models list, select the Show
All Pins check box. You might do this to see all the available pins.
“<none>” means the pin has no DC sink or VRM model.
“(disconnected)” applies only to IC pins and means the pin does not connect to the
power-supply net through a via or trace segments. These pins could represent board-
geometry problems. Sometimes you click the Pre-Process Geometry button in step 10 to
display the “(disconnected)” label.
6. To zoom to a reference designator and pin that you select in the Assigned Models list,
select the Zoom to Selection check box.
7. Type values for the following constraints:
• Max Voltage Drop
• Max Current Density
• Max Via Current—Applies to stitching vias.
The Reporter Dialog Box highlights simulation results that exceed constraint values, but
the optional spreadsheet does not.
8. To save results to a spreadsheet, select the Save spreadsheet check box, type or browse
to the report file, and click either of the following:
• Microsoft Excel (.XLS)
• Comma-separated (.CSV)
Spreadsheet files do not contain current-density measurements.

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9. To save power dissipation results to files that you can import into Mentor Graphics
FloTHERM, select Write power-map files for FloTHERM. You might do this to run
advanced thermal analysis.
Result: For the net you select, DC drop simulation writes a file containing power
dissipation results. The file name is of form Thermal_<net_name>.txt and is written to
the design folder. See “About Design Folder Locations” on page 1391.
10. To pre-process the design and to display anti-pads and anti-segments in the display
pane, click Pre-Process Geometry. Pre-processing does the following:
• Checks net connectivity through copper pours, traces, pads, and vias.
• Prepares copper areas (in memory only) for simulation by 1) removing overlapping
metal, 2) creating antipads where needed, using the default padstack values. See
Preferences Dialog Box - Default Padstack Tab.
Pre-processing enables you to display anti-pads and anti-segments without running
simulation.
11. Click Show PowerScope to open or re-open the HyperLynx PI PowerScope Dialog
Box.
12. Click Simulate.
The HyperLynx PI PowerScope Dialog Box displays graphical simulation results. To
view the graphical results at a later time, click Save to manually save the 3-D plot to a
transmission-plane simulation (.TPS) file.
The Reporter Dialog Box displays textual results and provides links to vias in the
display area.
For information about the contents and locations of the simulation output files, see
“Data Flow for DC Drop - Interactive Simulation” on page 991.
See also: “Example DC Drop Simulation Results” on page 1002
13. Repeat steps 2-12 to simulate other power-supply nets.

Tip: If anti-pads do not exist for pins or vias on a power-supply net, they are
automatically added prior to DC drop simulation. The anti-pad clearance is specified on
the Preferences Dialog Box - Default Padstack Tab.

DC Drop Analysis Display Pane

• Use the display pane to visually check for missing geometries, such as copper pours or
antipads, in the power-supply net. The BoardSim board translators can sometimes
produce board files with missing or incorrect geometries.
• The pane shows all traces, pads and copper areas of the selected nets.

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• The pane highlights, in white, the objects on the selected layer or individual area. If the
stackup layer contains multiple individual areas, you can select one of them for
highlighting by expanding the stackup layer item in the Display Area list and clicking an
area name.
• The pane highlights the pads for power-supply pins in either blue or yellow. A pad is
yellow when you select its pin in the Assigned Models list.
• To display a power-supply pin and its surrounding geometries, select the Zoom to
Selection check box and select the pin in the Assigned Models list. To display all
power-supply pins in the Assign Models list, see step 5.
• Right-click in the display area to zoom and pan.
• The display pane does not initially show anti-pads and anti-segments. Perform step 10 to
display them.
• Yellow circles represent stitching vias that are connected to selected pins through copper
areas or traces.
• Black dots represent stitching vias.

Related Topics
“Overlapping Anti-Pads That Isolate Metal Shapes” on page 1395

“Simulating DC Voltage Drop” on page 963

Running DC Drop Interactive Simulation -

LineSim
Use the DC Drop Analysis dialog box to simulate DC drop in the free-form schematic for all
power-supply nets containing both source and sink models.

Restriction: The cell-based schematic editor does not support DC drop simulation.

Prerequisite
Verify the design setup and model assignments. See “Setting Up Designs for Power-Integrity
Simulation” on page 341.

Procedure
1. Click Run DC Drop Simulation or select Simulate PI > Run DC Drop
Simulation.
The DC Drop Analysis dialog box opens.
2. Type values for the following constraints:

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• Max Voltage Drop

• Max Current Density
• Max Via Current—Applies to stitching vias.
3. To save results to a spreadsheet, select the Save spreadsheet check box, type or browse
to the report file, and click either of the following:
• Microsoft Excel (.XLS)
• Comma-separated (.CSV)
Spreadsheet files are located in the same folder as the design, unless you choose another
folder.
Note the spreadsheet does not contain current density values. The Reporter Dialog Box
displays the maximum current density.
4. To save power dissipation results to files that you can import into Mentor Graphics
FloTHERM, select Write power-map files for FloTHERM. You might do this to run
advanced thermal analysis.
Result: For all the nets in the PDN Editor, DC drop simulation writes a file containing
power dissipation results. The file name is of form Thermal_TPE.txt and is written to the
design folder. See “About Design Folder Locations” on page 1391.
5. Click Simulate.
The HyperLynx PI PowerScope Dialog Box displays graphical results. To view the
graphical results at a later time, click Save to manually save the 3-D plot to a
transmission-plane simulation (.TPS) file.
The Reporter Dialog Box displays textual results.
See also: “Example DC Drop Simulation Results” on page 1002

Related Topics
HyperLynx PI PowerScope Dialog Box

“Reporter Dialog Box” on page 1834

“Simulating DC Voltage Drop” on page 963

“Adding Symbols to Power-Distribution Networks”

Example DC Drop Simulation Results

This topic steps you through interpreting DC drop simulation results for a very simple design.

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This topic does not provide example spreadsheets or DC current distribution graphs.

This topic contains the following:

• “DC Drop Example Design” on page 1004

• “DC Drop Example Textual Report” on page 1005
• “DC Drop Example Voltage Drop Graphs” on page 1007
• “DC Drop Example Current Density Graphs” on page 1010

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DC Drop Example Design

Figure 22-16 shows a deliberately-simple design in the PDN Editor with one current sink and
one voltage source.

Figure 22-16. Measuring DC Drop - Design

Table 22-12. Measuring DC Drop - Design

An IC power-supply pin acting as a current sink. A DC model provides
the electrical behavior. DC drop simulation ignores AC electrical
models, if they are assigned.

To display the ToolTip containing model information, point to the pin.

A voltage-regulator module (VRM) pin acting as a voltage source. A
VRM model provides the electrical behavior.

To display the ToolTip containing model information, point to the pin.

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DC Drop Example Textual Report

Figure 22-17 shows the textual results displayed in the Reporter Dialog Box.

For information about mapping DC drop simulation circuit elements to terms used in this report,
see “DC Drop Conceptual Circuits” on page 979.

Figure 22-17. Measuring DC Drop - Reporter

Table 22-13. Measuring DC Drop - Reporter

This section summarizes the model assignments.

Current flowing into a pin has a positive sign. U2.1 has -5 A assigned to
it, so this is the voltage source (VRM). U1.1 has +5 A assigned to it, so
this is the current sink (IC power-supply pin).
This section provides statistics for design pins with voltage source
models.

In BoardSim, the X/Y coordinate text cross-probes to the board viewer.

But this is a LineSim design, and the text does not cross probe to the
PDN Editor window.

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Table 22-13. Measuring DC Drop - Reporter (cont.)

This section provides statistics for design pins with current sink models.

In BoardSim, the X/Y coordinate text cross-probes to the board viewer.

But this is a LineSim design, and the text does not cross probe to the
PDN Editor window.

Related Topics
“Reporter Dialog Box” on page 1834

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DC Drop Example Voltage Drop Graphs

Figure 22-18 on page 1007 shows the optional graphical results for voltage drop displayed in
the HyperLynx PI PowerScope Dialog Box. The HyperLynx PI PowerScope display is set to
two dimensions, which produces a “top down and flat” display of the power-supply net
geometries.

Figure 22-18. Measuring DC Drop - HyperLynx PI PowerScope 2-D

Table 22-14. Measuring DC Drop - HyperLynx PI PowerScope 2-D

Legend that maps the graph colors to the measured voltage.
Voltage values are relative to the origin set in the HyperLynx PI
PowerScope. Voltage drop values increase as the color shifts
from blue to red.
Voltage source pin.

To display the ToolTip containing model information, enable the

HyperLynx PI PowerScope “Inspect” mode, and then point to
the pin.

Note that you cannot display two ToolTips at a time in the

HyperLynx PI PowerScope; Figure 22-18 on page 1007 contains
two ToolTips with help from graphics editing software.

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Table 22-14. Measuring DC Drop - HyperLynx PI PowerScope 2-D (cont.)

Current sink pin.

To display the ToolTip containing model information, enable the

HyperLynx PI PowerScope “Inspect” mode, and then point to
the pin.
Maximum voltage difference between the voltage source and
current sink. Note the legend and this value have different
number of significant digits, so rounding is likely.

If there were multiple sources/sinks, The maximum voltage

difference across all of them is reported.
Figure 22-19 and Figure 22-20 on page 1009 show the optional graphical results for voltage
drop displayed in the HyperLynx PI PowerScope. The HyperLynx PI PowerScope display is set
to three dimensions, which displays the voltage in the Z axis (or height). You can rotate the
graph, and this particular orientation was chosen to emphasize the location of the sink/source
pins.

Figure 22-19. Measuring DC Drop - HyperLynx PI PowerScope 3-D Current Sink

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Figure 22-20. Measuring DC Drop - HyperLynx PI PowerScope 3-D Voltage

Source

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DC Drop Example Current Density Graphs

Figure 22-21 shows the optional graphical results for current density displayed in the
HyperLynx PI PowerScope Dialog Box. The HyperLynx PI PowerScope display is set to two
dimensions, which produces a “top down and flat” display of the power-supply net geometries.

Figure 22-21. Measuring Current Density - HyperLynx PI PowerScope 2-D

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Figure 22-22 shows the optional graphical results for current density displayed in the
HyperLynx PI PowerScope. The HyperLynx PI PowerScope display is set to three dimensions,
which displays the current density in the Z axis (or height). You can rotate the graph, and this
particular orientation was chosen to emphasize the location of the sink/source pins.

Note that you cannot display two ToolTips at a time in the HyperLynx PI PowerScope;
Figure 22-22 contains two ToolTips with help from graphics editing software.

Figure 22-22. Measuring Current Density - HyperLynx PI PowerScope 3-D

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 Analyzing Decoupling

Chapter 23
Analyzing Decoupling

Decoupling analysis helps you evaluate the ability of the power-distribution network (PDN) to
provide low-impedance paths for IC current loads. The analysis typically covers a broad
frequency range, especially the frequencies above the power-supply-response frequency and
below the plane-resonant frequency (although plane resonances can occur at low frequencies for
some PDNs).

Decoupling analysis can help you perform the following PCB design tasks:

• Identify the minimum number of capacitors needed to meet the PDN target impedance.
• Identify capacitors that connect to the PDN with highly-inductive mounting.
• Identify optimum capacitor locations, in a manual PDN planning or “what if” scenario.
• Identify IC power-supply pins that connect to the PDN with highly-inductive mounting.
• Quantify benefits of new technologies. Embedded capacitance technologies include
embedded capacitor materials (such as C-ply) and ultra-thin and high Er dielectric
materials. Via and IC mounting technologies include via-in-pad, microvias, and X2Y
capacitors.
Decoupling analysis supports lumped and distributed modeling of the PDN. Distributed
decoupling analysis is intended for higher frequency modeling where the transmission plane
effects are important and lumped decoupling analysis is intended for low frequency modeling
where the VRM model may be important. See “Decoupling Wizard - Choose a Type of
Analysis Page” on page 1508.

Use the Decoupling Wizard to run analysis and create one of the following main outputs:

• A Z-parameter model that reports the impedance of a pair of power-supply nets over a
frequency range. The Touchstone Viewer automatically displays the model. You can
then see if the reported impedances meet the target impedance for the PDN.
Distributed decoupling analysis displays the impedance of the PDN measured at the IC
power-supply pin (observation point), while lumped decoupling analysis displays the
impedance of the overall PDN.
• A spreadsheet that reports decoupling capacitor information, such as total mounting
inductance and mounted resonant frequency. This information enables you to quickly
identify ineffective decoupling capacitors.
You can simulate power-supply net decoupling on pre- and post-layout designs. Perform “what
if” experiments on post-layout designs by exporting the pair of power-supply nets from

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Decoupling Analysis QuickStart - BoardSim

BoardSim to a free-form schematic and editing it in the PDN Editor. See “Exporting BoardSim
Nets to LineSim” on page 1161.

Note
For computers running on Windows or Linux, decoupling analysis runs on all available
cores.

For computers running on Solaris, decoupling analysis runs on one core.

Restrictions:

• The Decoupling license is required to run decoupling analysis.

• In BoardSim, you cannot run decoupling analysis on power-supply nets formed entirely
by trace segments.
• Decoupling analysis is unavailable when a MultiBoard project is loaded.
This topic contains the following:

• “Decoupling Analysis QuickStart - BoardSim” on page 1014

• “Decoupling Analysis QuickStart - LineSim” on page 1019
• “Running Decoupling Analysis” on page 1026
• “Data Flow for Decoupling Analysis” on page 1027
• “Circuit Topology for Lumped Decoupling Analysis” on page 1029
• “Circuit Topology for Distributed Decoupling Analysis” on page 1030
• “Decoupling Capacitor Report Spreadsheets” on page 1031

Related Topics
“Setting Up Designs for Power-Integrity Simulation” on page 341
“Run HyperLynx with a Lower Priority” on page 1409

Decoupling Analysis QuickStart - BoardSim

Decoupling analysis helps you evaluate the ability of the power-distribution network (PDN) to
provide low-impedance paths for IC current loads. The analysis typically covers a broad
frequency range, especially the frequencies above the power-supply-response frequency and
below the plane-resonant frequency (although plane resonances can occur at low frequencies for
some PDNs). You can then see if the reported power-supply net impedances are below the
target impedance for the PDN.

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Decoupling analysis runs on one pair of power-supply nets at a time, where one net provides
power and the other provides return current. For ICs with multiple pairs of power-supply nets,
you run decoupling analysis multiple times, once for each pair of power-supply nets that draws
significant power.

Requirements
• The Decoupling license is required to run decoupling analysis.
• You cannot run decoupling analysis on power-supply nets formed entirely by trace
segments.
• Decoupling analysis is unavailable when a MultiBoard project is loaded.

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Decoupling Analysis QuickStart - BoardSim

Figure 23-1. Decoupling Analysis - BoardSim Task Flow

Procedure
When analyzing a power and ground net pair for the first time, you may want to get good results
from lumped analysis before running distributed analysis (which takes longer to set up and run).

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The first portion of this procedure (steps 1-6) shows how to setup and run lumped decoupling
analysis. The second portion of this procedure (steps 7-8) shows the additional setup steps to
run distributed decoupling analysis.

1. Open a BoardSim board.

• Select File > Open Board. See “Creating BoardSim Boards”.
2. Identify power-supply nets.
a. Select Setup > Power Supplies. The Edit Power-Supply Nets dialog box opens. See
“Identifying Power-Supply Nets - BoardSim” on page 345.
Verify that BoardSim has correctly identified all the power-supply nets. The
automatic identification algorithm can miss power-supply nets with arbitrary names
and few capacitor connections. This verification requirement includes both power
and ground nets.
b. In the Assign Supply Nets To Plane Layers area, assign at least two different power-
supply nets.
c. Click OK.
3. Set up stackup layer thicknesses and material properties.
• Select Edit > Stackup > Edit | Import. See “Creating and Editing Stackups” on
page 353 or “Exporting and Importing Stackups” on page 1177.
4. Assign decoupling capacitor values or models.
a. Optionally, create a QPL file to assign decoupling capacitor values or models to part
names. See “QPL File Editor”.
b. Create groups of decoupling capacitors. This enables you to assign values or models
to many capacitors at the same time.
i. Select Models > Edit Decoupling-Capacitor Groups. The Assign Decoupling-
Capacitor Groups Dialog Box opens.
The left spreadsheet contains capacitors that have not been assigned to a
capacitor group.
The right spreadsheet contains capacitor groups. BoardSim automatically
assigns decoupling capacitors with the same capacitance and maximum pin-to-
pin dimensions to the same group. If you created a QPL file in step a, group(s)
named QPL_<part_name> appear in the spreadsheet.
ii. To assign a capacitor to a group, click the row header for the capacitor, click the
row header for the existing or <new> group, and then click >>.
iii. Click OK.
c. Assign values or models to decoupling capacitors or capacitor groups.

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i. Select Models > Edit Decoupling-Capacitor Models. The Assign Decoupling-

Capacitor Models Dialog Box opens.
ii. Double-click the spreadsheet row for a group or an individual capacitor. The
Assign / Edit Capacitor Model Dialog Box opens.
iii. Assign values or a model and click OK. Capacitor model or value assignments
you make in this dialog box override assignments you make in a QPL file (see
step a).
iv. Repeat steps ii-iii to assign models to remaining decoupling capacitors.
v. Click Close.
5. Simulate using lumped analysis.
a. Select Simulate PI > Analyze Decoupling. The Decoupling Wizard opens.
b. Perform the steps in the Decoupling Wizard. Read the wizard page text to help you
set up the simulation.
6. View results. Is the impedance profile below the target impedance? If yes, move to step
7, if no, make changes to decoupling capacitor models and stackup and re-run lumped
analysis.
• Lumped and distributed analyses create Z-parameter models that contain the
impedance profile for the PDN. When analysis completes, the Touchstone and
Fitted-Poles Viewer automatically displays the model. See “Viewing and
Converting Touchstone and Fitted-Poles Models” on page 1065.
• Quick analysis creates a spreadsheet containing information about mounting
inductance, effective resonant frequency, and so on, for each decoupling capacitor.
See “Decoupling Capacitor Report Spreadsheets“.
7. Assign AC sink models, VRM models, and reference nets.
a. Select Models > Assign Power Integrity Models. The Assign Power Integrity
Models Dialog Box - IC Tab opens.
b. To filter the spreadsheet contents, to make it easy to find key power-supply nets or
reference designators, do any of the following:
• Type a string in the Reference Designator box and click Apply.
• Type a string in the Power-Supply Net box and click Apply.
• Select an item in the Component Types list.
The filter boxes support wildcard characters. Use the asterisk * wildcard to
match any number of characters. Use the question mark ? wildcard to match any
one character.

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c. Select one or more spreadsheet rows containing IC power-supply pins that you want
to assign a model or reference net to.
To select a block of rows, drag over the row headers. To select non-adjacent rows,
press Ctrl+Click over the row headers.
d. Click Assign in the appropriate model type area and perform the procedure in one of
the following topics:
• “Edit AC Power Pin Model Dialog Box” on page 1547
• “Assign VRM Model Dialog Box” on page 1470
• “Set Reference Nets Dialog Box” on page 1858
See “About Power-Integrity Models” on page 349.
8. Simulate using distributed decoupling analysis.
a. Select Simulate PI > Analyze Decoupling. The Decoupling Wizard opens.
b. Perform the steps in the Decoupling Wizard. Read the wizard page text to help you
set up the simulation.
You can include or exclude from analysis the series inductance that is unique to the
traces and vias that connect IC power-supply pins to the PDN.
• Exclude this series inductance to focus on decoupling capacitor placement and
values.
• After optimizing decoupling capacitors, include this series inductance to focus on
the effects of IC power-supply pin mounting.
Use the Remove series inductance unique to each power pin, to see plane decoupling
more clearly option on the Decoupling Wizard - Customize Settings Page to exclude or
include this series inductance.
9. View results. Is the impedance profile below the target impedance? If if no, make
changes to decoupling capacitor models and stackup and re-run the analysis.
10. For additional pairs of power-supply nets, repeat steps 5-8.

Related Topics
“Analyzing Decoupling”

“Setting Up Designs for Power-Integrity Simulation” on page 341

Decoupling Analysis QuickStart - LineSim

Decoupling analysis helps you evaluate the ability of the power-distribution network (PDN) to
provide low-impedance paths for IC current loads. The analysis typically covers a broad

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frequency range, especially the frequencies above the power-supply-response frequency and
below the plane-resonant frequency (although plane resonances can occur at low frequencies for
some PDNs). You can then see if the reported power-supply net impedances are below the
target impedance for the PDN.

Decoupling analysis runs on one pair of power-supply nets at a time, where one net provides
power and the other provides return current. For ICs with multiple pairs of power-supply nets,
you run decoupling analysis multiple times, once for each pair of power-supply nets that draws
significant power.

Requirements
• The Decoupling license is required to run decoupling analysis.

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Figure 23-2. Decoupling Analysis - LineSim Task Flow

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Procedure
When analyzing a power and ground net pair for the first time, you may want to get good results
from lumped analysis before running distributed analysis (which takes longer to set up and run).
The first portion of this procedure (steps 1-10) shows how to set up and run lumped decoupling
analysis. The second portion of this procedure (steps 8-9) shows the additional set up steps to
run distributed decoupling analysis.

1. Create the power-distribution network (PDN) layout.

a. Select File > New Free-Form Schematic. The PDN Editor and Free-Form
Schematic Editor windows open.
Restriction: If you do not have a power-integrity license, the PDN Editor does not
appear when you create a new free-form schematic.
b. Set up stackup layer thicknesses and material properties.
• Select Edit > Stackup > Edit | Import. See “Creating and Editing Stackups” on
page 353 or “Exporting and Importing Stackups” on page 1177.
c. Set up the PDN using the PDN Editor. Make sure it contains the exact geometries for
the PDN layout. See “Defining the Power-Distribution Network”.
After creating the metal area geometries, but before assigning decoupling capacitors,
you can measure the plane capacitance to see how much it decoupling it contributes.
To do this, perform steps 9-10 using lumped analysis. If the analysis results show
that the impedance profile for the board is above the target impedance, perform steps
2-3 to add decoupling capacitors and stitching vias to fix the problem and re-run
lumped decoupling analysis.
2. Set up decoupling capacitors.
a. Click Add Decoupling Capacitor(s) . The Add/Edit Decoupling Capacitor(s)
Dialog Box opens.
b. From the Place list, select one of the following:
• Single—Place an individual capacitor.
• Array—Place a group of capacitors. See “Adding a Group of Symbols to the
PDN Editor”.
c. Specify the location by typing values in the Location area or by clicking in the PDN
Editor. Note that clicking the PDN Editor fills the X/Y boxes in the dialog box, but
does not display a landmark.
d. To designate the pair of planes that the capacitor decouples and the padstack for the
vias:
i. Click Edit Mounting Scheme. The Decoupling Mounting Scheme Editor
Dialog Box opens.

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ii. Double-click each via to specify its connectivity and padstack. The Add/Edit Via
Dialog Box opens.
iii. Close the Decoupling Mounting Scheme Editor and Add/Edit Via dialog box.
You return to the Add Decoupling Capacitor(s) dialog box.
e. Click Assign Model. The Assign / Edit Capacitor Model Dialog Box opens.
Assign capacitor values or models.
f. Repeat steps a-e to add additional decoupling capacitors to the PDN.
3. Optionally add stitching vias to short planes together.
a. Click Add Stitching Via(s) . The Add Stitching Via(s) dialog box opens.
b. From the Place list, select one of the following:
• Single—Place an individual stitching via. See “Adding Stitching Vias“.
• Array—Place a group of stitching vias. See “Adding a Group of Symbols to the
PDN Editor”.
c. Specify the location by typing values in the Location area or by clicking in the PDN
Editor. Note that clicking the PDN Editor fills the X/Y boxes in the dialog box, but
does not display a landmark.
d. From the Connected Layers list, select each layer the vias connect to.
e. From the Padstack list, select the padstack.
f. Click OK.
4. If you plan to run PI and SI co-simulation, add single and differential vias. See
“Add Signal Via Dialog Box“.
5. Set up VRM pins.
a. Click Add VRM or DC-to-DC Converter . The Add/Edit VRM or DC to DC
Converter Dialog Box opens.
b. Type the reference designator and pin name.
c. Specify the location by typing values in the Location area or by clicking in the PDN
Editor. Note that clicking the PDN Editor fills the X/Y boxes in the dialog box, but
does not display a landmark.
d. From the Connected/Reference Layers area, do the following:
i. Assign a power plane connection to the Conn column.
ii. Assign a reference plane connection to the Ref column.

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iii. From the Net list, select the power-supply net. For information about the <auto>
net, see “Power-Supply Nets - PDN Editor”.
iv. From the Ref Net list, select the power-supply net. For information about the
<auto> net, see “Power-Supply Nets - PDN Editor”.
v. From the IC is on list, select the side of the board (top or bottom) the supply pin
resides on.
vi. Assign a padstack. Optionally, click Edit to view or modify the padstack.
e. From the Electrical Models area, type values into the boxes or select a model.
f. Click OK.
6. Simulate using lumped analysis.
a. Select Simulate PI > Analyze Decoupling. The Decoupling Wizard opens.
b. Perform the steps in the Decoupling Wizard. Read the wizard page text to help you
set up the simulation.
7. View results. Is the impedance profile below the target impedance? If yes, move on. If
no, make changes to decoupling capacitor models and stackup and re-run lumped
analysis.
• Lumped and distributed analyses create Z-parameter models that contain the
impedance profile for the PDN. When analysis completes, the Touchstone and
Fitted-Poles Viewer automatically displays the model. See “Viewing and
Converting Touchstone and Fitted-Poles Models” on page 1065.
• Quick analysis creates a spreadsheet containing information about mounting
inductance, effective resonant frequency, and so on, for each decoupling capacitor.
See “Decoupling Capacitor Report Spreadsheets“.
8. Set up IC power-supply pins
a. Click Add IC Power Pin(s) . The Add IC Power Pin(s) dialog box opens.
b. Type the reference designator and starting pin name.
c. From the Place list, select one of the following:
• Single—Place an individual IC power-supply pin. See “Add/Edit IC Power
Pin(s) Dialog Box” on page 1421.
• Array—Place a group of IC power-supply pins. See “Adding a Group of
Symbols to the PDN Editor”.
d. Specify the location by typing values in the Location area or by clicking in the PDN
Editor. Note that clicking the PDN Editor fills the X/Y boxes in the dialog box, but
does not display a landmark.

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e. From the Connected/Reference Layers area, select the following:

i. Assign a power plane connection to the Conn column.
ii. Assign a reference plane connection to the Ref column.
iii. From the Net list, select the power-supply net. For information about the <auto>
net, see “Power-Supply Nets - PDN Editor”.
iv. From the Ref Net list, select the power-supply net. For information about the
<auto> net, see “Power-Supply Nets - PDN Editor”.
v. From the IC is on list, select the side of the board (top or bottom) the supply pin
resides on.
vi. Assign a padstack. Optionally, click Edit to view or modify the padstack.
f. From the Electrical Models area, select the AC Model check box and click Edit to
assign the model. See “Edit AC Power Pin Model Dialog Box” on page 1547.
g. From the Electrical Models area, select the AC Model check box and click Edit to
assign the model. See “Edit AC Power Pin Model Dialog Box” on page 1547
h. Click OK.
9. Simulate using distributed decoupling analysis.
a. Select Simulate PI > Analyze Decoupling. The Decoupling Wizard opens.
b. Perform the steps in the Decoupling Wizard. Read the wizard page text to help you
set up the simulation.
You can use include or exclude from analysis the series inductance that is unique to IC
power-supply pins.
• Exclude this series inductance to focus on decoupling capacitor placement and
values.
• After optimizing decoupling capacitors, include this series inductance to focus on
the effects of IC power-supply pin mounting.
10. View results. Is the impedance profile below the target impedance? If yes, the analysis is
complete. If no, make changes to decoupling capacitor models and stackup and re-run
distributed analysis.
Use the Remove series inductance unique to each power pin, to see plane decoupling
more clearly option in the Decoupling Wizard - Customize Settings Page to exclude or
include this series inductance.

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Running Decoupling Analysis

Related Topics
“Analyzing Decoupling”
“Setting Up Designs for Power-Integrity Simulation” on page 341
“Defining the Power-Distribution Network”

Running Decoupling Analysis

Use the Decoupling Wizard to set up and run analysis. Decoupling analysis runs on one pair of
power-supply nets at a time, where one net provides power and the other provides return
current. For ICs with multiple pairs of power-supply nets, you run the Decoupling Wizard
multiple times, once for each pair of power-supply nets that draws significant power.

Decoupling analysis takes into account only the geometries and connectivity associated with the
PDN. It does not take into account signal-integrity structures and components, such as
transmission lines, signal vias, and IC buffer models.

Prerequisites
Before running decoupling analysis, verify the design setup and model assignments. See
“Setting Up Designs for Power-Integrity Simulation” on page 341.

Procedure
1. Select Simulate PI > Analyze Decoupling. The Decoupling Wizard opens.
2. On each wizard page, edit options and values as needed. Navigate among wizard pages
by clicking one of the following:
• Back/Next—Go to the previous/following page.
• <wizard_page_name> in the table of contents pane—Jump directly to the named
page. See “About the Decoupling Wizard Table of Contents Pane” on page 1027.
3. Repeat step 2 as needed to continue through the wizard.
4. In the last page, click Run Analysis.
The Run Analysis button (to the right of the Next button) displays other labels,
depending on the completeness of the setup data and whether you chose (on the Start
Analysis or Run Analysis page) to save the wizard settings to a file.
5. When analysis is complete, one of the following opens:
• Touchstone Viewer—Displays the Z-parameter file representing the impedance over
a frequency range for the pair of power-supply nets. See “Zooming Panning and
Other Curve-Examination Tools” on page 1075.

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• Reporter—Displays a link to the spreadsheet containing information about the

mounting quality of decoupling capacitors on the pair of power-supply nets. See
“Reporter Dialog Box” on page 1834 and “Decoupling Capacitor Report
Spreadsheets” on page 1031.

Related Topics
“Data Flow for Decoupling Analysis” on page 1027

“Analyzing Decoupling” on page 1013

About the Decoupling Wizard Table of Contents Pane

You can navigate directly to a wizard page by clicking its name in the table of contents pane,
which is located near the left side of each wizard dialog box.

The color of a non-highlighted page name indicates the following:

• White—All required information is specified.

• Red—Some required information is not specified.
• Gray—Similar to red, some required information is not specified. Gray is used when
information on a previous page is missing or, on the first wizard page, you click the
Load Saved Configuration option, but have not yet specified a file.

Data Flow for Decoupling Analysis

Figure 23-3 on page 1028 shows the main data inputs and outputs for decoupling analysis. For
information about output file names and contents, see Table 23-1 on page 1028. All files are
located in the <design> folder. See “About Design Folder Locations” on page 1391.

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Data Flow for Decoupling Analysis

Figure 23-3. Decoupling Analysis Data Flow

Table 23-1. Decoupling Analysis Output Files

File Description
Z-parameter file— Shows the impedance of the pair of power-supply
<design>_<analysis_iteration>.z<number nets over a frequency range.
_of_ports>p
Use the Touchstone Viewer to view Z-parameter
Restriction: Quick analysis does not files. See “Viewing and Converting Touchstone and
create this file. Fitted-Poles Models” on page 1065.

The file name is of form

<design>_<analysis_iteration>.z<number_of_ports
>p, where:
• design—name of the board or free-form
schematic
• <analysis_iteration>—starts at “empty” and
increments by one for each export. For example,
design_.z1p and design_1.z1p.
• <number_of_ports>—“1” for lumped analysis
and the number of probed ports for distributed
analysis

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Table 23-1. Decoupling Analysis Output Files (cont.)

File Description
Port-to-component pin mapping file— Maps Touchstone model ports to component pins.
<design>_<analysis_iteration>.z<number
_of_ports>p.ports The file name is of form
<design>_<analysis_iteration>.z<number_of_ports
Restriction: Quick and lumped analyses >p, where:
do not create this file. • design—name of the board or free-form
schematic
• <analysis_iteration>—starts at “empty” and
increments by one for each export. For example,
design_.z1p and design_1.z1p.
• <number_of_ports>—Number of probed ports
for distributed analysis
Power-integrity wizard options file— Contains settings for the Decoupling Wizard.
<design>.dao (optional)
Log file—DW.log Contains information produced by the analysis
engine.

Use the Reporter Dialog Box to view analysis log

files in order to investigate analysis failures or
unexpected results.

The decoupling capacitor spreadsheet also contains

information that can help investigate analysis
failures or unexpected results.
Decoupling capacitor report Contains mounting quality, inductance, and
spreadsheet—<design>_1.xls or resonant frequency information.
<design>_1.csv
The Reporter Dialog Box automatically displays a
Restriction: Lumped and distributed link to the spreadsheet file.
analyses do not create this file.
The file name is of form <design>_1.xls, where
design—name of the board or free-form schematic.

See “Decoupling Capacitor Report Spreadsheets”

on page 1031.

Circuit Topology for Lumped Decoupling

Analysis
Figure 23-4 on page 1030 shows the circuit topology for lumped decoupling analysis. The
topology also includes VRM models.

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Figure 23-4. Lumped Decoupling Analysis - Circuit Topology

Settings in the Customize Settings page can exclude certain design elements, such as inter-plane
capacitance, from the circuit topology. See “Decoupling Wizard - Customize Settings Page” on
page 1514.

Circuit Topology for Distributed Decoupling

Analysis
Figure 23-5 on page 1030 shows the circuit topology for distributed decoupling analysis. The
transmission-plane distributed model contains the inter-plane capacitance and the mounting
inductance for decoupling capacitors, which includes the effects of vias and traces used to
connect decoupling capacitors to the transmission plane. The topology also includes VRM
models.

Figure 23-5. Distributed Decoupling Analysis - Circuit Topology

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Decoupling Capacitor Report Spreadsheets

Decoupling analysis can create a spreadsheet that reports decoupling capacitor information,
such as mounting impedance and resonant frequency, for the pair of power-supply nets. You
can use this information to judge the effectiveness of individual decoupling capacitors.

To create the decoupling capacitor spreadsheet, enable the Quick Analysis option on the Choose
a Type of Analysis wizard page. See “Decoupling Wizard - Choose a Type of Analysis Page”
on page 1508.

Table 23-2 defines spreadsheet column headings. For each capacitor for the pair of power-
supply nets, the spreadsheet either reports detailed electrical information or why the capacitor
was excluded from the analysis model.

Table 23-2. Decoupling Capacitor Spreadsheet Column Definitions

Column Name Definition
Capacitor Reference designator for decoupling capacitor.
Model C-L-R values or name of the assigned SPICE or
Touchstone model.
Value, uF The value comes from assignments you make in the
Assign / Edit Capacitor Model Dialog Box.

If you assigned a C-L-R model to the capacitor, the

capacitance is displayed.

If you assigned a Touchstone or SPICE model to the

capacitor, “N/A” is displayed.

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Table 23-2. Decoupling Capacitor Spreadsheet Column Definitions (cont.)

Column Name Definition
Mounting Quality One of the following values:
• Good—Total mounting inductance, including both
trace segments and vias, is less than 1.92 nH. When
using simple C-L-R models, ESL from the model is
added to the total mounting inductance.
• Marginal—Total mounting inductance is 1.92 nH
or more, but the length of the longest mounting path
for at least one decoupling capacitor pin is less than
or equal to 5 millimeters or 197 mils. When using
simple C-L-R models, ESL from the model is added
to the total mounting inductance.

Note: Even capacitors with low mounting

inductance can be judged to be marginal, because of
ESL contributed by the model.

• Low-frequency—The length of the mounting path

for at least one decoupling capacitor pin is at least 5
millimeters or 197 mils. Distributed decoupling
analysis will not use this capacitor, but lumped
decoupling analysis will.
• Poor—For BoardSim only, the capacitor has a pin
that connects to PDN metal without using vias. This
can happen for capacitors with surface mounted
device (SMD) pins. Decoupling analysis will
attempt to find some via connection to the closest
area of the power-supply net.
• Rejected—The Reject Reason column provides
details.
Total Mounting Inductance, nH Sum of the next two columns.

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Table 23-2. Decoupling Capacitor Spreadsheet Column Definitions (cont.)

Column Name Definition
Mounting Inductance from Vias, nH The inductance of the vias used to mount the capacitor
to the board. Decoupling analysis attempts to account
for all vias connected to all capacitor pins by trace
segments or directly by pad shapes for via-in-pad
connections. Even surface-mounted capacitors often
connect to the PDN with tiny networks containing vias
and trace segments.

To provide some insight about how mounting

inductance is calculated, let us consider a capacitor that
has two pins, is mounted on top of the board (layer
Top), and connects to stackup layers Inner1 (which is
closest to layer Top) and Inner2. Differential via
inductance is calculated for the pair of differential vias
formed by the pin connected to layer Inner1 and the
portion of the other pin between layers Top and Inner1.
“Effective” single-ended via inductance is calculated
using the distributed model for the portion of the via
located between layers Inner1 and Inner2. The reported
mounting inductance is the sum of the differential via
inductance and effective single-ended via inductance
values. Capacitors mounted in more complex ways
require more complex calculations.
Mounting Inductance from Traces, The inductance of the trace segments used to mount the
nH capacitor to the board.
ESL, nH The value comes from assignments you make in the
Assign / Edit Capacitor Model Dialog Box.

If you assigned a C-L-R model to the capacitor, the

equivalent series inductance value is displayed.

If you assigned a Touchstone or SPICE model to the

capacitor, “N/A” is displayed.

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Table 23-2. Decoupling Capacitor Spreadsheet Column Definitions (cont.)

Column Name Definition
Actual Resonance Frequency, MHz If you assigned a C-L-R model to the capacitor, the
resonant frequency value is displayed. See “Assign /
Edit Capacitor Model Dialog Box” on page 1442.

The value comes from the following equation:

1
F = -------------------------------
2 × π × LC

where L is the sum of the values in the Mounting

Inductance from Vias, nH, Mounting Inductance from
Traces, nH, and ESL, nH columns.

If you assigned a Touchstone or SPICE model to the

capacitor, “N/A” is displayed.
Resonance Frequency w/o Mounting, Same as the Actual Resonance Frequency, MHz
MHz column, except the equation uses only the L from the
ESL, nH column.
Reject Reason Identifies why the capacitor is excluded from the
analysis circuit. See “Summary of Reject Reasons for
Decoupling Capacitor Spreadsheets” on page 1034.

Summary of Reject Reasons for Decoupling Capacitor

Spreadsheets
This topic contains a partial list of reasons that capacitors are excluded from the analysis circuit.
In some cases, the log file provides additional design-specific details. See “Data Flow for
Decoupling Analysis” on page 1027.

Values in the Reject Reason column of the decoupling capacitor spreadsheet can include the
following:

• Failed to create decoupling capacitor model; decoupling capacitor omitted

Cannot find transmission planes or capacitor has incorrect circuit connections.
• Failed to initialize decoupling circuit
The circuit file (including the circuit created by HyperLynx SI-SPICE or a Touchstone
model) is incorrect.

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• File name is not specified for model

The filename is not specified for the SPICE or Touchstone model. Usually appears if
you manually edit the schematic (.FFS) or BoardSim user session (.BUD) file.
• Model file isn't found
File specified for SPICE or Touchstone model is not located in the model-library file
paths defined in the Select Directories for IC-Model Files Dialog Box.
• Cannot find Decoupling Model
File specified for SPICE or Touchstone model is not located in the model-library file
paths defined in the Select Directories for IC-Model Files Dialog Box.
• Decoupling capacitor <name> is connected to only one net
All pins of the decoupling capacitor connect to the same power-supply net.
• Decoupling capacitor <name> is connected to more then two nets
Capacitor with three or more pins connects to three or more power-supply nets.
• Vias of decoupling array are connected to <number> nets
In LineSim, capacitors in the array can connect to only two power-supply nets.
• Cannot find pin <reference_designator>.<pin> in model
For SPICE and Touchstone models with three or more pins/ports, the pin-to-port
mapping does not contain a given pin. This may happen if model file was changed after
it had been assigned.
• Cannot determine model node-to-pin mapping
Usually appears if you manually edit the schematic (.FFS) or BoardSim user session
(.BUD) file.
• Decoupling Model is disabled
Decoupling capacitor/group is temporally disabled in a power-integrity wizard page or
in the Assign Decoupling-Capacitor Models Dialog Box (BoardSim only).
• Invalid Decoupling Model
May happen if the SPICE or Touchstone model file changes after it was assigned.
• Non-compatible Decoupling Model
A simple C-L-R model has been assigned to a capacitor with more than two pins, or a
SPICE or Touchstone file has the wrong number of ports or nodes. Usually appears if
you manually edit the schematic (.FFS) or BoardSim user session (.BUD) file.
• Wrong padstack and connection data

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Analyzing Decoupling
Decoupling Capacitor Report Spreadsheets

In LineSim only, the padstack specified for the via does not allow connections to this
layer.
• Wrong layer data
In LineSim only, this message usually appears if you manually edit the schematic (.FFS)
file.
• Pin <reference_designator>.<pin> is connected to metal with high-inductance, low-
frequency connection
This capacitor is omitted for distributed analysis and lumped analysis.

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 Chapter 24
Simulating Plane Noise

Plane-noise simulation shows how noise propagates across plane regions of the power-
distribution network (PDN) when IC power-supply pins draw large amounts of transient
current. Plane-noise simulation applies a current pulse to one or more IC power-supply pins to
imitate the large currents required for I/O or core logic switching, and then reports the voltage
difference between transmission-plane layers at all X/Y locations of the board. See “About
Transmission Planes” on page 1373.

The HyperLynx PI PowerScope Dialog Box displays plane-noise results in a three-dimensional

(3-D) form. As simulation runs, you can see how noise voltage varies in time across the PDN.
When simulation completes, the HyperLynx PI PowerScope displays the maximum plane-noise
voltages across the PDN. The 3-D plot can help identify PDN locations that need more
decoupling capacitors (or possibly less-inductive mounting for existing capacitors) by making it
easy to see “hot spots” on the board and to visualize the effectiveness of specific decoupling
capacitors. You can save the 3-D plot to a file for later viewing.

The HyperLynx PI PowerScope also reports the maximum plane noise voltage in text form.
Excessive plane noise can offset the localized voltage on a IC power-supply pin so much that a
receiver pin connected to it can switch logic state, even when the driver voltage is held constant.

You can simulate plane-noise on pre- and post-layout designs. Perform “what if” experiments
on post-layout designs by exporting the power-distribution network from BoardSim (you do not
have to select a signal net) to a free-form schematic and editing it in the PDN Editor.

Note
Before running plane-noise simulation, you should run decoupling analysis to verify that
the PDN impedance satisfies the target impedance requirements. See “Analyzing
Decoupling” on page 1013.

If the PDN impedance is too high, it is possible that simulated plane-noise voltages will
be too high and exceed the voltage ripple requirements.

If you observe high plane-noise voltage, you may have to modify the PDN design to
lower its impedance, run decoupling analysis to verify the PDN impedance profiles meet
the target impedance requirements, and re-rerun plane-noise simulation.

Restrictions:

• The Plane Noise license is required to run plane-noise simulation.

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Simulating Plane Noise

• In BoardSim, plane noise simulation does not include power-supply nets formed entirely
by trace segments.
• Plane-noise simulation is unavailable when a MultiBoard project is loaded.
This topic contains the following:

• “Plane Noise Simulation QuickStart - BoardSim” on page 1039

• “Plane Noise Simulation QuickStart - LineSim” on page 1041
• “Running Plane-Noise Simulation - LineSim” on page 1042
• “Running Plane-Noise Simulation - BoardSim” on page 1043
• “Example Plane-Noise Simulation Results” on page 1045

Related Topics
“Run HyperLynx with a Lower Priority” on page 1409

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February 2012
 Simulating Plane Noise
Plane Noise Simulation QuickStart - BoardSim

Plane Noise Simulation QuickStart - BoardSim

Plane-noise simulation shows how noise propagates across plane regions of the power-
distribution network (PDN) when power-supply pins draw large amounts of transient current.
Plane-noise simulation applies a current pulse to one or more IC power-supply pins to imitate
the large currents required for I/O or core logic switching, and then reports the layer-to-layer
voltage difference at all X/Y locations across the transmission plane. It also reports surface and
capacitor currents across the transmission plane. See “About Transmission Planes” on
page 1373.

The HyperLynx PI PowerScope Dialog Box displays plane-noise results in 3-D and text forms.
The 3-D plot makes it easy to see “hot spots” on the board and to visualize the effectiveness of
specific decoupling capacitors. You can save the 3-D plot to a file for later viewing. The text
reports the maximum noise voltage.

Prerequisites
• Run decoupling analysis before running plane noise simulation. See “Decoupling
Analysis QuickStart - BoardSim” on page 1014.
• Use a design that is already setup for decoupling analysis. See “Decoupling Analysis
QuickStart - BoardSim” on page 1014.
• The Plane Noise license is required to run plane noise simulation.
• Plane noise is unavailable when a MultiBoard project is loaded.

Figure 24-1. Plane Noise Simulation - BoardSim Task Flow

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Simulating Plane Noise
Plane Noise Simulation QuickStart - BoardSim

Procedure
This procedure assumes that you have already set up the design for distributed decoupling
analysis, have run distributed decoupling analysis, and have gotten good results. See
“Decoupling Analysis QuickStart - BoardSim” on page 1014.

1. Open a BoardSim board.

• Select File > Open Board. See “Creating BoardSim Boards“.
2. Simulate.
a. Select Simulate PI > Run Plane-Noise Simulation. The Plane Noise Analysis
dialog opens. See “Plane Noise Simulation QuickStart - BoardSim” on page 1039.
b. Select a power-supply net to analyze.
c. In the Simulation Time box, type the simulation time, in ns.
The default stop time is usually adequate for AC models with a rising edge or single
pulse current waveform. However if you repeat the stimulus, specify an initial delay
or wide pulse, or specify double pulses, you may need to increase the simulation
time to make sure simulation reports the maximum-amplitude plane noise.
d. Click Run Analysis.
3. View results.
• The HyperLynx PI PowerScope Dialog Box displays graphical and text simulation
results. See “Example Plane-Noise Simulation Results“.
4. Repeat steps 2-3 to simulate additional power-supply nets.
5. Export the selected net and board info to LineSim to fix problems.
a. Select Export > Net to > Free-Form Schematic. The Export to LineSim Free-Form
Schematic dialog box opens.
b. Select the Export to PDN Editor check box.
c. From the Supply list, select the power-supply nets to export.
d. Click Export. The exported net along with PDN information opens in LineSim.
e. Make changes in the PDN Editor and re-run the analysis. See “Plane Noise
Simulation QuickStart - LineSim” on page 1041.

Related Topics
“Simulating Plane Noise“

“Setting Up Designs for Power-Integrity Simulation” on page 341

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 Simulating Plane Noise
Plane Noise Simulation QuickStart - LineSim

Plane Noise Simulation QuickStart - LineSim

Plane-noise simulation shows how noise propagates across plane regions of the power-
distribution network (PDN) when IC power-supply pins draw large amounts of transient
current. Plane-noise simulation applies a current pulse to one or more IC power-supply pins to
imitate the large currents required for I/O or core logic switching, and then reports the layer-to-
layer voltage difference at all X/Y locations across the transmission plane. It also reports
surface and capacitor currents across the transmission plane. See “About Transmission Planes”
on page 1373.

The HyperLynx PI PowerScope Dialog Box displays plane-noise results in 3-D and text forms.
The 3-D plot makes it easy to see “hot spots” on the board and to visualize the effectiveness of
specific decoupling capacitors. You can save the 3-D plot to a file for later viewing. The text
reports the maximum noise voltage.

Requirements
• Run decoupling analysis before running plane noise simulation. See “Decoupling
Analysis QuickStart - LineSim” on page 1019.
• Use a design that is already set up for decoupling analysis. See “Decoupling Analysis
QuickStart - LineSim” on page 1019.
• The Plane Noise license is required to run plane noise simulation.

Figure 24-2. Plane Noise SImulation - LineSim Task Flow

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Simulating Plane Noise
Running Plane-Noise Simulation - LineSim

Procedure
This procedure assumes that you have already set up the design for distributed decoupling
analysis, have run distributed decoupling analysis, and have gotten good results. See
“Decoupling Analysis QuickStart - LineSim” on page 1019.

1. Open the schematic and PDN layout.

• Select File > Open Schematic.
Restriction: If you do not have a power-integrity license, the PDN Editor does not
appear when you open a free-form schematic.
2. Simulate.
a. Select Simulate PI > Run Plane-Noise Simulation. The HyperLynx PI
PowerScope Dialog Box dialog box opens.
b. Click Start Simulation.
3. View results.
• The HyperLynx PI PowerScope displays graphical and text simulation results. See
“Example Plane-Noise Simulation Results“.

Related Topics
“Simulating Plane Noise“
“Setting Up Designs for Power-Integrity Simulation” on page 341
“Defining the Power-Distribution Network”

Running Plane-Noise Simulation - LineSim

Before running plane-noise simulation, verify the design setup and model assignments. See
“Setting Up Designs for Power-Integrity Simulation” on page 341.

Restriction: Each stackup layer in LineSim can have only one net name. If the design has more
than one power-supply net on a stackup layer, you must create a design for each net that you
plan to simulate, where each design implements one power-supply net on the layer.

To run plane-noise simulation:

1. Click Run Plane-Noise Simulation or select Simulate PI > Run Plane-Noise

Simulation.
The HyperLynx PI PowerScope Dialog Box dialog box opens.
2. In the Stop field, type the simulation time, in ns.

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 Simulating Plane Noise
Running Plane-Noise Simulation - BoardSim

The default stop time is usually adequate for AC models with a rising edge or single
pulse current waveform. However if you repeat the stimulus, specify an initial delay or
wide pulse, or specify double pulses, you may need to increase the stop time to make
sure simulation captures the maximum-amplitude plane noise.
The value in the Stop box has precedence over the period length (for pulse signal types)
in the AC model. For example, if the AC model contains a repeating current waveform
that extends beyond the simulation time, the current waveform is truncated.
3. Click Start Simulation.
The HyperLynx PI PowerScope Dialog Box displays graphical and numerical
simulation results.
For simulation troubleshooting purposes you can use the Reporter dialog box to display
simulation information and warning messages. The Reporter Dialog Box reads the
SSN.log file located in the <design> folder. See “About Design Folder Locations” on
page 1391.
4. To view the graphical results at a later time, click Save to save the 3-D plot to a
transmission-plane simulation (.TPS) file located in the <design> folder.
The .TPS file contains information for one transmission-plane. If multiple transmission
planes exist, click the PowerScope tab to choose which set of data to save to the .TPS
file. See “About Transmission Planes” on page 1373.

Related Topics
“Simulating Plane Noise” on page 1037

“Example Plane-Noise Simulation Results” on page 1045

Running Plane-Noise Simulation - BoardSim

Use the Plane Noise Analysis dialog box to choose a power-supply net to simulate, to assign AC
models and reference nets to power-supply pins, and to run plane-noise simulation. BoardSim
simulates plane noise for one selected power-supply net at a time.

Before running plane-noise simulation, verify that the list of power-supply nets is complete,
verify decoupling-capacitor model values, and assign both AC models and reference planes to
each power-supply net you simulate. See “Setting Up Designs for Power-Integrity Simulation”
on page 341.

Restriction: While power-supply nets routed with trace segments are simulated, only the report
file describes their behavior and the HyperLynx PI PowerScope does not display 3-D plots for
them.

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Simulating Plane Noise
Running Plane-Noise Simulation - BoardSim

Procedure
1. Click Run Plane-Noise Simulation or select Simulate PI menu > Run Plane-
Noise Simulation.
The Plane Noise Analysis dialog box opens.
2. In the Select Supply Net To Analyze list, select a power-supply net to choose it for
simulation and display its existing AC model assignments in the Assigned Models list.
3. If models are missing, click Assign to assign AC models and reference nets to
component pins on the selected power-supply net. The Assign Power Integrity Models
dialog box opens. See “Assigning Power-Integrity Models - BoardSim”.
4. To display component pins on the selected power-supply net without AC models, select
the Show All Pins check box. This capability provides a quick way to display all the
pins that can receive AC model assignments.
“<none>” means the pin has no model.
5. In the Simulation Time box, type the simulation time, in ns.
The default stop time is usually adequate for AC models with a rising edge or single
pulse current waveform. However if you repeat the stimulus, specify an initial delay or
wide pulse, or specify double pulses, you may need to increase the simulation time to
make sure simulation reports the maximum-amplitude plane noise.
The value in the Simulation Time box has precedence over the period length (for pulse
signal types) in the AC model. For example, if the AC model contains a repeating
current waveform that extends beyond the simulation time, the current waveform is
truncated.
6. Click Run Analysis.
The HyperLynx PI PowerScope Dialog Box opens and displays graphical and numerical
simulation results.
For simulation troubleshooting purposes you can use the Reporter Dialog Box to display
simulation information and warning messages. The Reporter reads the SSN.log file
located in the <design> folder. See “About Design Folder Locations” on page 1391.
7. To view the graphical results at a later time, click Save to save the 3-D plot to a
transmission-plane simulation (.TPS) file located in the <design> folder.
The .TPS file contains information for one transmission-plane. If multiple transmission
planes exist, click the PowerScope tab to choose which set of data to save to the .TPS
file. See “About Transmission Planes” on page 1373.
8. Repeat steps 2-7 to simulate other power-supply nets.

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 Simulating Plane Noise
Example Plane-Noise Simulation Results

Related Topics
“Simulating Plane Noise” on page 1037

“Example Plane-Noise Simulation Results” on page 1045

Example Plane-Noise Simulation Results

This topic steps you through interpreting plane-noise simulation results for a very simple
design. This topic does not describe displacement current graphs.

This topic contains the following:

• “Plane Noise Example Design” on page 1045

• “Plane Noise Example Voltage Graphs” on page 1046
• “Plane Noise Example Current Graphs” on page 1048

Related Topics
“About Transmission Planes” on page 1373

Plane Noise Example Design

Figure 24-3 on page 1045 shows a deliberately-simple design in the PDN Editor with one IC
pin and two arrays of decoupling capacitors (C1-C4 and C5-C6). The design has one
transmission plane with both layers having the same geometry.

Figure 24-3. Plane Noise Example Design

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Simulating Plane Noise
Example Plane-Noise Simulation Results

Figure 24-4 on page 1046 shows a close up of two capacitor arrays (C1-C4, C5-C8), an IC pin
with an AC power-integrity model (U1.1), and an IC pin with a VRM model (U2.1).

The ToolTips display information about the power-integrity model(s) assigned to the
component pins in the PDN layout. To display ToolTips, point to the pin and wait. The PDN
Editor displays only one ToolTip at a time, but Figure 24-4 on page 1046 shows several
ToolTips at once.

Figure 24-4. Plane Noise Example Design - Zoomed In

Plane Noise Example Voltage Graphs

Figure 24-5 on page 1047 shows the graphical results for plane voltage noise displayed in the
HyperLynx PI PowerScope Dialog Box.

The HyperLynx PI PowerScope display is set to 2-D, which produces a “top down and flat”
display of the power-supply net geometries.

To display the ToolTip containing X/Y coordinates, simulation results, and model port
information, enable the HyperLynx PI PowerScope “Inspect” mode, and then point to the graph.

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 Simulating Plane Noise
Example Plane-Noise Simulation Results

Figure 24-5. Measuring Plane Voltage Noise - HyperLynx PI PowerScope 2-D

Table 24-1. Measuring Plane Voltage Noise - HyperLynx PI PowerScope 2D

Legend that maps the graph colors to the voltage difference at the
same X/Y coordinates between layers in the transmission plane.
Voltage values increase as the color shifts from blue to yellow.
IC pin with AC model.

To display the ToolTip containing X/Y coordinates, measured

voltage, and model port name (when available), enable the
HyperLynx PI PowerScope “Inspect” mode, and then point to the
pin.
Voltage difference at the same X/Y coordinates between layers
in the transmission plane. Voltage values are relative to the
origin set in the HyperLynx PI PowerScope.

Note the legend and this value have different number of

significant digits, so rounding is likely.

Figure 24-6 on page 1048 shows graphical results for plane noise displayed in the HyperLynx
PI PowerScope. The HyperLynx PI PowerScope display is set to 3-D, which displays the
voltage difference between the layers in the transmission plane in the Z axis (or height). You
can rotate the graph, and this particular orientation was chosen to emphasize the location of the
IC pin. Also notice the low voltages at the decoupling-capacitor locations.

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Simulating Plane Noise
Example Plane-Noise Simulation Results

Figure 24-6. Measuring Plane Voltage Noise - HyperLynx PI PowerScope 3-D

Plane Noise Example Current Graphs

Figure 24-7 on page 1049 shows the graphical results for surface and capacitor currents
displayed in the HyperLynx PI PowerScope. The HyperLynx PI PowerScope display is set to 2-
D, which produces a “top down and flat” display of the power-supply net geometries.

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 Simulating Plane Noise
Example Plane-Noise Simulation Results

Figure 24-7. Measuring Plane Surface and Capacitor Currents

Table 24-2. Measuring Plane Surface and Capacitor Currents

Current vectors that indicate current magnitude and direction.

Legend that maps the graph colors to the current magnitude on

both layers in the transmission plane.

Decoupling capacitor pin.

Short lines represent little current flow and may indicate the
capacitor is not helping to decoupling the transmission planes.
IC pin with AC model.

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Simulating Plane Noise
Example Plane-Noise Simulation Results

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 Analyzing Signal-Via Bypassing

Chapter 25
Analyzing Signal-Via Bypassing

Bypass analysis helps you evaluate the ability of the power-distribution network (PDN) to
provide low-impedance return current paths for signals transmitted through a single-ended via.
Signal-via bypassing analysis creates a Z-parameter model showing the return current
impedance across a frequency range. Values greater than several ohms indicate insufficient
bypassing. The Z-parameter model accounts for the effects of nearby stitching vias, bypass
capacitors, and interplane capacitance.

Bypass analysis runs on one signal via at a time. You can run bypass analysis additional times to
analyze other signal vias.

Bypass analysis runs on one pair of connected stackup layers at a time. If the signal via connects
to trace segments located on more than two stackup layers, you select which pair of stackup
layers to analyze. You can run bypass analysis additional times to analyze other stackup layer
pairs.

You can simulate signal-via bypassing on pre- and post-layout designs. Perform “what if”
experiments on post-layout designs by exporting the pair of power and ground nets from
BoardSim to a free-form schematic and editing it in the PDN Editor.

Note
For computers running on Windows or Linux, signal-via bypassing analysis runs on all
available cores.

For computers running on Solaris, signal-via bypassing analysis runs on one core.

Restrictions
• The Signal-Via Bypass Models license is required to run signal-via bypass analysis.
• In BoardSim, signal-via bypass analysis does not include power-supply nets formed
entirely by trace segments.
• Signal-via bypass modeling does not support differential signal-via pairs, although you
can create bypass models for individual vias in the via pair.
• You cannot export an S-parameter model for a signal via from a net in a free-form
schematic that contains a MOSFET (series bus switch) component.
• Signal-via bypass analysis is unavailable when a MultiBoard project is loaded.
This topic contains the following:

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Analyzing Signal-Via Bypassing
Data Flow for Signal-Via Bypass Analysis

• “Data Flow for Signal-Via Bypass Analysis” on page 1052

• “Running Signal-Via Bypass Analysis” on page 1053

Related Topics
“Setting Up Designs for Power-Integrity Simulation” on page 341
“Exporting Signal Vias to S-Parameter Models” on page 1180
“Run HyperLynx with a Lower Priority” on page 1409

Data Flow for Signal-Via Bypass Analysis

Figure 25-1 on page 1052 shows the main data inputs and outputs for bypass analysis. All files
are located in the <design> folder. See “About Design Folder Locations” on page 1391.

Figure 25-1. Bypass Analysis Data Flow

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 Analyzing Signal-Via Bypassing
Running Signal-Via Bypass Analysis

For information about output file names and contents, see Table 25-1 on page 1053.
Table 25-1. Bypass Analysis Output Files
File Description
Z-parameter file— Shows the impedance of the signal-via bypassing
<design>_<analysis_iteration>.z1p over a frequency range.

Use the Touchstone and Fitted-Poles Viewer to

view Z-parameter files. See “Viewing and
Converting Touchstone and Fitted-Poles Models”
on page 1065.

The file name is of form

<design>_<analysis_iteration>.z1p, where:
• design—name of the board or free-form
schematic
• <analysis_iteration>—starts at “empty” and
increments by one for each analysis. For
example, design_.z1p and design_1.z1p.
Power-integrity wizard options file— Contains settings for the Bypass Wizard.
<design>.dao (optional)
Log file—BW.log Contains information produced by the analysis
engine.

Use the Reporter Dialog Box to view analysis log

files in order to investigate analysis failures or
unexpected results.

Running Signal-Via Bypass Analysis

Use the Bypass Wizard to set up and run analysis.

Prerequisites
Before running signal-via bypass analysis, verify the design setup and model assignments. See
“Setting Up Designs for Power-Integrity Simulation” on page 341.

Procedure
1. Do any of the following:
• Select Simulate PI > Analyze Signal-Via Bypassing.
• From BoardSim, right-click via in the board viewer and select Run Bypass Wizard.
The Bypass Wizard opens.

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Analyzing Signal-Via Bypassing
Running Signal-Via Bypass Analysis

2. On each wizard page, edit options and values as needed. Navigate among wizard pages
by clicking one of the following:
• Back/Next—Go to the previous/following page.
• <wizard_page_name> in the table of contents pane—Jump directly to the named
page. See “About the Bypass Wizard Table of Contents Pane” on page 1054.
3. Repeat step 2 as needed to continue through the wizard.
4. In the last page, click Run Analysis.
The Run Analysis button (to the right of the Next button) displays other labels,
depending on the completeness of the setup data and whether you chose (on the Start
Analysis or Run Analysis page) to save the wizard settings to a file.
If you click Cancel, the Touchstone model contains all the results up to the frequency
point that was last calculated.
5. The Touchstone and Fitted-Poles Viewer automatically displays the exported Z-
parameter model.
See “Zooming Panning and Other Curve-Examination Tools” on page 1075.

Related Topics
“Data Flow for Signal-Via Bypass Analysis” on page 1052

“Analyzing Signal-Via Bypassing” on page 1051

About the Bypass Wizard Table of Contents Pane

You can navigate directly to a wizard page by clicking its name in the table of contents pane,
which is located near the left side of each wizard dialog box.

The color of a non-highlighted page name indicates the following:

• White—All required information is specified.

• Red—Some required information is not specified.
• Gray—Similar to red, some required information is not specified. Gray is used when
information on a previous page is missing or, on the first wizard page, you click the
Load Saved Configuration option, but have not yet specified a file.

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 Chapter 26
Viewing and Simulating Signal Vias

Use the Via Visualizer to display the electrical and geometric properties of a signal via or a pair
of coupled signal vias. This information can help you judge the effects of signal vias on signal
integrity.

Note
This chapter describes signal-via modeling that does not take the power-distribution
network (PDN) into account. See “Analyzing Signal-Via Bypassing“ and “Exporting
Signal Vias to S-Parameter Models“.

You can represent signal vias in free-form schematics with S-parameter models created
by 3-D electromagnetic simulators. See “Via Properties Dialog Box” on page 1908.

This topic contains the following:

• “Effects of Vias on Signal Integrity” on page 1055

• “Viewing Via Properties” on page 1056
• “What If Simulation Methods for Vias” on page 1058
• “Via Electrical Modeling” on page 1060

Effects of Vias on Signal Integrity

At "moderate" design frequencies, that is below 100-200 MHz, vias have a perceivable but not
significant effect on signal quality. A typical via may have less than 1 pF of capacitance and 1
pH of inductance, which is not a large disturbance to a driving signal, unless it has an extremely
fast slew time. By comparison, the presence of a receiver IC, which may have 5 pF of input
capacitance, midway along a net is usually more significant than the presence of a via.

However, several design practices and ever-higher operating frequencies can significantly
increase the negative effects of vias on signal integrity. Examples:

• The net is driven by extremely fast drivers, such as drivers with <300 ps slew time,
which introduces high frequencies into the switching waveforms. These fast signals are
electrically "shorter," that is their frequency components have shorter wavelengths than
in slower signals, and therefore even a structure as small as a via presents a noticeable
obstacle to signal propagation.

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Viewing and Simulating Signal Vias
Viewing Via Properties

• The net is routed on layers with different reference planes, which provide different
return-current paths for the signals. For high-speed signals, an impedance discontinuity
results when the signal is transmitted on traces with different reference planes.
• The net has a high number of vias, resulting in a significant cumulative effect. For
example, when an autorouter frequently switches routing layers as it struggles to
complete a very dense board.
• The net has abnormally large vias, such as vias with unusually large pads (resulting in
excess capacitance) or "long" vias due to a thick board stackup.
HyperLynx provides several ways to help you judge the effects of vias on signal integrity.

See also: “What If Simulation Methods for Vias” on page 1058

Related Topics
“Via Electrical Modeling” on page 1060

“Select Method of Simulating Vias Dialog Box” on page 1849

Viewing Via Properties

Use the Via Visualizer to display the electrical and geometric properties of the selected via, and
to export a SPICE netlist representing via electrical properties. You can use via properties to
help judge the effects of the via on propagation delay and signal integrity.

• The electrical properties represent the detailed model used for simulation.
• The geometric properties represent the via cross-section.
Requirement: The Via Models license is required to view via properties.

This topic contains the following:

• “Steps to View Via Properties” on page 1056

• “Coupled Vias in BoardSim” on page 1058
• “Warnings Reported by the Via Visualizer” on page 1058

Steps to View Via Properties

To view properties:

1. Verify the default rise/fall time, which determines the knee frequency and signal delay
reported by the Via Visualizer. See the Rise/Fall Time box on the General tab of the
Preferences dialog box. See “Preferences Dialog Box - General Tab” on page 1818.

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Viewing Via Properties

2. If you are using BoardSim, right-click over the via and click View Via Properties. Any
warnings appear in red text near the bottom of the Via Visualizer window.
Via electrical properties are approximate unless you enable the Auto-calculate option on
the Select Method of Simulating Vias dialog box. See “Select Method of Simulating
Vias Dialog Box” on page 1849.
The trace impedance is calculated using the trace width of the segment connecting to the
pad or barrel. The impedance value can be wrong if this trace width is not used by the
remainder of the trace.
If multiple traces on one signal layer connect to the via, impedance is displayed in the
form of XX-YY, where XX is the minimum impedance and YY is the maximum
impedance.
3. If you are using LineSim, double-click the via and, on the Via Properties dialog box,
click View. Any warnings appear in red text near the bottom of the Via Visualizer
window.
If multiple traces on one signal layer connect to the via, impedance is displayed in the
form of XX-YY, where XX is the minimum impedance and YY is the maximum
impedance.
Differential impedance is displayed below the padstack name for differential vias when
the ports connect to the same stackup layers. The value is two times the impedance value
of the transmission line displayed next to the via barrel/tube.
4. To change the appearance of the via, select any of the following check boxes:
• Draw proportionally—display the layers using proportional thicknesses
• Fit to window—display all of the via at once. This option can omit some property
labels.
• Use layer colors—display the layers using colors defined in the stackup editor
See also: “Creating and Editing Stackups” on page 353
5. To display from above the pad and antipad, right-click the pad and click View
TopView. Point to a shape to show its dimensions.
This option provides a way to display common anti-pads for differential vias in the Via
Visualizer. In BoardSim, you must enable Use common anti-pads for differential vias to
see common anti-pads.

6. To document the via properties, click any of the following options:

• Print—print the via properties image

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What If Simulation Methods for Vias

• Copy to Clip—copy the via properties image to the Windows Clipboard, so you can
paste it into another application such as Word or Wordpad
To include a comment with the print out or image, type the text into the Comment box.
7. To export the via electrical model to a SPICE netlist, click Export to SPICE, specify
the file and folder names, and then click Save.
8. To see the general via shapes on a specific stackup layer as though you were looking
down at the via, right-click the stackup layer and click View TopView.

Coupled Vias in BoardSim

If the selected via is adjacent to a via on a coupled, differential-pair, net that exceeds the
crosstalk threshold, the Via Visualizer displays both vias. If a third via is coupled to the selected
via, the selected via is not simulated with either of the coupled vias. The Via Visualizer reports
the condition and displays only the selected via.

Requirement: Crosstalk must be enabled to display coupled vias.

Warnings Reported by the Via Visualizer

The Via Visualizer reports impedance discontinuities and via stubs, both of which can degrade
signal integrity.

Via stubs exist when the via barrel extends beyond either of the following:

• BoardSim—Outermost signal layers used to implement traces for the selected net
• LineSim—Outermost stackup layers specified by the stackup or coupled stackup
transmission lines connected to the via

Related Topics
“Viewing and Simulating Signal Vias” on page 1055

What If Simulation Methods for Vias

You can perform "what if" investigations on vias using methods in Table 26-1.

Table 26-1. What If Simulation Methods for Vias

Method Description
“Including or Excluding Vias In BoardSim, choose whether to include or exclude vias
During Simulation” on during simulation, to help you judge whether they have an
page 1059 adverse effect on signal integrity of the net.

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What If Simulation Methods for Vias

Table 26-1. What If Simulation Methods for Vias (cont.)

“Select Method of Simulating In BoardSim, manually override the automatically
Vias Dialog Box” on page 1849 calculated L and C values for the padstack implementing
the via.
Model signal vias with S- In LineSim free-form schematics, assign S-parameter
parameter models models to represent a range of signal via geometries.

The idea is to create an S-parameter model for each

geometry you want to evaluate, assign it to the via, and
then run simulation. You create the S-parameter models
with HyperLynx 3D EM or an external 3-D
electromagnetic solver. See “Via Properties Dialog Box”
on page 1908.
Export vias as SPICE netlist Export the via electrical model to a SPICE netlist so you
can examine and modify via electrical models in another
See “Viewing Via Properties” simulation package.
on page 1056.

Related Topics
“Effects of Vias on Signal Integrity” on page 1055

Including or Excluding Vias During Simulation

To help you judge whether vias have an adverse effect on the signal integrity of the net, you can
run "what if" simulations by including or excluding vias from the electrical model used to
simulate the net. To view the effects of the via, run interactive simulation once with vias
included and then again with vias excluded. You can then compare the previous and current
simulation results.

In LineSim, you explicitly include or exclude vias when you define the schematic.

To include or exclude vias during simulation:

• Click Enable Via Modeling .

This button also updates the Include via L and C check box on the Select Method of Simulating
Vias Dialog Box.

Related Topics
“Select Method of Simulating Vias Dialog Box” on page 1849

“Effects of Vias on Signal Integrity” on page 1055

“Re-Simulating - Comparing Results” on page 594

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Via Electrical Modeling

Via Electrical Modeling

This section provides information about what via simulation takes into account and how a via
simulation model is produced.

This topic contains the following:

• “Physical Structure of Vias” on page 1060

• “Electrical Modeling Overview” on page 1061
• “Decomposing Vias Into Individual Physical Sections” on page 1061
• “Building the Via Simulation Model” on page 1063

Physical Structure of Vias

Vias are often used to connect traces or pins on one PCB stackup layer to traces or pins on
another, usually less congested, layer. There are several type of vias:

• Through-hole—Extends all the way through the board.

• Blind—Formed when only one end of the via is visible on the board surface.
• Buried—Formed when neither end of the via is visible on the board surface.
• Microvia—Miniature via that typically goes through only a few surface layers of the
board. Microvias do not change reference planes, do not have pads, and pass through
only very thin stackup layers. Because microvias do not have pads, they help route
traces to packages with closely-spaced pins.
Figure 26-1 shows the physical structure of a through-hole via on a board with four signal layers
(S1-S4) and two power plane layers (G1-G2).

Figure 26-1. Example Physical Structure of a Through-Hole Via

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Via Electrical Modeling

The barrel, or tube, is the central part of the via. It is created by drilling a hole through the board
and plating its walls, or filling the hole entirely, with copper or another conductive material. For
microvias, the hole is created by plasma-based, laser-based, or other processes.

Circular pads are often used to connect the barrel to traces on signal layers. Pads are sometimes
removed from vias transmitting differential signals.

Antipads, or annular clearances, are used to avoid connections with the poured power and
ground layers.

The layer span is the outermost pair of metal layers the via connects to or passes through. In
Figure 26-1, the layer span is S1-S4, even though no traces connect to the barrel.

A stub is any portion of the via that is not used to transmit signals on the selected net. Stubs are
formed when the barrel extends beyond the signal layers connecting to the via. In Figure 26-1, a
stub is formed by the via passing through layers G2 and S4 while traces connect only to layers
S1 and S3.

Electrical Modeling Overview

The Via Visualizer displays the electrical model used to simulate the selected via. HyperLynx
creates the electrical model by decomposing the physical via model into a set of individual
physical sections, converts each physical section into an electrical model, and then builds a
composite electrical model from the individual models.

Vias are treated differentially for via pairs whose nets exceed the crosstalk threshold. The Via
Visualizer displays both differential vias at the same time.

For very high frequency signals, stubs can be troublesome due to their resonant properties.
HyperLynx models via stubs with capacitances because it assumes the signal wavelength is
greater than the stub length. The Via Visualizer reports the existence of via stubs.

Via discontinuity occurs when the average via impedance is significantly different from the
impedance of any of the connected traces. The Via Visualizer reports the existence of
discontinuities caused by via impedance.

Decomposing Vias Into Individual Physical Sections

As a via passes through a high-speed PCB stackup, it passes through various signal and plane
layers. See Figure 26-2. A new via section is created each time any of the following conditions
is true:

• The via encounters a plane layer. The new via section persists until the next plane layer
is reached. For example, section 1 consists of the via section extending from layer S1 to
layer G1.

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Via Electrical Modeling

• The via passes through the thin plane layer. For example, section 2 consists of the via
section extending within layer G1.l

Figure 26-2. Via Sections When Traces on Layers S1 and S4 Connect to Barrel

Additional via sections are created when more than two traces connect to the barrel or when a
trace not on the top or bottom layer connects to the barrel. In these cases, a new via section is
created when the via passes through a signal layer that connects to the barrel.

Once the via is decomposed into physical sections, HyperLynx creates an electrical model for
each section.

Modeling Ambiguity for Widely-Spaced Radial Waveguides

Section 3 in Figure 26-2 consists of the via section lying between power plane layers G1 and
G2. When layers S2 and S3 do not connect to traces, the geometry of the via and power planes
form a widely spaced radial waveguide.

The accuracy of the electrical model HyperLynx creates for radial waveguides, especially for its
inductance predictions, depends on how well the board design observes the following
assumptions:

• All return current transitioning from plane-to-plane moves through the distributed
capacitance of the dielectric separating the planes
• No return current flows through nearby decoupling capacitors
• No return current flows through stitching vias
The above assumptions are reasonable for the following board properties:

• Decoupling capacitors are not placed very near the via

Or
Decoupling capacitors are placed very near the via, but the signal frequencies are
sufficiently high that the capacitors do not decouple effectively, due to their parasitic

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Via Electrical Modeling

inductances. This condition might happen for signaling frequencies above 400MHz or
so.
• The plane-to-plane separation is thin. This might happen when you try to maximize
plane-to-plane capacitance to compensate for the failure of decoupling capacitors.
The above assumptions may not be so good for the following board properties:

• A decoupling capacitor is placed very near the via, and the capacitor is connected or
mounted in such a way that its impedance is low for the signal frequencies of interest. A
decoupling capacitor might be located near the via accidentally or deliberately in order
to "bypass" the via.
• A stitching via is placed very near the via. This is possible only when the two planes are
at the same DC voltage.
• The plane-to-plane separation is thick, for example >20 mils. In this case, the via
electrical model overestimates the via inductance by assuming the current flowing
through the dielectric is very widely distributed, but it is likely to find a capacitor or
stitching via somewhere nearby to pass through. Note, however, that even a nearby
decoupling capacitor may not function effectively at higher signal frequencies.
If a via violates one or more of the assumptions above, the resulting model is conservative, that
is the via inductance is exaggerated. BoardSim should almost never claim that a via is OK when
it is not; it may sometimes warn about a via that is acceptable due to nearby bypassing, and so
on.

Modeling Ambiguity for Differential Vias

The electrical model HyperLynx creates for differential vias is optimized for differential
signaling. If the model is driven by common mode signaling, it will probably underestimate
inductance.

Common mode signaling can occur when you drive both differential pins in the same direction
or if the driver model has highly asymmetric rising and falling edge rates. Also, differential
signals on the board might contain some common mode content. However, well-designed
differential pairs should carry very little common-mode content.

Building the Via Simulation Model

The L and C for the electrical models representing the via sections are blended together into an
equivalent transmission line. However, the pad to plane capacitance for the signal entry and exit
trace layers is excluded from blending and is added to the transmission line model as lumped
capacitors connected to ground.

Since vias are electrically short compared to the primary wavelengths present in even very-
high-speed digital signals, the transmission-line representation is just as accurate as a pure
lumped model.

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Via Electrical Modeling

For vias that connect to three or more traces, additional equivalent transmission lines are created
so that every trace connecting to the barrel connects to a transmission line in the simulation
model.

Via Stub Capacitance

If a via contains a stub, its stub capacitance is added in the Via Visualizer to the lumped
capacitor representing the via entry- or exit-layer pad capacitance. Therefore, although it may
not appear as though the stub is modeled, it is because its effect is mixed with that of the
entry/exit capacitance.

Related Topics
“Effects of Vias on Signal Integrity” on page 1055

“Viewing Via Properties” on page 1056

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 Viewing and Converting Touchstone and Fitted-Poles Models

Chapter 27
Viewing and Converting Touchstone and Fitted-
Poles Models

Use the Touchstone and Fitted-Poles Viewer to judge the quality and understand the contents of
Touchstone and fitted-poles models. The Touchstone and Fitted-Poles Viewer reports model
information in the following forms:

• Potential causality and passivity errors

• Port-to-port frequency-response curves, such as magnitude, angle, and trajectory plot
• Port-to-port connectivity for Touchstone models only
You can load multiple models into the Touchstone and Fitted-Poles Viewer, which enables you
to compare models produced by different model-extraction options or representing variations of
a design.

You can convert an existing Touchstone model to another type (such as S-parameter to Z-
parameter), reduce the number of ports, and so on. You can also convert Touchstone models to
fitted-poles models, or vice versa.

Requirements:

• The Touchstone Viewer license is required to run the Touchstone and Fitted-Poles
Viewer.
• The Complex Pole Fitter license is required to run conversion tools from the Convert
menu.
This topic contains the following:

• “About Touchstone and Fitted-Poles Models” on page 1066

• “Opening Touchstone or Fitted-Poles Models” on page 1070
• “Checking and Fixing Passivity and Causality” on page 1071
• “Graphically Viewing Model Data” on page 1074
• “Reporting Connectivity Among Ports” on page 1080
• “Editing the Appearance of Curves and Legends” on page 1080
• “Checking S-Parameter Model Quality” on page 1082
• “Cascading Multiple S-Parameter Models in Series” on page 1105

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About Touchstone and Fitted-Poles Models

• “Converting and Fixing Touchstone and Fitted-Poles Models” on page 1115

• “Simulating S-Parameter Models in the Time Domain” on page 1116
• “Touchstone Viewer Dialog Boxes” on page 1117

Related Topics
“Exporting Nets to S-Parameter Models” on page 1152

About Touchstone and Fitted-Poles Models

Touchstone and fitted-poles models use n-port network parameter data to represent passive
interconnect networks and active devices. However understanding the quality or contents of
these models is difficult without help from analytic software, such as the Touchstone and Fitted-
Poles Viewer.

Touchstone models are in a format originally developed by Agilent Corporation and then
adopted by the EIA/IBIS Open Forum. Version 1.0 is supported.

You typically obtain Touchstone models from a component vendor or generate your own
models with a test bench and a vectored network analyzer (VNA).

Touchstone models containing S-, Y-, or Z-parameter data are often used to represent
equivalent circuits for backplane connectors and IC packages. Part of this popularity resulted
because VNAs make it relatively easy to collect n-port network parameter data for a circuit and
create a Touchstone model for it.

Fitted-poles models are in a proprietary format and represent Mentor Graphics preferred way to
simulate Touchstone S-parameter models. A fitted-poles model contains a set of complex
poles/residues representing frequency behavior in a semi-analytical way. You typically obtain
fitted-poles models by running an ADMS simulation, which automatically converts an S-
parameter model into a fitted-poles model to decrease simulation run time and model file
parsing time. You can manually obtain fitted-poles model using the Touchstone and Fitted-
Poles Viewer, which allows you to convert a Touchstone model into a fitted-poles model.

S-Parameter Port Numbering

On single-ended and differential nets, the ports of S-parameter models can have any ordering, as
long as the ordering of the ports in the S-parameter model follows the same sequence that the
HyperLynx LineSim schematic uses. The simulators and the Touchstone and Fitted-Poles
Viewer will automatically use the sequence specified in the schematic.

Touchstone models do not contain information to tell you how to associate the data sets they
contain with signal names on the circuit element or component which they describe.
Figure 27-1 shows the recommended ordering for the ports of an S-parameter model.

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About Touchstone and Fitted-Poles Models

Figure 27-1. Recommended S-Parameter Port Numbering

You can extend the recommended red numbering scheme to S-parameter models with more
than 4 ports.

The electrical significance of each S-parameter plot depends on the way you order the S-
parameter information. For example, the single mode S(2,1) S-parameter could be the
transmission coefficient (recommended), or the reflection coefficient (not recommended)
depending on how the information in the S-parameter file is ordered.

The descriptions for individual S-parameter plots in this document rely on the use of the
recommended port numbering scheme in Figure 27-1. If you use another scheme, you must
replace the S-parameter coefficients in the description in Table 27-1 with ones that match your
scheme.

Table 27-1 provides descriptions for the individual standard mode S-parameters corresponding
to an incident signal at port one.

The port numbering convention for S-parameters is S(<receive_port><stimulus_port>). The

responding port is always listed first. For example, S(2,1) represents the signal received at port
2 for the signal transmitted at port 1. This document uses a comma to separate the port numbers.

Note
The Touchstone and Fitted Poles Viewer display control grid always displays the
standard S-parameter descriptions.

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About Touchstone and Fitted-Poles Models

Table 27-1. S-Parameters for Differential Nets

Receive Port and Stimulus Means
Port Combination
S(1,1) Reflection coefficient; also know as return loss
S(2,1) Transmission loss; also known as insertion loss
S(3,1) Near-end or backward crosstalk
S(4,1) Far-end, or forward, crosstalk

Mixed Mode S-Parameters

To understand the performance of elements of differential nets, you should use mixed mode S-
parameters instead of standard mode S-parameters.

You can convert standard mode S-parameters to mixed-mode S-parameters using the Convert
Mode Dialog Box in the Touchstone and Fitted Poles Viewer.

Tip: It is important that the S-parameter port numbers in the convert mode dialog box
matches the numbering in the schematic and that you use the preferred port numbering
sequence.

If you use the recommended S-parameter port ordering, see Figure 27-1, the propagation of the
common mode signal and differential mode signal components of a signal are shown in
Figure 27-2.

Figure 27-2. S-Parameter Port Numbering for Mixed Mode S-Parameter Models

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About Touchstone and Fitted-Poles Models

The mixed mode S-parameters describe the propagation of the differential signal from port 1 to
port 2. In particular they describe the propagation and reflection of:

• the differential component of the signal, SDD(n,n)

• the common component of the signal, SCC(n,n)
• the component of the signal converted from differential mode to common mode,
SCD(n,n)
• the component of the signal converted from common mode to differential mode,
SDC(n,n)
Figure 27-3 shows all of the mixed mode parameters for a 4 port S-parameter element.

Figure 27-3. Mixed-mode S-Parameters for a 4 Port Model

The meaning of the individual S-parameter coefficients are similar to those of their standard S-
parameter equivalents. For signal originating at port 1:

• Differential Mode
o SDD(1, 1) — Differential mode reflection also known as return loss
o SDD(2, 1) — Differential mode transmission loss also known as insertion loss
• Common Mode
o SCC(1, 1) — Common mode reflection also known as return loss
o SCC(2, 1) — Common mode transmission loss also known as insertion loss
• Differential to Common Mode Conversion

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Opening Touchstone or Fitted-Poles Models

o SCD(1, 1) — Common mode reflection due to the forward differential mode signal
o SCD(2,1) — Common mode transmission due to the forward differential mode
signal
• Common to Differential Mode Conversion
o SDC(1, 1) — Differential mode reflection due to the forward common mode signal
o SDC(2, 1) — Differential mode transmission due to the forward common mode
signal
Looking at Figure 27-4, you can obtain the S-parameter propagation for signals originating at
port 2 by replacing 1 for 2 and 2 for 1 in all the descriptions above. For example, SDD(2,2) is
the differential mode reflection or return loss for signals originating at port 2.

The Touchstone and fitted poles viewer does not display the mixed-mode S-parameter
coefficients in its display control grid. For a 4 port S-parameter model, the grid will have 16
entries. You can use Figure 27-4 to select the correct grid square for a specific mixed-mode S-
parameter curve:

Figure 27-4. Mixed Mode S-Parameter Matrix

Opening Touchstone or Fitted-Poles Models

Use the Touchstone and Fitted-Poles Viewer to display and check the contents of Touchstone or
fitted-poles models.

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Checking and Fixing Passivity and Causality

Requirement: The Touchstone Viewer license is required to run the Touchstone and Fitted-
Poles Viewer.

To open Touchstone or fitted-poles models:

1. Select Models > Edit Touchstone Models or . The Touchstone and Fitted-Poles
Viewer opens.
This step applies to opening the Touchstone and Fitted-Poles Viewer from HyperLynx.
This documentation does not provide instructions to open the Touchstone and Fitted-
Poles Viewer from other Mentor Graphics products.
2. Do any of the following:
• Click Open Touchstone (SP) file or Open Fitted Poles (PLS) file ,
browse to the file > select one or more files > Open.
• Select File > Open Touchstone or Open Fitted Poles > browse to file > select one
or more files > Open.
• From a file manager, such as Windows Explorer, drag the file into the display area of
the viewer.
Restriction: Dragging files into the viewer is available only on computers running
Windows.
Restriction: The Touchstone and Fitted-Poles Viewer does not support Touchstone
models containing H- and G-parameters.
3. Repeat step 2 to open additional models.

Related Topics
“Checking S-Parameter Model Quality” on page 1082

Checking and Fixing Passivity and Causality

Use the Touchstone and Fitted-Poles Viewer to check and fix Touchstone and fitted-poles
models for passivity and causality errors.

Restriction: Passivity checking is valid only for S-parameter models.

This topic contains the following:

• “About Passivity and Causality Errors” on page 1072

• “Automatically Reporting Passivity and Causality Errors” on page 1073
• “Manually Reporting Passivity and Causality Errors” on page 1073

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Checking and Fixing Passivity and Causality

• “Fixing Passivity, Causality, and Symmetry Errors” on page 1073

Related Topics
“Checking S-Parameter Model Quality” on page 1082

About Passivity and Causality Errors

Passivity errors indicate that energy is created between ports on the model. For example, a
backplane connector is a passive component and its model should have passive behavior. The
passivity check looks across all the ports and reports an error if the sum of energy coming out of
the ports exceeds the energy going into one of the ports. The error can result from any number
of model-generation problems, including the following:

• Fixture and calibration errors in test bench or measurement equipment, such as a VNA
(vectored network analyzer)
• Limited fitting accuracy caused by insufficient resolution or non-causality of the
original sampled data
• Software used to extract the model may not have wide-band capabilities
Restrictions:

• Passivity checking is available only for Touchstone models containing S-parameters.

• Causality checking is unavailable for fitted-poles models. The fitted-poles model-
creation process enforces causality, producing models that are inherently causal.
Causality errors indicate a propagation speed faster than physics allow or a reversal in the phase
trajectory. Models with causality errors can produce simulator instability or incorrect delays.
The model may be inherently non-causal, in which case it should be re-created; or it may be
causal, but appear non-causal because it is not sampled with enough frequency points in some
regions, or contains numerical or measurement noise.

Model data can be slightly non-causal due to unavoidable measurement and simulation errors.
For example there may be insufficient frequency resolution in the sample, which typically
occurs at low frequencies because of using equidistant frequency points.

Even if no causality errors are reported, the model may still not be absolutely causal because the
Touchstone and Fitted-Poles Viewer does not perform an exhaustive causality check of the
sampled Touchstone data.

Tip: The fitted-poles model-creation process enforces causality, so fitted-poles models

are inherently causal.

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Checking and Fixing Passivity and Causality

To investigate errors, you can start by displaying model data in passivity plot curves (for
passivity errors) and trajectory plot curves (for causality errors).

See also: “Displaying Touchstone and Fitted-Poles Model Curves” on page 1074

Automatically Reporting Passivity and Causality Errors

The Touchstone and Fitted-Poles Viewer automatically checks passivity and causality when
you load the model. The Loaded Files area reports errors by displaying the file name in red
characters, followed by the error name(s).

The amount of time needed to evaluate a model for passivity and causality errors is short for
most models. However if your models take too long to process, you can disable the automatic
checking.

To disable automatic passivity and causality checking:

1. Edit menu > Options.

2. In the Files Loading tab, clear any of the check boxes and click OK.

Manually Reporting Passivity and Causality Errors

You can check the model for passivity and causality errors after the model is loaded. You might
want to do this if you disabled automatic checking when loading the files.

To manually check passivity and causality:

1. In the Loaded Files area, click the model name:

2. On the toolbar, click Perform Passivity Check or Perform Causality Check .
Alternative: In the Loaded Files area, right-click over the model name, point to Check,
and then click Passivity or Causality.

Fixing Passivity, Causality, and Symmetry Errors

To fix passivity and symmetry errors in a model, use the Convert > Correct Errors > Enforce
Passivity | Enforce Symmetry menu.

Converting a Touchstone model into a fitted-poles model fixes causality errors. To do this, use
the Convert > To Fitted Poles menu to convert the model to a fitted-poles model.

The Enforce Passivity option corrects poles/residues in such a way as to make the
approximation strictly passive.

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Graphically Viewing Model Data

Caution
Do not enforce passivity for active devices, such as amplifiers or active filters.

Note
The Enforce Symmetry option should only be used on a reciprocal network. This option
is unavailable when a fitted-poles model is loaded.

Graphically Viewing Model Data

Viewing model data as curves can help you understand the content of the numerical data and
judge the quality of the model.

This topic contains the following:

• “Displaying Touchstone and Fitted-Poles Model Curves” on page 1074

• “Zooming Panning and Other Curve-Examination Tools” on page 1075
• “Documenting Touchstone and Fitted-Poles Model Curves” on page 1079

Related Topics
“Checking S-Parameter Model Quality” on page 1082
“TDR Impedance Plot Dialog Box” on page 1133
“Time-Domain Response Dialog Box” on page 1142

Displaying Touchstone and Fitted-Poles Model Curves

You can display model data with several types of curves, making it easier to analyze model
behavior. Also, you can compare models representing variations of a design or models created
with different extraction options by opening all the models and overlaying their curves.

The Touchstone and Fitted-Poles Viewer can display Touchstone and PLS files simultaneously
because it is possible to synthesize the behavior of the poles at any frequency.

See also: “Opening Touchstone or Fitted-Poles Models” on page 1070

To display curves:

1. In the Loaded Files area, do any of the following:

• Select the check box for one or more models.

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If the models have a different number of ports, the size of the spreadsheet in the
Parameters area is the minimum number of ports among the loaded models.
• Click <All Files> to enable or disable elements in the Parameters spreadsheet for all
loaded files. While <All Files> provides the same behavior as selecting the check
box for every loaded file, it does not select the check boxes.
• If the check box for the model is already selected, click the model name to display its
Parameters spreadsheet.
2. In the Parameters spreadsheet, select the model ports for which you want to display
curves by doing any of the following:
• Select individual check boxes.
• Right-click over a check box and click an option.
If you have selected more than one model with the same number of ports, your
selections apply to all the models. This behavior can help you compare models more
easily.
If the Parameters area cannot fully display the spreadsheet and you do not want to scroll,
click the plus sign + button to the left of the spreadsheet to display it in a larger dialog
box.
3. Repeat steps 1-2 to display curves for additional models.
4. In the Display list, select any of the available curves.
Your own experience or education, such as an electrical engineer, will provide the best
guidance on how to choose and interpret curves. Briefly, magnitude represents
attenuation and angle represents phase shift.
See also: “Checking S-Parameter Model Quality” on page 1082
5. For fitted-poles models, specify the frequency range of the curves by using the boxes
and lists in the Full-fit Range area.
Restriction: For Touchstone models, the Full-fit Range area is read-only and displays
their frequency range.
Fitted-poles models do not contain frequency range information and you can display
their curves across a practically unlimited frequency range.
6. To help examine the curves, you can zoom, pan, change colors, and so on.
See also: “Zooming Panning and Other Curve-Examination Tools” on page 1075, “Editing the
Appearance of Curves and Legends” on page 1080

Zooming Panning and Other Curve-Examination Tools

You can adjust the chart to examine the curves more closely or make them easier to understand.

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This topic contains the following:

• “Zooming In” on page 1076

• “Fitting the Curve to the Window” on page 1076
• “Panning” on page 1076
• “Using Logarithmic Scales” on page 1076
• “Plotting Curves as Lines or Vertices” on page 1077
• “Adding Guidelines” on page 1078

Zooming In

Procedure
1. Right-click over the chart and click Zoom.
Alternative: Switch to Zoom mode button .
2. Drag the zoom rectangle to enclose the area you want to enlarge.

Fitting the Curve to the Window

After zooming in, you can again display the entire curve in the chart.

Procedure
• Right-click over the chart and click Fit to Window.
Alternative: Fit to Window button .

Panning
Panning moves the curves and X/Y axes across the chart without changing the magnification.

Procedure
1. Right-click over the chart and click Pan.
Alternative: Switch to Pan mode button .
2. Click anywhere in the chart and drag the curves to a new position.

Using Logarithmic Scales

For some types of curves, data are easier to understand when displayed on a logarithmic scale.

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Procedure
• Log scale X axis button or Log scale Y axis button .
Restriction: Logarithmic scales are unavailable if one or more curves contains negative values.

Plotting Curves as Lines or Vertices

You can plot curves as lines, vertices, or both.

Procedure
• View lines between vertices button or View vertices button .
Alternative: View menu > Lines or Vertices.

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Adding Guidelines
Add horizontal thresholds to the curve display to help you see curves that cross a limit. If you
specify one guideline point, the guideline is a straight line. If you specify multiple guideline
points, the guideline is a series of line segments. See Figure 27-5.

Figure 27-5. Guideline with Two Line Segments

Guidelines that you create will persist when you open different models. By contrast, when you
run decoupling analysis and create a Z-parameter model, its target Z value is displayed as an
<auto> guideline that is discarded when you close the model.

Procedure
1. Select View > Guidelines. The Manage Guidelines dialog box opens.
2. Click Add to create a new guideline. The Add/Edit Guideline dialog box opens.
A guideline consists of one or more guideline points, where each guideline point defines
the left end of a horizontal line segment and a Y-axis value. Figure 27-5 shows a

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guideline with the first guideline point located at 0 MHz and 0.0035 and the second
guideline point located at 20 MHz and 0.006.
3. Type frequency and Y-axis values for a guideline point, and then press <Enter>. Note
that the 0 MHz frequency value is read only.
A new spreadsheet row appears, ready to accept values for additional guideline points if
you want them.
Notes:
• The Value spreadsheet cell represents model data units and not display units. The
equation for Magnitude in DB display mode is Y(dB) = 20 * log(Y). For example, to
locate the guideline at -20 dB in the Magnitude in DB display mode, enter 0.1.
• When you open the Add/Edit Guideline dialog box to edit an existing guideline, a
blank row is not displayed at the bottom of the spreadsheet. In this case, you can add
a new row by clicking in the Value cell in the bottom row so that the cursor appears,
and then pressing <Enter>.
4. Close the dialog boxes.

Documenting Touchstone and Fitted-Poles Model Curves

You can record model curves by printing them or copying them as an image to the Windows
clipboard and pasting the contents of the clipboard into a document that can accept it, such as
Microsoft Word. This capability enables you to share the curves with other people or to
examine them at a later time.

This topic contains the following:

• “Copying Touchstone and Fitted-Poles Model Curves” on page 1079

• “Printing Touchstone and Fitted-Poles Model Curves” on page 1079

Copying Touchstone and Fitted-Poles Model Curves

To copy model curves to the Windows clipboard:

• Right-click over the chart and click Copy.

Alternative: Edit menu > Copy.

Printing Touchstone and Fitted-Poles Model Curves

To print model curves:

• Print chart button .

Alternative: File menu > Print.

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Reporting Connectivity Among Ports

Reporting Connectivity Among Ports

Since Touchstone models typically contain no port names or other helpful information about
how the model maps to the physical structure being modeled, it can be difficult to understand
even simple model properties, such as "which ports are directly connected to each other?"

The Touchstone and Fitted-Poles Viewer can identify ports on a Touchstone model (but not a
fitted-poles model) that connect to each other conductively at DC. This information can be
useful when you are connecting the model to a circuit in HyperLynx LineSim, but cannot access
the documentation indicating which ports connect directly to each other.

To identify connectivity among ports:

1. In the Loaded Files area, right-click over the model name and click Connectivity.
Alternative: Click the model name in the Loaded Files area and click View
Connectivity on the File menu.
Restriction: This capability is unavailable for fitted-poles models.
2. Click the port to view the ports it connects to and to report port-to-port connection
strength as one of the following:
• Strong—Ports probably have strong connectivity (magnitude of port-to-port signal
at DC is close to 1)
• Medium—Ports probably have medium connectitivy
• Weak—Ports probably do not connect or have minimal effect on each other

Editing the Appearance of Curves and Legends

You can change the appearance of the contents of the chart to make them easier to view or
improve printing legibility.

This topic contains the following:

• “Editing Curve Colors for the Current Session” on page 1080

• “Editing Default Curve Colors” on page 1081
• “Editing Chart Appearance Properties” on page 1081

Editing Curve Colors for the Current Session

To edit the color of curves for the current session:

1. In the Legend area, click the color square for the curve.

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2. Select the new color and click OK. The color is for the current session only and the
default color is applied when you next open the model file.

Editing Default Curve Colors

To edit the default color of curves:

1. Edit plot colors button .

Alternative: View menu > Colors.
2. Select the waveform type from the Data Type list.
Restriction: The Original options have no effect for this release.
3. Select the color scheme, or set, from the Color Scheme list.
4. Click Edit, edit the color scheme properties, and then click OK.
The color sequence is used to distinguish curves of the same type when multiple models
are open at the same time.
5. To manage the color schemes, for example add your own color scheme, click Organize,
manage the color schemes, and then click OK.
Result: The color scheme is applied to any currently-displayed curves, even if you
edited their color by performing the procedure in “Editing Curve Colors for the Current
Session” on page 1080.

Editing Chart Appearance Properties

You can change the legend font, chart colors (except for curves), and vertex size.

To edit chart appearance properties:

1. Edit menu > Options.

2. Click the Chart Control tab.
3. Edit properties as needed.
Vertex size is in pixels.

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Checking S-Parameter Model Quality

Checking S-Parameter Model Quality

S-parameter models are playing an increasingly major role in signal-integrity analysis and have
become the leading way to model connectors and IC packages, especially at SERDES-signaling
frequencies. However, many S-parameter models have serious quality problems and may give
erroneous or even unstable results during simulation.

The steps to check S-parameter model quality include loading the model into the Touchstone
and Fitted-Poles Viewer, displaying model data in a series of graphs, and then examining the
graphs for characteristics that indicate whether the model is good or bad. This topic describes
what to look for in the graphs, to help you judge the quality of an S-parameter model.

This topic contains the following:

• “Displaying S-Parameter Models Graphically” on page 1082

• “Example of a Good or High-Quality S-Parameter Model” on page 1082
• “Examples of Bad or Low-Quality S-Parameter Models” on page 1091

Related Topics
“Viewing and Converting Touchstone and Fitted-Poles Models” on page 1065

“Simulating S-Parameter Models in the Time Domain” on page 1116

Displaying S-Parameter Models Graphically

Because S-parameter models are in the Touchstone format, they appear incomprehensible when
viewed as text. What you see is a long, continuous listing of frequencies and associated complex
numbers, such as magnitude/angle and real/imaginary pairs, that describe the relationships
among the model ports. The Touchstone format is so minimal that port name syntax does not
exist and ports are simply numbered 1,2,…,N, based on their positions in the file.

Displaying the contents of Touchstone files in a graphical way can help you more easily
evaluate model quality. The Touchstone and Fitted-Poles Viewer can display the contents of
Touchstone files, including S-, Z-, and Y-parameter models, in several different graphs.

Example of a Good or High-Quality S-Parameter Model

A good S-parameter model has all of the following characteristics:

• “Sufficiently Wide Frequency Range” on page 1083

• “Proper Asymptotic Behavior at Zero and Infinite Frequency” on page 1084
• “Sufficient Resolution” on page 1084

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• “Proper Even and Odd Behavior” on page 1086

• “Causal Trajectory Plot” on page 1088
• “Passive Behavior” on page 1089

Sufficiently Wide Frequency Range

In a good model, the data range is broad and includes the frequencies of all important
resonances. If the model covers a wide frequency band, which is a requirement for digital
signaling, it should consist of data sampled at either of the following scales:

• Adaptive—varies the sampling step size depending on model characteristics

The adaptive scale is better than logarithmic because it increases the sampling rate near
frequencies with resonances.
• Logarithmic

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Figure 27-6 shows an S-parameter model with a frequency range of approximately 300 Hz to
100 GHz, with the real (pink) and imaginary (blue) portions of the S11 dependence.
Logarithmic sampling was used to provide sufficient resolution at low frequencies without
producing an overwhelming amount of data at high frequencies.

Figure 27-6. Real and Imaginary Portions of the S11 Dependence

Proper Asymptotic Behavior at Zero and Infinite Frequency

As previously noted, S-parameter data consists of a complex dependence (per port and between
ports) at each frequency. This dependence can be expressed as ,
with the real and imaginary parts displayed separately. In a good model, all dependencies
should tend asymptotically at low and high frequencies to purely real, which means the
imaginary portion should tend to zero.

Figure 27-6 shows the imaginary (blue) portion of S11 tends to zero at the lowest and highest
frequencies.

Sufficient Resolution
In a good model, even the sharpest resonances are represented with sufficient sampling
resolution. If you zoom in with the Touchstone and Fitted-Poles Viewer on sharp peaks or

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valleys in a dependence, many frequency points exist at each maximum/minimum. For

resonances with high-Q factors, this is possible only with adaptive sampling, which adds extra
points in the region of resonance.

Figure 27-7 and Figure 27-8 on page 1086 show that adaptive sampling provided sufficient
resolution for each resonance.

Figure 27-7. Two Resonances with Sufficient Resolution-Moderate Zoom

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Figure 27-8 shows that resonances have large numbers of frequency points, even at an extreme
zoom.

Figure 27-8. Two Resonances with Sufficient Resolution-Extreme Zoom

Proper Even and Odd Behavior

In a good model, the real part of a dependency is an even function of frequency [f(x) = f(-x)],
and the imaginary part is an odd function [f(x) = -f(-x)]. This means that the slope of the real
part at DC must be zero so that there is a smooth extension into negative frequencies. The value
itself may be non-zero. Conversely, the imaginary part can have non-zero slope, but must have
zero value. The dependence must have enough points defined near zero frequency to clearly
obey these requirements.

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Figure 27-9 shows a model dependency from about 70 MHz down to DC. As required, the real
portion (pink) approaches DC with zero slope, and the imaginary portion (blue) approaches DC
with zero value.

Figure 27-9. Proper Behavior of Real and Imaginary Parts of the Dependence

Technical Background on System Realness

Although you normally do not build the dependence for negative frequencies, you can. The
model time response, including impulse response, is a real function and the impulse response
and frequency-domain response are mutual Fourier transforms. If the inverse Fourier transform
of a complex frequency response is always a real function indicating system realness, then this
complex frequency response must obey the following special property:

• The real part of the dependence must be an even function of frequency

and
• The imaginary part must be an odd function
If this condition is satisfied, then the imaginary part of the inverse Fourier integral from minus
infinity to plus infinity becomes identically zero. Since these functions must also be continuous,
it immediately follows that all the following are true:

• Odd number (first, third, and so on) derivatives of the real part are zero
• Even number (zero, second,…) derivatives of the imaginary part are also zero

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Causal Trajectory Plot

In a good model, a trajectory plot (that is, a plot of imaginary versus real parts) of any
dependency shows a continuous and properly directed trajectory. Specifically, the trajectory
exhibits continual clockwise rotation, with resonances creating circles in the path. This is a
requirement if the model is causal. The trajectory starts and ends on the real axis because the
imaginary portion must tend to zero at DC and high frequencies, as required in “Proper Even
and Odd Behavior” on page 1086.

Figure 27-10 shows the trajectory plot corresponding to Figure 27-6 on page 1084. The starting
point of the trajectory is (-0.554, 0), and the end point is (1, 0). The path is always moving
clockwise.

Figure 27-10. Trajectory Plot with Clockwise Rotation

Technical Background on Causality

In the trajectory plot of a model dependency, each high-Q resonance creates an almost ideal
circle. By contrast, the overlap of several moderate resonances creates a more complicated
picture. For example, both of the following examples have clockwise trajectories:

• An isolated pair of complex conjugate poles creates a complete circle

• An isolated real pole creates a half-circle
Taken as a whole, the trajectory could be thought of as a composition of simple clockwise
rotations each with its own distinct center, radius, and speed. Sometimes the overlap of such

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rotations in some small isolated areas gives an impression of reverse or counterclockwise

movement. A well-known example is a cycloid, which is a composition of correct trajectories.

Why must a trajectory plot consist only of such proper, clockwise rotations? This property is
closely related to model causality, where cause must precede effect in the model behavior. A
realistic system can impose only positive delay. By contrast, a negative delay means the
response precedes the input, which cannot be physical. Locally, the delay can be defined
through "group delay," which is the derivative of the phase by frequency, negated. Clockwise
rotation produces positive group delay, while counterclockwise rotation makes negative delay.
Each cyclic component of the trajectory plot corresponds to a primitive time-domain impulse
response of the following form:

Each response, separately and any combination of such responses, thus obeys the following
requirement:

Thus, the sum of causal dependencies is a causal dependence. Less known is that the product of
causal dependencies is also causal. This is related to a property of convolution where you may
cascade several causal models and the signal propagating through all of them is properly
delayed. In the time domain, cascading means convolving impulse responses of the models, and
in the frequency domain it corresponds to finding their product, which must also remain causal.
The inverse is also true. If you multiply causal and non-causal frequency dependencies, the
product may well be non-causal.

Passive Behavior
In signal-integrity simulations, S-parameter models almost always represent interconnect
structures, which can dissipate energy but cannot produce energy (unlike an active device, such
as an amplifier). Thus, for an interconnect model, the passivity plot must be greater than zero at
all frequencies.

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Figure 27-11 shows the passivity plot corresponding to Figure 27-6 on page 1084. The value is
greater than zero at all frequencies. Note also that, unlike the previous plots shown, the passivity
graph is a property of the entire model and not a property of one of the model
dependencies/parameters, such as S11 or S21.

Figure 27-11. Good Passivity Plot

Comment on Passivity
Completely passive models can do any of the following:

• Absorb/dissipate active power. For example, a model of a resistor can transform input
energy into heat or radiate it.
• Reflect active power back into the surrounding circuit.
• Store input energy in an electric field, that is, an ideal capacitor, and then return it back
into the surrounding circuit.
• Store input energy in a magnetic field, that is, an ideal inductor, and then return it back
into the surrounding circuit.
Under no conditions can a passive model produce return energy exceeding the amount of energy
it has received.

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By contrast, non-passive models can produce energy. Sometimes non-passive models can cause
simulation instability in the form of voltages and currents that increase without limit. For
example, connected external resistances (losses) may be able to dissipate the surplus of energy
created by a non-passive model and thus prevent the total energy in the simulation from
growing. In another design using the same model, the surrounding circuitry may exhibit less
loss and allow the generated power to accumulate over time and lead eventually to instability.
Further, in an “in-between” case, the surplus of the energy may not be enough to cause obvious
instability, but be sufficient to make simulation results appear correct but actually be wrong.
Because of this unpredictability, non-passive S-parameter models are extremely dangerous and
should never be used in simulations.

For S parameters, the passivity function for the set of parameters A is defined as

where

'*' is the Hermitian transpose.

Examples of Bad or Low-Quality S-Parameter Models

A bad S-parameter model has any of the following characteristics:

• “Insufficient Data Range” on page 1092

• “Insufficient Resolution” on page 1097
• “Non-Ideal Asymptotic Behavior at DC” on page 1100
• “Inherent Non-Causality” on page 1103
• “Artificially Created and Modified Points” on page 1104

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Insufficient Data Range

Figure 27-12 shows a model defined from nearly DC to 20 GHz. If you are planning to simulate
a signal with a fundamental frequency of about 1.5 GHz and are convinced that little energy
exists in harmonics above 20 GHz, this model may look sufficient.

Figure 27-12. Insufficient Frequency Range

However, there is a problem with this model because its dependency above 20 GHz is
ambiguous. In a higher-quality version of the model, the dependency would continue upwards
in frequency until it was completely settled. Compare Figure 27-12 with Figure 27-6 on
page 1084. Recall the earlier requirement that in a good model, the imaginary part of the
dependency tend to zero at high frequency and DC. Figure 27-12 shows a non-zero value at
high frequencies.

Another problem with the model behavior illustrated by Figure 27-12 is a more mathematical
consideration. Ideally, you would create it from a perfect, infinite causal dependence by
multiplying the causal dependence by a rectangular window function (w(f) = 1 if f < 20 GHz;
w(f) = 0 otherwise). This rectangular function is most definitely non-causal because it would
have a straight-line trajectory plot. But as stated in “Technical Background on Causality” on
page 1088, the product of causal and non-causal models is non-causal and this is always true
except for trivial cases of models that are identically zero. Therefore, the truncated model in
Figure 27-12 is clearly non-causal if taken as is.

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If this model were simulated in a convolution-based simulator, some behavior above 20 GHz
would be imposed, but the exact behavior is unknown. For example, by applying inverse
Fourier transformation to the non-causal function in Figure 27-12 on page 1092, such a
simulator would get an impulse response that starts somewhere in negative time.
Programmatically, this negative portion of the response can be removed and not used in
convolution. However, such a mechanistic removal of the negative-time portion of the response
would affect the entire model in an unpredictable way. Transforming this truncated response
back into the frequency domain would result in a dependence quite different from the original.

By contrast, using Mentor Graphics complex pole fitting (CPF) based approach, you would first
fit the model to a set of complex poles and then, before simulating, you could compare the fitted
model to the original to see exactly what behaviors are being assumed outside the range of the
original model data. “Simulating S-Parameter Models in the Time Domain” on page 1116
describes CPF.

The fitted dependence must be a mathematically continuous function. It cannot be forced to

zero above 20 GHz. Nor should it be, since it is clear from Figure 27-12 on page 1092 that some
behavior occurs above that limit. But there is no data in the model to help define what the
behavior above 20 GHz should be, and the CPF fitter is forced to guess.

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Figure 27-13 shows the post-fit model, where the original (red, blue) and post-fit (pink, cyan)
dependencies overlay.

Figure 27-13. Overlaying Original and Post-Fit Dependencies of Previous Model

The Touchstone and Fitted-Poles Viewer supports simultaneously loading and displaying the
original S-parameter data and the fitted representation, so you can compare pre- and post-fit
data. The fitted representation is analytical, meaning that you can extend it to any frequency, to
understand its behavior outside the range of the original model. It is also guaranteed to be
causal, due to the natural by-product of the fitting process.

The fitted model may look good, but keep in mind that the behavior above 20 GHz is only
defined by the data given below 20 GHz. The behavior above 20 GHz is not unique, and the
extension process is uncontrollable. In particular, it is occasionally possible to have areas of
non-passivity in the extended frequencies above the original 20 GHz limit.

The dependence shown in Figure 27-13 is just a single matrix component in a 4x4 S-parameter
model. Each of the other components in the model has its own uncontrollable continuations
above 20 GHz. Since passivity is a property of the entire model, the combined effect from all
such components at high frequencies may be severe. On average, the effect becomes stronger
with increasing matrix size. Therefore, for larger matrices, the author of the model must define
the high-frequency region more carefully, and non-passive continuations become increasingly
unacceptable.

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A convolution-based simulator would also make assumptions about the model behavior above
20 GHz, including some that might cause model non-passivity. However, you cannot determine
these assumptions because the simulator lacks an intermediate fitting step that provides
viewable results.

Figure 27-14 shows the passivity function of the fitted model that indicates an area of non-
passivity between 25 GHz and 28 GHz, which is above the original data range.

Figure 27-14. Non-passivity Between 25 GHz and 28 GHz for Previous Model

Fortunately, you can use Mentor Graphics technology to enforce passivity on the fitted model
by slightly modifying the fitted poles residue, which helps avoid any possibility of model
instability. However, this post-fit passivation can reduce fit accuracy somewhat.

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Figure 27-15 shows the differences between the original (red), fitted (magenta) and
fitted/passivated (green) dependencies.

Figure 27-15. Comparison of Model Dependencies-Small Differences Exist

All of this trouble, though manageable, could have been avoided if the author of the original
model had supplied data to a higher frequency, preferably to a frequency at which the model
behavior is settled.

Sometimes, it may be difficult to expand an insufficient frequency range enough to reach the
desired asymptotic behavior when any of the following conditions are true:

• The asymptotic region is too far away in frequency from the range of interest
• The model does not behave properly
• Measurements cannot be accurately taken at high-enough frequencies
If so, the model must at least provide data well above the range of interest, even if the
dependence does not settle, so that during passivity enforcement the interesting portion of the
model will not be significantly affected.

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Insufficient Resolution
Insufficient resolution means that not enough sample points exist to resolve the model behavior
within the supplied data range, especially at resonances. This condition prevents CPF fitting
from constructing an accurate analytical representation of the model behavior. Poor resolution
leaves much ambiguity in a model and there is no way to uniquely define the behavior between
given points.

Sometimes, resolution problems manifest themselves as model non-causality. You can check
this by viewing the trajectory plot for the model, with the Touchstone and Fitted-Poles Viewer,
where non-causality can be seen as irregular behavior and a chaotic-looking trajectory. Such
non-smooth data can be the result of either of the following conditions:

• Not having enough sample points, which can be corrected by using a finer frequency
grid
• Measurement or simulation noise, which cannot easily be corrected
Figure 27-16 shows an example of model data with insufficient resolution. The dependency is
apparently oscillatory in the frequency domain, but you need at least 8-10 points per period to
validly represent it.

Figure 27-16. Insufficient Frequency Resolution

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Figure 27-17 shows the trajectory plot for the same model has a chaotic trajectory curve.

Figure 27-17. Trajectory Plot Showing a Chaotic Trajectory

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Suppose that, in spite of the overwhelming visual evidence in Figure 27-16 on page 1097 and
Figure 27-17 on page 1098 that the model suffers from serious resolution problems, you attempt
to fit it anyway in preparation for simulation. Figure 27-18 shows the results.

Figure 27-18. Results of Fitting Model from Previous Figure

The fitted results may actually seem acceptable because the fitter has found a representation that
passes through the original data points, is causal, and so on. But notice also how many
assumptions have been made about the dependency. For example, the value of each maximum
and minimum have no corresponding data points.

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Checking S-Parameter Model Quality

The CPF fitter has a high-resolution option and you might be tempted to try it on a model with
insufficient original resolution. However, this is exactly the wrong approach. Figure 27-19
shows, on an admittedly artificial case of extreme under-resolution, the high-resolution fit
causes catastrophic accuracy/passivity degradation.

Figure 27-19. Extreme Case of Under-Resolved Original Data

Figure 27-19 also shows that the fitter generates ambiguous results because it has a larger-than-
reasonable degree of freedom (that is, more poles are allowed), in combination with under-
sampled input data. Note that the fitter approximation at the original points (blue/red) in the
model is quite good and is sometimes even better than would occur with ordinary-precision
fitting. However, the fitting is essentially uncontrollable between the original points. Therefore,
if a model suffers from insufficient frequency resolution, do not run high-precision fitting.

Non-Ideal Asymptotic Behavior at DC

As described by “Proper Even and Odd Behavior” on page 1086, the real part of a model
dependence must be an even function having a slope of zero at DC and the imaginary part must
be an odd function with a value of zero at DC. If the original data in a model does not obey these
requirements, then the fitted dependence may deviate from the original as the fitter attempts to
impose the correct behavior.

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Checking S-Parameter Model Quality

Figure 27-20 and Figure 27-21 on page 1102 show examples, with the fitted data (magenta,
cyan) deviating from the original (red, blue) near DC. This effect may seem minor, but actually
even a small deviation may be important because it defines the model behavior at/near DC and
may strongly affect the results in a time-domain simulation. For example, the effect may
produce a wrong switching-voltage range or incorrect results over the time extent of a very long
eye diagram. A good S-parameter model should use some type of variable sweep, logarithmic at
least, to provide finer resolution near DC.

Figure 27-20. Deviation of Fitted Dependence Near DC

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Checking S-Parameter Model Quality

Figure 27-21. Deviation of Fitted Dependence Near DC-More Severe

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Checking S-Parameter Model Quality

In Figure 27-21 on page 1102, it may appear that the fitted data itself does not meet the low-
frequency asymptotic requirements. However Figure 27-22 displays the same data in a
logarithmic frequency scale, which makes the asymptotes easier to see and shows that the data
have the correct behavior.

Figure 27-22. Logarithmic Scale Shows Correct Asymptotic Behavior

Inherent Non-Causality
Figure 27-16 on page 1097 and Figure 27-17 on page 1098 show that insufficient frequency
resolution can generate non-causality. For example, if you take valid and causal data, resample
it with larger/coarser step size, you end up with non-causal data.

It is also possible to have S-parameter data that has sufficient resolution, but is inherently non-
causal. In this case, the trajectory plot exhibits trajectory errors with regions of
counterclockwise rotations, rather than clockwise rotation. Note that the trajectory errors may
not be chaotic or unsmooth, as Figure 27-16 on page 1097 and Figure 27-17 on page 1098
show.

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Checking S-Parameter Model Quality

Figure 27-23 shows an extreme case where the wrong sign was used for all imaginary
components. The result is a trajectory where much of the path is counterclockwise. This is a
useless model and simulations run with it would produce meaningless results.

Figure 27-23. Inherent Non-Causality with Substantial Counterclockwise

Rotation

Artificially Created and Modified Points

Unfortunately, attempts to manually correct bad models can unexpectedly introduce the types of
problems previously described, such as such as insufficient resolution, non-causality, or non-
realness. Further, it is possible for a model to exhibit all three of these problems.

One common cause of trouble is correcting or adding missing points near DC, to force proper
behavior or to balance differential/common-mode components. For example, in an attempt to
restore passivity, model consumers sometimes apply a brute-force method of simply scaling the
values at frequencies where passivity violations occur. As a rule, these attempts do not improve
the model quality, but instead introduce other problems like those detailed in the previous
topics. Unfortunately, it is almost impossible to guess the missing points or properly correct
existing ones. Therefore, it is almost always safer to use a model as is than to try to manually
correct it. If correction seems necessary, the model should be sent back to the supplier for re-
generation.

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Cascading Multiple S-Parameter Models in Series

Cascading Multiple S-Parameter Models in

Series
S-parameter models are increasingly used in SERDES and other high-speed simulations to
characterize portions of the interconnect between drivers and receivers. If multiple elements in a
signal path are described with S parameters, the circuit topology may contain a “chain” or
“cascade” of S-parameter models connected in series. For example, Figure 27-24 represents a
SERDES channel using the following sequence of S-parameter models for the entire path:

1. Driver (transmitter) package

2. Breakout (including differential via pair)
3. Transmission lines
4. Connector
5. Transmission lines
6. Breakout (including differential via pair)
7. Receiver package

Figure 27-24. SERDES Channel Represented by a Cascaded Series of S-

Parameter Models

Figure 27-25 shows the interconnect portion of the circuit in Figure 27-24, as it appears in
HyperLynx LineSim.

Figure 27-25. Interconnect Portion of SERDES Channel in a LineSim Schematic

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Cascading Multiple S-Parameter Models in Series

Since the channel is differential (that is, it contains a + and – side), each block is a 4-port S-
parameter model.

HyperLynx (and other circuit simulators, such as SPICE) can simulate a chain of S-parameter
models, but special care is required in the underlying algorithms to ensure accurate results. The
following sections explain why accurate cascading of S-parameter models is algorithmically
complex, and what features Touchstone and Fitted-Poles Viewer 2.0 (and newer) provides to
address the problem.

Algorithmic Complexity of S-Parameter Cascading

S-parameter models contain data sampled at a discrete set of frequencies. In a chain of S-
parameter models such as shown in Figure 27-25, rarely would each model use the same
frequencies. Thus, producing a single, cascaded model requires that each sub-model be
represented continuously, so that its value at every frequency used in the final cascaded model
is known precisely.

Less obvious is the fact that even if the constituent S-parameter models were sampled at the
same frequencies, a cascaded model using those frequencies could easily be undersampled (and
thus, simulate inaccurately). For example, Figure 27-26 shows the real and imaginary parts of
an S-parameter model representing 4 inches of a differential pair in red and blue; the sampling
is quite satisfactory. But if four copies of the model are cascaded (with no change in sampling
resolution) to represent a 16-inch pair, the orange and green plots result — clearly
undersampled.

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Cascading Multiple S-Parameter Models in Series

Figure 27-26. Real and Imaginary Parts for Non-Cascaded and Undersampled
Cascaded S-Parameter Models

Generating new frequency points in an S-parameter model requires interpolation, which sounds
relatively easy, but in fact is not. Commercial simulators use a variety of interpolation
algorithms, many of which are imperfect. Worse, the user typically has no visibility into these
algorithms, and their effects can sometimes be wrong in subtle ways. For example, one widely
used SPICE simulator, if instructed to perform an AC-sweep of an S-parameter model to
produce a version with finer frequency resolution, produces the magnitudes in Figure 27-27,
where the original points from simulation are in red and the denser-sampled output in blue.

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Cascading Multiple S-Parameter Models in Series

Figure 27-27. SPICE-Simulator AC-Sweep Interpolation of an Original S-

Parameter Model - Magnitude Plot

The results look quite good, until in Figure 27-28, the plot is switched to real/imaginary parts,
where the behavior of the new model between 10.80 and 10.85 GHz is clearly wrong.

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Cascading Multiple S-Parameter Models in Series

Figure 27-28. SPICE-Simulator AC-Sweep Interpolation of an Original S-

Parameter Model - Real and Imaginary Plot

Yet another challenge for cascading algorithms is the possibility that the channel may contain
series DC-blocking (or AC coupling) capacitors, or a series resonant circuit (such as an L-C
structure in an IC package model). Series capacitors or resonant structures make the channel
non-transparent at some frequencies. In one commonly used algorithm, the input S-parameter
models are each converted to T parameters; the cascaded T-parameter model is found by simple
matrix multiplication of the T-parameter sub-models; and the resulting T-parameter model is
converted to the final cascaded S-parameter model with a standard transformation.

Unfortunately, the transformation from S to T and from T back to S parameters involves

inversion of sub-matrices, such as S21. With non-transparent channels, S21 is singular (or
close) at certain frequencies, causing numerical instability in the transformations, which often
leads to poor results.

High-Accuracy Cascading
The Touchstone and Fitted-Poles Viewer 2.0 and newer implements a sophisticated algorithm
for cascading 4-port S-parameter models. It automatically selects the proper sampling
resolution for the cascaded output model, and uses a proprietary interpolation method that

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Cascading Multiple S-Parameter Models in Series

avoids any non-physical numerical artifacts (such as in Figure 27-28 on page 1109). The model
quality is equally good for symmetric or asymmetric, passive or non-passive, and transparent or
non-transparent cases.

To achieve the highest possible simulation accuracy, HyperLynx users are encouraged to
replace chains of 4-port S-parameter models with a single, cascaded model produced in the
Touchstone and Fitted-Poles Viewer, as shown in Figure 27-29.

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Cascading Multiple S-Parameter Models in Series

Figure 27-29. S-Parameter Cascading Work Flow

Procedure
1. Select Models > Edit Touchstone Models or . The Touchstone and Fitted-Poles
Viewer opens.

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Cascading Multiple S-Parameter Models in Series

This step applies to opening the Touchstone and Fitted-Poles Viewer from HyperLynx.
This documentation does not provide instructions to open the Touchstone and Fitted-
Poles Viewer from other Mentor Graphics products.
2. Select Convert > Cascade. The Cascade 4-Port S-Parameter Models Dialog Box opens.
3. Below the Files to Cascade spreadsheet, click Browse to select the cascaded 4-port S-
parameter models, in left-to-right, driver-to-receiver “signal-flow” order in the
schematic.
Referring to Figure 27-29 on page 1111, when you finish this step, the spreadsheet looks
something like Figure 27-30.

Figure 27-30. Files to Cascade Spreadsheet - Example Contents

4. Verify in the Port Map column that the port ordering for each model is correctly
specified. The default value of “13-24” means that the model has ports 1 and 3 on the

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Cascading Multiple S-Parameter Models in Series

left side, and 2 and 4 on the right (fairly standard for differential-channel models). If
needed, click a Port Map cell and select a different ordering.
5. In the Result File box, type or browse to specify the name/location of the output
cascaded model, and select the port ordering from the Port Map list.
6. Click OK. The Touchstone and Fitted-Poles Viewer produces the new cascaded model
and automatically opens it.
The minimum and maximum frequencies in the cascaded model are determined automatically
from the input models: the minimum frequency is the highest of the starting frequencies in the
input models, and maximum frequency is the lowest of the input ending frequencies. The
number of points in the cascaded model is chosen automatically by default, but you can disable
the Auto check box and specify a number you prefer.

You can include receiver-end termination in the cascaded model by selecting a 2-port S-
parameter model in the Rx Terminator box.

When the cascading operation completes, the Touchstone and Fitted-Poles Viewer shows the
output model. You can use other features in the Touchstone and Fitted-Poles Viewer to inspect
the model to prove to yourself that it is a high quality model. See “Checking S-Parameter Model
Quality” on page 1082. This is an important advantage over other circuit simulators which
perform such operations only internally, giving you no insight into the success of the algorithm
for any particular case.

Applying Cascading to Simulation of Certain IBIS-AMI

Models
The cascading feature is also useful when simulating with certain IBIS-AMI models (of
advanced SERDES driver/Tx and receiver/Rx buffers). Although the AMI standard requires the
analog portions of such models to be provided as IBIS models, some AMI models instead use S-
parameter characterizations.

Note
This is a questionable approach, since S-parameter models are linear, and the buffer
silicon may not be. Nevertheless, some AMI models are made this way.

Procedure
1. Gather the 4-port S-parameter models needed to represent the interconnect portion of the
channel. If necessary, create S-parameter models for certain sections by drawing their
circuits in a LineSim schematic and selecting Export > S-Parameter Model.
2. Locate the S-parameter models that represent the Tx and Rx analog stages of the AMI
model. The silicon vendor whose AMI you are simulating can help; you can also look in
the ASCII .AMI file accompanying the model, for entries such as:

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Cascading Multiple S-Parameter Models in Series

(Model_Specific
(Tstonefile (Usage Info) (Type String)
(List "Xs.s4p" "S.s4p" "T.s4p" "F.s4p" "XF.s4p"))
3. Use the Convert > Cascade feature in the Touchstone and Fitted-Poles Viewer to chain
the S-parameter models (including the AMI portions) in the proper order, starting with
the Tx analog-stage S-parameter model, adding interconnect models, and then ending
with the Rx model. Then convert the cascade to a single cascaded 4-port model.
4. Convert the cascaded model into a transfer function by selecting Convert > To
Transfer Function and doing the following in the Convert to Transfer Function Dialog
Box:
a. Set the Port Map to match the order in the cascaded channel model.
b. When working with AMI models as in this example, select Default Resistance and
Conductance.
c. Set the output file name/location, and click OK.
The result is a 1-port S-parameter file.
5. Convert the output file from step 4 to fitted-poles form, by selecting Convert > To
Fitted Poles. If the model is complex (has a wide frequency range and contains many
details, such as resonances, within its range), then it may be necessary to increase
Maximum complexity order from its default to a value of 1000. The result is a 1-port
.PLS file.
6. Finally, in LineSim, run the AMI wizard (select Simulate SI > Run IBIS-AMI
Channel Analysis) to perform the simulation. Because the channel (including attached
Tx and Rx analog stages) was characterized in the preceding steps, on the FastEye
Channel Analyzer - Set Up Channel Characterizations Page, click Load. This reads the
file created in step 5.
7. Proceed as normal in the rest of the wizard.
Step 4 above merits a little more comment. When Default Resistance and Conductance is
enabled, all termination values are set to zero, meaning that at the input end there is no series
termination, and at the output end there is no line-to-ground or line-to-line termination. These
are the proper values when the cascaded channel has AMI S-parameter models attached at the
input and output ends. However, if the Convert > To Transfer Function operation is applied to a
“pure” interconnect channel (with no attached AMI models), then it is sensible to apply 50-ohm
termination at both ends. To do so, disable the check box, and set Z1 = Z2 = 50 ohms, Y1 = Y2
= 0.02 1/ohms [Siemens], and Y12 = 0.0 1/ohms.

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Converting and Fixing Touchstone and Fitted-Poles Models

Converting and Fixing Touchstone and Fitted-

Poles Models
Requirement: The Complex Pole Fitter license is required to run conversion tools from the
Convert menu.

Use the options in the Convert menu to repair or convert Touchstone and fitted-poles models.
Table 27-2 lists the supported conversions and when to use them.

Table 27-2. Convert Menu Contents

Option Description
Correct Errors • Enforce Passivity—Make a Touchstone model passive.
• Enforce Symmetry—Make a Touchstone model symmetric.

See “Checking and Fixing Passivity and Causality” on page 1071.

Re-Normalize Opens the Re-Normalize Dialog Box.

Select to re-normalize the characteristic impedance of a Touchstone

model.
Parameter Type Opens the Convert Parameter Type Dialog Box.

Select to convert a Touchstone model of one parameter type (S, Y,

or Z) to another (S, Y, or Z).
Mode • General—Opens the Convert Mode Dialog Box with the
Convert to option fully available.
• Standard to Mixed—Opens the Convert Mode Dialog Box
with the Convert to option set to Mixed Mode and read only.
• Standard to Differential—Opens the Convert Mode Dialog
Box with the Convert to option set to Differential Mode and
read only.
Restriction: This option is only available for Touchstone models
with four or more ports.
Combine Modes Opens the Combine to Standard Mode Dialog Box.

Select to combine common and differential mode models.

This option is only available for a differential mode Touchstone or
fitted-poles model.
Cascade Opens the “Cascade 4-Port S-Parameter Models Dialog Box” on
page 1118.

Select to cascade (with high accuracy) multiple 4-port S-parameter

models into a single S-parameter model.

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Simulating S-Parameter Models in the Time Domain

Table 27-2. Convert Menu Contents (cont.)

Option Description
Reduce Ports Opens the Reduce Number of Ports Dialog Box.

Select to remove unused ports from a Touchstone model. This

option reduces the file size.
To Fitted Poles Opens the Convert to Fitted Poles Dialog Box.

Select to convert a Touchstone model to a fitted-poles model.

To Touchstone Opens the Convert to Touchstone Dialog Box.

Select to convert fitted-poles models to Touchstone models.

To Transfer Function Opens the Convert to Transfer Function Dialog Box.

Select to convert a 4-port Touchstone model to a transfer function,

in the form of a 1-port Touchstone model.

Restriction: This option is available only for 4-port Touchstone

models.
Export Equivalent Circuit Opens the Save As dialog box. There are no exporting options.

Select to convert an S-parameter fitted-poles model to an equivalent

SPICE circuit (INC). You cannot use this to convert a Touchstone
model to an equivalent SPICE circuit.

Validate the exported model by running an ADMS simulation with

the original PLS model and then the equivalent circuit model and
comparing the results. You cannot load the equivalent circuit file
into the Touchstone and Fitted-Poles Viewer.

Related Topics
“Mixed Mode S-Parameters” on page 1068
“Checking and Fixing Passivity and Causality” on page 1071
“Viewing and Converting Touchstone and Fitted-Poles Models” on page 1065

Simulating S-Parameter Models in the Time

Domain
S-parameter models are frequency-domain characterizations because they describe the
behaviors of a set of ports at a number of different frequencies. Because of these frequency

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Touchstone Viewer Dialog Boxes

dependencies, the simulator uses special techniques to solve S-parameter models in a time-
domain simulation.

Most simulators solve S-parameter behavior in time using a relatively straightforward method
involving inverse Fourier transformation and direct convolution. It is beyond the scope of this
topic to describe convolution, but a description can be found in nearly any undergraduate text
on communications theory.

By contrast, Mentor Graphics simulators use complex pole fitting (CPF) to simulate S
parameters in the time domain. Prior to simulation, the CPF method fits an S-parameter model
to a set of complex poles, which accurately represents the frequency dependencies of the model.
These poles can then be simulated directly in time. Fitting is required only once and the
resulting poles can be re-used.

Compared to convolution, CPF has these important advantages:

• Performance—CPF is typically 5-7 times faster than convolution.

• Accuracy—To increase speed, convolution-based simulators are often forced to
truncate the time-domain response they use to characterize an S-parameter model. This
can cause accuracy problems, especially at lower frequencies. CPF avoids truncation.
• Model compression—S-parameter models are often very large, for example, over 500
MB, which decreases overall simulation speed and makes them difficult to transfer from
person to person. By contrast, after CPF fitting, a model is greatly compressed 10-100
times. The fitted model is completely self-contained, allows all types of analyses (DC,
AC, and transient), and serves as a complete replacement for the original sampled data.
• Causality—A common problem with S-parameter models is the lack of causality,
which is described in more detail in “Inherent Non-Causality” on page 1103. CPF
automatically fixes causality problems during the fitting process.
• Passivity—The same truncation used in convolution to increase speed may also
introduce non-passivity into a model. CPF avoids truncation.
The explicit fitting step performed by CPF makes the input model quality problems explicit and
visible. Convolution-based simulators make similar transformations, but only internally. Thus
you have no visibility into what changes were needed and no control over how they occur. This
is an advantage of CPF because, after fitting, you can inspect data on which the simulator
actually runs and compare it to the original data.

Touchstone Viewer Dialog Boxes

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Cascade 4-Port S-Parameter Models Dialog Box

Cascade 4-Port S-Parameter Models Dialog Box

To access: Select Convert > Cascade
The Touchstone and Fitted-Poles Viewer can cascade (with high accuracy) multiple 4-port S-
parameter models into a single S-parameter model. The cascading feature is useful if you model
a SERDES channel as a serial chain of S-parameter models representing portions of the
interconnect between drivers and receivers. See “High-Accuracy Cascading” on page 1109.

Figure 27-31. Cascade 4-Port S-Parameter Models Dialog Box

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Cascade 4-Port S-Parameter Models Dialog Box

Figure 27-32. Order of Models in Spreadsheet

Table 27-3. Cascade 4-Port S-Parameter Models Dialog Box Contents

Option Description
Files to Cascade (from left to right) Area
File 4-port S-parameter model that represents an element, such as a connector
or interconnect, in the SERDES channel.

Assign models to spreadsheet rows in the transmitter-to-receiver order of

the SERDES channel, where the top row contains the model for the
element closest to the transmitter and the bottom row contains the model
for the element closest to the receiver. See Figure 27-32.

S-parameter models should be in “standard” format. While Mixed Mode

S-Parameters can be used, then every model you cascade must be mixed
mode and have the same normalizing impedance and port map.
Port Map Order of the ports. The default value of 13-24 indicates that the model
has ports 1 and 3 on the left side, and 2 and 4 on the right. See “S-
Parameter Port Numbering” on page 1066.
Browse Select a 4-port S-parameter model and add it to the bottom of the
spreadsheet.
Remove Select a row header and click Remove.
Moves the selected row up. Select a row header and click <<.

Moves the selected row down. Select a row header and click >>.

Rx Terminator (optional) Area

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Cascade 4-Port S-Parameter Models Dialog Box

Table 27-3. Cascade 4-Port S-Parameter Models Dialog Box Contents (cont.)
Option Description
Optional 2-port S-parameter model that represents termination at the
receiver. The model should be in the “standard” format with port 1
connecting to the positive and port 2 connecting to the negative side of
the receiver termination.
Browse Select a 2-port S-parameter model.
Remove --
Result File Area
Location and file name of the cascaded S-parameter model.

Port Map Order of the ports. The default value of 13-24 indicates that the model
has ports 1 and 3 on the left side, and 2 and 4 on the right. See “S-
Parameter Port Numbering” on page 1066.
Browse --
Sampling Area
Freq Min Highest starting frequency in the set of models in the spreadsheet.
Freq Max Lowest ending frequency in the set of models in the spreadsheet.
Number of Points Calculated automatically unless you disable Auto.
Auto Disable to manually specify Number of Points. The default quantity
should be sufficient for most cases.

Related Topics
“Cascading Multiple S-Parameter Models in Series” on page 1105
“Checking S-Parameter Model Quality” on page 1082
“Viewing and Converting Touchstone and Fitted-Poles Models” on page 1065

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Combine to Standard Mode Dialog Box

Combine to Standard Mode Dialog Box

To access: Select Convert > Combine Modes
Use this dialog box to combine a differential and common mode model into a standard mode
model.

Figure 27-33. Combine to Standard Mode Dialog Box

Related Topics
“Converting and Fixing Touchstone and Fitted-Poles Models” on page 1115

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Convert Mode Dialog Box

Convert Mode Dialog Box

To access:
• Select Convert > Mode
• Select Convert standard mode to mixed mode
• Select Convert standard mode to differential mode
Use this dialog box to convert between differential and non-differential mode for Touchstone
models that have at least four ports.
Restrictions:

• This menu option is unavailable when a fitted-poles model is loaded.

• This menu option is unavailable when a Touchstone model with fewer than 4 ports is
loaded.

Figure 27-34. Convert Mode Dialog Box

Table 27-4. Convert Mode Dialog Box Contents

Option Description
Convert to Standard mode—Convert a mixed mode model to a standard-
mode model.

Mixed Mode—Convert a standard mode model to a mixed mode

model.

Differential Mode—Convert a standard mode model to a

differential mode model.

This option is read only when you open this dialog box with the
or toolbar buttons.

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Convert Mode Dialog Box

Table 27-4. Convert Mode Dialog Box Contents (cont.)

Option Description
Differential Pair Identify the positive and negative input and output ports of the
differential pair.
Save as Type a file name and path for the new model.

Related Topics
“Mixed Mode S-Parameters” on page 1068
“Converting and Fixing Touchstone and Fitted-Poles Models” on page 1115

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Convert Parameter Type Dialog Box

Convert Parameter Type Dialog Box

To access: Select Convert > Parameter Type
Use this dialog box to change the parameter type of your Touchstone model.

Figure 27-35. Convert Parameter Type Dialog Box

Restriction: This menu option is unavailable when a fitted-poles model is loaded.

Table 27-5. Convert Parameter Type Dialog Box Contents
Option Description
Convert to Select a different parameter type (S, Y, or Z) to convert your
model to.
Save as Enter a file name and path for the new model.

Related Topics
“Converting and Fixing Touchstone and Fitted-Poles Models” on page 1115

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Convert to Fitted Poles Dialog Box

Convert to Fitted Poles Dialog Box

To access: Select Convert > To Fitted Poles
Use this dialog box to convert a Touchstone model into a fitted-poles model. You can specify
the maximum fitting order, how to perform the fix, the fitting precision, and more.

Figure 27-36. Convert to Fitted Poles Dialog Box

Table 27-6. Convert to Fitted Poles Dialog Box Contents

Option Description
Used points limit Sets a limit to the number of points in the original data that
are used to perform the fit.

Ideally, you would use all the points given in Touchstone

file to produce an analytical approximation. However, if
too many points are given, the fitting procedure becomes
increasingly slow. On average, 5000 points can be fitted in
a reasonable time, however this time also depends on the
number of ports and the number of poles (order of
complexity).

You may want to limit the number of points first to see if

the fit produces what you expect and then, if it works,
transform the data with a larger number of points for the
final results.

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Convert to Fitted Poles Dialog Box

Table 27-6. Convert to Fitted Poles Dialog Box Contents (cont.)

Option Description
Fitting precision High—Increase fitting accuracy by allowing more poles
than in normal mode. Selecting High slows the conversion
and generates a larger model.

Normal—Enable when performance is more important

than high accuracy. This produces a smaller fitted-poles
file.
Allows extrapolation to Yes—Restores a missing point at zero frequency (DC) by
Zero frequency extrapolating the curve from the low-frequency points
given in the Touchstone file. If the DC point exists in the
Touchstone file, selecting Yes has no effect.

No—The DC point exists in the Touchstone file.

Maximum complexity order If the default value is insufficient, set the order (val/2) to
the maximum order of complexity for fitting in CPF. For
very complicated (sharp, irregular) dependencies it is
sometimes reasonable to reduce the order of complexity,
especially if you have reasons not to trust the data at higher
frequencies.
Maximum Q-factor for The default value is usually sufficient. Increasing the Q-
poles factor can increase the accuracy of the fit.
Perform delay extraction Yes—Perform delay extraction. This reduces the
complexity of the fitted model.

No—Create a fitted model that does not impose limitations

on the transient solution step.
Save As Type a file name and path for the new model.

Related Topics
“Converting and Fixing Touchstone and Fitted-Poles Models” on page 1115

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Convert to Touchstone Dialog Box

Convert to Touchstone Dialog Box

To access: Select Convert > To Touchstone
Use this dialog box to convert a fitted-poles model to a Touchstone model.

Figure 27-37. Convert to Touchstone Dialog Box

Table 27-7. Convert to Touchstone Dialog Box Contents

Option Description
Sampling Algorithm The adaptive algorithm automatically varies the
resolution of the output based on the input model.

You cannot choose a different algorithm.

Resolution Factor Defines the maximum value of the norm of the matrix
increment over two neighboring points ||S(i+1)-S(i)||.
Frequency Range Type the frequency range.
Save As Type a file name and path for the new model.

Related Topics
“Converting and Fixing Touchstone and Fitted-Poles Models” on page 1115

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Convert to Transfer Function Dialog Box

Convert to Transfer Function Dialog Box

To access: Select Convert > To Transfer Function
Restriction: This option is available only if a 4-port Touchstone model is loaded.

Use this dialog box to convert a 4-port Touchstone model to a transfer function, in the form of a
1-port Touchstone model.

Figure 27-38. Convert to Transfer Function Dialog Box

Table 27-8. Convert to Transfer Function Dialog Box Contents

Option Description
Port Map Order of the ports. The default value of 13-24 indicates that the model has
ports 1 and 3 on the left side, and 2 and 4 on the right. See “S-Parameter
Port Numbering” on page 1066.

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Convert to Transfer Function Dialog Box

Table 27-8. Convert to Transfer Function Dialog Box Contents (cont.)

Option Description
Default Resistance Select to set all termination values to zero, where the input ports have no
and Conductance series termination and the output ports have no line-to-ground or line-to-
line termination.

The default settings are appropriate when you analyze a cascaded

SERDES channel with AMI S-parameter models attached at the input and
output ends. See “Applying Cascading to Simulation of Certain IBIS-
AMI Models” on page 1113.

Disable this option when analyzing a “pure” interconnect channel (with

no attached AMI S-parameter models). To apply a 50-ohm termination at
both ends of the channel, set the following values:
• Z1 = Z2 = 50 ohms
• Y1 = Y2 = 0.02 1/ohms (Siemens)
• Y12 = 0.0 1/ohms (Siemens)
Input Resistance Area
Z1 --
Z2 --
Output Conductance Area
Y1 --
Y2 --
Y12 --
Save As Location and file name of the 1-port S-parameter model.
Browse --

Related Topics
“Applying Cascading to Simulation of Certain IBIS-AMI Models” on page 1113
“Cascading Multiple S-Parameter Models in Series” on page 1105
“Converting and Fixing Touchstone and Fitted-Poles Models” on page 1115

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Reduce Number of Ports Dialog Box

Reduce Number of Ports Dialog Box

To access: Select Convert > Reduce Ports
Restriction: This menu option is unavailable when a fitted-poles model is loaded.

Use this dialog box to remove ports from a Touchstone model that are not being used in
simulation, to decrease the size of the model.
To remove a port, set the State value to Grounded, Terminated, or Non-connected. If you do not
want to remove a port, set the State value to Retained.

If you remove ports, the relative order of the remaining ports is preserved. For example, if the
original model has 10 ports and you remove ports 1, 3, 4, 7, and 8 (by terminating, grounding or
disconnecting them), the result is a 5 port model whose port sequence corresponds to the
following original numbers: [2, 5, 6, 9, 10].

Figure 27-39. Reduce Number of Ports Dialog Box

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Reduce Number of Ports Dialog Box

Figure 27-40. Mapping Ports Between Original Model and Reduced-Port Model

Related Topics
“Converting and Fixing Touchstone and Fitted-Poles Models” on page 1115

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Re-Normalize Dialog Box

Re-Normalize Dialog Box

To access: Select Convert > Re-Normalize
Use this dialog box to renormalize the characteristic impedance of a Touchstone model.

Figure 27-41. Re-Normalize Dialog Box

Related Topics
“Converting and Fixing Touchstone and Fitted-Poles Models” on page 1115

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 Viewing and Converting Touchstone and Fitted-Poles Models
TDR Impedance Plot Dialog Box

TDR Impedance Plot Dialog Box

To access: Load Touchstone model > select View > TDR Impedance Plot
Use this dialog box to reproduce the behavior of a TDR (time-domain reflectometer), by
displaying impedance over time for the selected Touchstone model port(s). Single-ended plots
can identify impedance changes seen by a signal propagating through the physical structure
represented by the Touchstone model. Mixed mode plots can identify differential or common-
mode impedance in the time domain.
The time domain response is built in two stages:
1. Find the scalar impedance as a function of frequency.
2. Convert the scalar impedance into a time-domain response.
Event times in the plot have a factor of two built in. For information, see “Event Times in TDR
Impedance Plots” on page 1137.
Note
To view a fitted-poles file (.PLS) in this dialog box, re-sample and convert it into a
Touchstone file by using the Convert to Touchstone Dialog Box.

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TDR Impedance Plot Dialog Box

Figure 27-42. TDR Impedance Plot Dialog Box

Table 27-9. TDR Impedance Plot Dialog Box Contents

Option Description
File Menu
Close Close the dialog box.
View Menu
Fit to window Select to display the entire curve in the chart.

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TDR Impedance Plot Dialog Box

Table 27-9. TDR Impedance Plot Dialog Box Contents (cont.)

Option Description
Zoom Select to enable zoom. Drag the zoom rectangle in the chart to
enclose the area you want to enlarge.

Pan Select to move the curves and X/Y axes across the chart without
changing the magnification. Click anywhere in the chart and drag
the curves to a new position.
Logarithmic Scale— Restriction: This option is never available.
Horizontal Axis

Logarithmic Scale— Select to display the Y axis on a logarithmic scale. For some types
Vertical Axis of curves, data are easier to understand when displayed on a
logarithmic scale.

Lines Select to plot curves as lines.

Vertices Select to plot curves as data points.

Plot Type Select the plot type.

Single Ended—Apply the stimulus to a single port.

Mixed Mode—Apply the stimulus to a pair of ports.

See “Electrical Circuits Used for TDR Impedance Plots” on

page 1136.
Port(s) Select the port(s) to observe.

For mixed mode plots, select ports that drive the same end of a
coupled pair of transmission lines. For a four-port model with
standard port numbering, this means ports 1-3 or 2-4. See “S-
Parameter Port Numbering” on page 1066.

The stimulus and probe are assigned to the same port, resulting in
a round-trip response.

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TDR Impedance Plot Dialog Box

Table 27-9. TDR Impedance Plot Dialog Box Contents (cont.)

Option Description
Mode For Mixed Mode Plot Types, select the stimulus mode.

Common—Apply the same polarity stimulus to both ports.

Differential—Apply the opposite polarity stimulus to the ports.

See “Electrical Circuits Used for TDR Impedance Plots” on

page 1136.
Other ports For the inactive ports, select one of the following types of circuit
connections:
• Terminated—Connect each inactive port to ground through a
termination impedance that is equal to the normalization
impedance selected for that port (the values could be different
among ports).
• Grounded—Short inactive ports to ground.
• Non-connected—Do not connect inactive ports to anything.

See “Electrical Circuits Used for TDR Impedance Plots” on

page 1136.
Stop Time Enter the overall length of time to display in the chart.

To avoid an overly-complex waveform with a series of stair steps

that can be difficult to evaluate, you can set the Stop Time to twice
the propagation time through the connector, channel, or other
topology represented by the Touchstone model.

You can use either the Time-Domain Response Dialog Box or the
procedure in Figure 27-46 on page 1138 to measure the delay
between connected ports in a Touchstone file.
Apply Select to re-display the chart with any plot type or parameter
changes that you make.

Electrical Circuits Used for TDR Impedance Plots

This section describes the stimulus/probe location and port termination used by the Touchstone
Viewer for TDR impedance plots. Knowing this information can help you interpret the results,
especially for the Y axis units and amplitude.
Even though this dialog box obtains the time-domain response indirectly, you can think of the
stimulus as a unit step, which is 0 for all t < 0 and 1 for t >= 0. The unit step stimulus produces
a waveform that resembles a set of stairs.

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TDR Impedance Plot Dialog Box

Note
Notes for Figure 27-43, Figure 27-44, and Figure 27-45:

For termination information for inactive ports, see “Other ports” on page 1136.

Reference to ground is not drawn for model ports, to reduce clutter.

Figure 27-43. Electrical Circuit Used for TDR Impedance Plots - Single-Ended

Figure 27-44. Electrical Circuit Used for TDR Impedance Plots - Mixed Mode
Plot Type and Differential Mode

Figure 27-45. Electrical Circuit Used for TDR Impedance Plots - Mixed Mode
Plot Type and Common Mode

Event Times in TDR Impedance Plots

Event times in the plot have a factor of two built in because the signal source and receiving
probe are both located at the same port, creating a round trip. This behavior is similar to
physical TDR equipment, where the incident voltage wave propagates to the location of the
impedance discontinuity and back to the probe.
Figure 27-46 shows how to use the Touchstone Viewer to measure the delay through the
connector or other topology represented by the Touchstone file. Use the delay to identify the
stair step interval in Figure 27-47. The 4-port Touchstone file in the figure uses standard port
numbering, as described in “S-Parameter Port Numbering” on page 1066. Also, the geometry
represented by Touchstone file includes a differential pair with two nearby stitching vias.

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TDR Impedance Plot Dialog Box

Figure 27-46. Measure Delay Between Touchstone File Ports

Figure 27-47 shows a single-ended plot to illustrate how the reported time for impedance
changes is twice the insertion delay.

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TDR Impedance Plot Dialog Box

Figure 27-47. Measure Stair Step Intervals - Single-Ended

Figure 27-48 shows a mixed mode plot to illustrate how the reported time for impedance
changes are two times the insertion delay from port to port.

Note
For mixed mode plots, there is no general rule about the stair step interval being twice the
delay between connected ports. For example, consider a Touchstone model extracted
from a coupled two conductor transmission line. With weak coupling, all delays could be
close to each other (for single ended, mixed mode differential, and mixed mode common
cases). With strong coupling, the delays may become different, because even and odd
mode propagation velocities on coupled microstrip traces are not equal.

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TDR Impedance Plot Dialog Box

Figure 27-48. Measure Stair Step Intervals - Differential

Figure 27-46, Figure 27-47, and Figure 27-48 show deliberately simple plots. The Touchstone
model was exported from LineSim, using the schematic in Figure 27-49.

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TDR Impedance Plot Dialog Box

Figure 27-49. TDR Impedance Plots - Schematic for Extracted Touchstone

Model

Related Topics
“Viewing and Converting Touchstone and Fitted-Poles Models” on page 1065

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Viewing and Converting Touchstone and Fitted-Poles Models
Time-Domain Response Dialog Box

Time-Domain Response Dialog Box

To access: Load Touchstone or fitted-poles model > select one or more ports > select View >
Time-Domain Responses
Use this dialog box to stimulate the selected port(s) and plot the responses in the time domain.
The resulting waveforms can provide a more intuitive view of Touchstone data, such as the time
delay and signal quality between ports for each end of a net.

Figure 27-50. Time-Domain Response Dialog Box

Note
You can select different ports from the Touchstone Viewer while this dialog box is open.
If needed, move this dialog box out of the way and, from the Touchstone Viewer, select
different or additional ports in Figure 27-51.

Figure 27-51. Parameter Spreadsheet in Touchstone Viewer

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Time-Domain Response Dialog Box

Table 27-10. Time-Domain Response Dialog Box Contents

Option Description
File Menu
Save As Select to save the currently-displayed curves as .LIS files. The
files are saved to the same folder containing the Touchstone
Model, unless you select a different location.
Close Close the dialog box.
View Menu
Fit to window Select to display the entire curve in the chart.

Zoom Select to enable zoom. Drag the zoom rectangle in the chart to
enclose the area you want to enlarge.

Pan Select to move the curves and X/Y axes across the chart without
changing the magnification. Click anywhere in the chart and drag
the curves to a new position.
Logarithmic Scale— Restriction: This option is never available.
Horizontal Axis

Logarithmic Scale— Select to display the Y axis on a logarithmic scale. For some types
Vertical Axis of curves, data are easier to understand when displayed on a
logarithmic scale.

Restriction: This option is available only when the Impulse value

is Unit Step.
Lines Select to plot curves as lines.

Vertices Select to plot curves as data points.

Impulse Select the type of stimulus to apply to the ports you selected in the
Parameters area of the Touchstone Viewer.

See “Stimulus Options for Time-Domain Responses” on

page 1147.

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Time-Domain Response Dialog Box

Table 27-10. Time-Domain Response Dialog Box Contents (cont.)

Option Description
Pulse Time The falling transition start time. This is an absolute time, starting
from t0 (time zero).

Restriction: This option is available only when the Impulse value

is Rectangular or Trapezoidal.
Rise Time The rising transition increases linearly from 0 to 1 between t0 and
this value. You can obtain this value from the slope of the rising
edge of the IC buffer.

Restriction: This option is available only when the Impulse value

is Trapezoidal.
Fall Time The falling transition decreases linearly from 0 to -1 between
Pulse Time plus this value. You can obtain this value from the
slope of the falling edge of the IC buffer.

Restriction: This option is available only when the Impulse value

is Trapezoidal.
Stop Time The overall length of time to display in the chart.
Apply Select to update the chart when you change the impulse type or a
time parameter.

Electrical Circuits Used for Time-Domain Responses

This section describes the stimulus type and location, probe location, and port termination used
by the Touchstone Viewer for time-domain responses. Knowing this information can help you
interpret the results, especially for the Y axis units and amplitude.
Note
Reference to ground is not drawn for model ports in the figures below, to reduce clutter.

Electrical Circuit Used for Time-Domain Responses - S-Parameters

See Figure 27-52. S(a,b) shows the ratio of the reflected wave at port a to the magnitude of the
incident wave, when the incident wave is applied to port b, and the incident waves at all other
ports (if any) are assumed to be zero. The incident wave is created by a wave source whose
internal impedance equals the normalizing impedance for port b.
Note
In this context, the source is an incident wave and the response is a reflected wave.

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Time-Domain Response Dialog Box

All ports, except for b, are terminated to ground by a normalizing impedance of the value
specified in the Touchstone model. The Touchstone model can either specify the same
normalizing impedance for all ports or specify a unique normalizing impedance for each port.

Figure 27-52. Electrical Circuit Used for Time-Domain Reponses - S(a,b)

The incident and reflected waves are formed by port voltage and current in the following ways:
( Va – ( Za × Ia ) )
Reflected wave Wa = ---------------------------------------
Za
where:
Va is the voltage at port a
Za is the normalizing impedance for port a
Ia is the current at port a
( Vb + ( Zb × Ib ) )
Incident wave Wb = -------------------------------------------
Zb
where:
Vb is the voltage at port b
Zb is the normalizing impedance for port b
Ib is the current at port b, where current enters the port
Wa
The response is a dimensionless ratio: ---------
Wb
When all normalizing impedances are identical in the Touchstone file, Z can be omitted
because the ratio stays the same. But when normalizing impedances are not identical, the
equations must include them.
For information about the available types of incident waves, see “Stimulus Options for Time-
Domain Responses” on page 1147.
Figure 27-53 shows an S(1,2) example for a four-port model.

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Time-Domain Response Dialog Box

Figure 27-53. Electrical Circuit Used for Time-Domain Reponses - S(1,2)

Electrical Circuit Used for Time-Domain Responses - Z-Parameters

See Figure 27-54. Z(a, b) shows the voltage at port a when the stimulus from an ideal current
source is applied to port b. All ports, except for b, are open.

Figure 27-54. Electrical Circuit Used for Time-Domain Reponses - Z(a,b)

where:
The ideal current source at port b has infinite internal impedance.
Current enters port b.
The response at port a has the dimension of impedance.
For Z(a,a), the current is applied and voltage is measured at the same port.
For information about the available types of incident waves, see “Stimulus Options for Time-
Domain Responses” on page 1147.
Figure 27-55 shows a Z(1,2) example for a four-port model.

Figure 27-55. Electrical Circuit Used for Time-Domain Reponses - Z(1,2)

Electrical Circuit Used for Time-Domain Responses - Y-Parameters

See Figure 27-56. Y(a, b) shows the current entering port a when the stimulus from an ideal
voltage source is applied to port b. All ports, except for b, are grounded by ideal conductors.

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Time-Domain Response Dialog Box

Figure 27-56. Electrical Circuit Used for Time-Domain Reponses - Y(a,b)

where:
The ideal voltage source at port b has zero internal impedance.
Voltage enters port b.
The response at port a has the dimension of conductance, assuming unit magnitude of
step or pulse.
For Y(a,a), the voltage is applied and current is measured at the same port.
For information about the available types of incident waves, see “Stimulus Options for Time-
Domain Responses” on page 1147.
Figure 27-57 shows a Y(1,2) example for a four-port model.

Figure 27-57. Electrical Circuit Used for Time-Domain Reponses - Y(1,2)

Stimulus Options for Time-Domain Responses

Note
t0 is time zero.

Dirac impulse—Can be thought of as a derivative of an ideal unit step or as a rectangular pulse

of height 1/H and width H when H approaches 0. To keep the area under the curve equal to one,
the amplitude is practically infinite. The Dirac impulse can also be thought of as infinite at t0
and 0 everywhere else.

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Time-Domain Response Dialog Box

Figure 27-58. Stimulus - Dirac Impulse

Unit step—0 for all t < 0 and 1 for t >= 0.

Figure 27-59. Stimulus - Unit Step

Rectangular—1 between t0 and Pulse Time (the start of the falling transition), and 0 otherwise.

Figure 27-60. Stimulus - Rectangular

Trapezoidal—The sum of two separate ramped rising and falling transitions: x(t)= a(t) +b(t)
where:
x(t) is the summed wave that is applied to the Touchstone model port. Note that the probed
response may be slightly distorted because it is not x(t), but the response on the port connected
to input x(t).
a(t) is the rising transition that goes up linearly from 0 to 1 between t0 and t = Rise Time, and
then stays a constant 1.
b(t) is the falling transition that stays 0 until t = Pulse Time (the start of the falling transition),
goes down linearly from 0 to -1 for Fall Time, and then stays a constant -1.
The stimulus becomes 0 at t > max(Rise Time, Pulse Time+Fall Time).
Figure 27-61 shows a single pulse, where Rise Time < Pulse Time.

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Time-Domain Response Dialog Box

Figure 27-61. Stimulus - Trapezoidal Pulse, Rise Time is Less Than Pulse Time

Figure 27-62 shows a double pulse, where Rise Time > Pulse Time.

Figure 27-62. Stimulus - Trapezoidal Pulse, Rise Time is More Than Pulse Time

Related Topics
“Viewing and Converting Touchstone and Fitted-Poles Models” on page 1065

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Time-Domain Response Dialog Box

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 Chapter 28
Exporting Design and Model Data

You can export nets, boards, power-distribution network (PDN) models, and so on in order to
use them with other simulation software or to analyze their electrical behavior. You can also
export constraint templates and design simulation file archives.

Example applications follow:

• Export a BoardSim net to LineSim to easily perform "what if" analysis to fix problems
such as excessive delay, crosstalk, DC drop, PDN impedance, and so on.
• Export signal nets, signal vias, or entire PDNs to S-parameter models in order to study
insertion and return loss in the frequency domain or to use them to simulate designs with
other software.
• Export a constraint template. This capability enables you to define net topologies in
LineSim that have good signal-integrity and transfer that information to constraint-
aware Mentor Graphics software, such as Constraint Editor System (CES) or Constraint
Template Editor (CTE). Usually the goal of constraints is to constrain routing in
downstream routers.
• In a multiple-board design where a daughter board has not yet been routed, you can
define in LineSim the topology for critical nets on the daughter board, export the
schematic to a .HYP file, create a BoardSim MultiBoard project to plug the daughter
board into the motherboard, and then simulate the system-level behavior.
This topic contains the following:

• “Exporting Nets to S-Parameter Models” on page 1152

• “Exporting Nets to SPICE Netlists” on page 1157
• “Exporting BoardSim Nets to LineSim” on page 1161
• “Exporting BoardSim Topologies to HyperLynx 3D EM Designer” on page 1165
• “Exporting BoardSim Boards to IBIS EBD Models” on page 1169
• “Exporting BoardSim Boards to ICX” on page 1172
• “Exporting LineSim Schematics to BoardSim” on page 1174
• “Exporting Constraint Templates from LineSim” on page 1175
• “Exporting Nets from CES to LineSim” on page 1177
• “Importing Constraints from CES to BoardSim” on page 1177

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Exporting Nets to S-Parameter Models

• “Exporting and Importing Stackups” on page 1177

• “Exporting Signal Vias to S-Parameter Models” on page 1180
• “Exporting PDNs to S-Parameter Models” on page 1183
• “Gathering and Archiving Design Simulation Files” on page 1186

Related Topics
“Importing Constraints from CES to the Batch Simulation Spreadsheet”

“Importing Model Assignments from CES to REF Files”

“Checking and Fixing Passivity and Causality” on page 1071

“Back-Annotating Board Changes“

“Pre-Layout Workflow”

“Post-Layout Workflow”

Exporting Nets to S-Parameter Models

Use the Extract S-Parameter Model dialog box to export passive networks, such as BoardSim
nets and LineSim schematics, to S-parameter models representing equivalent circuits.

Requirement: The SPICE Output and Advance Scope licenses are required to export nets to S-
parameter models.

You can also retain the SPICE netlist and simulation run file that are automatically created
when exporting an S-parameter model. See the “Do not delete S-parameter extraction netlists”
option on the Preferences Dialog Box - Advanced Tab.

This topic contains the following:

• “Reasons to Export S-Parameter Models” on page 1153

• “About Exported S-Parameter Models” on page 1153
• “Preparing the Design for Generating S-Parameter Models” on page 1153
• “Procedure to Export Nets to S-Parameter Models” on page 1154

Related Topics
“Viewing and Converting Touchstone and Fitted-Poles Models” on page 1065

“Exporting Signal Vias to S-Parameter Models” on page 1180

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 Exporting Design and Model Data
Exporting Nets to S-Parameter Models

Reasons to Export S-Parameter Models

Representing circuits in the form of S-parameter models provides the following benefits:

• Share design information with others in a format that protects any IP (intellectual
property) that might exist.
• Reduce simulation runtime because many simulators can simulate an S-parameter model
faster than a equivalent set of discrete transmission lines, resistors, and so on. This is
especially true for geometries that require small simulation time steps, such as curved
traces.
• Create connector models with pin-to-pin coupling.
Example: Create in LineSim a schematic that models a connector with pin-to-pin
coupling and export the schematic as an S-parameter model. You can use this model in
other LineSim schematics by assigning the S-parameter model to a free-form S-
Parameter/SPICE Model symbol.
• Analyze or simulate the circuits with other applications, such as the Touchstone and
Fitted-Poles Viewer, Matlab, and HSPICE.
Example: Examine the composite view of all loss factors, which you can display in the
Touchstone and Fitted-Poles viewer. If you are trying to design an interconnect that
meets a required loss budget, for example PCI Express has a loss budget of about -15dB,
the exported S-parameter model enables you to look at all the components of the
interconnect in one environment and verify that it meets the loss budget at the given
operating frequency.

About Exported S-Parameter Models

HyperLynx creates S-parameter models that are not purely linear or logarithmic. A
sophisticated adaptive sweeping technology increases the sampling rate at resonant frequencies
and other high-activity response events.

HyperLynx exports standard mode S-parameter models. To generate a mixed mode S-parameter
model, you must translate the standard mode model after exporting, see Convert Mode Dialog
Box.

Preparing the Design for Generating S-Parameter Models

Set up the circuit you want to model. While you do not have to assign IC models to the selected
net or schematic, the presence or absence of a driver may determine which electrically-small
features are accounted for in the S-parameter model. The process that converts the net to an
electrical circuit for export takes into account driver switching characteristics when simplifying
the electrical circuit to reduce simulation time. For example, drivers with slow slew rates may

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Exporting Nets to S-Parameter Models

enable the conversion process to combine additional transmission lines to speed up simulation
while affecting simulation results only slightly.

Preparing Boards for Exporting S-Parameter Models

Select a net for simulation. The exported S-parameter model includes nets associated
conductively or by coupling. If crosstalk is enabled, you should also adjust the crosstalk
threshold voltage so that the board viewer displays the aggressor nets you want to include in the
S-parameter model.

It is recommended that when exporting a differential pair from BoardSim, you assign to the
output pins an IBIS model containing the [Diff Pin] keyword. This ensures that all segments of
the differential pair are considered to be coupled during the export. After making this model
assignment, crosstalk does not need to be enabled for differential pair segments to be considered
as coupled if the “Always treat diff pairs as coupled” option is enabled in the Preferences
Dialog Box - Advanced Tab

Preparing Schematics for Exporting S-Parameter Models

Draw the schematic you want to model. The S-parameter model includes the effects of the
schematic elements, such as transmission lines, resistors, and so on.

The hierarchical port symbol provides a convenient way to add a port when you do not plan to
an assign IC model to that portion of the circuit.

Procedure to Export Nets to S-Parameter Models

Restriction: If you enabled HSPICE for interactive simulation on the Preferences Dialog Box -
Circuit Simulators Tab, you must change simulators and enable Eldo/ADMS before exporting
S-parameter models.

Note
HyperLynx exports standard mode S-Parameter models. To generate a mixed mode s-
parameter mode, you must translate the standard mode model after export, see Convert
Mode Dialog Box.

Procedure
1. Do one of the following:
• BoardSim — select a net and select Export > Net To > S-Parameter Model.
• LineSim — select Export > S-Parameter Model. The exported model can have
ports for all IC pins in the schematic.
The Extract S-Parameter Model dialog box opens.

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Exporting Nets to S-Parameter Models

2. Map IC pins to S-parameter model ports by doing any of the following:

• Click in a Port cell and do one of the following:
o Type an integer port number to add the IC pin to the model.
o Click NC to omit the IC pin from the model.
• Click Map Auto to automatically assign port numbers for all IC pins.
3. Type the frequency range of the S-parameter model in to the min and max frequency
fields.
4. Select the type of sampling to perform from the Sweeping Type list and do the
following:
• Linear — Set the sampling step size used to analyze the frequency response of the
circuit by dragging the slider. This setting is somewhat analogous to the time step in
time-domain simulators, where a low tolerance maps to a small sampling step size.
You might increase the tolerance if exporting the S-parameter model takes too long
or if you simulate with the exported S-parameter model and run out of simulation
points.
• Logarithmic — Set the number of points per decade.
• Adaptive — Adaptive sweeping varies the sampling step size depending on model
characteristics. It increases the sampling rate at resonant frequencies and other high-
activity response events.
You can evaluate the effect of this setting by exporting models produced by various
tolerance settings and comparing the models with the Touchstone viewer by
overlaying their curves.
5. In the Reference Impedance area, specify the impedance to which the model parameters
are normalized by clicking one of the following:
• Typical for Channel/Connector
• Typical for Decoupling
• Custom—Type a value in the box.
6. To display the new S-parameter model in the HyperLynx Touchstone and Fitted-Poles
Viewer, select the Automatically display results check box.
See also: “Viewing and Converting Touchstone and Fitted-Poles Models” on page 1065
7. Click Create Model. The Save S-Parameter Model dialog box opens.
8. Type or browse to the model folder and file name and click Save.

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Exporting Nets to S-Parameter Models

Related Topics
“Exporting Design and Model Data” on page 1151

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Exporting Nets to SPICE Netlists

Exporting Nets to SPICE Netlists

Use the SPICE Writer to generate SPICE netlists of a schematic in LineSim or a selected net in
BoardSim.

Requirement: The SPICE Output license is required to run the SPICE Writer.

This topic contains the following:

• “Why the SPICE Writer is Needed to Model Interconnect in SPICE” on page 1157
• “Netlists Generated by the SPICE Writer” on page 1158
• “Compatibility with SPICE Programs” on page 1159
• “Generating the SPICE Netlist” on page 1160

Why the SPICE Writer is Needed to Model Interconnect in

SPICE
Normally, as a HyperLynx user, you’ll perform your signal-integrity, crosstalk, and EMC
simulations in LineSim or BoardSim. However, there may be certain situations in which you
want to move interconnect simulation out of HyperLynx and into SPICE.

For example, HyperLynx does not supply models for analog ICs. If you have a mixed-mode
design, HyperLynx can simulate the digital portions, but not the analog. SPICE, of course,
handles analog simulation well.

However the difficulty with modeling interconnect in SPICE is getting the detailed
transmission-line information into a SPICE netlist. For example, on a typical PCB, the clock net
may involve literally hundreds of individual metal segments, each of which, for an accurate
simulation, must be modeled as an individual transmission line with a certain delay and
characteristic impedance. Translating this information from the PCB layout into SPICE
manually is virtually an impossible task.

Worse yet, consider trying to model several complex, real-world PCB traces that are coupled to
each other, using a SPICE netlist. SPICE itself may be able to perform the simulation if you can
produce the netlist, but the netlist creation is probably impossible at the required level of detail.
(To model coupling, you need to translate not only the "raw" physical layout information, but
also to run a field solver to find the coupling C and L matrices.)

Let HyperLynx Do All of the Interconnect Modeling Automatically

The beauty of the SPICE writer is that it allows HyperLynx to perform for you the task the
makes interconnect modeling in SPICE so difficult: the SPICE writer automatically extracts all
of the detailed physical information from your PCB layout (or LineSim schematic), converts it

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Exporting Nets to SPICE Netlists

to electrical data (including coupling), and writes it into a SPICE netlist. Then you can add
SPICE IC models as needed, and simulate.

Netlists Generated by the SPICE Writer

This section discusses the following:

• “What the SPICE Writer Generates” on page 1158

• “Two Types of Netlist Output - Uncoupled and Coupled” on page 1159
• “Coupled Netlists and the HyperLynx Field Solver” on page 1159

What the SPICE Writer Generates

The SPICE writer generates two files for every net or schematic on which you run it:

• A SPICE sub-circuit, containing the following elements:

o All of the interconnect for the net(s) (modeled as SPICE transmission lines)
Very short transmission lines, such as when exporting electrically-short vias, are not
exported in order to improve simulation performance.
If the net contains a via, very small capacitors used to model the via are discarded
before the SPICE netlist is written. These very small capacitors can take a long time
to simulate in SPICE.
o Any passive components (resistors, capacitors, inductors) attached to the
interconnect
o External nodes for the points on the net(s) at which IC pins are to be connected
(normally, SPICE IC models)
• A top-level SPICE "test bench," the use of which is optional; it contains:
o An instantiation of the sub-circuit
o Simple voltage-ramp + resistor "stand-in" models for the ICs attached to the sub-
circuit; the voltage ramp switches in a time equal to the IC’s slew time, and the
resistance equals the IC’s driving impedance
o Other control statements that allow the sub-circuit to be simulated, including
probing of all of the sub-circuit’s external nodes
• If a coupled netlist (containing HSPICE "W" elements) is generated, a series of .RLC
files containing the electrical cross-section information for each W element in the netlist

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Exporting Nets to SPICE Netlists

Two Types of Netlist Output - Uncoupled and Coupled

The files generated by the HyperLynx SPICE writer come in two "flavors", depending on
whether or not crosstalk is enabled in BoardSim/LineSim when you generate the netlist:

• Uncoupled, in which no coupling is modeled, and all transmission lines are modeled
with the standard SPICE lossless "T" element
• Coupled, in which coupling is included and all coupled transmission lines are modeled
with the HSPICE coupled, lossy "W" element
Specifically, the choice between uncoupled and coupled output is made automatically by the
SPICE Writer, as follows:

• If you are running BoardSim, and you have crosstalk enabled, coupled output is
generated; if crosstalk is disabled, uncoupled output is generated
• If you are running LineSim, and you have coupling anywhere in your schematic,
coupled output is generated; if there is no coupling in your schematic, uncoupled output
is generated

Coupled Netlists and the HyperLynx Field Solver

If you generate a coupled netlist, it includes HSPICE-compatible "W" elements (see above).
These require field solutions which result in capacitance and inductance matrices that
characterize each element’s coupling. The solutions are generated automatically by
HyperLynx’s field solver, and output in a series of files with extension ".RLC."

You can correlate each W element to its .RLC file by looking in the netlist at the "RLGCfile="
field in the W element line.

Resistance matrices are written to the .RLC file, however only "diagonal" DC resistances are
included.

Compatibility with SPICE Programs

The SPICE Writer’s uncoupled output uses only the standard "T" element, and should therefore
be compatible with most programs derived from Berkeley SPICE. The output has been tested
with a Berkeley version of SPICE.

The SPICE Writer’s coupled output uses the HSPICE "W" element, and is only known to be
compatible with HSPICE and ADMS. If you are running a different version of SPICE (not
HSPICE or ADMS), you probably cannot use the coupled flavor of the Writer’s output.

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Exporting Nets to SPICE Netlists

Generating the SPICE Netlist

Use the Export to SPICE Netlist dialog box to export the schematic or selected net to a SPICE
netlist.

This topic contains the following:

• “Preparing the Design for SPICE Netlist Generation” on page 1160

• “Steps to Generate the SPICE Netlist” on page 1160

Related Topics
“Exporting Nets to SPICE Netlists” on page 1157

Preparing the Design for SPICE Netlist Generation

Set up the circuit you want to model. While you do not have to assign IC models to the selected
net or schematic, the presence or absence of a driver may determine which electrically-small
features are accounted for in the SPICE netlist. The process that converts the net to an electrical
circuit for export takes into account driver switching characteristics when simplifying the
electrical circuit to reduce simulation time. For example, drivers with slow slew rates may
enable the conversion process to combine additional transmission lines to speed up simulation
while affecting simulation results only slightly.

In BoardSim, select a net for simulation. If crosstalk is enabled, you should also adjust
BoardSim Crosstalk’s threshold so that the desired number of aggressor nets are included in the
board viewer. The SPICE Writer will netlist the selected net, its associated nets, and (if
crosstalk is enabled) all aggressor nets.

In LineSim, draw the schematic you want netlisted. The SPICE writer will include in its netlist
all of the elements (transmission lines, resistors, capacitors, etc.) in the schematic.

Steps to Generate the SPICE Netlist

To generate the SPICE netlist:

1. Do one of the following:

• BoardSim — Select Export > Net To > SPICE Netlist.
• LineSim — Select Export > SPICE Netlist.
2. To start the SPICE node numbering in the sub-circuit output at a different value, type the
value into the First Node Number In Subcircuit box.
You can choose whether to model package parasitics and whether to force use of T
transmission line elements.

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Exporting BoardSim Nets to LineSim

See also: “Preferences Dialog Box - Circuit Simulators Tab” on page 1808
3. Click Save As. The Save As dialog box opens.
4. Type the sub-circuit name without the .SP file extension (it is added automatically), and
then click Save.
Result: The sub-circuit file and top-level test bench file are written. The sub-circuit file is
named <name>.SP and the top-level test bench file is named <name>_TEST.SP, where <name>
is the sub-circuit name you typed in.

Related Topics
“Exporting Nets to SPICE Netlists” on page 1157

“Exporting Design and Model Data” on page 1151

Exporting BoardSim Nets to LineSim

Use the Export to LineSim Free-Form Schematic dialog box to create a free-form LineSim
schematic for the selected signal net, selected power-supply net(s), or both. When exporting the
selected signal net, its associated nets can be exported too.

Signal nets exported to the schematic can include trace properties, IC model assignments, via
properties, termination components, and power-distribution network (PDN) properties. If you
have a MultiBoard project open and select a net that connects to nets on other boards, the
exported schematic contains those nets and their board-to-board connectors.

Power-supply nets exported to the schematic can include power-distribution network elements,
including IC power-supply pins, capacitor pins, vias, board outlines, copper pours and voids,
and so on. Use the PDN Editor to view and edit exported power-supply nets. See “Defining the
Power-Distribution Network”.

Caution
Verify the accuracy of exported decoupling capacitor mounting. In some complex
intersections of trace segments, vias, and pads, the exported mounting may include
structures from adjacent nets. If needed, fix it with the Decoupling Mounting Scheme
Editor. See “Decoupling Mounting Scheme Editor Dialog Box” on page 1505.

This topic contains the following:

• “Reasons to Use LineSim to Simulate Board Changes” on page 1162

• “Procedure to Export Nets to LineSim” on page 1162
• “Naming Convention Change for Power-Supply Nets Exported to LineSim” on
page 1164

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Exporting BoardSim Nets to LineSim

Restrictions:

• The Export to PDN Editor license is required to export power-supply nets to the PDN
editor.
• BoardSim does not export IC power-supply pins unless you assign a AC, DC, or VRM
model or a reference net to them. If you do not make any of these power-integrity model
assignments to a IC power-supply pin, BoardSim exports the metal areas but not the IC
power-supply pin. See “Edit AC Power Pin Model Dialog Box” on page 1547.
• BoardSim does not export traces for power-supply nets. The PDN Editor does not
supporting routing.
• BoardSim does not create cell-based LineSim schematics.
• BoardSim does not export vias on unrouted nets.
• BoardSim does not export vias that touch IC component pins.
• BoardSim does not export the extra capacitance if the net contains a via in an SMD pad
topology and you enable the Add extra capacitance for SMD pads if via-in-pad option in
the Select Method of Simulating Vias Dialog Box.
• You cannot export power-supply nets to LineSim when a MultiBoard project is loaded.

Reasons to Use LineSim to Simulate Board Changes

LineSim enables you to perform “what if” analysis on the nets you export from BoardSim.

Use LineSim to judge the effects of re-routing or component re-placement. After exporting a net
you can use LineSim to simulate the effects of routing or component placement changes to fix
problems such as excessive delay, crosstalk, or incorrectly coupled differential signals.

Restriction: BoardSim's Manhattan Routing feature can also simulate the effects of component
placement changes on the board, but the following LineSim capabilities are not available in
BoardSim for nets that have been routed or rerouted with Manhattan routing: Crosstalk analysis,
net scheduling (controlling the connectivity sequence and transmission line lengths among pins
on the net), routing on different stackup layers.

You can also use LineSim to judge the effects of PDN changes, such as the
location/quantity/value of decoupling capacitors, location and geometry of copper pours/voids,
location and quantity of stitching vias, and so on.

Procedure to Export Nets to LineSim

To export a net to LineSim:

1. If you want to export a signal net, you can select it now or you can select it in step a.

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Exporting BoardSim Nets to LineSim

If you want to export only power-supply nets, you do not have to select a signal net.
See also: “Selecting Nets for SI Analysis”
2. Select Export > Net To > Free-Form Schematic. The Export to LineSim Free-Form
Schematic dialog box opens.
3. Type or browse to the exported schematic location and file name.
The default name is the name of the selected signal net. If have not selected a net, a
generic default name is used.
4. To select a signal net to export, select the Export to Free-Form Schematic Editor
check box and do the following:
a. Click Select to select the signal net to export. If you selected a net in step 1, its name
is displayed in the Signal box.
b. To export coupled segments on other nets, select the Export coupled segments
check box.
Restriction: This option is unavailable if crosstalk simulation is disabled or the net
is not coupled to another net.
5. To export power-supply nets to the PDN Editor, select the Export to PDN Editor check
box and select the net(s) to export.
6. To set via-exporting options, clear the Export To PDN Editor check box, and select one
of the following:
• Schematic symbols—Model vias with single or differential via components. This
option offers the best simulation correlation and includes physical via properties,
such as padstack geometries.
• Electrical models—Model vias as sets of L, C, and transmission-line components,
using via simulation options in the Select Method of Simulating Vias Dialog Box.
This option can "clutter" the schematic with several transmission lines and
capacitors used to model the via. Exported capacitors used to model the via do not
have parasitic properties, unlike other capacitors in LineSim schematics.
Restriction: If the exported nets model vias as sets of L, C, and transmission-line
components, the schematic does not contain parasitic information for the passive
components representing via electrical properties. If you view the properties for this
type of passive component in the schematic, the dialog box does not contain a
Parasitics tab.
• Do not export—This capability enables you to isolate the effects of vias on the
selected net by creating schematics that do, and do not, model vias, and then
comparing simulation results.
Restriction: If you selected the Export To PDN Editor check box, vias are always
exported as schematic symbols and the Export Vias list is unavailable.

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Exporting BoardSim Nets to LineSim

7. To automatically open LineSim and load the exported net into the free-form schematic
editor, select the Open exported file in LineSim check box. This option is unavailable
if no LineSim license is available.
Requirement: BoardSim and LineSim must be installed on the computer to use this
option.
8. To include the electrical contents of EBD models assigned to pins on the net, select the
Expand into EBD check box. This check box is available only when an EBD model is
assigned to a pin on the net.
9. Click Export.
Restriction: This button is unavailable unless the Export to Free-Form Schematic
Editor or Export to PDN Editor check box(es) are enabled.

Naming Convention Change for Power-Supply Nets

Exported to LineSim
Starting with HyperLynx 8.2, power-supply nets exported from BoardSim to LineSim have the
same name in the free-form schematic as they do in BoardSim. Previous to v8.2, exported
power-supply net names were of form __TPE_<BoardSim_net_name>__.

For example, the power-supply net “gnd” in BoardSim is now exported as “gnd” in the free-
form schematic. In pre-8.2 versions, the net name was “__TPE_gnd__” in the exported free-
form schematic.

This change affects you when the following sequence is true:

1. Use HyperLynx pre-8.2 to export a power-supply net from BoardSim to LineSim.

2. When running decoupling analysis for the exported free-form schematic, save a wizard
.DAO file (which saves wizard settings).
3. Use HyperLynx 8.2 or newer to export a power-supply net (for the same design as step
1) from BoardSim to LineSim.
4. Open the free-form schematic created in step 3, open a wizard and load the .DAO file
created in step 2.
If you follow the above sequence, you may have to re-select net names and check probe settings
in the wizard to run simulation.

Related Topics
“Exporting Design and Model Data” on page 1151

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 Exporting Design and Model Data
Exporting BoardSim Topologies to HyperLynx 3D EM Designer

Exporting BoardSim Topologies to HyperLynx

3D EM Designer
3-D electromagnetic (EM) simulation excels at modeling structures with impedance
discontinuities, such as signal vias, complex BGA breakout routing, and trace segments or
series blocking capacitors located over a void. It also provides accurate simulation at
frequencies above 6-10 GHz.

Note
The frequency threshold for choosing a 3-D electromagnetic solver is not an arbitrary
number and can depend on design properties, such as signal trace and return current
topologies.

Defining the region and topology to export requires you to study the problem and make an
engineering judgement. Your familiarity with simulating with HyperLynx 3D EM Designer can
help.

To reduce 3-D electromagnetic simulation run time, consider exporting only the minimum
amount of data needed to simulate the topology of interest. You probably do not want to export
an entire SERDES channel topology to HyperLynx 3D EM Designer. HyperLynx SI quickly
and accurately simulates routing with well-controlled impedance, so sending lengthy routing to
HyperLynx 3D EM Designer simply consumes extra 3D EM simulation set up and run time.
Requirement: The 3D Area Model Export license is required to export topologies from
BoardSim.

Restriction: This feature is available only when running 32-bit software. On Windows 64-bit
installations, the 32-bit software is also installed and available from the Start menu in the
HyperLynx <release> 32-bit folder. By contrast, Linux installations are 64-bit only or 32-bit
only.

Procedure
1. Load the board and identify the channel topology to model and simulate with a 3-D
electromagnetic solver.
This typically includes structures with impedance discontinuities, such as signal vias,
complex BGA breakout routing, and trace segments or series blocking capacitors
located over a void.
2. Select Export > HyperLynx 3D EM Topology. The Export to HyperLynx 3D EM
Dialog Box opens.
3. Optionally, edit the location and file name of the .CCE file to export.
The default file name uses the form <board_name>_3dstruct.cce.

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Exporting BoardSim Topologies to HyperLynx 3D EM Designer

The default folder is the design folder. See “About Design Folder Locations” on
page 1391.
4. Specify the region to export by doing any of the following:
• Dragging a rectangle across a region of the board.
• Manually entering rectangle coordinates.
• Selecting Whole Board.
You can update region coordinates by entering new values and pressing <Enter>.
You can move the Export to HyperLynx 3D EM Dialog Box out of the way and use
board viewer features, such as zooming and selecting nets, to help find the region to
export. See “Summary of Board Viewer Operations”.
5. Select the stackup layers, nets, and objects to export.
Export at least one signal net and one reference net. Later, when setting up HyperLynx
3D EM Designer, you will identify each exported net as one of the following:
• Critical nets—Included in 3-D electromagnetic simulation and connected to an S-
parameter model port.
• Reference nets—Included in 3-D electromagnetic simulation and connected to an S-
parameter model port.
• Coupled nets—Included in 3-D electromagnetic simulation, but not connected to an
S-parameter model port.
• Non-critical nets—Not included in 3-D electromagnetic simulation.
To filter the Include Nets list, specify a string and click Apply. The filter box supports
wildcard characters. Use the asterisk * wildcard to match any number of characters. Use
the question mark ? wildcard to match any one character.
6. Optionally, select Open in HyperLynx 3D EM solver after export.
Restrictions:
• This option is unavailable on computers running Linux.
• This option is unavailable if the IE3DAGIF license is unavailable.
7. Click Export.
Results:
The .CCE file is written to the location you specified in step 3.
If you enabled Open in HyperLynx 3D EM solver after export in step 6, the Mentor CCZ
to HyperLynx 3D EM Flow dialog box displays the exported topology. For basic
information about running 3-D EM simulation to create an S-parameter model that

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Exporting BoardSim Topologies to HyperLynx 3D EM Designer

represents the exported topologies, see “Evaluating Exported BoardSim Topologies” on

page 1167.

Related Topics
“Export to HyperLynx 3D EM Dialog Box” on page 1588
“Evaluating Exported BoardSim Topologies” on page 1167

Evaluating Exported BoardSim Topologies

Once you have exported BoardSim topologies to a .CCE file, use HyperLynx 3D EM Designer
to set up simulation to create a Touchstone model. Use the Touchstone Viewer or LineSim to
evaluate the Touchstone model.

Requirement: The IE3DAGIF license is required to open the exported topology in the
HyperLynx 3D EM solver.

Restrictions:

• This feature is available only when running 32-bit software. On Windows 64-bit
installations, the 32-bit software is also installed and available from the Start menu in
the HyperLynx <release> 32-bit folder. By contrast, Linux installations are 64-bit only
or 32-bit only.
• The “Mentor CCZ to HyperLynx 3D EM Flow” in HyperLynx 3D EM Designer is
unavailable on computers running Linux. Open the exported .CCE file on a Windows
32-bit computer.

Procedure
1. If needed, open the exported .CCE file in HyperLynx 3D EM Designer.
a. Select Start menu > All Programs > Mentor Graphics SDD > [ HyperLynx
<version> | HyperLynx <version> 64-bit] > HyperLynx 3D EM > Program
Manager.
b. If the HyperLynx 3D EM Program Manager License Configuration dialog box
opens, select HyperLynx 3D EM Designer and click OK.
The HyperLynx 3D EM Program Manager dialog box opens.
c. Select HyperLynx 3D EM Designer > Agif.
The HyperLynx 3D EM SI dialog box opens.
d. Select Mentor CCZ to HyperLynx 3D EM Flow, click OK, and then browse to the
exported .CCE file.
The Mentor CCZ to HyperLynx 3D EM Flow dialog box opens.

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Exporting BoardSim Topologies to HyperLynx 3D EM Designer

2. Set up the exported topologies for simulation.

Refer to HyperLynx 3D EM Designer - AGIF Manual for information about setting up
the simulation. Click Help on the Mentor CCZ to HyperLynx 3D EM Flow dialog box.
Use various dialog boxes to do the following:
a. Define or “build” the physical 3-D model to solve.
b. If needed, add geometries to the physical 3-D model to receive ports.
c. Assign ports within the 3-D mesh structure.
d. Review the meshed structure and verify that it represents what you intend to
simulate.
e. Specify an adequate frequency range for simulation.
f. Run 3-D electromagnetic simulation to create the S-parameter model.
3. Optionally, use the Touchstone Viewer to evaluate the S-parameter model for insertion
loss, return loss, and other behaviors.
4. Optionally, use LineSim to evaluate the S-parameter model.
For example, if you modeled a signal via and the geometries immediately surrounding it
in HyperLynx 3D EM Designer, do the following:
a. Export the net(s) you specified in step 5 from BoardSim to a LineSim free-form
schematic. See “Exporting BoardSim Nets to LineSim” on page 1161.
b. In the free-form schematic, find the signal via that you modeled in HyperLynx 3D
EM Designer, and delete it.
c. From the symbol palette, select Add S-Parameter/SPICE Model to schematic, and
place the new symbol where the via symbol used to be.
d. Double-click the S-Parameter/SPICE Model symbol and assign to it the S-parameter
model created in step 2.f.
For information about using the Assign S-Parameter/SPICE Model dialog box, see
“Selecting S-Parameter and SPICE Models for Packages and Connectors”.
e. Connect the S-Parameter/SPICE Model symbol to net(s) in the free-form schematic.
f. Simulate the LineSim free-form schematic.

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Exporting BoardSim Boards to IBIS EBD Models

Related Topics
“Export to HyperLynx 3D EM Dialog Box” on page 1588
“Exporting BoardSim Topologies to HyperLynx 3D EM Designer” on page 1165

Exporting BoardSim Boards to IBIS EBD Models

The .EBD model generator is an optional BoardSim feature that allows you to generate an IBIS
.EBD model from a board file. The .EBD model generator is highly automated, so you may
need only a minimal knowledge of the .EBD syntax to create .EBD models.

Requirement: The EBD Writer license is required to generate IBIS .EBD models from
BoardSim board files.

The IBIS (I/O Buffer Information Specification) .EBD (electrical board description) format
enables you to describe:

• The electrical properties of the interconnections on your board

• The components that plug into your board
• Your board as a single component
• Your board's electrical properties without revealing its physical properties
This topic contains the following:

• “About EBD Models Generated by BoardSim” on page 1169

• “Preparing the Board for EBD Model Generation” on page 1170
• “Generating an EBD Model” on page 1171

Related Topics
“The EBD - Electrical Board Description - Format” on page 512

“IBIS Specification” on page 1327

About EBD Models Generated by BoardSim

This topic discusses the contents and limitations of EBD models created by BoardSim.

EBD Models Represent Only External Nets

The .EBD model can contain only nets that connect to external pins; there is no provision in the
IBIS specification to include nets that do not touch an external connector. Therefore the .EBD
generator will not write to the .EBD model any nets that are purely internal to the board file.

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Exporting BoardSim Boards to IBIS EBD Models

Nets that are conductively associated with an external net will be included in the generated
.EBD model.

EBD Models Cannot Represent Coupling Information

The .EBD model cannot represent coupling between nets; there is no provision in the IBIS
specification for including coupling information. Therefore, even if coupling has been enabled
in BoardSim, coupling data will be ignored and are not written to the .EBD model.

EBD Models Cannot Represent Ferrite Beads

The IBIS specification allows an .EBD model to point only to .IBS and other .EBD models.
However, .IBS and .EBD models cannot represent ferrite bead components. An error will be to
the screen if a component on the target net has been assigned a ferrite bead model when
BoardSim generates the .EBD model.

EBD Models Cannot Contain PML MOD or SPICE IC Models

The IBIS specification allows an .EBD model to point only to .IBS and other .EBD models. If
another IC model type is assigned to an IC on the target net, no model will be assigned to that IC
in the generated .EBD model.

See also: “Preparing the Board for EBD Model Generation” on page 1170

Power-Supply Net Names are Constants

Pins connected to power-supply nets and an external connector on your board, will be written
out only as "POWER" or "GND" in the .EBD model generated by BoardSim.

For example, if the original power-supply pin names were "Power3.3" and "GndDig," the
corresponding .EBD model power-supply pin names created by the .EBD model generator will
be "POWER" and "GND." In this case, you must edit the .EBD model generated by BoardSim
to restore the original power-supply pin names.

In BoardSim, you can interactively add nets to, or subtract nets from, the power supply list.

See also: “Editing Power-Supply Nets”

Preparing the Board for EBD Model Generation

For each net you want to include in the generated .EBD model, assign .IBS or .EBD models to
all ICs.

The IBIS specification allows an .EBD model to point only to .IBS or .EBD models. When ICs
on the target net have been assigned to .PML, .MOD, SPICE, or Touchstone models, BoardSim
displays a warning to the screen and to the [Reference Designator Map] section of the generated

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.EBD file. To find this type of warning in the generated .EBD file, search for "Warning: Supply
a valid mapping."

Restriction: BoardSim does not support .EBD models that point to other .EBD models.
However, BoardSim does support .EBD models that point to .IBS models.

Occasionally, you may have a board file in which two or more connectors together define the
external interface of the .EBD file. However, BoardSim supports only one connector to define
the external interface of the .EBD file.

Generating an EBD Model

To convert a board file to an .EBD model:

1. Load the board file into BoardSim.

Alternative: If the board is already loaded, Select File > Save BoardSim Session File.
2. Select Export > Board To > IBIS .EBD File.
Result: The Choose .EBD External Connector dialog box opens.
3. In the Reference Designator list, select the reference designator for the external
connector for the .EBD model you want to create.
4. To include vias in the .EBD model, select the Include vias in EBD description check
box. Via L and C depend on the via simulation options you set in the Select Method of
Simulating Vias Dialog Box.
5. Click OK. The Save EBD File dialog box opens.
6. Select or type the .EBD file name and click Save.
7. If BoardSim cannot map an IC model to an IC reference designator used in the .EBD
model, it will write dummy File Name and Component Name parameters to the
[Reference Designator Map] section of the .EBD file it has written.
Search for "Warning: Supply a valid mapping" in the .EBD file to identify IC reference
designators which have not been mapped to an IC model.
8. Check the syntax of the new .EBD model. See “Checking IBIS File Syntax” on
page 428.

Related Topics
“Exporting BoardSim Boards to IBIS EBD Models” on page 1169

“Exporting Design and Model Data” on page 1151

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Exporting Design and Model Data
Exporting BoardSim Boards to ICX

Exporting BoardSim Boards to ICX

In BoardSim, run Export to ICX to create the files needed to simulate the board in ICX. With
this capability, you can begin analyzing the board in HyperLynx, and then export the board to
ICX for more-advanced analysis.

This topic contains the following:

• “Capabilities” on page 1172

• “Limitations for Export to ICX” on page 1172
• “Steps to Export the Board to ICX” on page 1172
• “Optional Export Settings” on page 1173

Capabilities
Export to ICX can export the following properties to the ICX design:

• Component-wide .IBS model assignments made using the .REF automapping file
• Interactive buffer direction assignments for .IBS bidirectional buffers
• Physical termination components, including values set interactively or by the .REF file
• Series passive components, which are automatically translated into IBIS files

Limitations for Export to ICX

Export to ICX cannot export the following properties to the ICX design:

• Interactive .IBS model assignments

• MultiBoard projects
• .EBD, SPICE, Touchstone, .PML, and .MOD IC model assignments
• Quick Terminators (virtual terminators)

Steps to Export the Board to ICX

Caution
We recommend that you do not select any nets before exporting the board to ICX. If you
are unsure, close the board and re-open it before exporting the board to ICX. When you
select a net, BoardSim "net cleaning" behavior automatically deletes segments that lie
entirely within pads. ICX may not properly recognize connectivity if these segments are
deleted.

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Exporting BoardSim Boards to ICX

To export the board to ICX:

1. Select Export > Board To > ICX NDD File.

2. To change the output directory or the .NDD (neutral design data) file name, click
Browse, type or browse to the new location, and then click Save.
3. If HyperLynx and ICX are on the same computer, you can do the following:
a. To translate the .NDD file into an .ICX file and other related files, select the Run
XFORM utility to create .ICX file check box.
b. To launch ICX after export has completed, select the Launch ICX IS after export
check box.
4. To copy the IBIS models to the output directory, select the Copy IBIS files to output
directory check box. You can disable this option if the files are too big, too numerous,
or already exist in the output directory.
5. Click OK.
Result: The .NDD, .SCM, and .IBS files are created. ICX uses the .SCM file to load
models for series components when opening the design.
Requirement: The .NDD, .SCM, and .IBS files must be used together.
6. If you selected the Run XFORM utility to create .ICX file check box in step a, and
XFORM fails to create the .ICX file, click the Show LOG File button to display
XFORM messages.
7. If HyperLynx and ICX are not on the same computer, go to a computer with ICX and
run the ICX XFORM utility to translate the exported .NDD file into an .ICX file and
other related files. For information about running XFORM, see Appendix A in the IS
User's Guide provided with ICX.

Optional Export Settings

For additional control over the export to ICX process, you can add the following parameters to
the BSW.INI file's [EXPORT_TO_ICX] section:

Table 28-1. Export to ICX - Optional Export Settings

Parameter Description
Extra_XFORM_options=<values> Set the parameter value to "-n -w" (without the double-
quote characters) to add additional warnings and notes to
the XFORM log file.

See ICX documentation for other parameter values.

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Exporting LineSim Schematics to BoardSim

The BSW.INI file is located in the same folder as the HyperLynx application file bsw.exe
(Windows) or bsw (Solaris). For example,
C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx\bsw.exe. In Windows, you can
learn the folder name by right-clicking over the "HyperLynx Simulation Software" Start menu
item, and then clicking Properties. The Target box contains the folder name.

To set optional export settings in the BSW.INI file:

1. If BoardSim is open, close it.

You may want to print these instructions before closing BoardSim.
2. Open BSW.INI with Notepad or another text editor. BSW.INI is stored in the
HyperLynx installation directory, where the BSW.EXE application is located.
3. In the [EXPORT_TO_ICX] section, make any of edits in Table 28-1. If
"[EXPORT_TO_ICX]" does not exist, add it to the last row in the file, and then add the
new parameters below it.
4. Save the edits and close the text editor. The changes take effect the next time you open
BoardSim.

Related Topics
“Exporting Design and Model Data” on page 1151

Exporting LineSim Schematics to BoardSim

LineSim can create a BoardSim .HYP file that is electrically equivalent to the LineSim
schematic. An application of this feature is to define "what if" interconnect in LineSim for a
board that has not been laid out yet. See the following examples:

• You might have a motherboard .HYP file, but you have not yet decided how to lay out
two plug-in daughter PCBs. You could draw in LineSim the hypothetical path for the
daughter PCB, export the path to a .HYP file, plug the daughter card into the
motherboard with a MultiBoard project, and then simulate.
• Use LineSim to draw a flex cable or other connector, export the connector to a .HYP
file, and then include it in a MultiBoard project to connect two boards.
The exported board may appear to have random component placement and routing. The
schematic doesn't contain physical information, so the exported .HYP file contains components
with arbitrary positions and virtual nets rather than routed nets.

Restriction: PDN Editor geometries are not exported to BoardSim.

Requirement: The Via Models license is required to export vias to BoardSim.

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Exporting Constraint Templates from LineSim

To export the schematic to a .HYP file:

1. Select Export > BoardSim Board.

2. Type or browse to the .HYP file, and click Save.
Result: The exported .HYP file contains all schematic components and IC model
information. The .HYP file has arbitrary placements for components and nets, but it
should behave accurately from an electrical perspective.

Related Topics
“Exporting Design and Model Data” on page 1151

Exporting Constraint Templates from LineSim

Use the Export Constraint Template dialog box to export a constraint template file and to
optionally update CES, based on properties of the selected LineSim net. This capability enables
you to define net topologies in LineSim that have good signal-integrity and transfer that
information to constraint-aware Mentor Graphics software, such as Constraint Editor System
(CES) or Constraint Template Editor (CTE). Usually the goal of constraints is to constrain
routing in downstream routers.

Constraint templates are a reusable set of constraints that can be applied to similar nets in
different designs. Constraint templates can contain electrical constraints (such as maximum
transmission-line lengths), physical constraints, FromTos (net scheduling), IC model
assignments, and so on. You can collect constraint templates libraries, which provides a way to
apply known-good design rules to nets in new designs.

Restriction: The cell-based schematic editor cannot export constraint template files.

Prerequisites
If you plan to automatically update CES with the contents of the exported template file, start
CES before performing step 7.

Starting with HyperLynx 8.2, this feature encrypts constraint data before sending it to CTE. EE
7.9.3 and newer can read the encrypted constraint data, but older EE releases cannot. If you use
an older EE release, you can force this feature to send unencrypted constraint data. See “Setting
CTM_NON_ENCRYPTION”.

Procedure
1. Add part names to IC symbols on the net by double-clicking each symbol and typing a
value in the Part Name box in the Assign Models dialog box.
2. Select the net by doing any of the following:

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Exporting Constraint Templates from LineSim

• Right-click a driver IC symbol or an IC pin and click Create Constraint Template:

• Click the driver IC symbol and click Export menu > Constraint Template.
• Select Export > Constraint Template. If no driver IC symbol is selected and there
is more than one driver in the schematic, the Select Driver dialog box opens. Select
the driver pin and click OK.
The Export Constraint Template dialog box opens.
3. To specify detailed constraint values, click Edit Template. The Define Constraint
Template Dialog Box opens.
Requirement: If the schematic contains virtual pins or custom topologies, specify the
net scheduling in the Net Scheduling tab of the Define Constraint Template Dialog Box.
If you do not specify detailed constraints, the template contains a default set of pin pairs,
FromTos, maximum delays, IC models (if assigned), and so on.
Maximum delays are not exported for “simple” transmission lines because they do not
contain physical transmission-line lengths.
4. Type the template name to display in the CTE or CES application.
5. Type or browse to the template file name and folder.
You can export template files in the following formats:
• .CTM—Used by Expedition 2007 and newer. Selected by default.
• .CMS—Used by pre-Expedition 2007. Export by clicking Browse, in the Save As
Type list (in the Export Constraints To dialog box), select Constraint Files (*.CMS),
and then click Save.
6. To automatically open the exported template file, select Open generated template in
the Constraint Template Editor.
Requirement: Expedition 2005.1 or newer must be on the same computer to
automatically open CTE. If you have another flow release, you can manually open
CES/CTE, and then import the exported template. See the documentation for CES for
information about importing templates.
7. To automatically update CES with the contents of the exported template file, select
Update CES with generated template.
Requirements:
• This option is available only when CES exported the original free-form schematic.
• CES must be running to complete this operation.
• EE 7.9.3 or newer must be on the same computer to update CES.
8. Click OK.

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Exporting Nets from CES to LineSim

Related Topics
“Exporting Design and Model Data” on page 1151

“Define Constraint Template Dialog Box” on page 1528

Exporting Nets from CES to LineSim

You can export one or more electrical nets from the Nets page of the CES spreadsheet to a
LineSim free-form schematic. For information about this process, see the topic “Sending Nets
to HyperLynx LineSim” located in the CES documentation.

Importing Constraints from CES to BoardSim

You can use BoardSim to import the following types of constraints from CES:

• Constraints—Import to batch simulation spreadsheets. See “Batch Simulation

Spreadsheet”.
• Model assignments—Import to REF automapping files. See “Importing Model
Assignments from CES to REF Files”.

Exporting and Importing Stackups

You can reuse stackups among designs. Exporting/importing known good stackups can save
time when preparing the design for simulation. This capability also enables you to create a
backup copy of the stackup, which can be helpful when performing multiple “what if”
experiments.

Stackup (.STK) files contain exported stackup properties. Note that you can import stackups
directly from free-form schematic files (.FFS), so it is unnecessary to export the stackup from
the free-form schematic before importing it into another design.

Restrictions:

• You can cannot import stackups that contain fewer layers than the current design.
• Cell-based schematics do not support stackup importing or exporting.
• Stackup layer names are not imported, when a one-to-one layer mapping exists. This
behavior preserves existing design settings linked to existing layer names. For example,
transmission lines that use the stackup model type refer to stackup layer names.
To export a stackup:

1. Select Setup > Stackup > Export.

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Exporting and Importing Stackups

The Save as dialog box opens.

2. Type or select the .STK file location and click Save.
To import a stackup:

1. Select Setup > Stackup > Import.

The Open dialog box opens.
2. From the Files of Type list, select whether to import from a stackup file (.STK) or a free-
form schematic file (.FFS).
3. Select the file to import and click Open.
4. If you import a stackup containing more layers than the current design, the Layer
Mapping dialog box opens. See “Layer Mapping for Importing Stackups” on page 1178.
a. Click the Destination Layer cell to specify any of the following mappings:
• <layer_name>—Replace the current Destination Layer with the imported
Source Layer.
• Not Imported—Do not use the Source Layer.
• New Layer—Insert the Source Layer. New layer names are of form
new_layer_<number>.
b. Click OK.
The Used spreadsheet column identifies stackup layers that are used by nets in the board
or schematic.
5. Verify or edit the imported stackup with Stackup Editor.

Related Topics
“Creating and Editing Stackups” on page 353

Layer Mapping for Importing Stackups

Use the Layer Mapping dialog box to map stackup layers in the source design to stackup layers
in the current design. This dialog box opens only when you import a stackup containing more
layers than the current design.

The Used spreadsheet column identifies stackup layers that are used by nets in the board or
schematic.

To map stackup layers between the source and current designs:

1. Click the Destination Layer cell to specify any of the following mappings:

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Exporting and Importing Stackups

• <layer_name>—Replace the current Destination Layer with the imported Source

Layer.
• Not Imported—Do not use the Source Layer.
• New Layer—Insert the Source Layer. New layer names are of form
new_layer_<number>.
2. Click OK.

Related Topics
“Exporting and Importing Stackups” on page 1177

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Exporting Design and Model Data
Exporting Signal Vias to S-Parameter Models

Exporting Signal Vias to S-Parameter Models

You can export S-parameter models representing signal vias to visualize their behavior in the
frequency domain or to use them when simulating designs with other software. For example,
you can use the Touchstone Viewer to view the behavior of the via in the frequency domain,
which is good for customers who design SERDES channels entirely in the frequency domain
and study channels in terms of loss.

Before exporting signal-via models, verify the design setup and model assignments. See
“Setting Up Designs for Power-Integrity Simulation” on page 341.

You can export signal vias from BoardSim/LineSim. Or you can perform “what if” experiments
by exporting the signal via from BoardSim and using the exported S-parameter model in a S-
Parameter/SPICE Model symbol in a LineSim free-form schematic.

In LineSim, you can also create an S-parameter model for a signal via by running 3-D
electromagnetic simulation. See “Via Properties Dialog Box” on page 1908.

Note
For computers running on Windows or Linux, this feature runs on all available cores.

For computers running on Solaris, this feature runs on one core.

Restrictions:

• The Signal-Via Bypass Models license is required to export via models.

• S-parameter models can be exported for differential vias only when the vias have
symmetrical connections and connect to exactly two stackup layers.
• In BoardSim, the exporting via models feature does not include power-supply nets
formed entirely by trace segments.
• The exporting via models feature is unavailable when a MultiBoard project is loaded.
This topic contains the following:

• “Running Export to Signal-Via Models” on page 1181

• “Files Written by Signal-Via Model Extraction” on page 1182

Related Topics
“Exporting Nets to S-Parameter Models” on page 1152

“Exporting PDNs to S-Parameter Models” on page 1183

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Exporting Signal Vias to S-Parameter Models

Running Export to Signal-Via Models

Use the Via Model Extractor Wizard to export signal vias as S-parameter models.

To export signal-via models:

1. Select Export > Model > Signal-Via Model (LineSim) or select Export > Signal-Via
Model (BoardSim). The Via Model Extractor Wizard opens.
Restriction: The exporting via models feature is unavailable when a MultiBoard project
is loaded.
2. On each wizard page, edit options and values as needed. Navigate among wizard pages
by clicking one of the following:
• Back/Next—Go to the previous/next page.
• <wizard_page_name> in the table of contents pane—Jump directly to the named
page. See “About the Signal-Via Model Extractor Wizard Table of Contents Pane”
on page 1181.
3. Repeat step 2 as needed to continue through the wizard.
4. On any page, click Run Analysis.
The Run Analysis button (to the right of the Next button) displays other labels,
depending on the completeness of the setup data and whether you chose (on the Start
Analysis or Run Analysis page) to save the wizard settings to a file.
If you click Cancel (in the Frequency-domain distributed electromagnetic dialog box)
while the export feature is sweeping frequencies, the Touchstone model contains all the
results up to the frequency point that was last calculated.
5. The Touchstone and Fitted-Poles Viewer automatically displays the exported S-
parameter model.
See “Zooming Panning and Other Curve-Examination Tools” on page 1075 and “Files
Written by Signal-Via Model Extraction” on page 1182.

About the Signal-Via Model Extractor Wizard Table of Contents

Pane
You can navigate directly to a wizard page by clicking its name in the table of contents pane,
which is located near the left side of each wizard dialog box.

The color of a non-highlighted page name indicates the following:

• White—All required information is specified.

• Red—Some required information is not specified.

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Exporting Signal Vias to S-Parameter Models

• Gray—On the first wizard page, you have enabled the Load Saved Configuration option,
but have not yet specified a file.

Related Topics
“Exporting Signal Vias to S-Parameter Models” on page 1180

Files Written by Signal-Via Model Extraction

Signal-via model extraction writes S-parameter, log, and optional power-integrity wizard option
files to the <design> folder. See “About Design Folder Locations” on page 1391.

Table 28-2. Signal-Via Output Files - Exporting

File Description
<design>_<M>.s<N>p S-parameter file showing the signal scattering characteristics of the
signal via or differential via pair over a frequency range. Use the
Touchstone Viewer to view S-parameter files. See “Viewing and
Converting Touchstone and Fitted-Poles Models” on page 1065.

File name uses the form <design>_<M>.s<N>p where:

• design—name of the board or free-form schematic
• M—starts at “empty” and increments by one for each export.
For example, design_.s1p and design_1.s1p.
• N—<number_of_ports>. For single vias, there is a port for
every stackup layer connected to the via. For differential vias,
the number of ports depends on the via model type you enabled
on the Set Model Type page.
DV.log Export signal-via log file. Use the Reporter Dialog Box to view log
files, such as when investigating analysis failures or unexpected
results.
<design>.dao (optional) Power-integrity wizard options file. Contains the Via Model
Extractor wizard settings.

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Exporting PDNs to S-Parameter Models

Exporting PDNs to S-Parameter Models

Export a detailed model of the entire power-distribution network (PDN), with external ports at
your choice of IC power-supply pin and signal via locations. The result is an S-parameter model
that accounts for the effects of the entire PDN, including stitching vias, decoupling capacitors,
and buried capacitance.

You can view ports located at signal vias to study insertion and return loss.

You can include the model in complex system level plane noise simulations where, for example,
the signal ports are driven by SPICE buffer models and IC package models connect to the IC
power-pin ports. See “Simulating Plane Noise” on page 1037.

You can export PDN models from BoardSim/LineSim. Or you can perform “what if”
experiments by exporting the PDN geometries and electrical connections from BoardSim to
LineSim and editing the PDN in the PDN Editor.

Before exporting PDN models, verify the design setup and model assignments. See “Setting Up
Designs for Power-Integrity Simulation” on page 341.

Note
For computers running on Windows or Linux, this feature runs on all available cores.

For computers running on Solaris, this feature runs on one core.

Restrictions:

• The PDN Model Export license is required to export PDN models.

• In BoardSim, the exporting PDN models feature does not include power-supply nets
formed entirely by trace segments.
• The exporting PDN models feature is unavailable when a MultiBoard project is loaded.
This topic contains the following:

• “Running Export to PDN Models” on page 1184

• “Files Written by PDN Model Extraction” on page 1185

Related Topics
“Exporting Nets to S-Parameter Models” on page 1152

“Exporting Signal Vias to S-Parameter Models” on page 1180

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Exporting Design and Model Data
Exporting PDNs to S-Parameter Models

Running Export to PDN Models

Use the PDN Model Extractor wizard to export PDNs as S-parameter models.

Procedure
1. Select Export > Model > PDN & Channel Model (LineSim) or select Export > PDN
Model (BoardSim). The PDN Model Extractor Wizard opens.
Restriction: The exporting PDN model feature is unavailable when a MultiBoard
project is loaded.
2. On each wizard page, edit options and values as needed. Navigate among wizard pages
by clicking one of the following:
• Back/Next—Go to the previous/next page.
• <wizard_page_name> in the table of contents pane—Jump directly to the named
page. See “About the PDN Model Extractor Wizard Table of Contents Pane” on
page 1184.
3. Repeat step 2 as needed to continue through the wizard.
4. On the last page, click Run Analysis.
The Run Analysis button (to the right of the Next button) displays other labels,
depending on the completeness of the setup data and whether you chose (on the Start
Analysis or Run Analysis page) to save the wizard settings to a file.
If you click Cancel while the export feature is sweeping frequencies (in the Frequency-
domain distributed electromagnetic dialog box), the Touchstone model contains all the
results up to the frequency point that was last calculated.
5. The Touchstone and Fitted-Poles Viewer automatically displays the exported S-
parameter model.
See “Zooming Panning and Other Curve-Examination Tools” on page 1075 and “Files
Written by PDN Model Extraction” on page 1185.

About the PDN Model Extractor Wizard Table of Contents Pane

You can navigate directly to a wizard page by clicking its name in the table of contents pane,
which is located near the left side of each wizard dialog box.

The color of a non-highlighted page name indicates the following:

• White—All required information is specified.

• Red—Some required information is not specified.

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Exporting PDNs to S-Parameter Models

• Gray—Similar to red, some required information is not specified. Gray is used on the
first wizard page when you click the Load Saved Configuration option, but have not yet
specified a file.

Related Topics
“Exporting PDNs to S-Parameter Models” on page 1183

Files Written by PDN Model Extraction

PDN model extraction writes S-parameter, log, and optional power-integrity wizard option files
to the <design> folder. See “About Design Folder Locations” on page 1391.

Table 28-3. PDN Output Files - Exporting

File Description
<design>_<M>.s<N>p S-parameter file showing the signal scattering
characteristics of the PDN over a frequency range. Use
the Touchstone Viewer to view S-parameter files. See
“Viewing and Converting Touchstone and Fitted-Poles
Models” on page 1065.

File name is of form <design>_<M>.s<N>p where:

• design—name of the board or free-form schematic
• M—starts at “empty” and increments by one for
each export. For example, design_.s1p and
design_1.s1p.
• N—<number_of_ports> There is one port for every
IC pin. There is one port for every stackup layer
connection to a single or differential via.
Port-to-component pin mapping Maps Touchstone model ports to component pins.
file—
<design>_<analysis_iteration>.ports The port numbers correspond to wizard spreadsheet
numbers. See Figure 28-1 on page 1186.
ME.log Export PDN log file. Use the Reporter Dialog Box to
view log files, such as when investigating analysis
failures or unexpected results.
<design>.dao (optional) Power-integrity wizard options file. Contains the PDN
Model Extractor wizard settings.

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Gathering and Archiving Design Simulation Files

Figure 28-1. Mapping Spreadsheet Ports to Exported PDN Model Ports

Gathering and Archiving Design Simulation Files

Use the Archive Design Dialog Box to automatically gather and compress the design simulation
files for your board or schematic. You can do the following tasks with the Archive Design
utility:

• Take a “snapshot” of your board analysis files at a specific moment in your PCB design
cycle, so they can be restored (if necessary) at a later time.
• If you have experienced problems with a board or schematic, you can use Archive
Design to automatically gather all the files together into a single ZIP file to send to
technical support for investigation.
It is usually not sufficient to send only the BoardSim board file or the LineSim
schematic file to technical support. For example you may be using BoardSim and your
session edits are stored in the .BUD file.

Procedure
1. Do one of the following:
• If you are using BoardSim, load the board into BoardSim.
• If the board is already loaded and you have made changes to the design, select File >
Save BoardSim Session File. See BoardSim Session Files.
• If you are using LineSim, load the schematic into LineSim.
• If the schematic is already loaded and you have made changes to the design, select
File > Save.
2. Select Export > Design Archive. The Archive Design Dialog Box opens.
3. Enable options, specify the archive folder location, and click OK.

Files That Are Not Archived

• Batch simulation report file (.txt)

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Gathering and Archiving Design Simulation Files

• Backup BoardSim User Data (.BBD) files. Note that .BUD files are archived.
• Design Change Summary files (.txt)

About InfoZip
The Archive Design utility uses InfoZip technology.

Copyright (c) 1990-2001 Info-ZIP. All rights reserved.

The “zip” executable included with HyperLynx is Info-ZIP's compression utility. It is used by
HyperLynx to compress archive files. Info-ZIP's software (Zip, UnZip and related utilities) is
free and can be obtained as source code or executables from various anonymous-ftp sites,
including ftp.uu.net:/pub/archiving/zip/*. There is no charge for this software.

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 About Crosstalk in LineSim and BoardSim
Overview of LineSim and BoardSim Crosstalk

Chapter 29
About Crosstalk in LineSim and BoardSim

Use crosstalk analysis to understand how much crosstalk occurs when a signal propagates on a
PCB trace that is routed near two or more other traces. Crosstalk analysis can help you identify
excessive crosstalk on unrelated signals, accurately simulate differential signals, and so on.

This topic contains the following:

• “Overview of LineSim and BoardSim Crosstalk” on page 1189

• “Running the Field Solver in LineSim” on page 1199
• “Running Interactive Crosstalk Simulations in BoardSim” on page 1219
• “Running the Field Solver in BoardSim” on page 1235

Related Topics
“Technical Background on Crosstalk and Differential Signaling” on page 1348

“Adding Coupling to LineSim Schematics”

“Application Examples for LineSim Crosstalk”

Overview of LineSim and BoardSim Crosstalk

Welcome to the HyperLynx Crosstalk product. This add-on to the base LineSim and BoardSim
products extend those programs by adding powerful crosstalk and differential-pair analysis.

This topic contains the following:

• “About HyperLynx Crosstalk Analysis Options for LineSim and BoardSim” on

page 1190
• “How the Crosstalk Analysis Option Works with the Base LineSim Product” on
page 1193
• “How to Learn LineSim Crosstalk” on page 1194
• “What BoardSim Crosstalk Adds to the Base BoardSim Product” on page 1195
• “Applications Made Possible by BoardSim Crosstalk” on page 1195
• “Recommended Way to Use BoardSim Crosstalk Features” on page 1198

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Overview of LineSim and BoardSim Crosstalk

About HyperLynx Crosstalk Analysis Options for LineSim

and BoardSim
HyperLynx’s Crosstalk options for LineSim and BoardSim are powerful tools that enable you to
predict the effects of crosstalk on your PCB designs before beginning the expensive production
process. You can use this information to make informed decisions about which interconnect
scenarios are likely to be impacted by crosstalk and other coupling effects. HyperLynx’s
crosstalk analysis takes into account all types of design scenarios — from simple pairs of side-
by-side nets to the intricate, high-speed bus topologies on today's complex backplane designs.

Understanding the crosstalk aspects of your physical implementation before PCB layout (and
even schematic entry, using LineSim Crosstalk) will minimize costly, schedule-impacting
redesign.

Specifically, the Crosstalk option for LineSim:

• Focuses on pre-route analysis

• Extends the LineSim product interface to analyze coupled transmission lines
• Accurately predicts crosstalk waveforms, including forward and backward effects, for
any trace topology and IC placement
• Correctly simulates both short- and long-wire crosstalk
• Generates summaries of coupled trace impedance, signal-propagation delays, and
capacitance and inductance matrices
With LineSim Crosstalk’s full analysis of differential pairs, you can achieve desired differential
impedance and simulate differential signals, including the effects of inter-pair crosstalk. You
can also optimally terminate differential pairs for differential- and common-mode signal
components. LineSim's Crosstalk’s analysis flexibility makes it easier to generate PCB
constraints early in the design process so you can get your boards right the first time.

Up-front, pre-layout generation of crosstalk routing constraints allows you to:

• Develop a clear understanding early in the design cycle of where crosstalk problems are
likely
• Plan effective strategies for reducing/eliminating crosstalk up-front before layout
• Study the tradeoffs between different routing topologies, board-layer stackups, and IC-
driving technologies
• Examine the effect of grounded guard traces and compare their usage to increasing trace
separation
• Find accurate constraints for optimum reduction of coupling, including:
• Minimum trace-to-trace spacing

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 About Crosstalk in LineSim and BoardSim
Overview of LineSim and BoardSim Crosstalk

• Maximum parallel run lengths

• Maximum driver-IC slew rates
• Stackup layer thickness and position
BoardSim Crosstalk allows you to analyze crosstalk performance after layout has been
completed, but before a costly prototype is built. This can reduce the number of prototype turns
and lab testing required, improving time to market and reducing product development cost.

Specifically, the Crosstalk option for BoardSim:

• Focuses on post-route analysis

• Extends the BoardSim product interface to analyze coupled transmission lines
• Accurately predicts crosstalk waveforms, including forward and backward effects, for
any routing topology and IC placement
• Quickly and automatically identifies crosstalk aggressors
• Correctly simulates both short and long-wire crosstalk in both interactive and batch
simulations
• Generates summaries of coupled trace impedance, signal-propagation delays, and
capacitance and inductance matrices
With its ability to select coupled "aggressor" nets based on electrical thresholds, nets that
contribute significantly to crosstalk are quickly identified and automatically included in detailed
simulations. You can also optimally terminate nets to reduce crosstalk. BoardSim's analysis
flexibility makes it easier check your crosstalk as soon as routing is begun, so you can get your
boards right the first time.

Post-layout analysis of crosstalk allows you to:

• Quickly identify crosstalk coupled nets using electrical thresholds

• Study the tradeoffs between different termination strategies, board-layer stackups and
IC-driving technologies
• Examine the effect of grounded guard traces
• Plan effective strategies for reducing/eliminating crosstalk by termination, including:
• Reducing driver-IC slew rates
• Changing stackup layer thickness and position
• Changing termination strategy

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Overview of LineSim and BoardSim Crosstalk

Getting Started with Crosstalk in LineSim

If you are licensed for LineSim's crosstalk-analysis option:

You only need to learn a few basic concepts before you can begin productively analyzing
coupled-trace and differential-pair circuits.

• If you like to learn by reviewing examples, see “Application Examples for LineSim
Crosstalk”. These topics give an excellent overview of LineSim's crosstalk-related
features and teach you everything you need to know to get started.
• If you prefer to read in detail about features and capabilities first, see the associated
topics in this Help system, beginning with “Adding Coupling to LineSim Schematics”.
If you are not licensed for LineSim's crosstalk-analysis option:

You can still try some of LineSim's crosstalk-related features, to see if they might be valuable in
your design work. Specifically, you can load any of the following example schematics (located
in the HypFiles folder in the LineSim installation):

• XT_Manual_Basic_Crosstalk_Example.tln
• XT_Manual_Coupled_Differential.tln
• XT_Manual_Trace_Separation.tln
• XT_Manual_Guard_Trace.tln
You can simulate these schematics, view field-solver results, look at how coupling regions are
defined in LineSim, and so forth—but because you are not licensed, you cannot change the
schematics and continue analysis. If you do change something in the drawing or coupling
region, LineSim will refuse to give further results. (The names "XT_Manual_xxx.tln" refer to
the fact that each of these files is the basis for a detailed application example in “Application
Examples for LineSim Crosstalk”.

Getting Started with Crosstalk in BoardSim

If you are licensed for BoardSim’s crosstalk-analysis option:

You only need to learn a few basic concepts before you can begin productively analyzing
crosstalk on routed boards.

See also: “Running Interactive Crosstalk Simulations in BoardSim” on page 1219

If you are not licensed for BoardSim's crosstalk-analysis option:

You can still try some of BoardSim's crosstalk-related features, to see if they might be valuable
in your design work. Specifically, you can load any of the following example schematics
(located in the HypFiles folder in the BoardSim installation):

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Overview of LineSim and BoardSim Crosstalk

• Demo.hyp
• Demodiff.hyp
You can simulate these board layouts, view crosstalk results, look at how electrical thresholds
affect aggressor net selection in BoardSim, and so forth—but because you are not licensed, you
cannot change the layouts and continue analysis. If you do change something in the board
layout, BoardSim will refuse to give further results.

See also: “About Crosstalk in LineSim and BoardSim” on page 1189

How the Crosstalk Analysis Option Works with the Base

LineSim Product
The "base" LineSim product (i.e., the standard product, without crosstalk capability) allows you
to simulate arbitrarily complex schematics that contain virtually any kind of interconnect —
generic transmission lines, lines referenced to a specific kind of PCB cross section, lines
referenced to a complete PCB stackup, connectors, cables, and so forth. However, you cannot
couple any of these lines together, i.e., you cannot simulate the effect of one line
electromagnetically inducing currents and voltages on others.

Certain phenomena in high-speed digital systems arise from exactly this effect. Crosstalk, for
example, occurs when a signal is intentionally driven down one conductor (board trace, cable
wire, connector pin, etc.), but causes an unwanted signal to appear on another nearby conductor.
The induced signal appears even though the two conductors are not conductively connected to
each other.

Differential signaling (increasingly used for high-speed data transfer) also makes use of
electromagnetic coupling, although in this case, the coupling is intentional rather accidental. By
placing two PCB traces, for example, in close proximity, you can ensure that noise externally
induced on one of them also appears on the other (and is therefore rejected by a differential
receiver). But placing traces in close proximity causes them to couple, and concepts that are key
to differential signaling — like differential impedance — arise directly from this coupling.

In essence, what LineSim’s crosstalk option adds to the base LineSim product is the ability
to add coupling to a "standard" LineSim schematic, i.e., information about how various
transmission lines are coupled together. You supply this information geometrically (trace
separations, stackup layer, trace widths and thicknesses, etc.), and LineSim automatically
converts it to electromagnetic coupling parameters. That data, in turn, is used to include the
effects of the coupling in simulation waveforms.

The conversion from geometric to electromagnetic data occurs by running a "field solver," an
analysis engine that uses the basic equations of electromagnetics ("Maxwell’s equations") to
calculate the properties of coupled conductors. This tool is built-in to LineSim’s crosstalk
option; it runs automatically when needed.

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Overview of LineSim and BoardSim Crosstalk

Figure 29-1 shows how LineSim’s crosstalk option adds coupling analysis to the base LineSim
product.

Figure 29-1. Contents of Crosstalk Option in LineSim

How to Learn LineSim Crosstalk

If you prefer to learn by first reading about all of a tool’s capabilities, then the following topics
are recommended:

• “Adding Coupling to LineSim Schematics”

• “Running the Field Solver in LineSim” on page 1199
If you prefer to learn by seeing application examples, see:

• “Application Examples for LineSim Crosstalk”

If you want more background information on crosstalk, coupled transmission lines, and
differential signaling, see “Technical Background on Crosstalk and Differential Signaling” on
page 1348.

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Overview of LineSim and BoardSim Crosstalk

What BoardSim Crosstalk Adds to the Base BoardSim

Product
The "base" BoardSim product (i.e., the standard product, without crosstalk capability) allows
you to simulate traces on an actual routed PCB, including all the details of each trace’s layout:
individual metal segments, vias, pads, and so forth. However, you cannot analyze the effects of
coupling between multiple traces, i.e., you cannot simulate the effect of one trace
electromagnetically inducing currents and voltages on others.

Certain phenomena in high-speed digital systems arise from exactly this effect. Crosstalk, for
example, occurs when a signal is intentionally driven down one board trace, but causes an
unwanted signal to appear on another nearby trace. The induced signal appears even though the
two traces are not conductively connected to each other.

Differential signaling (increasingly used for high-speed data transfer) also makes use of
electromagnetic coupling, although in this case, the coupling is intentional rather accidental. By
placing two PCB traces in close proximity, you can ensure that noise externally induced on one
of them also appears on the other (and is therefore rejected by a differential receiver). But
placing traces in close proximity causes them to couple, and concepts that are key to differential
signaling — like differential impedance — arise directly from this coupling.

In essence, what BoardSim’s crosstalk option adds to the base BoardSim product is the ability
to include the effects of trace-to-trace coupling in simulations. As in base BoardSim, the
electromagnetic modeling is automatic: you choose a net for analysis, and BoardSim Crosstalk
does the difficult work of determining which other nets are significantly coupled to the chosen
net. Then all of the involved nets are modeled and simulated together; the effects of any
crosstalk or coupling between them appears automatically in the simulation results.

The calculation of exactly how traces are coupled to each other occurs by running a "field
solver," an analysis engine that uses the basic equations of electromagnetics ("Maxwell’s
equations") to calculate the properties of coupled conductors. This tool is built-in to BoardSim
Crosstalk; it runs automatically when needed. For maximum performance, the field solver has a
caching mechanism which allows it to calculate a given cross section once and then store that
section’s solution for fast retrieval later, when needed again.

Applications Made Possible by BoardSim Crosstalk

BoardSim Crosstalk adds several important application abilities to the base BoardSim product.
Figure 29-2 summarizes these.

This topic discusses the following;

• “Crosstalk Analysis - BoardSim Crosstalk Option” on page 1196

• “Differential-Signal Analysis” on page 1197
• “Effects of Nearby Traces for Signal-Integrity Simulations” on page 1197

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Overview of LineSim and BoardSim Crosstalk

Restriction: Crosstalk analysis is not available for nets that have been unrouted or routed using
BoardSim's Manhattan routing.

See also: “Crosstalk Analysis Not Available for Manhattan Routing” on page 1197

Figure 29-2. Contents of Crosstalk Option in BoardSim

Crosstalk Analysis - BoardSim Crosstalk Option

If you suspect that your PCB’s traces may crosstalk with each other (because, for example, your
routing density is very high or your driver ICs switch quickly), BoardSim’s crosstalk option can
show you whether the problem is likely to be serious or not, and help you find ways to reduce
crosstalk if it does occur. In particular, you can perform any mix of the following kinds of
crosstalk simulation:

• Interactive: choose a "victim" net; BoardSim automatically finds likely aggressor nets;
simulate to see exactly how much crosstalk will occur on the victim in your real system
• Quick batch-mode: run a fast analysis on your entire PCB to estimate the maximum
amount of crosstalk that could occur on each net; the results, summarized in a report file,
serve as a guide to which nets you should examine in more detail
• Detailed batch-mode: run detailed analysis on selected nets in a batch fashion (all nets,
if you want, although choosing a critical subset is smarter); BoardSim automatically sets
the driver IC on each victim net as "stuck high" and "stuck low" and permutes through

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Overview of LineSim and BoardSim Crosstalk

min/typ/max settings for the drivers on aggressor nets; crosstalk-amplitude and timing
results are written to a report file
For more details on how HyperLynx recommends mixing and using the features, see
“Recommended Way to Use BoardSim Crosstalk Features” on page 1198.

Crosstalk Analysis Not Available for Manhattan Routing

Manhattan routing has insufficient physical information for crosstalk analysis. For example,
Manhattan routing connects pins by a simple daisy chain and the Manhattan routing path
between pins is undefined. By contrast, crosstalk analysis requires trace-to-trace proximity
information that can be derived only from full routing information.

Restriction: Signal integrity and EMC analysis can be performed on nets with Manhattan
routing.

Differential-Signal Analysis
When the base BoardSim product analyzes differential signals, it models each trace in the pair
separately, without accounting for the coupling between the traces. This is adequate for loosely
coupled pairs, but not if the traces are tightly coupled.

BoardSim Crosstalk adds the ability to automatically account in detail for the coupling between
traces in a pair. This not only increases simulation accuracy, but also allows you to view directly
the differential- and common-mode impedances of the pair. And it enables the Terminator
Wizard to automatically calculate the resistor values needed to optimally terminate the pair.

Effects of Nearby Traces for Signal-Integrity Simulations

As PCBs become increasingly dense, there is a greater possibility that the behavior of individual
traces is affected by the presence of other, nearby traces. For example, you may calculate
exactly how to achieve 50-ohm trace impedances on your PCB (for example, by controlling
dielectric thicknesses and trace widths), but then discover after fabrication that the proximity of
nearby traces reduces your nominal impedance to 47 ohms.

When you simulate with the base BoardSim product, the trace you select for analysis (and nets
electrically connected to it, i.e., associated nets) are simulated ignoring the effects of other
nearby traces. Depending on your PCB’s density, this may be perfectly sufficient. However, in
some situations on dense PCBs, you may want to include the effects — e.g., impedance changes
— due to neighboring traces.

BoardSim Crosstalk optionally allows these "proximity effects" to be included. It does so in the
following ways:

1. In interactive simulation, by allowing you to enable crosstalk simulation so that nearby

coupled nets are included in simulations; you can set the driver ICs on these nets into a

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Overview of LineSim and BoardSim Crosstalk

static, "stuck-high" or "stuck-low" state, while the driver IC on the selected net switches
high or low
2. In batch simulation, by enabling a "high-accuracy" mode that automatically enables
coupling and includes nearby, coupled nets in simulations; the driver ICs on these
neighboring nets are automatically stuck low

Performance Trade-Off in Including Other Traces

There is a performance trade-off involved in including the effects of neighboring traces in
simulations: the simulations run slower. Therefore if you don’t believe that these effects are
likely to be significant (e.g., you don’t care for a particular board about the last few ohms of
impedance accuracy), you should avoid including other, coupled traces in your simulations.

To find out whether neighboring traces are affecting simulation results on a given board, you
can compare a few representative interactive simulations with coupling turned on and then off,
or view the coupled impedances directly in LineSim or BoardSim.

Recommended Way to Use BoardSim Crosstalk Features

This section provides some guidance about how to use BoardSim Crosstalk.

This topic contains the following:

• “For Crosstalk Analysis” on page 1198

• “For Differential-Pair Analysis” on page 1199

For Crosstalk Analysis

You can use any mix of BoardSim Crosstalk’s interactive and batch simulation features, to suit
the needs of your particular designs.

See also: “Crosstalk Analysis - BoardSim Crosstalk Option” on page 1196

However, since simulating crosstalk is probably the most-complex of all types of signal-
integrity analysis, your goal should always be maximum efficiency: focusing on the likely
"problem" nets and getting results as quickly as possible. Therefore, we recommend the
following approaches to analyzing a PCB’s crosstalk:

• If you do not know which nets are likely to exhibit crosstalk, you can use quick
analysis in batch simulation to quickly create a report containing a list of nets sorted by
the estimated maximum amount of crosstalk. Then, depending on the number of
problem nets found, use the report as a guide to either interactive or detailed batch
simulation.

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Running the Field Solver in LineSim

To report the estimated crosstalk for each net, select the Show crosstalk strength estimates
check box on the Options batch simulation wizard page.

See also: “Selecting Simulation Options”

• If you know which nets are likely to exhibit crosstalk, and the number of such nets
is limited, use interactive simulation.
• If you know which nets are likely to exhibit crosstalk, but the number of such nets
is large, use detailed batch-mode simulation.
To find out which nets are the most susceptible to crosstalk, use quick analysis in batch
simulation to create a report containing a list of nets sorted by the estimated maximum amount
of crosstalk. To report the estimated crosstalk for each net, select the Show crosstalk strength
estimates check box on the Options batch simulation wizard page.

See also: “Selecting Simulation Options”, “Getting to Know Batch Simulation”

For Differential-Pair Analysis

If you are using BoardSim Crosstalk’s coupling-analysis features mostly to simulate differential
pairs, then you will probably make use mostly of interactive simulation. (BoardSim’s batch-
mode analysis features are oriented more strongly at crosstalk.) You may also want to use the
Coupling-Region Viewer, because it allows you to check the differential impedances (and other
electrical characteristics) of your trace pairs.

Running the Field Solver in LineSim

This topic contains the following:

• “Quick Summary of How to View Field-Solver Results” on page 1199

• “About the Field Solver in LineSim” on page 1200
• “How the Field Solver Works in LineSim” on page 1201
• “How the Field Solver Runs in LineSim” on page 1202
• “Viewing Detailed Field-Solver Results” on page 1206
See also: “Viewing Resistance and Attenuation Over a Frequency Range” on page 392

Quick Summary of How to View Field-Solver Results

To run the LineSim field solver, for any coupling region already defined:

1. Do one of the following over any transmission line belonging to the coupling region
whose field properties you want to see:

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Running the Field Solver in LineSim

• If you are using the free-form schematic editor, double-click.

• If you are using the cell-based schematic editor, right-click.
2. Click the Field Solver tab.
3. To see field lines, in the Field Plotting area, click Start.
Or
To see numerical data (e.g., impedance matrix), in the Numerical Results area, click
View.

About the Field Solver in LineSim

A field solver is a program that can solve for the electrical characteristics of a system of
conductors and dielectrics, using one or more of the basic equations of electromagnetic theory
("Maxwell’s equations"). Specifically, LineSim uses its field solver to solve for the
capacitances, inductances, propagation velocities, and characteristic impedances of a coupling
region’s cross section.

See also: “Coupling Regions and Coupling Dots”, “Adding Coupling to LineSim Schematics”

Because coupling regions consist of two-dimensional cross sections that are assumed to be
constant over some specified length, LineSim’s field solver needs to work in only two
dimensions. Taking advantage of this fact allows LineSim to calculate coupling parameters
accurately, but also very quickly—in fact, interactively, as you work.

Tip: Three-dimensional electromagnetic solutions become important only if the

frequencies of the signals traveling on a system of conductors is so high that the
wavelengths of the signals’ components are shorter than the various conductor structures
in the system (e.g. vias, corner bends, etc.). This condition rarely occurs on PCBs
carrying digital signals, so tools that analyze digital PCBs use two- rather than three-
dimensional solvers. The big gain for users is speed: solvers run much faster in two
dimensions than in three.

When more than one transmission line is present in a coupling region, the various electrical
parameters of the system take on a matrix form. For example, for a two-trace coupling region,
there is no longer a single value of capacitance that describes the region’s cross section. Rather,
there exists a 2x2 matrix which specifies both the capacitances of the individual traces to
ground, and the capacitance between the traces.

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Running the Field Solver in LineSim

Tip: The matrix nature of the electrical parameters describing a multi-trace coupling
region is unfamiliar to many engineers and designers. For some detailed background
information on coupled transmission lines and how they are described in matrix form, see
“Electrical Parameters of Coupled Transmission Lines” on page 1357. This portion of the
Help system discusses matrix parameters as needed, but concentrates mainly on how to
use LineSim’s field solver, rather than the theory underlying it.

It is worth noting that there is no need to understand any of the electromagnetic details in order
to successfully use LineSim’s crosstalk-analysis features. You can enter all of your problems
geometrically, let LineSim’s field solver take care of the electrical details automatically, and get
results in the form of waveforms and report files. Even a parameter like differential impedance
is calculated automatically to prevent you from having to know how to calculate it from a
characteristic-impedance matrix.

How the Field Solver Works in LineSim

This information is provided only for readers who are curious about what techniques LineSim
Crosstalk’s field solver uses to perform calculations. This material is not needed to successfully
use LineSim’s crosstalk-analysis features, and can readily be skipped.

In order to completely determine the electromagnetic properties of a coupling region’s cross

section, LineSim Crosstalk’s field solver must calculate the capacitance and inductance
matrices for the cross section. These matrices give the conductor-to-ground and conductor-to-
conductor capacitances and the self and mutual inductances of the traces in the coupling region.

To calculate capacitance values, LineSim Crosstalk’s field solver finds the solution to Laplace’s
equation, a form of one of Maxwell’s basic equations of electromagnetics:

In the solution, the solver seeks to find charge densities on the conductor surfaces and dielectric
boundaries, rather than bothering to calculate the electric potential at all points between the
conductors. This approach makes LineSim’s field solver a "boundary-element" solver.
Several proprietary methods are used to speed calculations significantly while maintaining a
high level of accuracy.

The solution to Laplace’s equation occurs subject to all of the boundary conditions specified in
the coupling region’s cross section, i.e., it takes into account the exact shapes and locations of
the conductors in the region and the locations and material properties of the dielectric
boundaries. Special care is taken to calculate charge density accurately in regions in which it
changes rapidly (e.g., at the corners of conductors).

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Running the Field Solver in LineSim

Once the coupling region’s capacitance values are found, then to calculate the inductance
matrix, the field solver takes advantage of the following equation from transmission-line theory:

This allows a second solution to Laplace’s equation — one in which all of the dielectrics are
replaced by vacuum and the capacitance matrix C0 is found — to substitute for an explicit
calculation of the coupling region’s magnetic properties.

Once the capacitance and inductance matrices are both known, then the region’s propagation
speed(s) and characteristic impedances can be calculated. For the case of inhomogeneous
dielectrics (i.e., a mixture of dielectric constants, as occurs with microstrip and buried-
microstrip traces), multiple propagation speeds exist. These speeds are found from the
eigenvalues of the matrix product LC.

How the Field Solver Runs in LineSim

In LineSim, the field solver’s job is to calculate the following information for every coupling
region:

• Capacitance matrix
• Inductance matrix
• Characteristic impedance matrix
• Propagation speed(s)
• If multiple propagation speeds, the percentage of energy in each trace traveling at each
speed
• An optimal resistor termination array for the region’s transmission lines
For background information on why many of these quantities are described in matrices, and
what is meant by "multiple propagation speeds" and "optimal resistor termination array," see
“Electrical Parameters of Coupled Transmission Lines” on page 1357.

Note that this information is calculated from the purely geometric and material data you
provided in specifying each coupling region’s properties. For details on creating and specifying
coupling regions, see Adding Coupling to LineSim Schematics. Therefore, the field solver can
be thought of as a calculation engine that transforms geometric/material data into corresponding
electromagnetic data.

This topic contains the following:

• “How the Field Solver Results are Displayed” on page 1203

• “Auto-Calculate Versus As-Needed Modes” on page 1205

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Running the Field Solver in LineSim

How the Field Solver Results are Displayed

In LineSim, uncoupled transmission-line impedance and delay values are displayed explicitly in
the schematic editor, inside each transmission line’s symbol. They are also shown in the Edit
Transmission Line dialog box, in the Values tab.

With coupled transmission lines, LineSim attempts to display electrical information in much the
same way as with uncoupled. This is not entirely possible, because the information associated
with a collection of coupled lines is more complex than the single-value parameters associated
with uncoupled lines. For coupled lines, some information is displayed in the schematic editor;
some is shown in the Edit Coupling Regions dialog box; and full details are available from the
Field Solver dialog box.

See also: “Viewing Detailed Field-Solver Results” on page 1206

Field-Solver Results in the Schematic Editor

For coupled transmission lines, there is no single value that describes each line’s characteristic
impedance. Similarly, if the lines are microstrips or buried microstrips (rather than striplines),
so that the electromagnetic fields they generate lie in a mixture of dielectrics (e.g., FR-4 and
air), then multiple propagation velocities exist per line and there is no single line-delay value.

However, for coupled lines, LineSim Crosstalk does display a single value for impedance and
delay in each transmission-line symbol. The values shown are as follows:
Table 29-1. Display of Impedance and Delay in Transmission-Line Symbols
Parameter What is Displayed in a Transmission-Line
Symbol in the Schematic Editor
characteristic impedance line’s diagonal value from the characteristic-
impedance matrix
delay if line is a stripline (i.e., single dielectric):
the single delay value

if line is not a stripline (i.e., multiple

dielectrics):
weighted average of line’s multiple delays;
weighting based on percentage of energy
traveling at each speed

Schematic Impedance
You can think of each transmission line’s diagonal impedance as the impedance of the line to
ground, accounting for the presence of the nearby, coupled lines. If the lines in the region are
only weakly coupled, the diagonal value is close to what you would calculate for the line in
isolation (i.e., ignoring the neighboring traces); as the lines become more strongly coupled, the
diagonal impedance deviates more from the isolated value.

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Although it is not possible to completely terminate a coupled transmission line with a single
resistor (see “Terminating Coupled Transmission Lines” on page 1370 for details), if you are
forced to use only one resistor and the signal on the line is not either purely differential or
common-mode, then the diagonal impedance value is usually the best terminating value to use.

Schematic Delay
For coupled striplines, whose electromagnetic fields exist entirely in dielectric of one type, there
is only one signal propagation velocity and therefore a single delay value, which the schematic
editor displays.

However, for coupled microstrips or buried microstrips, whose fields penetrate both PCB
dielectric and air, there are multiple propagation velocities (specifically, as many velocities as
there are traces in the coupling region). In this case, in order to display a single delay value in
the schematic editor, LineSim Crosstalk averages each line’s multiple delays together. The
calculation is a weighted average, with the weighting based on the percentage of signal energy
that exists at each velocity. If only a small amount of energy travels at a given speed, then that
speed’s contribution to the average is small. The final result is displayed in the schematic editor.

Usually, unless a coupling region’s geometry is very asymmetric, the difference between
propagation velocities is small. (An example of an "asymmetric" geometry would be a
microstrip of one width coupled to a buried microstrip of a different width, with the buried trace
below and considerably off to the side of the outer-layer trace.) Therefore, the averaging effect
described above is usually not major.

For more details on multiple propagation velocities and why they occur, see “Differential and
Common Modes” on page 1366.

Field-Solver Results in the Edit Coupling Regions Dialog Box

Some field-solver results are displayed directly in the Edit Coupling Regions dialog box, so you
can monitor the effects of coupling-region geometry changes as you make them. Specifically, in
the dialog box’s Impedance area, the list shows impedance data for the current cross section.

By default, the field solver recalculates impedances every time you make a change in the dialog
box. You can optionally run with "auto-calculate" mode turned off, however; see “Auto-
Calculate Versus As-Needed Modes” on page 1205 for details.

Exactly how impedances values are displayed varies depending on whether there are two or
more than two traces in the coupling region.

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Impedance Display Area in Field Solver

The list in the Impedance area always shows the following information:

Table 29-2. Contents of Impedance Display Area in Field Solver

Column Description
Transmission Line The name of the transmission line; includes
schematic-cell coordinates plus any "comment"
you enter for the line.
Impedance An impedance value, in ohms; if multiple lines in
the coupling region, taken from the diagonal
values in the impedance matrix.
Notes A description of what the impedance is.

For details on getting more-complete impedance information (e.g., the full impedance matrix),
see “Viewing Detailed Field-Solver Results” on page 1206.

Extra Impedance Information - Differential Z - When Only Two Traces

When there are only two traces in a coupling region, LineSim Crosstalk assumes that you may
be interested in the differential impedance between the traces. (For details on what is meant by
differential impedance, see “Differential and Common-Mode Impedance” on page 1368.)
Therefore, with two traces, the Impedance-area list shows, in addition to the "diagonal
impedances" described above, the two-trace differential impedance. This value is labeled
"differential" in the Transmission Line column.

The differential impedance is the correct terminating value to use, line-to-line, only if the two
traces in the coupling region carry only differential signals.

Auto-Calculate Versus As-Needed Modes

LineSim Crosstalk’s field solver is designed to run fast enough that it is interactive, i.e., it can
afford to be run whenever its results are needed.

Auto-Calculate Mode
If you are working on small coupling regions (i.e., regions with a small number of transmission
lines) and if your computer is fast, you may want the field solver to run any time any change is
made to a coupling region, even while you’re in the middle of working in the Edit Coupling
Regions dialog box. In this "auto-calculate" mode, to which LineSim Crosstalk defaults, the
field solver runs each time you change a cross-section value anywhere in the dialog box.

To place the field-solver in auto-calculate mode (if previously disabled):

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• In the Edit Coupling Regions dialog box, in the Impedance area, select the Auto Calc
check box. The field solver runs and new results are placed in the Impedance list.
If you are working on a large coupling region (i.e., one with many transmission lines) or if the
field solver is taking several or more seconds to run each time it is invoked, then it is best to
leave auto-calculate mode off.

As-Needed Mode
Optionally, the field solver can be set up to run whenever a coupling region’s geometry or
material data are changed, but not while you are working in the Edit Coupling Regions dialog
box, in the middle of making changes. For details on opening the Edit Coupling Regions dialog
box and changing coupling-region properties, see “Edit Transmission Line Dialog Box - Edit
Coupling Regions Tab” on page 1562”. In this mode, the solver runs only when you close the
dialog box or click the Transmission-Line Type tab.

Disabling Auto-Calculate Mode

To disable auto-calculate mode:

• In the Edit Coupling Regions dialog box, in the Impedance area, clear the Auto Calc
check box. The field solver runs and new results are placed in the Impedance list.
If you want see the field solver’s output data before you are ready to close the Edit Coupling
Regions dialog box, you can force the solver to run. Running it will refresh the data displayed in
the Impedance list and also allow you to switch to the Field Solver tab and immediately click
the Numerical Results View button.

Manually Forcing the Field Solver to Run

To manually force the field solver to run, without closing the Edit Coupling Regions dialog box
(only if auto-calculate mode is disabled):

• In the Edit Coupling Regions dialog box, in the Impedance area, click Calculate. The
field solver runs and new results are placed in the Impedance list.

Viewing Detailed Field-Solver Results

The preceding pages describe how to get summary results from the field solver, i.e., impedances
and delays in the schematic editor and impedances in the Edit Coupling Regions dialog box.
However, for every coupling region, the field solver has considerably more than this summary
information available. Table 29-3 describes the additional information.

Table 29-3. Detailed Field-Solver Results

Information Description

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Table 29-3. Detailed Field-Solver Results (cont.)

capacitance matrix gives the self and mutual capacitances of the traces
in the coupling region
inductance matrix gives the self and mutual inductances of the traces
characteristic-impedance matrix full matrix impedance for the system of coupled
transmission lines; off-diagonal values are small
for weak coupling and large for strong
optimal terminator-resistor array an array of resistors (line-to-ground and line-to-
line) that perfectly terminates the system of
coupled lines; in theory, this array can completely
eliminate crosstalk amongst the lines
list of propagation speeds gives the velocities at which signals propagate on
the traces; there multiple values if the traces’
electromagnetic fields "see" more than one type of
dielectric (e.g., microstrip or buried microstrip)
table of energy percentages in each gives the amount of each trace’s energy that
propagation mode travels at each propagation velocity; for multi-
speed coupling regions only
recommended termination values list of impedance values, including the differential,
common-mode, and line-to-ground values; for
two-trace coupling regions only
graphical field lines a picture showing the coupling region’s electric
field lines and electric equipotentials

Related Topics
“How the Field Solver Results are Displayed” on page 1203

Viewing Electrical Field Lines

When a signal travels along a conductor, it transfers energy in the form of a wave that consists
of time-changing electric and magnetic fields. The field solver predicts these fields, given a
specific cross section containing conductive traces and various dielectrics.

Sometimes it is informative to actually view the field lines calculated by the field solver.
Though the field plots provide no direct analytic value, they can give an intuitive feeling for
how various traces are coupled to each other. Sometimes, too, they are just fun to look at.

Requirement: The LineSim/BoardSim Crosstalk license is required to run crosstalk simulation.

This topic contains the following:

• “Viewing Electrical Field Lines in LineSim for Coupling Regions” on page 1208

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• “Viewing Electrical Field Lines in BoardSim for Trace Segments” on page 1208

Viewing Electrical Field Lines in LineSim for Coupling Regions

To view the electrical field lines for a coupling region:

1. If needed, open the Edit Transmission Line dialog box by doing one of the following
over a transmission line that is in the coupling region whose field lines you want to see:
• If you are using the free-form schematic editor, double-click.
• If you are using the cell-based schematic editor, right-click.
2. Click the Field Solver tab. A large graphical view of the coupling region appears, see
“Field Solver and Edit Transmission Line Dialog Box - Field Solver Tab” on page 1636.
3. In the Propagation Mode list, do one of the following:
• Leave the mode at the default setting and go to step 4.
• Select the propagation mode for which you want to see field lines.
Restriction: The list is unavailable when the selected transmission line is not coupled to
another transmission line.
4. Do one of the following:
• If you changed the propagation mode in step 3, plotting starts automatically.
• If you didn’t change the mode, click Start. LineSim Crosstalk begins calculating
and displaying electric field lines and electric equipotentials.
See also: “How Field Lines are Plotted” on page 1209
5. To view numerical results from the field solver, click View.
See also: “Generating a Report of the Field Solver’s Numerical Results” on page 1212

Related Topics
“Field Solver and Edit Transmission Line Dialog Box - Field Solver Tab” on page 1636

Viewing Electrical Field Lines in BoardSim for Trace Segments

To view the electrical field lines for a trace segment:

1. In BoardSim, right-click over the trace segment and click View Field-Solver Output,
see “Field Solver and Edit Transmission Line Dialog Box - Field Solver Tab” on
page 1636.
2. If the trace segment is coupled to another trace segment, the Propagation Mode list
becomes available. You can do any of the following:

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• Leave the mode at the default setting and go to step 3.

• From the Propagation Mode list, select the propagation mode for which you want to
see field lines.
3. Do one of the following:
• If you changed the propagation mode in step 2, plotting starts automatically.
• If you didn’t change the mode, click Start. LineSim Crosstalk begins calculating
and displaying electric field lines and electric equipotentials.
See also: “How Field Lines are Plotted” on page 1209
4. To view numerical results from the field solver, click View.
See also: “Generating a Report of the Field Solver’s Numerical Results” on page 1212

Related Topics
“Field Solver and Edit Transmission Line Dialog Box - Field Solver Tab” on page 1636

How Field Lines are Plotted

In the graphical viewer, electric field lines are plotted in blue. These can be thought of as the
electric field’s "lines of force." Note that they begin and end on conductor surfaces (where
physical charges reside). They refract (i.e., change direction) at boundaries between different
dielectrics. See Figure 29-3.

Electric equipotentials are plotted in red. These are curves along which the electric potential
(i.e., voltage) is a constant. They form closed contours around one or more conductors, and
refract at dissimilar-dielectric boundaries. Again, see Figure 29-3.

Figure 29-3. Example of a Field-Line Plot

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The field lines are not plotted instantly, because LineSim Crosstalk calculates their positions
on-the-fly, when you click the Start button (or change propagation mode). The plotting is fairly
quick on most computers, but you can interrupt it before completion if you want.

Choosing a Propagation Mode to Plot

Conceptually, the term "propagation mode" refers to a manner in which signals are arranged on
a system of traces in order to propagate the signals. A "basis set" of propagation modes is a
collection of modes that could be used in some mixture to create any arbitrary set of real signals
on the traces.

Tip: The simulator automatically defines the propagation modes. You only need to think
about propagation modes when plotting field lines or looking at signal propagation
speeds.

For example, in the case of two traces coupled together, designers often think in terms of a set of
modes consists of "differential mode" and "common mode." The differential propagation mode
is one in which if one trace carries the voltage +V, the other trace carries -V (i.e., the two traces
always carry opposite voltages). For the common mode, if one trace carries +V, the other also
carries +V.

Note that it is conceptually possible to describe any pair of real signals traveling on the two
traces as some mixture of these two modes. For example, a mostly differential signal that had a
small common-mode component to it could be constructed by mixing 80% differential mode
with 20% common mode.

Note, too, that it is possible to conceive of other equally valid propagation-mode sets for the two
traces. Another possibility, for example, is a set in which mode 1 consists of signal V on trace 1
and no signal on trace 2; and mode 2 consists of no signal on trace 1 and signal V on trace 2.
This is a basis set just as valid as the set consisting of differential + common modes—i.e., you
can conceptually use either set to construct any real set of signals on the traces.

Tip: It should be emphasized that the construction of a propagation-mode set is arbitrary

and has nothing to do with the validity of the electromagnetic solutions generated by the
field solver or the waveforms generated by LineSim Crosstalk’s simulator. For stripline
configurations, any basis set is equally valid, and LineSim Crosstalk really only has to
choose one so that it can display field lines in some reasonable manner. Thus, it makes
sense to choose a set of modes that is conceptually simple.

Propagation Modes for Striplines - One Dielectric Only

For coupling regions that have only one propagation velocity, i.e., where all of the traces are
striplines (whose fields exist only in one type of dielectric), LineSim Crosstalk constructs the

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conceptually simplest possible set of propagation modes: one in which mode 1 means trace 1
has a signal V and all other traces have no signal; mode 2 means trace 2 has a signal V and all
other traces have no signal; and so forth.

Thus, when you choose mode 1 from the Propagation Mode combo box and click the Start
button, you will see lines emanating from and surrounding trace 1. Mode 2 produces lines
around trace 2—and so forth.

Propagation Modes for Microstrips and Buried Microstrips -

Multiple Dielectrics
However, for coupling regions that have multiple propagation velocities, i.e., where the traces
are microstrips or buried microstrips (whose fields penetrate multiple dielectrics), the concept
of propagation modes takes on added physical significance. In this case, it is possible to
construct a set of modes such that each mode represents the amount of signal on each trace that
travels at one of the propagation speeds. The number of speeds (and therefore modes) equals the
number of traces.

See also: “Multi-Speed Propagation” on page 1362

For example, for the coupling region shown in “How Field Lines are Plotted” on page 1209,
there are three modes, one propagating energy with a speed of 51.6% of the speed of light;
another propagating at 50.8% of light speed; and a third propagating at 49.1% of light speed. In
general for the multi-speed case, each mode involves some amount of signal on each trace.
Therefore, when you plot one of the modes (unlike with the single-velocity case; see
"Propagation Modes for Striplines" above), you see lines emanating from and surrounding all of
the traces. “How Field Lines are Plotted” on page 1209 shows the plot for this coupling region’s
propagation mode 1.

Following the theme of the previous sections’ discussion, you could define other mode sets for
Figure 29-3’s coupling region. Suppose, for example, that you defined mode 1 as [+V,0,0],
mode 2 as [0,+V,0] and mode 3 [0,0,+V]. This is conceptually simple at first glance, but now
each mode involves a mixture of three different propagating speeds. So the more physically
significant mode set for these traces is the one in which each mode propagates signals at one
"pure" speed.

For two-trace microstrip and buried-microstrip configurations in which the traces are
symmetrically arranged (i.e., each trace is on the same layer, has the same width and thickness,
etc.), it turns out that the mode set that describes the two propagation speed and the
differential/common mode set coincide, i.e., they’re the same. Thus, for symmetric trace
arrangements, driving purely differential signals means that only one mode is excited, and only
one propagation speed results.

See also: “Differential and Common Modes” on page 1366

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Generating a Report of the Field Solver’s Numerical

Results
Much of the field solver’s output data comes in the form of matrices or lists of numerical
parameters (e.g., impedance, propagation speed, etc.). All of this data can be viewed in a report
file, which in turn can be printed or saved for future reference.

To create a text report of the field solver’s numerical results:

1. If you are using LineSim, open the Edit Transmission Line dialog box by doing one of
the following over a transmission line that is in the coupling region whose field lines you
want to see:
• If you are using the free-form schematic editor, double-click.
• If you are using the cell-based schematic editor, right-click.
Or
If you are using BoardSim, right-click over a trace segment whose field lines you want
to see, and then click View Field-Solver Output.
2. If needed, click the Field Solver tab. A large graphical view of the coupling region
appears.
3. In the Numerical Results area, click View.
4. If the View button is unavailable (because the coupling region has changed and the field
solver has not yet been run), click Start and then click View.
A report file is created, and the HyperLynx File Editor opens on it. You can scroll up and down
in the editor to see the report’s data, and print it if desired. By default, the report is written into a
file named <Coupling_Region_Name>.TXT, where <Coupling_Region_Name> is the name of
the coupling region for which the data are being reported. The file is located in the same
directory as your .TLN or .FFS schematic file.

Preserving Numerical Results Files

If you typically leave your coupling regions with default names (e.g., "Coupling0001,"
"Coupling0002," etc.), your numerical-results files will likely be overwritten frequently.
Therefore, if you want to preserve field-solver data, save the results file under a unique name by
renaming the coupling region. For details on editing coupling region names, see“Edit
Transmission Line Dialog Box - Edit Coupling Regions Tab” on page 1562.

Contents of the Results Report

Table 29-3 gives an overview of the data contained in the field-solver numerical results file.
The following topics provide more details:

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• “Physical Input Data” on page 1213

Field-Solver Output Data:

• “Optimal Resistor-Terminator Array” on page 1214

• “Characteristic-Impedance Matrix” on page 1215
• “Capacitance Matrix” on page 1216
• “Inductance Matrix” on page 1216
• “Propagation-Speeds List in LineSim” on page 1217
• “Percentage of Energy Matrix for Multiple-Speed Coupling Regions Only” on
page 1218
Also:

• “Impedance and Termination Summary for Two-Line Coupling Regions Only” on

page 1250

Physical Input Data

This section of the report file shows for what geometric and material data the field-solver results
were calculated. The data serves as a record of the input problem, for future reference. Also, for
certain coupling regions whose characteristics are important in a key design decision, it may
also be worth looking at the input data to verify that the problem on which the field solver ran
was exactly as expected. The input data includes information on each trace in the coupling
region as well as the region’s PCB stackup.

Correlating Transmission Lines and Matrix Indices

In the input data, the Field Solver Traces section lists by name each transmission line in the
coupling region, and shows the corresponding trace index by which the line is referred to in the
electrical matrix data elsewhere in the file. This data allows you to correlate transmission lines
and trace indices. See Figure 29-4.

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Figure 29-4. Example of Table Correlating Transmission Lines and Trace

Indices

Field Solver Output Data

This section of the report file shows the electrical data calculated by the field solver for the
coupling region. As described earlier, much of this data are in matrix form, because the
transmission lines in the region are coupled together. For background information on how
electrical parameters are expressed for systems of coupled lines, see “Electrical Parameters of
Coupled Transmission Lines” on page 1357.

Refer to topics in the table of contents for details on the field solver’s electrical data.

Optimal Resistor-Terminator Array

Many times, users of LineSim Crosstalk’s crosstalk-analysis features are interested in how to
terminate traces that are coupled to other traces. This matrix gives the theoretically optimal
resistor termination array for the set of coupled lines in the coupling region.

A key fact about coupled lines is that they cannot be perfectly terminated individually. Instead,
a matrix of resistors that prescribes both line-to-ground and line-to-line resistances is required.
(For background information, see “Terminating Coupled Transmission Lines” on page 1370.)
This termination array has the remarkable property that it not only "kills" single-line reflections
at the line ends, but also eliminates arriving crosstalk signals.

On the other hand, there are many situations in digital electronics where line-to-line resistors (in
addition to adding undesirably to passive-component count) are simply not permissible for DC-
bias reasons. For example, whereas two coupled data lines may require a 160-ohm resistor
between them to eliminate line-to-line crosstalk, it is unlikely that the driver ICs on the lines
would be "happy" with the resistor when one line was pulled high and the other low.

Still, in some critical situations, especially when the line-to-line coupling is relatively weak and
therefore the line-to-line terminating resistances are fairly high, a matrix terminator may be
workable.

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There are some IC technologies which are specifically designed to work with line-to-line
termination: differential drivers. For these devices, line-to-line termination serves not only to
prevent line reflections and eliminate crosstalk, but is often also required to bias the ICs for
correct operation.

Implementing Optimal Termination

To implement the termination described in the Optimal Terminator-Resistor Array matrix:

1. Place the resistors in the diagonal matrix positions between the corresponding trace to
ground.
Example: Resistor 2-2 should be placed from trace 2 to ground, at the trace end.
2. Place the resistors in the off-diagonal matrix positions line-to-line between the
corresponding traces.
Example: Resistor 2-1 should be placed between traces 1 and 2, at the trace ends.
Note that there are twice as many off-diagonal values as there are line-to-line resistors, since,
for example, off-diagonal resistance 2-1 refers to the same resistor as resistance 1-2.

To correlate a specific transmission line in a coupling region to a matrix index, see the
Fieldsolver Traces section of the Physical Input Data section of the field-solver report, as
illustrated in Figure 29-4. For more information, see the following topics.

Characteristic-Impedance Matrix
This matrix gives the characteristic impedance (in ohms) of the system of coupled transmission
lines in the coupling region. As noted previously (and described in more detail in “Terminating
Coupled Transmission Lines” on page 1370), coupled lines do not have a single-value
impedance, like uncoupled lines. Rather, together, a set of coupled lines share an impedance
matrix.

The values in the diagonal matrix positions can be thought of as giving the impedances to
ground of the corresponding transmission lines, accounting for the presence of the other nearby,
coupled traces. When an IC drives into one of the lines, however, it "sees" not only the diagonal
impedance for that line, but also some of the off-diagonal terms in the matrix.

For lines that are only weakly coupled, the diagonal impedance terms are dominant, and the
diagonal values are close to what they would be if the lines were completely isolated from each
other. As the coupling becomes stronger, the diagonal terms deviate more from their standalone
values, and the off-diagonal terms increase. Note that small off-diagonal impedances mean
weak coupling; large impedances mean strong coupling.

Barring special cases like two-line pairs in which the two signals are known to be either purely
differential or purely common-mode, the diagonal impedances in the matrix are generally the
best single-resistor terminators to use. Note, however, that coupled transmission lines cannot be

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perfectly terminated unless a full matrix termination (including both line-to-ground and line-to-
line resistors) is employed. See “Optimal Resistor-Terminator Array” on page 1214 for details.

To correlate a specific transmission line in a coupling region to a matrix index, see the
Fieldsolver Traces section of the Physical Input Data section of the field-solver report, as
illustrated in Figure 29-4.

Capacitance Matrix
This matrix gives the self and mutual capacitances (in pF/m) of the coupled transmission lines
in the coupling region. More specifically, the diagonal values in the matrix give the
capacitances to ground of the corresponding transmission lines, while the off-diagonal values
give the capacitances between the corresponding pair of lines.

Many users are surprised to see that the off-diagonal capacitance-matrix values are negative.
The negative sign simply reflects the fact that if a positive charge is placed on a given trace,
negative charge will accumulate on all others.

For purposes of judging how much capacitance exists between traces, you can ignore the
negative signs. The off-diagonal values do represent real, physical capacitance.

However, in the mathematical formalism of coupled transmission lines, the negative signs are
important. For example, if you transfer the capacitance matrix for a coupling region to another
EDA tool (e.g., SPICE), the off-diagonal values must be negative.

Note that the values in the capacitance matrix have units of pF/m, rather than simply pF. This
means that if you are trying to calculate, for example, the total capacitance-to-ground of a
transmission line in the matrix, you must multiply the corresponding diagonal value in the
matrix by the length (in meters) of the line.

To correlate a specific transmission line in a coupling region to a matrix index, see the
Fieldsolver Traces section of the Physical Input Data section of the field-solver report, as
illustrated in Figure 29-4.

Inductance Matrix
This matrix gives the self and mutual inductances (in nH/m) of the coupled transmission lines in
the coupling region. More specifically, the diagonal values in the matrix give the self
inductances of the corresponding transmission lines, while the off-diagonal values give the
mutual inductances of the corresponding pair of lines.

Note that the values in the inductance matrix have units of nH/m, rather than simply nH. This
means that if you are trying to calculate, for example, the total self inductance of a transmission
line in the matrix, you must multiply the corresponding diagonal value in the matrix by the
length (in meters) of the line.

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To correlate a specific transmission line in a coupling region to a matrix index, see the
Fieldsolver Traces section of the Physical Input Data section of the field-solver report, as
illustrated in Figure 29-4.

Propagation-Speeds List in LineSim

This list gives the speed(s) (in m/s) at which signals propagate along the transmission lines in
the coupling region. As noted previously (e.g., see “Choosing a Propagation Mode to Plot” on
page 1210) and described in more detail in “Propagation Modes-Single-Dielectric versus
Layered-Dielectric Traces” on page 1361, coupling regions in which there is only dielectric
(e.g., for stripline traces) have only one propagation speed; the signals on all traces in the region
propagate with this single velocity.

However, coupling regions in which there are boundaries between dissimilar dielectrics (e.g.,
for microstrip or buried-microstrip traces) have multiple, discrete propagation speeds.
Generally, each transmission line in the coupling region propagates some energy at each of the
velocities prescribed by the region. There are as many speeds as there are transmission lines in
the coupling region.

For most practical cross-section geometries, the multiple speeds are all close to each other.
However, it is possible to construct highly asymmetric cross sections in which the speeds are
quite different. (An example of a "highly asymmetric" geometry would be a microstrip of one
width coupled to a buried microstrip of a different width, with the buried trace below and
considerably off to the side of the outer-layer trace.) This is an undesirable condition, however,
because multiple, widely varying propagation speeds cause signal distortion, as one portion of
the signal races ahead of the other(s).

For convenience, the propagation-speeds list displays velocities not only in m/s, but also as a
fraction of the speed of light. For example, a value of "0.4822c" means 48.22% of the speed of
light.

Tip: A misconception about propagation velocity on a transmission line is that electrons

in the conductor are traveling along the line at the propagation velocity. This is absolutely
not true! Electrons in a conductor spend almost all of their time randomly colliding with
atoms in the conductor lattice; the mean time between collisions is on the order of 10
femtoseconds (1/100th of a ps).

As a result, conduction electrons have only a relatively tiny average forward velocity in the
presence of a driving voltage. A typical electron "drift velocity" in a conductor is on the order of
1 foot/hour. Instead, what moves at the transmission line’s propagation velocity is the
electromagnetic wave that constitutes the actual signal on the line. Indeed, this wave is what you
measure in the lab with an oscilloscope: a voltage waveform, which is really a measure of the
electric field associated with the traveling electromagnetic wave.

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Running the Field Solver in LineSim

Percentage of Energy Matrix for Multiple-Speed Coupling

Regions Only
If the coupling region supports multiple propagation speeds, this matrix gives, for each
transmission line in the region, the percentage of signal energy that travels at each speed. In the
matrix, each column represents a line (i.e., a trace); reading down the column shows how much
of the signal energy in that line travels in each of the propagation modes listed in the
propagation-speeds list. The percentages in each column add to approximately 100%, to fully
account for the energy in each transmission line.

The values in this matrix are usually only of limited interest, unless the matrix shows a very
uneven breakdown in energy sharing between propagation modes. For example, for certain
highly asymmetric (and unusual) geometries, it is possible to have certain transmission lines
carrying most of their energy in one mode, while others carry a more even mixture of modes. If
the velocities between modes differ significantly, this uneven distribution could lead to
noticeable skew between signals on the lines.

Impedance and Termination Summary for Two-Line Coupling

Regions Only
For the special case of a two-line coupling region, the field-solver numerical results report gives
additional information about specific termination options. Table 29-4 summarizes the additional
data.

Table 29-4. Impedance and Termination Summary (Two Transmission Lines

Coupling Regions Only)
Termination Type Description
differential This is the proper line-to-line resistor to use if the
two transmission lines are being driven
differentially, i.e., with equal-but-opposite signals.
Will not terminate common-mode signals at all.
common-mode This is the proper line-to-ground resistor to use for
each line if the two transmission lines are being
driven identically, i.e., with equal signals of the
same polarity. Not very useful for signals that
sometimes switch together and sometimes
oppositely, unless crosstalk is primarily of concern
when they switch together.
line-to-ground This is the best line-to-ground resistor to use for
each line if the signals on the transmission lines
are completely unrelated. Will not perfectly
terminate the line, but is a good single-component
"compromise" value.

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Table 29-4. Impedance and Termination Summary (Two Transmission Lines

Coupling Regions Only) (cont.)
optimal termination Describes the theoretically optimal resistor-array
termination; consists of a line-to-line resistor plus
two line-to-ground resistors. Same as the values
given in the Optimal Terminator-Resistor Array
matrix. Successfully terminates differential,
common-mode, or mixed signals, but may violate
DC-bias conditions on the lines.

Running Interactive Crosstalk Simulations in

BoardSim
This and the following topics describe how to run interactive crosstalk simulations in
BoardSim. Click on any of the following topics for complete details:

• “Enabling Interactive Post-Layout Crosstalk Simulations” on page 1219

• “How BoardSim Crosstalk Finds Aggressor Nets” on page 1220
• “How Aggressor Nets are Displayed” on page 1229
• “Setting IC Models for Crosstalk Simulations” on page 1230
• “Running Simulations” on page 1232
• “How to Maximize Simulation Performance” on page 1233
This and the following Help topics assume you that you are already familiar with how to operate
the base BoardSim product, and describes only the extra steps required to run crosstalk
simulations in the Board Wizard. If you need help with the features of base BoardSim, refer to
other portions of the Help system.

Enabling Interactive Post-Layout Crosstalk Simulations

Enabling interactive crosstalk simulation in BoardSim Crosstalk is easy: with one mouse click,
you can tell BoardSim Crosstalk to consider coupling between nets every time you simulate.

To enable interactive crosstalk simulation:

• Enable Crosstalk Simulation button .

Alternative: Setup menu > Enable Crosstalk Simulation.
Whenever crosstalk simulation is enabled, BoardSim Crosstalk will consider the coupling
effects between neighboring nets for all interactive simulations. Coupling analysis is enabled
differently for batch simulations.

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See also: “Running the Field Solver in BoardSim” on page 1235

The easiest way to remember whether coupled simulation is enabled or not is to look at the
Enable Crosstalk Simulation button on the toolbar. If it is toggled "in," coupling will be
included during all interactive simulations; if it is toggled "out," coupling is disabled and
BoardSim Crosstalk will ignore coupling (just like base BoardSim does for all simulations).

Switching Between Coupled and Uncoupled Simulations

It is often useful when running BoardSim Crosstalk interactively to switch back and forth
between coupled and uncoupled simulations. The are several reasons to do this:

• Performance: Coupled simulations often take much longer to run than uncoupled. For
nets for which you are not concerned about crosstalk or coupling effects, why bother
with the overhead of a coupled simulation?
• Comparison of coupled versus non-coupled simulations, to isolate the effects of
coupling: Sometimes when you are viewing a complex and noisy waveform for a net, it
is not easy to determine which effects are due to coupling and which are not. Repeating
the simulation with coupling disabled can help you isolate the noise due specifically to
coupling.

How BoardSim Crosstalk Finds Aggressor Nets

Suppose crosstalk simulation is enabled (see “Enabling Interactive Post-Layout Crosstalk
Simulations” on page 1219 for details), and you now select a net for analysis. BoardSim
Crosstalk automatically identifies other nets which are coupled to the selected net, include them
in simulation, and show them in the board viewer along with the selected net.

In a crosstalk simulation, the selected net is usually considered to be the "victim" net and the
other coupled nets "aggressor nets. “Aggressor Versus Victim Nets” on page 1221 describes the
difference between victims and aggressors.

This topic contains the following:

• “Aggressor Versus Victim Nets” on page 1221

• “Electrical Versus Geometric Identification of Aggressor Nets - Why Electrical is
Superior” on page 1222
• “How to Set the Crosstalk Threshold” on page 1223
• “How Aggressor Nets are Found” on page 1227
• “Aggressor Nets are Found on All Layers” on page 1228

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Aggressor Versus Victim Nets

In a crosstalk analysis, any PCB trace that is intentionally driven (usually by a switching IC
output buffer) and is therefore a potential source of crosstalk on other traces is called an
"aggressor." Any trace that potentially receives unwanted crosstalk from an aggressor is called a
"victim."

Note that victim traces are not undriven. Rather, the victim trace is usually in a static state,
"sitting high" or "sitting low" when a nearby aggressor trace is actively switched, and an
unwanted signal appears on the victim. See Figure 29-5. Because of reflection effects, the state
of the victim trace’s static driver is an important factor in the crosstalk waveforms that actually
appear on the victim trace. If you omit the "stuck" driver(s), simulated crosstalk waveforms will
look much different than if you include them. This occurs because driver ICs are typically low
impedance and will reflect, rather than absorb, crosstalk signals. In general, you should check
both the stuck-low and stuck-high cases whenever you simulate, to see which generates more
crosstalk.

Figure 29-5. Aggressor and Victim Trace

Of course, it is possible to have a collection of traces (e.g., on a microprocessor bus) all of

which are actively driven and all of which receive unwanted signal components from the other
traces. In this situation, the distinction between aggressor and victim becomes blurred — each
trace is both an aggressor and a victim. Usually for simulation purposes, though, you would
make the victim net static, so that the crosstalk appearing on it is not mixed with a driving signal
and single-line reflection effects.

Note that in differential signaling, if the differential pair is tightly coupled, then the two traces
crosstalk with each other just like any two other coupled traces. However, it is not typical to use
the terms "aggressor" or "victim" in a differential case, or even "crosstalk," because the
coupling is actually wanted. "Crosstalk" usually refers to unwanted coupling. When simulating
differential pairs, you would normally drive both traces (rather than considering one trace to be
a "victim" and sticking it high or low).

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Electrical Versus Geometric Identification of Aggressor Nets -

Why Electrical is Superior
Most crosstalk-analysis tools allow you to set a geometric "zone" around victim nets; any other
net which enters this zone for a sufficient length is considered to be an aggressor net and is
included in simulation. For example, you might be able to specify a zone 40 mils wide and with
a minimum length threshold of 250 mils, meaning that any net which comes within 40 mils (or
less) of the victim net and stays that close for at least 250 mils is automatically assumed to be an
aggressor net.

BoardSim Crosstalk supports geometric identification of aggressor nets, but also offers a better,
"smarter" method, called an "electrical crosstalk threshold." In this method (which the tool uses
by default), probable aggressor nets are identified electrically by how many mV of crosstalk
they might generate, regardless of where they are located.

Why are electrical thresholds superior to geometric? There are several reasons:

• Electrical thresholds are expressed electrically, the way an engineer thinks about
crosstalk. For example, if you are concerned about any aggressor net that might generate
more than 250 mV of crosstalk on a certain victim net, simply set the electrical threshold
to 250 mV. BoardSim Crosstalk will attempt to find all nets that might cause 250 mV (or
more) of crosstalk, and automatically include them in simulation.
• Geometric thresholds force you to have some knowledge (or to guess) about how much
crosstalk can be generated by traces on a certain stackup layer a certain distance away
from the victim trace. Suppose your noise budget allows for 300 mV of crosstalk on
victim nets. How does that translate into a geometric setting? Should you set the
threshold to 25 mils or 50 or 100 to account for 300 mV of crosstalk? BoardSim
Crosstalk’s electrical thresholds eliminate having to make complex electrical-to-
geometric conversions.
• Geometric crosstalk thresholds are valid for only one setting of a PCB’s other geometric
factors. For example, suppose you finally get the geometric threshold optimally set to
pick up 300-mV-or-greater aggressor nets, then decide to experiment with a different
dielectric thickness in your board’s stackup. How should you now change the crosstalk
threshold? Or what if you switch to faster driver ICs? BoardSim Crosstalk’s electrical
thresholds are independent of such changes: one value holds automatically for all
stackups, driver-IC switching rates, etc.
• Geometric thresholds can sometimes be deceivingly optimistic. Suppose you set the
threshold to 20 mils and perform your simulations assuming that your setting captures
all of the significant crosstalk that can occur — and then find out later that some nets 40
mils away could also be significant aggressors? BoardSim Crosstalk’s electrical
thresholds are designed to be pessimistic: if you set your threshold to 200 mV, the tool
attempts to bring in any net that could possibly generate that much crosstalk.

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Running Interactive Crosstalk Simulations in BoardSim

How to Set the Crosstalk Threshold

Whenever you enable interactive crosstalk simulation you should immediately check and set the
crosstalk threshold (see “Enabling Interactive Post-Layout Crosstalk Simulations” on
page 1219 for details). The threshold is used by BoardSim Crosstalk to automatically identify
which other nets are coupled to the selected net. If the threshold is not set to match the amount
of crosstalk you are concerned about, you could easily run your simulations with too many or
too few aggressor nets.

If a driver or receiver on the selected net is driven by an IBIS model with a [Diff_pin] keyword,
the net for the other pin in the [Diff_pin] keyword is automatically coupled, regardless of the
crosstalk threshold you specify. This behavior enables you to set the crosstalk threshold to a
value that detects unwanted coupling rather than intentional coupling. You can disable the
automatic coupling capability by setting an option in the Advanced tab of the Preferences dialog
box.

To have BoardSim assume differential pairs are coupled, enable the “Always Treat Diff Pairs as
Coupled” option in the Advanced tab of the Preferences dialog box. See “Preferences Dialog
Box - Advanced Tab” on page 1792.

This topic contains the following:

• “Setting an Electrical Threshold” on page 1223

• “The Default IC Model” on page 1224
• “Setting Geometric Thresholds” on page 1225
• “Restoring Default Thresholds” on page 1227

Setting an Electrical Threshold

HyperLynx recommends using electrical crosstalk thresholds rather than geometric, unless you
have a compelling reason not to. For a summary of why electrical thresholds are almost always
superior to geometric, see “Electrical Versus Geometric Identification of Aggressor Nets - Why
Electrical is Superior” on page 1222.

To set an electrical crosstalk threshold:

1. Do any of the following:

• Setup menu > Crosstalk Thresholds.
• On the Stimulus and Crosstalk page of the DDRx wizard, click Set Crosstalk
Thresholds. For information about this wizard page, see “DDRx Wizard - Stimulus
and Crosstalk Page”.
Interactive and DDRx batch simulation settings are saved separately.

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2. Click Use Electrical Thresholds.

3. In the Include nets with coupled voltages greater than box, type the threshold value, in
mV.
Example: If you would like simulations to include any aggressor nets that could
possibly generate more than 250 mV of crosstalk, type "250" into the box.
4. To change the default IC model, click Change Default IC Model. See “The Default IC
Model” on page 1224 for details on what the default model means and how it is used.
5. Click OK.
The new threshold setting takes effect immediately. If you already had a net selected in the
board viewer and just made a significant change to the threshold setting, you will likely see
(after a brief pause) a change in the number of aggressor nets displayed. If you set the threshold
lower (for example, dropped it from 150 mV to 75 mV), more potential aggressor nets are likely
to be found. If you set the threshold higher, fewer nets will be found.

The Default IC Model

When BoardSim Crosstalk examines a given net to determine if it is an aggressor to the selected
net, the program considers a number of factors, one of which is the characteristics of the
potential aggressor net’s driver IC. (Driver-IC switching time strongly affects the forward
component of crosstalk.) If the net has a specific driver-IC model loaded onto it (e.g., from a
.REF file or manually), that IC’s characteristics are used in the determination.

But if there are no models loaded on the potential aggressor net, then BoardSim Crosstalk uses
the characteristics specified for the default IC model. Therefore, the details of the default model
— especially the Rise/Fall Time — have a strong effect on how many aggressor nets are found
for a given victim net. The model’s values default to aggressive but reasonable values. If you set
the Rise/Fall Time to a small number (e.g., 100 ps), you may find very large numbers of
aggressor nets being found for each victim net; this may be unrealistic and cause very long
simulation times.

Table 29-5 shows in detail how and when the default IC model is used.

Table 29-5. Crosstalk Simulation - Default IC Model

Case How the Default IC Model is Used
Net has at least one output or I/O IC IC model's characteristics are used; default IC
model loaded model is ignored
Net has multiple output or I/O Characteristics of the fastest IC model are used;
models loaded default IC model is ignored
Net has one or more IC models Characteristics of the default IC model are used
loaded, but they are all input-only (no output or I/O IC model available)

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Table 29-5. Crosstalk Simulation - Default IC Model (cont.)

Net has no IC models loaded Characteristics of the default IC model are used
(no output or I/O IC model available)
In the Set Crosstalk Thresholds dialog box, the Default IC model characteristics box displays
the value of the default IC model’s rise/fall time. (This is the most significant of the models’
parameters for predicting crosstalk and finding aggressor nets.) To change the value, click the
Change Default IC Model button.

Setting the Default IC Model Characteristics

The values you set for batch simulation are independent from the values you set for interactive
crosstalk simulation. However, for simplicity, you probably will use the same values in both
places.

To set the characteristics of the default IC model:

1. Setup menu > Crosstalk Thresholds.

2. Click Change Default IC Model. The Default IC Model Settings dialog box opens.
3. In the Rise/Fall Time box, type the value (in ns) of the time in which the default driver
IC switches high and low (0%-100%, not 10%-90% or 20%-80%).
If the rise and fall times differ, enter the faster of the two.
This box and the Rise/Fall Time box on the Preferences dialog box (Setup menu >
Options > General > General tab) are linked. Editing either box automatically update the
value in the other box.
4. In the Output Impedance box, type the driving resistance of the default driver.
If you’re not sure of the value, 5 ohms is a reasonable guess.
5. In the Input Capacitance box, type the input capacitance of the default model assuming
it stopped driving and acted as a receiver.
If you’re not sure, 5 pF is a reasonable guess.
6. In the Switching Range box, type the rail-to-rail, or full, voltage swing for the default
model.
7. Click OK.
See also: “Editing Default IC Model Properties”

Setting Geometric Thresholds

Again, HyperLynx recommends using electrical crosstalk thresholds rather than geometric (see
“Electrical Versus Geometric Identification of Aggressor Nets - Why Electrical is Superior” on
page 1222 for details). However, you can switch to geometric thresholds if you wish.

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Searching for aggressor nets geometrically requires two threshold values:

Table 29-6. Geometric Thresholds Used to Identify Aggressor Nets

Geometric Threshold Description
Minimum parallelism length The minimum length over which a neighboring net
must be parallel to the victim net before it can be
considered an aggressor; the parallelism can come
in multiple "sections," i.e., is cumulative.
Maximum distance from victim Defines a "zone" to either side of the victim net; if
a neighboring net never comes at least this close to
the victim, then the neighbor is not an aggressor.

These two values are "ANDed," i.e., both must be satisfied in order for a neighboring net to be
considered an aggressor net. The maximum-distance value is measured from trace edge to trace
edge (not center-to-center).

Suppose the thresholds are set to 250 mils minimum parallelism and 40 mils maximum
distance. Then:

• If a neighboring net ran alongside the victim net for two inches, but never came closer
than 50 mils, it would not be considered an aggressor net
• If a neighboring net came as close to the victim net as 10 mils, but was closer than (or
equal to) 40 mils for a total distance of only 200 mils, it would not be considered an
aggressor net
• If a neighboring net came in four separate sections within 20 mils of the victim net, and
each 20-mil pass was 75 mils long (for a total parallelism of 4x75 = 300 mils), the net
would be considered a victim net

Geometric Thresholds are Cumulative

Note that an aggressor net’s parallelism to the victim net is cumulative, i.e., each time the
candidate aggressor comes within the "zone" set by the maximum distance threshold, the
amount of parallelism increases. If the total parallelism inside the zone equals or exceeds the
minimum parallelism threshold, the candidate becomes an aggressor.

Said another way, the threshold is applied against the summed effect of all the coupling on a net
(not just at the conduits). As a result, two nets may be reported as coupled even though there is
no single, contiguous, coupling region longer than the threshold that you set. In this case,
coupling was reported because the total amount of parallelism was sufficient for the sum to
exceed the threshold.

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Restoring Default Thresholds

At any time after making changes to the crosstalk thresholds (electrical or geometric), you can
reset them back to BoardSim Crosstalk’s default values.

To reset the crosstalk thresholds back to BoardSim Crosstalk’s default values:

1. Do any of the following:

• Setup menu > Crosstalk Thresholds.
• On the Stimulus and Crosstalk page of the DDRx wizard, click Set Crosstalk
Thresholds. For information about this wizard page, see “DDRx Wizard - Stimulus
and Crosstalk Page”.
2. Click Restore Defaults.
Defaults for either interactive or DDRx batch simulation are restored, depending on how
you opened the Set Crosstalk Thresholds dialog box in step 1.
3. Click OK.

How Aggressor Nets are Found

Once you have enabled crosstalk simulation and set crosstalk thresholds, BoardSim Crosstalk
will constantly and automatically keep its list of aggressor nets up-to-date. Any change you
make that affects crosstalk — to IC models, to the board stackup, to the list of power-supply
nets, to trace widths, etc. — will cause the list of aggressors nets to be updated.

Nets for a differential pair are automatically coupled when driven by an IBIS differential model,
regardless of the crosstalk threshold you specify. This behavior enables you to set the crosstalk
threshold to a value that detects unwanted coupling rather than intentional coupling.

Victim Net is Treated as an Aggressor

As BoardSim Crosstalk interactively constructs its list of aggressor nets, its most-basic task is to
find which neighboring nets can cause more crosstalk on the selected net than is allowed by the
threshold setting. This means that the selected net is inherently considered to be an victim net.

However, because in interactive simulation you control the IC models on every net — including
the selected/victim net — you have the ability to run the victim net as though it were actually an
aggressor. I.e., normally, if you consider the selected net to be a victim, you would set its driver-
IC model to "Stuck High" or "Stuck Low" during simulation. However, there is nothing to
prevent you from setting the model instead to "Output," which would make the selected net as
much an aggressor to the other aggressor nets as the others are aggressors to the selected net.

Accordingly, when BoardSim Crosstalk searches using an electrical threshold for aggressor
nets, it first considers how other nets can aggress onto the selected net, then, in a second pass,

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how the selected net can aggress onto other nets. The complete set of nets found in these two
searches constitutes the list of aggressor nets.

Algorithm for Finding Aggressor Nets

Finding aggressor nets geometrically is a straightforward problem. However, finding aggressor
nets using an electrical threshold is a more-difficult problem, particularly considering that the
underlying algorithm must run very quickly in order to be interactive.

HyperLynx’s algorithm for finding aggressor nets electrically is proprietary; we believe it

to be one of BoardSim Crosstalk’s most-unique and -powerful features. It is based on the
"weak coupling" theory of crosstalk, which (at the price of being somewhat approximate
compared to a full treatment of crosstalk) yields a set of closed-form prediction equations that
can be run real-time. The resulting capability is sufficient to make reasonable first-cut guesses
as to how much crosstalk a given net can generate on another.

However, of necessity, any such approximation algorithm has limitations. For nets with
"clean" linear routing, which run parallel to each other for a medium distance, the aggressor-
finding algorithm is quite accurate. As the routing topology becomes more complex, then the
algorithm’s results are more approximate.

HyperLynx has attempted to adjust its aggressor-net-finding algorithm to be conservative, i.e.,

the goal is to identify as an aggressor any net which potentially can generate as much or more
crosstalk on the selected/victim net than specified by the threshold. However, there is no
guarantee that a given aggressor will generate the amount predicted, and it is quite possible that
it will generate less. (Or in some more-unusual cases, it may even generate more.) Only a
detailed simulation (interactive or batch) can determine the real amount.

Still, in spite of these limitations, the concept of electrical thresholds is very powerful. It allows
you to screen for crosstalk effects in the electrical terms that are the natural language of digital
design. It also generally does a good job of rapidly and automatically identifying important
aggressor nets, and rarely omits a significant crosstalk contributor from simulation.

Aggressor Nets are Found on All Layers

Unlike some tools, which by default look only for aggressor nets on the same layer as the victim
net, BoardSim Crosstalk looks at all layers when it searches for coupling regions and aggressor
nets.

If your PCB has multiple signal layers that are not separated by plane layers (e.g., a microstrip
and buried-microstrip layer), you’ll likely see some inter-layer coupling if you run the coupling-
region viewer

See also: “Viewing Coupling Regions” on page 1239

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How Aggressor Nets are Displayed

If you have crosstalk simulation enabled (see “Enabling Interactive Post-Layout Crosstalk
Simulations” on page 1219 for details), then each time you select a net for simulation,
BoardSim Crosstalk automatically searches for all nets that are aggressors to the selected net,
and displays them along with the selected net in the board viewer.

Remember that this process of finding aggressor nets is heavily dependent on how you have
BoardSim’s crosstalk thresholds set; low electrical thresholds will cause many aggressor nets to
be found, and high thresholds fewer nets (see “How to Set the Crosstalk Threshold” on
page 1223 for details). So after enabling crosstalk simulation and before simulating, be sure to
set the crosstalk thresholds sensibly.

Distinguishing the Selected Net from Aggressor Nets in the

Board Viewer
With crosstalk simulation enabled, the board viewer automatically shows both the selected net
and its aggressors. The selected net looks just like it does in the base BoardSim product, i.e., it is
drawn with solid, colored segments; the colors correspond to different stackup layers.
Aggressor nets also display with their layer colors, but they appear "dashed" — or more
precisely, have a dashed white line drawn along their centers.

Thus, it’s fairly easy in the board viewer to distinguish between the selected and aggressor nets.
Only the selected net is not dashed.

Another way to distinguish between the selected and aggressor nets is to toggle the toolbar’s
Enable Crosstalk Simulation button on and off several times. The aggressor nets will disappear
and re-appear; the selected net will always display.

Identifying a Particular Net in the Board Viewer

Sometimes, especially when there are many aggressor nets displayed, you may want to identify
particular nets in the board viewer. The can easily be done by pointing to the net in question
with the mouse.

To identify particular nets in the board viewer using the mouse:

1. Point to the net that you wish to identify.

2. Look in the status bar at the bottom left of the BoardSim window.
Result: The name of the net you’re pointing to is displayed.

This feature actually operates dynamically at all times in BoardSim, whether crosstalk
simulation is enabled or not. (As you move the mouse around, it even identifies nets that are not
presently visible in the board viewer.) If you point to a position at which there are multiple nets
(on different stackup layers), the readout in the status bar lists all net names.

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Setting IC Models for Crosstalk Simulations

How you choose IC models for the nets involved in a crosstalk simulation has a major impact on
the simulation results. There are several reasons for this:

• First, what models are loaded strongly affects which aggressor nets are found for any
selected victim net. Potential aggressors which have no models are assumed to behave
as if driven by the default IC model (see “The Default IC Model” on page 1224 for
details).
• Second, any aggressor net which enters the simulation (perhaps because the default IC
model has a fast switching time) but actually has no driver IC loaded will not switch
during simulation and therefore won’t contribute any crosstalk to the victim net. So it’s
important that all significant aggressor nets have driver-IC models present.
Thus, setting up IC models is an important aspect of running crosstalk simulations. As usual in
BoardSim, there are several ways to get models loaded, including from a .REF file or manually
in the Assign Models dialog box. And multiple model styles (.MOD, .PML, and IBIS) can be
used and mixed in any way desired.

See also: “Comparing Model-Selection Methods”

Effect of IC Models on Pins in the Assign Models Dialog Box

In the base BoardSim product, when you open the Assign Models dialog box to manually assign
IC models (or to check which models were automatically loaded), the Pins list displays all of the
component pins on the selected net and its associated nets. The contents of this list does not
change as you add or change IC models.

In BoardSim Crosstalk, on the other hand, the Pins list displays the component pins on the
selected net, on its associated nets, and on all nets which are aggressors to the selected net. But
the list of aggressor nets changes depending on which IC models are loaded (since the amount
of crosstalk generated depends on the characteristics of the driving ICs). Therefore, when
crosstalk simulation is enabled, the Pins list in the Assign Models dialog box changes
contents as you add, change, or remove IC models.

See also: “About the Assign Models Dialog Box” on page 485

Table 29-7 lists some of the effects you can see in the Assign Models Pin list as you make IC-
model changes.

Table 29-7. Changing IC Models - Effect on Pins List

Action Example Effect

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Table 29-7. Changing IC Models - Effect on Pins List (cont.)

Change an aggressor net's driver-IC Because the net is now driven with a slower
model to a slower model switching edge, it will not generate as much
crosstalk; if the crosstalk amount drops the
threshold, the net is now longer an aggressor and
all of its pins disappear from the Pins list
(including the one you just changed).
Remove an aggressor net's IC Several effects are possible. Suppose the aggressor
model net has no other output or I/O models loaded; then
the default IC model takes effect. If the default
model is slower, then the aggressor net's pins
disappear. If the default model is faster, the net
remains an aggressor and no changes occur.
Change an IC model on the victim Remember that aggressor nets are judged not only
net to a slower model by the effect they have on the victim net, but also
by whether the selected/victim net can aggress
onto them. Therefore, a slower driver-IC model on
the victim net could cause one or more aggressor
nets to disappear, and many pins in the Pins list to
vanish.
The key point is that with crosstalk simulation enabled, the contents of the Pins list in Assign
Models is dynamic. BoardSim Crosstalk will constantly update its list of aggressor nets in
response to IC-model changes you make. As you change IC models, the Pins list may grow or
shrink.

Identifying Nets in the Assign Models Dialog Box

One difference between coupled and uncoupled simulations is that with crosstalk enabled,
multiple nets are simulated simultaneously and the Pins list in the Assign Models dialog box
tends to be long (compared to when crosstalk is disabled). This can make it difficult to know
which pins belong to which nets, and whether a given pin is on an aggressor net or the
selected/victim net.

See also: “About the Assign Models Dialog Box” on page 485

How to tell whether a pin is on the selected/victim net or on an aggressor net:

• In the Pins list, if a pin has a "coupling" icon (see picture below) to its immediate left,
the pin belongs to an aggressor net.
If the pin has no icon, it belongs to the selected/victim net.

The coupling icon looks like this (indicates an aggressor net):

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How to tell which net an IC pin is on:

1. In the Pins list, select the IC pin.

2. To the right of the Pins list, the Net field displays the net the pin is on. The net name
appears in blue to make it easy to find.

Running Simulations
Once you have followed the steps described in the preceding topics, running interactive
crosstalk simulations is no different than running "ordinary" uncoupled simulations in the base
BoardSim product.

As a reminder, the following "extra" steps are required to perform crosstalk simulations,
compared to uncoupled simulations. For details on any of these topics, see the appropriate
topics in the Help system by using the index or browse buttons.

Basic Procedure to Run Interactive Crosstalk Simulation

"Extra" steps before running interactive crosstalk simulations:

1. Enable crosstalk simulation.

2. Set the crosstalk threshold (preferably using the electrical threshold).
3. Optionally, change the characteristics of the default IC model.
4. Add IC models, if needed, to the selected/victim and aggressor nets.
5. Include non-switching (i.e., "stuck") driver ICs on victim nets. See "Importance of
Modeling Drivers on Victim Nets (as "Stuck High" or "Stuck Low")" below in this
topic.
6. Note the number of aggressor nets displayed in the board viewer; make adjustments to
the crosstalk threshold, if desired (for more details, see “How to Set the Crosstalk
Threshold” on page 1223).
The only steps remaining are to apply oscilloscope probes and begin simulating.

Applying Oscilloscope Probes

Oscilloscope scope probes are applied for crosstalk simulations in the same way as for
"ordinary" uncoupled simulations. The only difference is that, because there are typically
multiple nets involved in a crosstalk simulation, there are usually many more pins available for
probing (compared to uncoupled simulations).

Accordingly, you may need to plan your probing strategy more carefully for crosstalk
simulations than for uncoupled. In particular, the auto-assignment feature (that places the

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oscilloscope probes on the first six available IC pins) will tend, for crosstalk simulations, to not
place probes where you’d like them.

Normally, you’ll want to probe on the selected/victim net, to see what the crosstalk waveforms
look like at various receiver pins. If you are also driving the selected net (so that it aggresses
onto the "aggressor" nets), you may want to place some probes on the aggressors.

Running a Simulation
Simulation proceeds exactly in BoardSim Crosstalk as in the base BoardSim product. Once
oscilloscope probes are applied, open the digital oscilloscope and click Start Simulation.

Importance of Modeling Drivers on Victim Nets as Stuck High or

Stuck Low - BoardSim
It is important to include non-switching (i.e., "stuck") driver ICs on victim nets, because on a
real PCB, victim nets do have drivers. If you omit the "stuck" driver(s), simulated crosstalk
waveforms will look much different than if you include them. This occurs because driver ICs
are typically low impedance and will reflect, rather than absorb, crosstalk signals. In general,
you should check both the stuck-low and stuck-high cases whenever you simulate, to see which
generates more crosstalk.

How to Maximize Simulation Performance

As noted previously, crosstalk simulations are often much more CPU-intensive than uncoupled
simulations. This is particularly true if the combination of your board’s geometry and stackup
and your crosstalk-threshold settings result in a large number of aggressor nets being found for
every selected net.

Although you generally do not want to miss the contribution of any net that could be an
aggressor, there are diminishing returns associated with including large numbers of aggressor
nets in every simulation. It is important to remember that BoardSim Crosstalk’s aggressor-net-
finding algorithm is designed to be conservative: many nets that it selects will actually generate
less crosstalk than expected.

Also, if you set your crosstalk thresholds to a reasonable level and are still finding large
numbers of aggressor net in each simulation, you may have a serious board-wide crosstalk
problem which is better addressed by globally changing your trace separations or PCB stackup
than by trying to simulate and "tune" individual nets one-at-a-time.

Do Not Set the Crosstalk Threshold Unrealistically Low

One thing to avoid is setting the crosstalk threshold unrealistically low. For example, suppose
you are worried about any crosstalk which exceeds 150 mV. There is no point in setting the

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threshold even lower—say, 50 mV—to try catching every possible simulation detail. This will
only result in much slower simulations that add no information to your analysis results.

Even though BoardSim Crosstalk allows you to set the electrical crosstalk threshold as low as
10 mV, you should rarely (if ever) use such a low setting. Remember that there are many
tolerances built-in to signal-integrity simulation: PCB manufacturing tolerances, IC-model
approximations, and so forth. For many simulations, results in the 10-20 mV range may be
down at the noise floor of these various tolerances.

Limiting the Number of Aggressor Nets

BoardSim Crosstalk has a user-settable limit on the maximum number of aggressor nets to
include in a simulation. This limit works as follows:

• If the limit is set to "N," then the N strongest aggressors are included in the simulation;
other, weaker aggressors are omitted
The concept of choosing the strongest aggressor nets is important. If a given crosstalk-threshold
setting yields 30 possible aggressor nets, choosing the 12 strongest is quite reasonable; choosing
12 at random would be error-prone. Note that BoardSim Crosstalk’s aggressor-net-finding
algorithm is "smart" enough to know with good accuracy how aggressor nets rank against each
other in terms of crosstalk-generating strength (see “How Aggressor Nets are Found” on
page 1227 for more details).

The limit is defaulted to a reasonable number that will almost always incorporate all of the
significant aggressor nets into your simulations. Nevertheless, you can change the limiting
value, if you wish.

Changing the Number of Aggressor Nets Limit

To change the limit on the maximum number of aggressor nets to include in a simulation:

1. Setup menu > Options > General > BoardSim tab.

2. In the Crosstalk Options area, in the Maximum Number of Aggressor Nets box, type the
new value.
3. Click OK.
Note that the limit setting is not completely dynamic. If you change it with a net selected, the
number of aggressor nets found will not change until you re-select the net or toggle crosstalk
simulation off and back on.

Aggressor Net Limit Applies to More than Simulation

The limit on the maximum number of aggressor nets to include in analysis applies to more than
just simulation: it actually affects the entire BoardSim Crosstalk product, for consistency. For

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example, the limit applies in the board viewer, when the Terminator Wizard runs, etc. — any
portion of the software which uses aggressor nets.

Each Aggressor Net and Its Associated Nets Count Only Once
Note that the number-of-aggressors maximum applies to combinations of aggressor nets and
their associated nets. Therefore, the actual number of nets in the simulation may exceed the
value of the limit. For example, if the limit is "12" and each aggressor net has one associated
net, then there could validly be 25 nets in the simulation (the selected net + 12 aggressors + 12
nets associated with the aggressors).

Using the Aggressor-Net Limit to Improve Simulation Performance

The default value of the aggressor-net limit is fine for most designs and does not need to be
changed. However, if you begin running interactive simulations and find them to be running
very slowly, you may need to decrease the limit so that fewer aggressors are included and
simulations run faster. Depending on the routing of your board and the amount of accuracy you
need in your simulations, values as low as "4" or "5" may be reasonable.

Determining How Many Aggressor Nets Have been Found

You can determine exactly how many aggressor nets have been found for a given selected net.
The same feature also lists the names of each aggressor net (and its associated nets).

To determine how many aggressor nets there are for the currently selected net:

1. Export menu > Reports > Net Statistics.

2. After a pause for processing, the Associated Nets list displays all nets associated with
the currently selected net.
Aggressor nets which are in the list because of coupling are denoted with "by coupling"
following their name. Nets in the list without this label are electrically associated with the
selected net (i.e., connected directly to it through a component, e.g., a resistor).

Running the Field Solver in BoardSim

This section describes what a field solver is and how you can use it to calculate impedances,
delays, and other electrical parameters of coupled transmission lines. You can use the coupling-
region viewer to display individual coupling regions along a set of coupled nets. You can view
and save detailed electrical parameters for a coupling region.

This topic contains the following:

• “About BoardSim Crosstalk and the Field Solver” on page 1236

• “About the Field Solver in BoardSim” on page 1236

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• “How BoardSim Crosstalk Field Solver Works” on page 1237

• “Viewing Coupling Regions” on page 1239
• “Details of the Field-Solver Information” on page 1245
• “Generating a Report of the Field Solver Numerical Results” on page 1251

About BoardSim Crosstalk and the Field Solver

In LineSim Crosstalk, the use of the field solver is very explicit: you define "coupling regions"
in LineSim’s schematic editor, and the field solver is invoked to find the coupled electrical
characteristics of each region.

See also: “Adding Coupling to LineSim Schematics”

By contrast, BoardSim Crosstalk’s use of the field solver is much more hidden and automatic.
When you select a net in BoardSim with crosstalk analysis enabled, the program automatically
finds the nets to which the selected net is coupled (for details, see “How BoardSim Crosstalk
Finds Aggressor Nets” on page 1220). Furthermore, the program models in detail all of the
coupling regions implied by the physical layout of your board. (A "coupling region" is just a
cross section of some length which specifies geometrically how a set of traces are coupled to
each other.) Then, before detailed simulation can be run, the field solver must be invoked to find
the electrical characteristics of each of the regions.

The BoardSim Crosstalk product can be constructed such that the entire process of finding and
characterizing coupling regions is completely hidden. While you can run BoardSim Crosstalk in
this manner (without bothering to look at any of the details), it is also possible to request
information about which coupling regions have been identified for a particular selected net, and
what the electrical characteristics of those regions are. This is strictly optional — there’s no
need to look at any of the details — but for users who want to see how BoardSim is choosing
coupling regions or need information about coupled impedances, etc., the data are available.

About the Field Solver in BoardSim

A field solver is a program that can solve for the electrical characteristics of a system of
conductors and dielectrics, using one or more of the basic equations of electromagnetic theory
("Maxwell’s equations"). Specifically, BoardSim Crosstalk uses its field solver to solve for the
capacitances, inductances, propagation velocities, and characteristic impedances of the coupling
regions it automatically detects when you select a net for analysis (for details on coupling
regions, see “How BoardSim Crosstalk Finds Aggressor Nets” on page 1220).

Because coupling regions consist of two-dimensional cross sections that are assumed to be
constant over some specified length, BoardSim Crosstalk’s field solver needs to work in only
two dimensions. Taking advantage of this fact allows BoardSim to calculate coupling
parameters accurately, but also very quickly.

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Tip: Three-dimensional electromagnetic solutions become important only if the

frequencies of the signals traveling on a system of conductors is so high that the
wavelengths of the signals’ components are shorter than the various conductor structures
in the system (e.g. vias, corner bends, etc.). This condition rarely occurs on PCBs
carrying digital signals, so tools that analyze digital PCBs use two- rather than three-
dimensional solvers. The big gain for users is speed: solvers run much faster in two
dimensions than in three.

When more than one transmission line is present in a coupling region, the various electrical
parameters of the system take on a matrix form. For example, for a two-trace coupling region,
there is no longer a single value of capacitance that describes the region’s cross section. Rather,
there exists a 2x2 matrix which specifies both the capacitances of the individual traces to
ground, and the capacitance between the traces.

Tip: The matrix nature of the electrical parameters describing a multi-trace coupling
region is unfamiliar to many engineers and designers. For some detailed background
information on coupled transmission lines and how they are described in matrix form, see
“Information in the Impedance Pane” on page 1244.

How BoardSim Crosstalk Field Solver Works

The information in this topic is provided only for those who are curious about what techniques
BoardSim Crosstalk’s field solver uses to perform calculations.

This topic contains the following:

• “Calculation Details” on page 1237

• “Field-Solver Cache” on page 1238
• “What Information is Calculated” on page 1239

Calculation Details
After finding aggressor nets and identifying the coupling regions associated with, then in order
to determine the electromagnetic properties of each region’s cross section, BoardSim
Crosstalk’s field solver must calculate the capacitance and inductance matrices of each cross
section. These matrices give the conductor-to-ground and conductor-to-conductor capacitances
and the self and mutual inductances of the traces in the coupling region.

To calculate capacitance values, BoardSim Crosstalk’s field solver finds the solution to
Laplace’s equation, a form of one of Maxwell’s basic equations of electromagnetics:

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In the solution, the solver seeks to find charge densities on the conductor surfaces and dielectric
boundaries, rather than bothering to calculate the electric potential at all points between the
conductors. This approach makes BoardSim’s field solver a "boundary-element" solver.
Several proprietary methods are used to speed calculations significantly while maintaining a
high level of accuracy.

The solution to Laplace’s equation occurs subject to all of the boundary conditions specified in
the coupling region’s cross section, i.e., it takes into account the exact shapes and locations of
the conductors in the region and the locations and material properties of the dielectric
boundaries. Special care is taken to calculate charge density accurately in regions in which it
changes rapidly (e.g., at the corners of conductors).

Once the coupling region’s capacitance values are found, then to calculate the inductance
matrix, the field solver takes advantage of the following equation from transmission-line theory:

This allows a second solution to Laplace’s equation — one in which all of the dielectrics are
replaced by vacuum and the capacitance matrix C0 is found — to substitute for an explicit
calculation of the coupling region’s magnetic properties.

Once the capacitance and inductance matrices are both known, then the region’s propagation
speed(s) and characteristic impedances can be calculated. For the case of inhomogeneous
dielectrics (i.e., a mixture of dielectric constants, as occurs with microstrip and buried-
microstrip traces), multiple propagation speeds exist. These speeds are found from the
eigenvalues of the matrix product LC.

Field-Solver Cache
Since for each selected net and its aggressor nets, there are usually many physical coupling
regions, BoardSim runs the field solver and repeats the steps described above for each region.
Sometimes, there may be a hundred or more regions involved in a single selected net’s analysis;
the solver must run on all of these.

To speed the process, the field solver uses a smart cache which stores previous solutions; when
the same cross section (or a geometric "reflection" of it) needs to be solved again, the answer is
read from the cache rather than being recomputed. Usually, using this technology, BoardSim
Crosstalk can solve all of the required cross sections for a given set of nets in a few seconds;
however, very large or complex sets of nets may take longer.

If running the field solver is likely to introduce a noticeable delay, then a progress bar is
displayed to show you the solver’s status.

The field solver’s cache file is stored in the same directory as the BoardSim Crosstalk
executable (BSW.EXE). The name of the cache file is "FS_Cache.cah"; it is a binary file. If the

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file is deleted, BoardSim Crosstalk will start rebuilding it; you may notice a small slowdown in
the program while the cache builds back up. The cache is flushed periodically to prevent the
cache file from growing beyond several megabytes in size.

What Information is Calculated

In BoardSim Crosstalk, the field solver’s job is to calculate the following information for every
coupling region found for the selected net and its aggressor nets.

The field solver produces the following data:

• “Capacitance Matrix” on page 1248

• “Inductance Matrix” on page 1248
• “Characteristic-Impedance Matrix” on page 1247
• “Propagation-Speeds List” on page 1249
• “Optimal Terminator-Resistor Array” on page 1246
For background information on why many of these quantities are described in matrices, see
“Propagation-Speeds List” on page 1249 and “Optimal Terminator-Resistor Array” on
page 1246.

This information is calculated from the purely geometric and material data provided in your
board’s .HYP file and its stackup. Therefore, the field solver can be thought of as a calculation
engine that transforms geometric/material data into corresponding electromagnetic data.

It is possible, if you want, to view the results of the field solver’s calculations for a selected
net’s coupling regions.

See also: “Viewing Coupling Regions” on page 1239

Viewing Coupling Regions

Use the Coupling Region dialog box to view the physical and electrical properties of one
coupling region on the selected net. A coupling region is a coupling cross section with two or
more trace segments with specific electrical characteristics. The information provided by the
Coupling Region dialog box is helpful in understanding how each net contributes to the
coupling in the region.

The board viewer automatically highlights the net trace segments that make up the coupling
region, so you can see the coupling region location in the board layout. Usually there are
multiple coupling regions along the whole length of a net. You can view other coupling regions
on the selected net by moving, or "walking," from one coupling region to another.

See also: “Coupling Regions and Coupling Dots”

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Requirement: The BoardSim Crosstalk license is required to view coupling regions.

This topic contains the following:

• “When to View Coupling Regions” on page 1240

• “Viewing Coupling Regions in the Board Viewer” on page 1240
• “Opening the Coupling-Region Viewer” on page 1240
• “Moving from Region to Region” on page 1241
• “Viewing Coupling Region Properties” on page 1241

When to View Coupling Regions

BoardSim Crosstalk automatically identifies aggressor nets, finds their coupling regions, and
generates field-solver data for each coupling region. There is absolutely no requirement for you
to examine coupling region properties. However, you may want to know the details in some
cases. Examples:

• Suppose you have one or more differential trace pairs on the board. You may want to
know the trace-to-trace impedance the field solver calculated for the differential pairs.
• You may want to know the location of the strongest coupling between the selected
victim net and nearby aggressor nets.

Viewing Coupling Regions in the Board Viewer

To make it easy to see the location of a coupling region in the board layout, the board viewer
highlights the trace segments in the coupling region in a contrasting color. When you move
from region to region, the board viewer highlights the segments for the current coupling region.

The board viewer does not automatically keep the current coupling region in view, so you may
need to pan the board or move the Coupling Region dialog box out of the way. When the
Coupling Region dialog box is open, most of the BoardSim menu and toolbar functionality is
unavailable, however viewing functionality remains available. This enables you to pan and
zoom in the board viewer to see various coupling regions.

It is easiest to see highlighted coupling regions if you zoom out fairly far, so you will do less
panning, and make the Coupling Region dialog box fairly small (it can be resized).

Opening the Coupling-Region Viewer

You can view coupling region information if you have crosstalk enabled and have set the
crosstalk threshold to a value such that at least one aggressor net is found for the selected net.

Requirement: The BoardSim Crosstalk license is required to view coupling regions.

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To open the coupling-region viewer by selecting a net:

1. Select a net.
See also: “Selecting Nets for SI Analysis”
2. View menu > Coupling Regions. The Coupling Region dialog box opens and displays
the strongest coupling region.
To open the coupling-region viewer by right-clicking over a net object in the board viewer:

• Right-click over a trace segment for the net, and click Walk Coupling Regions. The
Coupling Region dialog box opens and displays the coupling region nearest the pointer.
See also: “Viewing Coupling Regions” on page 1239, “Reporting Net Segment Properties”

Moving from Region to Region

Since the Coupling Region dialog box displays only one coupling region at a time, it provides a
way to move from one coupling region to another.

The Coupling Region dialog box sorts the coupling regions by coupling strength. The title pane
of the dialog box displays the current coupling region name (an arbitrary integer) and the total
number of coupling regions found along the selected net.

To move from region to region, do the following:

• To move to a weaker coupling region, click Next.

• To move to a stronger coupling region, click Back.
Result: The other coupling region is displayed in the Coupling Region dialog box and
highlighted in the board viewer.

When you move beyond the last coupling region, the Coupling Region dialog box displays the
first coupling region.

Viewing Coupling Region Properties

The Coupling Region dialog box consists of three panes. See Figure 29-6.

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Figure 29-6. Coupling Region Dialog Box Panes

Table 29-8 shows the information displayed in the panes.

Table 29-8. Coupling Region Dialog Box - Contents Overview

Pane Contains

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Table 29-8. Coupling Region Dialog Box - Contents Overview (cont.)

Nets Names of the nets in the coupling region and the
geometric relationships among their trace
segments.

The distance of the other nets from the selected

net. If the nets are on the same layer, the distance
is edge to edge. If the layers are on different layers,
the distance is the vertical separation in the
stackup.

The layer implementing the net in the stackup.

While a net may be partially routed on different
layers, this layer is used for this specific coupling
region.

The trace segment width.

Usually the coupling region contains different

nets, such as one from the selected victim net and
others from various aggressor nets. However since
a net can couple to itself, for example a
"serpentine" route, it is possible for the coupling
region to consist entirely of trace segments from
the same net.
Impedance Electrical characteristics of the coupling region, as
generated by the field solver.

See also: “Information in the Impedance Pane” on

page 1244, “Details of the Field-Solver
Information” on page 1245, “Generating a Report
of the Field Solver Numerical Results” on
page 1251
Cross Section Geometric relationships of the nets in the coupling
region. Essentially the information is the same as
displayed by the Nets pane, but in a graphical
form.

To identify the net for a trace segment, move the

pointer over it. A ToolTip displaying the net name
appears.

If the ToolTip does not appear, make the Cross

Section pane larger and try again, or drag the
splitter bar to enlarge the Cross Section pane.

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Hiding or Showing Panes

If you are moving from region to region and find the Coupling Regions dialog box obscures
your view, you can make the dialog box smaller by a combination of resizing the window and
hiding unwanted panes.

To hide or show panes:

• Click Nets, Impedance, or Cross Section.

To resize a pane, drag the splitter bar between the panes.

When you show a pane that is currently hidden, it appears below any currently-displayed panes.

Information in the Impedance Pane

The Impedance pane on the Coupling Region dialog box shows you all of the data calculated by
the field solver for traces in the current coupling region.

Table 29-9 summarizes the electrical information contained in the Impedance pane.

Table 29-9. Coupling Region Dialog Box - Contents of Impedance Pane

Information Means
Impedance and Termination Impedance values, including the differential,
Summary common-mode, and line-to-ground values.

Available only for coupling regions with two

traces.
Physical Input Data Geometric data for the coupling region.
Optimal Terminator-Resistor Array An array of resistors, line-to-ground and line-to-
line, that perfectly terminates the system of
coupled transmission lines. In theory, this array
can completely eliminate crosstalk amongst the
transmission lines.
Characteristic Impedance Matrix Full matrix impedance for the system of coupled
transmission lines. Off-diagonal values are small
for weak coupling and large for strong coupling.
Capacitance Matrix Self and mutual capacitances of the traces
Inductance Matrix Self and mutual inductances of the traces
Propagation Speeds Velocities at which signals propagate on the traces.
Multiple values exist if the trace electromagnetic
fields pass through more than one type of
dielectric, such as microstrip or buried microstrip.

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Table 29-9. Coupling Region Dialog Box - Contents of Impedance Pane (cont.)
Percentage of energy traveling in Amount of energy in the trace that travels at each
each mode propagation velocity.

Available only for multiple-speed coupling

regions.

Related Topics
“Viewing Coupling Regions” on page 1239

“Details of the Field-Solver Information” on page 1245

“Generating a Report of the Field Solver Numerical Results” on page 1251

“Running the Field Solver in BoardSim” on page 1235

Details of the Field-Solver Information

While Table 29-9 summarizes the electrical information contained in the Impedance pane,
detailed explanations are available.

This topic describes the following:

• “Physical Input Data” on page 1245

• “Optimal Terminator-Resistor Array” on page 1246
• “Characteristic-Impedance Matrix” on page 1247
• “Capacitance Matrix” on page 1248
• “Inductance Matrix” on page 1248
• “Propagation-Speeds List” on page 1249
• “Percentage of Energy Matrix for Multiple-Speed Coupling Regions Only” on
page 1250
See also: “Impedance and Termination Summary for Two-Line Coupling Regions Only” on
page 1250

Physical Input Data

This section of the field-solver data shows for what geometric and material information the
field-solver results were calculated. The information serves as a record of the input problem, for
future reference. The input data includes information on each trace in the coupling region as
well as the board’s stackup.

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Running the Field Solver in BoardSim

Correlating Transmission Lines and Matrix Indices

In the input data, the Field Solver Traces section lists by name each net in the coupling region,
and shows the corresponding trace index by which the net’s segment is referred to in the
electrical matrix data elsewhere in the data. This data allows you to correlate nets and trace
indices. See Figure 29-7.

Figure 29-7. Example of Table Correlating Nets and Trace Indices

Field-Solver Output Data

This section of the field-solver data shows the electrical data calculated by the field solver for
the coupling region. As described earlier, much of this data are in matrix form, because the
transmission lines in the region are coupled together. For background information on how
electrical parameters are expressed for systems of coupled lines, see “Electrical Parameters of
Coupled Transmission Lines” on page 1357.

Refer to topics in the table of contents for details on the field solver’s electrical data.

Optimal Terminator-Resistor Array

Sometimes, users of BoardSim Crosstalk’s crosstalk-analysis features are interested in how to
terminate traces that are coupled to other traces. This matrix gives the theoretically optimal
resistor termination array for the set of coupled lines in the coupling region.

A key fact about coupled lines is that they cannot be perfectly terminated individually. Instead,
a matrix of resistors that prescribes both line-to-ground and line-to-line resistances is required.
(Again, for background information, see “About Crosstalk and its Causes” on page 1348.) This
termination array has the remarkable property that it not only "kills" single-line reflections at
the line ends, but also eliminates arriving crosstalk signals.

On the other hand, there are many situations in digital electronics where line-to-line resistors (in
addition to adding undesirably to passive-component count) are simply not permissible for DC-
bias reasons. For example, whereas two coupled data lines may require a 160-ohm resistor
between them to eliminate line-to-line crosstalk, it is unlikely that the driver ICs on the lines
would be "happy" with the resistor when one line was pulled high and the other low.

Still, in some critical situations, especially when the line-to-line coupling is relatively weak and
therefore the line-to-line terminating resistances are fairly high, a matrix terminator may be
workable.

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There are some IC technologies which are specifically designed to work with line-to-line
termination: differential drivers. For these devices, line-to-line termination serves not only to
prevent line reflections and eliminate crosstalk, but is often also required to bias the ICs for
correct operation.

To implement the termination described in the Optimal Terminator-Resistor Array matrix:

1. Place the resistors in the diagonal matrix positions between the corresponding trace to
ground.
Example: Resistor 2-2 should be placed from trace 2 to ground, at the trace end.
2. Place the resistors in the off-diagonal matrix positions line-to-line between the
corresponding traces.
Example: Resistor 2-1 should be placed between traces 1 and 2, at the trace ends.
Note that there are twice as many off-diagonal values as there are line-to-line resistors, since,
for example, off-diagonal resistance 2-1 refers to the same resistor as resistance 1-2.

To correlate a specific transmission line in a coupling region to a matrix index, see the
Fieldsolver Traces section of the Physical Input Data section of the field-solver report, as
illustrated in Figure 29-4.

See also: “Physical Input Data” on page 1245

Characteristic-Impedance Matrix
This matrix gives the characteristic impedance (in ohms) of the system of coupled nets in the
coupling region. Coupled lines do not have a single-value impedance, like uncoupled lines.
Rather, together, a set of coupled lines share an impedance matrix.

The values in the diagonal matrix positions can be thought of as giving the impedances to
ground of the corresponding nets, accounting for the presence of the other nearby, coupled
traces. When an IC drives into one of the lines, however, it "sees" not only the diagonal
impedance for that line, but also some of the off-diagonal terms in the matrix.

For nets that are only weakly coupled, the diagonal impedance terms are dominant, and the
diagonal values are close to what they would be if the lines were completely isolated from each
other. As the coupling becomes stronger, the diagonal terms deviate more from their standalone
values, and the off-diagonal terms increase. Note that small off-diagonal impedances mean
weak coupling; large impedances mean strong coupling.

Barring special cases like two-line pairs in which the two signals are known to be either purely
differential or purely common-mode, the diagonal impedances in the matrix are generally the
best single-resistor terminators to use. Note, however, that coupled transmission lines cannot be
perfectly terminated unless a full matrix termination (including both line-to-ground and line-to-
line resistors) is employed. See “Optimal Terminator-Resistor Array” on page 1246 for details.

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To correlate a specific transmission line in a coupling region to a matrix index, see the
Fieldsolver Traces section of the Physical Input Data section of the field-solver report, as
illustrated in Figure 29-4.

See also: “Physical Input Data” on page 1245

Capacitance Matrix
This matrix gives the self and mutual capacitances (in pF/m) of the coupled nets in the coupling
region. More specifically, the diagonal values in the matrix give the capacitances to ground of
the corresponding transmission lines, while the off-diagonal values give the capacitances
between the corresponding pair of lines.

Many users are surprised to see that the off-diagonal capacitance-matrix values are negative.
The negative sign simply reflects the fact that if a positive charge is placed on a given trace,
negative charge will accumulate on all others.

For purposes of judging how much capacitance exists between traces, you can ignore the
negative signs. The off-diagonal values do represent real, physical capacitance.

However, in the mathematical formalism of coupled transmission lines, the negative signs are
important. For example, if you transfer the capacitance matrix for a coupling region to another
EDA tool (e.g., SPICE), the off-diagonal values must be negative.

Note that the values in the capacitance matrix have units of pF/m, rather than simply pF. This
means that if you are trying to calculate, for example, the total capacitance-to-ground of a net in
the matrix, you must multiply the corresponding diagonal value in the matrix by the length (in
meters) of the net.

To correlate a specific transmission line in a coupling region to a matrix index, see the
Fieldsolver Traces section of the Physical Input Data section of the field-solver report, as
illustrated in Figure 29-4.

See also: “Physical Input Data” on page 1245

Inductance Matrix
This matrix gives the self and mutual inductances (in nH/m) of the coupled nets in the coupling
region. More specifically, the diagonal values in the matrix give the self inductances of the
corresponding transmission lines, while the off-diagonal values give the mutual inductances of
the corresponding pair of lines.

Note that the values in the inductance matrix have units of nH/m, rather than simply nH. This
means that if you are trying to calculate, for example, the total self inductance of a net in the
matrix, you must multiply the corresponding diagonal value in the matrix by the length (in
meters) of the net.

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To correlate a specific transmission line in a coupling region to a matrix index, see the
Fieldsolver Traces section of the Physical Input Data section of the field-solver report, as
illustrated in Figure 29-4.

See also: “Physical Input Data” on page 1245

Propagation-Speeds List
This list gives the speed(s) (in m/s) at which signals propagate along the nets in the coupling
region. As described in more detail in “Coupled Transmission Lines” on page 1358, coupling
regions in which there is only dielectric (e.g., for stripline traces) have only one propagation
speed; the signals on all traces in the region propagate with this single velocity.

However, coupling regions in which there are boundaries between dissimilar dielectrics (e.g.,
for microstrip or buried-microstrip traces) have multiple, discrete propagation speeds.
Generally, each transmission line in the coupling region propagates some energy at each of the
velocities prescribed by the region. There are as many speeds as there are transmission lines in
the coupling region.

For most practical cross-section geometries, the multiple speeds are all close to each other.
However, it is possible to encounter highly asymmetric cross sections in which the speeds are
quite different. (An example of a "highly asymmetric" geometry would be a microstrip of one
width coupled to a buried microstrip of a different width, with the buried trace below and
considerably off to the side of the outer-layer trace.) This is an undesirable condition, however,
because multiple, widely varying propagation speeds cause signal distortion, as one portion of
the signal races ahead of the other(s).

For convenience, the propagation-speeds list displays velocities not only in m/s, but also as a
fraction of the speed of light. For example, a value of "0.4822c" means 48.22% of the speed of
light.

Tip: A misconception about propagation velocity on a transmission line is that electrons

in the conductor are traveling along the line at the propagation velocity. This is absolutely
not true! Electrons in a conductor spend almost all of their time randomly colliding with
atoms in the conductor lattice; the mean time between collisions is on the order of 10
femtoseconds (1/100th of a ps).

As a result, conduction electrons have only a relatively tiny average forward velocity in the
presence of a driving voltage. A typical electron "drift velocity" in a conductor is on the order of
1 foot/hour. Instead, what moves at the transmission line’s propagation velocity is the
electromagnetic wave that constitutes the actual signal on the line. Indeed, this wave is what you
measure in the lab with an oscilloscope: a voltage waveform, which is really a measure of the
electric field associated with the traveling electromagnetic wave.

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Percentage of Energy Matrix for Multiple-Speed Coupling

Regions Only
If the coupling region supports multiple propagation speeds, this matrix gives, for each net in
the region, the percentage of signal energy that travels at each speed. In the matrix, each column
represents a line (for example, a net’s trace); reading down the column shows how much of the
signal energy in that line travels in each of the propagation modes listed in the propagation-
speeds list. The percentages in each column add to approximately 100%, to fully account for the
energy on each net.

The values in this matrix are usually only of limited interest, unless the matrix shows a very
uneven breakdown in energy sharing between propagation modes. For example, for certain
highly asymmetric (and unusual) geometries, it is possible to have certain nets carrying most of
their energy in one mode, while others carry a more even mixture of modes. If the velocities
between modes differ significantly, this uneven distribution could lead to noticeable skew
between signals on the nets.

Impedance and Termination Summary for Two-Line Coupling

Regions Only
For the special case of a two-line coupling region, the field-solver numerical results report gives
additional information about specific termination options. Table 29-10 summarizes the
additional data.

It is this section that reports the differential impedance of a pair of coupled traces.

Table 29-10. Termination Recommendations for Two Coupled Transmission-

Lines
Termination Type Description
differential This is the proper line-to-line resistor to use if the
two nets are being driven differentially, i.e., with
equal-but-opposite signals. Will not terminate
common-mode signals at all.
common-mode This is the proper line-to-ground resistor to use for
each line if the two nets are being driven
identically, i.e., with equal signals of the same
polarity. Not very useful for signals that
sometimes switch together and sometimes
oppositely, unless crosstalk is primarily of concern
when they switch together.
line-to-ground This is the best line-to-ground resistor to use for
each line if the signals on the transmission lines
are completely unrelated. Will not perfectly
terminate the line, but is a good single-component
"compromise" value.

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Running the Field Solver in BoardSim

Table 29-10. Termination Recommendations for Two Coupled Transmission-

Lines (cont.)
optimal termination Describes the theoretically optimal resistor-array
termination; consists of a line-to-line resistor plus
two line-to-ground resistors. Same as the values
given in the Optimal Terminator-Resistor Array
matrix. Successfully terminates differential,
common-mode, or mixed signals, but may violate
DC-bias conditions on the lines.

Generating a Report of the Field Solver Numerical

Results
Much of the field solver’s output data comes in the form of matrices or lists of numerical
parameters (e.g., impedance, propagation speed, etc.). All of this data can be viewed in a report
file, which in turn can be printed or saved for future reference.

To create a text report of the field solver’s numerical results:

1. If you are using LineSim, open the Edit Transmission Line Dialog Box - Transmission-
Line Type Tab by doing one of the following over a transmission line that is in the
coupling region whose field lines you want to see:
• If you are using the free-form schematic editor, double-click.
• If you are using the cell-based schematic editor, right-click.
2. If you are using BoardSim, right-click over a trace segment whose field lines you want
to see, and then click View Field-Solver Output.
3. If needed, click the Field Solver tab in the Field Solver and Lossy dialog box. A large
graphical view of the coupling region appears.
4. In the Numerical Results area, click View.
5. If the View button is unavailable (because the coupling region has changed and the field
solver has not yet been run), click Start and then click View.
A report file is created, and the HyperLynx File Editor opens on it. You can scroll up and down
in the editor to see the report’s data, and print it if desired. By default, the report is written into a
file named <Coupling_Region_Name>.TXT, where <Coupling_Region_Name> is the name of
the coupling region for which the data are being reported. The file is located in the same
directory as your .TLN or .FFS schematic file.

Preserving Numerical Results Files

If you typically leave your coupling regions with default names (e.g., "Coupling0001,"
"Coupling0002," etc.), your numerical-results files will likely be overwritten frequently.

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Running the Field Solver in BoardSim

Therefore, if you want to preserve field-solver data, save the results file under a unique name by
renaming the coupling region. For details on editing coupling region names, see “Edit
Transmission Line Dialog Box - Edit Coupling Regions Tab” on page 1562.

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 Chapter 30
Back-Annotating Board Changes

After analyzing your board with BoardSim, you may have made several changes that you want
to pass back to your board layout or schematic capture program (i.e. PCB CAD program).
BoardSim's automatic back annotation feature helps to reduce the back annotation effort and to
ensure that correct components and values are used for future analysis and for board production.

BoardSim's back annotation feature allows you to pass back several types of board changes to
your PCB CAD program. For example, you can back annotate changed passive component
values, IC model assignments, and new terminators (i.e., Quick Terminators).

The back annotation data are written to an ASCII ECO (i.e. engineering change order) file that
is formatted for your PCB CAD program. ASCII ECO files can be generated for the PADS
Layout, PADS Logic, and Mentor Graphics DxDesigner programs.

Optionally, the back annotation data may be dynamically transferred to a running copy of your
PCB CAD program. The PCB CAD program's board viewing screen is quickly updated to
reflect the changes specified by the back annotation data. Dynamic back annotation is supported
for the PADS Layout and PADS Logic programs.

Restriction: The back annotation feature is not available when a MultiBoard project is loaded
into BoardSim.

This topic contains the following:

• “An Example Workflow” on page 1254

• “ASCII ECO Data File” on page 1255
• “Dynamic Back Annotation Option” on page 1255
• “Setting Passive Component Attributes After Back Annotation” on page 1256
• “Preventing Redundant Quick Terminator Components” on page 1257
• “Generating Back Annotation Data” on page 1257
• “Back Annotation Dialog Boxes” on page 1259

Related Topics
“Terminating Nets” on page 935

“Generate ECO Back-Annotation File-Data Dialog Box” on page 1260

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An Example Workflow

“ASCII ECO Data File” on page 1255

“Dynamic Back Annotation Option” on page 1255

An Example Workflow
This section describes just one of the possible workflow scenarios to illustrate how you might
use BoardSim's back annotation feature. While the following example describes a workflow
using PADS Layout, BoardSim can also generate ECO data for PADS Logic and DxDesigner.

Example Back Annotation Flow Using BoardSim and

PADS Layout
1. Transfer a placed, but not yet routed, design from PADS Layout to BoardSim.
2. Make the following board changes based on BoardSim's signal integrity results and
Terminator Wizard recommendations:
• Assign IC models in the .REF file
• Modify existing terminator values
• Add new terminators (for example, Quick Terminators)
• Add a power-supply net
3. Generate ECO data and dynamically pass them back to a running copy of PADS Layout.
The ASCII ECO file will also be written.
4. Place and route the Quick Terminator components in PADS Layout.
5. Optionally, transfer the design to BoardSim to verify the actual placement of the Quick
Terminator components will meet your signal integrity goals.
If necessary, modify the terminator values, generate new ECO data, and transfer them to
PADS Layout.
To avoid redundant Quick Terminator components, create a new board file before
loading the board into BoardSim. When loading the new board file, clear the Quick
Terminators check box in the Restore Session Edits dialog box.
6. Route the design with PADS Layout.
7. Create a new board file.
8. Transfer the design to BoardSim and verify signal integrity and timing after routing.
To avoid redundant Quick Terminator components, clear the Quick Terminators check
box in the Restore Session Edits dialog box when loading the board.
9. Perform additional iterations if needed.

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ASCII ECO Data File

10. Once back annotation is complete, you may need to update the attributes for changed
passive components within your PCB CAD program environment to ensure the correct
parts will be listed in the BOM (that is, bill of materials).

ASCII ECO Data File

BoardSim writes out the ECO data to an ASCII file that has been formatted for your PCB CAD
program. To generate the ECO file, see “Generate ECO Back-Annotation File-Data Dialog
Box” on page 1260.

When you choose to transfer the ECO data dynamically, the ASCII ECO file is also written and
serves to document the board changes you made in BoardSim. See “Dynamic Back Annotation
Option” on page 1255.

The default ASCII ECO file is based on your board file name. See Table 30-1 for details. The
default PADS Layout and PADS Logic ECO file name is foo_HYP.eco. The "_HYP" string
prevents BoardSim from accidentally overwriting PADS Layout and PADS Logic ECO files.

You can also type in a file name to override the default ECO file name, see “Save ECO Back-
Annotation File Dialog Box” on page 1262.

Table 30-1 lists the default ASCII ECO file names for the various PCB CAD programs.
Table 30-1. Default ASCII ECO File Names
Target PCB CAD Board File Name ECO File Name
Program
PADS Layout foo.hyp foo_HYP.eco
PADS Logic foo.hyp foo_HYP.eco
DxDesigner foo.hyp foo.eco (plus foo.asc)

Dynamic Back Annotation Option

BoardSim can dynamically transfer the ECO data to your running PCB CAD program. When
the dynamic ECO data transfer is complete, your PCB CAD program's board viewing screen is
refreshed and you may view the back annotation changes. This flow allows you to continue
board design work without having to read the ASCII ECO file into your PCB CAD program.

When you choose to transfer the ECO data dynamically, the ASCII ECO file is also written and
serves to document the board changes you made in BoardSim.

To enable the dynamic ECO data transfer, see the detailed instructions in the “Generate ECO
Back-Annotation File-Data Dialog Box” on page 1260 topic.

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Setting Passive Component Attributes After Back Annotation

Dynamic Back Annotation Requirements

The following sections describe the various requirements to dynamically run back annotation.

Programs are Running on the Same Computer

BoardSim and your PCB CAD program must be running on the same computer for dynamic
back annotation to work.

Exactly One Copy of Your PCB CAD Program is Running

BoardSim can dynamically back annotate to one, and only one, copy of your PCB CAD
program. If the wrong quantity of PCB CAD programs are running on your computer (i.e., 0, 2,
3, etc.), BoardSim will warn you of the condition and advise you on how to correct it.

• If your PCB CAD program is not running, BoardSim will instruct to you to start the
PCB CAD program and load your board before continuing.
• If two or more copies of your PCB CAD program are running, BoardSim will not
attempt to back annotate dynamically and will instruct you to manually load the ASCII
ECO file into your PCB CAD program. The reason is that BoardSim cannot determine
which copy, if any, of the program has the correct board in memory.

DxDesigner Users Need PCBBACK if not Using PADS Layout or

PADS Logic
If you do not have PADS Layout or PADS Logic installed on the computer, the PCBBACK
program is required for BoardSim to back annotate to DxDesigner.

Setting Passive Component Attributes After

Back Annotation
Once back annotation is complete, you may need to update the attributes for changed passive
components within your PCB CAD program environment to ensure the correct parts will be
listed in the BOM (that is, bill of materials).

Quick Terminators
BoardSim assigns a single part type to all new resistor (e.g., RES0805) and capacitor (e.g.,
CAP0805) components back annotated to your PCB CAD program. When multiple component
types are required, back annotation's limit of one part type per component type will cause at
least one of the components to have the wrong part type. In this case, use the PCB CAD
program to correct the part type attribute.

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Preventing Redundant Quick Terminator Components

You can specify the resistor and capacitor part types used for back annotation in the Options For
New Terminators (i.e., Quick Terminators) dialog box.

See also: “Options for New Terminators - Quick Terminators - Dialog Box” on page 1261

Changed Passive Component Value

When a change of value is back annotated, only the value attribute is changed. A new part type,
if needed to implement the value change, is not back annotated.

After back annotation is complete, update the attributes for the changed resistor and capacitor
components within the PCB CAD program environment. This may involve changing the part
type or other attributes.

Preventing Redundant Quick Terminator

Components
BoardSim's "Quick Terminator" feature allows you to add to your board virtual terminating
components that are not actually present in the board's layout. This capability allows you to
experiment with new terminations to improve signal integrity, crosstalk or EMC characteristics.

See also: “Optimizing Termination with the Terminator Wizard” on page 945

Quick Terminator components are stored in the .BUD file and are present in the back annotation
data. After adding Quick Terminator components to your board using your PCB CAD
program's back annotation flow, the next board file you create will contain real terminating
components in place of the virtual ones created by Quick Terminator. Now you have potentially
redundant terminating components in your design; the real ones in the board file and the virtual
ones in the .BUD file.

To prevent redundant terminating components when reading in the new board file, clear the
Quick Terminator check box in the Restore Session Edits dialog box. BoardSim will then ignore
the new components described in the .BUD file.

Generating Back Annotation Data

BoardSim has a Wizard-like series of dialog boxes to guide you through the back annotation
process.

See also: “Back Annotation Dialog Boxes” on page 1259

To generate back annotation data:

1. Load your board into BoardSim and make the desired changes.

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Generating Back Annotation Data

Alternative: Load your board into BoardSim and restore the changes saved from your
last BoardSim session (i.e., from the .BUD file).
2. Select Export > Generate ECO Back-Annotation File. The Generate ECO Back-
Annotation File/Data dialog box opens.
3. In the Target Program list, select the PCB CAD program.
4. Optionally, you may send the ECO data dynamically to a running copy of the target
program by selecting the If target program is running… check box.
Restriction: The check box is unavailable when BoardSim does not support dynamic
ECO data transfer for the selected target program.
5. In the Information To Back Annotate area, select the changes that you want to back
annotate.
If you select the New Terminators check box, the Finish button changes into a Next
button and the Options For New Terminators (that is, Quick Terminators) dialog box
will open next. This is reversible; the Next button becomes a Finish button when you
clear the check box.
When you click the Finish or Next button (i.e. whichever is present), BoardSim reads
the KEY statement in the .HYP file to learn which program was used to generate the
.HYP file. Then it compares the Target Program you selected to the KEY statement's
value. If they do not match, BoardSim warns you about the mismatch and asks whether
to continue anyway.
Click No to return to the Generate Back-Annotation File/Data dialog box and change the
Target Program choice.
Click Yes to proceed with the current Target Program choice. The main goal of this
check is to make sure the target program can use the back annotation data written by
BoardSim.
6. If the Finish button is displayed, skip ahead to step 15.
7. Click the Next button. The Options For New Terminators (that is, Quick Terminators)
dialog box opens.
8. Review the values in the Resistors area.
9. Select or type the desired reference designator prefix in the Use Prefix list.
If you type in a new prefix, it will be automatically added to BoardSim's reference
designator map. If you type in a prefix already assigned to another component type (e.g.,
IC), you will be prompted to enter a different value.
See also: “Edit Reference Designator Mappings Dialog Box” on page 1553

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Back Annotation Dialog Boxes

10. Select the Start with number check box and type in the desired starting reference
designator number. New components are numbered using the specified starting number,
unless that number has already been used.
Alternative: Clear the Start with number check box. New components are numbered
using the smallest number not currently used on the board for resistors or capacitors (as
needed).
11. In the Part Type or Symbol boxes, type new values. This value will be used for all the
new components created by BoardSim.
12. Repeat steps 10-11 for the Capacitors area in the Options For New Terminators (i.e.,
Quick Terminators) dialog box.
13. To return to the Generate ECO Back Annotation File/Data dialog box, click Back.
14. Click Finish. The Save ECO Back-Annotation File Dialog Box opens.
15. Select or type the file name for the ECO file to be created and click Save. The Save ECO
Back Annotation File dialog box closes and the ASCII ECO file is written.
If you have chosen to send the ECO data to your running PCB CAD program, the data
are transferred to the target program now.
See also: “Dynamic Back Annotation Option” on page 1255
It is highly recommended that you immediately generate a new board file based on the
back annotation data that you have just transferred to your PCB CAD program.
Using the new board file, and clearing the Quick Terminators check box in the Restore Session
Edits dialog box when loading the new board file, ensures that you do not duplicate Quick
Terminator components. Generating a new board file also ensures that you perform analysis
using the latest layout and component selections.

See also: “Preventing Redundant Quick Terminator Components” on page 1257

Setting Passive Component Attributes within the PCB

CAD Program
When BoardSim back annotates a changed passive component, only the value is passed back to
the PCB CAD program. You will likely need to change the passive component's part type or
symbol within the PCB CAD system.

See also: “Setting Passive Component Attributes After Back Annotation” on page 1256

Back Annotation Dialog Boxes

BoardSim has a Wizard-like series of dialog boxes to guide you through the ECO data
generation process. When you have completed your entries for the dialog boxes, BoardSim will

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Back Annotation Dialog Boxes

generate the ECO data for your PCB CAD program. See “Generating Back Annotation Data”
on page 1257 for the steps to generate back annotation data.

The dialog boxes allow you to choose:

• The types of changes that you want to back annotate

• Whether to dynamically transfer back annotation data to your running PCB CAD
program
• The attributes for Quick Terminator components (e.g., reference designator prefix,
generic part type)
• The ASCII ECO file name, if you don't want to use the default name

Related Topics
“Generate ECO Back-Annotation File-Data Dialog Box” on page 1260

“Options for New Terminators - Quick Terminators - Dialog Box” on page 1261

“Save ECO Back-Annotation File Dialog Box” on page 1262

Generate ECO Back-Annotation File-Data Dialog Box

This dialog box allows you to choose the types of changes that you want to back annotate to
your PCB CAD program, and to indicate whether you want to dynamically transfer the back
annotation to your PCB CAD program.

Choosing the Dynamic Back Annotation Option

The back annotation data can be dynamically transferred to your PCB CAD program by
selecting the If Target Program Is Running, Automatically Send ECO Information To It check
box. This check box will be dimmed if you select a target program to which BoardSim cannot
dynamically transfer back annotation data.

Changed Values for Existing Passive Components

Resistor, capacitor, or inductor values that you have interactively changed in BoardSim can be
back annotated to your PCB CAD program by selecting the Changed Values For Existing
Passive Components (Cs, Rs, etc.) check box.

Restriction: Resistor or capacitor values that you specify in the .REF or .QPL file are not back
annotated.

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Back Annotation Dialog Boxes

Quick Terminators
Quick Terminator components (i.e., resistors or capacitors) that you have added using
BoardSim's Quick Terminators feature can be back annotated to your PCB CAD system.

See also: “Optimizing Termination with the Terminator Wizard” on page 945

IC Models
IC models assigned only by the .REF automapping file can be back annotated to your PCB
CAD system. By contrast, IC models assigned by .QPL files or by interactive selections cannot
be back annotated.

See also: “Selecting Models and Values for Entire Components” on page 296

Ferrite bead models cannot be back annotated, primarily because they cannot be written to a
.HYP file.

Back annotation support for IC and ferrite bead model assignments:

Table 30-2. Back Annotation Support for IC and Ferrite Bead Models
Component Type and Model Assignment Back Annotated?
Method
IC model assignments using .REF file Yes
IC model assignments using .QPL file No
IC model assignments using interactive selection No
Ferrite bead model assignments No

Power-Supply Net Voltage and Identification

Power-supply net voltage changes, and nets that have been added or subtracted from the power-
supply nets list, can be back annotated to your PCB CAD program.

See also: “Editing Power-Supply Nets” on page 281

Related Topics
“Back-Annotating Board Changes” on page 1253

Options for New Terminators - Quick Terminators - Dialog

Box
When BoardSim creates a Quick Terminator component, it only specifies the component's value
and its electrical connectivity to other components on your board. While these properties are

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sufficient for analysis, they are insufficient for back annotation. At a minimum, PCB CAD
systems also require the back annotation data to contain the reference designator and part type
for each new terminator component.

The Options For New Terminators (i.e., Quick Terminators) dialog box allows you to specify
the reference designator prefix and part type for new resistor or capacitor components.

Tip: You will likely need to set additional attributes for Quick Terminator components
from within your PCB CAD program. See “Setting Passive Component Attributes After
Back Annotation” on page 1256.

This dialog box opens only when you select the New Terminators check box in the Generate
ECO Back-Annotation File/Data dialog box. See “Generate ECO Back-Annotation File-Data
Dialog Box” on page 1260.

Save ECO Back-Annotation File Dialog Box

The Save ECO Back-Annotation File dialog box allows you to override the default ECO file
name. The default ECO file name is based on the board file name. See Table 30-1 for the default
ECO file names.

This dialog box is the last dialog box in the Wizard-like series of dialog boxes for back
annotation. When you click its Save button, the back annotation data are generated.

Once the Save ECO Back-Annotation File dialog box opens, you cannot return to the prior
dialog boxes. Clicking Cancel exits the ECO generation process. However, the values you have
entered will persist and be present in the prior dialog boxes the next time you open them.

DxDesigner ASC File

DxDesigner requires the .ASC file (e.g. foo.asc) for back annotation to function; if the .ASC file
is absent, back annotation will fail. BoardSim automatically generates the .ASC file when you
select DxDesigner as the target program in the Generate ECO Back-Annotation File/Data dialog
box.

Related Topics
“Back-Annotating Board Changes” on page 1253

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Chapter 31
Concepts and Reference Guide

The information contained in this guide is part of the documentation for HyperLynx.

This topic contains the following:

• “Supported SI Models and Simulators” on page 1264

• “File Specifications” on page 1267
• “Application Notes” on page 1336
• “Technical Background on Crosstalk and Differential Signaling” on page 1348
• “About Transmission Planes” on page 1373
• “Jitter Distribution Types” on page 1379
• “Miscellaneous Reference Information” on page 1388

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Supported SI Models and Simulators

This topic lists the supported models and simulators for different types of SI simulation with
HyperLynx.

Restrictions:

• SI-SPICE automatically installs with HyperLynx and requires the DDRx or GHz license
bundle.
• Mentor Graphics Eldo/ADMS and Synopsys HSPICE require separate installation and
licensing.
• Simulating S-parameters requires the GHz license bundle.
Table 31-1 shows the models and simulators that interactive simulation with the oscilloscope
and sweep simulation support. See “Simulating Signal Integrity with the Oscilloscope” on
page 533 and “Simulating Signal Integrity with Sweeps” on page 601.
Table 31-1. Oscilloscope and Sweep Manager Simulations
Simulators
Model Types Native Eldo/ SI-SPICE2 HSPICE
HyperLynx ADMS1
MOD Yes -- -- --
IBIS Yes Yes Yes Yes
EBD Yes Yes Yes Yes
Series MOSFET -- Yes Yes3 Yes
IBIS-AMI -- -- -- --
Eldo -- Yes Yes2 Yes4
Encrypted Eldo -- Yes -- --
HSPICE -- Yes Yes2 Yes
Encrypted HSPICE -- -- -- Yes
S-parameter -- Yes Yes Yes

1. Pre-compiled VHDL-AMS models are supported by ADMS in HyperLynx when they are embedded in a
top-level SPICE netlist, which is typically provided by a Mentor Graphics device kit. HyperLynx cannot
dynamically compile VHDL-AMS models that you create.
2. The SI-SPICE simulator supports only passive components, passive S-parameters, and ideal sources. It
does not support diodes and transistor models.
3. HyperLynx switches to the SI-SPICE simulator for all series MOSFET model simulations.
4. The syntax for some object types is different for HPSICE and Eldo. Both Eldo and HSPICE support
standard, Berkeley SPICE syntax.

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Table 31-2 shows the models and simulators that generic batch simulation supports. See
“Simulating SI for Entire Boards or Multiple Nets”.

Table 31-2. Generic Batch Simulation (Batch-Mode Wizard)

Simulators
Model Types Native Eldo/ SI-SPICE1 HSPICE
HyperLynx ADMS
MOD Yes -- -- --
IBIS Yes -- -- --
EBD Yes -- -- --
Series MOSFET Yes -- -- --
IBIS-AMI -- -- -- --
Eldo -- -- -- --
Encrypted Eldo -- -- -- --
HSPICE -- -- -- --
Encrypted HSPICE -- -- -- --
S-parameter -- -- -- --

1. The SI-SPICE simulator supports only passive components, passive S-parameters, and ideal sources. It
does not support diodes and transistor models.

Table 31-3 shows the models and simulators that the DDRx Wizard supports. See “Simulating
DDRx Memory Interfaces”.

Table 31-3. DDRx Wizard Simulations

Simulators
Model Types Native Eldo/ SI-SPICE1 HSPICE
HyperLynx ADMS
MOD -- -- -- --
3
IBIS Yes -- Yes --
2 3
EBD Yes -- Yes --
Series MOSFET -- -- -- --
IBIS-AMI -- -- -- --
1, 3
Eldo -- -- Yes --
Encrypted Eldo -- -- -- --
1, 3
HSPICE -- -- Yes --

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Table 31-3. DDRx Wizard Simulations (cont.)

Simulators
Model Types Native Eldo/ SI-SPICE1 HSPICE
HyperLynx ADMS
Encrypted HSPICE -- -- -- --
3
S-parameter -- -- Yes --
1. The SI-SPICE simulator supports only passive components, passive S-parameters, and ideal sources. It
does not support diodes and transistor models.
2. EBD models are supported in DDRx Wizard only in HyperLynx version 8.1 and higher.
3. When the DDRx Wizard detects a SPICE or S-Parameter model for a connector, it automatically switches
to the SI-SPICE simulator. Note that simulating S-parameter models requires the GHz license bundle.

Table 31-4 shows the models and simulators that the FastEye channel analyzer supports. See
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629.
Table 31-4. FastEye Channel Analyzer Simulations
Simulators
Model Types Native Eldo/ SI-SPICE1 HSPICE
HyperLynx ADMS
MOD Yes -- -- --
IBIS Yes Yes -- Yes
EBD Yes Yes -- Yes
Series MOSFET -- Yes -- Yes
IBIS-AMI -- -- -- --
Eldo -- Yes -- Yes
Encrypted Eldo -- Yes -- --
HSPICE -- Yes -- Yes
Encrypted HSPICE -- -- -- Yes
S-parameter -- Yes -- Yes

1. The SI-SPICE simulator supports only passive components, passive S-parameters, and ideal sources. It
does not support diodes and transistor models.

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Table 31-5 shows the models and simulators that the IBIS-AMI channel analyzer supports. See
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611.
Table 31-5. IBIS-AMI Channel Analyzer Simulations
Simulators
Model Types Native Eldo/ SI-SPICE1 HSPICE
HyperLynx ADMS
MOD Yes -- -- --
IBIS Yes Yes -- Yes
EBD Yes Yes -- Yes
Series MOSFET -- Yes -- Yes
IBIS-AMI Yes Yes --
Eldo -- Yes -- Yes
Encrypted Eldo -- Yes -- --
HSPICE -- Yes -- Yes
Encrypted HSPICE -- -- -- Yes
S-parameter -- Yes -- Yes

1. The SI-SPICE simulator supports only passive components, passive S-parameters, and ideal sources. It
does not support diodes and transistor models.

Related Topics
“Preferences Dialog Box - Circuit Simulators Tab” on page 1808

File Specifications
This topic contains the following:

• “FBD File Specification” on page 1268

• “HyperLynx Timing Model Format” on page 1270
• “HyperLynx DDRx Wizard Setup File Format” on page 1307
• “IBIS Specification” on page 1327
• “PAK File Specification” on page 1327
• “SLM File Specification” on page 1334

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FBD File Specification

This document contains a brief specification for the HyperLynx ferrite-bead-modeling (.FBD)
format. The .FBD format is used to create the files BSW.FBD and USER.FBD, which together
define the ferrite-bead models available to BoardSim.

********************** Ferrite Bead Models **********************

* Copyright 1996, HyperLynx, Inc. (now Mentor Graphics)
*
* Description of format:
* ----------------------
* {MANUFACTURER=<name>}
* - Sets the manufacturer name for all ensuing beads
* - <name> is limited to 12 characters; truncated if longer
* - Applies until superseded by another MANUFACTURER record
* - Must be a MANUFACTURER record before the first BEAD
*
* Example:
* {MANUFACTURER=DALE}
* ---------------------
* {BEAD=<name>
* (R_DC=<resistance>)
* (PT1=<freq>, <impedance>)
* (PT2=<freq>, <impedance>)
* (PT3=<freq>, <impedance>)
* }
* - BEAD=<name> names the bead model; <name> is limited to 30
* characters
* - R_DC=<resistance> gives the bead's DC resistance
* - PTx=<freq>, <impedance> gives a frequency/impedance pair
* for the bead
* - <freq> numbers can be scaled by a trailing 'M' or 'MHZ' to
* give values in MegaHertz
* - Exactly 3 freq/Z pairs are required, as follows:
* - The first point should be at (10-20)% of the nominal
* impedance (nominal impedance is usually at 100 MHz)
* - The last point should be the highest frequency shown in
* the impedance vs. frequency graph for the bead
* - If the resonant point is available, it should be PT2.
* If the resonant point is not available, the 2nd point
* should generally be the impedance at the nominal bead
* impedance indicated by the vendor (usually 100 MHz).
* If the nominal impedance and frequency are not specified,
* then the 2nd point should be taken from the mid-point
* of the Z-vs-freq graph for the bead
*
* WARNING: To provide accurate modeling, the data must following
* the above rules.
*
* For example:
* {BEAD=ILB-1206-19
* (R_DC=0.035)
* (PT1=6.0MHZ, 4.0)
* (PT2=100.0MHZ,19.0)
* (PT3=500.0MHZ,27.0)
* }

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HyperLynx Timing Model Format

HyperLynx timing models specify net-to-net timing requirements for signals in the DDRx
memory interface. DDRx batch simulation reports net pairs that do not satisfy net-to-net timing
requirements contained in HyperLynx timing models.

HyperLynx timing models are based on the Verilog programming language, and contain a few
extensions added to facilitate the specification of timing models.

HyperLynx ships with timing model files for the supported DDRx memory interfaces. These
files may help you learn about the formatting and application of the timing models used by
DDRx simulation. These files are located in the Libs folder, such as
C:\MentorGraphics\<release>\SDD_HOME\hyperlynx\Libs.

Caution
Do not modify the default timing models (.v) unless advised to do by Mentor Graphics
personnel.

While DRAM timing values are often the same for DRAM modules from different vendors,
memory controller timing values are more likely to be different for memory controller ICs from
different vendors. HyperLynx provides a wizard to help you create controller timing models.
HyperLynx also provides a timing model editor to help you edit memory and controller timing
models. See “Creating and Editing HyperLynx DDRx Timing Models“.

Note
If you opened this topic from the Help menu in the HyperLynx Timing Model Editor,
please note that no Help is available for this application.

This topic contains the following:

• “About HyperLynx Timing Models” on page 1270

• “General Structure - HyperLynx Timing Models” on page 1271
• “Slew Rate Derating Tables” on page 1274
• “Detailed Syntax - HyperLynx Timing Models” on page 1275

Related Topics
“Simulating DDRx Memory Interfaces”

About HyperLynx Timing Models

HyperLynx uses a number of modeling techniques to simulate, analyze, and report the electrical
characteristics of signal paths of interest in a circuit. In the DDRx analysis flow, IBIS models

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are used to model the various signal I/O characteristics for the memory controller and DDRx
DRAM devices.

Timing analysis generally involves measuring and verifying the time relationship between a
pair of signals as they enter or exit a device. Existing forms of SI-related models, like IBIS, are
inadequate for performing timing analysis because they are not designed for that purpose. The
set of timing constraints and parameters that comprise a timing model for a component must
reside in a separate file from the other types of modeling files used in HyperLynx.

HyperLynx timing models are based on the Verilog programming language, and contain a few
extensions added to facilitate the specification of timing models. This origin provides the
following benefits:

• Verilog is easy to learn and easy to use. It is similar to the C programming language.
Many developers will already be familiar with Verilog, or can easily learn it.
• Verilog already provides most of the syntactical constructions needed to specify timing
values and timing verification functions.
Verilog files are ASCII files, which can be manually edited with a text editor.

The HyperLynx timing model file syntax derived from Verilog is, with just a few exceptions, a
proper subset of Verilog file syntax. Verilog file syntax is described in IEEE Standard 1364-
2005, and in numerous books written about the subject.

Note
Verilog itself has evolved into SystemVerilog, which is now IEEE Std. P1800-2005, but
SystemVerilog is a superset of the more widely-used legacy Verilog (last formalized as
IEEE Std. 1364-2005), so the following discussions still apply.

General Structure - HyperLynx Timing Models

This section illustrates the general structure of a basic HyperLynx timing model file, showing
how the various Verilog-defined constructions and HyperLynx timing model-introduced
extensions might be used to define a timing model. Although the various Verilog language
details discussed in the sections that follow may seem complex, the actual timing model
specified using them is typically fairly simple.

The essence of a HyperLynx timing model consists of a single, top-level module, defining the
interface ports to the outside world. In fact, there are currently no provisions in the HyperLynx
timing model compiler to handle anything but a single top-level module. This module would
contain a number of parameters, specifying the timing values, and a specify block defining the
timing checks and delay relationships between various module ports.

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The following statements establish that time values in the file are measured in picoseconds and
that simulations would be run with a time precision rounded to a resolution of one picosecond.
These are the HyperLynx timing model compiler default values.

// Establishes time scale scale, should always be 1 ps / 1 ps

`timescale 1 ps / 1 ps;

The following statement declares the top-level module, lists the interface ports used in the
model, and lists the directional characteristics of each interface port.

// top-level module definition and interface ports

// ...the port names are HyperLynx standard names...do not change
module ddr2_dram (
input ck,
input addr_cmd,
input ctl,
input dm,
inout dq,
inout dqs
);

The following statements specify the timing parameter values for the delays and the constraint
checks declared later in the module. For brevity, timing parameters for several speed grades are
omitted.

/***********************************************************************
* HyperLynx DDR2 DRAM Timing Model Parameters
*
* A DRAM2 timing model should define the following parameters:
*
* All cycles:
* tIS Address, Command, Control Input Setup Time to CK (pS)
* tIH Address, Command, Control Input Hold Time to CK (pS)
*
* Write cycles:
* tDQSS Rising clock edge to DQS/DQS# latching transition (* tCK)
* tDSS DQS falling edge to CK rising (setup time) (* tCK)
* tDSH DQS falling edge from CKrising (setup time) (* tCK)
* tDS DQ and DM input setup time relative to DQS (pS)
* tDH DQ and DM input hold time relative to DQS (pS)
*
* Read cycles
* tDQSCK DQS output access time from CK/CK# (pS)
* tDQSQ DQS-DQ maximum skew, DQS to last DQ valid, per group, per access
(pS)
* tQHS Data hold skew factor (pS)
*
************************************************************************/

// Timing parameters by speed grade

// The speed grade identifier is set by the DDRx wizard at compile time.
`ifdef DDR2_1066
parameter tIS = 125;
parameter tIH = 200;
parameter tDQSS = 0.25;

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parameter tDSS = 0.20;

parameter tDSH = 0.20;
parameter tDS = 0;
parameter tDH = 75;
parameter tDQSCK = 300;
parameter tDQSQ = 175;
parameter tQHS = 250;
`elsif DDR2_800
parameter tIS = 175;
parameter tIH = 250;
parameter tDQSS = 0.25;
parameter tDSS = 0.20;
parameter tDSH = 0.20;
parameter tDS = 50;
parameter tDH = 125;
parameter tDQSCK = 350;
parameter tDQSQ = 200;
parameter tQHS = 300;

// This example omits statements for other speed grades ...

`else `define DDR2_400

parameter tIS = 350;
parameter tIH = 475;
parameter tDQSS = 0.25;
parameter tDSS = 0.20;
parameter tDSH = 0.20;
parameter tDS = 150;
parameter tDH = 275;
parameter tDQSCK = 500;
parameter tDQSQ = 350;
parameter tQHS = 450;
`endif

The following statements specify the timing checks involved in DRAM write and read
operations, as well as the general timing checks performed on the address bus during all data
transfer cycles.

The “edge” specifiers are ignored, but they are useful for reference.

/***********************************************************************
* Timing relationships
***********************************************************************/
specify

// Address/Command/Control S/H checks

$setuphold(posedge ck, addr_cmd, tIS, tIH);
$setuphold(posedge ck, ctl, tIS, tIH);

// Data Write S/H checks

$setuphold(dqs, dq, tDS, tDH);
$setuphold(dqs, dm, tDS, tDH);

// ...Clock to DQS skew (write cycles only)

// $fullskew(ref, data, max_ref_to_data, max_data_to_ref);
$fullskew(posedge ck, posedge dqs, tDQSS1, tDQSS1);

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$setuphold(posedge ck, negedge dqs, tDSS1, tDSH1);

// Data Read Output delays

$delay(ck, dqs, -tDQSCK, tDQSCK);
$delay(dqs, dq, -tQHS, tDQSQ);

endspecify // closes specify block

The following statement ends the module definition, and also effectively ends the timing model.

endmodule // closes module definition

Slew Rate Derating Tables

Figure 31-1 on page 1274 shows the basic syntax for derating tables in a timing model. The
example shows one table for the 667 MT/s (megatransfers per second) speed grade and another
table for other speed grades.

Table 31-14 on page 1302 provides detailed syntax for creating derating tables. “DDR2_667” in
Figure 31-1 is one of several predefined speed grade designators supported by the DDRx timing
wizard file. For more information about speed grade designators, see Table 31-9 on page 1291.

Figure 31-1. Slew Rate Derating Table - Syntax

Figure 31-2 on page 1275 is taken from the Read Setup Derating page in the HyperLynx
Timing Model Wizard, and shows the same data as the 667 MT/s (megatransfers per second)

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speed grade portion of Figure 31-1 on page 1274. For information about using the wizard, see
“Creating and Editing HyperLynx DDRx Timing Models“.

Figure 31-2. Slew Rate Derating Table - Controller Wizard Page

Related Topics
“Detailed Syntax - HyperLynx Timing Models” on page 1275

Detailed Syntax - HyperLynx Timing Models

In this section, HLTM represents “HyperLynx timing model”.

7.1 Timing Model Overview

Verilog files are ASCII files, which can be easily edited manually using a standard text editor.
The HLTM file syntax derived from Verilog is, with just a few exceptions, a proper subset of
Verilog file syntax. Verilog file syntax is described in IEEE Standard 1364-2005, and in
numerous books written about the subject (Verilog itself has evolved into SystemVerilog,
which is now IEEE Std P1800-2005, but SystemVerilog is a superset of the more widely used
“legacy” Verilog last formalized as IEEE Std. 1364-2005, so the following discussions still
apply). One goal for well-written HLTM files is that they may be compiled with standard
Verilog tools; conversely, the HLTM file compiler recognizes only the subset of Verilog syntax
needed for timing, and will typically not be able to compile most regular Verilog files.

Many designs using Verilog files evolve to be quite complex. HLTM files will typically be
fairly short and simple. This document will focus on the subset of standard Verilog syntax
recognized by the HLTM compiler, and the few extensions added to facilitate the specification
of timing models. Unless a specific Verilog structure is mentioned in this document, it should be
assumed that the HLTM compiler does not support it.

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7.2 Lexical Conventions

In general, the language elements and syntactical conventions that comprise a HLTM file are
identical to those found in the Verilog language. Rather than repeating the Verilog standard,
only brief descriptions of these items follow. More detailed descriptions can be found in the
Verilog IEEE Std., section 3.

7.2.1 Tokens
HLTM and Verilog files are considered a stream of tokens. A token consist of a sequence of one
or more characters, separated from other tokens by “white space”. The end-of-line sequence
generally does not have any special meaning, except that it is considered “white space.”

7.2.2 White Space

“White space” consists of the characters for spaces, tabs, and the end-of-line sequence. White
space is ignored (other than recognizing its function to separate tokens) unless it is within a
quoted string.

7.2.3 Comments
As with standard Verilog, comments can be specified in one of the following formats:

• One-line comment—Starts with the two characters // and ends at the end-of-line. The
“//” sequence can be anywhere on the line, and can follow active language constructs.
• Block comment—Starts with the sequence /* and ends with the sequence */. Block
comments cannot be nested. Block comments may span multiple lines. The one-line
comment token // does not have any special meaning when it appears within a block
comment.

7.2.4 Operators
Operators are single- and double-character sequences used in expressions. Verilog itself also
has some three-character operators, but they are not recognized by the HLTM compiler.

7.2.5 Numbers
Numbers in HLTM files are currently limited to decimal integer and floating-point values, and
“base-format” (binary, octal, hexadecimal) values. Size constants (values defined for a
particular bit width) are not allowed. This is not considered to be serious limitations in HLTM
files (as there would be very little reason to use them), but this limitation may be removed in the
future to allow more general compatibility with standard Verilog files. When necessary,
floating-point values are converted automatically to integers, by rounding rather than truncation
(this is also standard Verilog behavior).

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7.2.6 Strings
Strings are sequences of characters enclosed by double quotes (“ “) and must be contained on a
single line.

7.2.7 Identifiers
An identifier is used to give an object a unique name so it can be referenced later. The HLTM
compiler only supports simple identifiers (it does not support escaped identifiers; see IEEE spec
Section 3.7.1). A simple identifier consists of any sequence of letters, numeric digits, dollar
signs ($), and underscore characters (_), except that the first character shall not be a digit or $.
Verilog identifiers are case sensitive, but the HLTM compiler is not case sensitive and you
should not use identifiers that are identical except in case.

7.2.8 Keywords
Keywords are predefined identifiers used to define language constructs. Verilog keywords are
defined in lowercase only, and this standard should be followed in HLTM files, although the
HLTM compiler is not case-sensitive. The set of HLTM-recognized keywords and their
meanings is provided later in this document.

7.2.9 System Functions

A dollar sign ($) preceding an identifier (without white space between them) denotes a system
task or function. The HLTM compiler does not recognize any actual Verilog system tasks or
functions, as HLTM files are not “executed” as standard Verilog files are. However, Verilog
also provides a group of functions for performing timing checks, which use the same naming
convention as the Verilog system tasks and functions (the leading $ is present because of
historical usage). The HLTM compiler does recognize many of the Verilog timing check
functions, which are described later in this document.

7.2.10 Compiler Directives

The grave accent ` character (ASCII 0x60) is used to denote a compiler directive. This character
is not the more commonly-used single-quote character ‘. The directive consists of the `
character followed by an identifier without any white space separating them. The behavior
dictated by a compiler directive takes effect as soon as the compiler reads the directive and
remains in effect until another directive takes effect. A compiler directive in one description file
can, therefore, control compilation behavior in multiple description files.

7.2.11 Attributes
The HLTM compiler does not currently support the Verilog attribute construct (IEEE spec
Section 3.8).

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7.3 Data Types

The Verilog language defines a multitude of data types needed for hardware structural,
synthesis, and behavioral operations. Only a few of these “data types” are allowed in HLTM
files, however. These include the data storage type register, the variable types real and integer,
the range specifier ([msb:lsb]), which allows the definition of multiple-bit bus structures, and
the parameter type, which is used to specify constant values. This restriction is not considered a
serious limitation for HLTM files, because most situations that need data type specifications in
Verilog apply to nets and other synthesis and simulation related objects, which are not used in
HLTM files.

7.3.1 Registers
Registers in Verilog represent data storage elements, which retain their value until another value
is placed into them. The register type declaration is made with the keyword reg. HLTM files do
not have a use for registers in the traditional Verilog sense; they are allowed in HLTM only for
the purpose for assigning a character string value to a variable name, which in Verilog is a
capability unique to registers. In HLTM files, these strings can then be passed from the timing
model to the simulator/analyzer.

The following register declaration syntax variants are legal in HLTM files:

reg varID;
reg [range]varID;
reg varID = “character string”;
reg [range]varID = “character string”;

The two variants that include range specifiers allow the register size to be specified (see “7.3.3
Ranges” on page 1279). The HLTM compiler ignores this range specification, and will always
create a variable capable of storing the complete character string assigned to it.

The two variants that include the equal sign = character allow the initial value of the variable to
be specified in the register declaration. If the assignment is not made at declaration time, the
statement must be followed by another statement using the assign keyword (see “7.6.2 Variable
Assignments” on page 1287).

To clarify the purpose of the register declaration in HLTM files, the HLTM compiler will also
accept the keyword string as a synonym for reg. This is not Verilog compliant, however.

7.3.2 Variables
A variable is an abstraction of a data storage element. A variable stores a value from one
assignment to the next. As HLTM files are not executed, however, there is no benefit to making
an assignment to a variable more than once. It is illegal to re-declare a variable name already
declared by a parameter of another variable declaration. Variables must be defined within a
module definition. Unlike true-Verilog programs, HLTM variables are globally accessible
outside of the module by the simulator/analyzer.

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HLTM files allow the declaration of variables of type integer or of type real. The following
syntax structures are legal in HLTM files:

type varID;
type varID = expression;
type varID[range];
type varID[range1][range2];
type varID[range] = { exp1, exp2,…, expN };

where:

type is either the keyword real or the keyword integer.

varID is the variable identifier.
expression (and exp) is an expression that evaluates to a constant value.
range (including the bracketing “[“ and “]” characters) is a range construction (see
“7.3.3 Ranges” on page 1279).
The three variants that include range specifiers allow the variable to consist of arrays with up to
two dimensions. True-Verilog allows arrays of more than two dimensions; HLTM files are
limited to two dimensions or less.

The two variants that include the equal sign = character allow the initial value of the variable to
be specified in the variable declaration. The array values of a one-dimensional array variable are
specified by a sequence of constant expressions, separated by commas and bracketed by
opening and closing braces { } characters.

True-Verilog provides a number of ways to assign values to variables. However, other than
assigning these values at declaration time using the equal sign = variants, the only way to assign
values to variables allowed in HLTM files is by using the assign keyword (see “7.6.2 Variable
Assignments” on page 1287).

The primary purpose for variables in HLTM files is to allow the specification of particular
constant values that can be passed from the timing model to the simulator/analyzer. These
variable identifiers require certain pre-defined names to be useful. Non-arrayed variables can
also be used in expressions.

7.3.3 Ranges
The range data type is used in HLTM files to define multiple-bit signals, or buses. The syntax
consists of the following:

[ msb_constant_expression : lsb_constant_expression ]

The most significant bit specified by the msb_constant_expression is the left-hand value in the
range, and the least significant bit specified by the lsb_constant_expression is the right-hand
value in the range. Both the msb and lsb constant expressions must evaluate to integer constants.

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7.3.4 Parameters
Parameters are used to specify constant values. Verilog defines two types of parameters:
module parameters, and specify parameters (see IEEE spec section 4.10). Only module
parameters may be used in HLTM files. Furthermore, only the following variations of the
Verilog parameter statement are allowed in HLTM files:

parameter paramID = expression;

parameter pID1 = exp1, pID2 = exp2, ... , pIDN = expN;

Unlike true-Verilog, each “expression” (or “expN”) must evaluate to a single number (Verilog
also allows “min:typ:max” triplet-style constants to specify a range of delay values; see IEEE
spec section 5.3). Although the HLTM compiler accepts the “min:typ:max” syntax, it currently
does not evaluate or use the “typ” or “max” part of the value.

“Local parameters” and “specify parameters” (see IEEE spec section 4.10.2 and 4.10.3) are not
used in HLTM files. Module parameters that use data type qualifiers, such as integer, real, time,
or ranges ([msb:lsb]) are also not allowed. Parameters must be defined within a module
definition.

7.4 Expressions
An expression is a construct that combines operands with operators to produce a result that is a
function of the values of the operands and the semantic meaning of the operators. Generally,
wherever a value is needed in a Verilog statement, an expression may be used. In many cases,
Verilog allows operands to consist of variables as well as constants. Only non-arrayed variables
are allowed to be used in expressions within HLTM files. Constant expressions in HLTM files
contain operands that consist of constant numbers, parameters, non-arrayed variables, and other
constant expressions defined by macros.

7.4.1 Operators
The symbols used for Verilog operators are similar to those used in the C and C++
programming languages. The Verilog operators allowed in HLTM expressions are limited to the
set contained in Table 31-6.

Table 31-6. Timing Model Operators

Operator Description
unary + Unary operators
unary -
+ - * / ** Arithmetic
% Modulus
> >= < <= Relational
! Logical negation

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Table 31-6. Timing Model Operators (cont.)

Operator Description
&& Logical And
|| Logical Or
== Equality
!= Inequality
~ Bitwise Negation
& Bitwise And
| Bitwise inclusive Or
^ Bitwise exclusive
Or
<< Logical left shift
>> Logical right shift
?: Conditional

7.4.2 Operator Precedence

Table 31-7 shows the precedence order of Verilog operators used in HLTM files. Operators
shown on the same row have the same precedence. Operations with higher precedence are
evaluated first. Parentheses can be used to change the natural operator precedence, or to simply
clarify the expression.

Table 31-7. Timing Model Operator Precedence

Operator(s) Precedence
unary+ unary- ! & ~ Highest
**
*/%
+ - (binary)
<< >>
< <= > >=
== !=
&
^
!
&&

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Table 31-7. Timing Model Operator Precedence

Operator(s) Precedence
||
?: Lowest

7.4.3 Arithmetic Operators

The arithmetic operators include +, -, *, /, **, and %, which perform addition, subtraction,
multiplication, division, exponential, and modulo functions, respectively. Real operands are
converted to integers, if necessary; however, most arithmetic operations are performed using
floating point arithmetic

7.4.3.1 Relational and Equality Operators

The relational operators include <, <=, >, and >=, which perform a signed comparison of two
operands. The resulting value of the comparison is 0 if the relation is false and 1 if it is true. The
equality operator == and inequality operator != will similarly result in a value of 0 if false and 1
if true.

7.4.3.2 Logical Operators

The logical operators !, &&, and || return a value of 0 if false and 1 if true.

7.4.3.3 Bitwise Operators

The bitwise operators include ~, &, |, and ^ perform operations on integer operands (real values
are converted, if necessary). These operations are of limited use in HLTM files.

7.4.3.4 Shift Operators

The shift operators << and >> perform left-shift and right-shift operations, respectively. For
example, the expression

op1 << op2

shifts op1 to the left by op2 bits. Op1 and op2 must be integers, and are converted, if necessary.

7.4.3.5 Conditional Operator

The conditional operator uses three operands separated by two operators (? and :) in the
following format:

expression1 ? expression2 : expression3

The evaluation of a conditional operator begins with a logical equality comparison of

expression1 with zero, termed the condition. If the condition evaluates to false (0), then

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expression3 is evaluated and used as the result of the expression. If the condition evaluates to
true (1), then expression2 is evaluated and used as the result of the expression. For example,

(param1 >= param2) ? param1 : param2

returns the value param1 if param1 is greater than or equal to param2, and returns the value
param2 if param1 is less than param2.

7.4.3.6 Other Operators

The Verilog language includes several other operators that can be used in expressions.
Operators not listed in the preceding discussions, however, are not recognized by the HLTM
compiler. They are omitted primarily because they would have extremely limited use in an
HLTM file.

7.5 Timing Model Compiler Directives

All Verilog compiler directives are preceded by the grave accent ` character. It is different from
the apostrophe ‘ character. The scope of a compiler directive extends from the point where it is
processed, across all files processed, to the point where another compiler directive supersedes it
or the compilation completes. The following Verilog compiler directives are recognized by the
HLTM compiler.

7.5.1 `define
The directive `define creates a macro for text substitution, similar to the #define directive in C
and C++. This directive can be used anywhere in a Verilog source file. After a text macro is
defined, it can be used in the source description by using the (`) character, followed by the
macro name. When used in this way, the compiler substitutes the macro_text for the
instantiation of `text_macro_name.

`define text_macro_name macro_text

For example, the statements

`define ClockRate 400

parameter dataRate = `ClockRate * 2;

will assign a value of 800 to parameter “dataRate.”

Unlike true-Verilog, `define macros in HLTM files cannot be declared with arguments and
cannot span multiple lines.

The macro_text field may be blank.

The macro_text field may reference other macros specified with the `define directive. For
example,

`define ClockPeriod 2500

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`define DataTime `ClockPeriod/2

parameter setup = 100;
parameter hold = 100;
parameter validWindow = `DataTime - setup - hold;

The HLTM compiler itself pre-defines the macro “HyperLynx_Timing,” which can be used to
isolate non-Verilog conforming sections of the HLTM file to prevent compilation errors on
standard Verilog compilers. This implicit macro definition is identical to a situation where you
explicitly inserted the statement

`define HyperLynx_Timing

as the first statement in the timing model file.

7.5.2 `undef
The directive

`undef text_macro_name

“undefines” a previously defined text macro. Usage of the macro after the `undef directive will
result in a compilation error, unless it is redefined.

7.5.3 `ifdef, `else, `elsif, `endif, `ifndef

These conditional compilation compiler directives are used to optionally include lines of source
code during compilation. The individual syntax of these directives is:

`ifdef text_macro_name
`ifndef text_macro_name
`else
`elsif text_macro_name
`endif

The `ifdef compiler directive checks for the definition of macro text_macro_name. If
text_macro_name is defined (the macro_text part of the macro definition is unimportant), the
lines following the `ifdef directive are actively compiled. If the text_macro_name is not defined
and a corresponding `else directive exists later in the file, the source following the `ifdef is
ignored as if it were commented out, and the source following the `else directive is actively
compiled instead. The source control imparted by the `ifdef directive is terminated by a
corresponding `endif directive. There can be only one `else directive for each `ifdef directive.

The `ifndef compiler directive, like the `ifdef directive, also checks for the definition of macro
text_macro_name; however, it works in an opposite fashion. With the `ifndef directive, if the
text_macro_name is not defined, the lines following the `ifndef directive are actively compiled.
If the text_macro_name is defined and a corresponding `else directive exists, the source
following the `ifndef is ignored as if it were commented out, and the source following the `else
directive is actively compiled. The source control imparted by the `ifndef directive is terminated
by a corresponding `endif directive. There can be only one `else directive for each `ifndef
directive.

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The `elsif directive must be preceded by either an `ifdef or `ifndef directive. If the `elsif
directive is used (instead of the `else directive), and if the original `ifdef or `ifndef condition
was false, the compiler checks for the definition of the text_macro_name. If the macro exists,
the lines following the `elsif directive are actively compiled. The `elsif directive is equivalent to
the compiler directive sequence `else `ifdef ... `endif. The `elsif directive, unlike the `else `ifdef
sequence, must not be followed with a corresponding `endif directive. Also unlike the `else
directive, there can be multiple `elsif directives for each `ifdef or `ifndef directive.

These directives may appear anywhere in the source description, and may be nested. Each `ifdef
or `ifndef directive in a nested conditional structure requires a corresponding `endif directive.

A good coding practice would be to add a default `define directive at the end of a long chain of
`ifdef ...`elsif ...`elsif ...`else directives used for defining parameter sets or similar constructions,
to ensure that the parameters will not end up being completely undefined if none of the prior
`ifdef or `elsif conditions is true.

7.5.4 `include
The file inclusion (`include) compiler directive is used to insert the entire contents of a source
file into another file during compilation. The result is as though the entire contents of the
included source file appear in place of the `include compiler directive. The `include compiler
directive can be used to include global or commonly used definitions and tasks without
encapsulating repeated code within the module boundaries. The syntax for the `include directive
is:

`include “filename”

The filename is the name of the file to be included in the source file. The filename can be a full
or relative path name, and must appear within the double-quote marks. A file included using this
directive may itself include other files with more `include directives.

7.5.5 `timescale
This directive specifies the time unit and time precision of the modules that follow it. The time
unit is the unit of measurement for time values such as the simulation time and delay values.
The syntax of this directive is:

`timescale time_unit / time_precision

The time_unit and time_precision arguments consist of an integer constant (limited to the values
of 1, 10, or 100) followed by a time-unit specifier (s, ms, us, ns, ps, or fs). For example,

`timescale 10 ps / 1 ps
parameter TSH = 32;

indicates that the parameter TSH has a value of 320 ps (32 units * 10 ps/unit) and that
calculations will be rounded with 1 ps precision.

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The default values used by the HLTM compiler are 1 ps for both the time_unit and
time_precision. Since the HLTM compiler only compiles the source code, and never executes it,
the time_precision field is rather meaningless in this context; however, it must be present to
maintain Verilog compatibility.

7.6 Hierarchical Structures

Verilog supports a hierarchical structure by allowing function blocks, referred to as modules, to
be embedded within other modules. Higher level modules create instances of lower level
modules and interface to them through input, output, and bidirectional ports. Verilog modules
may also contain purely internal ports and variables. As HLTM models are meant to only
describe the timing relationships at the physical component pins, the structural composition of a
HLTM model must consist of a single top-level module without an internal structure, and that is
all the HLTM compiler currently supports.

7.6.1 Modules
A module definition is enclosed between the keywords module and endmodule. An identifier
following the keyword module is the name of the module being defined. An optional list of
ports or port declarations specifies a list of the external interface ports for the module.

Module declarations in Verilog allow a multitude of formats. The HLTM compiler restricts
these to the following formats:

module modName(list_of_ports);
module modName(list_of_port_declarations);

These two formats may seem similar until the distinction is made between a list_of_ports and a
list_of_port_declarations.

A list_of_ports is simply a comma-separated sequence of port name identifiers. Modules

declared in this way must have the port characteristics for each port in the list_of_ports declared
separately in the module body. Port characteristics include the port type (input, output, inout)
and optional range attributes (for ports that are buses).

A list_of_port_declarations combines the port and port-attribute declarations into a single list
within the module declaration itself. Ports declared in the list of port declarations must not be
re-declared within the body of the module (refer to IEEE spec section 12.1).

You must use one of the two module declaration formats exclusively; a list_of_ports cannot be
mixed with a list_of_port_declarations. This is a Verilog language requirement, not a limitation
imposed by the HLTM compiler.

To illustrate the difference between the two module declaration formats, consider the following
two (and functionally identical) module declarations for an eight-bit data register:

module register8(clk, d, q);

input clk;

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input [7:0] d;
output [7:0] q;
endmodule

module register8(
input clk,
input [7:0] d,
output [7:0] q);
endmodule

7.6.2 Variable Assignments

The Verilog language is rich with constructs needed for behavioral modeling. Only one of these
mechanisms is allowed within HLTM files, however: the assign statement. The assign
statement, as it implies, is used to assign a value to a pre-declared variable or register. The
formats for the assign statement are:

assign varID = expression;

assign varID = { exp1, exp2, ... , expN };

where:

varID is the variable or register identifier.

expression (and exp) is an expression that evaluates to a constant value for numeric
variables, and to a character string for registers (see “7.3.1 Registers” on page 1278).
The first variant is used to assign a value to either a non-arrayed variable or to a particular single
element of an arrayed variable. For example, if “arr1Var” is a one-dimensional array and
“arr2Var” is a two-dimensional array:

assign arr1Var[3] = 12;

assign arr2Var[3][2] = 13;

These statements assign the value “12” to the element [3] of “arr1Var” and the value “13” to
element [3][2] of array “arr2Var”.

The second variant is used to assign a complete set of values to either a one-dimensional array,
or to a particular “row” of a two-dimensional array. The array values are specified by a
sequence of constant expressions, separated by commas and bracketed by the opening and
closing brace {} characters. For example, if “arr1Var” is a one-dimensional array and “arr2Var”
is a two-dimensional array:

assign arr1Var = { 1, 2, 3 };
assign arr2Var[3] = { 1, 2, 3 };

These statements assign the values “1”, “2”, and “3” to array “arr1Var” and also to “row” [3] of
array “arr2Var”. The number of values in the expression list must match the number of elements
(or “columns”) in the array. The number of “rows” and “columns” of an arrayed variable are
specified when the variable is declared (see “7.3.1 Registers” on page 1278).

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The assign statement must occur within a module.

7.6.3 Specify Blocks

In standard Verilog files, the specify block is the mechanism for describing paths between a
source and a destination, for assigning delays to those paths, and for specifying and performing
timing checks to ensure that events occurring at the module inputs satisfy the timing constraints
of the device described by the module. The path statements are not used in HLTM files, but the
HLTM compiler does use the specify blocks to declare the delay relationships and timing
constraint checks.

A specify block must reside within a module, begins with the keyword specify, and ends with
the keyword endspecify.

7.6.4 Timing Checks

Timing checks must be placed within specify blocks to verify the timing of a design by making
sure critical events occur within given time limits. Timing checks are declared using Verilog
system function syntax, even though they are not considered system functions. System function
identifiers are preceded by a dollar sign ($). Verilog defines the following timing check
functions (Verilog syntax optionally allows more argument fields in some of these functions
than are shown here; the following syntax formats are what the HLTM compiler recognizes--
Note: not all of these may actually be used by the batch simulation engine):

$setup(data_event, reference_event, timing_check_limit);

$hold(reference_event, data_event, timing_check_limit);
$setuphold(reference_event, data_event, timing_check_limit1,
timing_check_limit2);
$skew(reference_event, data_event, timing_check_limit);
$timeskew(reference_event, data_event, timing_check_limit);
$fullskew(reference_event, data_event, timing_check_limit1,
timing_check_limit2);
$width(reference_event, timing_check_limit);
$period(reference_event, timing_check_limit);

The reference_event and data_event fields consist of an optional edge specification keyword
followed by a port identifier (a range of a bus port identifier may also be specified). An edge
specification consists of one the keywords posedge or negedge; Verilog itself also has other
ways to specify edges, but these two keywords are sufficient for HLTM files and are the only
edge specification keywords accepted by the HLTM compiler. If an edge specification keyword
is not present, it is assumed that the event may occur on any state transition on the port
identifier.

The timing_check_limit field is a numeric expression that evaluates to a time value. In most
cases, this value is non-negative. For example, even though a $setup check describes a
condition where a data_event occurs before the reference_event, the timing_check_limit is still
specified with a positive value (the parameter is relative to the data_event, rather than the
reference_event).

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The following discussions describe the Verilog implementation of the timing check functions.
As the actual implementation of each function in this framework resides in the program that
instantiates the HLTM compiler, it is free to make slightly different interpretations of the
functions, as needed.

The $setup function requires that time of occurrence of the reference_event minus the time of
occurrence of the data_event must be greater than timing_check_limit. As timing_check_limit
must be >0, a valid setup relationship exists only if the data_event occurs before the
reference_event.

The $hold function requires that time of occurrence of the data_event minus the time of
occurrence of the reference_event must be greater than timing_check_limit. As
timing_check_limit must be >0, a valid hold relationship exists only if the data_event occurs
after the reference_event.

The $setuphold function effectively combines the $setup and $hold functions, with
timing_check_limit1 being the setup value and timing_check_limit2 being the hold value.
Unlike those functions, however, the $setuphold function can accept negative limit values. The
invocation

$setuphold(posedge clk, data, tSU, tHLD);

is equivalent to the following (if tSU and tHLD are not negative):

$setup(data, posedge clk, tSU);

$hold(posedge clk, data, tHLD);

The $skew function requires that time of occurrence of the data_event minus the time of
occurrence of the reference_event must be less than timing_check_limit. This implies that the
data_event must occur after the reference_event. The reference_event triggers the $skew check.
If the data_event never happens, the $skew check is never completed.

The $timeskew function is similar to the $skew check, except that if no data_event has occurred
before the timing_check_limit, an error is reported (at least is in standard Verilog; the HLTM
compiler only compiles but doesn’t actually execute the code).

The $fullskew function is perhaps the most useful “skew” function in HLTM models. It is
similar to $timeskew except that the reference and data events can transition in either order. The
first timing_check_limit is the maximum time by which the data event may follow the reference
event. The second timing_check_limit is the maximum time by which the reference event may
follow the data event. Figure 31-3 illustrates this relationship.

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Figure 31-3. $fullskew Timing Check Limits

The $fullskew and $setuphold functions can be viewed as somewhat complementary timing
check functions, in that the $setuphold function specifies the minimum time that a data signal
can transition before and after a reference signal transition while the $fullskew function
specifies the maximum time that a data signal can transition before or after a reference signal
transition.

The $width function is used to perform a pulse width check of the reference signal. The
reference_event must include an edge specifier (posedge or negedge).

The $period function is used to perform a period check of the reference signal. The
reference_event must include an edge specifier (posedge or negedge).

7.6.5 Timing Delays

Verilog permits a variety of formats for specifying signal paths and signal path delays within
specify blocks. Those methods are currently not supported by the HLTM compiler. Instead, a
simple non-Verilog construct is added to the syntax to specify the simple delay relationships
between module ports:

$delay(fromport_event, toport_event, min_delay, max_delay);

The fromport_event and toport_event refer to module ports (with an optional edge specifier).
The fromport_event is the controlling event, while the toport_event is the dependent event. The
delay arguments specify the minimum and maximum delays between the fromport_event and
the toport_event, and may be negative.

As the $delay function is not part of the Verilog language, it should be surrounded by a

`ifdef HyperLynx_Timing
$delay( );
`endif

sequence to prevent compilation errors on standard Verilog compilers.

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The introduction of the $delay function simplifies the writing of and parsing of HLTM files.
Table 31-8 contains examples to contrast the use of the HLTM $delay function with standard
Verilog equivalent syntax (see IEEE specification sections 14.2.2 and 14.2.3).

Table 31-8. Contrasting HLTM and Verilog $delay Functions

HLTM Syntax Verilog Syntax
delay(ck, out, min, max); ck => out) = min:max;
$delay(posedge ck, out, min, max); (posedge ck => (out:in)) = min:max;

Verilog also allows much more complex path timing declarations than these, which include
behavioral information as well as the timing values associated with those behaviors. This
functionality is beyond what is needed in HLTM models.

7.7 HyperLynx Timing Model Requirements

The preceding sections describe the overall syntax for Verilog files in general, and for the
HyperLynx Timing Model compiler in particular. However, for the DDR/2/3 simulations in
HyperLynx, these further requirements and restrictions are placed on acceptable timing models,
in order to simplify the actual models:

• The `timescale declaration must always be “1 ps / 1ps,” if present. If omitted, the

compiler will automatically assume this timescale.
• All timing parameters in the model must resolve to a time value (not a clock cycle
value), measured in picoseconds.
• All timing parameters based on clock periods must accept the pre-defined macro
directive `tCK, which will be the designated clock period (supplied from the DDRx
wizard), measured in picoseconds.
• If a model defines timing values for a multitude of speed grades (using `ifdef, `elsif, and
`else directives), it must accept the DDRx wizard speed grade designators in Table 31-9.
The wizard pre-defines all permutations of a particular speed grade designator, so the
model can use whatever designator is most appropriate; not all speed grades are actually
available for all three DDR technologies.

Table 31-9. DDRx Wizard Speed Grade Designators

Wizard Designators Micron Designators Samsung Designators
DDR_266, DDR2_266, DDR3_266 -75 (TBD)
DDR_333, DDR2_333, DDR3_333 -6T (TBD)
DDR_400, DDR2_400, DDR3_400 -5B, -5E CC
DDR_533, DDR2_533, DDR3_533 -37E D5
DDR_667, DDR2_667, DDR3_667 -3, -3E E6

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Table 31-9. DDRx Wizard Speed Grade Designators (cont.)

Wizard Designators Micron Designators Samsung Designators
DDR_800, DDR2_800, DDR3_800 -25, -25E E7, F7
DDR_1066, DDR2_1066, DDR3_1066 -187, -187E (TBD)
DDR_1333, DDR2_1333, DDR3_1333 -15, -15E (TBD)
DDR_1600, DDR2_1600, DDR3_1600 (TBD) (TBD)
• A timing model should contain the module interface ports in Table 31-10, and must use
these specifically designated port names (any associated bit range specifications will be
ignored).

Table 31-10. Timing Model Module Interface Ports

Port Controller DRAM PLL Register Description
Name Direction Direction Direction Direction
ck output input input input Clock from controller to
DRAMs, PLL, Registers
addr_cmd output input N/A N/A Address and Command signals
from controller to DRAM
ctl output input N/A N/A Control signals from controller
to DRAM
dqs inout inout N/A N/A Data Strobes (bidirectional)
dq inout inout N/A N/A Data signals (bidirectional)
dm output input N/A N/A Data Mask signals from
controller to DRAM
y N/A N/A output N/A Clock outputs from PLL to
DRAMs and Registers
d N/A N/A N/A input Address, Command and
Control signals from controller
to Register
q N/A N/A N/A output Address, Command and
Control signals from Register to
DRAMs

• A Memory Controller timing model should include the following timing relationships in
the model’s specify block (signal edge qualifiers will be ignored; refer to Figure 31-4,
Figure 31-5, Figure 31-6, Figure 31-7, and Figure 31-8). Note that parameter tDQDQS
and parameters tDS/tDH are complementary methods of describing the DQ-to-DQS

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timings during read cycles; only one of the two methods should be specified in the
timing model file.

Table 31-11. Controller Timing Model Timing Relationships

Parameter Model File Active Description
Relationship Cycle
tCKAC $delay(ck, addr_cmd, All Simulation pre-launch delay, CK to
min, max); Address and Command signals (will be
See Figure 31-4 specified differently in the datasheet)
on page 1294.
tCKCTL $delay(ck, ctl, min, All Simulation pre-launch delay, CK to
max); Control signals (will be specified
See Figure 31-4 differently in the datasheet)
on page 1294.
tCKDQS $delay(ck, dqs, min, Write Output delay or skew, CK output to DQS
max); output
See Figure 31-5
on page 1294.
tDQSDQ $delay(dqs, dq, min, Write Simulation pre-launch delay, DQS output
max); to DQ and DM outputs
See Figure 31-6
on page 1295.
tDQDQS $fullskew(dqs, dq, Read Tolerable input skew between DQS and
min, max); DQ. Optionally specify this instead of
See Figure 31-7 tDS/tDH.
on page 1295.
tDS, tDH $setup(dq, dqs, tDS); Read DQ to internally shifted DQS setup/hold
$hold(dqs, dq, tDH); requirements. Optionally specify these
See Figure 31-8 instead of tDQDQS.
on page 1296. Or

$setuphold(dqs, dq,
tDS, tDH);

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Figure 31-4. Controller Parameters tCKAC and tCKCTL

Parameter Cycle I/O Type Description

tCKAC Any Output Delay Address/Command prelaunch delay, relative to CK(r).
Address/Command timings set to 2T.
tCKCTL Any Output Delay Control prelaunch delay, relative to CK(r)

Figure 31-5. Controller Parameter tCKDQS

Parameter Cycle I/O Type Description

tCKDQS Write Output Delay DQS delay, relative to CK

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Figure 31-6. Controller Parameter tDQSDQ

Parameter Cycle I/O Type Description

tDQSDQ Write Output Skew DQ prelaunch delay, relative to DQS

Figure 31-7. Controller Parameter tDQDQS

Parameter Cycle I/O Type Description

tDQDQS Read Input Skew Maximum tolerable DQ to DSQ skew (-, +), derived
from tDS and tDH

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Figure 31-8. Controller Parameters tDS and tDH

Parameter Cycle I/O Type Description

tDS Read Input Setup DQ valid to shifted DQS
tDH Read Input Hold Shifted DQS to DQ invalid

• A memory controller timing model may also include other variables containing
information needed for meaningful read-cycle simulations and analysis. This
information is summarized below. If any of these variables is missing in the model,
default characteristics are assumed. To be recognized, the model must use the variable
identifiers in Table 31-12.
Table 31-12. Controller Timing Model Variables
Variable Syntax Description
DQSReadShift real DQSReadShift = 0; Specifies the internal delay that
should be applied to the DQS
real DQSReadShift = `tCK/4; signal during read operations,
before making setup/hold
Default: `tCK/4; measurements on DQ signals. If
this variable is missing, a 90
degree (1/4 clock cycle) phase
shift is assumed. If timing is to be
measured at the device pins, the
value should be zero. The value
should be specified in
picoseconds.

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Table 31-12. Controller Timing Model Variables (cont.)

Variable Syntax Description
Derate_tDS real Derate_tDS = 0; Specify input derating tables for
Derate_tDH setup/hold measurements. If one of
real Derate_tDS = these variables is missing, no
USE_JEDEC_DERATING; derating will be applied to that
measurement (this is also the case
real Derate_tDS[rows:0][cols:0]; if the value is specified as zero).
assign Derate_tDS[row] = { colValList };
If the value is set to the constant
... (the other variable has the same basic USE_JEDEC_DERATING, the
syntax) JEDEC tables specified for
DRAMs is used, which may not be
Default: No derating is applied. appropriate for memory
controllers.

Custom derating tables can be

defined by first defining the size of
the table, followed by assign
statements that specify the
derating values for each row of the
table. The rows of the table
represent variations in the slew
rate for DQ signals, while the
columns represent variations in the
slew rate for DQS signals. For
each row, the first entry (column)
will be the DQ slew rate value,
specified in V/ns. Likewise, row 0
will contain the DQS slew rate
values for each column, specified
in V/ns. Table entry [0][0] is not
used. The remainder of the table
consists of the derating values,
specified in picoseconds.

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• A DRAM timing model should include the timing relationships in Figure 31-13 on
page 1298 in the model’s specify block (signal edge qualifiers will be ignored. See
Figure 31-9, Figure 31-10, Figure 31-11, Figure 31-12, and Figure 31-13.

Table 31-13. Memory Timing Model Parameters

Parameter Model File Relationship Active Description
Cycle
tIS, tIH $setup(addr_cmd, ck, tIS); All Address, Command and Control
See $hold(ck, addr_cmd, tIH); signals to CK setup/hold requirements
Figure 31-9.
Or

$setuphold(ck, addr_cmd, tIS,

tIH);
tDQSS $fullskew(ck, dqs, min, max); Write Tolerable input skew, CK rising input
See to DQS rising input
Figure 31-1
0.
tDSS, tDSH $setup(dqs, ck, tDSS); Write CK rising input to DQS falling input
See $hold(ck, dqs, tDSH); setup/hold requirements; tDSS is valid
Figure 31-1 only if tDQSS >=0; tDSH is valid
0. Or only if tDQSS <=0

$setuphold(ck, dqs, tDSS,

tDSH);
tDS, tDH $setup(dq, dqs, tDS); Write DQ, DM to DQS setup/hold
See $hold(dqs, dq, tDH); requirements
Figure 31-1
1. Or

$setuphold(dqs, dq, tDS, tDH);

tDQSCK $delay(ck, dqs, min, max); Read Output delay or skew, CK input to
See DQS output
Figure 31-1
2.
tDQSQ $delay(dqs, dq, min, max); Read Output delay or skew, DQS output to
See DQ output
Figure 31-1
3.

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Figure 31-9. DRAM Parameters tIS and tIH

Parameter Cycle I/O Type Description

tIS Any Input Setup Address/Command/Control valid to CK(r)
tIH Any Input Hold CK(r) to Address/Command/Control invalid

Figure 31-10. DRAM Parameters tDQSS, tDSS, tDSH

Parameter Cycle I/O Type Description

tDQSS Write Input Skew DQS(r), relative to CK(r)(-,+)
tDSS Write Input Setup DQS(f) to CK(r), if tDQSS >= 0
tDSH Write Input Hold CK(r) to DQS(f), if tDQSS <= 0

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Figure 31-11. DRAM Parameters tDS and tDH

Parameter Cycle I/O Type Description

tDS Write Input Setup DQ,DM valid to DQS
tDH Write Input Hold DQS to DQ,DM invalid

Figure 31-12. DRAM Parameter tDQSCK

Parameter Cycle I/O Type Description

tDQSCK Read Output Delay DQS delay, relative to CK

Figure 31-13. DRAM Parameter tDQSQ

Parameter Cycle I/O Type Description

tDQSQ Read Output Skew DQ delay, relative to DQS

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• A DRAM timing model may also include other variables that provide custom input slew
rate derating tables. Table 31-14 summarizes this information. If any of these variables
is missing in the model, the appropriate JEDEC derating tables are assumed (most
situations will not require custom derating tables). To be recognized, the model must use
the specified variable identifiers.
See also: “Slew Rate Derating Tables” on page 1274

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Table 31-14. Memory Timing Model Variables

Variable Syntax Description
Derate_tDS real Derate_tDS = 0; The variables Derate_tDS and Derate_tDH are
Derate_tDH used to specify input derating tables for data
Derate_tIS real Derate_tDS[rows:0][cols:0]; and data mask setup/hold measurements,
Derate_tIH assign Derate_tDS[row] = { respectively. The variables Derate_tIS and
colValList }; Derate_tIH are used to specify input derating
tables for address, command, and control
... (the other variables have the signal setup/hold measurements, respectively.
same basic syntax) If one of these variables is missing, the
relevant JEDEC derating table will be used.
Default: Standard JEDEC Normally, you will use the JEDEC tables.
derating is applied.
Custom derating tables can be defined by first
defining the size of the table, followed by
assign statements that specify the derating
values for each row of the table.

The rows of the Derate_tDS and Derate_tDH

tables represent variations in the slew rate for
DQ signals, while the columns represent
variations in the slew rate for DQS signals. For
each row, the first entry (column) will be the
DQ slew rate value, specified in V/ns.
Likewise, row 0 will contain the DQS slew
rate values for each column, specified in V/ns.
Table entry [0][0] is not used. The remainder
of the table consists of the derating values,
specified in picoseconds.

The rows of the Derate_tIS and Derate_tIH

tables represent variations in the slew rate for
address, command, and control signals, while
the columns represent variations in the slew
rate for clock CK signals. For each row, the
first entry (column) will be the address,
command, and control slew rate value,
specified in V/ns. Likewise, row 0 will contain
the CK slew rate values for each column,
specified in V/ns. Table entry [0][0] is not
used. The remainder of the table consists of the
derating values, specified in picoseconds.

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• A clock PLL timing model should include the timing relationships contained in
Table 31-15 on page 1303 in the model’s specify block (signal edge qualifiers will be
ignored; see Figure 31-14, Figure 31-15, and Figure 31-16).

Table 31-15. PLL Timing Model Parameters

Parameter Model File Active Description
Relationship Cycle
tDPO $delay(ck, y, min, max); All Input-to-output phase offset, CK input to any
See Y output (min = -max)
Figure 31-1
4.
tJIT $delay(ck, ck, min, All Output period jitter at any Y output (min = -
See max); max)
Figure 31-1
5.
tSKO $delay(y, y, min, max); All Output-to-output skew, any Y output to any
See other Y output (min = -max)
Figure 31-1
6.

Figure 31-14. PLL Parameter tDPO

Parameter Cycle I/O Type Description

tDPO Any Output Skew Phase offset CK to Y

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Figure 31-15. PLL Parameter tJIT

Parameter Cycle I/O Type Description

tJIT Any Output Jitter Output period jitter

Figure 31-16. PLL Parameter tSKO

Parameter Cycle I/O Type Description

tSKO Any Output Skew Output-to-output skew

• An address/command/control register timing model should include the timing

relationships contained in Table 31-16 on page 1304 in the model’s specify block
(signal edge qualifiers will be ignored; see Figure 31-17 and Figure 31-18).

Table 31-16. Register Timing Model Parameters

Parameter Model File Relationship Active Description
Cycle
tDS, tDH $setup(d, ck, tDS); All Address, Command and Control signals
See $hold(ck, d, tDH); to rising CK setup/hold requirements
Figure 31-1
7. Or

$setuphold(ck, d, tDS, tDH);

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Table 31-16. Register Timing Model Parameters (cont.)

Parameter Model File Relationship Active Description
Cycle
tCKQ $delay(ck, q, min, max); All Input-to-output delay, rising CK to any
See output Q
Figure 31-1
8.

Figure 31-17. Register Parameters tDS and tDH

Parameter Cycle I/O Type Description

tDS Any Input Setup D valid to CK(r)
tDH Any Input Hold CK(r) to D invalid

Figure 31-18. Register Parameter tCKQ

Parameter Cycle I/O Type Description

tCKQ Any Output Delay CK(r) to Q delay

7.8.1 HyperLynx Timing Model Pre-Defined Variables

When a HLTM file is compiled using through the DDRx wizard, the wizard pre-defines a set of
variables and makes them available for use within the timing model. The nature of these
variables is as if they had been declared within the model file itself as a macro using a `define
keyword (see “7.5.1 `define” on page 1283), and therefore they should be used syntactically in

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the same manner. Some of the variables are assigned a value, specified in the wizard, while
others simple are defined (or undefined). See Table 31-17.

Table 31-17. Pre-Defined Variables for Timing Models

Variable Assigned Value Description
tCK The clock period, in Assigned in the Wizard,
picoseconds. as (data rate/2).
DDR One and only one of The DDR type.
DDR2 these will be defined.
DDR3
DDR_266, DDR2_266, DDR3_266 One and only one set of The component speed
DDR_333, DDR2_333, DDR3_333 these designators will be grade.
DDR_400, DDR2_400, DDR3_400 defined.
DDR_533, DDR2_533, DDR3_533
DDR_667, DDR2_667, DDR3_667 For example, if the
DDR_800, DDR2_800, DDR3_800 device is a “800” speed
DDR_1066, DDR2_1066, DDR3_1066 grade, DDR_800,
DDR_1333, DDR2_1333, DDR3_1333 DDR2_800, and
DDR_1600, DDR2_1600, DDR3_1600 DDR3_800 will all be
defined.
ADDRCMD1T One and only one of Defined according to
ADDRCMD2T these will be defined. whether the address and
command signals are
using 1T or 2T timing.
NOT_A_NUMBER The actual pre-defined The only place this
value is unimportant and variable can be used in
should not be used. current timing models is
in derating table
specifications. It is used
to declare that the
relevant table entry is not
defined.

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Table 31-17. Pre-Defined Variables for Timing Models (cont.)

Variable Assigned Value Description
USE_JEDEC_DERATING The actual pre-defined The only place this
value is unimportant and variable can be used in
should not be used. current timing models is
in derating table
specifications. It is used
to declare that the entire
table should use values
defined within the
JEDEC DRAM
specification. For
example, real
Derate_tDS =
`USE_JEDEC_DERATI
NG;

HyperLynx DDRx Wizard Setup File Format

The DDRx wizard is a tool for setting up batch simulations in HyperLynx for analyzing a
standard DDRx interface between a memory controller device and DDRx memory devices. The
wizard writes the setup information to the ASCII-formatted DDRx wizard setup file so it can be
read in by DDRx batch simulation or a future DDRx wizard session.

Because the wizard edits and writes the setup file, you are not required to learn the setup file
syntax. Advanced users who run many DDRx simulation variations on a design, such as
simulating different speed grades, may prefer to manually edit the setup file. Although the setup
file itself contains many helpful syntax comments, this section provides detailed syntax and a
complete example setup file.

This topic contains the following:

• “Contents of the DDRx Wizard Setup File” on page 1307

• “Example DDRx Setup File” on page 1323

Related Topics
“Simulating DDRx Memory Interfaces”

Contents of the DDRx Wizard Setup File

This topic contains the following:

• “General Syntax Notes - DDRx” on page 1308

• “Pre-Defined Keywords” on page 1310

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General Syntax Notes - DDRx

The file is structured as a sequence of information records.

Each record consists of an opening curly-brace { followed by a record-type identifying

keyword, record-type specific data, and a closing curly-brace } which terminates the record.

Records may occur in any order within the file.

All record-types are optional. This is not a limitation for the DDRx wizard itself, but
information that is missing from the file may inhibit setting up the actual batch-mode
simulations.

When a record contains multiple sub-records, a semicolon ; is used to separate one sub-record
from another.

Sub-records usually are of form:

KeywordID = argumentList;
Keywords are not case-sensitive.

Keywords may be abbreviated to whatever length is required to make them unique from another
keyword.

Keywords can generally also be used as argument identifiers.

Whitespace characters (spaces, tabs, and end-of-line sequences) can be placed anywhere, to
improve readability.

Comments may be inserted anywhere, using the comment designators in Table 31-18.

Table 31-18. Comment Designators for DDRx Wizard Setup File

Comment Description
Designator
* If this character is in the first column, the remaining characters on the line are
considered to be a comment (like other HyperLynx files).
// Characters following this sequence, to the end of the line, are considered to be
a comment (like C++ comments).
-- Characters following this sequence, to the end of the line, are considered to be
a comment (like VHDL comments).

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Table 31-18. Comment Designators for DDRx Wizard Setup File (cont.)
Comment Description
Designator
/* */ Anything between these opening-closing sequences are considered to be a
comment (like C and C++ comments). Comments defined in this way may
span multiple lines. These comments cannot be nested. For example, “/* ... /*
... */ ... */" will not nest one comment within another. The "one-line" comment
sequences do not have any special meaning within the /* ... */ comment
sequence, that is, the end of the line will not terminate the comment defined by
/* ... */.
Records and sub-records are normally terminated by the closing curly-brace } and semicolon ;
characters, respectively, although records and sub-records may abnormally terminate with the
opening curly-brace { character (which starts a new record). An end-of-line sequence will not
automatically terminate a record, sub-record, or a comment defined by the /*...*/ markers.

When the DDRx wizard is used to automatically create or update a setup file, it automatically
removes manually-inserted comments and restores “standard” comments when it saves the
setup file. Persistent manually-inserted comments may be placed in the "Notes" section of the
setup file.

Arguments that are character strings may optionally be enclosed within doublequotes " ". If a
string-type argument contains a symbol or character sequence that might be misinterpreted by
the file parser, such as comment-sequence markers or identifier names that can be
misinterpreted as a number, that string must be enclosed within doublequotes.

Argument lists consist of individual arguments separated by commas.

If an argument list contains argument strings with indexed identifiers such as DQ0, DQ1, DQ2,
the list may be abbreviated by either using the ellipsis-like character sequence .. or a colon : to
indicate a range of identifiers. For example, the argument list U1, U2, U3, U7 may be
abbreviated either as U1..3, U7 or U1:3, U7. The ellipsis or colon may occur anywhere within
the identifier as long as there is a number on both sides. For example, DQS0..3NOT will expand
as DQS0NOT, DQS1NOT, DQS2NOT, DQS3NOT.

Arguments that are comprised of file names do not include any directory path information, in
order to maintain some degree of portability. Some external means must be provided for
locating the files within a particular directory structure. Usually this is the HyperLynx model-
library path. See “Select Directories for IC-Model Files Dialog Box” on page 1844.

Numeric arguments may optionally be followed by a units-type designator, where appropriate.

In such cases, if the units-type designator is not specified, a default unit-type is assumed. The
following unit-type keywords are defined (as with other keywords, these unit-type keywords are
not case-sensitive and may be abbreviated to any length that keeps them unique from other
keywords):

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m — meters
cm — centimeters
mm — millimeters
in — inches
mils — 1/1000 of an inch
Min — minutes
S — seconds
mS — milliseconds
uS — microseconds
nS — nanoseconds
pS — picoseconds
V — volts
mV — millivolts
uV — microvolts

Pre-Defined Keywords
The file parser recognizes the keywords in this section. Some keywords may be used in more
than one context.

Table 31-19. Record Identifier Keywords

AddrCommNets DisabledNets Options
Boards DRAM ODTBehavior
ClockNets DRAMRanks ODTModels
Controller DRAMs Parts
ControlNets End PartTypes
DataNets IBISModelSelectors Project
DataRate Notes Version

Table 31-20. Sub-Record Identifier Keywords

ACCTiming MaxRunTime SimulationRuns
Corners PLL Skew

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Table 31-20. Sub-Record Identifier Keywords (cont.)

Crosstalk Rank Slot
DataSimulations Read Stimulus
DataStrobes Register StrobeTiming
DataTiming SaveAll Thresholds
DDRType SavePoints VaryRef
DIMMType SimLoss Write
IncludeVias SimRuns XLSAutoFormat
MaxOvershoot SimulateLoss

Table 31-21. Argument Keywords

1T DDR2_400 None
2T DDR2_533 Off
All DDR2_667 On
Audit DDR2_800 PRBS
Batch DDR2_1066 Rank
Both DDR3 RDIMM
Controller DDR3_800 ReadOnly
Custom DDR3_1066 SingleEnded
DDR DDR3_1333 Slow
DDR_266 DDR3_1600 Strong
DDR_333 Differential True
DDR_400 Disabled Typical
DDR_533 Electrical UDIMM
DDR_667 Enabled Vtt
DDR_800 False Weak
DDR_1066 Fast WriteOnly
DDR_1333 FBDIMM Yes
DDR_1600 Geometric
DDR2 No

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Table 31-22. Argument Unit-Type Keywords

cm mm S
in mS uS
m mV uV
mils nS V
Min pS

Many of the keywords in Table 31-22 on page 1312 can be treated as binary values, and can be
used interchangeably. These include the following:

• False, No, Off, Disabled, None (“0” also works)

• True, Yes, On, Enabled (“1” also works)

Records
This section contains information about record types. Records may be placed in any order
within the file, although a logically intuitive file structure aids human readability. The DDRx
wizard considers all records as optional, but some records are required by batch simulation.

{Version versionID}

Identifies the file-version. versionID is a number between zero and infinity.

{Notes

any notes
...
}

The Notes record provides a place for your comments. In the Notes record, comments do
not need to be explicitly designated as comments using comment identifying characters
such as “//” or “/* */”.
The comments in this section are written out to setup files created by the Wizard,
enabling you to create persistent notations.
Because this record is terminated by the ‘}’ character, that character may not appear in
the actual comments, even if it is enclosed by double quotes “ “.
{Project projectFile}

Identifies the HyperLynx project file. This may be either a HYP or PJH file (usually
PJH).

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{Boards

boardID1 = hypFile1;
boardID2 = hypFile2;
...
boardIDn = hypFilen;
}

Identifies the individual boards in a BoardSim MultiBoard project. boardIDn is the

board designator assigned within HyperLynx, such as B00). hypFilen is the BoardSim
HYP file defining the board.
{PartTypes

partType1 = ibisFile1, ibisComponent1;

partType2 = ibisFile2, ibisComponent2;
...
partTypen = ibisFilen, ibisComponentn;
}

Identifies the part types used for the memory controller and DRAM components.
partTypen is the part name or part type. ibisFilen is the IBIS file modeling the
component. ibisComponentn identifies the [Component] record within the IBIS file.
{Parts

partRef1 = partType1;
partRef2 = partType2;
...
partRefn = partTypen;
}

Identifies the parts used for the memory controller, DRAM, clock PLL and
address/command/control register components.
partRefn is the component’s reference designator, such as U37.
partTypen is ideally a part type declared in the PartTypes record. In MultiBoard
projects, the partRefn identifier may be in either Uyy_Bxx or Bxx:Uyy format,
specifying the board ID as well as the local reference designator. BoardSim uses the

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Uyy_Bxx format, while the DDRx Wizard itself displays the Bxx:Uyy format. Either
format is acceptable in the setup file.
{Options

optionID1 = optionArgList1;
optionID2 = optionArgList2;
...
optionIDn = optionArgListn;
}

Specifies most of the setup, simulation, and reporting options that can be selected within
the DDRx wizard.
optionIDn is a keyword that identifies the option.
optionArgListn is a list of values for setting the option state (most options are set with a
single value).
Table 31-23 contains the options and their possible values.

Table 31-23. Options and Option Values

Option ID Values Description
ACCTiming Disabled Specifies whether to include address,
1T command, and control signals in
2T batch simulations, and the timing for
the address and command signals, if
enabled (control signals always use
1T timing, if enabled).
Corners None IC Model corners. The value can
Slow either be None, or any combination
Typical of Slow, Typical, and Fast.
Fast
Crosstalk Disabled Crosstalk simulation effects. If
Geometric, minLength, maxDistance enabled, it must be specified as either
Electrical, minVoltage Geometric or Electrical, along with
the appropriate parameters.

minLength and maxDistance are

length values with a default unit-type
of mils.

minVoltage has a default unit-type of

millivolts.

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Table 31-23. Options and Option Values (cont.)

Option ID Values Description
DataSimulations Both Specifies whether to simulate the
ReadOnly Data signals (also qualified by
WriteOnly DataTiming = Enabled) during all
data transfer cycles or just for read or
write cycles.

The default value is Both.

DataStrobes SingleEnded Specifies the signal types for the Data
Differential Strobe (DQS) signals. This option is
relevant for only DDR2 interfaces;
DDR is always single-ended, and
DDR3 is always differential.
DataTiming Disabled Specifies whether to include data
Enabled signals (DQ and DM) in the batch
simulations.
DDRType DDR Indicates which type of DDR devices
DDR2 are used in the interface. If this entry
DDR3 is missing, the default value of DDR2
is used.
DIMMType UDIMM If DIMMs are used, this indicates the
RDIMM type of DIMM.

UDIMM is Unbuffered
RDIMM is Registered
MaxOvershoot Default Maximum voltage a signal can
maxVoltage briefly exceed Vdd/VddQ or
Vss/VssQ.

If Default, JEDEC specified values

are used.

The default units for non-default

values is millivolts.
MaxRunTime value Specifies the maximum run-time per
net during simulation. value is a
number with the default unit-type of
minutes.
SaveAll Enabled Enabled specifies to save all
Disabled simulation waveforms to disk.
SimLoss Enabled The SimLoss and SimulateLoss
SimulateLoss Disabled keywords are interchangeable.

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Table 31-23. Options and Option Values (cont.)

Option ID Values Description
SimRuns Batch Specifies whether to run batch
SimulationRuns Audit simulation only, audit only, or both
Batch, Audit batch simulation and audit.

The SimRuns and SimulationRuns

keywords are interchangeable.
Skew value Specifies the maximum skew
between non-strobe/clock drivers.

value is a number with default unit-

type of picoseconds.
Stimulus PRBS, bitOrder Specifies the stimulus for non-
Custom, bitStimulusFile strobe/clock nets.

If PRBS, bitOrder is a number from 3

to 15.

If Custom, bitStimulusFile identifies

a HyperLynx BIT file containing the
stimulus bit pattern, which is a
sequence of 1 and 0 characters. See
“Specifying Bit Patterns with a Text
Editor” on page 549.
StrobeTiming Enabled Specifies whether to include clock-
Disabled to-data strobe skew in batch
simulation.
Thresholds Vtt Specifies which receiver voltage
All thresholds to use in timing
measurements.
VaryRef Enabled Specifies whether or not to vary the
Disabled voltage reference values with IC
corners during simulation.
XLSAutoFormat Enabled Specifies whether to format errors in
Disabled red characters.
{DataRate bitRate}

Specifies the data bit rate, in Mbps.

Standard bit rates for DDR interfaces include 266, 333, and 400 Mbps.
Standard bit rates for DDR2 interfaces include 400, 533, 667, 800, and 1066 Mbps.

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Standard bit rates for DDR3 interface include 800, 1066, 1333, and 1600 Mbps.
A bit rate value that is different than one of these values will show up in the Wizard as a
Custom rate.
{Controller controllerRefDes}

Specifies the reference designator for the memory controller component. This value is a
global value. In a MultiBoard project, the reference designator should include the board
ID as well as the local reference designator. For example, either B00:U100 or
U100_B00. Ideally, this reference designator will match a component declared in the
Parts record.
{DRAM
Slot[1] = boardID1;
Slot[2] = boardID2;
Rank[1,1] = refDesList1_1;
Rank[1,2] = refDesList1_2;
Rank[2,1] = refDesList2_1;
Rank[2,2] = refDesList2_2;
PLL[1] = pllRefDesList1;
PLL[2] = pllRefDesList2;
Register[1] = regRefDesList1;
Register[2] = regRefDesList2;
}

Specifies the reference designators used for the DRAM components, and for clock PLL
and address/command/control registers used in registered designs. Alternative record-
type keywords DRAMs and DRAMRanks may be used interchangeably with the
DRAM keyword. The DRAM record supports the following sub-records:
• Slot—Identifies a particular DIMM module, if used, in a MultiBoard project. There
can be up to two DIMM modules, or slots, in a DDR2/3 interface. If the design does
not use DIMM modules, the Slot sub-records should be omitted. Note that a single-
board project does not use DIMM modules, but still contains logical slots; however,
these are not explicitly declared in the DRAM record.
• Rank—Identifies a group of DRAM components that function together during
read/write data transfer cycles. For DIMM modules, this is also commonly referred
to as a side of a particular slot. Each Rank sub-record is specified as part of a [slot,
side] array. A complete DDR2/3 interface may contain up to two slots with each slot

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containing up to two sides for a total of four ranks. The slots and sides may be
logical rather than physical if the design does not use DIMMs. The reference
designators in each refDesList are local to the boardID containing the parts. Ideally,
the global reference designators that can be created from combining Slot and Rank
sub-record information (boardID:refDes) will match components declared in the
Parts record.

Note
PLL and Register sub-records are only valid if the DIMMType sub-record of the Options
record is set to RDIMM.

• PLL—Identifies a set of clock PLL components (typically, there is only one) that
distributes clock signals to the DRAMs and registers in the designated slot.
• Register —Identifies a set of address/command/control register components that
distribute these signals to the DRAMs in the designated slot.
The reference designators in each refDesList are local to the boardID containing the
parts (identified in the Slot sub-record). Ideally, the global reference designators that can
be created from combining Slot with PLL or Register sub-record information
(boardID:refDes) will match components declared in the Parts record.
{ClockNets clkNetList}

Specifies the clock nets (CK) used in the DDR/2/3 interface between the memory
controller and DRAM components. As these nets are always differential, specify only
the positive net of the pair. The net names should be local names within the board
containing the memory controller; in fact, these nets should be physically attached to the
controller.
{DataNets

dataStrobeNet1 : dataMaskNet1 | dataNetList1;

dataStrobeNet2 : dataMaskNet2 | dataNetList2;

...
dataStrobeNetn : dataMaskNetn | dataNetListn;

Specifies each dataStrobeNet (DQS) and the associated dataMaskNet (DM) and
dataNets (DQ) used in the DDR/2/3 interface. Each sub-record declares a unique data
strobe net and associates it with a particular data mask net and a group of data bit nets.
Because the data strobe nets may be implemented using differential pairs, specify only
the positive net of the pair in this case. The net names should be local names within the
board containing the memory controller; in fact, these nets should be physically attached
to the controller. The dataStrobeNet identifier is separated from the dataMaskNet

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identifier by a colon : character (an equal sign = character will also work, for
consistency with other sub-record types). The dataMaskNet identifier is separated from
the dataNetList by a vertical bar | character. The dataNetList is a list of nets, separated
by commas , and terminated with a semicolon ; .
{AddrCommNets addrCommNetList}

Specifies the address nets (A, BA) and command nets (RAS, CAS, WE) used in the
DDR/2/3 interface between the memory controller and DRAM components. The net
names should be local names within the board containing the memory controller; in fact,
these nets should be physically attached to the controller. These nets differ from control
nets in that they may be simulated with either 1T or 2T timing (you should verify that
the controller is actually capable of operating in the designated mode).
{ControlNets addrCommNetList}

Specifies the control nets (CKE, ODT, S) used in the DDR/2/3 interface between the
memory controller and DRAM components. The net names should be local names
within the board containing the memory controller; in fact, these nets should be
physically attached to the controller. These nets differ from address and command nets
in that they are always simulated with 1T timing.
{ODTModels

ibisComponent1 = modelSelectorList1;
ibisComponent2 = modelSelectorList2;
...
ibisComponentn = modelSelectorListn;
partRef1 = modelSelectorListR1;
partRef2 = modelSelectorListR2;
...
partRefn = modelSelectorListRn;
}

Identifies the IBIS [Model] choices for IBIS [Model Selector]s within IBIS
[Component]s for signals that employ ODT (DQS/DQS#, DQ, and DM). IBIS
[Component]s should be declared in the PartTypes record. There are two forms for
specifying the [Model] choices:
Collectively, by specifying the IBIS [Component] name (ibisComponent), which
applies the [Model] choices to all devices that have the same IBIS [Model] and
[Component] values.

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Individually (partRef), which applies the [Model] choices to the particular device
with the specified reference designator, such as U37.
For either form, modelSelectorList is a list of IBIS [Model Selector]s and the desired
[Model] choices for ODT disabled and ODT enabled for each. The format of each item
in the modelSelectorList is:
modelSelectorName(odtDisabledModelName, odtEnabledModelName)
where:
modelSelectorName” is a [Model Selector] name
odtDisabledModelName and odtEnabledModelName are [Model] names that are
valid choices for that [Model Selector]. If either odtDisabledModelName and/or
odtEnabledModelName are blank (that is, missing), those specifications will appear
in the DDRx wizard as <none selected>. If only one [Model] name appears within
the parentheses (with no comma separator), that [Model] choice will be used for
both ODT disabled and ODT enabled settings.
In MultiBoard projects, the partRefn identifier may be in either Uyy_Bxx or Bxx:Uyy
format, specifying the board ID as well as the local reference designator. BoardSim uses
the Uyy_Bxx format, while the DDRx wizard itself displays the Bxx:Uyy format. Either
format is acceptable in the setup file.
If the IBIS Component name is common to multiple IBIS model files, the
ibisComponent designator should be of form:
ibisModelFileName[ibisComponentName]
where:
ibisModelFileName is the name of the IBIS model file.
ibisComponentName is the component identifier.
First-generation DDR devices do not allow ODT, so this record is ignored in that case.
{ODTBehavior

Read[1] = ODTEnabledList;
Read[2] = ODTEnabledList;
Write[1] = ODTEnabledList;
Write[2] = ODTEnabledList;
}

Specifies the devices that have ODT enabled for a given operation. This record is
optional, and only needs to be specified if there are non-default ODT behaviors. There
are two types of sub-records defined within the ODTBehavior record, which specify a

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particular DRAM operation: Read and Write. Each Read or Write sub-record specifies
the devices that have ODT enabled for that operation, with the index number within the
brackets specifying a particular DRAM slot, that is, either 1 or 2.
To be consistent, only ODT behaviors for operations possible given the DRAM
configuration (number of slots and sides filled with actual devices) should be specified.
In other words, do not specify ODT behavior for a write operation to slot 2, if slot 2 is
empty. Similarly, do not enable Rank[2,1] or Rank[2,2] if slot 2 is empty.
The ODTEnabledList consists of from zero to five items, indicating which set of devices
have ODT enabled for the operation. If there are no items in the list, none of the devices
have ODT enabled. These items are specified by the following keywords:
Controller—Can appear only once in the list, indicating that the controller device
has ODT enabled.
Rank[slot,side]—Indicates that all DRAM devices in this rank have ODT
enabled.
For example, the default ODT behaviors for a DRAM configuration with all four ranks
filled (2R/2R) could be specified as follows (since this is the default, the record could
also be omitted entirely):
{ODTBehavior
Read[1] = Controller, Rank[2,1];
Read[2] = Controller, Rank[1,1];
Write[1] = Rank[2,1];
Write[2] = Rank[1,1];
}
First-generation DDR devices do not allow ODT, so this record is ignored in that case.
{TimingModels

partType1 = modelFile1, speedGrade1;

partType2 = modelFile2, speedGrade2;
...
partTypen = modelFilen, speedGraden;
partRef1 = modelFileR1, speedGradeRn;
partRef2 = modelFileR2, speedGradeRn;
...
partRefn = modelFileRn, speedGradeRn;
}

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Identifies the timing model files and speed grades for the controller, DRAM, clock PLL
and address/command/control register devices. There are two forms for specifying the
model choices:
• Collectively (partType), by specifying the part type, which applies the model and
speed grade choices to all devices that have the same part type.
• Individually (partRef), which applies the model and speed grade choices to the
particular device with the specified reference designator, such as U37.
The partType and partRef designators should be declared in the Parts record.
For either form, modelFile is the name of a timing model file. If this field is a null string
““ or missing, the default timing model for the DDR-type (DDR, DDR2, or DDR3) and
part type (controller, DRAM, etceteras.) is used.
speedGrade identifies the speed grade value for the component, using the following
designators: DDR_266, DDR_333, DDR_400, DDR_533, DDR_667, DDR_800,
DDR_1066, DDR_1333, or DDR_1600. The parser will also accept DDR2 and DDR3
permutations of these designators, such as DDR2_667 and DDR3_1600. If the
speedGrade field is a null string ““ or missing, the default speed grade for the DDR-type
and specified data rate is used.
In MultiBoard projects, the partRefn identifier may be in either Uyy_Bxx or Bxx:Uyy
format, specifying the board ID as well as the local reference designator. BoardSim uses
the Uyy_Bxx format, while the DDR/2/3 Wizard itself displays the Bxx:Uyy format.
Either format is acceptable in the Setup file.
Because the modelFile and speedGrade fields can both be null strings or omitted
entirely, if you want to use default timing models and speed grades, the TimingModels
record can be optionally omitted or left blank.
{DisabledNets disabledNetList}

Specifies the data, data mask, address, command and control nets to exclude from batch
simulations. The net names should be local names within the board containing the
memory controller, matching nets specified in the DataNets, AddrCommNets and
ControlNets records. These nets can also be excluded as a group by setting the
DataTiming and/or ACCTiming sub-records to disabled in the Options record.
{WriteLeveling

dataStrobeNet1 = slot1Delay, slot2Delay;

dataStrobeNet2 = slot1Delay, slot2Delay;
...
dataStrobeNetn = slot1Delay, slot2Delay;
}

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Associates write-leveling delays with data strobes for DDR3 interfaces. dataStrobeNetn
should be a data strobe net identified in the DataNets record. The slot1Delay and
slot2Delay fields are the delays between the rising edge of the controller's CK output
and the identified data strobe (in picoseconds), during a write to DRAM data cycle, to
the identified slot. Typically, the controller hardware determines the proper delay
dynamically during an initialization cycle, but this record allows you to specify a
particular delay for simulation and analysis purposes. You should limit these values to
delays actually supported by the specific memory controller hardware.
{End}

Specifies the end of the setup file. This is an optional record, and typically unnecessary,
since the parser recognizes the end of the file without it.

Example DDRx Setup File

The following listing illustrates most of the syntax and how record types used in a setup file.
The comments shown are similar to those automatically written by the Wizard, although the
exact commentary may change.

// HyperLynx DDR2 Setup File

{Version 1.00}

// The HyperLynx BoardSim project file

{Project "Two_board_set_multi_brd.pjh"}

// Multiboard project board list

// boardName = HYPFileName;
{Boards
B00 = "ibm_2dimm_5inch10mil.hyp";
B01 = "PC2-6400_PC2-UDIMM_V10_RC_E0_20040902.hyp";
B02 = "PC2-6400_PC2-UDIMM_V10_RC_E0_20040902.hyp";
}

// Controller and DRAM part types used in the DDR2 simulations

// partName = IBISModelFile, IBISComponentName;
{PartTypes
IBM__2DIMMCHIPSET10MIL = "ddr2_1430_weak_800.ibs",
"IBM_CHIPSET_1430_WEAK_800";
“DDR2_96B_X8-BASE-FBGA96_12X21 = "u37y_800_jedec_dim.ibs",
"DDR2_96B_X8-BASE-FBGA96_12X21";
}

// Controller and DRAM part instances used in the DDR2 simulations

// ...using Bxx:Uyy syntax instead of BoardSim's Uyy_Bxx format
// ...because that's the format that the DDR2 Wizard displays...
{Parts
B00:U100 = "IBM__2DIMMCHIPSET10MIL";
B01:U1 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U2 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U3 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U4 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U5 = "DDR2_96B_X8-BASE-FBGA96_12X21";

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B01:U6 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U7 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U8 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U10 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U11 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U12 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U13 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U14 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U15 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U16 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B01:U17 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U1 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U2 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U3 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U4 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U5 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U6 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U7 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U8 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U10 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U11 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U12 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U13 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U14 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U15 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U16 = "DDR2_96B_X8-BASE-FBGA96_12X21";
B02:U17 = "DDR2_96B_X8-BASE-FBGA96_12X21";
}

// Setup and Simulation Options

{Options
DataTiming = Enabled; // Disabled or Enabled
ACCTiming = 1T; // Disabled, 1T or 2T
StrobeTiming = Enabled; // Disabled or Enabled
Thresholds = All; // Vtt or All

// Non-clock/strobe net stimulus; Values:

// = PRBS, BitOrderValue;
// = Custom, BitStimulusFileName;
Stimulus = PRBS, 7; // PRBS or Custom

// Crosstalk simulation effects; Values:

// = Disabled;
// = Geometric, MinParallelLength, MaxAgressorDistance;
// = Electrical, MinCoupledVoltage;
Crosstalk = Disabled; // Disabled, Geometric or Electrical

Skew = 100.0 pS; // Maximum skew between non-clock/strobe drivers

Corners = Slow; //IC model corners: None, Slow, Typical, and/or Fast
VaryRef = Disabled; // Disabled or Enabled
SimulateLoss = Enabled; // Disabled or Enabled
IncludeVias = Enabled; // Disabled or Enabled
MaxRunTime = 5.0 Min; // Maximum run-time per net
SimulationRuns = Batch; // Batch and/or Audit
XLSAutoFormat = Enabled; // Disabled or Enabled
SaveAll = Enabled; // Disabled or Enabled
DDRType = DDR2; // DDR, DDR2, or DDR3
DataStrobes = Differential; // Single or Differential

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// Data rate of the interface (MHz)

// ...Standard DDR2 rates include 400, 533, 667, 800, and 1066
{DataRate 400.00}

// Controller part identifier

{Controller B00:U100}

// DRAM Rank (Slot/Side) part identifiers---

// ...A "Rank" is a group of DRAM components that functions together
// ...A full DDR2 interface may contain up to four "Ranks," which
typically
// consists of two "Slots" (or DIMMs), each with two "Sides"
// ...A "Slot" identifies a board (DIMM) in a multiboard implementation
// ...Here, each "Rank" grouping is an element of a [Slot,Side] array
{DRAMRanks
Slot[1] = B01;
Slot[2] = B02;
Rank[1,1] = U1:8;
Rank[1,2] = U10..17;
Rank[2,1] = U1..8;
Rank[2,2] = U10..17;
}

// Data Nets---
// ...All Data-type Nets are assumed to be on the same board as the
Controller
// ...Only the (+) side of a differential strobe pair is listed
// ...Format:
//DataStrobeNet : DataMaskNet | DataNetList;
//where the DataMaskNet and the data nets in DataNetList are all
//associated with DataStrobeNet
{DataNets
DQS0+: DM0 | DQ0..7;
DQS1+: DM1 | DQ8..15;
DQS2+: DM2 | DQ16..23;
DQS3+: DM3 | DQ24..31;
DQS4+: DM4 | DQ32..39;
DQS5+: DM5 | DQ40..47;
DQS6+: DM6 | DQ48..55;
DQS7+: DM7 | DQ56..63;
DQS8+: DM8 | CB0..7;
}

// Clock Nets---
// ...All Clock Nets are assumed to be on the same board as the Controller
// ...Only the (+) side of a differential clock pair is listed
{ClockNets CK0..5+ }

// Address/Command Nets---
// ...All nets are assumed to be on the same board as the Controller
// ...Address and Command nets differ from Control nets in that Control
nets
// always use 1T timing, whereas Address and Command nets may use either
// 1T or 2T timing.
// ...Address/Command nets include:
// Address: A0..n

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// Bank Address: BA0..n

// Command: RAS, CAS, WE
{AddrCommNets A0..15, BA0..2, CAS, RAS, WE }

// Control Nets---
// ...All nets are assumed to be on the same board as the Controller
// ...Address and Command nets differ from Control nets in that Control
nets
// always use 1T timing, whereas Address and Command nets may use either
// 1T or 2T timing.
// ...Control nets include:
// Chip Select: S0..n
// Clock Enable: CKE0..n
// On-Die Termination: ODT0..n
{ControlNets CKE0..3, ODT0..3, S0..3 }

// ODT Models---
// ...ODT Models can be specified either by:
// IBIS [Component] name -- Applies models to a group of parts; the
IBIS
// [Component] name should be one declared in the "PartTypes"
record.
// Part Reference Designator -- Applies models to a single part; the
reference
// designator should be one declared in the "Parts" record.
// ...Generally, it is easier to specify models by IBIS [Component] name,
as all parts
// defined by a common IBIS model would typically use the same ODT model
// selections.
// ...Formats:
// ibisComponentName = ibisModelSelectorList;
// partRefDes = ibisModelSelectorList;
// ...where:
// "ibisComponentName" is the IBIS [Component] name
// "partRefDes" is an individual component's reference designator
// "ibisModelSelectorList" is a list of IBIS [Model Selector]
specifiers.
// ...Each [Model Selector] specifier is of the form:
// msName(odtDisModel,odtEnModel)
// ...For example, "DQS(NO_ODT_MODEL,ODT_75_MODEL)"
{ODTModels
"DDR2_96B_X8-BASE-FBGA96_12X21" = DQ(DQ_FULL_800,
DQ_FULL_ODT75_800);
"IBM_CHIPSET_1430_WEAK_800" = DQ(BPVARDATA_30_800),
DQS(BPVARDATA_30_800);
B01:U10 = DQ(DQFULL_800, DQFULL_ODT75_800);
}

// ODT Behavior
// ...This needs to be specified only for non-standard behaviors
// ...Format:
// operation[Slot#] = EnabledDeviceList;
// ...where:
// "operation" is either "Read" or "Write"
// "EnabledDeviceList" is a list of devices that have ODT enabled
// for the operation:
// Controller -- the Controller device
// Rank[slot,side] -- DRAM devices in Rank[slot,side]

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// ...If a particular relevant operation is not specified, "standard"

behavior is
// assumed.
// (refer to Micro Technology document TN-47-07, Tables 2 and 3)
{ODTBehavior
Write[1] = Rank[2,2];
Write[2] = Rank[1,1];
Read[1] = Controller, Rank[2,1];
Read[2] = Controller, Rank[1,1];
}

// Timing Models---
// ...Timing Models can be specified either by:
// Part Type -- Applies models to a group of parts; the Part Type
// identifier should be one declared in the "PartTypes" record.
// Part Reference Designator -- Applies models to a single part; the
reference
// designator should be one declared in the "Parts" record.
// ...Generally, it is easier to specify models by Part Type, as all parts
defined
// by a common type would typically use the same timing model
selections.
// ...Formats:
// partType = timingModelFile, speedGrade;
// partRefDes = timingModelFile, speedGrade;
// ...where:
// "timingModelFile" is the timing model file name
// ...If this field is "", the default model file is used
// "speedGrade" is the speed grade of the part, identified by one
of:
// DDR_400, DDR_533, DDR_667, DDR_800, or DDR_1066
{TimingModels
" IBM__2DIMMCHIPSET10MIL " = "", "DDR_667";
" DDR2_96B_X8-BASE-FBGA96_12X21" = "", "DDR_667";
}

// Disabled Nets---
// ...All nets are assumed to be on the same board as the Controller
// ...These nets are from the Data, Data Mask, Address, Command and
Control
// net groups, that are excluded from simulation
{DisabledNets
RODT0..3;
}

{End}

IBIS Specification
The specification is installed with the product. See
\MentorGraphics\<release>HL\SDD_HOME\hyperlynx\ibis<version>.txt.

PAK File Specification

HyperLynx Resistor/Capacitor Pack (PAK) File Format, Version 1.02B

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December 29, 1994

This topic contains the complete and official specification for the HyperLynx package-
modeling (.PAK) format for describing the electrical connections in a resistor or capacitor
network package. The .PAK format can be read by the HyperLynx BoardSim signal-integrity
software, and allows users to add new definitions to BoardSim's default R/C-package library.

This topic contains the following:

• “Overview of PAK File Format” on page 1328

• “General Syntax Notes” on page 1328
• “Keyword PAK” on page 1329
• “Keyword VERSION” on page 1330
• “Keyword PACK” on page 1330
• “Keyword END” on page 1334

Overview of PAK File Format

{PAK}
{VERSION=number [comment]}
{PACK=name [comment]
(package information) [comment]
(package information)
...
(package information)
}
{PACK=name
(package information)
(package information)
...
(package information)
}
...more packages...
{PACK=name
(package information)
(package information)
...
(package information)
}
{END}

General Syntax Notes

Italicized fields are to be filled in with appropriate values.

Square brackets [ ] denote optional parameters.

All subrecords [lines beginning with '('] must be on a single line.

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Curly braces { } can be separated from keywords and record ends by white space; the right
brace } can be on the same line as the last subrecord or on the next line.

Parentheses ( ) can be separated from keywords and record ends by white space; must be on the
same line as the subrecord.

If on the same line as other text, comments must be separated by at least one white space from
the preceding text. If an entire line is a comment, it can begin in column 1, but must contain not
contain the character '}'.

The maximum allowed line length is 180 characters.

Lines can be terminated by CR, LF, CR-LF, or LF-CR.

White space is defined as space, horizontal tab, vertical tab, linefeed, form feed, or carriage
return.

Any characters are allowed in a name, except white-space characters.

Numeric values can be followed by an exponent of the form

exxx or Exxx
where xxx is any integer value, positive or negative.
All numeric values can be followed by alphabetic scaling factors:

M=mega (1,000,000x)
K or k =kilo (1,000x)
m=milli (0.001x)
u or U=micro (1e-6x)
n or N=nano (1e-9x)
p or P=pico (1e-12x)
Suffixes may be separated from their numeric values by white space.

Scaling suffixes may be followed by other alphanumeric characters, e.g., uH or pF; the
additional characters are terminated by white space

Keyword PAK
Format:

{PAK}

• PAK identifies the file format as .PAK to BoardSim

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• required record; must be the first non-blank line in file

• only one PAK record allowed per file

Keyword VERSION
Format:

{VERSION=number [comment]}

• VERSION specifies the version of the file format

• number specifies the .PAK-file version number
• required record; must be the second non-blank line in file
• only one VERSION record allowed per file
Example Records:

example 1:

{VERSION=1.02}

example 2:

{VERSION=1.02 new definition added by Dave S.}

Keyword PACK
Format:

{PACK=name [comment]
(STYLE=package_style) [comment]
(SHAPE=package_shape) [comment]
(TOTAL_PINS=number) [comment]
(PIN_PAIR=pin_name,pin_name[,pin_name]) [comment]
(PIN_PAIR=pin_name,pin_name[,pin_name]) [comment]
...more pin pairs...
(PIN_PAIR=pin_name,pin_name[,pin_name]) [comment]
(PIN_LOC=pin_name,location_number)
(PIN_LOC=pin_name,location_number)
...more pin locations...
(PIN_LOC=pin_name,location_number)
}

• PACK identifies a resistor- or capacitor-package record

• must be at least one PACK record per PAK file
• name is the package's name; if it exceeds 20 characters, it will be truncated
• three different subrecords must follow: STYLE, TOTAL_PINS, and PIN_PAIR

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• subrecords must be in the specified order, i.e., first STYLE, then TOTAL_PINS, the
PIN_PAIR

STYLE Subrecord
• STYLE record defines the package's component and connection style
• package_style specifies the package's style; valid values are:
o R_SERIES
o R_PULLUP
o R_PULLUP_PULLDOWN
o C_SERIES
o C_PULLUP
• R_xxx specifies a resistor package;
• C_xxx specifies a capacitor package
• x_SERIES specifies that each element in the package has two independent pins, i.e., is
independent of the other elements;
• x_PULLUP specifies that each element in the package has one independent pin and one
pin in common with the other elements;
• x_PULLUP_PULLDOWN specifies that each element in the package has one
independent pin and two pins in common with the other elements

SHAPE Subrecord
• SHAPE record defines the package's physical shape
• package_shape specifies the package's shape; valid values are:
o DIP
o SIP
DIP specifies a dual-in-line package; SIP specifies a single-in-line

TOTAL_PINS Subrecord
• TOTAL_PINS record specifies the total number of pins on the package
• number must be a positive integer

PIN_PAIR Subrecord
• PIN_PAIR record specifies the pairing of two or three pins on a package

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• pin_name is the pin's name; can be any valid name string (typically an integer number,
but can be alphabetic; if it exceeds 5 characters, it will be truncated)
• all styles except R_PULLUP_PULLDOWN allow two pin_name fields;
R_PULLUP_PULLDOWN requires three pin_name fields
• for x_SERIES styles, both pin_name fields are for independent pins;
o for x_PULLUP styles, the first pin_name field is for the independent pin and the
second is for the common pin;
o for the R_PULLUP_PULLDOWN style, the first pin_name field is for the
independent pin, the second is for the common pull-up pin, and the third is for the
common pull-down pin

PIN_LOC Subrecord
• PIN_LOC record specifies the physical position of each pin on the package
• pin_name is the pin's name; must match a name specified in a PIN_PAIR record
• location_number is an integer number that specifies the named pin's position on the
package, according to the following rules:
o if the package shape is SIP and the package has n pins, the pin names must be
numbered from 1 to n with 1 defined as the top-most pin, n as the bottom-most pin;
o if the package shape is DIP and the package has n pins, the pin names must be
numbered from 1 to n with 1 in standard DIP style: pin 1 in the upper left-hand
corner, pin n as the pin in upper right-hand corner
• the PIN_LOC information is used for drawing the package's internal connections; if
missing, the internal connections are not drawn when the package is displayed in
BoardSim's user interface
• the PIN_LOC records must come AFTER the PIN_PAIR records; if a PIN_LOC record
for a pin comes before the PIN_PAIR record for that pin, the .PAK file is considered to
have a syntax error
• each STYLE, TOTAL_PINS, or PIN_PAIR record must be on a single line
• every pin on a package must be mentioned at least once in a PIN_PAIR pin_name field;
independent pins can be mentioned only once; common pins can be mentioned multiple
times
Example Records

example 1:

{PACK=R_16_SER_SIP 16-pin, series-style DIP resistor

(STYLE=R_SERIES) package
(SHAPE=DIP)

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(TOTAL_PINS=16)
(PIN_PAIR=1,16)
(PIN_PAIR=2,15)
(PIN_PAIR=3,14)
(PIN_PAIR=4,13)
(PIN_PAIR=5,12)
(PIN_PAIR=6,11)
(PIN_PAIR=7,10)
(PIN_PAIR=8,9)
(PIN_LOC=1,1)
(PIN_LOC=2,2)
(PIN_LOC=3,3)
(PIN_LOC=4,4)
(PIN_LOC=5,5)
(PIN_LOC=6,6)
(PIN_LOC=7,7)
(PIN_LOC=8,8)
(PIN_LOC=9,9)
(PIN_LOC=10,10)
(PIN_LOC=11,11)
(PIN_LOC=12,12)
(PIN_LOC=13,13)
(PIN_LOC=14,14)
(PIN_LOC=15,15)
(PIN_LOC=16,16)
}

example 2:

{PACK=cap_9_comm_sip 9-pin, pull-up-style SIP capacitor

(STYLE=C_PULLUP) package, with alpha pin names
(SHAPE=SIP)
(TOTAL_PINS=9)
(PIN_PAIR=B,A) pin A is to the common pull-up voltage
(PIN_PAIR=C,A)
(PIN_PAIR=D,A)
(PIN_PAIR=E,A)
(PIN_PAIR=F,A)
(PIN_PAIR=G,A)
(PIN_PAIR=H,A)
(PIN_PAIR=I,A)
(PIN_LOC=A,1)
(PIN_LOC=B,2)
(PIN_LOC=C,3)
(PIN_LOC=D,4)
(PIN_LOC=E,5)
(PIN_LOC=F,6)
(PIN_LOC=G,7)
(PIN_LOC=H,8)
(PIN_LOC=I,9)
}

example 3: a 10-pin, SIP Pullup/pull-down package

{PACK=R_PACK_9SIP
(STYLE=R_PULLUP_PULLDOWN)
(SHAPE=SIP)

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(TOTAL_PINS=10)
(PIN_PAIR=2,1,10) pin 1 is to the common pull-up voltage;
(PIN_PAIR=3,1,10) pin 10 is to the common pull-down voltage
(PIN_PAIR=4,1,10)
(PIN_PAIR=5,1,10)
(PIN_PAIR=6,1,10)
(PIN_PAIR=7,1,10)
(PIN_PAIR=8,1,10)
(PIN_PAIR=9,1,10)
(PIN_LOC=1,1)
(PIN_LOC=2,2)
(PIN_LOC=3,3)
(PIN_LOC=4,4)
(PIN_LOC=5,5)
(PIN_LOC=6,6)
(PIN_LOC=7,7)
(PIN_LOC=8,8)
(PIN_LOC=9,9)
(PIN_LOC=10,10)
}

Keyword END
Format:

{END}

• END identifies the end of the file

SLM File Specification

This topic contains a combined sample file / specification for the HyperLynx version of the
single-line connector model (.SLM) format. The .SLM format can be used to create single-
transmission-line models for connectors. This format is fully compatible with the .SLM files
provided by Amp, Inc. for their single-line models.

See also: “Edit Transmission Line Dialog Box - Connectors Tab” on page 1559

Example File and Specification

* EXAMPLE2.SLM ****************************************
* HyperLynx single-line connector-modeling format
* Files must have a file extension of .SLM
* Files are fully compatible with AMP, Inc. .SLM models
*
* EXAMPLE CONNECTOR MODEL FOR AN ISA BUS CONNECTOR
***************************************************************
* COPYRIGHT 1996, by HyperLynx, Inc. (now Mentor Graphics)
* Catalog Number: EXAMPLE2
* Part Number: 0001
***************************************************************
* ROW A Single t-line model
.SUBCKT EXAMPLE2A-L

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R1 1 1 0.010
T1 1 1 1 1 Z0=51.0 TD=0.080NS
.ENDS EXAMPLE2A-L
* ROW B Single t-line model
.SUBCKT EXAMPLE2B-L
R1 1 1 0.010
T1 1 1 1 1 Z0=48.0 TD=0.090NS
.ENDS EXAMPLE2B-L
* ROW C Single t-line model
.SUBCKT EXAMPLE2C-L
R1 1 1 0.010
T1 1 1 1 1 Z0=51.0 TD=100PS
.ENDS EXAMPLE2C-L
***************************************************************
*
***************** Format specification ************************
*
* COMMENTS:
* Lines that begin with * are comment lines.
*
* COPYRIGHT:
* COPYRIGHT is optional.
* Consists of a comment line including the text 'COPYRIGHT'.
* The text is case insensitive.
* Everything on the line after and including 'copyright'
* is displayed to the user.
*
* CATALOG NUMBER:
* CATALOG NUMBER is optional.
* Consists of a comment line including the text 'catalog n'.
* Therefore any of the following are allowed: 'Catalog Num',
* 'CATALOG NOM', 'CATALOG NUMBER:', etc.
* The text is case insensitive.
* Everything on the line after and including 'catalog'
* is displayed to the user.
*
* PART NUMBER:
* PART NUMBER is optional.
* Consists of a comment line including the text 'part n'.
* The text is case insensitive.
* Everything on the line after and including 'part'
* is displayed to the user.
*
* .SUBCKT:
* .SUBCKT is required.
* More than one .SUBCKT may included. For example, each
* pin on the connector could have a .SUBCKT record, or more
* typically each row in the connector could have a .SUBCKT.
* The beginning of a connector model is indicated by a line
* which starts with a '.' in the first column followed
* immediately by 'SUBCKT'. The .SUBCKT record must
* included a name that ends with the character 'L'. This
* convention is used to indicate it is a transmission _L_ine
* model (not a lumped-element model).
* Any characters after the name are ignored. For example:
* '.SUBCKT testL 1 2' is valid.
*
* R:

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* R is optional.
* Represents the DC resistance of the connector from 'in' to 'out'.
* The line must have the character 'R' in the first column.
* There must be at least 4 parameters on the line separated
* by spaces. The 2nd and 3rd parameters are ignored.
* Examples:
* 'R1 1 1 0.010' is 10 miliohms
* 'R4 1 2 10k' is 10000 ohms
*
* T:
* T is required.
* Consists of the transmission-line model used to represent the
* connector.
* The line must have the character 'T' in the first column.
* There must be at least 7 parameters on the line separated
* by spaces. The 2nd, 3rd, 4th, and 5th parameters are
* ignored. The 6th and 7th parameters must begin with either
* 'TD=' or 'Z0='. Standard units are excepted.
* The impedance and delay are the two critical parameters.
* Examples:
* 'T1 1 1 1 1 Z0=50 TD=40PS' is 50 ohm, 40 picoseconds
* 'T4 1 2 3 4 TD=0.01NS Z0=34' is 34 ohm, 10 picoseconds
*
* .ENDS
* .ENDS is required.
* This represents the end of the SUBCKT.

Application Notes
This topic contains the following:

• “Converting SPICE Models to HyperLynx Databook Format” on page 1336

• “Creating IBIS Models” on page 1342

Converting SPICE Models to HyperLynx Databook Format

Occasionally, you may have no model for a driver IC other than a SPICE model. This
application note describes a relatively simple way in which you can convert a SPICE model—as
long as you can run it in SPICE to extract some basic behavioral information—into a
HyperLynx databook-format (i.e., ".MOD") model.

If you cannot run the steps described below (because, for example, you do not have a SPICE
package capable of compiling and exercising the model), another option is to get the
semiconductor vendor who created the model to run the steps for you.

Another means of converting from SPICE models exists—a university-written SPICE-to-IBIS

translator—but Mentor Graphics believes that for customers, the method described in this
application note is considerably easier and more likely to succeed than using the converter. The
converter is not a commercial product; is poorly documented; has bugs; and is not trivial to
understand or run. The method described here is relatively straightforward.

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SPICE Writer Option

If the conversion process described in this application note is not possible or appealing, a
different way of interfacing BoardSim and SPICE models is by using the HyperLynx SPICE
Writer option. The SPICE Writer converts nets in BoardSim into detailed SPICE netlists. This
enables you to use BoardSim to automatically model all the details of your PCB routing—
including impedance calculations—and end up with a netlist in SPICE to which you can attach
SPICE IC models. In BoardSim Crosstalk, the Writer can even generate netlists that include
trace-to-trace coupling.

For information on the SPICE Writer option, contact Mentor Graphics or your local reseller.

Requirements for Converting

In order to implement the method described in this application note, the following must be true:

• you have access to a version of SPICE that compiles and runs the model you want to
convert
• you can embed the SPICE model in a simple SPICE test circuit that allows the model's
output(s) to be switched high and low
• you can plot the waveform results of such a simulation so you can measure certain
features of the waveforms

Access to a SPICE Simulator

Having a SPICE package and having one that compiles a particular SPICE model are sometimes
different things. Some semiconductor-vendor-supplied SPICE models are developed to run in a
proprietary in-house SPICE package, and may not compile in a commercial package. Others
may require particular versions of Synopsys' HSPICE simulator. If you lack a suitable SPICE
package, fax the semiconductor vendor who created the SPICE model this application note and
have them generate the data for you.

SPICE Test Circuit

The SPICE test circuit required by this application note is simple: it entails adding only a few
extra nodes to the model's SPICE deck. However, in order to understand where in the SPICE
deck to add the new nodes, you need to know which existing nodes represent the input and
output of the buffer you're modeling. In some cases, you may also need to tie certain other input
nodes (e.g., an enable pin) high or low to make the buffer output respond to input stimulus.

If the SPICE model you're trying to convert is complex or poorly documented, request a
schematic diagram or list of key nodes from the semiconductor vendor.

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How This Method Works

The conversion method described below has a simple goal: find out enough about the behavior
of the SPICE model to fill in the parameters in BoardSim's databook (.MOD) model editor. If
you can fill in the required parameters, then the editor will generate a .MOD model for you and
you're ready to simulate.

To open the editor in BoardSim, click Models menu > Edit Databook IC Models.

Many of the parameters in the editor are relatively easy to fill in: you can find them in a data
sheet, or (in a few non-critical cases) even make reasonable guesses. But two important ones are
harder to determine and must usually be found experimentally from the SPICE model:

• driver resistance (high and low)

• driver slew time (high and low)
Notes:

• If you happen to find resistance or slew time—or both—in a data sheet or by some other
non-SPICE means, use them! This application note assumes that you lack both and have
to resort to the SPICE model.
• If the data sheet contains I-V curves for the output buffer, you can convert the curves to
equivalent resistances by drawing a straight line through the linear part of the curve
(after it "turns on" but before it shows any saturation) and measuring the slope DV/DI.

Finding Driver Resistance from a SPICE Model

To make a SPICE model "reveal" a driving resistance, you can make use of a simple fact of
electromagnetics: when a device output drives a transmission line, the transmission line
initially looks exactly like a resistance to ground or Vcc (depending on whether the driver
rises or falls). As soon as a reflection from the end of the transmission line travels back to the
device, the line's behavior changes and becomes more complex, of course; ultimately, the line
looks like an open circuit (i.e., presents no load to the driver).

But the transmission line's behavior before any reflections occur gives a simple and powerful
method of finding a driver's resistance via simple voltage division. A transmission line's
effective resistance during initial switching is equal to its characteristic impedance (Z0).
Therefore, if you load a driver with a transmission line of known impedance and measure—
again, before any reflections occur—how much of the driver's voltage step actually appears in
the transmission line, you can trivially solve for the driver's resistance (see below for formulas).

In practice, to isolate a driver's initial switching behavior into a transmission line from the
behavior after reflections occur, you can simply use a very long transmission line. In the
detailed steps below, for example, a 25-ns line is recommended. Any delay value that is longer
than the entire amount of time for which you simulate in SPICE guarantees that your

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measurements will not be "polluted" by line reflections. Figure 31-19 shows the recommended
transmission line and how it connects to the driver model's output.

Note that driving resistance (and slew time) must be found separately for the high and low
stages of a driver, because the stages are often not balanced. (Usually, the low side has lower
impedance.)

Figure 31-19. Connecting the Test Transmission Line to the Driver Model

Finding Driver Slew Time from a SPICE Model

Unlike driver resistance, driver slew time is not difficult to find—no "tricks" are required. Slew
times can be measured directly from plots of the driver switching high and low into a
transmission-line load. See below for details on making the measurements.

Finding Driver Resistance and Slew Time

To find a driver's high and low resistances and slew times:

First, add a test circuit to the SPICE model

1. Open the driver's SPICE model in a text editor. Find the SPICE node representing the
driver's output. Add a new line to the model that ties the driver output to a simple,
lossless transmission line. Set the line's parameters to delay = 25 ns and characteristic
impedance = 40 ohms. Leave the far end of the transmission line open.
For example, if the driver's output node number is 10, add the following line to the
SPICE model:
T1 10 0 200 0 Z0=40 TD=25ns
This ties one end of a transmission line to the driver output node (node 10); creates a
new, open node at the other end (node 200; use any unused node number); and sets delay
and impedance as described above. The "0's" reference the line to SPICE's global
ground node.
2. Open the driver's SPICE model in a text editor. Find the SPICE node representing the
driver's input. Add a new line to the model that ties the driver input to a ramping voltage
generator. Set the generator's ramp time to 1 ns; make it switch from the driver's low
power supply to the high supply.
For example, if the driver's input node number is 20, add the following line to the SPICE
model:

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V1 20 0 PWL 0ns 0V, 1ns 5V

This ties a 0-ohm (ideal) voltage source to the driver input node (node 20), and switches
the source in a linear ramp from 0V to 5V in 1 ns.
If the driver is inverting, then compensate by reversing the polarity of the input voltage
source.
3. If the driver model requires certain other input nodes to be tied high or low in order for
the output to switch, tie them to Vcc or ground as needed.
Then, run a simulation with the driver switching high, and plot the driver's output node
4. Run a transient SPICE simulation. To ensure that your measurements are not "polluted"
by reflections, set the total simulation time to be greater than the driver's switching time,
but less than the delay time of the transmission line you added in step 1.
For example, if the driver model switches in about 3 ns and you used a 25-ns
transmission line as recommended above, run the transient simulation for 10 ns. This is
long enough to see the driver switch completely, but not long enough for reflections to
return from the line's far end.
5. Plot the simulation voltage versus time at the driver's output node. (This is the voltage at
the near end of the transmission line, not the far, open end.) Set up the plot so that the
switching fills most of the horizontal scale, so you can make an accurate measurement
of the switching time.
Then, from the plot, calculate the driver's high-stage resistance and slew time:
6. Calculate the driving resistance with the following formula:
Rdrv (rise) = Z0 (Vfinal / Vstep - 1),
where Z0 = characteristic impedance of the transmission line (40 ohms),
Vfinal = final DC voltage swing of the driver,
Vstep = voltage swing of the initial step into the transmission line
(ignore signs of the voltage values)
The "final DC swing" means how many volts the driver switches edge-to-edge after any
transmission line reflections die out. For example, for a 5-V CMOS driver, this would be
5V; for a TTL device, about 3.6V.
The "initial step" swing is the lesser number of volts that the driver swings in the
simulation plot. The value is less than the final DC swing because, initially, before
reflections, the voltage divides between the resistance of the driver and the resistance
(characteristic impedance) of the transmission line. See Figure 31-20.
(There's nothing mysterious about this formula—it's a simple voltage division, solved
for the unknown driving resistance.)

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Then, calculate the slew time by measuring the amount of time to go from 10% to 90%
of the plotted waveform voltage.
Finally, re-run the simulation with the driver switching low, and use the same methods
to find the low-side resistance and slew time:
7. Alter the input voltage source to switch in the opposite direction. Run another
simulation and plot the driver-output node (falling edge this time). Use the same formula
as above to calculate the driving resistance; measure the 90% to 10% time as the slew
time. Use absolute values of all quantities, i.e., ignore negative signs.

Figure 31-20. Measuring Vstep

Finding Other Required Model Parameters

Driver resistance and slew time (high and low) are usually the only parameters that must be
derived from the SPICE model. The remaining databook model values can generally be found
in a data sheet, or in a few non-critical cases, can be guessed at. Table 31-24 summarizes how to
find the other parameters in the .MOD model editor.

Table 31-24. .MOD Models - Specifying Other Parameters

Parameter How to Find
Type—high and low Pull down the combo box and choose the appropriate
technology type. For a bipolar device, use the data
sheet's circuit diagram to determine whether a given
stage uses a silicon or Schottky-clamped transistor
(unless ECL). Ignore "ramp"; use "open" for the high
side of an open collector/drain.

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Table 31-24. .MOD Models - Specifying Other Parameters (cont.)

Offset Voltage—high and low Set to 0.0V for any device that switches from supply
rail to supply rail. For stages that do not switch to a rail,
set equal to the amount by which the final voltage is
offset from the rail, minus one diode drop. E.g., for 5-V
TTL, high side offset is 1.4V – 0.4V (0.4 for the
Schottky-diode drop). For most CMOS devices, use
0.0V, since switching is rail-to-rail.
Clamp Diodes, Type and Relatively unimportant for driver models. Can do a
Resistance—high and low SPICE DC sweep above/below power-supply rails to
find diode "resistance," but not usually worth the effort.
Instead, use standard "good guess" values: Type =
Silicon, Resistance = 15 ohms.
Default Power Supply Set to Vcc for all non-ECL devices; to Vee for ECL
devices.
Capacitance Get from data sheet (Cout or "output capacitance"). If
not provided (rare), use 5 pF.

Creating the Model

Once you've collected all the required parameters, you can actually create the databook (.MOD)
model by running BoardSim's model editor; entering the parameters; and saving the model
under an appropriate name in user library.

See also: “Editing MOD IC Models” on page 513

Once the model is saved, you're ready to simulate.

Creating IBIS Models

This application note discusses how to create an IBIS model. Most or all of the information here
can be gleaned from the IBIS specification. However, you may find this discussion easier to
read and follow than the specification alone.

See also: “IBIS Specification” on page 1327

.IBS models are not difficult to create. They are based on data that can be collected from real
devices, or derived from proprietary silicon models. Whatever the data-collection method, the
resulting .IBS model will accurately describe the device's behavior without giving away
proprietary information about the silicon's design.

Before attempting to create a .IBS model, you should read the IBIS specification. The
specification is also available in a text file in the main BoardSim directory, for example
"IBIS32.TXT."

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Elements of an IBS Model

The following elements are required in a .IBS model:

• "default" package R, L, and C

• pin/signal list
• model for each unique I/O type
Models include:

• model type (I/O type)

• component capacitance
• power-supply voltage range
• V-I table for pull-up stage, pull-down stage, GND clamp diode, and Vcc clamp diode
(whichever apply)
• rising/falling slew rate
The following elements are optional in a model:

• package R, L, and C for individual pins

• model polarity; enable polarity
• input thresholds
The next few sections describe the model elements in detail.

Default Package R - L - C
The "default" package resistance, inductance, and capacitance specify a range of values for
modeling the device package. Typical data is required; min and max data are optional. If only
typical data is available, the package R, L, and C can be thought of as the "average" data for the
device package.

BoardSim converts the R, L, and C values into an equivalent transmission line—a good model
for the IC's bond-out structure and package pins.

BoardSim provides the additional flexibility to set the package parameters to 0.0. This indicates
that the data was unavailable; BoardSim will omit the package-model transmission line and
simulate with the silicon data only.

Semiconductor vendors can determine R, L, and C with high-accuracy test equipment or

electromagnetic modeling. End users can get package data from the vendor, use data for a
similar package, or set R, L, and C to 0.0 and omit package modeling entirely.

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Tip: In most situations, package R, L, and C have only a minor effect on simulation.
Don't be afraid to omit them if you have no data.

Example of package R, L, and C:

[Package]
| variable typ min max
R_pkg 250.0m 225.0m 275.0m
L_pkg 15.0nH 12.0nH 18.0nH
C_pkg 18.0pF 15.0pF 20.0pF

Requirement: IBIS keywords (delimited by square brackets []) must begin in the first column
of the actual .IBS file.

Pin-Signal List
The pin/signal list is a list that associates device signal names and pin numbers with simulation
models. There are simulation models for each unique kind of driver or receiver on a device.
Typically, though, many signals will share a single model, e.g., all the address lines on a device
might have the same driver structure.

See the IBIS specification for details on length limits for names, etc.

Example of pin/signal list:

[Pin] signal_name model_name R_pin L_pin C_pin

|
1 RAS0# Buffer1
2 RAS1# Buffer2
3 EN1# Input1
4 A0 3-state
5 D0 I/O1
6 RD# Input2
7 WR# Input2
8 A1 I/O2
9 D1 I/O2
10 GND GND

For details on R_pin, L_pin, and C_pin, see “Package R L C for Individual Pins” on page 1347.

Model Type
Within a simulation model, the model type specifies whether the signal is a driver, a receiver, or
bi-directional.

If bi-directional, BoardSim allows the model's Buffer Direction to be specified as either a driver
or a receiver.

Example of model type:

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Model_type Output

The IBIS specification defines two model types, 3-state and Open_drain, which are not
supported by the modeling constructs in V1.1.

Component Capacitance
The component capacitance specifies a model's silicon die capacitance. It should not include the
capacitance of the device package. Typical data is required; min and max data are optional.

BoardSim allows the component capacitance to be 0.0, if no data is available.

Example of component capacitance:

| variable typ min max

C_comp 12.0pF 10.0pF 15.0pF

Values of 4-5 pF are common for component capacitance and would be a reasonable
approximation in the absence of better data.

Power-Supply Voltage Range

The power-supply voltage range defines the power-supply tolerance over which a model's data
is valid. This should be the same range over which the model's V-I curves and slew rates were
measured. All data is required, though the min and max values can be the same as typical if only
a nominal voltage is supported.

BoardSim allows you to set a driver's supply voltage to a variety of common increments, but
only inside the range specified.

Example of power-supply voltage range:

| variable typ min max

[Voltage range] 5.0V 4.5V 5.5V

V-I Tables
The V-I tables define the V-I curves of the pull-up and pull-down structures in an output driver
and the clamp diodes (if any) to Vcc and GND. A table can be omitted if the corresponding
structure doesn't exist (for example, the pull-up table for an open-drain output, or the Vcc-side
clamp diode for a 74F receiver.)

Typical data is required; min and max data are optional. The IBIS specification disallows more
than 100 points in a table, although BoardSim doesn't bother enforcing this. Linear interpolation
is used to find values that lie between points in the table. Currents for voltages outside the table
are assumed equal to the last point in the table.

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Tip: The last point—that currents for voltages outside the table are assumed to be equal
to the last stated current precludes creating a purely resistive driver by using data points
0,0 and some other V1,I1. For voltages greater than V1, BoardSim will still use current
I1. Be sure you specify V-I points all the way out to where the current begins to saturate.

BoardSim allows changing between best-case, typical, and worst-case signal specs if max,
typical, and min currents are all specified. See Chapter 12, section "What IC Operating Settings
Mean" for details. BoardSim requires at least two points in a V-I table.

Voltages in pull-up and Vcc-clamp-diode tables are relative to Vcc, not ground. See the IBIS
specification for more details.

End users can collect V-I data in the lab by a variety of means. (Don't be afraid to use an
apparatus as simple as a multimeter, power supply, and current-limiting resistor.) Since driver
pull-up and pull-down structures cannot be completely isolated on a real device, some
approximations must be made for the turning-off portion of each stage's curve. Don't bother
with many data points in regions where a curve is fairly linear; BoardSim will automatically
interpolate.

There is some risk of damaging a device while taking clamp-diode data. If you have any
information regarding the diode's fully-on "resistance," construct a table that has zero current
until the correct turn-on voltage, then is linear with the slope dictated by the "on" resistance.

Example of V-I table (for a driver pull-up):

[Pullup]
|
| Voltage I(typ) I(min) I(max)
|
-5.0V 32.0m 30.0m 35.0m
-4.0V 31.0m 29.0m 33.0m
| .
| .
0.0V 0.0m 0.0m 0.0m
| .
| .
5.0V -32.0m -30.0m -35.0m
10.0V -38.0m -35.0m -40.0m

Slew Rates
The slew rates (or "ramp" rates) define the rise and fall times of a driver. Typical data is
required; min and max data are optional. BoardSim allows changing between best-case, typical,
and worst-case signal specs if max, typical, and min slew rates are all specified.

End users can collect slew-rate data in the lab with a high-bandwidth oscilloscope. To remove
package-related effects, slew the driver output into an open load. The slew rates are specified in
the IBIS file as a convenient ratio of the delta-V and delta-T values measured on the scope. The

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IBIS specification recommends measuring between the 20% and 80% points of the driver's
swing.

Example of slew rates:

[Ramp]
| variable typ min max
dV/dt_r 4.2/1.8n 3.5/2.5n 5.0/1.1n
dV/dt_f 2.5/1.5n 2.0/2.3n 3.0/0.8n

Package R L C for Individual Pins

Individual signals can have their own, unique pin R, L, and C values. These appear in the
signal/pin list, and can be specified for any or all of the device's signals. If a signal has no
individual data, the default package R, L, and C is used.

BoardSim allows the flexibility to specify any or all of the values for each signal. E.g., you can
specify a signal-specific C, but leave R and L unspecified (as "NA"); the default R and L will be
used.

For details on package modeling, see “Default Package R - L - C” on page 1343.

Example of individual package R, L, and C:

[Pin] signal_name model_name R_pin L_pin C_pin

|
1 RAS0# Buffer1 200.0m 5.0nH 2.0pF
2 RAS1# Buffer2 209.0m NA 2.5pF
3 EN1# Input1 NA 6.3nH NA
4 A0 3-state
5 D0 I/O1
6 RD# Input2 310.0m 3.0nH 2.0pF

Model and Enable Polarity

The model polarity specifies whether an output signal is inverting or non-inverting. The enable
polarity defines whether an enabling signal is active-high or active-low.

Both of these constructs are read by BoardSim but ignored. They are present in the IBIS
specification for timing-analysis tools.

Input Thresholds
The input thresholds specify the voltages at which an input signal is recognized as a valid 1 or 0.
They are used by BoardSim's Board Wizard to calculate timing delays.

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Technical Background on Crosstalk and Differential Signaling

Technical Background on Crosstalk and

Differential Signaling
This topic provides technical background information on crosstalk, coupled transmission lines,
and differential signals.

• “About Crosstalk and its Causes” on page 1348

• “Forward and Backward Crosstalk” on page 1350
• “Electrical Parameters of Coupled Transmission Lines” on page 1357
• “Propagation Modes-Single-Dielectric versus Layered-Dielectric Traces” on page 1361
• “Differential Signals” on page 1365
• “Terminating Coupled Transmission Lines” on page 1370

Related Topics
• “About Crosstalk in LineSim and BoardSim” on page 1189

About Crosstalk and its Causes

In the simplest terms, crosstalk is unwanted coupling of voltages and currents between
neighboring conductors. On a PCB, the conductors are usually traces, although crosstalk can
also occur in connectors, cables, and component packages. In the classic crosstalk scenario,
when a signal is intentionally driven on one conductor, an unwanted signal also appears on a
neighboring conductor—even though there is no conductive connection between the driven
conductor and its neighbor.

In the remainder of this help, conductors will usually be referred to as "traces," even though
crosstalk can occur between any types of conductors.

Aggressor versus Victim Traces

In a crosstalk scenario, any trace that is intentionally driven (usually by a switching IC output
buffer) and is therefore a potential source of crosstalk on other traces is called an "aggressor."
Any trace that potentially receives unwanted crosstalk from an aggressor is called a "victim."

Note that victim traces are not undriven. Rather, the victim trace is usually in a static state,
"sitting high" or "sitting low" when a nearby aggressor trace is actively switched, and an
unwanted signal appears on the victim. See Figure 31-21. Because of reflection effects, the state
of the victim trace’s static driver is an important factor in the crosstalk waveforms that actually
appear on the victim trace.

See also: “Reflection of Backward Crosstalk from Victim Driver IC” on page 1355

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Figure 31-21. Aggressor and Victim Trace

Of course, it is possible to have a collection of traces (e.g., on a microprocessor bus) all of

which are actively driven and all of which receive unwanted signal components from the other
traces. In this situation, the distinction between aggressor and victim becomes blurred—each
trace is both an aggressor and a victim.

Note that in differential signaling, if the differential pair is tightly coupled, then the two traces
crosstalk with each other just like any two other coupled traces. However, it is not typical to use
the terms "aggressor" or "victim" in a differential case, or even "crosstalk," because the coupled
signals are actually wanted. "Crosstalk" usually refers to unwanted coupling.

Causes of Crosstalk
When a signal travels down a trace, it is an electromagnetic wave that is propagating along the
trace, from the driver end toward the trace’s far end. At points along the trace which the wave
has already reached, transient voltages appear and currents flow, in response to the wave’s
presence.

Tip: A misconception about propagation on a transmission line is that electrons in the

conductor are traveling along the line at the propagation velocity. This is absolutely not
true! Electrons in a conductor spend almost all of their time randomly colliding with
atoms in the conductor lattice; the mean time between collisions is on the order of 10
femtoseconds (1/100th of a ps).As a result, conduction electrons have only a relatively
tiny average forward velocity in the presence of a driving voltage. A typical electron
"drift velocity" in a conductor is on the order of 1 foot/hour. Instead, what moves at the
transmission line’s propagation velocity is the electromagnetic wave that constitutes the
actual signal on the line. Indeed, this wave is what you measure in the lab with an
oscilloscope: a voltage waveform, which is really a measure of the electric field
associated with the traveling electromagnetic wave.

Electromagnetic waves consist of time-changing electric and magnetic fields. The fields are not
confined to the inside of the trace that carries them—in fact, just the opposite: the fields’ energy
exists very predominantly outside the trace.

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Therefore, as a signal propagates along one trace on a PCB, if there are other traces in the
vicinity, they "see" the propagating signal’s electric and magnetic fields. But according to
Maxwell’s equations (which define the behavior of all electromagnetic phenomena, except at
atomic distance scales), time-changing fields induce voltages and currents in conductors—and
thus the fields created by the propagation of a signal along one trace cause signals to appear on
other nearby traces. This is crosstalk.

Forward and Backward Crosstalk

As a signal propagates along an aggressor trace, it causes an unwanted crosstalk signal to appear
on a nearby victim trace. But exactly what kind of signal appears on the victim trace?

The crosstalk signal on a victim trace can be divided into two components: a forward signal and
a backward signal. The following topics describe how these components are created, and what
their properties are:

• “Speedboat Analogy” on page 1350

• “Details of Forward Crosstalk” on page 1351
• “Details of Backward Crosstalk” on page 1353

Speedboat Analogy
The mathematics that governs crosstalk is somewhat complex. However, it’s possible to
describe a few of the qualitative features of forward and backward crosstalk using a physical
analogy: a speedboat traveling across a lake.

When a speedboat travels through water, it disturbs the water in two ways. First, the boat tends
to build up a "pile" of water in front of it; this "bow wake" travels along with the boat. Second,
the boat leaves another wake behind it; this wake stretches out for a long distance behind the
boat. See Figure 31-22.

Roughly speaking, the same thing happens on a victim net when a signal travels along the
aggressor net. Two crosstalk components develop: a forward signal, which travels on the victim
net just "in front" of the aggressor signal, and looks like a "piled-up" voltage; and a backward
signal, which trails out behind the aggressor signal and stretches out in time. See Figure 31-23
and compare to Figure 31-22.

Admittedly, this analogy can’t be pushed very far before it breaks down. For example, the "bow
wake" in front of a speedboat consists of water which is "raised up" by the boat, but flows
around the moving bow—it doesn’t really travel with the boat, as a forward crosstalk signal
does with its aggressor signal. Also, when a boat travels fast enough, i.e., begins "planing," the
bow wake becomes very small—there is no such analogy with crosstalk (unfortunately).
Similarly, the backward wake left by a boat spreads in width, but doesn’t really travel
backward, like a backward crosstalk signal does. Also, a speedboat’s backward wake is
normally much larger in amplitude than its bow wake—not true for crosstalk.

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Nevertheless, this analogy is a useful way to remember that forward crosstalk signals "pile up"
and travel along with the aggressor signal, and that backward signals stretch out in time behind
the signal.

Figure 31-22. Speedboat Analogy for Crosstalk Signals

Figure 31-23. Forward and Backward Crosstalk Signals

Details of Forward Crosstalk

The "speedboat analogy" suggests only the crude details of how a forward-crosstalk signal
behaves: that it travels along "in front" of the aggressor signal that creates it, and that it tends to
be short and "piled up" rather than long and stretched out. This topic gives more detail.

Forward crosstalk appears as a result of two competing coupling mechanisms, one capacitive
and one inductive.

Capacitive Forward Crosstalk

As an aggressor signal travels down its trace, its time-varying electric field tends to generate on
the victim trace a signal whose voltage polarity is the same as the aggressor’s, e.g., a rising edge
on the aggressor trace creates a positive pulse on the victim trace. This crosstalk pulse travels
ahead on the victim trace at the same speed (or set of speeds; see “Propagation Modes-Single-
Dielectric versus Layered-Dielectric Traces” on page 1361 for details) as the aggressor signal

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travels on its trace. Therefore, the pulse doesn’t spread out in time, but rather keeps getting
added to as the aggressor signal travels along and couples more and more energy onto the victim
trace. See Figure 31-24.

Figure 31-24. Capacitive Portion of Forward Crosstalk Signal; Same Polarity as

Aggressor Signal

Notice in Figure 31-24 that the forward crosstalk pulse is not a one-way ramp, like the
aggressor signal, but rather an up-and-down pulse. This occurs because the crosstalk occurs
only when the aggressor signal is changing, i.e., the crosstalk pulse’s shape is related to the
derivative of the aggressor signal’s shape. The time duration of the forward pulse is therefore
equal to the switching time of the aggressor signal.

The height of the crosstalk pulse depends on how strongly the two traces are coupled
capacitively; the coupling strength, in turn, depends on all of the details (geometric and
material) of the PCB cross section in which the traces lie. Calculating the coupling strength is
difficult; in LineSim/BoardSim Crosstalk, that job is performed automatically by the built-in
field solver.

The crosstalk pulse tends to grow in height proportionally to the length over which the two
traces are parallel, i.e., the longer the traces run side-by-side, the higher the crosstalk pulse is.
However, there is a limit to this effect; after a while, the amplitude of the pulse tends to
approach a limiting value. This occurs because the aggressor signal slowly loses energy to the
victim trace, and also because the victim trace couples back to the aggressor.

The height of the crosstalk pulse also tends to increase with the slew rate of the aggressor signal,
i.e., the faster the driver signal switches (and the further it swings), the higher the crosstalk pulse
is. This is the reason that faster-switching driver ICs tend to generate more crosstalk.

Inductive Forward Crosstalk

As an aggressor signal travels down its trace, its time-varying magnetic field also generates a
crosstalk pulse; this is the inductive component of forward crosstalk. In fact, everything
described in the preceding section about capacitive forward crosstalk—generates a pulse on the
victim trace, pulse length equals aggressor switching time, pulse height is approximately
proportional to trace length and to aggressor slew rate—is true of inductive crosstalk.

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But there is one major difference: the polarity of inductive forward crosstalk is opposite that of
capacitive forward crosstalk. See Figure 31-25. This means that in the forward direction, the
capacitive and inductive components of crosstalk are competing, i.e., they tend to cancel each
other out. If the capacitive and inductive coupling strengths are exactly equal, then no forward
crosstalk will occur at all.

Figure 31-25. Inductive Portion of Forward Crosstalk Signal; Opposite Polarity

of Aggressor Signal and Capacitive Crosstalk

In practice, you would rarely see perfect cancellation between the capacitive and inductive
components of forward crosstalk. But for many cross sections, the forward crosstalk is indeed
fairly small, and reverse crosstalk becomes the major concern. This is often the case especially
for traces on stripline layers (i.e., between two planes), because the capacitive coupling is
usually enhanced. But there’s really no way to know for certain without simulating.

Notice that if you do see a forward crosstalk pulse, you can tell from the polarity of the pulse
whether your traces are more capacitively or inductively coupled. If the pulse has the same
polarity as the aggressor signal that created it, capacitive coupling dominates; if the pulse has
the opposite polarity, inductive coupling is stronger. (On PCBs, the inductive coupling is
usually stronger.)

Details of Backward Crosstalk

Backward crosstalk is caused by the same physical mechanisms as forward crosstalk—time-
changing electric and magnetic fields from the aggressor signal, which induce both a capacitive
and inductive signal on the victim trace—but there are several major differences between the
backward and forward signals.

The biggest difference is the time duration of backward signals. Forward crosstalk signals are
short pulses which last only as long as the switching time of the aggressor signal. This occurs
because forward signals travel at the same speed and in the same direction as the aggressor
signal.

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But backward crosstalk is launched in the opposite direction of the aggressor signal’s travel.
Therefore, backward crosstalk does not "pile up" like forward crosstalk does; rather, it "flows
out" behind the aggressor signal, and forms a long pulse. (The "speedboat analogy" may help
make this clearer; backward crosstalk corresponds to the long wake behind the boat.) See
Figure 31-26. Unlike with forward crosstalk, the height of the backward pulse is not related to
the trace length.

Figure 31-26. Shape of Backward Crosstalk Signal

In fact, the time duration of a backward crosstalk pulse is twice the delay length of the aggressor
trace. To see why this occurs, consider Figure 31-27. Suppose you are watching the backward
pulse from the vantage point of the victim-trace driver IC. You see the backward pulse start as
soon as the aggressor signal leaves the driver; when the aggressor signal reaches the far end of
the aggressor trace, it is still generating a backward pulse, and the far end of it doesn’t reach you
until another line-delay’s-worth of time. Hence the total duration of the pulse is two aggressor-
trace line delays.

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Figure 31-27. Length of Backward Crosstalk Signal

Reflection of Backward Crosstalk from Victim Driver IC

Of course, you generally don’t care about crosstalk at a driver IC—it’s receiver ICs that matter.
So in Figure 31-27, why do we even care about the backward pulse? The answer is that driver
ICs, because they are normally low-impedance, reflect rather than absorb crosstalk signals. So
the backward crosstalk pulse that reaches the victim-net driver IC in Figure 31-27 will reflect
back toward the receiver IC. This reflection of backward crosstalk is why it’s critical in
crosstalk simulations to model the victim-trace driver IC. In LineSim or BoardSim simulations,
you would usually do this by applying an IC model to the victim-trace driver location, then
setting it to be "stuck low" or "stuck high" (i.e., driving, but not actively switching). See
Figure 31-28.

Since the driver IC is almost always lower in impedance than the trace itself, the reflection off
the driver usually causes the backward crosstalk pulse to invert.

Because many driver ICs have different impedances when driving high than when driving low,
it is often important to check crosstalk waveforms with the victim-trace IC model in both states,
stuck high and stuck low. However, the low-side impedance of a driver is usually the same as or
less than the high-side impedance, so if you simulate in only one of the two stuck states, "stuck
low" is the best choice (it usually generates a maximum reflection).

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Polarity of Backward-Crosstalk Components

Unlike with the capacitive and inductive components of forward crosstalk, the backward
components have the same polarity. This means that backward crosstalk never cancels itself out
like forward crosstalk sometimes does. The polarity of both backward components is the same
as that of the aggressor signal, e.g., a rising edge on the aggressor trace creates a positive
capacitive and inductive backward pulse. The height of the total backward pulse is the sum of
the two component heights.

However, remember that if you observe the backward pulse at the victim-trace receiver
(assuming the IC positions in Figure 31-26), you are looking at a signal that has been reflected
and inverted by the victim driver IC. So you often observe backward crosstalk as having the
opposite polarity of the aggressor signal. See Figure 31-28.

Figure 31-28. Backward Crosstalk Reflecting Off of Victim Driver IC and

Inverting

Figure 31-29 shows a "classic" crosstalk waveform at the victim-trace receiver IC, for two
traces on a microstrip stackup layer (for which inductive coupling normally dominates
capacitive). The trace and IC topology is assumed to be as Figure 31-28 (i.e., aggressor and
victim drivers on same end, receivers on same end). The waveform interpretation is shown in
Figure 31-29.

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Figure 31-29. Classic Crosstalk Waveform at Victim-Trace Receiver IC

Electrical Parameters of Coupled Transmission Lines

A trace on a PCB can be treated as a mathematical construct called a "transmission line,"
provided that the distance between the trace and a ground-return structure is small compared to
the wavelength of the signals propagating along the trace. For PCBs with solid ground/Vcc
planes, the transmission-line model is usually very accurate. (It may not be for boards with no
planes—single- or double-sided PCBs—or for boards on which the plane layers are "cut" or
otherwise compromised.)

Transmission-line theory does not deal explicitly with electric and magnetic fields. Rather, a
transmission line is defined in terms of the capacitance and inductance that is distributed
uniformly along the length of the line. However, there is a close link between these circuit
quantities and the underlying field theory: capacitance is basically a measure of how much
electric field is produced when a given quantity of charge is placed on a conductor, and
inductance measures the amount of magnetic field that "links" a circuit when a given current
flows in the circuit’s conductor.

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Uncoupled Transmission Lines

The behavior of a single, uncoupled transmission line (providing that loss mechanisms are
ignored) is fairly straightforward. The line’s total capacitance (C) and total inductance (L)
combine to create a propagation delay that is given by:

If you are using L and C per unit length instead, then the above equation must be multiplied by
the length of the transmission line:

where L is the inductance per unit length of the transmission line, C is the capacitance per unit
length of the line, and l is length of the line.

The distributed C and L also create a property called "characteristic impedance," which
determines the ratio of voltage to current that flows in each direction along the line.
Characteristic impedance plays a central role in how the line responds to an initial driver-IC
impulse (i.e., how much voltage "steps" into the line) and how the line generates reflections at
its ends. The characteristic impedance (Z0) is given by:

In the equation for characteristic impedance above, you can use either total or per-unit-length
values of L and C.

In both of these equations, note that C and L are single numeric values. For example, for a
typical 8-inch microstrip transmission line, total C = 16 pF and total L = 84 nH.

Coupled Transmission Lines

Capacitance and Inductance

The mathematics for coupled transmission lines bears strong resemblance to the theory of
uncoupled lines, but there are some important—and surprising—differences. First, the
quantities C and L become matrices instead of being single numbers. For example, the same
microstrip line referred to in “Uncoupled Transmission Lines” on page 1358, if another trace is
placed in parallel with it, 8 mils away, has the following capacitance matrix:

At first glance, you might think this result is wrong, because some of the capacitance values are
negative. It is correct, however.

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Each diagonal value in the matrix represents the capacitance of the corresponding trace when
that trace is charged to 1V and all other traces are grounded. The off-diagonal values in each
column of the matrix represent the capacitances between the 1-V trace and the other traces. But
since the 1-V trace is positively charged, all other traces accumulate negative charge; and since
capacitance is defined as the ratio of charge to voltage (Q/V), their matrix capacitance values
are also negative.

If the concept of negative capacitance bothers you, just ignore the negative signs and
concentrate on the magnitude of the values. The negative signs are important in the
mathematical formalism of coupled transmission lines, but intuitively not of much use.
LineSim/BoardSim preserves the negative signs in its field-solver output reports because if the
capacitance matrix is transferred to another tool (e.g., SPICE), the negative values must be used.

Similarly, the inductance matrix for the two side-by-side microstrip traces is:

Per-Unit versus Absolute Values of C and L

In the equations given in “Uncoupled Transmission Lines” on page 1358, C and L were total
values, for the entire length of the transmission line. It is more traditional (especially with field
solvers) to make C and L per-unit-length values, e.g., to give C in units like pF/m and L in
nH/m. When specified this way, you must multiply C and L by the length of a particular line (or
set of coupled lines) in order to get total C and L.

Given in per-unit-length terms, the matrices shown in the preceding topic become:

The values in these matrices result from dividing the values in the total L and C matrices by the
length of the traces, 8 inches, and then converting inches to meters.

Characteristic Impedance
A pair of coupled traces also has a characteristic impedance, but as is the case with L and C, Z0
is also a matrix quantity. For example, for the pair of traces described above, the characteristic-
impedance matrix is:

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For an uncoupled transmission line, the impedance Z0 gives the ratio of voltage to current
flowing in either of the two directions on the line (i.e., either forward or backward). For
example, if you consider one end of the transmission line, if it is carrying a voltage Vf toward
you, then you can find the current If which is traveling toward you from the expression:

It is not true that the ratio of total voltage to total current on a transmission line at any point is
equal to Z0. Rather, this equation holds separately at every point for both the forward and
backward waves traveling on the line. But the total voltage is the sum of these waves, and the
ratio Vtotal/Itotal is not equal to Z0.

However, when you initially drive into a line, before any reflections have had a chance to return
to the driver, Vtotal/Itotal does equal Z0, since Vtotal and Itotal consist of only one wave. Then
when a reflected wave comes back, this relationship ceases to be true.

For a coupled transmission line, the same equation holds, but the quantities are now all
matrices:

The matrix nature of the characteristic impedance causes the lines to exhibit crosstalk. For
example, suppose you drive a 100-mA pulse into the near end of one of the coupled microstrip
traces we’ve been discussing, but no current into the near end of line 2. You might expect a
voltage to appear on line 1, since you forced current to flow in it, but no voltage on line 2 since
you didn’t drive it. But according to the equation above, since the lines are coupled, this is not
the case:

Even though you forced current only into line 1, a 1.6-V signal appeared on line 2. This
occurred because the lines are coupled; the matrix impedance causes signals to appear on both
lines. Note that it is the off-diagonal terms in Z0 that embody the coupling.

Symmetry of Matrix Parameters

All of the matrices that define coupled-transmission-line parameters (e.g., C, L, Z0) are
symmetric, i.e., element aij = element aji. (Another way to say this is that the matrix "reflects"
across the diagonal.) This occurs because each off-diagonal element describes the coupling
between a pair of traces, and this coupling has to be symmetric.

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For example, in a capacitance matrix, element C12 represents the capacitance between trace 1
and trace 2 in some coupled region. Suppose C12 = 50pF/m. Then C21 must also be 50pF/m,
because it makes no sense that "looking" in one direction between a pair of traces you would
find one capacitance value and looking in the opposite you would find another.

One the other hand, the diagonal elements in the parameter matrices can all have different
values. This occurs because these values represent the "self" or "to-ground" values of each trace.
In the example we’ve been using in this section, the two diagonal values happened to be equal,
because the two traces were physically symmetric. For example, when both traces were on the
same layer and had the same width, we found

But suppose we halve the width of trace 2. Then we find

Note that the diagonal values now differ from each other. Each trace has a different impedance
"to ground"; since trace 2 is narrower, it has less self-capacitance and more self-inductance than
trace 1, and therefore has a higher diagonal impedance (90.8 ohms versus 72.5 ohms). But the
off-diagonal coupling impedance is the same in both position Z12 and Z21, as it must be.

Propagation Modes-Single-Dielectric versus Layered-

Dielectric Traces
The behavior of coupled transmission lines changes depending on whether the lines are in a
stripline configuration, where the lines’ electric and magnetic fields "see" only a single
dielectric value, or in a microstrip or buried-microstrip configuration where the fields penetrate
dielectrics with two or more permittivities. See Figure 31-30.

Figure 31-30. Single-Dielectric Versus Layered-Dielectric Cross Sections

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When coupled transmission lines are in a single-dielectric configuration, they behave much like
single, uncoupled lines: each line has the same propagation velocity, which is related in a simple
way to the speed of light:

where v is the propagation velocity on each transmission line, c is the speed of light, and er is
the permittivity (i.e., dielectric constant) of the PCB’s dielectric material. For example, coupled
traces on a stripline layer of a PCB built from FR-4 with dielectric constant of 4.3 each
propagate signals at v = 0.48c (i.e., at 48% of the speed of light).

However, the situation changes in an interesting way if the same traces are moved to a
microstrip or buried-microstrip layer so that the trace’s fields exist in two dielectrics, FR-4 and
air. Now, the traces will support multiple propagation modes, each with a different propagation
velocity. The next topics describe this effect in detail.

Multi-Speed Propagation
Consider the pair of coupled microstrip traces shown in Figure 31-31. Since each trace, when it
carries a signal, will generate electric and magnetic fields that exist in both FR-4 and air, it’s
fairly obvious that the propagation velocity can’t be given by the simple expression of the
previous topic — after all, there are two different dielectric constants involved now, not one as
with a stripline.

Figure 31-31. Two Coupled Microstrip Traces

One reasonable guess as to the actual behavior of the pair might be that each trace propagates a
signal at one speed that is based on some sort of average dielectric constant (something between
4.3 and 1.0). Another is that there is a continuum of speeds ranging from the one predicted by
the permittivity of FR-4 to the speed in air. But neither is correct.

Instead, two speeds exist, each associated with a distinct "propagation mode" for the pair of
traces. Each trace carries some amount of energy in each mode, i.e., if you drive a signal down
trace 1, it will propagate some portion of the signal energy in mode 1 at speed 1, and the
remaining energy in mode 2 at speed 2. Trace 2 also propagates signals in both modes.

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This behavior is true not only of coupled pairs, but of sets of coupled traces of any size. In
general, if there are N coupled traces in a multi-dielectric configuration, the traces will support
N distinct propagation modes, each trace carrying a mixture of all modes.

Example 1 - A Pair of Coupled Microstrip Traces

As an example, consider the pair of microstrip traces shown in Figure 31-31. The traces are 8
mils wide, 8 mils apart, and 10 mils above a ground plane on a layer of dielectric with
permittivity 4.3.

When a signal is sent down either of these traces, it propagates partly in one mode, and partly in
another. The two modes have the following characteristics:

Table 31-25. Propagation Modes of Two Coupled Microstrip Traces

Trace Propagation Speed (as a Percentage of Energy
Mode percentage of light Traveling in This Mode
speed)
1 or 2 1 63.7% 50%
1 or 2 2 56.6% 50%

Note that both traces carry half of a propagating signal’s energy in mode 1 and mode 2; this
occurs because of the geometric symmetry of the cross section in Figure 31-31. If the traces
were in a stripline configuration with the same dielectric material, signals would travel at 48%
of the speed of light; here, with the mixture of FR-4 and air, both modal speeds are higher (64%
and 57% of c).

Example 2 - A Pair of Traces in an Asymmetric Configuration

In the preceding example, the symmetric breakdown of signal energy (50% in each mode, for
both traces) was due to the symmetry of Figure 31-31’s cross section. If the geometry is
asymmetric, then the distribution of energy across modes also becomes, in general, asymmetric.

Consider the geometry of Figure 31-32. It is the same as for Figure 31-31, except that a second
"buried microstrip" trace layer has been added to the stackup, and trace 2 has been placed on the
new layer.

Figure 31-32. Two Traces in an Asymmetric Cross Section

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Now the two propagation modes have the characteristics in Table 31-26.

Table 31-26. Propagation Modes of Two Coupled Microstrip and Buried

Microstrip Traces
Trace Propagation Speed (as a Percentage of Trace’s Energy
Mode percentage of light Traveling in This Mode
speed)
1 1 59.6% 91.3%
1 2 49.7% 8.7%
2 1 59.6% 14.9%
2 2 49.7% 85.1%

Here, the breakdown of signal energy into the propagation modes is significantly different for
one trace versus the other. Trace 1 carries energy mostly in mode 1, which has the higher
propagating speed (60%of c); this is sensible because trace 1 lies partly in air. Trace 2 carries
energy mostly in mode 2, which is the slower mode (50% of c); again, this seems reasonable,
because trace 2 is buried in dielectric and less of its fields are in air.

Signal Dispersion
The fact that coupled traces in a layered dielectric support multiple propagation speeds means
that a signal is at least slightly distorted when it travels down such a trace. In particular, some
portion of the signal will arrive before others, resulting in a "stair-step" effect.

For example, if a TDR (time-domain reflectometer) drives a fast edge into the one of the traces
shown in Figure 31-31, and the signal is probed at both the TDR output and the trace’s
terminated end 12 inches away, the resulting waveforms are as in Figure 31-33.

Note that the input waveform is a nearly perfect ramp, but by the time this signal reaches the
end of the trace, it has broken noticeably into two components, one of which arrives faster than
the other. If you measure the end-of-the-line waveform carefully and compare it to the
propagation data in Table 31-25, you’ll see that the percentage of signal in each mode and the
difference in arrival times matches the table’s data well.

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Figure 31-33. TDR Waveforms Illustrating Stair Step Effect

From a practical standpoint, several things should be pointed out about this dispersive effect:

• We drove only one of the traces in the pair to produce this waveform; doing so
stimulated both propagation modes, and resulted in a "split" signal; however, had we
driven in differential or common mode only, we would have excited only one of the
propagation modes, and the entire signal would have traveled at a single speed and
arrived without dispersion.
See also: “Differential-Common Modes and Propagation Speeds” on page 1367
• Unless you’re running with very fast driver edges, even if you do drive in a "non-pure"
mode (i.e., not purely differential or common mode) you probably won’t observe the
effect; the waveforms above come from a TDR with a 100-psec rise/fall time
• The difference in propagating speeds is rarely wider than shown in the preceding
example; the typical range between fastest and slowest modal speeds is 10%-20%
• Transmission lines have multiple ways of dispersing a signal; the effect described in this
section is only one of them

Differential Signals
Differential signaling is becoming increasingly important in electronics. Differential methods
have been in use for many years, of course, but there has been renewed interest recently as new
high-speed IC technologies have sought to push bit rates into the hundreds-of-MHz range.
Examples of new IC technologies that use differential signaling include LVDS (low-voltage
differential signaling) and various PECL-like CMOS-based families. These kinds of devices are
becoming particularly important in telecommunications, networking, and high-speed computer
applications.

Proponents of differential signaling cite a number of benefits, probably the most-important of

which are immunity to external noise and reduced generation of radiated emissions. However,

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detailed "philosophies" of differential design vary considerably. For example, some designers
prefer to couple their differential traces strongly; other advocate weak coupling.

However, many newer differential-IC technologies require a certain line-to-line terminator to

achieve proper DC biasing of the differential output buffers. Since this same resistor is also the
differential terminator for the trace pair, requiring a certain resistor value for DC bias essentially
forces you to design your traces to have a matching differential impedance. Thus, you may not
have the luxury of choosing how tightly coupled your lines are.

Differential Traces in LineSim and BoardSim

It is important to realize that differential traces in LineSim and BoardSim are not treated in the
field solver or simulation engine as a special case. Rather, the programs handle any set of
coupled traces in the same way, whether there be two nicely balanced differential traces in the
cross section, or two highly asymmetric traces, or five coupled traces.

However, if your cross section contains only two traces, LineSim/BoardSim recognizes that you
may be designing a differential pair, and automatically changes its impedance display and field-
solver output report (LineSim) or coupling-region-viewer impedance display (BoardSim) to
include differential impedance and other parameters of interest for differential design.

Differential and Common Modes

The Concept of Propagation Modes

Conceptually, the term "propagation mode" refers to a manner in which signals are arranged on
a set of traces in order to propagate the signals. A "basis set" of propagation modes is a
collection of modes that could be used in some mixture to create any arbitrary set of real signals
on the traces. In “Multi-Speed Propagation” on page 1362, the propagation modes discussed
were a set that have the added physical significance of each mode propagating energy at a
different, unique speed (a phenomenon that occurs only with layered dielectrics; see “Multi-
Speed Propagation” on page 1362 for details).

In differential signaling, designers typically conceive of a pair of modes called "differential

mode" and "common mode." The differential mode is one in which if one trace carries the
voltage +V, the other trace carries –V (i.e., the two traces always carry opposite voltages). The
common mode is one in which if one trace carries +V, the other also carries +V.

Note that it is conceptually possible to describe any pair of real signals traveling on the two
traces as some mixture of these two modes. For example, a mostly differential signal that had a
small common-mode component to it could be constructed by mixing 80% differential mode
with 20% common mode.

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Differential-Common Modes and Propagation Speeds

For two-trace microstrip and buried-microstrip configurations in which the traces are
symmetrically arranged (i.e., each trace is on the same layer, has the same width and thickness,
etc.), it turns out that the mode set that describes the two propagation speeds and the
differential/common mode set coincide, i.e., they’re the same. Thus, for symmetric trace
arrangements, driving purely differential signals means that only one mode is stimulated, and
only one propagation speed results. The same is true for driving in common mode (both traces
carrying the same rather than the opposite polarity), except that the other speed results.

Figure 31-34 shows two microstrip traces in a symmetric configuration, i.e., the two traces
share the same layer, are the same thickness and width, etc. — generally, they can’t be
distinguished from each other except that one is on the left and the other on the right. This
means that if these traces are driven purely differentially or purely in common mode, only one
propagation speed will result.

The waveform in Figure 31-34 shows what happens if one trace is driven and the other not. This
is not a "pure" mode: differential mode corresponds to driving the traces with signals [+V,-V]
and common mode means driving [+V,+V], but here we’re driving [+V,0]. So we would expect
a mixture of differential and common mode to be excited, and to see part of the signal arriving
with one velocity and a part with the other — exactly as Figure 31-34’s waveform shows.

Figure 31-34. A Symmetric Microstrip Trace Pair, Driven with a Mixture of

Differential and Common Modes

Now suppose we drive instead differentially, which should produce a "pure" mode and
propagate at only one speed. Figure 31-35 shows the resulting waveform.

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Figure 31-35. Same Cross Section as Previous Figure, but Driven Differentially

Indeed, as expected, the entire signal does arrive does arrive with one propagation speed, and
therefore one delay.

Thus, you can clearly see one benefit of driving a pair of coupled traces differentially: if the
traces are microstrips or buried microstrips (i.e., located in layered dielectrics), the dispersion
which would normally result from driving the traces in an arbitrary manner is eliminated.

However, it is important to note that this benefit is achieved only if the traces are symmetric
(i.e., interchangeable geometrically); otherwise, differential mode will not correspond to a
single-speed propagation mode. The safest way to achieve this symmetry is to route two traces
of the same width and thickness together on the same stackup layer.

Again, it should be noted that these considerations apply only to traces in a layered-dielectric
configuration (microstrips or buried microstrips). For striplines, all propagation is always at a
single velocity.

Differential and Common-Mode Impedance

In differential signaling, another commonly encountered concept is that of "differential
impedance" and "common-mode impedance." There are various ways of motivating the
definitions for these impedances, but the most practical from a signal-integrity viewpoint is
based on the discussion of propagation modes in the preceding topics (see “Differential and
Common Modes” on page 1366):

For a pair of symmetric coupled traces,

• The differential impedance is the trace-to-trace resistance that will properly terminate a
pair of signals driven in differential mode

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• The common-mode impedance is the trace-to-ground impedance (for each trace) that
will properly terminate a pair of signals driven in common mode
For asymmetric traces, these impedances are still useful as terminators, but they will not
function as well as for symmetric traces because asymmetric configurations introduce multiple
propagation speeds into both differential and common modes.

See also: “Differential-Common Modes and Propagation Speeds” on page 1367

LineSim and BoardSim automatically display differential impedance in the Edit Coupling
Regions dialog box (LineSim) or coupling-region viewer (BoardSim) when you’re working
with a two-trace coupling region. The values of differential and common-mode impedance are
also given in the field solver’s report file (LineSim).

Figure 31-36 illustrates the use of these impedances for terminating purposes.

Figure 31-36. Differential and Common-Mode Terminators

These definitions explain why differential trace pairs are often terminated with only a single
resistor, line-to-line. If the traces are indeed driven with "pure" differential signals, nothing else
is required for perfect termination. However, if the actual driven signals contain a mixture of
differential and common modes, the common-mode portion will not be terminated by a line-to-
line resistor.

Generally, the only termination which can guarantee proper termination of a pair of traces given
non-ideal signals is a three-resistor network that simultaneously implements both the
differential and common-mode impedances.

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See also: “Terminating Coupled Transmission Lines” on page 1370

Relationship of Impedances to Characteristic-Impedance Matrix

The values of differential and common-mode impedance are derived from the trace pair’s
characteristic impedance matrix. (For details on the Z0 matrix, see “Characteristic Impedance”
on page 1359.)

If the traces are in a symmetric configuration (same width, thickness, distance from a ground
plane, etc.), then the following relations hold:

If the traces are asymmetric, then the expression for differential impedance becomes:

Again, the asymmetric case will not terminate perfectly with this value because differential
mode will excite two propagation speeds.

See also: “Differential-Common Modes and Propagation Speeds” on page 1367

It should be emphasized that whenever you are working with a two-trace coupling region,
LineSim and BoardSim calculate the differential and common-mode impedances automatically
for you, so you should never need to make these calculations manually.

Terminating Coupled Transmission Lines

The preceding topic (see “Differential and Common-Mode Impedance” on page 1368)
discussed termination of differential trace pairs specifically. In that context, the concepts of
differential and common-mode impedance are useful.

However, it is possible to draw more-general conclusions about the termination of coupled

transmission lines. These concepts can be extended, for example, to an arbitrary number of
lines, and have some interesting properties relative to eliminating crosstalk at line ends.

Termination into the Characteristic-Impedance Matrix

If a single, uncoupled transmission line is terminated into its characteristic impedance, i.e., into
a resistance equaling the line’s Z0, then no reflections will be generated from the end of the line.

For a set of coupled transmission lines, nearly the same statement can be made: that terminating
into an array of resistors that synthesizes the impedance Z0 will perfectly terminate the lines.
Note that because, for coupled lines, Z0 is a matrix quantity, the terminator required to

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implement it is an array of resistors. (For details on matrix impedances, see “Characteristic

Impedance” on page 1359.)

Also, the required resistors do not have the values in the Z0 matrix, rather together in a network,
they implement the impedances in Z0. The array consists not only of resistors from each
transmission line to ground, but also from line to line. LineSim and BoardSim calculate the
proper resistances for the termination array; look for the section in the field solver’s detailed
report (LineSim) or coupling-region viewer’s Impedance pane (BoardSim) called "Optimal
Terminator-Resistor Array."

Such an array of resistors has fairly remarkable properties. First (as is the case for an uncoupled
line), the array will eliminate reflections from each of the line ends. More surprisingly, the array
will also cancel any crosstalk that appears at the line ends.

Example - Perfectly Terminating a Three-Trace Cross Section

Figure 31-37 shows an example cross section containing three coupled traces.

Figure 31-37. Cross Section with Three Coupled Traces

For this cross section, the characteristic-impedance matrix is:

To terminate the traces "into" Z0, a resistor array must be constructed such that an observer
"looking" from each trace end would see the appropriate diagonal impedance to ground; and
from trace-to-trace, would see the appropriate off-diagonal values.

In this case, the properly constructed resistor array is:

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This termination, if fully implemented, would have the following:

to ground from the ends of traces 1, 2, and 3 respectively;

line-to-line between the ends of traces 1 and 2, and 2 and 3; and

line-to-line between traces 1 and 3. However, because 3692 ohms is so large compared to the
diagonal line impedances, this resistor could be omitted without effect.

If this termination is implemented, then the set of coupled traces is as perfectly terminated as
possible: line-end reflections are eliminated for any set of signals driven down the traces, and
crosstalk at the end of the lines is canceled.

Admittedly, such a termination is "expensive" from a component-count standpoint. It also may

not be possible owing to the small value—in this case:

of some of the line-to-line resistors, which might cause too much current to flow between
drivers on different traces when the drivers are in opposed states. (The line-to-ground
resistances could also present too heavy a load to individual drivers.) If these problems exist but
it is still desired to use the terminator, AC coupling (through the addition of capacitors) may
help (adds still more components, though).

In spite of possible implementation difficulties, the resistor-array terminator is a potentially

powerful weapon against reflections and crosstalk. In certain critical situations, where tolerance
for over/undershoot, ringing, excessive delays, or crosstalk is very low, array terminations may
prove quite valuable.

See also: “Optimal Terminator-Resistor Array” on page 1246

Terminating a Differential Pair with a Resistor Array

The array termination for a pair of coupled traces is a three-resistor terminator, consisting of one
resistor line-to-line and two (one for each line) line-to-ground. Together, these resistors
implement a combined differential/common-mode terminator. Thus, the array properly
terminates any kind of signal driven down the lines: differential, common-mode, or a mixture of
the two.

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About Transmission Planes

About Transmission Planes

Transmission planes propagate electric and magnetic fields along cavities formed between two
metal areas on different stackup layers. See Figure 31-38 on page 1373. Transmission planes
help to store and propagate energy to IC power-supply pins, and also accidently carry other
types of noise signals.

Figure 31-38. Transmission-Plane Model

In simulation, “transmission plane” is analogous to “transmission line”, in the sense that both
provides ways to model how energy is transmitted on a conductor and received among power-
supply pins (transmission planes) and signal pins (transmission lines). See Table 31-27.

Table 31-27. Comparing Transmission Planes to Transmission Lines

Transmission Planes Transmission Lines
Signal source IC power-supply pins that IC driver pins that switch to
demand current and create signals
generate power flow
Conductor Cavity formed by two metal Trace segments
shapes on different stackup
layers
Signal loads (things that Decoupling capacitors, IC receiver pins, passive
shape signals) stitching vias, voltage- termination, signal trace
regulator modules (VRMs), geometries (including
power-distribution network stackup)
(PDN) geometries
(including stackup)

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About Transmission Planes

How Transmission Planes Propagate Energy to ICs

Transmission planes have inherent distributed capacitance that stores energy very near to IC
power-supply pins. Their inductance is low, especially if the dielectric layer separating the
metal shapes is thin. Their inherent low impedance enables large amounts of energy to
propagate, with little loss.

This section describes transmission-plane physics, starting with a discussion of transmission

lines. While people commonly think of transmission lines in circuit terms, this section discusses
some of the underlying electromagnetics.

• Question: Where does the signal energy reside in Figure 31-39?

Figure 31-39. Transmission-Line Structure

• Answer: In the electromagnetic fields. See Figure 31-40. The signal energy is located
almost entirely outside the conductors, in the air and dielectric materials. From a circuit
point of view, by contrast, we usually think only of conductor currents and voltages.

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Figure 31-40. Transmission-Line Electromagnetic Fields

The same effect is true in transmission planes, where the energy (in this case, power
propagating to IC power-supply pins) is carried in the dielectric layer, in the cavity between
transmission plane layers. See Figure 31-41.

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Figure 31-41. Transmission Plane

• Question: How do transmission planes know when and where to propagate energy
needed by IC power-supply pins?
• Answer: Let us again use transmission lines as an analogy. A transmission line begins to
propagate energy when a driver IC pin switches state and causes a traveling
“disturbance” (that is, electromagnetic wave) at one end of the transmission line. See
Figure 31-42. The traveling wave pulls current from further and further along the
transmission line into the IC pin.

Figure 31-42. Electromagnetic Wave Propagating in a Transmission Line

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A very similar thing happens in a transmission plane (except radially), when an IC power-
supply pin needs to pull in current. See Figure 31-43. The traveling electromagnetic wave pulls
current further and further away in the transmission plane into the IC pin.

Figure 31-43. Electromagnetic Wave Propagating in a Transmission Plane

Figure 31-44 shows three transmission planes formed by metal areas located on four stackup
layers.

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Figure 31-44. Example Containing Three Transmission Planes

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Jitter Distribution Types

Jitter Distribution Types

This section briefly summarizes the jitter types supported by HyperLynx. Table 31-28 maps
jitter types to the features that support them.

Table 31-28. Jitter Types Supported by HyperLynx Features

FastEye Diagrams IBIS-AMI Eye Diagrams
Standard Eye Diagrams
Gaussian Jitter X X
Sinusoidal Deterministic X
Jitter
Uniform Jitter X
Dual-Dirac Jitter X
DjRj Jitter X

This topic contains the following:

• “Gaussian Jitter” on page 1379

• “Sinusoidal Deterministic Jitter” on page 1382
• “Uniform Jitter” on page 1383
• “Dual-Dirac Jitter” on page 1384
• “DjRj Jitter” on page 1385
• “Jitter Applications” on page 1386
• “Units for Gaussian and Uniform Jitter” on page 1386

Gaussian Jitter
Gaussian jitter is added to the stimulus so that each transition is adjusted away from its ideal
transition time by a random amount. A histogram built from increasingly long observations of
Gaussian random jitter, with a sufficiently small size of subintervals and large number of such
subintervals, resembles a bell curve. See Figure 31-45. In the limit, the histogram approaches a
smooth continuous function called a Gaussian probability density function (PDF), with one
parameter:

1  x
2 
p ( x ) = G ( sigma, x ) = ------------------------- exp  – -------------------2-
sigma 2π  2sigma 

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Where:

sigma is called the standard or mean deviation

Figure 31-45. Gaussian Probability Density Function

Figure 31-45 has the following properties:

• The Gaussian distribution is implemented as a symmetric PDF with a a mean of zero.

• The distribution has one maximum, which is located at the mean.
• The parameter sigma shows how widely (on average) the Gaussian random variable may
deviate around its mean value. In most cases, with probability of 99.73%, the random
variable gets into the +/-3 sigma interval.
Specify the width (or magnitude) of the jitter at one sigma. HyperLynx automatically
derives the width of other sigmas. The sigmas are equally spaced from one another.
Specify sigma as an absolute value (for example, in nanoseconds) or as a relative value
(for example, a fraction of the unit interval set for the simulation).
Increasing the value of sigma increases (on average) the deviation of the timing of
waveform transitions away from the ideal switching time.
• The function is non-negative, p(x) > 0.
• Although it starts from x = -infinity and goes up to x = +infinity (the function has no left
or right bounds), the area enclosed by the curve and the X axis is finite and equals 1.
If we compare two functions with different sigma, the one with smaller sigma will be
narrower but higher, to preserve the area equal 1.
While there is no theoretical limit on the Gaussian random jitter value, a practical limit
exists for serialization/deserialization (SERDES) channels. For example, if adjacent

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transitions are each jittered toward each other by more than half the bit interval, we get a
bit sampling error. HyperLynx prevents this from happening.
• Table 31-29 shows the relationship of the Gaussian distribution to the confidence
interval. The first column shows the probability of any particular event falling inside the
range of the sigma in the second column.
To determine the likelihood of an event happening outside the range of sigma in the
second column, subtract the value in the first column from 1. For example, the
probability of an event falling outside 3 sigma is 1 - 0.9973 = 0.0027, or one in 370.

Table 31-29. Gaussian Distribution - Confidence Interval

Probability Range (in sigma)
0.80 1.28155
0.90 1.64485
0.95 1.95996
0.98 2.32635
0.99 2.57583
0.995 2.80703
0.9973 3.000
0.998 3.09023
0.999 3.29052
0.9999 3.8906
0.99999 4.4172

See also: “Units for Gaussian and Uniform Jitter” on page 1386

Fast-Developing Jitter Sources

Starting with V8.0, HyperLynx uses “fast-developing jitter”. Fast-developing jitter means that
jitter values can vary fast from bit to bit, as if they are almost uncorrelated. By contrast, slow-
developing jitter means that jitter values vary slowly or continuously.

If you compared the distribution of fast-developing jitter and slow-developing jitter, while using
the same sigma for both distributions, many more bits are required for slow-developing jitter to
show its full variability. Because of this, the visible effect from the jitter was sometimes too
small in eye-diagrams when the number of simulated bits was not sufficiently large. When
using “fast-developing jitter”, V8.0 shows more jitter effect on the same bit length than previous
releases.

Gaussian Random Jitter Conceptual Example

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Specify jitter as 10% of the nominal bit interval of 3.8 ns.

Specify a stimulus length of more than 370 bits.

This indicates that 68.33% of the time (1 sigma), the jittered transition will occur between the
times of (nominal - (3.8 ns * 10%)) and (nominal + (3.8 ns * 10%)).

Similarly, 95.5% of the time (2 sigma) the jittered transition will occur between the times of
(nominal - (3.8 ns * 20%)) and (nominal + (3.8 ns * 20%)).

Sinusoidal Deterministic Jitter

Sinusoidal deterministic jitter represents a non-Gaussian distribution with a finite peak-to-peak
amplitude. Figure 31-46 on page 1382 shows how the timing offset varies over the sinusoidal
jitter period, which is usually much greater than the bit interval. Zero timing offset is the ideal
switching time for the signal.

Figure 31-46 shows a zero-degree initial phase, where the timing offset increases slowly to
reach the maximum positive timing offset, decreases slowly to reach the maximum negative
timing offset, and so on.

Figure 31-46. Timing Offset Over Sinusoidal Jitter Period - 0 Degrees Initial
Phase

Figure 31-47 shows a ninety-degree initial phase, where the timing offset slowly decreases to
reach the maximum negative timing offset, and then slowly increases to reach the maximum
positive timing offset.

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Figure 31-47. Timing Offset Over Sinusoidal Jitter Period - 90 Degrees Initial
Phase

A histogram consisting of a large number of sinusoidally-distributed jitter values resembles

Figure 31-48.

Figure 31-48. Sinusoidal Jitter - Histogram

Uniform Jitter
Uniform jitter represents a non-Gaussian distribution where each possible value has the same
probability of happening.

A histogram consisting of a large number of uniformly-distributed jitter values with no offset

(mean = 0) from ideal signal transition timing values resembles Figure 31-49. Figure 31-50
shows uniform jitter with a positive offset (mean > 0) from ideal signal transition timing.

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Figure 31-49. Uniform Jitter Histogram - Mean = 0

Figure 31-50. Uniform Jitter Histogram - Mean > 0

Dual-Dirac Jitter
Dual-Dirac jitter characterizes the cumulative effect of periodic (sine) and Gaussian jitter.

A histogram of the sine jitter has only two peaks that are often approximated by two Dirac
functions. The distance between the Dirac peaks is two times the magnitude of the underlying
periodic jitter. If the jitter has no DC or constant phase offset, the peaks of the sine jitter PDF are
located at equal distances from the ideal transition time. If not, they could both be offset to the
right or left.

The Gaussian component is characterized by its sigma.

When both components are present, the total PDF becomes a convolution of partial PDFs and,
since one of them consists of two Dirac functions, the result is the sum of the two Gaussian
PDFs taken with a factor of 0.5. When the magnitude of the sine component is large compared
to the sigma of the Gaussian component, the cumulative PDF resembles two bell curves, with
their maximums located at “mean1” and “mean2”, where abs(mean1-mean2) is two times the
magnitude of the sine jitter. See Figure 31-51.

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With progressively smaller (magnitude of sine jitter) to (sigma of Gaussian jitter) ratios, the two
bell curve peaks move closer together and the depression between them begins to lift until
finally they form a single bell curve with twice the original magnitude. This happens if the
magnitude of the sine component becomes negligible, and a single Gaussian distribution is
formed.

Figure 31-51. Dual-Dirac Jitter Histogram

DjRj Jitter
DjRj jitter represents a combination of Gaussian and uniform distributions.

A histogram consisting of a large number of DjRj-distributed jitter values resembles a uniform

distribution with Gaussian distributions at its sides. See Figure 31-52. The Gaussian distribution
portions represent the random and unbounded jitter contribution. The uniform distribution
portion represents the determinstic and bounded jitter contribution.

Figure 31-52. DjRj Jitter Histogram

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Jitter Applications
Table 31-30 shows some common uses for the various jitter distributions.

Table 31-30. Jitter Applications

Jitter Type Can Represent
Gaussian • Random noise present in the system, such as thermal and transistor device
noise, which is associated with conductor electron flow and increases with
frequency and temperature. Common random noise sources include thermal
noise, shot noise, and flick noise.
• Power/substrate connection because of finite power-supply rejection ratio
Sine • Deterministic noise sources
• Power-supply voltage variations (that is, ripple)
• Crosstalk. This includes electromagnetic effects that you cannot precisely
predict and effects whose variations are much slower than the frequency of
the data channel.
Restriction: FastEye and IBIS-AMI channel analysis do not include crosstalk.
Standard eye diagrams do include crosstalk.
Uniform Receiver clock-and-data recovery (CDR) jitter. There are indications that steady
state phase distribution in receiver CDR circuitry alone has a flat “top”, that
cannot be modeled with only Gaussian or sine jitter distributions. You may need
to combine uniform and Gaussian jitter distributions to fully represent this
behavior.

Note: You can also use uniform jitter to produce a worst-case distribution more
quickly than Gaussian jitter, which can be helpful during “what if” experiments.
DjRj Receiver clock-and-data recovery (CDR) jitter. There are indications that steady
state phase distribution in receiver CDR circuitry alone has a flat “top”, that
cannot be modeled with only Gaussian or sine jitter distributions.
Dual-Dirac Characterize the cumulative effect of periodic (sine) and Gaussian jitter.

Units for Gaussian and Uniform Jitter

% and ns units represent the same thing. Some IC manufacturers specify maximum jitter in
simple time units while others specify the maximum jitter relative to the bit interval or unit
interval (UI) for which the part is designed to function. Signaling technology specifications
might also specify the maximum allowable jitter for a driver in the circuit.
To convert between the two formats, use the equation:
UI * percent / 100 = time
Where:
UI is the unit interval or bit interval
percent is the specified maximum jitter in percentage of the UI

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time is the maximum time in seconds for the specified jitter

For a Gaussian distribution, the % or ns time is the one sigma value of the jitter distribution. For
an illustration of three sigma, see Figure 31-45 on page 1380.
For a uniform distribution, the % or ns time is the magnitude of the jitter distribution. For an
illustration of magnitude, see Figure 31-49 on page 1384.

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Miscellaneous Reference Information

This topic contains the following:

• “About Lossy Transmission-Line Modeling” on page 1388

• “About the Surface Roughness of Copper Foil” on page 1389
• “Measuring Delay and Overshoot on Waveforms” on page 1390
• “About Design Folder Locations” on page 1391
• “Precedence Among Pad Sizes and Anti-Pad Clearances” on page 1391
• “Precedence Among Anti-Segment Clearances” on page 1394
• “Overlapping Anti-Pads That Isolate Metal Shapes” on page 1395
• “Metal-Area and Padstack Usage for PI Analysis” on page 1398
• “Run HyperLynx with a Lower Priority” on page 1409
• “Wizard Table of Contents Pane” on page 1410
• “HyperLynx Initialization File - BSW.INI” on page 1411

About Lossy Transmission-Line Modeling

Use lossy transmission line modeling ("lossy") to improve simulation accuracy for nets driven
by ICs with very fast edge rates and for nets implemented by traces that are very long or very
narrow. To simulate with lossy, you simply set lossy parameters for dielectric, signal, and plane
layers, and then enable lossy.

Requirement: The Lossy license is required to run lossy simulation.

For signals with fast edge rates, loss is important because the following effects become stronger
as frequency increases:

• Skin effect—Increased trace resistance caused by current flowing along the perimeter of
the trace at high frequencies
• Dielectric loss—Due to heating in the dielectric material
A faster edge rate has higher frequency content, so losses go up and signals degrade more.

For signals implemented by very long or narrow traces, loss is important due to increased
resistance: A long trace has more resistance than a short one and a narrow trace crowds the
current into a smaller cross section (which means more resistance) than a wide one.

The HyperLynx native, ADMS, and HSPICE simulators support the W-element transmission
line algorithm, which accounts for both skin effect and dielectric loss. Since losses change with

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frequency, this algorithm is frequency-dependent. The W-element algorithm uses the following
lossy parameters:

• Loss tangent information for each dielectric layer

• Metal resistivity information for each signal and plane layer
• Metal surface roughness
Restriction: The surface roughness simulation option is enabled independently from
lossy. See “Surface Roughness Dialog Box” on page 1871.

Related Topics
“Preparing Designs for Interactive SI Simulation” on page 533

“Enabling SI Simulation Options” on page 536

About the Surface Roughness of Copper Foil

Roughness can be thought of as the random small-scale “bumpiness” of a metal surface.
Figure 31-53 shows the cross section of electrodeposited copper foil. Figure 31-54 shows the
cross section of rolled copper foil. In both figures, the dark areas are dielectric resin and the
light area is copper foil.

Figure 31-53. Surface Roughness Example - Electrodeposited Copper Foil

Figure 31-54. Surface Roughness Example - Rolled Copper Foil

PCB manufacturers intentionally increase the surface roughness of copper foil to improve its
adhesion to dielectric resin. A strong copper-to-dielectric resin bond is needed to withstand the
many tensile, shear, vibration, chemical, thermal, and other stresses present during PCB
fabrication, assembly, and customer usage. The treatment used to increase surface roughness
may consist of electro-chemically depositing a layer of copper that has a highly granular
crystalline structure. The top and bottom sides may have different roughness values.

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Roughness is commonly measured in terms of amplitude parameters Rq (rms) and Ra

(arithmetic average). HyperLynx uses Rq, which is the root-mean-squared method, calculated
by the following equation:
n
1
--- ∑ y i
2
Rq =
n
i=1

Where:

n is a sequence of equally-spaced measurements on the surface

yi is the vertical distance from the “mean line” to the ith measurement

mean line runs parallel to the surface and is located vertically down from the maximum yi value
to the average value of y1 to yn. This is an approximate definition because some industry
definitions discard outlier yi measurements when calculating the mean line.

Note
The mean line is potentially a local landmark and not global to the stackup layer. Possible
copper foil height variations or “waviness” over relatively large-scale distances can cause
the mean line to follow those variations.

Effect of Surface Roughness on Signal Integrity

Signal loss is related to surface roughness. While increased roughness increases adhesion
strength, it can also increase high-frequency signal loss.

The idea is that as the frequency increases, the current density near the conductor surface
increases because the skin depth decreases. At some high frequency, the skin depth approaches
the surface roughness amplitude, and the signal follows the irregular contours of the conductor
surface, which increases the distance the signal travels.

Related Topics
“Surface Roughness Dialog Box” on page 1871

Measuring Delay and Overshoot on Waveforms

To see how delay and signal integrity overshoot are calculated using hypothetical driver and
receiver single-ended (non-differential) signals, see Figure 31-55.

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Figure 31-55. Signal Integrity Overshoot and Pin Delay on Single-Ended

Waveforms

About Design Folder Locations

When the documentation refers to the “design folder”, it refers to the folder containing the
board/schematic file that is currently open in BoardSim/LineSim/ThermalSim.

You can locate BoardSim boards and LineSim schematic files anywhere on the computer or
network, and in multiple folders if you want.

HyperLynx ships with some example designs and stores them in the following folders:

• C:\MentorGraphics\<release>\SDD_HOME\hyperlynx\HypFiles (32 bit software)

• C:\MentorGraphics\<release>\SDD_HOME\hyperlynx64\HypFiles (64 bit software)
For information about specifying design folders, see “Set Directories Dialog Box” on
page 1854.

Precedence Among Pad Sizes and Anti-Pad Clearances

Several design and user-defined values can specify the pad sizes and anti-pad clearances used
for simulation and the graphical display of vias and surrounding metal regions. BoardSim and
LineSim use the value from the source with the highest precedence (priority) to determine the
pad size and anti-pad clearance for a specific stackup layer.

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You may need to know which design data or user-defined value is used when investigating
unexpected simulation results or visually inspecting the design.

This topic contains the following:

• “Precedence Among Pad Sizes” on page 1392

• “Precedence Among Anti-Pad Clearances - BoardSim” on page 1392
• “Precedence Among Anti-Pad Clearances - LineSim” on page 1393

Precedence Among Pad Sizes

In BoardSim, the PADSTACK keyword in the .HYP file defines the size of via pads.

In LineSim, padstack information in the .FFS file defines the size of via pads. See “Modeling
Vias in Free-Form Schematics”.

The following list sorts pad sizes from highest precedence to lowest:

1. Pad size on a specific layer.

2. Pad size on a default layer.
In BoardSim, in the PADSTACK keyword, the reserved (and optional) MDEF layer
name indicates all metal layers and serves as the source of the default value.
3. The specific layer has no pad, but pads on other layers exist and have the following
properties:
a. The same shape and size.
In this case, use the pad properties from the other layers for the layer with no pad
properties.
b. A different shape or size.
In this case, use the pad size for a round pad with a diameter equal to the minimum
pad size in the padstack.
Item a has higher precedence than item b.
In BoardSim, this happens for a specific layer when the PADSTACK keyword contains
neither the specific layer name or the reserved MDEF layer name.
In the LineSim Padstack Editor, note that <None> in the Pad Shape column represents a
round pad with the same diameter as the drill size.

Precedence Among Anti-Pad Clearances - BoardSim

The following list sorts clearance settings from highest precedence to lowest:

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1. Either of the following:

• .HYP file where all plane areas are defined by POUR keywords.
• You have assigned a power-supply net to a plane layer in the Edit Power-Supply
Nets dialog box. This creates, on the specific plane layer, an implicit plane area that
is the shape of the board outline. See “Editing Power-Supply Nets”.
2. Setup Anti-Pads & Anti-Segments dialog box.
Enable the Force User-Defined Clearances option and type values in the Anti-Pad
Clearance box. See “Setup Anti-Pads and Anti-Segments Dialog Box” on page 1860.
3. .HYP file with the following information:
a. Anti-pad value for a given layer in the PADSTACK keyword.
b. PS value in the PLANE and SIGNAL subrecords of the STACKUP keyword.
c. PLANE_SEP keyword value.
Item a has the highest precedence.
4. Preferences dialog box — Default Padstack tab.
The default anti-pad value comes from the <Auto> Anti-Pads box. See“Preferences
Dialog Box - Default Padstack Tab” on page 1813.

Precedence Among Anti-Pad Clearances - LineSim

The following list sorts clearance value settings from highest precedence to lowest:

1. Setup Anti-Pads & Anti-Segments dialog box.

Enable the Force User-Defined Clearances option and type a value in the Anti-Pad
Clearance box. See “Setup Anti-Pads and Anti-Segments Dialog Box” on page 1860.
This setting does not affect trace-to-trace separation values in coupling regions in the
free-form schematic editor.
2. Padstack Editor.
a. Anti-pad clearances for non-default stackup layers. See “Editing Padstack
Properties“.
b. Anti-pad clearances for the <default> stackup layer. See “Editing Padstack
Properties“.
Item a has higher precedence than item b.
3. Padstack Editor and Preferences dialog box, Default Padstack tab.
In the Padstack Editor, it is possible to define the size of the pad while leaving the size of
the anti-pad undefined. In this case, the anti-pad is formed by adding the size of the anti-

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pad from the <Auto> Anti-Pads box in the Default Padstack tab to the size of the pad
from the Padstack Editor.
If you have defined pad sizes for specific stackup layers, those values have higher
precedence than the pad size for the <default> stackup layer.
See “Editing Padstack Properties“ and “Preferences Dialog Box - Default Padstack Tab”
on page 1813.

Precedence Among Anti-Segment Clearances

If the .HYP file contains anti-pads, but does not contain explicit anti-pad information,
BoardSim automatically generates anti-pad geometries to display in the board viewer. In this
case, several design and user-defined values can specify trace-segment-to-metal-area clearances
used by BoardSim for simulation and graphical display. You may need to know which design
data or user-defined value is used when investigating unexpected simulation results or visually
inspecting the design.

Note
The PDN Editor in LineSim does not use anti-segment values.

Starting with HyperLynx 8.0, translators create .HYP files that explicitly define metal areas (by
using NET keywords with POLYGON records and POUR values) and have all trace-segment-
to-metal area clearances cut directly in the metal areas as voids. In possibly uncommon
circumstances, if the .HYP file contains stackup layers containing both signal traces and metal
areas of the PLANE type (that is either explicitly defined in the .HYP file or implicitly created
for PLANE layers with the associated net), BoardSim automatically generates clearances
between traces and metal areas.

When generating these clearances, BoardSim uses the value from one of the following sources
(ranked from highest to lowest precedence):

1. Setup Anti-Pads and Anti-Segments Dialog Box.

Enable the Force User-Defined Clearances option and type a value in the Anti-Segment
Clearance box.
2. .HYP-file values.
a. PS value in the PLANE and SIGNAL subrecords of the STACKUP keyword
b. PLANE_SEP keyword value.
Item a has higher precedence than item b.
3. Preferences Dialog Box - BoardSim Tab.
Type a value in the Trace to plane box.

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Overlapping Anti-Pads That Isolate Metal Shapes

For some power-distribution network (PDN) topologies, overlapping anti-pads can
unexpectedly isolate metal shapes from each other. You may not see this condition until you
display DC drop or other PI simulation results in the HyperLynx PI PowerScope Dialog Box.

Figure 31-56 on page 1396 shows a power-supply net with overlapping anti-pads that is
displayed in the BoardSim board viewer, the display pane of the DC Drop Analysis dialog box
in BoardSim, and the HyperLynx PI PowerScope Dialog Box.

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Figure 31-56. Overlapping Anti-Pads That Isolate Metal Shapes

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Table 31-31. Overlapping Anti-Pads That Isolate Metal Shapes

Landmark Description
This image comes from the BoardSim board viewer. Notice that pins for the
BGA (the top IC) are surrounded by solid metal because the option to display
anti-pads and anti-segments is disabled.

To speed the display of large boards with many stackup layers, anti-pads and
anti-segments are not displayed by default in the BoardSim board viewer. By
contrast, the HyperLynx PI PowerScope Dialog Box and the display pane in the
DC Drop Analysis box always display them.

If you plan to study PDN metal shapes in the board viewer, you can display
anti-pads and other forms of automatically-calculated clearances by enabling
the Show anti-objects in board viewer (worst performance) option in the Setup
Anti-Pads and Anti-Segments Dialog Box.
This image comes from the BoardSim board viewer. Notice that pins for the
BGA are surrounded by anti-pads because the option to display anti-pads and
anti-segments is enabled.

VRM and DC sink models have been assigned to pins in order to run DC drop
simulation.
This image comes from the layout pane of the DC Drop Analysis dialog box in
BoardSim. Notice that it matches the metal shapes displayed by the BoardSim
board viewer with the option to display anti-pads and anti-segments enabled.
This image comes from the HyperLynx PI PowerScope. Notice that it does not
display the metal shapes below the BGA. This is because:
1. VRM and DC sink models are connected only to the metal shape above the
BGA (see landmark 2). The HyperLynx PI PowerScope only displays metal
shapes that are included in simulation.
2. Overlapping anti-pads, near the bottom of the BGA, isolate the top metal
shape from the bottom metal shape.
3. VRM and DC sink models are not connected to the metal shape below the
BGA. If additional VRM and DC sink models were connected to this metal
shape, the HyperLynx PI PowerScope would display them.

DC drop simulation requires pins with DC sink models to connect through the
PDN topology to pins with VRM models. The overlapping anti-pads for the
BGA isolate the top and bottom metal shapes in landmarks 1, 2, and 3. If you
had assigned a DC sink model to a pin in the top metal shape and assigned a
VRM model to the bottom metal shape, DC drop simulation would not run and
it would display a message similar to: DC Engine failed: No connected VRMs
found in power net.

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Table 31-31. Overlapping Anti-Pads That Isolate Metal Shapes (cont.)

Landmark Description
This image comes from the HyperLynx PI PowerScope and magnifies the
enclosed area for landmark 3.

If you look carefully at the area near the bottom of the BGA, you will see that
the metal shape connected to pins at the top of the BGA is isolated from the
metal shape connected to pins for the bottom IC.

Related Topics
“Setup Anti-Pads and Anti-Segments Dialog Box” on page 1860
“DC Drop Analysis Display Pane” on page 1000
”Viewing BoardSim Boards”
“HyperLynx PI PowerScope Dialog Box” on page 1707

Metal-Area and Padstack Usage for PI Analysis

Even for signal-integrity (SI) analysis, it is very important to know for signal vias whether or
not they are placed inside (or close to) metal areas on a given layer. This fact affects the
electrical model created by HyperLynx for this signal via during simulation. For power-
integrity (PI) analysis, this information is even more important - usage and modeling of the via
strongly depends on its exact position. Vias of power-supply nets may be used as:

• stitching vias that connect metal areas on different layers

• decoupling vias that connect a metal area to a decoupling device (i.e., a capacitor)
• supply vias that connect a metal area to an IC supply pin or VRM (voltage regulator
module)
Some vias may share two or more of the above functions.

To allow HyperLynx to find via-to-metal-area connectivity properly, it's very important that
.HYP-file translators and exporters to follow some rules, as described below.

Metal Area Rules

Translators must pay attention to the type of exported metal areas in the .HYP file. The default
type is PLANE.

• COPPER areas are to be used to describe metal areas that come to the PCB-layout tool's
CAM output exactly in the form they are specified by user. COPPER areas don't depend
on the presence of other elements of the same and other nets. The sizes of COPPER
areas are usually not large. COPPERs may be used do export things like:

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o decal coppers
o pin pads of complex shape
o metal screens below the components (manually drawn)
o embedded capacitors
• PLANE areas define areas (usually large ones) that the user wants to be poured with
metal, but where the actual shape of the metal depends on other nets' elements inside and
near the PLANE as well as the set of clearance rules used in layout system. Different
layout systems use complex and different sets of clearance rules; that's why HyperLynx
doesn't even attempt to offer its own difficult system of such rules. In the .HYP file, only
a very simple hierarchy of clearances is supported (see below for a description).
Clearances from this simple hierarchy are used inside HyperLynx to perform the
pouring procedure for PLANEs specified in the .HYP file (or assumed to exist on
stackup layers of type PLANE).
It's clearly not expected that this simple clearance hierarchy in HyperLynx can be used
to describe exactly the metal shapes as in a layout system, so exporting PLANE metal
areas to the .HYP file will allow HyperLynx to perform only approximate PI analysis.
• To perform accurate PI analysis, a translator/exporter must write to the .HYP file metal
shapes exactly the same as they will be passed to manufacturing system. This means
using the POUR type for metal areas. No processing or modification of POUR metals is
done inside HyperLynx. All clearances (specified in the HYP file or manually in
BoardSim's GUI) are ignored for POUR areas.
It's recommended that translators/exporters optionally support both ways to export metal areas
to the .HYP file:

PLANEs - to allow fast, preliminary, but approximate PI investigations

POURs - to perform detailed, accurate analysis
Using POURs may lead to significant performance loss, but it's always required for detailed,
high-accuracy PI analysis, so if a translator/exporter can create only one type of output, it
must be based on POURs.

The following rules apply to exporting metal areas to the .HYP file:

1. It's recommended to not mix PLANE and POUR areas for the same metal layer in the
HYP file; use one or the other, preferably based on a user option
2. POUR and COPPER areas of different nets cannot intersect
3. POUR and COPPER areas cannot intersect with net elements of other nets
4. POUR areas cannot intersect even for the same net
5. PLANE areas of different nets cannot intersect

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Clearance Hierarchy
As described above, HyperLynx clearance rules are applied to metal areas of the PLANE type.

For vias, the source of clearances used to generate anti-pad voids in PLANES are (from highest
to lowest priority):

1. anti-pad padstack entry on given layer

2. default anti-pad entry specified in a padstack with the MDEF keyword
3. plane separation on a given stackup layer, if specified in the STACKUP
4. plane separation specified for the whole board
5. user-specified (interactively in the BoardSim GUI) clearance value
In three last cases, the clearance is applied to the pad on a given layer or the default pad on an
MDEF layer.

For segments, only three sources of clearances exist; they are applied with this precedence
(highest to lowest):

1. plane separation on a given stackup layer, if specified in the STACKUP

2. plane separation specified for the whole board
3. user-specified (interactively in the BoardSim GUI) clearance value
Note that as implied above, there is a special "what-if" mode controlled interactively in
HyperLynx that allows ignoring all plane separations and anti-pad data in the .HYP file, and
obeying a user-specified clearance in all cases.

See also: “Precedence Among Pad Sizes and Anti-Pad Clearances” on page 1391

Thermal Relief - Connected Vias

Note that thermal reliefs make sense only for metal areas of type POUR.

Actually, for translators/exporters to HyperLynx v8.0, there is no need to bother exporting exact
thermal-relief shapes; this data is not currently used, even for PI analysis. But if thermal reliefs
are exported anyway, it's recommended that thermal spokes are exported as POLYLINE records
(though it's possible to use just a complex POUR area that includes spokes as regular
POLYGONs).

If thermal reliefs are exported, only one rule must be met:

• The via/pin pad in the layer must touch the shape of POUR area.
The safest and most effective way to comply with this rule is to ensure that center of the
via falls inside the POUR area.

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Padstack Rules - Shape and Size of Pad

A padstack in HyperLynx defines for each via/pad both layer span and the set of pads on each
layer.

The layer span of a via is from top layer to bottom (a through via) if the corresponding padstack
in the .HYP file has an MDEF entry of metal (M) type. Otherwise, the layer span is defined as
the topmost to the bottommost of the layers among those that are present in padstack as metal
(M) type subrecords. This means that an MDEF entry cannot be used if you mean to specify a
partial (buried or blind) via. The only way to specify partial via is to list in the padstack all
layers that the via passes through, even it has the same pad shapes and sizes on all layers in the
span. If a metal entry isn't specified on some layer in the span, HyperLynx will create one; and
in such cases, there is no guarantee about the correctness of the shape and size of this created
pad.

Example of a correctly specified partial via:

{PADSTACK=PADSTACK24,0.019000
(4, 0, 0.026000, 0.026000, 0.000000)
(4, 0, 0.066000, 0.066000, 0.000000, A)
(5, 0, 0.026000, 0.026000, 0.000000)
(6, 0, 0.026000, 0.026000, 0.000000)
}
This padstack defines a via that spans from layer "4" to layer "6". On layer "4", the via is
detected to come close to a POUR area (within anti-pad size of 660 mils).

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Figure 31-57. Partial Via - Top View

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Figure 31-58. Partial Via - Side View

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Many layout systems have the option to delete unused pads. But HyperLynx doesn't have a
mechanism to delete pads. If a via does not have a pad on some layer, this lack of pad must be
specified explicitly. The only way to remove a pad on layer is to specify on the layer a
round pad with diameter equal to the drill size.

Example of a via with removed pad:

{PADSTACK=PADSTACK24,0.019000
(4, 0, 0.026000, 0.026000, 0.000000)
(4, 0, 0.066000, 0.066000, 0.000000, A)
(5, 0, 0.0.019000, 0.0.019000, 0.000000)
(6, 0, 0.026000, 0.026000, 0.000000)
}

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Figure 31-59. Partial Via - Side View and Removed Pad

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Creating electrical models of the via requires knowledge of the clearance between the via's pads
and surrounding metal areas (if any are present in the vicinity of the via). The value of this
clearance is defined as the difference between anti-pad and pad sizes in the padstack of a given
via. Everything is clear to BoardSim if anti-pads are explicitly specified on the layer - but if not,
then hierarchical or interactively specified clearances are used instead.

Thus, it's required that anti-pads entries are explicitly specified in the padstack for all layers
where a via referring to this padstack passes through (or near) the metal area of nets other than
the net to which the via belongs.

Padstack Rules - Via-to-Area Connectivity

In HyperLynx v8.0, padstacks are also used to determine whether or not each via is connected to
a metal area on a given layer. To force HyperLynx to properly check this connectivity, some
rules must be applied:

A via is assumed to be connected to a metal area (of any type) of the same net (as the
via) on the layer if its pad on this layer touches the area shape. This means that
translators must be careful about exporting correct pad size; the pad must be large
enough to make the via connect to the area.
For example:

1. If thermal shape is explicitly exported (for POUR area), then it's recommended to make
sure that the center of the via is inside this thermal shape.
2. There is no need to export thermal shapes for vias with a center that falls inside POUR
area.
3. If a via is placed close to but outside a POUR outline it, and should be regarded as
connected, then the pad size must large enough to provide connectivity.
Note that a via is always assumed to be disconnected from any metal areas of nets other than the
net to which the via belongs.

To create an adequate electrical model of a via, it often must be understood whether this via
penetrates a metal area of another net (or is placed very close to the area). HyperLynx v8.0 uses
anti-pad entries to perform this check. If an anti-pad - specified in the padstack of the generated
via based on clearance rules - touches a metal area of any type, then BoardSim assumes that the
via penetrates the area and uses a corresponding electrical model. Obviously, this means that
any via placed (centered) inside a metal area of a net other than the via's net is detected as
"passing though". This is quite clear for PLANE areas, where most pins/vias either fall inside
the area or are well separated from the area. But for a POUR area, all vias belonging to nets
other than the area's net pass through the void in the area that is specially generated in
HyperLynx for this via. That's why specifying correct anti-pads is so important if POUR areas
are exported.

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There may be a case where a given via causes cavities in two (or more) areas simultaneously,
and where the sizes of these cavities differ in each metal are. In this case, the anti-pad entry in
the padstack is recommended to be equal to the size of the maximum cavity.

Figure 31-60 on page 1408 shows an example of via in a gap between two areas.

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Figure 31-60. Via Located in Gap Between Two Areas

Note that two vias in the picture are placed in the gap between two areas of different nets, and
have different clearances to these two areas. To allow HyperLynx to properly detect that both of

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these areas are affected by vias, the translator/exporter must specify the anti-pad size as the
maximum of these two clearances:

{PADSTACK=PADSTACK4,0.038000
(1, 0, 0.062000, 0.062000, 0.000000)
(2, 0, 0.062000, 0.062000, 0.000000)
(2, 0, 0.102000, 0.102000, 0.000000, A)
(3, 0, 0.062000, 0.062000, 0.000000)
(4, 0, 0.062000, 0.062000, 0.000000)
(4, 0, 0.102000, 0.102000, 0.000000, A)
(5, 0, 0.062000, 0.062000, 0.000000)
(6, 0, 0.062000, 0.062000, 0.000000)
}

(Note that 0.092-0.062 = 2 * 20 mils.)

Note that similarly, the definition for the picture's upper via with square pad would be:

{PADSTACK=PADSTACK5,0.038000
(MDEF, 1, 0.062000, 0.062000, 0.000000)
(MDEF, 1, 0.102000, 0.102000, 0.000000, A)
}

Run HyperLynx with a Lower Priority

Some simulations and analyses, especially power-integrity, can consume all the CPU cores and
make it hard to do other work, such as reading and sending e-mail. In some extreme cases,
running processing-intensive simulation or analysis can interfere with refreshing the checkout
of Mentor Graphics licenses and drop VPN (virtual private network) connections.

A workaround is to run HyperLynx with a lower priority. Figure 31-61 shows how to use the
Windows Task Manager to select the HyperLynx process (bsw.exe) and set its priority to Below
Normal or Low. If the only CPU-intensive process running on the computer is HyperLynx,
running HyperLynx with a lower priority will likely not increase the overall run time.

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Figure 31-61. Run HyperLynx with a Lower Priority

Wizard Table of Contents Pane

Some wizards contain a “table of contents” pane near the left side of the dialog box. See
Figure 31-62 on page 1411.

Use the table of contents pane to do the following:

• Navigate directly to a wizard page by clicking its name.

You can access a specific page without having to sequentially step through other pages.
• See the relationship of the current page to the complete list of pages.

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Figure 31-62. Wizard Table of Contents Pane

HyperLynx Initialization File - BSW.INI

BoardSim and LineSim save global session information into a Windows-style initialization file
called BSW.INI. This file contains design-independent information, such as settings from the
Preferences dialog box.

Caution
Mentor Graphics recommends against modifying BSW.INI, unless Mentor Graphics staff
advise you to do so. Only the BoardSim and LineSim programs should write these files.

If the BSW.INI is deleted or lost, BoardSim or LineSim creates a new file with all settings
restored to “factory defaults”. You must modify any global settings you previously changed.

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 Appendix 32
Dialog Boxes

This chapter provides reference information for dialog boxes.

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Dialog Boxes
Add/Edit Decoupling Capacitor(s) Dialog Box

Add/Edit Decoupling Capacitor(s) Dialog Box

To access: Select Decoupling Capacitor or double-click an existing capacitor in the PDN
Editor
Use this dialog box to add or edit individual or groups of decoupling capacitors in the PDN
Editor. Use decoupling capacitors to specify decoupling and signal via bypassing between plane
layers.
The contents of the left side of the dialog changes a lot, depending on the value of the Place
option. Figure 32-1 shows the dialog box when Place is Single. Figure 32-2 shows the dialog
box when Place is Array.
Note
Capacitors in the free-form schematic do not interact with transmission planes in the PDN
Editor.

Figure 32-1. Add/Edit Decoupling Capacitor(s) Dialog Box - Place = Single

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 Dialog Boxes
Add/Edit Decoupling Capacitor(s) Dialog Box

Table 32-1. Add/Edit Decoupling Capacitor(s) Dialog Box Contents - Place =

Single
Option Description
Name Usually a reference designator, but Name can be another value.

Example decoupling capacitor reference designator displayed in

the PDN Editor:

Place Single—Place an individual capacitor.

Array—Place a group of capacitors.

Location Area
X Specify the component location by either:
• Typing the coordinate values
Y • Clicking the location in the PDN Editor. Note that clicking the
PDN Editor fills the X/Y boxes in the dialog box, but does not
display a landmark.
Mounting Scheme Area
Right-click to modify the number and location of the vias and to
modify trace routing.

Double-click a via to open the Add/Edit Via Dialog Box and

specify the stackup layer it connects to and which padstack it uses.

To open a more powerful editor, click Edit Mounting Scheme.

Edit Mounting Scheme Opens the Decoupling Mounting Scheme Editor Dialog Box.
Connected To Area
Via 1 Net Select the power-supply net connected to each via. Via 1 is on the
left and via 2 is on the right, unless you edit the mounting scheme.
Via 2 Net
Select <auto> when the IC pin connects to a stackup layer that
contains one power-supply net.

Select a named net when the IC pin connects to a stackup layer

that contains more than one power-supply net.

Use the PDN Net Manager Dialog Box to add new power-supply
nets or edit their voltages.

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Add/Edit Decoupling Capacitor(s) Dialog Box

Table 32-1. Add/Edit Decoupling Capacitor(s) Dialog Box Contents - Place =

Single (cont.)
Option Description
Via 1 Layer Select the stackup layer(s) connected to each via.

Via 2 Layer Select <multiple> to open the Add/Edit Via Dialog Box.
Model Area
Display the capacitor properties or SPICE/Touchstone model file
name.

Assign Model Open the Assign / Edit Capacitor Model Dialog Box to specify
capacitor values or select a SPICE or Touchstone model.

Restriction: When you specify three or more ports, you must

assign a Touchstone, SPICE, or fitted-poles model with the same
number of ports. This is because the Decoupling Mounting
Scheme Editor Dialog Box does not know the internal port-to-port
connectivity of the capacitor.
Remove Model --

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 Dialog Boxes
Add/Edit Decoupling Capacitor(s) Dialog Box

Figure 32-2. Add/Edit Decoupling Capacitor(s) Dialog Box - Place = Array

Table 32-2. Add/Edit Decoupling Capacitor(s) Dialog Box Contents - Place =

Array
Option Description
Group Name for the capacitor array. Each capacitor group remains a
single object in the PDN Editor, so you can edit it later if needed.

Example decoupling capacitor array displayed in the PDN Editor:

Prefix Reference designator prefix.

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Dialog Boxes
Add/Edit Decoupling Capacitor(s) Dialog Box

Table 32-2. Add/Edit Decoupling Capacitor(s) Dialog Box Contents - Place =

Array (cont.)
Option Description
Start # Starting reference designator instance number.
Place Single—Place an individual capacitor.

Array—Place a group of capacitors.

Location Area
Set By Size—Specify the number of columns and rows in the array.

By Pitch—Specify the distance between capacitors in the array.

Area Whole Board—Distribute the capacitors across the entire board.

Rectangular Area—Distribute the capacitors within a specific

region of the board, specified in the Area Area.
Size The number of columns (left box) and rows (right box) in the
array.

Restriction: This option is unavailable if you select By Pitch in

the Set option.
Pitch Area
X Specify the distance between capacitors.

Y Restriction: This option is unavailable if you select By Size in the

Set option.
Area Area
Left Specify the array boundary by either:
• Typing the coordinate values for the area corners
Bottom • Selecting a region in the PDN Editor, by dragging a box with
the mouse
Right Restriction: This option is unavailable if you select Whole Board
in the Set option.
Top
Mounting Scheme

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 Dialog Boxes
Add/Edit Decoupling Capacitor(s) Dialog Box

Table 32-2. Add/Edit Decoupling Capacitor(s) Dialog Box Contents - Place =

Array (cont.)
Option Description
Right-click to modify the number and location of the vias and to
modify trace routing. All capacitors in the array use the same
mounting scheme.

Double-click a via to open the Add/Edit Via Dialog Box and

specify the stackup layer it connects to and which padstack it uses.

To open a more powerful editor, click Edit Mounting Scheme.

Edit Mounting Scheme Opens the Decoupling Mounting Scheme Editor Dialog Box.
Connected To Area
Via 1 Net Select the power-supply net connected to each via. Via 1 is on the
left and via 2 is on the right, unless you edit the mounting scheme.
Via 2 Net
Select <auto> when the IC pin connects to a stackup layer that
contains one power-supply net.

Select a named net when the IC pin connects to a stackup layer

that contains more than one power-supply net.

Use the PDN Net Manager Dialog Box to add new power-supply
nets or edit their voltages.
Via 1 Layer Select the stackup layer(s) connected to each via.

Via 2 Layer Select <multiple> to open the Add/Edit Via Dialog Box.
Model Area
Display the capacitor properties or SPICE/Touchstone model file
name.

Assign Model Open the Assign / Edit Capacitor Model Dialog Box to specify
capacitor values or select a SPICE or Touchstone model.

Restriction: When you specify three or more ports, you must

assign a Touchstone or SPICE, model with the same number of
ports. This is because the Decoupling Mounting Scheme Editor
Dialog Box does not know the internal port-to-port connectivity of
the capacitor.
Remove Model --

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Add/Edit Decoupling Capacitor(s) Dialog Box

Related Topics
“Adding Symbols to Power-Distribution Networks”

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 Dialog Boxes
Add/Edit IC Power Pin(s) Dialog Box

Add/Edit IC Power Pin(s) Dialog Box

To access: Select Add IC Power Pin(s) or double-click an existing IC power-supply pin in
the PDN Editor
Use this dialog box to add individual and groups of IC power-supply pins to the PDN.
The contents of the left side of the dialog changes a lot, depending on the value of the Place
option. Figure 32-3 shows the dialog box when Place is Single. Figure 32-4 shows the dialog
box when Place is Array.

Figure 32-3. Add/Edit IC Power Pin(s) Dialog Box - Place = Single

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Dialog Boxes
Add/Edit IC Power Pin(s) Dialog Box

Table 32-3. Add/Edit IC Power Pin(s) Dialog Box Contents - Place = Single
Option Description
Reference designator --

Pin name Example IC pin reference designator displayed in the PDN Editor:

Place Single—Place an individual IC pin.

Array—Place a group of IC pins.

Distance to Ref Pin Distance from the IC pin to the reference pin. See “Default
separation between IC power and reference pins” on page 1831.

The value you define here overrides the default value set by the
Default separation between IC power and reference pins option.
You can assign unique values to each IC pin and array of IC pins.
Location Area
X Specify the pin location by either:
Y • Typing the coordinate values
• Clicking the location in the PDN Editor. Note that clicking the
PDN Editor fills the X/Y boxes in the dialog box, but does not
display a landmark.
Connected/Reference Layers Area
Layer column Stackup layer name
Conn column Plane layer that carries current for the IC pin.
Ref column Plane layer that carries return current for the IC pin.
Net Power-supply net that carries current for the IC pin.

Select <auto> when the IC pin connects to a stackup layer that

contains one power-supply net.

Select a named net when the IC pin connects to a stackup layer

that contains more than one power-supply net.

Use the PDN Net Manager Dialog Box to add new power-supply
nets or edit their voltages.

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Add/Edit IC Power Pin(s) Dialog Box

Table 32-3. Add/Edit IC Power Pin(s) Dialog Box Contents - Place = Single
Option Description
Ref Net Power-supply net that carries return current for the IC pin.

Select <auto> when the IC pin connects to a stackup layer that

contains one power-supply net.

Select a named net when the IC pin connects to a stackup layer

that contains more than one power-supply net.

Use the PDN Net Manager Dialog Box to add new power-supply
nets or edit their voltages.
IC is on Side of the board where the VRM pin is located.
Padstack --

Optionally, click Edit to view or modify the selected padstack.

Electrical Models Area
AC Model Specify the electrical characteristics and stimulus waveform of the
current source model assigned to the IC power-supply pin. AC
Edit models typically represent I/O buffer switching and IC core-logic
power on/off transitions.

Click Edit to assign or edit an AC model, using the Edit AC

Power Pin Model Dialog Box.

Selecting AC Model enables the model. Deselecting this option

disables the model, but retains the assignment.
DC Model Specify the electrical characteristics of the current sink model
assigned to the IC power-supply pin. DC models represent static
Edit loads, such as IC power-supply pins connected only to non-
switching circuitry.

Click Edit to assign or edit a DC model, using the Edit DC Power

Pin Model Dialog Box.

Selecting DC Model enables the model. Deselecting this option

disables the model, but retains the assignment.

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Dialog Boxes
Add/Edit IC Power Pin(s) Dialog Box

Figure 32-4. Add/Edit IC Power Pin(s) Dialog Box - Place = Array

Table 32-4. Add/Edit IC Power Pin(s) Dialog Box Contents - Place = Array
Option Description
Reference designator Name for the IC pin array. Each IC pin group remains a single
object in the PDN Editor, so you can edit it later if needed.

Example IC pin array displayed in the PDN Editor:

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 Dialog Boxes
Add/Edit IC Power Pin(s) Dialog Box

Table 32-4. Add/Edit IC Power Pin(s) Dialog Box Contents - Place = Array
Option Description
Starting pin index Starting reference designator instance number.
Place Single—Place an individual IC pin.

Array—Place a group of IC pins.

Distance to Ref Pin Distance from the starting IC pin in the array to the reference pin.

See “Default separation between IC power and reference pins” on

page 1831.

The value you define here overrides the default value set by the
Default separation between IC power and reference pins option.
You can assign unique values to each IC pin and array of IC pins.
Location Area
Set By Size—Specify the number of columns and rows in the array.

By Pitch—Specify the distance between IC pins in the array.

Area Whole Board—Distribute the IC pins across the entire board.

Rectangular Area—Distribute the IC pins within a specific region

of the board, specified in the Area Area.
Size The number of columns (left box) and rows (right box) in the
array.

Restriction: This option is unavailable if you select By Pitch in

the Set option.
Pitch Area
X Specify the distance between IC pins.

Y Restriction: This option is unavailable if you select By Size in the

Set option.
Area Area
Left Specify the array boundary by either:
• Typing the coordinate values for the area corners
Bottom • Selecting a region in the PDN Editor, by dragging a box with
the mouse
Right Restriction: This option is unavailable if you select Whole Board
in the Set option.
Top
Connected/Reference Layers Area

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Dialog Boxes
Add/Edit IC Power Pin(s) Dialog Box

Table 32-4. Add/Edit IC Power Pin(s) Dialog Box Contents - Place = Array
Option Description
Layer column Stackup layer name
Conn column Plane layer that carries current for the IC pin.
Ref column Plane layer that carries return current for the IC pin.
Net Power-supply net that carries current for the IC pin.

Select <auto> when the IC pin connects to a stackup layer that

contains one power-supply net.

Select a named net when the IC pin connects to a stackup layer

that contains more than one power-supply net.

Use the PDN Net Manager Dialog Box to add new power-supply
nets or edit their voltages.
Ref Net Power-supply net that carries return current for the IC pin.

Select <auto> when the IC pin connects to a stackup layer that

contains one power-supply net.

Select a named net when the IC pin connects to a stackup layer

that contains more than one power-supply net.

Use the PDN Net Manager Dialog Box to add new power-supply
nets or edit their voltages.
IC is on Side of the board where the VRM pin is located.
Padstack --

Optionally, click Edit to view or modify the selected padstack.

Electrical Models Area
AC Model Specify the electrical characteristics and stimulus waveform of the
current source model assigned to the IC power-supply pin. AC
Edit models typically represent I/O buffer switching and IC core-logic
power on/off transitions.

Click Edit to assign or edit an AC model, using the Edit AC

Power Pin Model Dialog Box.

Selecting AC Model enables the model. Deselecting this option

disables the model, but retains the assignment.

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 Dialog Boxes
Add/Edit IC Power Pin(s) Dialog Box

Table 32-4. Add/Edit IC Power Pin(s) Dialog Box Contents - Place = Array
Option Description
DC Model Specify the electrical characteristics of the current sink model
assigned to the IC power-supply pin. DC models represent static
Edit loads, such as IC power-supply pins connected only to non-
switching circuitry.

Click Edit to assign or edit a DC model, using the Edit DC Power

Pin Model Dialog Box.

Selecting DC Model enables the model. Deselecting this option

disables the model, but retains the assignment.

Related Topics
“Adding Symbols to Power-Distribution Networks”

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Dialog Boxes
Add/Edit Via Dialog Box

Add/Edit Via Dialog Box

To access: Double-click via in Add/Edit Decoupling Capacitor(s) Dialog Box or click Add Via
in the Decoupling Mounting Scheme Editor Dialog Box.
Use this dialog box to specify the mounting scheme for the vias on your decoupling capacitors.

Figure 32-5. Add/Edit Via Dialog Box

Table 32-5. Add/Edit Via Dialog Box Contents

Option Description
Connnected Net Name of the power-supply net the via connects to.

For information how the net is identified, see “Power-Supply

Nets - PDN Editor”.
Net Manager Open the PDN Net Manager Dialog Box to add or rename power-
supply nets.
Connected Layers Select the layers that the via at the corresponding circuit port will
connect.
Padstack Select the padstack.
Edit Padstack Click to open the Padstack Editor.

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 Dialog Boxes
Add/Edit Via Dialog Box

Table 32-5. Add/Edit Via Dialog Box Contents (cont.)

Location Enter coordinates for the via or graphically select a point in the
Decoupling Mounting Scheme Editor Dialog Box.

Related Topics
“Decoupling Mounting Scheme Editor Dialog Box” on page 1505

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Dialog Boxes
Add/Edit VRM or DC to DC Converter Dialog Box

Add/Edit VRM or DC to DC Converter Dialog Box

To access: Select Add VRM or DC-to-DC converter or double-click an existing VRM in
the PDN Editor

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 Dialog Boxes
Add/Edit VRM or DC to DC Converter Dialog Box

Use this dialog box to specify VRM (voltage-regulator module) models in the PDN Editor
layout. VRMs represent power supplies and act like voltage sources. VRMs are also known as
DC to DC converters.

Figure 32-6. Add/Edit VRM or DC to DC Converter Dialog Box

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Dialog Boxes
Add/Edit VRM or DC to DC Converter Dialog Box

Table 32-6. Add/Edit VRM or DC to DC Converter Dialog Box Contents

Option Description
Reference designator --

Pin name Example VRM reference designator displayed in the PDN Editor:

Location Area
X Set values by either:
• Typing the values
Y • Clicking the pin location in the PDN Editor
If the VRM is not located on the same board, find a power-supply
pin located closest to the connection to the off-board VRM and
assign a VRM model to it. Because VRMs work only at very low
frequencies, the location of the VRM has little effect on the
impedance profile.
Electrical Model Area
Model Simple—Model VRM using a buck switching regulator.

Advanced—Model VRM using a linear regulator.

Voltage The “on” voltage of the VRM.
Resistance The “on” resistance of the VRM. It can represent the following:
• The I/V behavior of the VRM.
• The value of the resistor inside the VRM that is between the
VRM sense point and where the VRM connects to the PCB.
If you do not know the VRM resistance, use 0 milliohms.

Restriction: Unavailable for Advanced Model

Inductance The “on” inductance of the VRM. For example, the inductance
may come from the inductance of pins or cables that connect the
VRM to the PCB. If you do not know the VRM inductance, use 0
nanohenries.

This value is used only for AC power-integrity analysis.

Restriction: Unavailable for Advanced Model

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 Dialog Boxes
Add/Edit VRM or DC to DC Converter Dialog Box

Table 32-6. Add/Edit VRM or DC to DC Converter Dialog Box Contents (cont.)

Option Description
R0 The “on” resistance of the VRM. It can represent the following:
• The I/V behavior of the VRM.
• The value of the resistor inside the VRM that is between the
VRM sense point and where the VRM connects to the PCB.
If you do not know the VRM resistance, use 0 milliohms.

Restriction: Unavailable for Simple Model

L out The “on” inductance of the VRM. For example, the inductance
may come from the inductance of pins or cables that connect the
VRM to the PCB. If you do not know the VRM inductance, use 0
nanohenries.

This value is used only for AC power-integrity analysis.

Restriction: Unavailable for Simple Model

R flat The equivalent series resistance (ESR) of the capacitor associated
with the VRM.

Restriction: Unavailable for Simple Model

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Dialog Boxes
Add/Edit VRM or DC to DC Converter Dialog Box

Table 32-6. Add/Edit VRM or DC to DC Converter Dialog Box Contents (cont.)

Option Description
L slew This value does not trace back to an element in the non-linear
VRM model. Instead, choose the L slew value so that current is
ramped up in the linear VRM model in about the same amount of
time that current is ramped up in the PCB.

This value is used only for AC power-integrity analysis.

L slew = V(dt/di)

where:

V is the maximum voltage ripple. Specify ripple as an offset from

the nominal DC voltage. Do not specify ripple as the peak-to-peak
range of the nominal DC voltage.

dt is the total amount of time needed for the VRM to ramp up or

ramp down the maximum transient current

di is the maximum transient current

Example for a VRM with a maximum ripple of 5 % of 1.5 V and

that can ramp down 20 A in 20 microseconds:

L slew = V(dt/di) = (1.5 V * 0.05)(20 us/20 A) = 75 nH

Restriction: Unavailable for Simple Model

Connected/Reference Layers Area
Layer column Stackup layer name
Conn column Plane layer that carries current for the VRM pin.
Ref column Plane layer that carries return current for the VRM pin.
Net Power-supply net that carries current for the VRM pin.

Select <auto> when the VRM pin connects to a stackup layer that
contains one power-supply net.

Select a named net when the VRM pin connects to a stackup layer
that contains more than one power-supply net.

Use the PDN Net Manager Dialog Box to add new power-supply
nets or edit their voltages.

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 Dialog Boxes
Add/Edit VRM or DC to DC Converter Dialog Box

Table 32-6. Add/Edit VRM or DC to DC Converter Dialog Box Contents (cont.)

Option Description
Ref Net Power-supply net that carries return current for the VRM pin.

Select <auto> when the VRM pin connects to a stackup layer that
contains one power-supply net.

Select a named net when the VRM pin connects to a stackup layer
that contains more than one power-supply net.

Use the PDN Net Manager Dialog Box to add new power-supply
nets or edit their voltages.
IC is on Side of the board where the VRM pin is located.
Padstack --
Edit Optionally, click Edit to view or modify the selected padstack.

Related Topics
“Adding Symbols to Power-Distribution Networks”

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Dialog Boxes
Add Signal Via Dialog Box

Add Signal Via Dialog Box

To access: Click Add Signal Via or Add Differential Signal Via .
Use this dialog box to add single-ended and differential vias to the PDN. Signal vias are
assumed to be connected to schematic transmission lines, which in turn will be driven by IBIS
or other IC-buffer models.
Note
Signal vias are not shared between the PDN Editor and free-form schematic editor unless
you add them to the PDN Editor first. If you are setting up for power-integrity simulation
and want the signal via in the free-form schematic to interact with the PDN, add the via
with the PDN Editor.

Figure 32-7. Add Signal Via Dialog Box

Table 32-7. Add Signal Via Dialog Box Contents

Option Description
Name Enter a unique name for the via(s).

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 Dialog Boxes
Add Signal Via Dialog Box

Table 32-7. Add Signal Via Dialog Box Contents (cont.)

Location Enter X and Y coordinates for the via or click in the PDN
Editor to automatically add coordinates.

For a differential via, the X/Y coordinates define the mid

point between the two via barrels.
Padstack Select the padstack for the via.
Edit Click to open the Padstack Editor.
Separation For differential vias, specify the separation between the via
barrel centerlines.

Restriction: This option is unavailable for single vias.

Common anti-pad Enable to use a single anti-pad that encloses both barrels in
a differential via.

Disable to use an individual anti-pad for each barrel in a

differential via.

Restriction: This option is unavailable for single vias.

Related Topics
“Defining the Power-Distribution Network”
“Via Properties Dialog Box” on page 1908

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Dialog Boxes
AMI File Assignment Dialog Box

AMI File Assignment Dialog Box

To access: Simulate SI > Run IBIS-AMI Channel Analysis > Configure AMI Models page >
Assign AMI Files
Use this page to assign .AMI and .DLL (Windows)/.so (Linux) files to the channel driver and
receiver.
If you assign IBIS models containing [Algorithmic Model] keywords to the channel driver and
receiver ICs, this dialog box automatically displays the location of the .AMI and .DLL/.so files.
You can override the assignments made by [Algorithmic Model] keywords. The .FEW file
stores your changes, not the IBIS model.
Caution
.DLL files are executable files. Make sure the IBIS model specifies .DLL/.so files for all
the computer platforms you run simulation on. Store .DLL/.so files in the same folder as
the IBIS model or in another folder displayed in the Model-library file path(s) list in the
Set Directories Dialog Box.

Figure 32-8. AMI File Assignment Dialog Box

Table 32-8. AMI File Assignment Dialog Box Contents

Option Description
AMI Tx files Area

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 Dialog Boxes
AMI File Assignment Dialog Box

Table 32-8. AMI File Assignment Dialog Box Contents (cont.)

Option Description
Tx AMI .ami path Location of the external ASCII file that contains parameters for the
driver.

See Usage Notes.

Tx AMI .dll or .so Location of the external compiled file that contains signal-processing
path functions for the driver.

See Usage Notes.

AMI Rx files Area
Rx AMI .ami path Location of the external ASCII file that contains parameters for the
driver.

See Usage Notes.

Rx AMI .dll or .so Location of the external compiled file that contains signal-processing
path functions for the receiver.

See Usage Notes.

Usage Notes
The .DLL/.so and .AMI paths and Browse buttons are unavailable when an IBIS model
specifies the .DLL/.so or .AMI. To change the .DLL/.so or .AMI path, edit the IBIS model. See
“Opening the Visual IBIS Editor” on page 407.
Related Topics
“IBIS-AMI Channel Analyzer Wizard - Configure AMI Models Page” on page 1732
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

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Dialog Boxes
Archive Design Dialog Box

Archive Design Dialog Box

To access: Export > Design Archive
Use this dialog box to automatically gather and compress the design simulation files for your
board or schematic.
You can perform the following tasks with the Archive Design utility:
• Take a “snapshot” of your board analysis files at a specific moment in your PCB design
cycle, so they can be restored (if necessary) at a later time.
• If you have experienced problems with a board or schematic, you can use Archive
Design to automatically gather all the files together into a single ZIP file to send to
technical support for investigation.
It is usually not sufficient to send only the BoardSim board file or the LineSim
schematic file to technical support. For example you may be using BoardSim and your
session edits are stored in the .BUD file.

Figure 32-9. Archive Design Dialog Box

Table 32-9. Archive Design Dialog Box Contents

Option Description
Files to archive Types of files available to archive.

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 Dialog Boxes
Archive Design Dialog Box

Table 32-9. Archive Design Dialog Box Contents (cont.)

Option Description
Select All Archive all file types.

This setting is recommended when you plan to

send design files to technical support for
investigation.
Unselect All Archive no file types. Usually used prior to
selecting only a few types of files to archive.
Compress to single file The files will be added to a ZIP file. This
setting is recommended when you plan to send
design files to technical support for
investigation.
Copy files The files will be copied to the archive folder.
Both The files will be copied to the archive folder
and added to a ZIP file.
Archive location The folder that contains the archived files.
Type the location or browse to it.

Related Topics
“Gathering and Archiving Design Simulation Files” on page 1186
“Files That Are Not Archived” on page 1186

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Dialog Boxes
Assign / Edit Capacitor Model Dialog Box

Assign / Edit Capacitor Model Dialog Box

To access:
• From BoardSim, select Models > Edit Decoupling-Capacitor Models and double-
click a spreadsheet row
• From LineSim, open the PDN Editor and double-click decoupling capacitor symbol or
click the Assign Model button
• (Decoupling Wizard | Bypass Wizard | Via Model Extractor Wizard | PDN Model
Extractor Wizard) — Check Capacitor Models page, double-click spreadsheet row
Use this dialog box to assign a model or C-L-R values to a capacitor.
You can load and save capacitor models to directories that are listed in the Model-library file
path area of the “Set Directories Dialog Box” on page 1854. If you need to load or save models
from or to another directory, add the path to the Model-library file path area.
Note: In BoardSim, capacitor model or value assignments you make in this dialog box override
assignments you make in a QPL file. See “QPL File Editor”.

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 Dialog Boxes
Assign / Edit Capacitor Model Dialog Box

Figure 32-10. Assign / Edit Capacitor Model Dialog Box - Simple C-L-R

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Dialog Boxes
Assign / Edit Capacitor Model Dialog Box

Figure 32-11. Assign / Edit Capacitor Model Dialog Box - SPICE

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 Dialog Boxes
Assign / Edit Capacitor Model Dialog Box

Figure 32-12. Assign / Edit Capacitor Model Dialog Box - Touchstone

Table 32-10. Assign / Edit Capacitor Model Dialog Box

Option Description
Model type • Click Simple C-L-R to type capacitance, inductance,
and resistance values.
• Click SPICE to specify a SPICE model.
• Click Touchstone to specify a Touchstone model
(.SnP).
Capacitor model includes Select when the capacitor model includes the effects of the
mounting inductance (no via and its connectivity to the capacitor package. This situ-
additional inductance will ation happens when the vendor did not de-embed the
be calculated/added during capacitor model from how the capacitor package was
analysis) mounted in the test fixture.
Library Models Area — Load or save capacitor models from or to libraries.

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Dialog Boxes
Assign / Edit Capacitor Model Dialog Box

Table 32-10. Assign / Edit Capacitor Model Dialog Box (cont.)

Library Do any of the following:
• Select a library file to load.
• Select <custom model> to create a new and blank
library file. See the descriptions for Save and
Save As .
Model Select a capacitor model to load or save changes to.
Save If Library is set to <custom model>, this opens the Save
Model As Dialog Box. Otherwise, it saves the current
capacitor specifications to the selected capacitor model.
Save as Opens the Save Model As Dialog Box. Use this to create
new library files and save new or existing models to exist-
ing library files.
Delete Removes a selected model from the library file. If the
library file does not contain any models, it removes the
library file.
Simple C-L-R
Capacitance Type the capacitance of the capacitor.
ESR Type the equivalent series resistance of the capacitor.

This is a frequency-dependent value. Choose the value

somewhere near the frequency the mounted capacitor will
resonate. For PCBs, the range is typically 1 - 100 MHz.
ESL Area - Use to specify the equivalent series inductance of the capacitor.

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 Dialog Boxes
Assign / Edit Capacitor Model Dialog Box

Table 32-10. Assign / Edit Capacitor Model Dialog Box (cont.)

Auto-calculate Automatically calculate the inductance of the capacitor
body mounted over the board. Select a Capacitor Size:
• <Auto-estimate>—Automatically calculate the
package body dimensions.
• <Custom>—Enter the package body dimensions.
• <predefined_body_size>—Select a standard package
body size.

Width is the width of the rectangular SMD pads. For Auto-

estimate, if the SMD pad width appears to be unrealistic,
the width is one-half the capacitor body length.

Length is the distance between the capacitor body pins

(BoardSim) or capacitor body ports (LineSim). In Line-
Sim, use the Decoupling Mounting Scheme Editor Dialog
Box to view capacitor body port distances.

Height is the distance between conductors inside the

capacitor body and the PCB surface. For Auto-estimate
and <predefined_body_size>, the value is always 39 mils
/ 1 mm.

BoardSim automatically determines whether the capacitor

is located on the top or bottom of the board. In LineSim,
use the Edit Decoupling Circuit dialog box (open from the
Decoupling Mounting Scheme Editor Dialog Box) to
define whether the capacitor is located on the top or bot-
tom of the board.
Specify value Type the equivalent series inductance. This is a frequency-
dependent value. Choose the value somewhere near the
frequency the mounted capacitor will resonate. For PCBs,
the range is typically 1 - 100 MHz.

Note that ESL is usually much smaller than the mounting

inductance.
Resonance Displays the resonant frequency of the unmounted capaci-
tor. At this frequency and higher, the impedance of the
capacitor increases. Figure 32-13 on page 1449 shows the
resonant frequency plotted for a Z-parameter model.

Restriction: This read-only value is displayed only when

you enable Specify value.
SPICE

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Dialog Boxes
Assign / Edit Capacitor Model Dialog Box

Table 32-10. Assign / Edit Capacitor Model Dialog Box (cont.)

SPICE Files Select a SPICE file. To specify folders that contain mod-
els, in order to display them in this list, see “Select Direc-
tories for IC-Model Files Dialog Box” on page 1844.
Sub-circuits Select the sub-circuit representing the capacitor behavior.

Requirement: The number of sub-circuit ports and capac-

itor pins must be the same.
Show only compatible sub- Select to hide models that have more or fewer ports than
circuits the number of capacitor pins.
View Models Open the SPICE file in the HyperLynx File Editor.
Spreadsheet The read-only spreadsheet maps model nodes to pin
names.

Restriction: The spreadsheet is displayed only when the

sub-circuit ports and capacitor pins is the same.
Touchstone
Files Select a Touchstone model. To specify folders that contain
models, in order to display them in this list, see “Select
Directories for IC-Model Files Dialog Box” on page 1844.
Show only compatible mod- Select to hide models that have more or fewer ports than
els the number of capacitor pins.

Click one of the following sub-filters:

• One-port only
• Two-port only
• One- and two-port
View Model Open the model in the Touchstone and Fitted Poles
Viewer.
Two-port model type Describes how the capacitor was connected when mea-
sured. Figure 32-14 on page 1449 and Figure 32-15 on
page 1449 show the measurement setup for series and
shunt models.

The Autodetect option relies on the conductance between

ports 1 and 2 to choose between series and shunt types.
Series capacitors have small conductance, especially at
low frequencies. Shunt capacitors have large inductance.

Restriction: This area is hidden unless a two-port model

is selected in the Files list.

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 Dialog Boxes
Assign / Edit Capacitor Model Dialog Box

Figure 32-13. Capacitor Resonant Frequency Example

Figure 32-14. Measurement Setup for Series Model

Figure 32-15. Measurement Setup for Shunt Model

Related Topics
“Select Directories for IC-Model Files Dialog Box” on page 1844
“Save Model As Dialog Box” on page 1841

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Dialog Boxes
Assign Decoupling-Capacitor Groups Dialog Box

Assign Decoupling-Capacitor Groups Dialog Box

To access:
• From BoardSim, select Models > Edit Decoupling-Capacitor Groups
• Open the Assign Decoupling-Capacitor Models Dialog Box and click Edit Groups.
• From BoardSim, Open the Decoupling Wizard - Check Capacitor Models Page and
click Edit Groups.
Use this dialog box to edit decoupling-capacitor groups. After you assign decoupling capacitors
to the correct groups, you can assign models to entire groups instead of assigning models to
individual capacitors. To assign models to individual capacitors, remove them from groups.
When you open the board for the very first time, BoardSim automatically assigns decoupling
capacitors with the same capacitance and maximum pin-to-pin dimensions to the same group.
From then on, opening the board does not affect decoupling-capacitor groups.
You manually edit groups by moving decoupling-capacitor instances from one spreadsheet to
the other.
You automatically edit groups by clicking Auto-Grouping and selecting an option.
The BoardSim user session data (.BUD) file contains decoupling-capacitor model group
assignments. The .BUD file is located in the <design> folder. See “About Design Folder
Locations” on page 1391.

Figure 32-16. Assign Decoupling-Capacitor Groups Dialog Box

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 Dialog Boxes
Assign Decoupling-Capacitor Groups Dialog Box

Table 32-11. Assign Decoupling-Capacitor Groups Dialog Box Contents

Field Description
Decoupling capacitors The spreadsheet displays capacitors not in a group.

To assign capacitors to a group:

1. Select one or more rows in the left spreadsheet.
2. Select the existing or <new> destination group in the right
spreadsheet.
3. Click >>.
4. If assigning capacitors to a new group, type the group name.

To select a block of rows, drag over rows or click a row and press
Shift+Click over another row. To select or deselect an individual
row, press Ctrl+Click over a row.
Capacitor groups The spreadsheet displays capacitor groups. Click +/- to
expand/collapse group rows.

When you use a QPL file to assign models or values to

decoupling-capacitor part names, groups named
QPL_<part_name> appear in this spreadsheet. See “QPL File
Editor”.

To rename groups, click the group name row in the right

spreadsheet and type the new name.

To move capacitors in an existing group to a different group:

1. Select one or more rows in the right spreadsheet and click <<.
2. Select one or more rows in the left spreadsheet.
3. Select the existing or <new> destination group in the right
spreadsheet.
4. Click >>.
5. If assigning capacitors to a new group, type the group name.
Ref Des --
Part Name --
Value Capacitance values from the .REF file, .QPL file, or .HYP file
(from highest to lowest priority). If the .HYP file specifies the
capacitor in a ? sub-record for the DEVICES keyword, the
capacitance value comes from the VALUE field. These values
are used only to create the initial membership of decoupling-
capacitor groups. Power-integrity simulation never uses these
values.
Max Dimen The board file provides dimensions.

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Dialog Boxes
Assign Decoupling-Capacitor Groups Dialog Box

Table 32-11. Assign Decoupling-Capacitor Groups Dialog Box Contents (cont.)

Field Description
Auto-Grouping Click to open the Auto-Grouping dialog box, which provides the
following automatic capacitor grouping options:
• Selected capacitors only—Create a new capacitor group
with the unassigned capacitors you have selected in the left
spreadsheet. This option is unavailable if all capacitors
already belong to groups or you have not selected capacitors
in the left spreadsheet.
• All available capacitors (preserve existing groups)—Add
all the unassigned capacitors in the left spreadsheet to one or
more new capacitor groups in the right spreadsheet.
BoardSim automatically assigns decoupling capacitors with
the same capacitance and maximum pin-to-pin dimensions to
the same group. This option does not edit the contents of
existing groups.
• Remove existing groups and perform complete
regrouping—Unassign all capacitors by deleting all groups
and then automatically assign all capacitors to new groups.
BoardSim assigns decoupling capacitors with the same
capacitance and maximum pin-to-pin dimensions to the same
group.

Caution: This option deletes all existing capacitor groups,

including groups that you have manually created.

Related Topics
“Assign Decoupling-Capacitor Models Dialog Box” on page 1453
“Setting Up Designs for Power-Integrity Simulation” on page 341

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 Dialog Boxes
Assign Decoupling-Capacitor Models Dialog Box

Assign Decoupling-Capacitor Models Dialog Box

To access:
• BoardSim > Models > Edit Decoupling-Capacitor Models
• (Decoupling Wizard | Bypass Wizard | Via Model Extractor Wizard | PDN Model
Extractor Wizard) > Check Capacitor Models page
Use this dialog box or Check Capacitor Models page in various wizards to assign models to
decoupling capacitors. Power-integrity simulation supports several ways to model decoupling-
capacitors, including C-L-R values, SPICE models, and Touchstone models.
You can temporarily disable model assignments in order to judge decoupling-capacitor
effectiveness by running power-integrity simulations with and without the model assignments.
For BoardSim, the BoardSim user session data (.BUD) file contains decoupling-capacitor
model assignments. For LineSim, the free-form schematic (.FFS) file contains the assignments.
The .BUD and .FFS files are located in the <design> folder. See “About Design Folder
Locations” on page 1391.

Figure 32-17. Assign Decoupling-Capacitor Models Dialog Box

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Dialog Boxes
Assign Decoupling-Capacitor Models Dialog Box

Table 32-12. Assign Decoupling-Capacitor Models Dialog Box Contents

Option Description
Show these nets only To filter the spreadsheet, click Show these nets only and do one
of the following:
• To display decoupling capacitors and groups connected to a
specific pair of power-supply nets, select power-supply nets
from both lists.
• To display decoupling capacitors and groups connected to
one specific power-supply net and any other power-supply
net, select a specific power-supply net from one list, and then
select <All Supply Nets> from the other list.
In LineSim, the bottom portion of the lists display the “built in”
power-supply nets for signal-integrity simulation, such as Vcc,
VpullDn, VpullUp, and VSS. The exporting features do not use
these nets.
Group/Ref Des --
Part Name --
Value Capacitance values from the .REF file, .QPL file (if you assign a
signal-terminating capacitor value as opposed to a decoupling
capacitor value), or .HYP file (from highest to lowest priority), if
they exist. If the .HYP file specifies the capacitor in a ? sub-
record for the DEVICES keyword, the capacitance value comes
from the VALUE field.

Caution: These values are used only to create the initial

membership of decoupling-capacitor groups. Power-integrity
simulation never uses these values.
Model Info C-L-R values or capacitor models used by power-integrity
simulation.
Enabled To temporarily remove model assignments, clear the Enabled
check box for the groups or individual capacitors.

This capability enables you to judge decoupling-capacitor

effectiveness by running power-integrity simulations with and
without the capacitor assignments.

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 Dialog Boxes
Assign Decoupling-Capacitor Models Dialog Box

Table 32-12. Assign Decoupling-Capacitor Models Dialog Box Contents (cont.)

Option Description
Assign Model To assign or edit decoupling-capacitor model assignments with
the Assign / Edit Capacitor Model Dialog Box, do either of the
following:
• Double-click a spreadsheet row.
• Select one or more spreadsheet rows and click Assign Model.
To select a block of rows, drag over rows or click a row and
press Shift+Click over another row. To select or deselect an
individual row, press Ctrl+Click over a row.
If you expand a group and select one row, the model assignment
applies to the group.
Remove Models To permanently remove model assignments, select one or more
spreadsheet rows and click Remove Models.
Edit Groups To manage group membership, click Edit Groups to open the
Assign Decoupling-Capacitor Groups Dialog Box.
Restriction: This option is
unavailable in LineSim.

Usage Notes
To sort the spreadsheet rows, right-click a spreadsheet cell or column and click the sorting
option.

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Dialog Boxes
Assign Power Integrity Models Dialog Box - IC Tab

Assign Power Integrity Models Dialog Box - IC Tab

To access:
• From BoardSim, select Models > Assign Power Integrity Models
• From the Board Viewer, right-click and IC power-supply pin and select Assign Power
Integrity Model
• From the Decoupling Wizard or PDN Model Extractor Wizard, select the IC Power
Pins page and click Add IC Power Pin
• From the Plane Noise Analysis dialog box, click Assign.
• From the DC Drop Analysis dialog box, click Assign. You can cannot assign AC
models when the Assign Power Integrity Models dialog box is opened this way.
Description
Use this dialog box to assign power-integrity models to IC power-supply pins. The types of
models you assign depend on the type of power-integrity simulation you plan to run. See

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 Dialog Boxes
Assign Power Integrity Models Dialog Box - IC Tab

“Required Power-Integrity Model Assignments” on page 348. Power-integrity models are also
required for the types of model-export features that use power-integrity simulation results.

Figure 32-18. Assign Power Integrity Models Dialog Box — IC Tab Contents

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Dialog Boxes
Assign Power Integrity Models Dialog Box - IC Tab

Table 32-13. Assign Power Integrity Models Dialog Box — IC Tab Contents
Option Description
Filters Area Use this area to filter the contents of the spreadsheet:
• Type a string in the Reference Designator field and click
Apply.
• Type a string in the Power-Supply Net field and click
Apply.
• Select an item in the Component Types list.
The filter boxes support wildcard characters. Use the asterisk
* wildcard to match any number of characters. Use the
question mark ? wildcard to match any one character.
You can display/hide power-supply pins for a reference
designator by clicking row headers marked + or -.
Include attached nets Select to add to the spreadsheet the pins from power-supply
nets associated to the selected net by a series component.

Restriction: This check box is unavailable unless you open

the Assign Power Integrity Models dialog box from the DC
Drop Analysis dialog box.
AC Model Area
Assign Opens the Edit AC Power Pin Model Dialog Box.

Use this to specify the electrical characteristics and stimulus

waveform of the current source model assigned to the IC
power-supply pin. AC models typically represent I/O buffer
switching and IC core-logic power on/off transitions.
Remove Removes AC models from selected spreadsheet rows.
DC Sink Model Area
Assign Opens the Edit DC Power Pin Model Dialog Box.

Use the Edit DC Power Pin Model dialog box to specify the
electrical characteristics of the current sink model assigned to
the IC power-supply pin. DC models represent static loads,
such as IC power-supply pins connected only to non-
switching circuitry.
Remove --
VRM Model Area

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 Dialog Boxes
Assign Power Integrity Models Dialog Box - IC Tab

Table 32-13. Assign Power Integrity Models Dialog Box — IC Tab Contents
Option Description
Assign Opens the Assign VRM Model Dialog Box.

Use this to specify the electrical characteristics of the

voltage-regulator model (VRM) assigned to the IC power-
supply pin. A VRM is a form of DC-to-DC converter and is
used as a voltage source in simulation.
Remove --
Reference Net Area
Assign Opens the Set Reference Nets Dialog Box.

Use this to identify the net and stackup layer(s) used to

provide return-current paths for the selected power-supply
pin(s).
Remove --
Selecting Pins
To assign or remove a model or reference net for IC power-supply pin(s), select one or more
spreadsheet rows containing pins, click the Assign/Remove button located in the appropriate
model type area.
To select a block of rows, drag over the row headers. To select non-adjacent rows, press
Ctrl+Click over the row headers.
Related Topics
“Assigning Power-Integrity Models - BoardSim” on page 351
“Assign Power Integrity Models Dialog Box - Supply-Net Resistors Tab” on page 1460
“Assign Power Integrity Models Dialog Box - Supply-Net Inductors Tab” on page 1463
“Assign Power Integrity Models Dialog Box - Other Supply-Net Components Tab” on
page 1466

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Dialog Boxes
Assign Power Integrity Models Dialog Box - Supply-Net Resistors Tab

Assign Power Integrity Models Dialog Box - Supply-Net

Resistors Tab
To access: Open the Assign Power Integrity Models Dialog Box - IC Tab and click the Supply-
Net Resistors tab.
Use this tab to interactively assign values to resistors that connect the power-supply net that you
plan to analyze to another power-supply net or to a voltage-regulator-module (VRM).
For DC drop simulation, these series components “associate” one power-supply net to another
power-supply net in the same way that series components associate signal nets, which means
the associated power-supply nets are included in the power-integrity analysis. See “Series
Components for Power-Supply Nets” on page 351 and “Associated Nets”.
For AC PI simulations, such as decoupling analysis, these series components can help find
VRMs connected to the transmission plane.
Note
Only DC drop simulation supports series components that associate one power-supply net
to another power-supply net.

Before you begin assigning resistor values, verify the accuracy and completeness of the list of
power-supply nets you plan to simulate. The Select Resistor list contains resistors that connect
one power-supply net to another power-supply net.
If the Select Resistor list is empty and you expected to see reference designators, perhaps
BoardSim did not automatically identify a power-supply net because it has an arbitrary name,
few pins or capacitors, and so on. See “How BoardSim Identifies Power-Supply Nets” and
“Editing Power-Supply Nets”. Another possibility for an empty list is incorrect reference-
designator mappings. See “About Reference-Designator Mappings in BoardSim“.
You can also assign resistance values with .REF and .QPL automapping files. See “Selecting
Models and Values for Entire Components” and “Precedence Among Model and Value
Selection Methods”.

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 Dialog Boxes
Assign Power Integrity Models Dialog Box - Supply-Net Resistors Tab

Figure 32-19. Assign Power Integrity Models Dialog Box — Supply-Net

Resistors Tab

Table 32-14. Assign Power Integrity Models Dialog Box — Supply-Net

Resistors Tab Contents
Option Description
Filters Area Use this area to filter the contents of the spreadsheet:
• Type a string in the Reference Designator field and click
Apply.
• Type a string in the Power-Supply Net field and click
Apply.
The filter boxes support wildcard characters. Use the asterisk
* wildcard to match any number of characters. Use the
question mark ? wildcard to match any one character.
You can display/hide power-supply pins for a reference
designator by clicking row headers marked + or -.

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Assign Power Integrity Models Dialog Box - Supply-Net Resistors Tab

Table 32-14. Assign Power Integrity Models Dialog Box — Supply-Net

Resistors Tab Contents (cont.)
Option Description
Include attached nets Select to add to the spreadsheet the pins from power-supply
nets associated to the selected net by a series component.

Restriction: This check box is unavailable unless you open

the Assign Power Integrity Models dialog box from the DC
Drop Analysis dialog box.
Select Resistor Select a resistor from this list, do one of the following, and
click Assign:
• Discrete (two pin) resistor—Type the value in the
Resistance box.
• Resistor package—Select the package and type the value
in the Resistance box.
See “Choosing Resistor and Capacitor Packages”.
If a .REF or .QPL file determines the existing value, an R
or Q appears next to the checkmark symbol .
If no value is assigned by a .REF or .QPL file, the initial
value is based on the component name.
Resistance Resistance for the selected resistor.
Assign Click to assign a resistance to the selected resistor.
Remove Remove assignment for selected resistor.

Related Topics
“Assigning Power-Integrity Models - BoardSim” on page 351
“Assign Power Integrity Models Dialog Box - IC Tab” on page 1456
“Assign Power Integrity Models Dialog Box - Supply-Net Inductors Tab” on page 1463
“Assign Power Integrity Models Dialog Box - Other Supply-Net Components Tab” on
page 1466

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 Dialog Boxes
Assign Power Integrity Models Dialog Box - Supply-Net Inductors Tab

Assign Power Integrity Models Dialog Box - Supply-Net

Inductors Tab
To access: Open the Assign Power Integrity Models Dialog Box - IC Tab and click the Supply-
Net Inductors tab.
Use this tab to interactively assign values to inductors that connect the power-supply net that
you plan to analyze to another power-supply net or to a voltage-regulator-module (VRM).
For DC drop simulation, these series components “associate” one power-supply net to another
power-supply net in the same way that series components associate signal nets, which means
the associated power-supply nets are included in the power-integrity analysis. See “Series
Components for Power-Supply Nets” on page 351 and “Associated Nets”.
For AC PI simulations, such as decoupling analysis, these series components can help find
VRMs connected to the transmission plane.
Note
Only DC drop simulation supports series components that associate one power-supply net
to another power-supply net.

Before you begin assigning inductor values, verify the accuracy and completeness of the list of
power-supply nets you plan to simulate. The Select Inductor list contains inductors that connect
one power-supply net to another power-supply net.
If the Select Inductor list is empty and you expected to see reference designators, perhaps
BoardSim did not automatically identify a power-supply net because it has an arbitrary name,
few pins or capacitors, and so on. See “How BoardSim Identifies Power-Supply Nets” and
“Editing Power-Supply Nets”. Another possibility for an empty list is incorrect reference-
designator mappings. See “About Reference-Designator Mappings in BoardSim“.
You can also assign inductor values with .REF and .QPL automapping files. See “Selecting
Models and Values for Entire Components” and “Precedence Among Model and Value
Selection Methods”

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Dialog Boxes
Assign Power Integrity Models Dialog Box - Supply-Net Inductors Tab

Figure 32-20. Assign Power Integrity Models Dialog Box — Supply-Net

Inductors Tab

Table 32-15. Assign Power Integrity Models Dialog Box — Supply-Net

Inductors Tab Contents
Option Description
Filters Area Use this area to filter the contents of the spreadsheet:
• Type a string in the Reference Designator field and click
Apply.
• Type a string in the Power-Supply Net field and click
Apply.
The filter boxes support wildcard characters. Use the asterisk
* wildcard to match any number of characters. Use the
question mark ? wildcard to match any one character.
You can display/hide power-supply pins for a reference
designator by clicking row headers marked + or -.
Include attached nets Select to add to the spreadsheet the pins from power-supply
nets associated to the selected net by a series component.

Restriction: This check box is unavailable unless you open

the Assign Power Integrity Models dialog box from the DC
Drop Analysis dialog box.

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Assign Power Integrity Models Dialog Box - Supply-Net Inductors Tab

Table 32-15. Assign Power Integrity Models Dialog Box — Supply-Net

Inductors Tab Contents (cont.)
Option Description
Select Inductor Select and inductor and assign resistance and inductance
values.

If a .REF or .QPL file determines the existing value, an R or

Q appears next to the checkmark symbol .

If no value is assigned by a .REF or .QPL file, the initial

value is based on the component name.
Inductance Inductance of selected inductor.
Resistance Resistance of selected inductor. Resistance values are used
for DC power-integrity simulations.
Assign Assigns R and L values to selected inductor.
Remove Removes R and L values for selected inductor.
Related Topics
“Assigning Power-Integrity Models - BoardSim” on page 351
“Assign Power Integrity Models Dialog Box - IC Tab” on page 1456
“Assign Power Integrity Models Dialog Box - Supply-Net Resistors Tab” on page 1460
“Assign Power Integrity Models Dialog Box - Other Supply-Net Components Tab” on
page 1466

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Dialog Boxes
Assign Power Integrity Models Dialog Box - Other Supply-Net Components Tab

Assign Power Integrity Models Dialog Box - Other Supply-

Net Components Tab
To access: Open the Assign Power Integrity Models Dialog Box - IC Tab and click the Other
Supply-Net Components tab.
Description
Use this tab to interactively assign values to non-resistor/inductor components, such as high-
current power FETs, that connect the power-supply net that you plan to analyze to another
power-supply net. These series components “associate” power-supply nets in the same way that
series components associate signal nets, which means the associated power-supply nets are
included in the power-integrity analysis. See “Series Components for Power-Supply Nets” on
page 351 and “Associated Nets”.
Note
Only DC drop simulation supports series components that associate one power-supply net
to another power-supply net.

Before you begin assigning IC resistance values, verify the accuracy and completeness of the
list of power-supply nets you plan to simulate. The Select IC list contains components with
reference designators that map to ICs and connectors and connect to a power-supply net.
If the Select IC list is empty and you expected to see reference designators, perhaps BoardSim
did not automatically identify a power-supply net because it has an arbitrary name, few pins or
capacitors, and so on. See “How BoardSim Identifies Power-Supply Nets” and “Editing Power-
Supply Nets”. Another possibility for an empty list is incorrect reference-designator mappings.
See Edit Reference Designator Mappings Dialog Box.
Resistance values for ICs and connectors are used for DC power-integrity analyses.

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Assign Power Integrity Models Dialog Box - Other Supply-Net Components Tab

Figure 32-21. Assign Power Integrity Models Dialog Box — Other Supply-Net
Components Tab

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Assign Power Integrity Models Dialog Box - Other Supply-Net Components Tab

Table 32-16. Assign Power Integrity Models Dialog Box — Other Supply-Net
Components Tab Contents
Option Description
Filters Area Use this area to filter the contents of the spreadsheet:
• Type a string in the Reference Designator field and click
Apply.
• Type a string in the Power-Supply Net field and click
Apply.
The filter boxes support wildcard characters. Use the asterisk
* wildcard to match any number of characters. Use the
question mark ? wildcard to match any one character.
You can display/hide power-supply pins for a reference
designator by clicking row headers marked + or -.
Include attached nets Select to add to the spreadsheet the pins from power-supply
nets associated to the selected net by a series component.

Restriction: This check box is unavailable unless you open

the Assign Power Integrity Models dialog box from the DC
Drop Analysis dialog box.
Select IC Select and IC to display a list of pins for the IC.
Select First Pin To connect two pins, click the spreadsheet row header for the
first and second pins of the component, and click Connect.

Note: You must select and IC before connecting pins.

If needed, assign voltages to power-supply nets. See “Editing

Power-Supply Nets”.
Select Second Pin To connect two pins, click the spreadsheet row header for the
first and second pins of the component, and click Connect.

Note: You must select and IC before connecting pins.

If needed, assign voltages to power-supply nets. See “Editing

Power-Supply Nets”.
Resistance, Ohm To assign a resistance value to the series component, click a
row in the Connections spreadsheet, type a resistance value in
the Resistance box, and click Assign.
Assign Assigns a resistance to the selected row in the Connections
spreadsheet.
Connect Connects pins selected in the Select First Pin and Select
Second Pin lists.

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Assign Power Integrity Models Dialog Box - Other Supply-Net Components Tab

Table 32-16. Assign Power Integrity Models Dialog Box — Other Supply-Net
Components Tab Contents (cont.)
Option Description
Delete Deletes selected connection.
Connections Lists connected pins.
Related Topics
“Assigning Power-Integrity Models - BoardSim” on page 351
“Assign Power Integrity Models Dialog Box - IC Tab” on page 1456
“Assign Power Integrity Models Dialog Box - Supply-Net Resistors Tab” on page 1460
“Assign Power Integrity Models Dialog Box - Supply-Net Inductors Tab” on page 1463

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Dialog Boxes
Assign VRM Model Dialog Box

Assign VRM Model Dialog Box

To access: Open the Assign Power Integrity Models Dialog Box - IC Tab and from the VRM
Model area click Assign
Use the Assign VRM Model dialog box to specify the electrical characteristics of the voltage-
regulator model (VRM) assigned to the IC power-supply pin. A VRM is a form of DC-to-DC
converter and is used as a voltage source in simulation.
You assign VRM models to power-supply pins by selecting one or more spreadsheet rows in the
Assign Power Integrity Models Dialog Box - IC Tab.
Requirement: You must also assign a reference net when assigning a VRM model and you
plan to run AC power-integrity simulation. See “Assign Reference Nets When Assigning VRM
Models and Running AC Power-Integrity Simulation” on page 1473.

Tip: If the VRM is not located on the same board, find a power-supply pin located closest
to the connection to the off-board VRM and assign a VRM model to it. Because VRMs
work only at very low frequencies, the location of the VRM has little effect on the
impedance profile.

Figure 32-22. Assign VRM Model Dialog Box - Simple

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 Dialog Boxes
Assign VRM Model Dialog Box

Figure 32-23. Assign VRM Model Dialog Box - Advanced

Table 32-17. Assign VRM Model Dialog Box Contents

Field Description
Model Simple—Use to model VRMs using a buck switching
regulator.

Advanced—Use to model VRMs using a linear regulator.

Voltage The “on” voltage of the VRM.
Resistance The “on” resistance of the VRM. It can represent the
following:
(Available only when • The I/V behavior of the VRM.
Simple is selected in the • The value of the resistor inside the VRM that is
Model pull-down menu.) between the VRM sense point and where the VRM
connects to the PCB.
If you do not know the VRM resistance, use 0 milliohms.
Inductance The “on” inductance of the VRM. For example, the
inductance may come from the inductance of pins or
(Available only when cables that connect the VRM to the PCB. If you do not
Simple is selected in the know the VRM inductance, use 0 nanohenries.
Model pull-down menu.)
This value is used only for AC power-integrity analysis.

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Assign VRM Model Dialog Box

Table 32-17. Assign VRM Model Dialog Box Contents (cont.)

Field Description
R0 The “on” resistance of the VRM. It can represent the
following:
(Available only when • The I/V behavior of the VRM.
Advanced is selected in the • The value of the resistor inside the VRM that is
Model pull-down menu.) between the VRM sense point and where the VRM
connects to the PCB.
If you do not know the VRM resistance, use 0 milliohms.
L out The “on” inductance of the VRM. For example, the
inductance may come from the inductance of pins or
(Available only when cables that connect the VRM to the PCB. If you do not
Advanced is selected in the know the VRM inductance, use 0 nanohenries.
Model pull-down menu.)
This value is used only for AC power-integrity analysis.
R flat The equivalent series resistance (ESR) of the capacitor
associated with the VRM.
(Available only when
Advanced is selected in the
Model pull-down menu.)
L slew This value does not trace back to an element in the non-
linear VRM model. Instead, choose the L slew value so
(Available only when that current is ramped up in the linear VRM model in
Advanced is selected in the about the same amount of time that current is ramped up
Model pull-down menu.) in the PCB.

This value is used only for AC power-integrity analysis.

L slew = V(dt/di)

where:

V is the maximum voltage ripple. Specify ripple as an

offset from the nominal DC voltage. Do not specify ripple
as the peak-to-peak range of the nominal DC voltage.

dt is the total amount of time needed for the VRM to ramp

up or ramp down the maximum transient current

di is the maximum transient current

Example for a VRM with a maximum ripple of 5 % of 1.5

V and that can ramp down 20 A in 20 microseconds:

L slew = V(dt/di) = (1.5 V * 0.05)(20 us/20 A) = 75 nH

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Assign VRM Model Dialog Box

Assign Reference Nets When Assigning VRM Models and Running AC Power-
Integrity Simulation
Some VRMs require a large-value resistive load to ground, to maintain some current flow at all
times. To the algorithm that follows connectivity through series resistors, to identify “associated
power-supply nets” that are simulated at the same time, these resistors appear to be additional
series resistors, even though they function as load resistances to ground. This mis-identification
can cause many power-supply nets to be incorrectly simulated at the same time.
To avoid this problem, you assign a reference net when you assign a VRM model. This causes
the algorithm that identifies associated power-supply nets to stop at the reference net. It is
optional to assign reference nets for DC drop simulation because it runs faster than AC power-
integrity simulation and the resistor values are high enough to not significantly affect DC drop
results.
In a somewhat rare situation, the selected reference net itself may connect to series elements. To
avoid associating power-supply nets through series VRM load resistors connected to the
reference net, BoardSim does not associate through resistors that exceed 100 ohms. Such large-
valued series resistors would not likely exist in the DC path in a power-distribution network.
Related Topics
“Assign Power Integrity Models Dialog Box - IC Tab” on page 1456

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Dialog Boxes
Bathtub Chart Dialog Box

Bathtub Chart Dialog Box

To access:
• FastEye Channel Analyzer - View Analysis Results Page > select Bathtub curves and
run analysis
• IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page > select Bathtub
curves and run analysis
Use this dialog box to display and document bathtub curves. Bathtub curves help identify valid
data sampling locations by reporting the bit error rate (BER) as a function of the sampling
location across the unit interval (UI, same as bit interval) at several voltage offsets.
The Y axis represents the BER and the X axis represents the unit interval.
Bathtub curves indicate the quality of sampling locations across the UI by providing the
probability of failure at each sampling location. If a point on the bathtub curve is located at 0.5
on the Y axis, an equal probability of bit transmission success and failure exists at that sampling
location. By contrast, eye diagrams leave it to you to judge the probability of failure at sampling
locations.
BER is directly related to the signal-to-noise ratio. Channel behaviors that can increase BER
include reflections, jitter (random, deterministic), crosstalk, loss, and so on.

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Bathtub Chart Dialog Box

Figure 32-24. Bathtub Chart Dialog Box

Table 32-18. Bathtub Chart Dialog Box Contents

Option Description
Print the graph with a white background.
Print (right-click)
Zoom in by doing the following:
1. Position the mouse pointer over one corner of the zoom box
Zooming (right-click) you want to create, and then drag to define the other corner
of the zoom box.
2. Release the mouse button to magnify the contents of the
zoom box to fill the graph.

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Bathtub Chart Dialog Box

Table 32-18. Bathtub Chart Dialog Box Contents (cont.)

Option Description
Pan by dragging the graph across the dialog box.
Panning (right-click)
Attach measurement crosshairs to a waveform by clicking the
waveform to measure.
Track Cursor (right-click)
As you move the mouse horizontally, the measurement
crosshairs tracks the selected curve.
Fit the entire curve to window.
Fit to window (right-click)
Display only lines between curve vertices (no vertice dots).

Display only curve vertices (no lines).

Display both lines and vertice dots.

Open Help for the dialog box.

Copy (right-click) Copy graph to the clipboard and use a white background.

This option uses less printer ink or toner if you print it out.

You can paste the image from the Windows clipboard into
another program such as Microsoft WordPad.
Copy inverted (right-click) Copy graph to the clipboard and use a black background.

You can paste the image from the Windows clipboard into
another program such as Microsoft WordPad.
Save As Save the numerical bathtub data to a file. You can open the file
with a spreadsheet application, such as Microsoft Excel.

Unit Interval Origin

The origin of the UI axis is based on the time of the maximum voltage for the initial transition
of the waveform. As a result, 0.5 on the UI axis may not be located at the “center” of the bathtub
curve. Asymmetric bathtub curves can also move the center of the bathtub away from 0.5 on the
UI axis.

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Bathtub Chart Dialog Box

When multiple bathtub curves are displayed, note that their UI origins are set by independent
maximum voltages and do not necessarily align to each other or to the start of simulation.

Bathtub Curve Sampling Voltage Offsets

The Bathtub Chart dialog box displays BER curves for several sampling voltage offsets, which
can represent sampling threshold level variations in the system. A legend near the bottom of the
X axis maps the color of the BER curve to the sampling voltage offset.
The nominal sampling voltage (or voltage origin—0 V) is the median value of the high and low
voltage levels, which is the crossover voltage for differential signaling and linear models. The
curve associated with the nominal sampling voltage maps to the left-most legend color square.
Related Topics
“FastEye Channel Analyzer - View Analysis Results Page” on page 1628
“IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page” on page 1756

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Dialog Boxes
Bypass Wizard - Check Capacitor Models Page

Bypass Wizard - Check Capacitor Models Page

To access: Select Simulate PI > Analyze Signal-Via Bypassing and select the Check
Capacitor Models page
Use this page to review and edit decoupling capacitor model assignments.
Double-click a capacitor to assign or edit capacitor models. See “Assign Decoupling-Capacitor
Models Dialog Box” on page 1453.
Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Analyzing Signal-Via Bypassing” on page 1051

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 Dialog Boxes
Bypass Wizard - Choose Easy / Custom Page

Bypass Wizard - Choose Easy / Custom Page

To access: Select Simulate PI > Analyze Signal-Via Bypassing and select the Choose Easy /
Custom page
Use this page to choose between default and custom analysis options.

Figure 32-25. Bypass Wizard - Choose Easy / Custom Page

Table 32-19. Bypass Wizard - Choose Easy / Custom Page Contents

Option Description
Easy Popular analysis settings are automatically enabled on some of
the following wizard pages. Many of the automatically-enabled
settings become read only.
Custom You can edit all analysis settings on the following wizard pages

Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Analyzing Signal-Via Bypassing” on page 1051

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Dialog Boxes
Bypass Wizard - Control Frequency Sweep Page

Bypass Wizard - Control Frequency Sweep Page

To access: Select Simulate PI > Analyze Signal-Via Bypassing and select the Control
Frequency Sweep page
Use this page to edit frequency range and sampling options, both of which affect analysis run
time and the resolution of the exported Z-parameter model.

Figure 32-26. Bypass Wizard - Control Frequency Sweep Page

Table 32-20. Bypass Wizard - Control Frequency Sweep Page Contents

Option Description
Min frequency The minimum simulation frequency, in MHz.
Max frequency The maximum simulation frequency, in MHz.
Adaptive sampling Varies the sampling step size depending on model
characteristics. The adaptive scale is better than
Restriction: This option is logarithmic and linear because it increases the sampling
unavailable if you enable the Easy rate near frequencies with resonances.
option in the Bypass Wizard -
Choose Easy / Custom Page.

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Bypass Wizard - Control Frequency Sweep Page

Table 32-20. Bypass Wizard - Control Frequency Sweep Page Contents (cont.)
Option Description
Logarithmic sampling Sampling points are distributed at logarithmic intervals
across the frequency range. The intervals between
Restriction: This option is sampling points are smaller at lower frequencies and
unavailable if you enable the Easy larger for higher frequencies. With logarithmic
option in the Bypass Wizard - sampling, every next frequency point is equal to the
Choose Easy / Custom Page. previous value times a factor K > 1. This produces a
constant increase ratio, but the absolute distance
between sampling points grows.
Linear sampling Sampling points are distributed at equal intervals across
the frequency range.
Restriction: This option is
unavailable if you enable the Easy
option in the Bypass Wizard -
Choose Easy / Custom Page.
Accuracy at resonances For lumped analysis, enabling the High option may still
yield reasonably fast simulation run times.
Restriction: This option is
unavailable unless you enable the For distributed analysis, you should take the complexity
Adaptive sampling option on this of the design into account. If the design has large
page. numbers of power-supply nets, hundreds of decoupling
capacitors, and hundreds or thousands of stitching vias,
enabling the Low option provides preliminary results
with decreased analysis run time. After evaluating the
preliminary results, you can identify which frequency
ranges interest you the most and try running analysis
with higher accuracy on each range of interest.
Minimum number of samples in The number of samples you specify applies to flat, non-
flat, non-resonant regions resonant, regions of an impedance profile. See the
enclosed curve region Figure 32-41 on page 1513.
Restriction: This option is
unavailable unless you enable the
Adaptive sampling option on this
page.
Number of samples The number of samples you specify applies to the entire
frequency range.
Restriction: This option is
unavailable if you enable the
Adaptive sampling option on this
page.
Default Click Default to restore the initial settings.

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Bypass Wizard - Control Frequency Sweep Page

Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Analyzing Signal-Via Bypassing” on page 1051

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 Dialog Boxes
Bypass Wizard - Customize Settings Page

Bypass Wizard - Customize Settings Page

To access: Select Simulate PI > Analyze Signal-Via Bypassing and select the Customize
Settings page
Use this page to enable detailed analysis options. Simulating the design with different sets of
enabled and disabled options can help you determine how individual types of design properties
contribute to signal-via bypassing performance.
Restriction: If you enable the Easy option on the Bypass Wizard - Choose Easy / Custom Page,
you cannot edit options on this page.

Figure 32-27. Bypass Wizard - Customize Settings Page

Table 32-21. Bypass Wizard - Customize Settings Page Contents

Option Description
Include capacitor mounting To determine the contribution of capacitor mounting inductance
inductance to the overall signal-via bypassing performance, you can run
analysis with this option enabled, run it again with this option
disabled, and then compare the results.
Enable stitching-via Find stitching vias that are located close together and merge their
optimization individual models into an equivalent model. This process is
repeated across the transmission plane. Reducing the number of
stitching-via models speeds up simulation and reduces memory
consumption because each model adds a variable to the systems
of equations to solve. See “Stitching-Via Optimization - Bypass
Wizard” on page 1484.

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Dialog Boxes
Bypass Wizard - Customize Settings Page

Stitching-Via Optimization - Bypass Wizard

Stitching-via optimization takes advantage of the fact that when the size of objects (or groups of
them) is much smaller than the wavelength of a signal, the signal does not respond to them in
detail, and approximate models can accurately represent those objects in simulation.
The Tolerance slider controls the merging radius for optimization:
• Low—1/30th of the minimum wavelength of the signal
• Medium—1/20th of the minimum wavelength of the signal
• High—1/10th of the minimum wavelength of the signal
For example, let us say that signal-via bypassing analysis does not exceed 300 MHz and that the
wavelength of a 300 MHz signal in FR-4 is about 20 inches. In electromagnetic analysis, 1/10th
wavelength is considered to be safely “much smaller” than the wavelength of the signal and that
within a 2 inch radius, we can avoid representing individual stitching vias by modeling them
with one equivalent (or “clumped”) via.
Not all stitching vias are eligible for optimization and most optimization takes place far away
from IC and decoupling-capacitor pins. The optimization algorithm preserves individual models
for caging vias and for stitching vias that contribute significantly to transmission-plane or
decoupling-capacitor inductance. As a result, this setting may have little effect for designs
where most of the stitching vias in the transmission plane contribute significantly to
transmission-plane or decoupling-capacitor inductance.
For example, caging vias that are located very close to the IC or decoupling-capacitor pin are
always modeled individually. In other words, if you run bypass analysis to produce Z
parameters for a signal net topology that uses a via with a stitching section, then any very-
nearby stitching vias are preserved as individual models to observe their full caging effect.
Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Analyzing Signal-Via Bypassing” on page 1051

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Bypass Wizard - Run Analysis Page

Bypass Wizard - Run Analysis Page

To access: Select Simulate PI > Analyze Signal-Via Bypassing and select the Run Analysis
page
Use this page to choose the name of the Z-parameter file created by signal-via bypass analysis,
to save to a file the wizard page settings, and to save to a spreadsheet information for all the
decoupling capacitors connected to the pair of power and ground nets.
Editing a setting on this page updates the same setting on the Bypass Wizard - Start Analysis
Page.

Figure 32-28. Bypass Wizard - Run Analysis Page

Table 32-22. Bypass Wizard - Run Analysis Page Contents

Option Description
Save settings to file Save wizard settings to a .DAO file. The default file location is
the <design> folder. See “About Design Folder Locations” on
page 1391. You can change the file locations.

To specify another settings file location, click Browse to specify

the file name and location.

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Bypass Wizard - Run Analysis Page

Table 32-22. Bypass Wizard - Run Analysis Page Contents (cont.)

Option Description
Auto-generate output file Name the output file using form
name <design>_<simulation_iteration>.z1p.

For example, test_2.z1p.

The default file location is the <design> folder. See “About

Design Folder Locations” on page 1391.

To specify another output file location, deselect Auto-generate

output file name and click Browse to specify the file name and
location.

Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Data Flow for Signal-Via Bypass Analysis” on page 1052
“Analyzing Signal-Via Bypassing” on page 1051

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Bypass Wizard - Select Signal Via Page

Bypass Wizard - Select Signal Via Page

To access: Select Simulate PI > Analyze Signal-Via Bypassing and select the Select Signal
Via page
Use this page to select the signal via to analyze. Bypass analysis runs on one signal via at a time.
You can run bypass analysis additional times to analyze other signal vias.
Bypass analysis runs on one pair of connected stackup layers at a time. If the signal via connects
to trace segments located on more than two stackup layers, you select which pair of stackup
layers to analyze. You can run bypass analysis additional times to analyze other stackup layer
pairs.
Restrictions:
• Signal-via bypass modeling does not support differential signal-via pairs. The
spreadsheet on this page does not display differential signal vias.
• In LineSim, you can export models only for vias connected to stackup type (coupled or
uncoupled) transmission lines.

Figure 32-29. Bypass Wizard - Select Signal Via Page - LineSim

Table 32-23. Bypass Wizard - Select Signal Via Page - LineSim Contents
Option Description
Check box Select to choose the signal via to analyze.
Schematic Via Name Reference designator for the signal via symbol.

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Bypass Wizard - Select Signal Via Page

Table 32-23. Bypass Wizard - Select Signal Via Page - LineSim Contents (cont.)
Option Description
Connected Layers The complete set of stackup layers the signal via connects to.

Click the plus sign + to expand the spreadsheet row to display all
connected stackup layers.

Click the minus sign - to collapse the spreadsheet row to display

only the top-most connected stackup layer.
Layer Pair Select the portion of the via tube to model by clicking the Layer
Pair cell and selecting a pair of stackup layers.

Figure 32-30. Bypass Wizard - Select Signal Via Page - BoardSim

Table 32-24. Bypass Wizard - Select Signal Via Page - BoardSim Contents
Option Description
Net Name of the net that contains the selected signal via.

This field is blank until you select a signal via in the board
viewer.

To select a signal via:

1. Display the via in the board viewer, zooming and panning if
needed. See “Viewing BoardSim Boards”.
2. Either double-click the via or Right-click via > Select Via.

To replace an existing via selection, select a different via.

Position The X/Y coordinates of the selected signal via.

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Bypass Wizard - Select Signal Via Page

Table 32-24. Bypass Wizard - Select Signal Via Page - BoardSim Contents
Option Description
Connected layers The complete set of stackup layers the signal via connects to.
Pair of connected layers to The pair of stackup layers to include in the model. Select the
analyze portion of the via tube to model by selecting a pair of stackup
layers from the list.

To see the stackup layers with the Via Visualizer, right-click the
via in the board viewer and click View Via Properties.
Pan to To pan to an already-selected via, click Pan to.

The selected via is displayed in the center of the board viewer. If

the wizard dialog box covers part of the board viewer, the
selected via is displayed in the center of the largest visible area of
the board viewer.

Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Analyzing Signal-Via Bypassing” on page 1051

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Bypass Wizard - Set the Target Impedance Page

Bypass Wizard - Set the Target Impedance Page

To access: Select Simulate PI > Analyze Signal-Via Bypassing and select the Set the Target
Impedance page
Use this page to specify the target impedance of the PDN return current paths for signals
transmitted through a single-ended via. The value you specify is displayed as a green reference
line in the Touchstone Viewer when you display the output Z-parameter file.

Figure 32-31. Bypass Wizard - Set the Target Impedance Page

Table 32-25. Bypass Wizard - Set the Target Impedance Page Contents
Option Description
Target Z The target impedance, in milliOhms.

Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Analyzing Signal-Via Bypassing” on page 1051

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Bypass Wizard - Start Analysis Page

Bypass Wizard - Start Analysis Page

To access: Select Simulate PI > Analyze Signal-Via Bypassing and select the Start Analysis
page
Use this page to start a new analysis or load the settings for a saved analysis.
Editing the setting on this page also edits the same setting on the “Bypass Wizard - Run
Analysis Page” on page 1485.

Figure 32-32. Bypass Wizard - Start Analysis Page

Table 32-26. Bypass Wizard - Start Analysis Page Contents

Option Description
New --
Use last configuration Reuse settings from the current BoardSim/LineSim session. This
option is unavailable until you have opened and closed the wizard
in the current BoardSim/LineSim session.

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Bypass Wizard - Start Analysis Page

Table 32-26. Bypass Wizard - Start Analysis Page Contents (cont.)

Option Description
Load save configuration Open a settings file (.DAO) by selecting Load save
configuration, clicking Load, browsing to the file, and then
clicking Open.

Note: If you load a .DAO file saved from LineSim in HyperLynx

8.1.1 or older, you may have to reselect power-supply nets and
pins to probe on other pages in this wizard. Starting with
HyperLynx 8.2, the PDN Editor supports customer-defined
power-supply net names, such as 1.8V. In previous releases, the
PDN Editor used only names that it created automatically, such
as __TPE_VCC__.
Save settings to file Save setup information to the settings file. By default, this file is
written to the <design> folder and named <design>.dao. See
“About Design Folder Locations” on page 1391.

Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Data Flow for Signal-Via Bypass Analysis” on page 1052
“Analyzing Signal-Via Bypassing” on page 1051

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 Dialog Boxes
Channel Characterization Dialog Box

Channel Characterization Dialog Box

To access: Select SI Simulation > [Run IBIS-AMI Channel Analysis | Run FastEye
Channel Analysis], select the Set Up Channel Characterization page, click New/View or
select a crosstalk spreadsheet row and click Characterize Selected
Use this dialog box to set up simulation properties for a new channel characterization.
Optionally, you can view channel-response waveforms automatically created by channel
analysis or manually created by this dialog box.

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Channel Characterization Dialog Box

Figure 32-33. Channel Characterization Dialog Box

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Channel Characterization Dialog Box

Table 32-27. Channel Characterization Dialog Box Contents

Option Description
Signal Channel Signal Channel—Indicates a signal channel without crosstalk
Crosstalk Channel modeling or a victim channel with crosstalk modeling.

Crosstalk Channel—Indicates an aggressor channel. Note

that many options are unavailable for aggressor channels.
Transmitter probe Area
Receiver Probe Area
Pin Name of the channel pin to probe. You can run channel
analysis for one single-ended channel or one differential
channel at a time.

If an expected differential probe does not appear, manually

create a differential probe with the oscilloscope. See
“Manually Attaching Differential Probes” on page 556.

See “Locating Probes at the Die or Pin” on page 555.

Simulation to characterize channel Area
Bit interval When choosing between Bit interval and Bit rate, use the
option that provides the best accuracy. For example, to test
Bit rate
the channel at 333 Mb/s, you can specify a bit rate of 0.333
Gb/s instead of a bit interval of 3.00300300300 ns. Editing
the Bit interval value updates the Bit rate value, and vice
versa.

The values may have been previously set by any of the

following sources, sorted in descending priority:
1. The fitted-poles (.PLS) file used to characterize the
channel and loaded on the IBIS-AMI Channel Analyzer
Wizard - Set Up Channel Characterizations Page. The
.PLS file contains a comment that specifies the bit
interval.
2. The Bit interval and Bit rate values used for standard eye
diagrams and specified in the Stimulus tab of the
Configure Eye Diagram dialog box. See “Setting Up
Global Stimulus for Standard-Eye Diagrams” on
page 541.
IC modeling area IC-model operating conditions:
• Slow-Weak
• Typical
• Fast-Strong
See “Setting IC Operating Parameters” on page 551

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Channel Characterization Dialog Box

Table 32-27. Channel Characterization Dialog Box Contents (cont.)

Option Description
Simulator area Simulator used for channel characterization.
• HyperLynx
• Eldo/ADMS
• <other>
This area displays the simulators you enable in the
Preferences Dialog Box - Circuit Simulators Tab.
Automatic or manual characterization Area
Automatically characterize Automatically create channel-response waveforms and
channel extract a fitted-poles channel characterization file from them.
Manually characterize, using Use a previously-saved channel characterization file. See
my responses “External Analog Channel Characterization Files” on
page 1621.
Characterization type Area
Step/Pulse response Drive step response and pulse response waveforms and
analyze the channel response.
PRBS Drive a PRBS (pseudorandom binary sequence) waveform
and analyze the channel response. The PRBS waveform
usually provides enough time for the initial conditions for the
channel and transmitter/receiver ICs to settle out.

See “Bit Sequence for Automatic Channel Characterization”

on page 645.
Channel response Area
Default (recommended) You typically de-select this option to investigate non-
linearity or other analysis-related errors reported by the
wizard.
ISI effects are gone after Specify the number of bit intervals needed for transient
activity to settle. The wizard reports an error if it detects
unsettled activity at the end of the channel-characterization
simulation. See “inter-symbol interference (ISI)” on
page 1959.

The default value is conservative and provides ample time

for interference, due to the topology and reflection
characteristics of the channel, to die out.

Restriction: You can type values from 50 to 1000, in bit

intervals.

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Channel Characterization Dialog Box

Table 32-27. Channel Characterization Dialog Box Contents (cont.)

Option Description
Number of warmup bits before Specify a sufficient number of bits for the driver and receiver
the Tx/channel are stable circuits to stabilize and reach normal operating conditions.
See “Factors that Affect the Number of Warmup Bits” on
page 1499.

This option adds bits to the beginning of the overall bit

sequence used to create the channel-response extraction
waveforms.

Restriction: You can type values from 0 to 255, in bit

intervals.
Channel-response waveforms Area - The contents of this area highly depends on the
option you enable in the Characterization type area.
Direct waveform only Select to specify only one waveform, instead of a pair of
direct and inverted waveforms.
Pulse and step waveforms Generate both step response and pulse response waveforms.
(recommended) This option is recommended because it enables the wizard to
check the channel for linear response behaviors and to
identify the DC values for logic zero and one, which are
required for accurate results.
Pulse waveform only This option is never available.
Step waveform only Generate only the step waveform.
Pulse Waveform After you optionally Generate Waveforms, you can save
Step Waveform them to disk.
Save As
Restriction: These options are available when you select
Step/Pulse response.
Direct waveform After you optionally Generate Waveforms, you can save
Inverted waveform them to disk.
Save As
Restriction: These options are available when you select
PRBS.
Generate Waveforms Optionally generate the waveforms while this dialog box is
open. This enables you to display the waveforms and save
them to disk.

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Channel Characterization Dialog Box

Table 32-27. Channel Characterization Dialog Box Contents (cont.)

Option Description
Display PRBS Waveforms After you optionally Generate Waveforms, you can display
Display Waveforms them. These waveforms are extracted from the fitted-poles
file and their length is based on the unit interval.

You may want to display channel-response waveforms to

investigate unexpected channel analysis results or to learn
details about the channel characterization. For example, a
good step response waveform eventually settles to the
opposite voltage and a good pulse response waveform has a
single peak and the leading edge starts its transition at about
the same time as the step response.
Browse Load a channel-response waveform file that you either saved
by clicking Save As in this dialog box or created with third-
party software and then clicked Manually characterize, using
my responses.

Waveform files that you create with third-party software

must meet the requirements listed in “External Channel-
Response Waveform Requirements” on page 1499. By
contrast, waveform files created by this dialog box
automatically meet the requirements.
Linearity check Area
Check channel linearity Compare the pulse and step waveforms and report non-linear
(strongly recommended) channel-response. See “Checking Channels for Linear and
Time-Invariant Behavior” on page 642.

You can disable this option for any of the following reasons:
• You are absolutely certain the channel is linear
• You previously ran the wizard with the same input
waveform files, and they passed linearity checking
• You are creating only a worst-case bit sequence and are
not creating a FastEye diagram
Default Enable to apply the default Non-linearity limit, which is the
maximum value that has been empirically tested to provide
FastEye channel analysis results that are very close to time
domain SPICE simulations.

Disable this option to investigate non-linearity or other

analysis related errors reported by the wizard. The wizard
reports an error if the difference of the energy between the
actual and calculated pulse responses exceed the Non-
linearity limit value.

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Channel Characterization Dialog Box

Table 32-27. Channel Characterization Dialog Box Contents (cont.)

Option Description
Non-linearity limit The channel non-linearity threshold. The wizard reports an
error if the channel non-linearity exceeds this value. Channel
analysis checks the linearity of the channel by comparing the
energy in the actual pulse response to the energy in the
calculated pulse response, where the calculated pulse
response is the difference between the actual step response
and the actual step response negated and delayed. See
“Checking Channels for Linear and Time-Invariant
Behavior” on page 642.
Factors that Affect the Number of Warmup Bits
Provide enough simulation time for the driver and receiver circuits to stabilize and reach normal
operating conditions. Some drivers and receivers contain circuitry that requires several bits to
stabilize and produce linear or representative signal transitions. For example, bigger drivers and
receivers may need several bits to set internal flip flops to a known state.
The number of warmup bits depends on any of the following:
• Your knowledge of the driver/receiver model and channel interaction.
• Documentation that comes with a HyperLynx device kit.
• Documentation that comes from the driver/receiver model vendor.
• Troubleshooting efforts—If the extracted step/pulse-response waveforms look wrong
and you suspect that channel stabilization could be a factor, try adding more bits.
External Channel-Response Waveform Requirements
To run FastEye/IBIS-AMI channel analysis with step- and pulse-response or PRBS waveforms
that you create using third-party software, verify they meet the requirements contained in this
section.
After manually editing the waveform files, you can display them in the oscilloscope to verify
their contents. See “Saving and Loading Waveform Files” on page 596.
1. General content requirements.
• Waveform files can contain waveforms for more than one signal or differential pair.
• For differential channels, the simulation waveforms must represent the differential
behavior between the pins in the differential pair.
In other words, do not specify waveforms for the individual pins in a differential
pair.
• If you provide a PRBS waveform, the simulation stimulus should consist of a PRBS
bit pattern with a minimum bit order of 6.

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Channel Characterization Dialog Box

This produces a waveform consisting of 63 bits ().

• If you provide separate PRBS direct and inverted waveform files, they must have the
same number of simulation cycles.
For example, you could create the direct waveforms with the initial stimulus state of
“Low” and create the inverted waveforms with the initial stimulus state of “High”
while inverting the logic state of each bit in the stimulus.
• Provide simulation waveforms that meets or exceeds the minimum extraction time
(also known as “correlation time”) of either of the following:
o ISI x bit interval. You specify the bit interval and ISI values in the Channel
Characterization Dialog Box.
o 15 x maximum driver delay.
2. Provide enough time for the channel to settle down.
The simulation used to create the waveforms must allow enough time for the channel to
dissipate its responses to the stimulus. The suggested simulation run time for each pulse-
response and step-response waveform is the greater of the following:
o Bit interval * ISI_propagation_length_(in_bits)
Physically, this value is how long (in bits) the response to a single transition lasts.
See also: “inter-symbol interference (ISI)” on page 1959
o Longest delay * 15
For example waveforms, see “Analog Channel Characterization Step/Pulse Waveform
Descriptions” on page 1502.
3. Provide enough simulation time for the driver and receiver circuits to stabilize and reach
normal operating conditions.
Some drivers and receivers contain circuitry that requires several simulation cycles to
stabilize and produce linear or representative signal transitions. For example, bigger
drivers and receivers may need several simulation cycles to set internal flip flops to a
known state.
4. Provide enough simulation time for series capacitors to charge.
Series decoupling capacitors in the channel may not always start with the correct DC
initial condition, and the channel may drift for some time before reaching normal DC
values.
5. Provide a quiet time (a period of stimulus inactivity) between the group of simulation
cycles used to stabilize the driver and receiver circuits and the group of simulation
cycles used to provide step- and pulse-responses to characterize the channel behavior.

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Channel Characterization Dialog Box

The quiet time should be long enough for reflections to end. Knowing how long to wait
for the channel to settle may require experimentation because it depends on both the
channel length and the influence of discontinuities and terminations.
6. Step- and pulse-response waveforms start at the same logic state and identical voltage.
While Figure 32-35 and Figure 32-36 show waveforms starting at logic zero, the wizard
accepts externally-generated waveforms starting at logic one. If the step-response
waveform starts at logic one, the pulse-response waveform must also start at logic one.
Similarly, if the step-response waveform starts at logic zero, the pulse-response
waveform must also start at logic zero.
Waveforms automatically created by the wizard start at logic zero.
7. The starting voltages for the step- and pulse-response waveforms must be identical. If
not, FastEye/IBIS-AMI channel analysis reports non-linearity and uses only the step-
response waveform. See Figure 32-34.

Figure 32-34. Pulse and Step Response Waveforms - Zoomed In

See also: FastEye Step and Pulse Responses Dialog Box and PRBS Waveforms Dialog
Box
8. Pulse-response waveforms start and end within a voltage tolerance.
The starting and ending voltages must be within 1% of the peak value of the pulse-
response waveform.
9. Align the initial transition times for the step- and pulse-response waveforms.
The initial rising (or falling) transition must begin at the same time in the step- and
pulse-response waveforms.
10. Remove un-needed portions of the waveforms.

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Channel Characterization Dialog Box

The goal is to provide the step-response behavior in one waveform file and the pulse-
response behavior in another waveform file.
Remove waveform activity preceding and following the step-response or pulse-response
behavior. Remember that the waveforms must provide enough time for the channel to
settle down.
Some complex SPICE models need to run for several simulation cycles for the driver
circuitry to reach normal switching behaviors. Remove this “circuitry start up” portion
of the waveform preceding the step-response or pulse-response behavior.
If you remove waveform activity preceding the step-response or pulse-response
behavior, make sure the start up portion of the final waveforms are identical, that is they
originate from the same voltage and transition time.
11. For differential channels, the simulation waveforms must represent the differential
behavior between the pins in the differential pair.
In other words, do not specify waveforms for the individual pins in a differential pair.

Analog Channel Characterization Step/Pulse Waveform Descriptions

The Channel Characterization Dialog Box can use the following types of step/pulse waveforms:
• Single edge step— Step-response curves show where reflections occur and how long
energy is stored in the channel. From a bit sequence perspective, a step-response
waveform resembles the 011111111111 bit sequence, with many trailing ones. See
Figure 32-35.
• Single pulse— Pulse-response curves show information about ISI and serve as a
building block for the FastEye/IBIS-AMI analysis contour. From a bit sequence
perspective, a pulse-response waveform resembles the 010000000000 bit sequence, with
many trailing zeroes. See Figure 32-36.

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Channel Characterization Dialog Box

Figure 32-35. Step Response Waveform - Full

Figure 32-36. Pulse Response Waveform - Full

Supported Analog Channel Characterization Waveform File Formats

The wizard accepts waveform files in the following formats:
• .LIS— Created by SPICE simulation
• .LIS (HyperLynx)— Created by the HyperLynx oscilloscope
See also: “Saving Waveform Files” on page 597
• .CHI— Created by ADMS
• .CSV— Created by ICX, ICX Pro, and the HyperLynx oscilloscope
See also: “Saving Waveform Files” on page 597

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Channel Characterization Dialog Box

Related Topics
“IBIS-AMI Channel Analysis QuickStart” on page 612
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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 Dialog Boxes
Decoupling Mounting Scheme Editor Dialog Box

Decoupling Mounting Scheme Editor Dialog Box

To access: Click Edit Mounting Scheme in the Add/Edit Decoupling Capacitor(s) dialog box.
Use this dialog box to manually create or modify the mounting scheme for decoupling
capacitors. For instructions on how to use the editor, see Defining Decoupling Capacitor
Mounting Using the Decoupling Mounting Scheme Editor.
The distance from the center of the capacitor package to the mouse pointer is displayed in the
lower-right corner of the Decoupling Mounting Scheme Editor.
Caution
Do not specify decoupling capacitor mounting using this dialog box if the capacitor
model you assigned in the Model area of the Add/Edit Decoupling Capacitor(s) Dialog
Box includes via mounting.

Figure 32-37. Decoupling Mounting Scheme Editor Dialog Box

Table 32-28. Decoupling Mounting Scheme Editor Dialog Box Contents

Palette Object Description
Load Mounting Scheme Select to load an existing decoupling mounting schematic
(DMS) file.

Save Mounting Scheme Save mounting scheme to a DMS file.

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Decoupling Mounting Scheme Editor Dialog Box

Table 32-28. Decoupling Mounting Scheme Editor Dialog Box Contents (cont.)
Palette Object Description
Edit Decoupling Circuit Opens the Edit Decoupling Circuit dialog box. This
dialog box enables you to change the number of ports on
a circuit, specify whether the capacitor is on the top or
bottom of the board, and modify the placement of ports.
Add Via Opens the Add/Edit Via Dialog Box. Use to add
additional vias to the decoupling capacitor mounting
scheme. To modify existing vias, double click the via to
open the Add/Edit Via Dialog Box.
Add Trace Segment Opens Add Trace Segment dialog box and enables trace
routing mode. Use to draw one or more trace segments
that connect vias to capacitor pins.
Delete schematic element Removes a selected object from the schematic.

Zoom In Use these buttons to change the scale of the display.

Zoom Out

Fit to Window

Related Topics
Defining Decoupling Capacitor Mounting Using the Decoupling Mounting Scheme Editor

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 Dialog Boxes
Decoupling Wizard - Check Capacitor Models Page

Decoupling Wizard - Check Capacitor Models Page

To access: Select Simulate PI > Analyze Decoupling and select the Check Capacitor Models
page
Use this page to review and edit decoupling capacitor model assignments.
Double-click a capacitor to assign or edit capacitor models. See “Assign Decoupling-Capacitor
Models Dialog Box” on page 1453.

Related Topics
“Running Decoupling Analysis” on page 1026
“Analyzing Decoupling” on page 1013

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Dialog Boxes
Decoupling Wizard - Choose a Type of Analysis Page

Decoupling Wizard - Choose a Type of Analysis Page

To access: Select Simulate PI > Analyze Decoupling and select the Choose a Type of
Analysis page
Use this page to choose the type of decoupling analysis to run.

Tip: When analyzing a pair of power-supply nets for the first time, you may want to get
good results from quick analysis and lumped analysis before running distributed analysis
(which takes much longer to set up and run). See Figure 23-1 on page 1016 (BoardSim)
or Figure 23-2 on page 1021 (LineSim).

Figure 32-38. Decoupling Wizard - Choose a Type of Analysis Page

Table 32-29. Decoupling Wizard - Choose a Type of Analysis Page Contents

Option Description
Quick Analysis Quickly create a spreadsheet containing detailed information
about all decoupling capacitors in the design, including total
mounting inductance and mounted resonant frequency. This
information enables you to identify ineffective decoupling
capacitors.

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Decoupling Wizard - Choose a Type of Analysis Page

Table 32-29. Decoupling Wizard - Choose a Type of Analysis Page Contents

Option Description
Lumped Analysis Model the pair of power-supply nets as a series of directly-
connected elements and create a Z-parameter model. See “Circuit
Topology for Lumped Decoupling Analysis” on page 1029 and
“Usage Notes” on page 1509.

Lumped analysis runs quickly, but its results may be optimistic

because it does not take into account spreading inductance,
capacitor locations, and plane resonances. If the lumped analysis
results are not acceptable, you need to improve decoupling by
changing the quantity or value of decoupling capacitors, editing
stackup properties, and so on. Once the lumped analysis results
are acceptable, run distributed analysis.
Distributed Analysis Model the pair of power-supply nets as one or more transmission
planes and create a Z-parameter model. See “Circuit Topology
for Distributed Decoupling Analysis” on page 1030 and “Usage
Notes” on page 1509.

This method provides the most accurate Z-parameter model, but

consumes more memory and run time than lumped analysis.

Usage Notes
The Z-parameter model created by lumped and distributed analyses reports the impedance of a
pair of power-supply nets over a frequency range. The Touchstone Viewer automatically
displays the model. You can then see if the reported impedances meet the target impedance for
the PDN.
Decoupling analysis searches the design to identify all the capacitors that are connected to the
pair of power-supply nets. Sometimes BoardSim/LineSim cannot identify some or all capacitors
due to complex geometries for capacitor mounting connections. The log and spreadsheet files
report individual decoupling capacitors that are included and excluded from the simulation
model.
Related Topics
“Running Decoupling Analysis” on page 1026
“Analyzing Decoupling” on page 1013

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Dialog Boxes
Decoupling Wizard - Choose Easy / Custom Page

Decoupling Wizard - Choose Easy / Custom Page

To access: Select Simulate PI > Analyze Decoupling and select the Choose Easy / Custom
page
Use this page to choose between default and custom decoupling analysis options.
Restriction: This page is unavailable if you select Quick Analysis on the Decoupling Wizard -
Choose a Type of Analysis Page.

Figure 32-39. Decoupling Wizard - Choose Easy / Custom Page

Table 32-30. Decoupling Wizard - Choose Easy / Custom Page Contents

Option Description
Easy Popular analysis settings are automatically enabled on some of
the following wizard pages. Many of the automatically-enabled
settings become read only.
Custom You can edit all analysis settings on the following wizard pages

Related Topics
“Running Decoupling Analysis” on page 1026
“Analyzing Decoupling” on page 1013

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 Dialog Boxes
Decoupling Wizard - Control Frequency Sweep Page

Decoupling Wizard - Control Frequency Sweep Page

To access: Select Simulate PI > Analyze Decoupling and select the Control Frequency
Sweep page
Use this page to edit frequency range and sampling options, both of which affect analysis run
time and the resolution of the Z-parameter model.
Restriction: This page is unavailable if you select Quick Analysis on the Decoupling Wizard -
Choose a Type of Analysis Page.

Figure 32-40. Decoupling Wizard - Control Frequency Sweep Page

Table 32-31. Decoupling Wizard - Control Frequency Sweep Page Contents

Option Description
Min frequency The minimum simulation frequency, in MHz.
Max frequency The maximum simulation frequency, in MHz.

Many ICs have in-package decoupling that provide the main

decoupling effects above a certain frequency, such as 150 MHz.
This means decoupling capacitors and buried capacitance located
in the PCB contribute little or no decoupling above this design-
dependent frequency.

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Dialog Boxes
Decoupling Wizard - Control Frequency Sweep Page

Table 32-31. Decoupling Wizard - Control Frequency Sweep Page Contents

Option Description
Adaptive sampling Varies the sampling step size depending on model characteristics.
The adaptive scale is better than logarithmic and linear because it
Restriction: This option is increases the sampling rate near frequencies with resonances.
unavailable if you enable the
Easy option in the
Decoupling Wizard -
Choose Easy / Custom Page.
Logarithmic sampling Sampling points are distributed at logarithmic intervals across the
frequency range. The intervals between sampling points are
Restriction: This option is smaller at lower frequencies and larger for higher frequencies.
unavailable if you enable the With logarithmic sampling, every next frequency point is equal
Easy option in the to the previous value times a factor K > 1. This produces a
Decoupling Wizard - constant increase ratio, but the absolute distance between
Choose Easy / Custom Page. sampling points grows.
Linear sampling Sampling points are distributed at equal intervals across the
frequency range.
Restriction: This option is
unavailable if you enable the
Easy option in the
Decoupling Wizard -
Choose Easy / Custom Page.
Accuracy at resonances For lumped analysis, enabling the High option may still yield
reasonably fast simulation run times.
Restriction: This option is
unavailable unless you For distributed analysis, you should take the complexity of the
enable the Adaptive design into account. If the design has large numbers of power-
sampling option on this supply nets, hundreds of decoupling capacitors, and hundreds or
page. thousands of stitching vias, enabling the Low option provides
preliminary results with decreased analysis run time. After
evaluating the preliminary results, you can identify which
frequency ranges interest you the most and try running analysis
with higher accuracy on each range of interest.
Minimum number of The number of samples you specify applies to flat, non-resonant,
samples in flat, non-resonant regions of an impedance profile. See the enclosed curve region
regions Figure 32-41 on page 1513.

Restriction: This option is

unavailable unless you
enable the Adaptive
sampling option on this
page.

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 Dialog Boxes
Decoupling Wizard - Control Frequency Sweep Page

Table 32-31. Decoupling Wizard - Control Frequency Sweep Page Contents

Option Description
Number of samples The number of samples you specify applies to the entire
frequency range.
Restriction: This option is
unavailable if you enable the
Adaptive sampling option
on this page.
Default Click Default to restore the initial settings.

Flat and Non-Resonant Region of an Impedance Profile

Figure 32-41. Flat and Non-Resonant Region of an Impedance Profile

Related Topics
“Running Decoupling Analysis” on page 1026
“Analyzing Decoupling” on page 1013

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Dialog Boxes
Decoupling Wizard - Customize Settings Page

Decoupling Wizard - Customize Settings Page

To access: Select Simulate PI > Analyze Decoupling and select the Customize Settings page
Use this page to enable detailed analysis options. Simulating the design with different sets of
enabled and disabled options can help you determine how individual types of design properties
contribute to decoupling performance.
Restrictions:
• If you selected Easy on the Decoupling Wizard - Choose Easy / Custom Page, you
cannot edit options on this page.
• This page is unavailable if you select Quick Analysis on the Decoupling Wizard -
Choose a Type of Analysis Page.

Figure 32-42. Decoupling Wizard - Customize Settings Page - Lumped Analysis

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 Dialog Boxes
Decoupling Wizard - Customize Settings Page

Figure 32-43. Decoupling Wizard - Customize Settings Page - Distributed

Analysis

Table 32-32. Decoupling Wizard - Customize Settings Page Contents

Option Description
Include all power / ground Examine transmission planes formed by all power-supply nets
nets in the analysis that can influence the decoupling behavior of the already-selected
pair of power-supply nets. This can happen when transmission
planes formed by non-selected power-supply nets receive energy
from the analysis. For example, transmission planes formed by
other pairs of power-supply nets (possibly including one of the
currently-selected nets) can be “activated” by energy traveling
through stitching vias that run vertically throughout the stackup.

Note: Enabling this option can increase analysis run time because
the analysis model and calculations are bigger and more complex.

Disable this option to analyze only the pair of power-supply nets

specified on the Decoupling Wizard - Select Nets for Analysis
Page. You might disable this option if you are convinced that no
other pairs of power-supply nets contribute to the decoupling
behavior of the selected power-supply nets.
Include capacitor mounting To determine the contribution of capacitor mounting inductance
inductance to the overall decoupling performance, you can run analysis with
this option enabled, run it again with this option disabled, and
then compare the results.

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Dialog Boxes
Decoupling Wizard - Customize Settings Page

Table 32-32. Decoupling Wizard - Customize Settings Page Contents (cont.)

Option Description
Remove series inductance Exclude the series inductance that is unique to each power-supply
unique to each power pin, to pin. Inductance from IC power-supply pin mounting, such as
see plane decoupling more fanout traces and the portions of mounting vias that lie above the
clearly first reference layer, can obscure the impedance of the overall
transmission-plane decoupling. Including such inductance in
analysis may lead to overly pessimistic (that is, high-impedance)
Restriction: This option is results, because ICs actually use many power pins in parallel,
unavailable if you enable the thereby reducing the effect of the series inductance.
“Lumped Analysis” option
on the Decoupling Wizard - Enable this option to evaluate the PDN impedance without the
Choose a Type of Analysis effects of power-supply pin series mounting inductance. For
Page. example, you might do this to evaluate the effects of decoupling-
capacitor placement or values on PDN impedance.

Disable this option to evaluate the effects of power-supply pin

series mounting inductance on PDN impedance.
Include inter-plane To determine the contribution of inter-plane capacitance to the
capacitance overall decoupling performance, you can run analysis with this
option enabled, run it again with this option disabled, and then
Restriction: This option is compare the results.
unavailable if you enable the
“Distributed Analysis”
option on the Decoupling
Wizard - Choose a Type of
Analysis Page.
Include poorly connected Include all decoupling capacitors in the simulation.
capacitors
Normally, simulation excludes capacitors with poor or non-ideal
Restriction: This option is mounting properties that make the capacitor useful only at low
unavailable if you enable the frequencies. Examples of poor mounting include long connection
“Distributed Analysis” traces and vias located outside the power-ground plane pairs
option on the Decoupling being decoupled. These types of capacitor mounting usually have
Wizard - Choose a Type of large inductances, which cause them to be mostly ineffective at
Analysis Page, high frequencies, and are difficult to accurately model for
simulation. In some cases, only a rough approximation of the
inductance can be made for capacitors with this type of
mounting.

If you enable Quick Analysis in the Decoupling Wizard - Choose

a Type of Analysis Page, decoupling analysis automatically
creates a spreadsheet containing decoupling capacitor
information, including mounting quality.

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Decoupling Wizard - Customize Settings Page

Table 32-32. Decoupling Wizard - Customize Settings Page Contents (cont.)

Option Description
Enable stitching-via Find stitching vias that are located close together and merge their
optimization individual models into an equivalent model. This process is
repeated across the transmission plane. Reducing the number of
Restriction: If you enabled stitching-via models speeds up simulation and reduces memory
the “Lumped Analysis” consumption because each model adds a variable to the systems
option on the Decoupling of equations to solve. See “Stitching-Via Optimization -
Wizard - Choose a Type of Decoupling Wizard” on page 1517.
Analysis Page, this option is
unavailable.
Stitching-Via Optimization - Decoupling Wizard
Stitching-via optimization takes advantage of the fact that when the size of objects (or groups of
them) is much smaller than the wavelength of a signal, the signal does not respond to them in
detail, and approximate models can accurately represent those objects in simulation.
The Tolerance slider controls the merging radius for optimization:
• Low—1/30th of the minimum wavelength of the signal
• Medium—1/20th of the minimum wavelength of the signal
• High—1/10th of the minimum wavelength of the signal
For example, let us say that decoupling analysis does not exceed 300 MHz and that the
wavelength of a 300 MHz signal in FR-4 is about 20 inches. In electromagnetic analysis, 1/10th
wavelength is considered to be safely “much smaller” than the wavelength of the signal and that
within a 2 inch radius, we can avoid representing individual stitching vias by modeling them
with one equivalent (or “clumped”) via.
Not all stitching vias are eligible for optimization and most optimization takes place far away
from IC and decoupling-capacitor pins. The optimization algorithm preserves individual models
for caging vias and for stitching vias that contribute significantly to transmission-plane or
decoupling-capacitor inductance. As a result, this setting may have little effect for designs
where most of the stitching vias in the transmission plane contribute significantly to
transmission-plane or decoupling-capacitor inductance.
For example, caging vias that are located very close to the IC or decoupling-capacitor pin are
always modeled individually. In other words, if you run decoupling analysis to produce Z
parameters for an IC power-supply pin that uses a via with a stitching section, then any very-
nearby stitching vias are preserved as individual models to observe their full caging effect.
Related Topics
“Running Decoupling Analysis” on page 1026
“Decoupling Capacitor Report Spreadsheets” on page 1031
“Analyzing Decoupling” on page 1013

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Dialog Boxes
Decoupling Wizard - Run Analysis Page

Decoupling Wizard - Run Analysis Page

To access: Select Simulate PI > Analyze Decoupling and select the Run Analysis page
Use this page to choose the name of the Z-parameter file created by decoupling analysis, to save
to a file the wizard page settings, and to save to a spreadsheet information for all the decoupling
capacitors connected to the pair of power-supply nets.
Editing a setting on this page updates the same setting on the Decoupling Wizard - Start
Analysis Page.

Figure 32-44. Decoupling Wizard - Run Analysis Page

Table 32-33. Decoupling Wizard - Run Analysis Page Contents

Option Description
Save settings to file Save wizard settings to a .DAO file. The default file location is
the <design> folder. See “About Design Folder Locations” on
page 1391. You can change the file locations.

To specify another settings file location, click Browse to specify

the file name and location.

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Decoupling Wizard - Run Analysis Page

Table 32-33. Decoupling Wizard - Run Analysis Page Contents (cont.)

Option Description
Auto-generate output file Name the output file using form
name <design>_<simulation_iteration>.z<number_of_ports>p.

Restriction: This option is For example, test_2.z6p.

unavailable if you enable the
Quick Analysis option on <number_of_ports> is always one for lumped analysis.
the Decoupling Wizard -
Choose a Type of Analysis The default file location is the <design> folder. See “About
Page. Design Folder Locations” on page 1391.

To specify another output file location, deselect Auto-generate

output file name and click Browse to specify the file name and
location.
Save spreadsheet Create a spreadsheet containing decoupling capacitor mounting
information. See “Decoupling Capacitor Report Spreadsheets”
Restriction: This option is on page 1031.
unavailable unless you
enable the Quick Analysis The default file location is the <design> folder. See “About
option on the Decoupling Design Folder Locations” on page 1391.
Wizard - Choose a Type of
Analysis Page. To specify another output file location, click Browse to specify
the file name and location.
Microsoft Excel (.XLS) --
Comma-separated (.CSV) --

Related Topics
“Running Decoupling Analysis” on page 1026
“Data Flow for Decoupling Analysis” on page 1027
“Analyzing Decoupling” on page 1013

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Dialog Boxes
Decoupling Wizard - Select IC Power Pins Page

Decoupling Wizard - Select IC Power Pins Page

To access: Select Simulate PI > Analyze Decoupling and select the Select IC Power Pins
page
Use this page to select the pin(s) on the pair of power-supply nets to include as ports in the Z-
parameter model created by decoupling analysis. The more pins you select, the longer analysis
takes and the larger the model file becomes.
Restriction: This page is unavailable unless you have selected a pair of power-supply nets and
selected distributed analysis. See “Decoupling Wizard - Select Nets for Analysis Page” on
page 1523 and “Decoupling Wizard - Choose a Type of Analysis Page” on page 1508.

Figure 32-45. Decoupling Wizard - Select IC Power Pins Page - LineSim

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 Dialog Boxes
Decoupling Wizard - Select IC Power Pins Page

Figure 32-46. Decoupling Wizard - Select IC Power Pins Page - BoardSim

Table 32-34. Decoupling Wizard - Select IC Power Pins Page Contents

Option Description
Spreadsheet check box Select the check box for each component pin to include in
decoupling analysis.

See “Identifying IC Power-Supply Pins That Can Be Selected”

on page 1522.
Group by Reference Collapse spreadsheet rows into groups of pins with the same
Designators reference designator.
Add IC Power Pin Click Add IC Power Pin to add missing IC power-supply pins to
the spreadsheet. You assign reference nets to power-supply pins,
Restriction: This option is to make them available as Z-parameter model ports. If the
unavailable in LineSim. spreadsheet does not display the added port, the transmission
plane does not enclose it with sufficient overlap. See “Identifying
IC Power-Supply Pins That Can Be Selected” on page 1522.

The Assign Power Integrity Models dialog box opens. For

information about assigning reference nets to pins, see
“Assigning Power-Integrity Models - BoardSim”.
Check All --

Restriction: This option is

unavailable in LineSim.

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Dialog Boxes
Decoupling Wizard - Select IC Power Pins Page

Table 32-34. Decoupling Wizard - Select IC Power Pins Page Contents (cont.)
Option Description
Uncheck All --

Restriction: This option is

unavailable in LineSim.
Identifying IC Power-Supply Pins That Can Be Selected
This wizard page searches the design for transmission planes that either enclose IC power-
supply pins or are very close (about 118 mils or 3 millimeters) to them. In LineSim, if at least
one of the found transmission planes has a layer that connects to the IC power-supply pin and a
layer that references the IC power-supply pin (that is, you identified it as a reference layer when
you added the IC power-supply pin symbol to the PDN layout), the IC power-supply pin is
available for probing. BoardSim has the same behavior as LineSim, except the reference layer
for the IC power-supply pin does not have to be found.
See also: “About Transmission Planes” on page 1373
For example, in LineSim, let us assume an IC power-supply pin connects to a metal area on
LAYER1 on net VCC and references metal areas on LAYER5 on net GND. If the wizard finds
at least one transmission plane that contains a metal area on LAYER1 on net VCC and a metal
area on LAYER5 on net GND, the IC power-supply pin is available for probing.
Note that even if an IC power-supply pin is available for probing, it can be rejected when you
finish running the wizard, when a more-detailed analysis of its location is performed.
Related Topics
“Running Decoupling Analysis” on page 1026
“Analyzing Decoupling” on page 1013

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 Dialog Boxes
Decoupling Wizard - Select Nets for Analysis Page

Decoupling Wizard - Select Nets for Analysis Page

To access: Select Simulate PI > Analyze Decoupling and select the Select Nets for Analysis
page
Use this page to select the pair of power-supply nets that form the transmission-plane you want
to analyze.
Restriction: This page is unavailable if you select Quick Analysis on the Decoupling Wizard -
Choose a Type of Analysis Page.

Figure 32-47. Decoupling Wizard - Select Nets for Analysis Page

Table 32-35. Select Nets for Analysis Page Contents

Field Description
Available nets All the unassigned power-supply nets. See “Usage Notes” on
page 1524.

To add a power-supply net to the Nets to analyze list, do either of

the following:
• Double-click the power-supply net.
• Select the power-supply net and click .
Nets to analyze Assign a pair of power-supply nets for analysis.

To remove a power-supply net from the Nets to analyze list, do

either of the following:
• Double-click the power-supply net.
• Select the power-supply net and click .

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Dialog Boxes
Decoupling Wizard - Select Nets for Analysis Page

Usage Notes
In LineSim, the Available nets list displays power-supply nets defined in the PDN Editor. The
PDN Editor initially contains a power-supply net for each stackup layer that is assigned the
“plane” usage type. If you short together power-supply nets, the Available Nets area displays
the name of only one of the power-supply nets. You can short power-supply nets with stitching
vias and by specifying two or more connected or reference layers a IC power-supply pin,
decoupling via pin, or VRM pin.
In BoardSim, the Available nets list displays power-supply nets fully or partially formed by
copper plane areas. The Available nets list excludes power-supply nets formed only by trace
segments.
Related Topics
“Running Decoupling Analysis” on page 1026
“Analyzing Decoupling” on page 1013

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 Dialog Boxes
Decoupling Wizard - Set the Target Impedance Page

Decoupling Wizard - Set the Target Impedance Page

To access: Select Simulate PI > Analyze Decoupling and select the Set the Target
Impedance page
Use this page to specify the target impedance of the pair of power-supply nets. The value you
specify is displayed as a green reference line in the Touchstone Viewer when you display the
output Z-parameter file.
Restriction: This page is unavailable if you select Quick Analysis on the Decoupling Wizard -
Choose a Type of Analysis Page.

Figure 32-48. Decoupling Wizard - Set the Target Impedance Page

Table 32-36. Decoupling Wizard - Set the Target Impedance Page Contents
Option Description
Target Z The target impedance, in milliOhms.
Calculator If you do not know the target impedance, but you know peak
transient current, nominal VCC, and power-supply ripple, click
Calculator to open the Target-Z Wizard. See “Target-Z Wizard -
Specify Peak Transient Current Page” on page 1884.

Related Topics
“Running Decoupling Analysis” on page 1026
“Analyzing Decoupling” on page 1013

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Dialog Boxes
Decoupling Wizard - Start Analysis Page

Decoupling Wizard - Start Analysis Page

To access: Select Simulate PI > Analyze Decoupling and select the Start Analysis page
Use this page to start a new analysis or load the settings for a saved analysis.
Editing the setting on this page also edits the same setting on the Decoupling Wizard - Run
Analysis Page.

Figure 32-49. Decoupling Wizard - Start Analysis Page

Table 32-37. Decoupling Wizard - Start Analysis Page Contents

Option Description
New --
Use last configuration Reuse settings from the current BoardSim/LineSim session. This
option is unavailable until you have opened and closed the wizard
in the current BoardSim/LineSim session.

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Decoupling Wizard - Start Analysis Page

Table 32-37. Decoupling Wizard - Start Analysis Page Contents (cont.)

Option Description
Load save configuration Open a settings file (.DAO) by selecting Load save
configuration, clicking Load, browsing to the file, and then
clicking Open.

Note: If you load a .DAO file saved from LineSim in HyperLynx

8.1.1 or older, you may have to reselect power-supply nets and
pins to probe on other pages in this wizard. Starting with
HyperLynx 8.2, the PDN Editor supports customer-defined
power-supply net names, such as 1.8V. In previous releases, the
PDN Editor used only names that it created automatically, such
as __TPE_VCC__.
Save settings to file Save setup information to the settings file. By default, this file is
written to the <design> folder and named <design>.dao. See
“About Design Folder Locations” on page 1391.

Related Topics
“Running Decoupling Analysis” on page 1026
“Data Flow for Decoupling Analysis” on page 1027
“Analyzing Decoupling” on page 1013

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Dialog Boxes
Define Constraint Template Dialog Box

Define Constraint Template Dialog Box

To access:
• Select Edit > Constraint Template, the Select Driver dialog box opens. Select a driver
pin and click OK.
• Click Edit Template in the Export Constraint Templates Dialog Box (Export >
Constraint Template).
Use this dialog box to specify the detailed constraints to export to CES.
LineSim enables you to specify pin pairs and From/Tos in a graphical and intuitive way. When
this dialog box is open, you can right-click IC pins in the free-form schematic to add them to the
constraint template. For large or complex nets, this graphical method can be easier and more
accurate than selecting pin names in a spreadsheet.
The narrow/basic version of this dialog box obscures less of the schematic when defining pin
pairs by double-clicking or right-clicking ICs in the schematic. You can define advanced
constraints after defining the pin pairs.

Figure 32-50. Define Constraint Template Dialog Box

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Define Constraint Template Dialog Box

Table 32-38. Define Constraint Template Dialog Box Contents

Tab Description
Length/Delay Use the Length/Delay tab to specify length and delay constraints for the
net and its pin pairs. Add only the constraints you need; it is OK to have
empty spreadsheet cells.
Diff Pair Use the Diff Pair tab to specify constraints for differential pairs. Add
only the constraints you need; it is OK to have empty value cells.
Net Scheduling Use the Net Scheduling tab to specify FromTos that appear in the
FromTos section of the exported template file. FromTos represent the
pin-to-pin, or pin-to-branch-point, routing sequence of a net or
differential pair.
Pin Sets Use the Pin Sets tab to view pin sets and modify the type property for
pin sets. If a schematic does not have any pin sets, the Pin Sets tab is
empty.

Related Topics
Exporting Constraint Templates from LineSim

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Dialog Boxes
Define Constraint Template Dialog Box - Length/Delay Tab

Define Constraint Template Dialog Box - Length/Delay Tab

To access: Define Constraint Template Dialog Box — Length/Delay Tab
Use the Length/Delay tab to specify length and delay constraints for the net and its pin pairs.
Add only the constraints you need; it is OK to have empty spreadsheet cells.
For complete and up-to-date constraint descriptions, refer to the documentation for Constraint
Editor System (CES).

Figure 32-51. Define Constraint Templates Dialog Box - Length/Delay Tab

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Define Constraint Template Dialog Box - Length/Delay Tab

Table 32-39. Define Constraint Templates Dialog Box - Length/Delay Tab

Contents
Field Description
Net-level constraint section Select Length or Delay in the Type column and enter constraint
values. Click Expand To Advanced Mode to see a
complete list of constraints. For constraint descriptions, see
Table 32-40.
Type • Length refers to physical length.
• Delay refers to electrical length, such as signal propagation
delay or time of flight (TOF).
Constrained pin pairs • Use the Constrained Pin Pairs spreadsheet to specify pin pair
section constraints that appear in the PinPairs section of the exported
template file.

Pin pairs are not the same as FromTos. Pin pairs define
electrical pairings that define electrical relationships among
component pins. FromTos define physical pairings used to
instruct the router to implement traces between component
pins.

Restrictions:
• The net must have at least one driver and receiver to add pin
pairs to the Constrained Pin Pairs spreadsheet.
• For differential nets, virtual pins are not exported to the
template file.
Type • Length refers to physical length.
• Delay refers to electrical length, such as signal propagation
delay or time of flight (TOF).
Pin 1, Pin 2 You can select a pin pairs from the list or from the schematic.

To select pin pairs from the schematic:

• Right-click the pin and click Add as Pin 1 (or Add as Pin 2).
The pin is added to the top-most blank Pin 1 cell (or Pin 2
cell).
• Double-click the pin. Double-clicking adds the pin name to
the top-most and left-most blank Pin 1 or Pin 2 cell.
• Double-click the single-ended (not differential) IC symbol.
Double-clicking adds the pin name to the top-most and left-
most blank Pin 1 or Pin 2 cell.
Constraints For constraint descriptions, see Table 32-40.

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Dialog Boxes
Define Constraint Template Dialog Box - Length/Delay Tab

Table 32-39. Define Constraint Templates Dialog Box - Length/Delay Tab

Contents (cont.)
Field Description
Add All Adds pin pairs for all IC components, passive components, and
virtual pins.

You can also right-click anywhere in the schematic and click

Add All Pin Pairs.
Add Drvs -> Adds pin pairs for all combinations of IC components (including
Rcvrs virtual pins), but not for passive components.

You can also right-click anywhere in the schematic and click

Add Drv->Rcv Pin Pairs.
Delete To delete pin pairs, do any of the following and click Delete:
• Select a block of rows by dragging the mouse over the first
column.
• Select multiple non-adjacent rows by pressing Ctrl+Click in
the first column.
• Select an individual row, or deselect all currently-selected
rows, by clicking its first column.
Expand To Advanced Mode Click to see all constraints.

Switch to Basic Mode << Click to see only the Min and Max constraints.

Table 32-40. Constraint Descriptions

Constraint Description
Min The minimum acceptable physical routing length or signal
propagation delay between component pins.
Max The maximum acceptable physical routing length or signal
propagation delay between component pins.
Match A text string (such a 1, A, or group1) that identifies the net as
belonging to a group of nets with similar length or time of flight
delay routing requirements.

CES supports match names consisting of a single alphabetical or

numerical character, or a string of characters starting with an
alphabetical character followed by any combination of
alphabetical, numerical, and underscore _ characters.
Tol A tolerance range for net routing delay requirements for nets
belonging to the same match name group.

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Define Constraint Template Dialog Box - Length/Delay Tab

Table 32-40. Constraint Descriptions (cont.)

Constraint Description
Formula A formula, following the rules supported by CES, that can be
used to create pin pair delay relationships.

You can set up delay relationships among similar design objects

that would benefit from such associations. For example, you can
set one pin pair delay to equal the delay of another (=), specify
that the delay of one net must be greater than or less than the
delay of another (> or <), add or subtract the delay of one pin
pair to or from the delay of another. You can also include
constants and variables to define net and pin pair delay with even
more detail.

LineSim does not check formulas for validity.

Related Topics
Define Constraint Template Dialog Box
Exporting Constraint Templates from LineSim

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Dialog Boxes
Define Constraint Template Dialog Box - Diff Pair Tab

Define Constraint Template Dialog Box - Diff Pair Tab

To access: Open the Define Constraint Template Dialog Box and select the Diff Pair tab
Use the Diff Pair tab to specify constraints for differential pairs. Add only the constraints you
need; it is OK to have empty value cells.

Figure 32-52. Define Constraint Templates Dialog Box - Diff Pair Tab

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Define Constraint Template Dialog Box - Diff Pair Tab

Table 32-41. Define Constraint Templates Dialog Box - Diff Pair Tab Contents
Field Description
Pair Tolerance section
Constraint Type • Length refers to physical length.
• Delay refers to electrical length, such as signal propagation
delay or time of flight (TOF).
Max Tolerance Net lengths/delays are measured from pin to pin. Tolerance is
measured by subtracting one net length/delay from the other, and
taking the absolute value of the difference.
Routing convergence section
Max Distance The maximum distance between the pins and the convergence
point.
Max difference/ The maximum difference of the routing lengths between the pins
tolerance and the convergence point.

The convergence point is where the traces begin the controlled

routing gap, which creates a uniform mutual impedance as the
traces are routed.
Separation Distance section
Max distance Differential pair trace separation exists where the controlled
routing gap is temporarily exceeded to avoid a routing obstacle,
such as a via or pin.
Differential Z section
Target Target impedance.

Note: The physical spacing for differential pairs is specified per-

layer (not per-net) in the CES "Trace and Via Properties" page.
Physical spacing rules are used whenever the differential Z target
can not be met.
Tolerance +/- Tolerance for target impedance.
Net class Enter the name of the net class.

Related Topics
Define Constraint Template Dialog Box
Exporting Constraint Templates from LineSim

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Dialog Boxes
Define Constraint Template Dialog Box - Net Scheduling Tab

Define Constraint Template Dialog Box - Net Scheduling

Tab
To access: Open the Define Constraint Template Dialog Box and select the Net Scheduling tab
Use the Net Scheduling tab to specify FromTos that appear in the FromTos section of the
exported template file. FromTos represent the pin-to-pin, or pin-to-branch-point, routing
sequence of a net or differential pair.
A branch point exists where one transmission line connects to two or more other transmission
lines. The free-form schematic automatically creates “virtual pins” to serve as branch points.
See “Virtual Pins“.
Requirement: If the schematic contains virtual pins or custom topologies, specify the net
scheduling in this tab.
FromTos are not the same as pin pairs. FromTos define physical pairings used to instruct the
router to implement traces between component pins. Pin pairs define electrical pairings that
define electrical relationships among component pins.

Figure 32-53. Define Constraint Templates Dialog Box - Net Scheduling Tab

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 Dialog Boxes
Define Constraint Template Dialog Box - Net Scheduling Tab

Table 32-42. Define Constraint Templates Dialog Box - Net Scheduling Tab
Contents
Field Description
From Select a from pin.

Restriction: Virtual pins are not available from the lists in the
spreadsheet cells. For information about virtual pins, see
Virtual Pins.
To Select a to pin.

Restriction: Virtual pins are not available from the lists in the
spreadsheet cells. See Virtual Pins.
Use Schematic Click to add FromTos for all IC components, passive
Topology components, and virtual pins.

You can also right-click anywhere in the schematic and select

Use Schematic Topology’s FromTo’s.
Delete Deletes selected row.

Usage Notes
To add FromTos, do any of the following:
• To add FromTos for all IC components, passive components, and virtual pins, do either
of the following:
o Click Use Schematic Topology.
o In the schematic, right-click anywhere and click Use Schematic Topology’s
FromTo’s.
• To add individual FromTos, do any of the following:
o In the schematic, right-click the pin and click Add as From or Add as To. The pin is
added to the top-most blank From or To cell.
o In the schematic, double-click the pin. Double-clicking adds the pin name to the top-
most blank From or To cell.
o In the schematic, double-click the single-ended (not differential) IC symbol. Double-
clicking adds the pin name to the top-most blank From or To cell.
o Click a cell in the From or To column and select a pin from the list.
Restriction: Virtual pins are not available from the lists in the spreadsheet cells, see
Virtual Pins.

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Dialog Boxes
Define Constraint Template Dialog Box - Net Scheduling Tab

Related Topics
Define Constraint Template Dialog Box
Exporting Constraint Templates from LineSim

1538 BoardSim User Guide, v8.2

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 Dialog Boxes
Define Constraint Template Dialog Box - Pin Sets Tab

Define Constraint Template Dialog Box - Pin Sets Tab

To access: Open the Define Constraint Template Dialog Box and select the Pin Sets tab
Use the Pin Sets tab to view pin sets and modify the type property for pin sets. If a schematic
does not have any pin sets, the Pin Sets tab is empty.
To have a pin set, you need to have a "virtual pin", which is a point where three or more
transmission lines come together. See Virtual Pins.

Figure 32-54. Virtual Pin Example

Figure 32-55. Define Constraint Template Dialog Box - Pin Sets Tab

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Dialog Boxes
Define Constraint Template Dialog Box - Pin Sets Tab

Table 32-43. Define Constraint Templates Dialog Box - Pin Sets Tab Contents
Field Description
Name The name of the pin set that displays is the name of that virtual
pin.

Tip: To change the name of the pin set, Right-click a virtual pin
and select Edit Virtual Pin Name.
Type • Balanced — The distance between the virtual pin and all pins
in the pin set must be equal.
• Unbalanced — CES does not perform automatic balancing.
This is useful when you want to specify unequal constraints on
branches of the pin set.
Pins Contains the list of pins that comprise the pin set, which are the
pins at the other end of the transmission lines. This can contain
device pins and other virtual pins.

Related Topics
Define Constraint Template Dialog Box
Exporting Constraint Templates from LineSim

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February 2012
 Dialog Boxes
Differential Pair Net Suffixes Dialog Box

Differential Pair Net Suffixes Dialog Box

To access: From the HyperLynx shell (with no board or schematic loaded), select Setup >
Differential Pairs
Use this dialog box to help BoardSim automatically identify differential pairs by using net name
suffixes. For example, to pair nets clk_p and clk_n, specify the suffix pair _p and _n.
Caution
Differential pairs identified by IBIS IC models and parallel terminators have higher
priority than differential pairs identified in this dialog box. Adding or removing
differential pairs using this dialog box has no effect on differential pairs created by IBIS
IC models and parallel terminators.

Requirement: Both nets in a differential pair must connect to at least one pair of pins on the
same reference designator.
The HyperLynx initialization file BSW.INI stores settings from this dialog box and applies
them to all boards. This file is located in the
C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx folder.

Figure 32-56. Differential Pair Net Suffixes Dialog Box

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Dialog Boxes
Differential Pair Net Suffixes Dialog Box

Table 32-44. Differential Pair Net Suffixes Dialog Box Contents

Option Description
Enter a suffix into each box and click Add.

Do not use wildcard characters, such as * and ?.

Alphabetic characters are case insensitive. For example, _P is

the same as _p.
Add Enter a suffix into each box and click Add.
Remove Select a suffix pair from the list and click Remove.
Remove All --
Build differential pairs when Select to use net name suffixes to automatically identify
loading differential pairs when you load a board, by using the net name
suffix pairing in this dialog box.

Related Topics
“Transferring HyperLynx Settings”
“Differential Pairs Dialog Box” on page 1543

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 Dialog Boxes
Differential Pairs Dialog Box

Differential Pairs Dialog Box

To access: Load a board into BoardSim, select Setup > Differential Pairs
Use this dialog box to help BoardSim automatically identify differential pairs by using net name
suffixes. For example, to pair nets clk_p and clk_n, specify the suffix pair _p and _n. You can
also use this dialog box to review and temporarily edit the list of differential pairs.
Caution
Differential pairs identified by IBIS IC models and parallel terminators have higher
priority (precedence) than differential pairs identified in this dialog box. Adding or
removing differential pairs using this dialog box has no effect on differential pairs created
by IBIS IC models and parallel terminators.

Requirement: Both nets in a differential pair must connect to at least one pair of pins on the
same reference designator.
The HyperLynx initialization file BSW.INI stores the suffix settings from this dialog box and
applies them to all boards. This file is located in the
C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx folder.
Note
Manual assignments in the Differential pairs area are not saved. Changes you make are
not restored the next time you load the board.

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Dialog Boxes
Differential Pairs Dialog Box

Figure 32-57. Differential Pairs Dialog Box

Table 32-45. Differential Pairs Dialog Box Contents

Option Description
Differential pair net suffixes Area
Enter a suffix into each box and click Add.

Alphabetic characters are case insensitive. For example, _P is

the same as _p.
Remove Select a suffix pair from the list and click Remove.
Remove All --

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 Dialog Boxes
Differential Pairs Dialog Box

Table 32-45. Differential Pairs Dialog Box Contents (cont.)

Option Description
Build differential pairs Select to use net name suffixes to automatically identify
when loading differential pairs when you load a board, by using the net name
suffix pairing in this dialog box.
Differential pairs Area
Nets Displays all the single-ended nets on the board.

When a multiple-board project is loaded in BoardSim, the net

names include the board ID (such as B00). See “About Board
IDs”.
>> Select two nets from the Nets list and click >> to add them as a
differential pair in the Differential pairs list.

Restriction: Manual assignments are not saved. Changes you

make are not restored the next time you load the board.
<< Select a differential pair from the Differential pairs list and
click << to add them to the Nets list.

Restriction: Manual assignments are not saved. Changes you

make are not restored the next time you load the board.
Rebuild All Click to erase the current list of differential pairs from the
Differential pairs list and re-identify the differential pairs on
the board.

You might want to do this when you enable Build differential

pairs when loading, add or remove suffix pairs, and want to see
an updated list of differential pairs.
Differential pairs Displays all the differential pairs on the board. Resize the
dialog box to see long net names.

Note: The list does not display differential pairs formed by

differential IBIS model assignments or by parallel terminators.

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Dialog Boxes
Differential Pairs Dialog Box

Table 32-45. Differential Pairs Dialog Box Contents (cont.)

Option Description
Display specific nets by specifying a combination of net name
characters and wildcard characters.

Filtering is not case sensitive.

Use the asterisk * wildcard to match any number of characters.

Use the question mark ? wildcard to match any one character.

For example, to display all net names starting with X, type x*.

The list refreshes automatically as you type the filter

characters.

Related Topics
“Transferring HyperLynx Settings”
“Differential Pair Net Suffixes Dialog Box” on page 1541

1546 BoardSim User Guide, v8.2

February 2012
 Edit AC Power Pin Model Dialog Box

Edit AC Power Pin Model Dialog Box

To access: Open the Assign Power Integrity Models Dialog Box - IC Tab > select a pin > from
the AC Model area click Assign
Use this dialog box to specify the electrical characteristics and stimulus waveform of the current
source model assigned to the IC power-supply pin. AC models typically represent I/O buffer
switching and IC core-logic power on/off transitions. Contact the IC vendor to obtain IC power-
supply current waveforms or signatures.

Figure 33-1. Edit AC Power Pin Model Dialog Box

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Edit AC Power Pin Model Dialog Box

Table 33-1 on page 1548 and Table 33-2 on page 1548 define the fields in the dialog box, in
alphabetical order. The availability of specific fields depends on the signal type and other values
you choose.

Table 33-1. Edit AC Power Pin Model Dialog Box - Current Source Area
Contents
Field Description
Capacitance --
Resistance --

Table 33-2. Edit AC Power Pin Model Dialog Box - Stimulus Area Contents
Field Description
Amplitude Maximum current, in amperes.

For double triangle signals, you can specify a unique

amplitude value for each pulse.
Delay 1-2 Available only when Signal Type is Pulse and Shape is
Double Triangle.

Time from the start of the first pulse to the start of the
second pulse, in ns.
Fall Time The time from the start of the falling edge to end of the
falling edge.

For double triangle signals, you can specify a unique fall

time value for each pulse.
Initial Delay Time from time zero when the current waveform is
applied.
Initial Phase Phase offset for sinusoidal pulses (Shape is set to
Sinusoidal), in degrees.

Figure 31-46 on page 1382 shows a zero-degree initial

phase, where the timing offset increases slowly to reach
the maximum positive timing offset, decreases slowly to
reach the maximum negative timing offset, and so on.

Figure 31-47 on page 1383 shows a ninety-degree initial

phase, where the timing offset slowly decreases to reach
the maximum negative timing offset, and then slowly
increases to reach the maximum positive timing offset.

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 Edit AC Power Pin Model Dialog Box

Table 33-2. Edit AC Power Pin Model Dialog Box - Stimulus Area Contents
Field Description
Max Freq Maximum frequency of the signal spectrum, in MHz, for a
Gaussian pulse shape. To calculate the signal spectrum
you use third-party software to apply the Fourier
transformation to a function describing the pulse shape.
Period Enable the Period check box to repeat the stimulus for the
time you specify in the Period box.

This is a required value for sinusoidal waveshapes.

The plane noise simulation time has precedence over the

period length in the AC model. For example, if the AC
model contains a repeating current waveform that extends
beyond the simulation time, the current waveform is
truncated. Use the stop value in the HyperLynx PI
PowerScope Dialog Box to set the simulation time.
Pulse Time The pulse width, from the start of the rising edge to the
end of the falling edge.
Rise Time The time from the start of the rising edge to end of the
rising edge.

For double triangle waveforms, you can specify a unique

rise time value for each pulse.
Shape Waveform for pulse signal types.
• Triangle—Represent large-scale IC structures, such as
an I/O bus or large block of core logic, that switch on
and off at the same time.
• Double Triangle—Represent large-scale IC structures,
such as an I/O bus and large block of core logic, that
switch on and off at two different times (that is, out of
phase) and with different amplitudes.
• Trapezoid—Same as the triangle shape with a delay
added between the rising and falling edges. The high
and low levels are DC loads.
• Sinusoidal—Evaluate how a specific frequency is
filtered by decoupling capacitors. This is probably an
“experiment only” shape because any real stimulus
would be wideband, that is, contains lots of frequency
content.
• Gaussian—Similar function as the triangle waveform,
but with a Gaussian shape. This shape may be more
realistic than the triangle shape because it “rounds off”
the higher frequencies, due to filtering effect of the
package that connects the PCB to the silicon.

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Edit AC Power Pin Model Dialog Box

Table 33-2. Edit AC Power Pin Model Dialog Box - Stimulus Area Contents
Field Description
Signal Type Choose between a rising edge waveform and a variety of
pulse waveforms.

Related Topics
“Assign Power Integrity Models Dialog Box - IC Tab” on page 1456

“Adding Symbols to Power Distribution Networks” - LineSim

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 Edit DC Power Pin Model Dialog Box

Edit DC Power Pin Model Dialog Box

To access: Open the Assign Power Integrity Models Dialog Box - IC Tab and from the DC Sink
Model area click Assign
Use the Edit DC Power Pin Model dialog box to specify the electrical characteristics of the
current sink model assigned to the IC power-supply pin. DC models represent static loads, such
as IC power-supply pins connected only to non-switching circuitry.
In BoardSim, you assign DC models to power-supply pins by selecting one or more spreadsheet
rows in the Assign Power Integrity Models Dialog Box - IC Tab.
In LineSim, you assign DC models to an individual IC power-supply pin with the Edit DC
Power Pin Model Dialog Box.
For information about determining values for DC sink models, see “Obtaining DC Current
Properties for ICs” on page 342.

Figure 33-2. Edit DC Power Pin Model Dialog Box

Table 33-3. Edit DC Power Pin Model Dialog Box Contents

Field Description
Apply Current to • Each Sink—Each DC model receives the value
specified in the Current box.
• Whole Group—Each DC model receives (value
specified in the Current box)/(number of selected
power-supply pins). For example, (5 A)/(10) = 0.5 A
per DC model.
Current --
Resistance --

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Edit DC Power Pin Model Dialog Box

Related Topics
“Assign Power Integrity Models Dialog Box - IC Tab” on page 1456

“Adding Symbols to Power-Distribution Networks” - LineSim

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 Dialog Boxes
Edit Reference Designator Mappings Dialog Box

Edit Reference Designator Mappings Dialog Box

To access: Setup > Options > Reference Designator Mappings
Dialog Boxes

Use this dialog box to edit, add, delete, and restore default reference-designator mappings.
Reference-designator mappings are global and apply to all designs.
You should change mappings before loading the schematic/board because LineSim/BoardSim
examines the devices in the schematic/board file as it loads the design. Therefore, if you make
changes to reference-designator mappings after a design is loaded, you must re-load the design
fore the changes to take effect.

Figure 33-3. Edit Reference Designator Mappings Dialog Box

Table 33-4. Edit Reference Designator Mappings Dialog Box Contents

Field Description
Mappings list Lists available mappings. Select a mapping to edit or remove it from the
list.

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Dialog Boxes
Edit Reference Designator Mappings Dialog Box

Table 33-4. Edit Reference Designator Mappings Dialog Box Contents (cont.)
Field Description
Ref. prefix Type the new reference-designator prefix that you want to map and
select the type of symbol to apply the mapping to. The following
symbols are available:
• IC
• Resistor / resistor pack
• Capacitor / capacitor pack
• Inductor
• Ferrite bead
• Connector
• Test Point
Add/ Apply Adds a new reference-designator mapping to the mapping list or apply
changes to an existing reference designator mapping.

The order in which the reference-designator mappings appear in the

Mappings list is significant, see Usage Notes below for details.
Delete Removes the mapping that is selected in the mappings list.
Defaults Restores the default reference designator mappings.

LineSim/BoardSim has a set of default mappings for reference-

designator prefixes that it uses to identify the component types of
devices in the schematic/board. If your (or your company's) rules for
reference designators match LineSim/BoardSim's defaults, you do not
need to change the mappings at all.
Usage Notes
The order in which the reference-designator mappings appear in the Mappings list is significant.
When LineSim/BoardSim examines a device's reference designator, it searches for a prefix
match starting with the mappings at the top of the list, and moving toward the bottom, until the
first match is found.
Note that when you add mappings, two-character mappings appear above single-character,
three-character above two-character, etc. This ensures that a mapping like "RP" will be found
even if there is also a mapping for "R". For example, if LineSim/BoardSim searched on
reference designator "RP31" and reached mapping "R" first, an inferior match might occur.
Within each group of equal character size, the search ordering is alphabetical.
Related Topics
Reference-Designator Mapping - LineSim
About Reference-Designator Mapping - BoardSim

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 Dialog Boxes
Edit Transmission Line Dialog Box - Add/Move to Coupling Region Tab

Edit Transmission Line Dialog Box - Add/Move to Coupling

Region Tab
To access: Open the Edit Transmission Line Dialog Box - Transmission-Line Type Tab and
select Coupled Stackup from the Transmission-line type area.
Restriction: This tab is available only when modeling coupled transmission lines.
Use the Add to Coupling Region tab of the Edit Transmission Line dialog box to assign a
transmission line to a new or existing coupling region.
Use the Move to Coupling Region tab of the Edit Transmission Line dialog box to assign a
transmission line to a different coupling region.
If you use the free-form schematic editor, you can select multiple uncoupled transmission lines
at the same time and add them to a coupling region. Alternatively, you can assign individual
uncoupled transmission lines to a coupling region using either schematic editor.

Figure 33-4. Edit Transmission Line Dialog Box - Add/Move to Coupling Region
Tab

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Dialog Boxes
Edit Transmission Line Dialog Box - Add/Move to Coupling Region Tab

Table 33-5. Edit Transmission Line Dialog Box - Add/Move to Coupling

Region Tab Contents
Field Description
Coupling regions A coupling region defines how two or more conductors, usually PCB
traces, are coupled together electromagnetically. Such a region exists
when the conductors lie near each other for some length, and the result
is usually some amount of crosstalk between the conductors.

Coupling regions are inherently two dimensional in that they have a

fixed cross section over their entire length. They are defined in terms of
a PCB stackup cross section that includes the following information:
• The width of each conductor
• The position of each conductor relative to other conductors:
• Which stackup layer is used to implement the conductor
• Horizontal separation of conductors on the same layer
• Vertical and horizontal separation of conductors on different
layers
The coupling region is then assigned a length, which specifies the
distance over which the conductors are coupled in the way described in
the cross section.

While the goal of a coupling region is to define electromagnetic

coupling, you define a coupling region in geometric terms. The field
solver automatically converts this geometric data into electromagnetic
data that can be used to predict crosstalk voltages and currents.

See also: “About the Field Solver in LineSim” on page 1200, Adding
Coupling to LineSim Schematics, Coupling Regions and Coupling
Dots

Related Topics
Adding Transmission Lines to Free-Form Schematics
Adding Transmission Lines to Cell-Based Schematics
Adding Coupling to LineSim Schematics

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 Dialog Boxes
Edit Transmission Line Dialog Box - Cables Tab

Edit Transmission Line Dialog Box - Cables Tab

To access: Open the Edit Transmission Line Dialog Box - Transmission-Line Type Tab and
select Cable from the Transmission-line type area.
Use this tab to assign properties to a cable transmission line.
LineSim provides the electrical properties for several industry-standard cable types, mainly
coaxial cables. You can assign these properties to a transmission line.

Tip: If a model is not available for the cable used in your design, you can create a simple
transmission line model to represent the cable. See Modeling Cables With the Simple
Transmission-Line Models.

Figure 33-5. Edit Transmission Line Dialog Box - Cables Tab

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Dialog Boxes
Edit Transmission Line Dialog Box - Cables Tab

Table 33-6. Edit Transmission Line Dialog Box - Cables Tab Contents
Field Description
Cables Select the type of cable.

If a model is not available for the cable used in your design, you can create
a simple transmission line model to represent the cable. See Modeling
Cables With the Simple Transmission-Line Models.
Cable length The length of the transmission line.

Modeling Cables With the Simple Transmission-Line Models

If LineSim does not provide electrical properties for the cable you use, you can use the simple
transmission line model instead.
Procedure
1. Learn the following cable properties:
• Inductance per unit length, L
• Capacitance per unit length, C
• Total length, length
Inductance and capacitance per unit length are parameters that are available from the
cable manufacturer, and usually printed in the data sheet for the cable.
For multiple conductor cables, the parameters typically depend on the grounding
configuration used in the cable, that is, whether ground returns are located on every
other wire, every third wire, and so on. Be sure to account for the grounding scheme
used by the cable.
2. Calculate the characteristic impedance (Z0) and propagation delay for the cable from the
following formulas:
Z0 = sqrt(L/C)
delay = length * sqrt(LC)

3. Open the Edit Transmission Line Dialog Box - Transmission-Line Type Tab.
4. Set the Transmission-line type to Uncoupled - Simple.
5. Assign transmission line properties.
Related Topics
Adding Transmission Lines to Free-Form Schematics
Adding Transmission Lines to Cell-Based Schematics

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 Dialog Boxes
Edit Transmission Line Dialog Box - Connectors Tab

Edit Transmission Line Dialog Box - Connectors Tab

To access: Open the Edit Transmission Line Dialog Box - Transmission-Line Type Tab and
select Connector from the Transmission-line type area.
Use this tab to assign properties for connectors.
A good first-order model for a connector is a transmission line with a characteristic impedance
and propagation delay that match the effective impedance and delay of the connector.
LineSim can read characteristic impedance and propagation delay data from an ASCII format
called SLM (single line model) and apply the data to a transmission line in the schematic. The
SLM model format is based on SPICE and is used by Tyco Electronics Corporation to provide
single line models for many of its connectors. HyperLynx ships with a large set of SLM models
created by Tyco Electronics Corporation.

Figure 33-6. Edit Transmission Line Dialog Box - Connectors Tab

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Dialog Boxes
Edit Transmission Line Dialog Box - Connectors Tab

Table 33-7. Edit Transmission Line Dialog Box - Connectors Tab Contents
Field Description
Connectors Select the SLM connector.

Each SLM library file represents a single connector. Multiple models

in the file then represent different portions of the connector, for
example, different rows, each of which may have a different
impedance. For a description and example of the SLM format, see
“SLM File Specification” on page 1334.

Connector models very often assume that the connector is used with a
particular grounding scheme because the location of ground pins in
the connector is essentially what determines the impedance and delay
for other pins. Be sure to read information in the source text of any
particular model related to grounding schemes, to avoid using a
model that does not represent your application of the connector.

The AMP models are provided for customer use with certain
disclaimers. To view this information, click About File in the Select
View area.
Pin models Select the pin model.
Select view • .SLM file —
• About file —

Modeling Connectors as Custom SLM Models or Simple

Transmission Lines
To model a connector that is not included in the AMP SLM model set, create a custom SLM file
or create a simple-type transmission line to represent the connector. In either case, you must
learn the following the electrical properties for the connector:
• Characteristic impedance
• Propagation delay
• DC resistance
You might get the electrical properties, for example, from a data sheet or from an application
engineer working for the connector vendor.
Once you know the electrical properties, do any of the following:
• Model the connector using a simple-type transmission line model, where you provide
the electrical data directly.
See also: Edit Transmission Line Dialog Box - Transmission-Line Type Tab

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 Dialog Boxes
Edit Transmission Line Dialog Box - Connectors Tab

• Model the connector using a custom SLM model. To create a custom SLM model, see
the example file and formatting specification in “SLM File Specification” on page 1334.
Add the custom SLM model to a current models folder, such as LIBS. Custom SLM
models appear at the bottom of the Connectors list on the Connectors tab on the Edit
Transmission Line dialog box.

Caution
The AMP-generated SLM models are indexed with an undocumented format in a file
called AMP.TXT in the LIBS folder, which you are strongly discouraged from
modifying. Your models, since they are not in the index, will appear in the Connector list
simply as file names, at the bottom of the list.

Related Topics
Adding Transmission Lines to Free-Form Schematics
Adding Transmission Lines to Cell-Based Schematics
“Selecting S-Parameter and SPICE Models for Packages and Connectors”

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Dialog Boxes
Edit Transmission Line Dialog Box - Edit Coupling Regions Tab

Edit Transmission Line Dialog Box - Edit Coupling

Regions Tab
To access: Open the Edit Transmission Line Dialog Box - Transmission-Line Type Tab and
select the Edit Coupling Regions tab.
Restriction: This tab is available only when modeling coupled transmission lines.
Once you have added one or more transmission lines to a coupling region, use the Edit Coupling
Regions tab on the Edit Transmission Line dialog box to edit the geometric properties for the
coupling region cross section. For information about opening the Edit Transmission Line dialog
box and selecting a coupling region to edit, see “Edit Transmission Line Dialog Box -
Transmission-Line Type Tab” on page 1573.
For this tab, transmission lines are assumed to be PCB traces or PCB trace segments.
It is important to assign non-switching, that is, stuck, driver ICs on victim nets, because on a
real PCB victim nets do have drivers. If you omit stuck driver(s), simulated crosstalk
waveforms will look much different than if you include them. This occurs because driver ICs
are typically low impedance and will reflect, rather than absorb, crosstalk signals. In general,
you should check both the stuck-low and stuck-high cases whenever you simulate, to see which
generates more crosstalk.

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 Dialog Boxes
Edit Transmission Line Dialog Box - Edit Coupling Regions Tab

Figure 33-7. Edit Transmission Line Dialog Box - Edit Coupling Regions Tab

BoardSim User Guide, v8.2 1563

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Dialog Boxes
Edit Transmission Line Dialog Box - Edit Coupling Regions Tab

Figure 33-8. Example Coupling Region Tree List

Table 33-8. Edit Transmission Line Dialog Box - Edit Coupling Regions Tab
Contents
Field Description
Coupling regions The Coupling Regions area displays in a tree view and a graphic
display, the contents of the coupling regions you create, see
Figure 33-8. You can select the transmission line whose coupling
region properties you want to edit in both the tree view and graphic
display areas.

The tree view contains the coupling region name, the stackup layers
in the coupling region, and the transmission lines (if any) in the
stackup layer. The top transmission line in the tree view corresponds
to the left transmission line in the graphic view. Expand or collapse
the tree view, if needed, to see the contents of the coupling region
you want to examine.

Transmission lines are named as TL<name><comment>. <name> is

in the form xx:yy for the cell-based schematic editor and ## for the
free-form schematic editor. For xx:yy, xx is the schematic cell
coordinate of the transmission line left or top end and yy is the
coordinate of the transmission line right or bottom end. ## is a
somewhat random integer. <comment> is an optional comment that
you add to the transmission line in the Comment field in the Edit
Transmission Line Dialog Box - Transmission-Line Type Tab.

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 Dialog Boxes
Edit Transmission Line Dialog Box - Edit Coupling Regions Tab

Table 33-8. Edit Transmission Line Dialog Box - Edit Coupling Regions Tab
Contents (cont.)
Field Description
Move trace Use the arrows to move the selected transmission line left or right of
other traces that share the transmission line layer or to move the
transmission line up or down to another layer.

Results:
• The selected transmission line swaps position with the adjacent
transmission line in the direction you specified.
• When a trace is moved left or right, its trace separations move
with it, so that its new neighboring transmission lines are
properly separated from it. The neighboring transmission lines
shift position, as needed, to accommodate the moved
transmission line separations.
See also: Trace-to-trace separation, Trace-to-plane separation
Auto zoom --
Coupling region Area
Name Name of the coupling region.

The coupling region name is used in the field solver numerical report
file.

See also: “Generating a Report of the Field Solver’s Numerical

Results” on page 1212
Edit Stackup Opens the Stackup Editor. Use this to verify and make changes to the
stackup that you want to base your coupling region on.

See “Creating and Editing Stackups” on page 353.

Length Recall that a coupling region essentially consists of a cross section
plus the length which specifies over what distance the cross section
applies. When you specify the length of a coupling region, all of the
transmission lines in the coupling region become that length. For
example, if there are three transmission lines in a coupling region
and you set the coupling region length to three inches, all three of the
transmission lines and their associated traces become three inches
long.
Transmission line Area

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Edit Transmission Line Dialog Box - Edit Coupling Regions Tab

Table 33-8. Edit Transmission Line Dialog Box - Edit Coupling Regions Tab
Contents (cont.)
Field Description
X position Use to move all the traces on a layer together left or right by an "X
position" amount. This capability is useful when you want to shift all
the traces on one layer left or right relative to the traces on another
layer, such as when you have differential routing with broadside
coupling.

In the Coupling Regions graphical display, the X position is

displayed both as a value and as a gray vertical line, with a somewhat
arbitrary value of zero.

For an example, see Figure 33-9.

Restriction: This field is available only when transmission lines

exist on another layer.
Trace width The width of the trace selected in the Coupling Regions list or
graphical display, see Figure 33-8.
Layer Moves the selected transmission line to the selected layer.

The list of possible layers is determined by the current stackup. Nets

exported from MultiBoard projects create stackup layers with names
ending with “_B<number>” to indicate the board number, such as
TOP_B00.

Result: If you move a transmission line to a destination layer already

containing transmission lines, the existing transmission lines on the
destination layer will make room while preserving the X position of
the moved transmission line. Also, if the transmission line had
separated transmission lines on the original layer, the separated
transmission lines will move together to fill the void left by the
moved transmission line.

See also: How Transmission Lines are Positioned on a Destination

Layer

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Edit Transmission Line Dialog Box - Edit Coupling Regions Tab

Table 33-8. Edit Transmission Line Dialog Box - Edit Coupling Regions Tab
Contents (cont.)
Field Description
Trace-to-trace The distance from the edge of the selected trace to the edge of other
separation traces, using separate left and right trace-to-trace separation values.
Specifying the distance between traces by separation values is
typically easier than calculating the equivalent center-to-center
distances, and helps you to quickly construct coupling regions. See
below for an example of how this is measured.

For example, if the original transmission line in the coupling region

has left and right separations of 6 mils, then if other transmission
lines are added to the coupling region and placed on the same layer
on both sides of the original transmission line, the original
transmission line will automatically be separated from the others by
6 mils, edge-to-edge.

If the transmission line is located on a stackup plane layer rather than

a signal layer, and is bordered on either side by plane copper rather
than other traces, LineSim uses the trace-to-plane separation
parameters instead.

Restriction: The Left field is unavailable if no transmission line

exists to the left of the selected transmission line. Similarly, the
Right field is unavailable if no transmission line exists to the right of
the selected transmission line.

You can change the default trace-to-trace separation from the

Preferences Dialog Box - LineSim Tab.

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Edit Transmission Line Dialog Box - Edit Coupling Regions Tab

Table 33-8. Edit Transmission Line Dialog Box - Edit Coupling Regions Tab
Contents (cont.)
Field Description
Trace-to-plane The distance from the edge of the selected transmission line to the
separation edge of the plane copper, using separate left and right trace-to-plane
separation values. You might happen to move a transmission line to a
plane layer as you move it from layer to layer in a coupling region.

For example, if a transmission line is moved to a plane layer and has

left and right plane separations of 8 mils, LineSim will separate the
transmission line from plane copper by 8 mils, measured from the
edge of the trace to the edge of the plane.

Restriction: The Left field is unavailable if no transmission line

exists to the left of the selected transmission line. Similarly, the
Right field is unavailable if no transmission line exists to the right of
the selected transmission line.

You can change the default trace-to-trace separation from the

Preferences Dialog Box - LineSim Tab.
Impedance Area
Auto calc Select this check box to automatically calculate the impedance for
the transmission line any time you change any parameter that affects
the electrical data.

Clear this check box to manually update the impedance using the
Calculate button. You might do this when working with large
problems, to save time.

LineSim converts the geometric data you enter on the Edit Coupling
Regions tab into electrical data by running a field solver. A summary
of the field solver calculations is displayed in the Impedance area.
The data includes diagonal impedance values and, for two-trace
coupling regions, the differential impedance.

The field solver actually calculates far more data than is visible in the
Impedance area in the Edit Coupling Regions dialog box. You can
see a detailed report of the field solver calculations, including
recommended terminations, capacitance/inductance/characteristic-
impedance matrices, propagation speeds, and so on, see Field Solver
and Edit Transmission Line Dialog Box - Field Solver Tab.

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Edit Transmission Line Dialog Box - Edit Coupling Regions Tab

Table 33-8. Edit Transmission Line Dialog Box - Edit Coupling Regions Tab
Contents (cont.)
Field Description
Calculate This button is unavailable when the Auto Calc check box is selected.

If you clear the Auto Calc check box, the Calculate button becomes
available when the data in the Impedance area are not up to date,
such as when you change a transmission line geometry and question
marks appear in the Impedance column of the Impedance table.

The field solver actually calculates far more data than is visible in the
Impedance area in the Edit Coupling Regions dialog box. You can
see a detailed report of the field solver calculations, including
recommended terminations, capacitance/inductance/characteristic-
impedance matrices, propagation speeds, and so on, see Field Solver
and Edit Transmission Line Dialog Box - Field Solver Tab.

Usage Notes
Figure 33-9 illustrates a case where the traces on the lower signal layer have been shifted to the
right, so that they are aligned in a staggered way relative to the traces on the upper signal layer.

Figure 33-9. Moving All Traces on the Lower Signal Layer to the Right

Related Topics
Adding Transmission Lines to Free-Form Schematics
Adding Transmission Lines to Cell-Based Schematics
Adding Coupling to LineSim Schematics

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Edit Transmission Line Dialog Box - Loss Tab

Edit Transmission Line Dialog Box - Loss Tab

To access: Select Enable Lossy Simulation > open the Edit Transmission Line Dialog
Box - Transmission-Line Type Tab > select the Loss tab
Use this tab to view the resistance or attenuation frequency range for the selected transmission
line. This tab is available for the following types of transmission lines:
• Stackup
• Coupled Stackup
• Microstrip
• Buried Microstrip
• Stripline
• Wire Over Ground

Figure 33-10. Edit Transmission Line Dialog Box - Loss Tab

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Edit Transmission Line Dialog Box - Loss Tab

Table 33-9. Edit Transmission Line Dialog Box - Loss Tab Contents
Field Description
Show Area
Resistance Select to view resistance information for the transmission
line.
Attenuation Select to view signal attenuation information for the
transmission line. The blue curve represents the combined
resistive and dielectric attenuation.
• Resistive Select to view the resistive component of the signal
attenuation.
• Dielectric Select to view the dielectric component of the signal
attenuation.
Surf. Roughness Select to include the effects of conductor surface roughness
in loss calculations.

See also: “Surface Roughness Dialog Box” on page 1871

Per unit length Clear the Per Unit Length check box to display the resistance
or attenuation for the full transmission line length.
Select the Per Unit Length check box to display the resistance
or attenuation on a per-unit basis. This information can be
helpful if the net/trace must meet a specified per-unit value.
Frequency range Area
Min --
Max --
Log scale for X axis Select to display data on a logarithmic scale.
Log scale for Y axis Select to display data on a logarithmic scale.

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Edit Transmission Line Dialog Box - Loss Tab

Table 33-9. Edit Transmission Line Dialog Box - Loss Tab Contents (cont.)
Field Description
Propagation mode Select the propagation mode for which you want to see field
lines. The list is unavailable when the selected transmission
*Available only for line is not coupled to another transmission line. The list
coupled contains one of the following sets of items:
transmission lines • If the selected transmission line is coupled to one other
transmission line, this list contains Differential(+-) and
Common(++) items, where + and - are the voltage
polarity of the stimulus applied to the coupled
transmission lines. For example Differential(+-) indicates
that the field solver stimulates the coupled transmission
lines with opposite polarity signals.
• If the selected transmission line is coupled to two or more
other transmission lines, this list contains #(<polarity
list>) items. # is the mode number. <polarity list> is the
stimulus applied to the coupled transmission lines.
<polarity list> values can be +, -, or 0, where + and - are
signal voltage polarity and 0 is no signal. For example if
there are three coupled transmission lines, the
Propagation Mode list may contain 1(+-+), 2(+++), and
3(-+-).
See also:
Choosing a Propagation Mode to Plot
Propagation Modes-Single-Dielectric versus Layered-
Dielectric Traces
Dielectric loss Displays the frequency at which dielectric attenuation crosses
dominates at resistive attenuation and therefore begins to dominate.

Note: Available only if you select the Resistive and

Dielectric check boxes under the Attenuation radio button.

Related Topics
Adding Transmission Lines to Free-Form Schematics
Adding Transmission Lines to Cell-Based Schematics

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Edit Transmission Line Dialog Box - Transmission-Line Type Tab

Edit Transmission Line Dialog Box - Transmission-Line

Type Tab
To access:
• Free-form schematic editor — Double-click transmission line or right-click transmission
line and select Edit Type and Values.
• Cell-based schematic editor — Right-click the transmission line.
Requirement: The LineSim GHZ license is required to simulate S-parameter or SPICE models.
Description
Use this tab to specify properties for transmission lines used to model PCB trace segments,
connectors, cables, wires, and so on. You can use any combination of transmission line model
types in the schematic.
The explicit modeling of transmission lines is a key difference between LineSim and BoardSim.
In BoardSim, transmission-line modeling is automatic, because the PCB routing and stackup
determine the transmission line properties. However LineSim is intended to be a pre-route or
"what if" tool, and it makes no assumptions about the PCB routing.
The information you know about the PCB net you want to simulate can help you choose the
appropriate transmission line model. Direct electrical modeling of a transmission line is the
fastest modeling method, if you know the electrical properties to use. However many times you
may know what the connection looks like geometrically, but not what the geometry implies
electrically. In these cases, LineSim can automatically convert your geometric parameters to
electrical parameters.
In some cases, S-parameter or passive SPICE models are used to represent connector behavior.

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Edit Transmission Line Dialog Box - Transmission-Line Type Tab

Figure 33-11. Edit Transmission Line Dialog Box - Transmission-Line Type Tab

Table 33-10. Edit Transmission Line Dialog Box - Transmission-Line Type Tab
Contents
Field Description
Transmission-line type Area
Uncoupled (single line)

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Edit Transmission Line Dialog Box - Transmission-Line Type Tab

Table 33-10. Edit Transmission Line Dialog Box - Transmission-Line Type Tab
Contents (cont.)
Field Description
• Simple (electrical) Use when the transmission line characteristic impedance and
propagation delay are known.

You will run hypothetical experiments with the simulator.

Examples:
• How long can this transmission line be before we are in
trouble?
• How low of an impedance can this IC drive?
• You are building controlled-impedance PCBs, for example
every trace on your board is 50 ohms.
• Stackup (uncoupled) Before selecting this option, verify the stackup on which you
want to base your modeling is correct. See “Editing Stackups in
LineSim”.

Use when the PCB cross section geometry is known and you
want to link the transmission line to a global stackup. When
you edit the stackup in the stackup editor, LineSim
automatically updates the properties for all the stackup type
transmission lines.

The schematic represents a circuit that exists entirely on one

PCB, or on several PCBs that all have the same stackup. This
model type enables you to place each transmission line on a
layer in the stackup so you can modify all of the stackup-style
lines simultaneously by making global changes in the stackup
editor.

If the schematic represents a circuit that exists on multiple

PCBs that have different stackups, you can model only one of
the stackups with the stackup method. Choose the board with
the most transmission lines as the one to model with the
stackup model and then model the transmission lines on the
other boards with other methods, such as individual cross
sections (microstrip, buried microstrip, and stripline).

Note: Selecting this option selects and enables the Values tab,
see Values Tab - Uncoupled Stackup Transmission Lines.

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Edit Transmission Line Dialog Box - Transmission-Line Type Tab

Table 33-10. Edit Transmission Line Dialog Box - Transmission-Line Type Tab
Contents (cont.)
Field Description
• Microstrip Use when the PCB cross section geometry is known and the
transmission line is implemented as Microstrip—The
conductor is on an outer-layer trace, bound on one side by air
and on the other by dielectric.

Note: Selecting this option selects and enables the Values tab,
see Values Tab - Cross Section and Wire Over Ground
Transmission Lines.
• Buried Microstrip Use when the PCB cross section geometry is known and the
transmission line is implemented as Buried Microstrip—The
conductor is on an inner-layer trace, but with an AC ground
plane to only one side. For example, on a six-layer board with
planes at layers 3 and 4, layers 2 and 5 are buried microstrips.

Note: Selecting this option selects and enables the Values tab,
see Values Tab - Cross Section and Wire Over Ground
Transmission Lines.
• Stripline Use when the PCB cross section geometry is known and the
transmission line is implemented as Stripline—The conductor
is on an inner layer trace, with an AC ground plane to both
sides. For example, on a six-layer board with planes at layers 2
and 5, layers 3 and 4 are striplines.

Note: Selecting this option selects and enables the Values tab,
see Values Tab - Cross Section and Wire Over Ground
Transmission Lines.
• Wire Over Ground Use when the wire and wire-to-AC-ground geometries for the
transmission line are known.

Requirement: The wire must have a circular cross section.

Note: Selecting this option selects and enables the Values tab,
see Values Tab - Cross Section and Wire Over Ground
Transmission Lines.
• Cable Use when the transmission line is implemented as an industry-
standard cable. HyperLynx ships with the electrical properties
for a set of cables, mostly coaxial.

If a model is not available for the cable used in your design,

you can create a simple transmission line model to represent
the cable. See Modeling Cables With the Simple Transmission-
Line Models.

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Edit Transmission Line Dialog Box - Transmission-Line Type Tab

Table 33-10. Edit Transmission Line Dialog Box - Transmission-Line Type Tab
Contents (cont.)
Field Description
• Connector Use when the transmission line is implemented as an industry-
standard connector and a first-order model is sufficient.
HyperLynx is installed with a Tyco/Amp connector library.

You can also create your own connector model, using the SLM
modeling format.

See also: “SLM File Specification” on page 1334

Coupled (Stackup) Same conditions as for the Stackup (uncoupled) model type,
except that you want to electrically couple the transmission line
to one or more other transmission lines.

Requirement: The Crosstalk license is required to use coupled

stackup transmission lines.

See also: Adding Coupling to LineSim Schematics

• Coupling Direction Select the location of the coupling dot for the transmission line.

To distinguish one end of a coupled transmission line from the

other end, a coupled transmission line displays a small round
coupling dot on one end. LineSim considers the dotted ends of
the transmission lines in a coupling region to be
electromagnetically coupled.

See also: Coupling Regions and Coupling Dots

Hints --
Transmission-line properties Area - Use this area to label transmission lines and to
define electrical properties for Simple transmission-lines.
ZO Characteristic impedance of Simple transmission line.

Z0 = sqrt(L/C)

Result: If you type a new value and click into another box,
LineSim calculates and displays the new inductance and
capacitance.

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Edit Transmission Line Dialog Box - Transmission-Line Type Tab

Table 33-10. Edit Transmission Line Dialog Box - Transmission-Line Type Tab
Contents (cont.)
Field Description
Delay Propagation delay of Simple transmission line.

delay = length * sqrt(LC)

Result: If you type a new value and click into another box,
LineSim calculates and displays the new inductance and
capacitance.
R Result: If you type a new value and click into another box,
LineSim calculates and displays the new inductance and
capacitance.
Comment Adds a label to the transmission line. You can use this to
document the circuit you are drawing.
Transmission line to paste Area
Copy Use this to copy the properties of the transmission line to
another transmission line. This method is an alternative to
copying the transmission line symbol with the correct
properties, deleting the transmission line symbol with the
incorrect properties, and pasting another copy of the
transmission line symbol with the correct properties.
Paste Use this to paste properties from a copied transmission line to
the current transmission line.

Related Topics
Editing Schematic Symbol Properties
“Selecting S-Parameter and SPICE Models for Packages and Connectors”
Adding Transmission Lines to Free-Form Schematics
Adding Transmission Lines to Cell-Based Schematics
Adding Coupling to LineSim Schematics

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 Dialog Boxes
Edit Transmission Line Dialog Box - Values Tab

Edit Transmission Line Dialog Box - Values Tab

To access: Open the Edit Transmission Line Dialog Box - Transmission-Line Type Tab and
select one of the following from the Transmission-line type area:
• Stackup, see Values Tab - Uncoupled Stackup Transmission Lines
• Microstrip, see Values Tab - Cross Section and Wire Over Ground Transmission Lines
• Buried Microstrip, see Values Tab - Cross Section and Wire Over Ground Transmission
Lines
• Stripline, see Values Tab - Cross Section and Wire Over Ground Transmission Lines
• Wire Over Ground, see Values Tab - Cross Section and Wire Over Ground
Transmission Lines
Use this tab to define transmission line properties. The contents of this tab change depending on
the type of transmission line selected on the Edit Transmission Line Dialog Box -
Transmission-Line Type Tab.

Tip: You can change the measurements units used in the Edit Transmission Line dialog
box used for dimensions and metal thickness. See “Setting Measurement Units” on
page 401.

Electrical Properties
LineSim automatically calculates some or all of the electrical properties for transmission lines
based on the geometric properties you set.

Table 33-11. Electrical Properties for Cross-Section Models

Property Means
Impedance (Z0) The characteristic impedance of a trace, cable, or wire.
Delay The propagation delay from one end of the trace, cable, or
wire to the other.
Inductance (L) The total inductance of a trace, cable, or wire.
Capacitance (C) The total capacitance of a trace, cable, or wire.
Resistance (R) The total DC resistance of a trace or wire, assuming
copper and 20 degrees Celsius.

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Values Tab - Uncoupled Stackup Transmission Lines

Values Tab - Uncoupled Stackup Transmission Lines

The schematic represents a circuit that exists entirely on one PCB, or on several PCBs that all
have the same stackup. This model type enables you to place each transmission line on a layer
in the stackup so you can modify all of the stackup-style lines simultaneously by making global
changes in the stackup editor.
If the schematic represents a circuit that exists on multiple PCBs that have different stackups,
you can model only one of the stackups with the stackup method. Choose the board with the
most transmission lines as the one to model with the stackup model and then model the
transmission lines on the other boards with other methods, such as individual cross sections
(microstrip, buried microstrip, and stripline).

Tip: Before modeling uncoupled stackup transmission lines, verify that your stackup is
correct, see “Creating and Editing Stackups” on page 353.

Figure 33-12. Values Tab - Uncoupled Stackup Transmission Lines

Table 33-12. Values Tab Contents for Uncoupled Stackup Transmission Lines
Field Description
Layer Select the stackup layer to which you want to assign the transmission line.

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 Dialog Boxes
Values Tab - Uncoupled Stackup Transmission Lines

Table 33-12. Values Tab Contents for Uncoupled Stackup Transmission Lines
Field Description
Length Enter the length of the transmission line.

If you type a new value and click into another field, LineSim calculates and
displays the new electrical properties.

See also: “Values Tab Contents for Cross Section Transmission Lines” on
page 1583
Width Enter the width of the transmission line.

If you type a new value and click into another field, LineSim calculates and
displays the new electrical properties.

See also: “Values Tab Contents for Cross Section Transmission Lines” on
page 1583

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Dialog Boxes
Values Tab - Cross Section and Wire Over Ground Transmission Lines

Values Tab - Cross Section and Wire Over Ground Transmission

Lines
Use this tab to define transmission line properties for microstrip, buried microstrip, and stripline
transmission lines.
The geometric properties that you can enter in the Edit Transmission Line dialog box vary
somewhat from section type to section type. Some properties apply to all cross sections while
others do not. For example, Plating Thickness is available only for microstrips.

Tip: When you type a new value and click into another field, LineSim calculates and
displays the new electrical properties.

Figure 33-13. Values Tab - Cross Section and Wire Over Ground Transmission
Lines

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 Dialog Boxes
Values Tab - Cross Section and Wire Over Ground Transmission Lines

Table 33-13. Values Tab Contents for Cross Section Transmission Lines
Field Description
Length (L) The length of a trace, cable, or wire used to calculate line delay and total L, C,
and R.
Plating The amount of copper plating used over an outer-layer trace. 1 ounce is a
Thickness common value.
(P)
Restriction: This option is available only for microstrip transmission lines.
Conductor The amount of base copper used to make a trace. 0.5 ounce is a common
Thickness value.
(T)
Restriction: This option is available only for microstrip, buried microstrip,
and stripline transmission lines.
Width (W) The total cross-sectional width of a trace, resulting from base and plated
copper. This value cannot be determined directly from the copper weights
because it depends on the etching process used.

Restriction: This option is available only for microstrip, buried microstrip,

and stripline transmission lines.
Radius (R) The radius of a circular wire.

Restriction: This option is available only for wire over ground transmission
lines.
Dielectric The height or thickness of the dielectric between a trace or wire and AC-
Height (H) ground, or reference, plane.
Dielectric The constant describing the dielectric properties of the circuit-board or other
Constant insulating material.
(Er)
Loss tangent --
(Lt)
Advanced Click to specify the following advanced impedance options:
• Bulk resistivity
• Temperature coef

Related Topics
Adding Transmission Lines to Free-Form Schematics
Adding Transmission Lines to Cell-Based Schematics

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Dialog Boxes
eDxD/eExp View

eDxD/eExp View
To access: From BoardSim, select File > Run eDxD/eExp View
You can view layout designs stored in .CCE (CADCAM Professional, encrypted and
compressed) format in eDxD/eExp View or the BoardSim board viewer. eDxD/eExp View has
the following advantages over the board viewer:
• Displays artwork layers and manufacturing data not supported by the BoardSim .HYP
file format
• Displays very large layouts in a viewer that is faster than the board viewer
You can create these files by exporting a design from Mentor Graphics Expedition PCB or
CAMCAD Professional.
For information about zooming and panning, see “Zooming and Panning” on page 1586.
BoardSim can directly load .CCE files. See “Opening BoardSim Boards”.
Restriction: eDxD/eExp View is unavailable when running the 64-bit version of HyperLynx.
On Windows, use the 32-bit version of HyperLynx (which is also installed when you install the
64 bit version) to open CAMCAD files. Select Start > All Programs > Mentor Graphics SDD >
HyperLynx <release> 32-bit > HyperLynx Simulation Software. By contrast, Linux
installations are 64-bit only or 32-bit only.

Prerequisites
To enable selecting nets in eDxD/eExp View for simulation in BoardSim, load the .HYP file for
the design into BoardSim and load the .CCE file for the same design into eDxD/eExp View.

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 Dialog Boxes
eDxD/eExp View

Figure 33-14. eDxD/eExp View

Table 33-14. eDxD/eExp View Contents

Option Description
File menu
Open Open a .CCE file exported from Expedition PCB or CAMCAD
Professional.
Select menu
Net for BoardSim Opens the Select Net for BoardSim Analysis dialog box. The
Simulation filter box supports wildcard characters. Use the asterisk *
wildcard to match any number of characters. Use the question
mark ? wildcard to match any one character.
Displays the board X/Y origin and lines representing the X and Y
axes.

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eDxD/eExp View

Table 33-14. eDxD/eExp View Contents (cont.)

Option Description
Fits the full board in the window. Does not show any objects that
might lie outside the boundary of the board.

Fits all objects in the window. Use this option when the layout
contain objects that lie outside the boundary of the board.

Zoom the view to the selected objects.

Show the previous view.

Show the next view.

Opens the Display Control dialog box from which you can control
the visibility of objects in eDxD/eExp View.

The dialog box has the following three tabs:

• Layers— Toggle the visibility of layout layers. You can
change the color of the layers by double-clicking the color
column for the layer to change.
• Graphics Classes—Toggle the visibility of the layout graphics
classes.
• Insert Types—Toggle the visibility of the layout insert types.

Zooming and Panning

Table 33-15 shows how to use the mouse to zoom and pan.

eDxD/eExp View and Expedition PCB have the same zoom and pan behaviors.
Table 33-15. Zoom and Pan Commands for eDxD/eExp View
Operation Button Mouse Action
Zoom in Middle Click or scroll wheel (roll forward)
Zoom out Middle Shift+<click> or scroll wheel (roll backward)
Zoom in area Middle or Right Shift+<press and drag> left to right
Zoom out area Middle or Right Shift+<press and drag> right to left
Pan Middle <press and drag>

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 Dialog Boxes
eDxD/eExp View

Related Topics
“Viewing BoardSim Boards”

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Dialog Boxes
Export to HyperLynx 3D EM Dialog Box

Export to HyperLynx 3D EM Dialog Box

To access: From BoardSim, select Export > HyperLynx 3D EM Topology
Use this dialog box to specify the region and objects in the BoardSim board to export to a .CCE
(CADCAM encrypted) file. Use HyperLynx 3D EM to run 3-D electromagnetic simulation on
the exported topology and create an S-parameter model.
To reduce 3-D electromagnetic simulation run time, consider exporting only the minimum
amount of data required to simulate the topology of interest. This dialog box provides many
ways to specify only the region, layers, nets, and objects that you need to simulate in
HyperLynx 3D EM Designer.
Requirements:

• The 3D Area Model Export license is required to export topologies from BoardSim.
• The IE3DAGIF license is required to open the exported topology in the HyperLynx 3D
EM solver.
Restrictions:
• This feature is available only when running 32-bit software. On Windows 64-bit
installations, the 32-bit software is also installed and available from the Start menu in
the HyperLynx <release> 32-bit folder. By contrast, Linux installations are 64-bit only
or 32-bit only.
• The “Mentor CCZ to HyperLynx 3D EM Flow” in HyperLynx 3D EM Designer is
unavailable on computers running Linux. Open the exported .CCE file on a Windows
32-bit computer.

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 Dialog Boxes
Export to HyperLynx 3D EM Dialog Box

Figure 33-15. Export to HyperLynx 3D EM Dialog Box

Table 33-16. Export to HyperLynx 3D EM Dialog Box Contents

Option Description
Export to File Specify the location and file name of the .CCE (CADCAM
encrypted and compressed) file that contains the region and
objects exported from BoardSim. Click Browse to browse to the
file.

The filename form is <board_name>_3dstruct.cce.

The default folder is the design folder. See “About Design

Folder Locations” on page 1391.
Area of Interest Area

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Export to HyperLynx 3D EM Dialog Box

Table 33-16. Export to HyperLynx 3D EM Dialog Box Contents (cont.)

Option Description
Left Specify the corners of the region to export by dragging a
Right rectangle across the board viewer or by entering coordinate
Bottom values.
Top
You can move the dialog box out of the way and use board
viewer features, such as zooming and selecting nets, to help find
the region to export. See “Summary of Board Viewer
Operations”.

Restriction: These options are unavailable if you select Whole

Board.
Whole Board Select to export the entire board area.
Exported Data Filter Area
Included Layers Select the stackup layers to export.
Include Objects Select the types of objects to export.
Available Nets Full set of nets in the board.

Filter To select nets to export, do any of the following:

• Double-click the net.
• Select the net and select .
• To export all nets, select .

To filter the Available Nets list, specify a string and click

Apply.

The Mark All and Clear All buttons operate only on the nets
displayed in the list. For example, if you enter a filter string of
*gnd*, click Apply, and then click Mark All, nets not in the list
(such as DQS2) are not selected.

The filter box supports wildcard characters. Use the asterisk *

wildcard to match any number of characters. Use the question
mark ? wildcard to match any one character.

The filter box is case insensitive; Q is treated the same as q.

Included Nets Set of nets to include in the exported .CCE file.

To remote nets from the export, do any of the following:

• Double-click the net.
• Select the net and select .
• To remove all nets, select .

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Export to HyperLynx 3D EM Dialog Box

Table 33-16. Export to HyperLynx 3D EM Dialog Box Contents (cont.)

Option Description
Open in HyperLynx 3D EM Opens the Mentor CCE to HyperLynx 3D EM Flow dialog box,
solver after export which you use to set up the geometries to simulate and start the
process to create an S-parameter model.

Restrictions:
• This option is unavailable on computers running Linux.
• This option is unavailable if the IE3DAGIF license is
unavailable.
Export Select to export the board to a .CCE file.

Related Topics
“Exporting BoardSim Topologies to HyperLynx 3D EM Designer” on page 1165

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FastEye Channel Analyzer - Add Jitter Page

FastEye Channel Analyzer - Add Jitter Page

To access: Select SI Simulation > Run FastEye Channel Analysis and select the Add Jitter
page
Use this page to add jitter to the input stimulus. FastEye channel analysis supports Gaussian,
sine, and uniform jitter distributions. For definitions, see “Jitter Distribution Types” on
page 1379. You can enable multiple jitter distributions at the same time. If you enable multiple
jitter distributions, the total jitter probability distribution function (PDF) is a convolution of the
individual jitter distributions. See “Usage Notes” on page 1595.
If you are not sure what jitter distribution to use, enable only Gaussian and obtain the combined
driver and receiver jitter values (in sigma) from IC datasheets, design kit documentation, and so
on. See “Jitter Applications” on page 1386. You may have your own reasoning on how to
combine driver and receiver jitter values, by treating them statistically independent or not.
Note
Jitter increases FastEye channel analysis run time. When planning to run very long bit
sequences or many stimulus repetitions, you might first run analysis without jitter to see
how closed the eye already is.

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FastEye Channel Analyzer - Add Jitter Page

Figure 33-16. FastEye Channel Analyzer - Add Jitter Page

Table 33-17. FastEye Channel Analyzer - Add Jitter Page Contents

Option Description
Generate the same random number Enable this option to make the analysis results
sequence for each simulation repeatable. This option may be helpful if you make
termination or topology changes and want to use exactly
Restriction: This option is available the same jitter to compare results, or if you want to
only for Gaussian and uniform jitter. correlate your results with another person.
Sine jitter is always repeatable.
Add Gaussian jitter Apply random jitter to the stimulus. See “Gaussian
Jitter” on page 1379.

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FastEye Channel Analyzer - Add Jitter Page

Table 33-17. FastEye Channel Analyzer - Add Jitter Page Contents (cont.)
Option Description
• Standard Deviation—magnitude Specify jitter width (or magnitude) at one standard
deviation (that is, one sigma). Increasing the value of
sigma increases (on average) the deviation of the timing
of waveform transitions away from the ideal switching
time. You specify the width of one sigma and FastEye
channel analysis derives the width of other sigmas from
it. The sigmas are equally spaced from one another.

If you want the maximum jitter value (on average) to

exceed three sigma, the bit sequence must contain at least
370 bits. This value is based on reference information
about the Gaussian distribution and its relationship to the
confidence interval. See Table 31-29 on page 1381.
• Standard Deviation—units Specify jitter units as an absolute (for example, in
nanoseconds) or as a relative value (for example, a
fraction of the unit interval set for the simulation). See
“Units for Gaussian and Uniform Jitter” on page 1386.
• Frequency—value and units Jitter frequency is the rate at which the jitter offset varies
from bit to bit. Median frequency is the frequency that
divides the jitter spread into two parts of equal area.

Note: This is an advanced setting. Use the default

advanced setting values, unless you have a reason to
change them.
Add uniform jitter Apply uniform jitter to the stimulus, See “Uniform Jitter”
on page 1383.
• Magnitude—value The magnitude represents one half the overall width of
the distribution. See Figure 31-49 and Figure 31-50.
• Magnitude—units Specify jitter units as an absolute (for example, in
nanoseconds) or as a relative value (for example, a
fraction of the unit interval set for the simulation). See
“Units for Gaussian and Uniform Jitter” on page 1386.
• Mean—value and units The mean represents the center of the possible jitter value
range. A non-zero mean value offsets the center of the
distribution away from the ideal switching time.

Note: This is an advanced setting. Use the default values,

unless you have a reason to change them.
Add sine jitter Apply deterministic sinusoidal jitter to the stimulus. See
“Sinusoidal Deterministic Jitter” on page 1382.

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FastEye Channel Analyzer - Add Jitter Page

Table 33-17. FastEye Channel Analyzer - Add Jitter Page Contents (cont.)
Option Description
• Magnitude—value and units The magnitude represents one half the overall width of
the distribution. See Figure 31-48 on page 1383.
• Initial phase Initial phase of the sinusoidal jitter in degrees. You can
usually set this value to zero degrees. You might specify
a non-zero initial phase value for “short” simulations that
are not long enough to contain many periods of slowly-
changing jitter. Sinusoidal jitter usually shifts slowly
relative to the bit rate.

See Figure 31-46 on page 1382 and Figure 31-47 on

page 1383.

Note: This is an advanced setting. Use the default values,

unless you have a reason to change them.
• Frequency—value and units Jitter frequency is the rate at which the jitter offset varies.

Note: This is an advanced setting. Use the default values,

unless you have a reason to change them.

Usage Notes
Although FastEye channel analysis is based on the analog channel characterization measured at
the receiver input pin, the goal is to find the BER or eye diagram at the receiver decision point
(which is beyond its amplifiers, DFE, filters, and CDR circuitry). Because drivers and receivers
are active devices, they both contribute random jitter due to thermal and transistor device noise,
PLL (that is, CDR circuitry) behavior, and so on. This is why you should specify a jitter
distribution representing both driver and receiver jitter.
Do not specify the jitter produced by the following effects, unless you have a specific reason to
do so:
• PCB layout effects—Such as impedance mismatches and signal dispersion
• Data-dependent effects—Such as ISI, duty-cycle distortion, pseudo-random bit
sequence periodicity

Related Topics
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page

FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page

To access: Select SI Simulation > Run FastEye Channel Analysis and select the Add Pre-
Emphasis/DFE page
Use this page to do the following:
• Add pre-emphasis to step response and pulse response waveforms used as inputs to
FastEye channel analysis.
• Add decision-feedback equalization (DFE) to FastEye results.
• Identify optimum values for pre-emphasis and DFE taps to create the best-possible eye
opening.
In many SERDES channels, the IC driver contains circuitry that performs pre-emphasis and the
IC receiver contains circuitry that performs equalization (usually DFE). These digital-signal
processing (DSP) technologies modify transmitted and received waveforms to compensate for
channel distortions, such as high-frequency losses. See “Pre-Emphasis and DFE Structures” on
page 1599.
If the channel driver/receiver implements pre-emphasis/DFE, enabling the FastEye channel
analysis options on this wizard page can help avoid pessimism by applying the same eye-
opening methods during analysis that are used in system operation.
Caution
If you provide external characterization waveforms that include the effects of pre-
emphasis, do not duplicate that pre-emphasis here.

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FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page

Figure 33-17. FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page

Table 33-18. FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page

Contents
Option Description
Pre-emphasis Area

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FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page

Table 33-18. FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page

Contents (cont.)
Option Description
Add driver pre-emphasis Add pre-emphasis to the step response and pulse response
waveforms.
Restriction: If you enable pre-
emphasis synthesis, you cannot Enable this option if the IC model supports pre-emphasis
enable DFE. behavior, but pre-emphasis is disabled when producing the
waveforms. This condition is true whether the wizard
automatically creates the waveforms or you provide external
waveforms.

Disable this option if any of the following conditions are true:

• The IC model does not support pre-emphasis behavior.
• The IC model supports pre-emphasis behavior and it was
enabled when producing the waveforms. Because the
waveforms already contain pre-emphasis, disabling this
option avoids adding it again. This condition is true
whether the wizard automatically creates the waveforms
or you provide external waveforms.
• The IC model does support pre-emphasis and you want to
learn how much pre-emphasis opens the eye by
temporarily disabling it during FastEye channel analysis.
• Specify taps/weights Manually specify taps and tap weights by enabling this option
and clicking Details. Use this option to see how effective the
current tap weights are.
• Synthesize optimal values Automatically identify optimal tap weights.

Restriction: FastEye Use this option to see tap weight values that open the eye the
channel analysis cannot most. These values may be used to program the IC
optimize the tap weight driver/receiver tap values.
values for pre-emphasis
when you manually specify
DFE tap weights.
• Details If you enabled Specify taps/weights, opens the Specify Pre-
Emphasis Dialog Box.

If you enabled Synthesize optimal values, opens the

Synthesize Pre-Emphasis Dialog Box.
Decision feedback equalization Area

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FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page

Table 33-18. FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page

Contents (cont.)
Option Description
Add DFE Add decision-feedback equalization to the received analysis
waveform.

Disable this option if the receiver IC does not support DFE.

By contrast, if the receiver IC does support DFE, you can
learn how much DFE opens the eye by temporarily disabling
it during FastEye channel analysis.
• Specify taps/weights Manually specify taps and tap weights by enabling this option
and clicking Details. Use this option to see how effective the
current tap weights are.
• Synthesize optimal values Automatically identify optimal tap weights.

Use this option to see tap weight values that open the eye the
most. These values may be used to program the IC
driver/receiver tap values.
• Details If you enabled Specify taps/weights, opens the Specify DFE
Dialog Box.

If you enabled Synthesize optimal values, opens the

Synthesize DFE Dialog Box.

Pre-Emphasis and DFE Structures

To use this optional feature, you must know the details of how pre-emphasis/DFE is
implemented in the driver/receiver, such as the number of taps and their weights. Many PCB
designers will not know this information and some IC vendors consider this information to be
proprietary and do not distribute it. However, IC I/O designers will know this information and
some IC vendors publish driver/receiver datasheets with this information.
FastEye channel analysis makes the following assumptions:
• Driver/receiver ICs implement pre-emphasis/DFE circuits commonly used by SERDES
designs. Driver/receiver ICs implement linear pre-emphasis and non-linear DFE that
contains clamping.
• Crosstalk is not taken into account.
• Noise is taken into account, if you specify jitter properties to represent it. See “FastEye
Channel Analyzer - Add Jitter Page” on page 1592.

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FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page

Map Tap Weights to Pre-Emphasis and DFE Structures

FastEye channel analysis assumes that drivers/receivers implement circuitry for pre-
emphasis/DFE that resemble the structures in Figure 33-18 on page 1600 and Figure 33-19 on
page 1600. FastEye channel analysis supports a large number of pre-taps (pre-emphasis only)
and post-taps, not just the number of taps displayed in Figure 33-18 and Figure 33-19.

Figure 33-18. FastEye Pre-Emphasis Filter - Feed-Forward

Table 33-19. FastEye Pre-Emphasis Filter - Feed-Forward

Symbol Description
T Delay element with duration of one bit interval
K-2, K-1 Pre-taps
K Main tap
K1, K2, K3 Post-taps
+ Addition operator

Figure 33-19. FastEye DFE Filter - Feed-Backward

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FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page

Table 33-20. FastEye DFE Filter - Feed-Backward Contents

Symbol Description
— Subtraction operator
Decision point or slicer. Converts an arbitrary waveform into
a two-level waveform, for example, Y(t) = F(x(t)). If x > x0,
then Y = 1, else Y = -1. FastEye analysis assumes the
threshold is zero (centered waveforms) and the gain of the
decision point is 1.
T Delay element with duration of one bit interval
K Main tap
K1, K2 Post-taps. This filter does not use pre-taps.
+ Addition operator

Identifying Optimum Tap Weights

If you do not already know the best tap weights for the channel, FastEye analysis can
automatically identify them for you.

Procedure
1. In the IC model, set all the tap weights to zero.
2. If you provide external step- and pulse-response waveforms, generate them prior to
running FastEye channel analysis and specify them in the Channel Characterization
Dialog Box.
3. On the FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page, enable both
Synthesize optimal values options.
4. Set other wizard options as needed, run FastEye channel analysis, and see if the FastEye
diagram, BER, and other measurements indicate acceptable results.
5. In the IC model, set the tap weights to the synthesized values.

Related Topics
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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FastEye Channel Analyzer - Choose Fitting/Convolution Page

FastEye Channel Analyzer - Choose Fitting/Convolution

Page
To access: Select SI Simulation > Run FastEye Channel Analysis and select the Choose
Fitting/Convolution page
Use this page to select the analysis method used by FastEye channel analysis engine.

Figure 33-20. FastEye Channel Analyzer - Choose Fitting/Convolution Page

Table 33-21. FastEye Channel Analyzer - Choose Fitting/Convolution Page

Contents
Option Description
Complex-pole fitting Table 33-22 on page 1603 compares the strengths of each analysis
method.
Convolution
Additional advantages exist for complex-pole fitting. See “Model
Channel Frequency Response with Complex-Pole Models” on
page 644

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FastEye Channel Analyzer - Choose Fitting/Convolution Page

Table 33-22. Comparing the Strengths of Complex-Pole Fitting and Convolu-

tion
Wide Spectrum Narrow Spectrum or Few Reso-
nance Peaks
Long Response Both may be slow Complex-pole fitting is faster

For example, a long cable with low For example, channels with just a
loss and strong reflections. few narrow resonances may have
very long response times (take a
long time for transient residuals to
die out).
Short Response Convolution is faster Both may be fast

For example, channels producing

short and sharp-edged pulse
response, which can be character-
ized by low loss, but no reflections
and high-Q resonances.

Related Topics
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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Dialog Boxes
FastEye Channel Analyzer - Choose New/Saved Analysis Page

FastEye Channel Analyzer - Choose New/Saved Analysis

Page
To access: Select SI Simulation > Run FastEye Channel Analysis and select the Choose
New/Saved Analysis page
Use this page to start an all-new FastEye channel analysis or to load settings saved from a
previous FastEye channel analysis.
The FastEye Channel Analyzer wizard saves its settings to the .FEW (FastEye wizard) file,
which is located in the design folder unless you specify another location. See “About Design
Folder Locations” on page 1391.

Requirements
• The FastEye / AMI Support license is required to run FastEye channel analysis.
• The BoardSim PI Only or LineSim PI Only license cannot be checked out when you run
IBIS-AMI channel analysis.

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FastEye Channel Analyzer - Choose New/Saved Analysis Page

Figure 33-21. FastEye Channel Analyzer - Choose New/Saved Analysis Page

Table 33-23. FastEye Channel Analyzer - Choose New/Saved Analysis Page

Contents
Option Description
New Select to start a new analysis using default wizard settings.

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FastEye Channel Analyzer - Choose New/Saved Analysis Page

Table 33-23. FastEye Channel Analyzer - Choose New/Saved Analysis Page

Contents (cont.)
Option Description
Use last configuration Select to load settings from memory.

Wizard settings are stored in memory until you close HyperLynx.

Loading settings from memory may be useful when analyzing
similar structures, such as different instances of a channel.
Load saved configuration Select and click Load to browse to a wizard settings file (.FEW).

Loading previously saved settings may useful when analyzing

similar structures, such as different instances of a channel, or to
reproduce previous analysis results. After loading the saved
settings, you can edit and save them to another file.
Load Click to browse to a wizard settings file (.FEW).
Save-on-exit options Area
Save settings to file Select and click Browse to save wizard settings to a new or
existing file. You can also type the file location in the box.

Selecting this option causes the button labels Save & Run and
Save & Exit to display near the bottom of the wizard page.
Deselecting this option causes the button labels Run and Exit to
display.
Browse Click to browse to a wizard settings file (.FEW).

Related Topics
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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FastEye Channel Analyzer - Define Stimulus Page

FastEye Channel Analyzer - Define Stimulus Page

To access: Select SI Simulation > Run FastEye Channel Analysis and select the Define
Stimulus page
Use this page to specify the stimulus to apply to the channel during FastEye channel analysis.

Figure 33-22. FastEye Channel Analyzer - Define Stimulus Page - Worst Case

Figure 33-23. FastEye Channel Analyzer - Define Stimulus Page - PRBS

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FastEye Channel Analyzer - Define Stimulus Page

Figure 33-24. FastEye Channel Analyzer - Define Stimulus Page - 8B/10B

Figure 33-25. FastEye Channel Analyzer - Define Stimulus Page - Custom

Table 33-24. FastEye Channel Analyzer - Define Stimulus Page Contents

Option Description
Bit pattern Area

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FastEye Channel Analyzer - Define Stimulus Page

Table 33-24. FastEye Channel Analyzer - Define Stimulus Page Contents (cont.)
Option Description
Type Select any of the following types of bit patterns:
• Worst-case PRBS—The sequence of pseudorandom bits that close
the eye the most.
• Worst-case 8B/10B—The sequence of characters that close the eye
the most.
• PRBS—Pseudorandom binary sequence.
• 8B/10B—Randomly-generated characters that obey the signaling
protocol.
• Custom—Bit sequences that you define or load from a bit stimulus
(.BIT) file. See “Setting Up Custom Bit Patterns” on page 548.
# of 10 bit Specify how many 10-bit characters the bit sequence will contain.
Characters
Restriction: This option is available only for the 8B/10B stimulus type.
Bit Order Select the bit order to determine the number of bits in the sequence. The
number of bits is 2bit order - 1. For example, if the bit order is 6, the
number of bits is 63 (that is, 26 - 1).

Restriction: This option is available only for the PRBS stimulus type.
Checks per UI Select the number of points per UI for which the worst-case bit
sequence is determined. See “Checks Per UI” on page 1610.

This value cannot exceed the Samples per bit interval value in the
FastEye Channel Analyzer - View Analysis Results Page. This check
makes sure the overall analysis can show the details found when
determining the worst-case bit stimulus.

Restriction: This option is available only for the Worst-case PRBS and
Worst-case 8B/10B stimulus types.
Load Load an existing bit stimulus file or create a new bit pattern. See
“Setting Up Custom Bit Patterns” on page 548. The file location is
displayed near the bottom of the Bit pattern area.

Restriction: This option is available only for the Custom stimulus type.
Save Save the bit pattern to a .BIT file. The FastEye Channel Analyzer
wizard saves the bit pattern file to the design folder unless you specify
another location. See “About Design Folder Locations” on page 1391.

Restriction: This option is available only for the Custom stimulus type.
Stimulus length Area

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FastEye Channel Analyzer - Define Stimulus Page

Table 33-24. FastEye Channel Analyzer - Define Stimulus Page Contents (cont.)
Option Description
Bit interval Specify the value for the bit interval or rate.
Bit rate
When choosing between the Bit interval and Bit rate options, use the
one that provides the best accuracy. For example, to test the channel at
333 Mbps, you can specify a bit rate of 0.333 Gbps instead of a bit
interval of 3.00300300300 ns. Editing the Bit Interval value updates the
Bit Rate value, and vice versa.

The values may have been previously set by any of the following
sources, sorted in descending priority:
1. The Bit interval and Bit rate values in the Channel Characterization
Dialog Box.
2. The fitted-poles (.PLS) file used to characterize the channel and
loaded on the IBIS-AMI Channel Analyzer Wizard - Set Up
Channel Characterizations Page. The .PLS file contains a comment
that specifies the bit interval.
3. The Bit interval and Bit rate values used for standard eye diagrams
and specified in the Stimulus tab of the Configure Eye Diagram
dialog box. See “Setting Up Global Stimulus for Standard-Eye
Diagrams” on page 541.
Pattern repetitions Specify the number of times to run the pattern during simulation.

Checks Per UI
If you select worst-case PRBS or worst-case 8B/10B bit patterns, the FastEye Channel Analyzer
wizard creates multiple temporary worst-case bit sequences, one for each equally-spaced
sampling location in the UI. From this set of temporary bit sequences, the wizard calculates a
final worst-case bit sequence that it uses during analysis or saves to a file.
For example, if you specify eleven sampling locations, the wizard creates eleven temporary
worst-case bit sequences, one for each equally-spaced sampling location. See Figure 33-26. It
then creates a cumulative worst-case bit sequence from the eleven temporary bit sequences.

Figure 33-26. Checks Per UI - 11 Sampling Locations

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FastEye Channel Analyzer - Define Stimulus Page

Use Checks per UI on the FastEye Channel Analyzer - Define Stimulus Page to specify the
number of sampling locations. The default value provides a reasonable balance of accuracy and
run time. You might decrease the value to reduce analysis run time when repeating the stimulus
many times, such as when testing for a bit-error rate (BER) of 1e-12.

Tip: The FastEye Channel Analyzer wizard does not apply jitter when determining
worst-case bit sequences.

Related Topics
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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FastEye Channel Analyzer - FastEye/Worst-Case Analysis Page

FastEye Channel Analyzer - FastEye/Worst-Case Analysis

Page
To access: Select SI Simulation > Run FastEye Channel Analysis and select the
FastEye/Worst-case Analysis page
Use this page to choose whether to enable all the pages in the wizard or to enable only the pages
needed to create a worst-case stimulus file. Disabled page names are displayed in red fonts in
the table of contents pane.

Figure 33-27. FastEye Channel Analyzer - FastEye/Worst-case Analysis Page

Table 33-25. FastEye Channel Analyzer - FastEye/Worst-Case Analysis Page

Contents
Option Description
Perform FastEye analysis and optionally Select to enable all the wizard pages and run
generate worst-case sequence FastEye channel analysis. You can also generate
and apply the worst-case PRBS or 8B/10B bit
pattern or apply a non-worst-case bit pattern, such
as PRBS.

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FastEye Channel Analyzer - FastEye/Worst-Case Analysis Page

Table 33-25. FastEye Channel Analyzer - FastEye/Worst-Case Analysis Page

Contents (cont.)
Option Description
Only generate worst-case sequence Select to enable only the wizard pages needed to
generate the worst-case PRBS or 8B/10B bit
pattern.

If you know the channel contains a non-linear

element (such as the driver) and suspect that
FastEye channel analysis results will be invalid,
you may want to create only the worst-case
stimulus and simulate it in the time domain with the
oscilloscope.

See “Worst-Case Bit Patterns Overview” on

page 643 and “Setting Up the Oscilloscope” on
page 537.

Related Topics
“Checking Channels for Linear and Time-Invariant Behavior” on page 642
“Worst-Case Bit Patterns Overview” on page 643
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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Dialog Boxes
FastEye Channel Analyzer - Introduction Page

FastEye Channel Analyzer - Introduction Page

To access: Select SI Simulation > Run FastEye Channel Analysis and select the
Introduction page
Use the text on this page to familiarize yourself with FastEye Channel Analyzer wizard
capabilities, inputs, and types of results.

Figure 33-28. FastEye Channel Analyzer - Introduction Page

Related Topics
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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 Dialog Boxes
FastEye Channel Analyzer - Set Up Channel Characterizations Page

FastEye Channel Analyzer - Set Up Channel

Characterizations Page
To access: Select SI Simulation > Run FastEye Channel Analysis and select the Set Up
Channel Characterizations page
Use this page to set up simulation to create a new analog channel characterization, create
optional crosstalk files, or load existing characterization or crosstalk files.
Note
Wizard settings include the channel-characterization file and probe location for a specific
LineSim schematic or BoardSim selected net. If you load settings for a different
schematic or selected net, be sure to update the Loaded and probe-related options on this
page.

Figure 33-29. FastEye Channel Analyzer - Set Up Channel Characterizations

Page

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FastEye Channel Analyzer - Set Up Channel Characterizations Page

Table 33-26. FastEye Channel Analyzer - Set Up Channel Characterizations

Page Contents
Option Description
Transmitter probe, Receiver probe Areas
Pin Differential or single-ended channel pin to probe.

If an expected differential probe does not appear, manually

create a differential probe with the oscilloscope. See
“Manually Creating Differential Probes with the
Oscilloscope” on page 1621.

You can run FastEye channel analysis for one single-ended

or differential channel at a time.
Probe locations Area
Location Probe location. See “Locating Probes at the Die or Pin” on
page 555.
Signal (victim) channel characterization Area
New/View Open the Channel Characterization Dialog Box to do either
of the following:
• Set up simulation properties for a new channel
characterization.
• View channel characterization waveforms manually
created from the Channel Characterization Dialog Box or
automatically created when you run analysis to
completion.
New Create a new channel characterization when you run channel
analysis.

Clicking New deletes from memory a previous channel

characterization.

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FastEye Channel Analyzer - Set Up Channel Characterizations Page

Table 33-26. FastEye Channel Analyzer - Set Up Channel Characterizations

Page Contents (cont.)
Option Description
Use last Use a previous channel characterization that is still in
memory.

You might use this option when using the same channel
topology and probe locations with different analysis settings.

This option is unavailable if you do any of the following:

• Change the net topology, such as editing stackup layer
properties or the probe location
• Select another net (BoardSim only)
• Click New
• Close HyperLynx

Enabling this option makes unavailable nearly all the other

options on this page.
Loaded Browse to an existing fitted-poles (.PLS) or S-parameter file
Load (.S2P, .S4P) that contains results from a previous channel
characterization. See “External Analog Channel
Characterization Files” on page 1621.

Enabling this option makes unavailable nearly all the other

options on this page.
Include crosstalk effects from Channel characterization includes the crosstalk effects from
aggressor channels nearby aggressor channels/nets.

If you do not see any aggressors in the spreadsheet, some

likely causes are:
• None of the aggressors have enabled transmitter/driver
pins
• In BoardSim, none of the aggressors exceed the crosstalk
threshold
• You have not loaded any optional external crosstalk files

Restriction: The Crosstalk license is required to run

crosstalk simulation.

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FastEye Channel Analyzer - Set Up Channel Characterizations Page

Table 33-26. FastEye Channel Analyzer - Set Up Channel Characterizations

Page Contents (cont.)
Option Description
Allow external aggressor Optionally, add crosstalk effects on the victim channel
channels receiver from a channel or net that you have characterized
outside of the wizard.

You might use this capability to use crosstalk files that

represent channel behavior measured on PCB hardware.

See “External Aggressor Channel Characterization Files” on

page 1622.
Aggressor channel driver default Area
Victim channel driver default Area
Inactive stuck state The default value to use in the spreadsheet.

See Aggressor and Victim.

Spreadsheet columns
Notes:
• The spreadsheet contains a row for each aggressor channel/net in the design with the
transmitter/driver set to output. Aggressors are characterized one at a time.
• BoardSim identifies an aggressor channel/net when it exceeds the crosstalk threshold you
set.
• LineSim identifies an aggressor channel/net when it is part of the same coupling region as
the victim channel.
• If the contents of the spreadsheet cells is not fully visible, you can either make the dialog box
larger or scroll the spreadsheet.
Enable Select to either use the channel as an aggressor to or to
receive actions from the Characterize Selected or Display
Selected buttons.

This option links to the same option on the FastEye Channel

Analyzer - Set Up Crosstalk Analysis Page.

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FastEye Channel Analyzer - Set Up Channel Characterizations Page

Table 33-26. FastEye Channel Analyzer - Set Up Channel Characterizations

Page Contents (cont.)
Option Description
Name Reference designator, pin name, and probe location for an
aggressor transmitter/driver IC pin.

The Location option determines the probe location.

Aggressor The transmitter/driver state to apply to the aggressor when it
is not being characterized. Aggressors are characterized one
a time, so if the design contains aggressors A and B,
aggressor A is set to the selected inactive state when
aggressor B is characterized.

If the value is Default, use the Inactive stuck state option

value.

For information about the role of “stuck” states in crosstalk

simulation, see “Importance of Modeling Drivers on Victim
Nets as Stuck High or Stuck Low - BoardSim”.
Victim The transmitter/driver state to apply to the victim when an
aggressor is being characterized.

If the value is Default, use the Inactive stuck state option

value.
Path Location of the file representing the crosstalk received at the
victim receiver pin and caused by a transmitter/driver
switching high or low to create a step response.

Click the cell to browse to the file.

Running analysis to completion automatically characterizes

aggressor channels internal to the design.

For external aggressor channels, you can specify SPICE

(.LIS), fitted-poles (.PLS), or Touchstone (.S2P, .S4P) files.
To delete the path to an external aggressor channel file, right-
click the cell and click Yes.

For external file requirements, see “External Aggressor

Channel Characterization Files” on page 1622.

Point to the cell with the mouse to display a ToolTip

containing the full file path.

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FastEye Channel Analyzer - Set Up Channel Characterizations Page

Table 33-26. FastEye Channel Analyzer - Set Up Channel Characterizations

Page Contents (cont.)
Option Description
Port Map Click to select a port mapping for an S-parameter file.

L and R represent ports on the left and right sides of the

simulation symbol. For example, L13R24 means that ports 1
and 3 are on the left side and ports 2 and 4 are on the right
side. See “S-Parameter Port Numbering” on page 1066.

Restriction: This cell does not display port-mapping options

when you load a fitted-poles model or .LIS file in the Path
cell because they have known port mapping.
Characterize Selected Optionally, characterize a single aggressor crosstalk channel.
Aggressor channel characterization is done automatically
when you run analysis, but you may want to do this manually
to investigate the crosstalk contribution of a specific channel.

Restriction: This button is unavailable unless you enable a

spreadsheet row.
Display Selected Optionally, after you manually characterize an aggressor
crosstalk channel, you can display it.

Restriction: This button is unavailable unless you enable a

spreadsheet row.
Characterize All Optionally, characterize all the aggressor crosstalk channels.
Aggressor channel characterization is done automatically
when you run analysis, but you may want to do this manually
to investigate the crosstalk contribution of one or more
specific channels.
+ Channel Add a new spreadsheet row to add crosstalk effects on the
victim channel receiver from a channel or net that you have
characterized outside of the wizard.

You might use this capability when running channel analysis

from a set of S-parameter files that represent channel
behavior measured on PCB hardware.

Restriction: This option is unavailable if Allow external

aggressor channel is disabled.
- Channel Remove the selected spreadsheet row for a channel or net
that you have characterized outside of the wizard.

Restriction: This option is unavailable if Allow external

aggressor channel is disabled.

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FastEye Channel Analyzer - Set Up Channel Characterizations Page

Manually Creating Differential Probes with the Oscilloscope

1. Close the FastEye Channel Analyzer wizard, saving your settings.
2. Select Simulate SI > Run Interactive Simulation. The oscilloscope opens.
3. Perform the steps in “Manually Attaching Differential Probes” on page 556.
4. Open the FastEye Channel Analyzer wizard, load your saved settings, and then resume
stepping through the wizard.
External Analog Channel Characterization Files
You may want to use external channel characterization files for any of the following reasons:

• Channel characterization simulation is slow (perhaps due to SPICE models) and you
want to use the same channel topology and probe locations with different analysis
settings.
• You prefer to analyze channels only in the frequency domain and want to use an S-
parameter file to represent the analog channel characterization.
Check that the external files meet the requirements in this topic.

Channel Characterization File Corresponds to Current Design

The channel characterization file must accurately represent the channel implementation and
transmitter/receiver analog buffer behavior. The following kinds of changes can cause the file to
not accurately represent the current channel behavior:

• Channel topology, which is the set of physical elements and geometries used to
implement the channel and includes trace segments, stackup, signal vias, and so on
• Crosstalk thresholds (BoardSim) or coupling regions (LineSim)
• Transmitter/receiver analog buffer settings
• Transmitter output/input mode for channels with more than one transmitter
External Analog Channel Characterization Files - Time Domain
You can manually save .PLS files from the Channel Characterization Dialog Box. These files
are saved to the design folder unless you specify another location. See “About Design Folder
Locations” on page 1391.

External Analog Channel Characterization Files - Frequency Domain

You can provide S-parameter models that you create with third-party software. Provide one
model to represent the channel behavior between the transmitter and receiver analog pins. If you
have a chain of S-parameter models to represent individual channel elements, cascade them into
a single S-parameter model. See “Cascading Multiple S-Parameter Models in Series” on
page 1105.

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Dialog Boxes
FastEye Channel Analyzer - Set Up Channel Characterizations Page

External Aggressor Channel Characterization Files

Provide characterization files that represent the victim receiver behavior when an aggressor
switches from low to high or high to low. If the aggressor net has two drivers, provide files for
signals being transferred in both directions.

You may want to use external aggressor channel characterization files for any of the following
reasons:

• Channel characterization simulation is slow (perhaps due to SPICE models) and you
want to use the same channel topology and probe locations with different analysis
settings.
• Your company’s channel design process prefers to analyze channels only in the
frequency domain and you use an S-parameter file to represent the aggressor channel
characterization.
Check that the external files meet the requirements in this topic.

Check the model quality before loading the file. See “Checking S-Parameter Model Quality” on
page 1082.

Aggressor Channel Characterization File Corresponds to Current Design

The aggressor channel characterization file must accurately represent the channel
implementation and transmitter/receiver analog buffer behavior. The following kinds of
changes can cause the file to not accurately represent the current channel behavior:

• Channel topology, which is the set of physical elements and geometries used to
implement the channel and includes trace segments, stackup, signal vias, and so on
• Crosstalk thresholds (BoardSim) or coupling regions (LineSim)
• Transmitter/receiver analog buffer settings
• Transmitter output/input mode for channels with more than one transmitter
External Aggressor Channel Characterization Files - Time Domain
These files contain the response of a single receiver to an aggressor making a single step from
low to high or from high to low. You can load:
• .LIS file created by SPICE or the oscilloscope. The simulation length must be at least
165 ns.
• .PLS files from other sources.
External Aggressor Channel Characterization Files - Frequency Domain
Restriction: If the channel is non-linear, you cannot use S-parameter files as aggressor
characterization files.

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FastEye Channel Analyzer - Set Up Channel Characterizations Page

These files contain the response of a single receiver to an aggressor making a single step from
low to high or from high to low. You can load:
• .S4P files created by PCB hardware measurements for a differential pair. Figure 33-30
shows the channel buffer and VNA setup for a near-end crosstalk (NEXT) measurement
for victim differential receiver RX2. Note that the VNA and channel buffers in
Figure 33-30 are not set up to measure far-end crosstalk (FEXT), but it is marked to
provide the general idea of how to do it.

Figure 33-30. PCB Measurement Set Up to Measure Crosstalk

• .S2P files created by PCB hardware measurements for a single-ended signal.

Related Topics
“Bit Sequence for Automatic Channel Characterization” on page 645
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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Dialog Boxes
FastEye Channel Analyzer - Set Up Crosstalk Analysis Page

FastEye Channel Analyzer - Set Up Crosstalk Analysis

Page
To access: Select SI Simulation > Run FastEye Channel Analysis and select the Set Up
Crosstalk Analysis page
Use this page to set up crosstalk options.
Restrictions:
• This page is unavailable unless you enable Include crosstalk effects from aggressor
channels on the FastEye Channel Analyzer - Set Up Channel Characterizations Page.
• The Crosstalk license is required to run crosstalk simulation.

Figure 33-31. FastEye Channel Analyzer - Set Up Crosstalk Analysis Page

Table 33-27. FastEye Channel Analyzer - Set Up Crosstalk Analysis Page

Contents
Option Description
Crosstalk timing Area

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FastEye Channel Analyzer - Set Up Crosstalk Analysis Page

Table 33-27. FastEye Channel Analyzer - Set Up Crosstalk Analysis Page

Contents (cont.)
Option Description
Synchronous Victim and aggressor channels are phase locked. There is a
constant phase among transitions for all aggressor and victim
channels.

This option can take into account the effects of many causes of
crosstalk, such as the mutual delays between rising/falling edges
in different channels.

Even when you select this option, note that the channel
interconnect can spread out the arrival of aggressor crosstalk on
the victim net.
Asynchronous Victim and aggressor channels are not phase locked. There is an
arbitrary phase of transitions among the aggressor and victim
channels.

This option can take into account statistically independent

sources of crosstalk.

Reports only the average crosstalk effect obtained on the final

eye diagram along the unit interval.
Analysis type Area
Time domain Select when the aggressor transmitter/output switching is non-
linear.
Statistical Select when the aggressor transmitter/output switching is linear.
Default stimulus Area—The Default value in the Stimulus column in the spreadsheet
applies values defined in this area.

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FastEye Channel Analyzer - Set Up Crosstalk Analysis Page

Table 33-27. FastEye Channel Analyzer - Set Up Crosstalk Analysis Page

Contents (cont.)
Option Description
Type Select any of the following types of bit patterns:
Parameter • Random—Random binary sequence. Unlike PRBS, a
random bit pattern can produce repeating bit sequences at
any number of bits.

Parameter represents the random seed value, which can be

either of the following:
• <random>—Use to produce random sequences that are
uncorrelated to other random sequences.
• Any positive or negative integer—Use to produce random
sequences that are correlated to other random sequences
using the same seed. You can use the same seed to apply
the same random bit pattern to multiple channels or during
a future analysis session (to reproduce results).
• 8B10B—Randomly-generated 10 bit characters that obey
the signaling protocol.

Parameter represents the random seed value, which can be

either of the following:
• <random>—Use to produce 8B10 character sequences
that are uncorrelated to other random sequences.
• Any positive or negative integer—Use to produce random
sequences that are correlated to other random sequences
using the same seed. You can use the same seed to apply
the same random 8B10B character pattern to multiple
channels or during a future analysis session (to reproduce
results).
• PRBS—Pseudorandom binary sequence that does not repeat
within the number of bits you specify in the Parameter
option.

Parameter is the bit order that determines the number of bits

in the sequence. The number of bits is 2bit order - 1. For
example, if the bit order is 6, the number of bits is 63 (that is,
26 - 1).
• Bit Sequence File—Custom bit sequences loaded from a bit
stimulus (.BIT) file. See “Setting Up Custom Bit Patterns”
on page 548.

Parameter shows the location of the loaded file.

Spreadsheet columns

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FastEye Channel Analyzer - Set Up Crosstalk Analysis Page

Table 33-27. FastEye Channel Analyzer - Set Up Crosstalk Analysis Page

Contents (cont.)
Option Description
Notes:
• The spreadsheet contains a row for each aggressor channel/net in the design with the
transmitter/driver set to output. Aggressors are characterized one at a time.
• BoardSim identifies an aggressor channel/net when it exceeds the crosstalk threshold you
set.
• LineSim identifies an aggressor channel/net when it is part of the same coupling region as
the victim channel.
• If spreadsheet cells are not visible, you can either make the dialog box larger or drag the
scroll bars.
Enable Select to use the channel as an aggressor. This option links to
the same option on the FastEye Channel Analyzer - Set Up
Channel Characterizations Page.
Name Reference designator, pin name, and probe location for an
aggressor transmitter/driver IC pin.

The Location option on the FastEye Channel Analyzer - Set Up

Channel Characterizations Page determines the probe location.
Stimulus Default applies the stimulus specified in the Default stimulus
Parameter area. There is no Parameter for the Default stimulus type.

You can specify per-channel stimulus. For information about

the stimulus types and parameters, see Type Parameter. Note
that Bit_File in the spreadsheet is the same stimulus type as Bit
Sequence File in the Default stimulus area.

Related Topics
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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Dialog Boxes
FastEye Channel Analyzer - View Analysis Results Page

FastEye Channel Analyzer - View Analysis Results Page

To access: Select SI Simulation > Run FastEye Channel Analysis and select the View
Analysis Results page
Use this page to choose the types of analysis results to create and to specify the number of
samples per bit interval. You can also use this page to view simulation results that are still in
memory or load simulation results that you have manually saved to disk.
To save displayed results to disk, use the save features available from the dialog box that
displays the results. For example, save the BER plot from the HyperLynx SI Eye Density
Viewer.

Figure 33-32. FastEye Channel Analyzer - View Analysis Results Page

Table 33-28. FastEye Channel Analyzer - View Analysis Results Page Contents
Option Description
Eye diagram Display analysis results as an eye diagram.

To save eye diagrams, use the FastEye Viewer (detailed

waveforms only) or the Windows clipboard (detailed
waveforms and contours).

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FastEye Channel Analyzer - View Analysis Results Page

Table 33-28. FastEye Channel Analyzer - View Analysis Results Page Contents
Option Description
• All traces Display detailed eye-diagram waveforms.

The wizard automatically overrides this option and displays

eye diagram contours if you run extremely long bit sequences,
when it becomes impractical to store and display waveform
traces for individual bit intervals.
• Contours only Display only filled-in inner and outer perimeters of the eye
diagram. For an example, see Figure 33-33 on page 1631.
BER plots Display eye density plots or bit error rate plots in the
HyperLynx SI Eye Density Viewer.

BER plots help identify valid data sampling locations by

reporting BER as a function of the sampling location across
the unit interval (UI, same as bit interval) and voltage. The
color of the contour indicates its BER.
Bathtub curves Display the Bathtub Chart Dialog Box. Use this dialog box to
display and document bathtub curves. Bathtub curves help
identify valid data sampling locations by reporting the bit error
rate (BER) as a function of the sampling location across the
unit interval (UI, same as bit interval) at several voltage
offsets.
Statistical contours Display the Statistical Contour Chart Dialog Box. Use this
dialog box to display a nested series of eye opening contours
and their bit error rate (BER). The color of the contour
indicates its BER. Like bathtub curves, statistical contours
indicate the quality of sampling locations across the unit
interval (UI, same as bit interval). An advantage of statistical
contours over bathtub curves is that the inner-eye contours
display both sampling time and voltage information.
Synthesized taps Display the Synthesized DFE Weights Dialog Box and
Synthesized Pre-Emphasis Weights Dialog Box when analysis
finishes. These dialog boxes display the synthesized tap
weight values and enable you to save them to files.

Restriction: This option is available when you enable tap

weight synthesis options on the FastEye Channel Analyzer -
Add Pre-Emphasis/DFE Page.

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FastEye Channel Analyzer - View Analysis Results Page

Table 33-28. FastEye Channel Analyzer - View Analysis Results Page Contents
Option Description
Save worst-case stimulus to Optionally save the bit values that close the eye the most to a
file file.

Use the FastEye Channel Analyzer - Define Stimulus Page to

specify whether the sequence is unconstrained or constrained
to support 8B/10B protocol requirements.

You can use the sequence to simulate the channel in the time
domain.
• <file_name> The default file name is of form <design>-worst-case.bit,
where <design> is the file name of the LineSim schematic or
BoardSim board.

The default file location is the <design> folder. See “About

Design Folder Locations” on page 1391.
• Browse --
Samples per bit interval Specify the number of samples per bit interval to adjust the
display resolution of eye diagram contours in the FastEye
Viewer and HyperLynx SI Eye Density Viewer.

Type a number from 16 to 32. Large numbers will slow

analysis considerably.
View Optionally, re-open an analysis results window.

Analysis windows open automatically when analysis

completes. If you close an analysis window, you can re-
display the results until you close the wizard. There is a View
button for each type of analysis output.

The bottom two buttons are unavailable until you run analysis
to completion.
Load Optionally, open previously-saved bathtub charts (*.BTD) and
statistical contour charts (*.SCD).

The default file location is the <design> folder. See “About

Design Folder Locations” on page 1391.

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FastEye Channel Analyzer - View Analysis Results Page

Figure 33-33. Example FastEye Channel Analysis Contour

Related Topics
“FastEye Diagram Measurements” on page 645
“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

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Dialog Boxes
FastEye Step and Pulse Responses Dialog Box and PRBS Waveforms Dialog Box

FastEye Step and Pulse Responses Dialog Box and PRBS

Waveforms Dialog Box
To access: From the Channel Characterization Dialog Box > click the Display Waveforms or
Display Response or Display PRBS Waveforms button
Use this dialog box to display waveforms that are used as part of channel characterization. To
zoom, pan, copy to clip, and so on, click a toolbar button or right-click over the graph.

Figure 33-34. FastEye Step and Pulse Responses Dialog Box

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FastEye Step and Pulse Responses Dialog Box and PRBS Waveforms Dialog Box

Figure 33-35. PRBS Waveforms Dialog Box

Table 33-29. FastEye Step and Pulse Responses Dialog Box and PRBS
Waveforms Dialog Box
Option Description
Print the graph with a white background, which uses less printer
ink or toner.
Print (right-click)
Zoom in by doing the following:
1. Position the mouse pointer over one corner of the zoom box
Zooming (right-click) you want to create, and then drag to define the other corner
of the zoom box.
2. Release the mouse button to magnify the contents of the
zoom box to fill the graph.
Pan by dragging the graph across the dialog box.
Panning (right-click)
Attach measurement crosshairs to a waveform by clicking the
waveform to measure.
Track Cursor (right-click)
As you move the mouse horizontally, the measurement
crosshairs tracks the selected curve.

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Dialog Boxes
FastEye Step and Pulse Responses Dialog Box and PRBS Waveforms Dialog Box

Table 33-29. FastEye Step and Pulse Responses Dialog Box and PRBS
Waveforms Dialog Box (cont.)
Option Description
Fit the entire curve to window.
Fit to window (right-click)
Display only lines between curve vertices (no vertice dots).

Display only curve vertices (no lines).

Display both lines and vertice dots.

Open Help for the dialog box.

Copy (right-click) Copy graph to the clipboard and use a white background.

This option uses less printer ink or toner if you print it out.

You can paste the image from the Windows clipboard into
another program such as Microsoft WordPad.
Copy inverted (right-click) Copy graph to the clipboard and use a black background.

You can paste the image from the Windows clipboard into
another program such as Microsoft WordPad.
Show Area - Pulse Extraction dialog box
Step response This dialog box can display either of the following types of
waveforms:
Pulse response
• step response and pulse response, which checks the channel
for linearity (FastEye channel analysis only) and is used as
the basis of complex-pole fitting. You can use these
waveforms to help choose how long to run the channel-
response simulation or to investigate unexpected analysis
results.
• Crosstalk from an aggressor channel, which contributes to
the channel characterization. You can use these waveforms
to see the crosstalk on the victim channel receiver when an
aggressor channel transmitter switches high or low.
Show Area - PRBS Waveforms dialog box

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 Dialog Boxes
FastEye Step and Pulse Responses Dialog Box and PRBS Waveforms Dialog Box

Table 33-29. FastEye Step and Pulse Responses Dialog Box and PRBS
Waveforms Dialog Box (cont.)
Option Description
Direct Waveform Display the pseudorandom bit simulus (PRBS) simulation
waveforms used as the basis of automatic pulse- and step-
Inverted Waveform response waveform extraction. You can use these waveforms to
investigate unexpected FastEye channel analysis results.

Related Topics
“Channel Characterization Dialog Box” on page 1493
“FastEye Channel Analyzer - Set Up Channel Characterizations Page” on page 1615
“IBIS-AMI Channel Analyzer Wizard - Set Up Channel Characterizations Page” on page 1742

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Dialog Boxes
Field Solver and Edit Transmission Line Dialog Box - Field Solver Tab

Field Solver and Edit Transmission Line Dialog Box - Field

Solver Tab
To access:
• LineSim Free-Form Schematic Editor — Double-click a transmission line > Edit
Transmission Line Dialog Box - Transmission-Line Type Tab > select Coupled
Stackup > Field Solver tab
• LineSim Cell-Based Schematic Editor — Right-click a transmission line > Edit
Transmission Line Dialog Box - Transmission-Line Type Tab > select Coupled
Stackup > Field Solver tab
• BoardSim — Right-click trace segment > select View Field-Solver Output
Use this dialog box to run the field solver and view electrical field lines.
When a signal travels along a conductor, it transfers energy in the form of a wave that consists
of time-changing electric and magnetic fields. The field solver predicts these fields, given a
specific cross section containing conductive traces and various dielectrics.
Sometimes it is informative to actually view the field lines calculated by the field solver.
Though the field plots provide no direct analytic value, they can give an intuitive feeling for
how various traces are coupled to each other. Sometimes, too, they are just fun to look at.
Requirement: The LineSim Crosstalk license is required to run crosstalk simulation.

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Field Solver and Edit Transmission Line Dialog Box - Field Solver Tab

Figure 33-36. Field Solver Dialog Box / Edit Transmission Line Dialog Box -
Field Solver Tab

Table 33-30. Field Solver Dialog Box / Edit Transmission Line Dialog Box -
Field Solver Tab Contents
Field Description
Field plotting Area
Start Click to calculate and display the electric field lines and electric
equipotentials.

Requirement: The LineSim/BoardSim Crosstalk license is required to

run crosstalk simulation.

See also: “How Field Lines are Plotted” on page 1209

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Field Solver and Edit Transmission Line Dialog Box - Field Solver Tab

Table 33-30. Field Solver Dialog Box / Edit Transmission Line Dialog Box -
Field Solver Tab Contents (cont.)
Field Description
Stop Click to interrupt or stop field-line plotting. The plotting stops
immediately.

The reason LineSim Crosstalk must calculate field-line positions as a post

process is that its field solver is a boundary-element solver (see “How the
Field Solver Works in LineSim” on page 1201). To find a coupling
region’s capacitance and inductance matrices, the solver needs only
calculate charge densities on conductor surfaces and dielectric
boundaries. There is no information that needs to be calculated or stored
about electric potentials in the regions between conductors and dielectric
boundaries. However, to generate the field-line plots, these potentials are
needed. They are therefore found on-the-fly by solving certain
differential equations which they must satisfy.

You can plot another propagation mode’s field lines simply by changing
the mode selection in the Propagation Mode combo box.
Propagation Select the propagation mode for which you want to see field lines.
mode
Restriction: The list is unavailable when the selected transmission line is
not coupled to another transmission line. If the list is available, it contains
one of the following sets of items:
• If the selected transmission line is coupled to one other transmission
line, the Propagation Mode list contains Differential(+-) and
Common(++) items, where "+" and "-" are the voltage polarity of the
stimulus applied to the coupled transmission lines. For example
Differential(+-) indicates the field solver stimulates the coupled
transmission lines with opposite polarity signals.
• If the selected transmission line is coupled to two or more other
transmission lines, the Propagation Mode list contains #(<polarity
list>) items. # is the mode number. <polarity list> is the stimulus
applied to the coupled transmission lines. <polarity list> values can be
"+", "-", or "0", where "+" and "-" are signal voltage polarity and "0"
is no signal. For example if there are three coupled transmission lines,
the Propagation Mode list may contain 1(+-+), 2(+++), and 3(-+-).
See also:
Choosing a Propagation Mode to Plot
• Propagation Modes-Single-Dielectric versus Layered-Dielectric
Traces
Copy to Clip Click to capture a copy of the field solver graphics to the clipboard.

The field-line plot is captured in Enhanced Metafile format, a "smart"

Windows format which can be flexibly resized (i.e., "stretched") in other
applications.

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Field Solver and Edit Transmission Line Dialog Box - Field Solver Tab

Table 33-30. Field Solver Dialog Box / Edit Transmission Line Dialog Box -
Field Solver Tab Contents (cont.)
Field Description
Auto zoom --
Graphical viewing Area
See also: “How You can identify traces in the graphical viewer by pointing to them and
Field Lines are waiting for a ToolTip containing the trace name to appear. This capability
Plotted” on helps you to correlate the traces to transmission lines in the schematic or
page 1209 nets in the board.

Exception: If you are using BoardSim or the free-form schematic editor,

the ToolTip contains the layer name.
If the traces are too small to easily locate with the pointer, try zooming in
closer by selecting the Auto Zoom check box.
Numerical results Area
View Click to view a detailed report of the field solver calculations.

See also: “Generating a Report of the Field Solver’s Numerical Results”

on page 1212

Related Topics
Adding Transmission Lines to Free-Form Schematics
Adding Transmission Lines to Cell-Based Schematics
“How the Field Solver Works in LineSim” on page 1201

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Dialog Boxes
Find Component Dialog Box

Find Component Dialog Box

To access: From BoardSim, select View > Find Component
Use this dialog box to find a component, zoom and pan to make it visible, and highlight its
location with a blinking dashed outline.

Figure 33-37. Find Component Dialog Box

Table 33-31. Find Component Dialog Box Contents

Option Description
Select Component Select a reference designator and click OK to display the component in
the board viewer.

If a MultiBoard project is loaded, the board ID is appended to the

reference designator. For example, U1_B00. See “About Board IDs”.
Filter To display specific components in the list, specify a combination of
reference designator characters and wildcard characters and click
Apply. For example, to display all IC components with the U reference
designator prefix, type u*.

Filtering is case insensitive.

The filter box supports wildcard characters. Use the asterisk * wildcard
to match any number of characters. Use the question mark ? wildcard
to match any one character.
Zoom Select <Auto> or another zoom level to adjust how much zoom the
board viewer uses to display the found component.

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 Dialog Boxes
Highlight Net Dialog Box

Highlight Net Dialog Box

To access:
• Select View > Highlight Net.
• Viewing Filter Dialog Box > Modify list button.
Use this dialog box to display nets in the BoardSim board viewer without selecting them for
interactive simulation or other forms of analysis. This feature enables you to view the routing at
full brightness for several nets at a time and to view power-supply net shapes and routing.

Figure 33-38. Highlight Net Dialog Box

Table 33-32. Highlight Net Dialog Box Contents

Option Description
List of nets The length and names of signal and power-supply nets in the design.
When you select a net in this list, the board viewer dims all the other
nets.

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Highlight Net Dialog Box

Table 33-32. Highlight Net Dialog Box Contents (cont.)

Option Description
Filter Type the filter value and click Apply. Supported wildcard characters
include the asterisk * (substitute any number of characters) and
question mark ? (substitute one character).
Design file If a MultiBoard project is open, select the board ID.
Sort nets by Click an option to sort the list of nets.
Highlight using Select the color(s) to use for net highlighting. Click one of the
following:
• Layer colors—Display each net segment with the color associated
with the stackup layer on which the net segment is located. If the
net is routed on different stackup layers, it will likely be displayed
in more than one color.
• User color and <color_shape>—Use one color for the entire net,
even if it is routed on different stackup layers. Click the color
shape to select another color.
Include associated nets Highlight associated nets. Most of the time, you probably want to
highlight associated nets.

If you highlight a net and then unroute it, the associated nets will still
be displayed even after unrouting is complete. Clear the check box to
avoid highlighting associated nets for an unrouted net.
Highlight If you select a net in the list, clicking Highlight applies the properties
in the Highlight using area to it.
Remove Highlight If you select a net in the list, clicking Remove Highlight unhighlights
it.
Remove All Click Remove All to unhighlight all nets.

Appearance of Highlighted Nets

The board viewer displays highlighted nets as long dashed lines in colors that you choose. By
contrast, selected nets appear as solid lines in colors defined in the stackup. See Figure 33-39.
BoardSim Crosstalk displays crosstalk aggressor nets as short dashed lines in colors defined in
the stackup. You can distinguish crosstalk aggressor nets from highlighted nets by the length of
the dashed lines:
• Highlighted nets have long dashes.
• Crosstalk aggressor nets have short dashes.
If a net is both highlighted for viewing and selected for analysis, the board viewer displays the
net as a selected net.

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Highlight Net Dialog Box

If a net is both highlighted for viewing and is an aggressor net, the board viewer displays the net
as an aggressor net.

Figure 33-39. Appearance of Highlighted Nets

Related Topics
“Viewing BoardSim Boards”

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Dialog Boxes
HyperLynx 3D EM Full-Wave EM Simulation Dialog Box

HyperLynx 3D EM Full-Wave EM Simulation Dialog Box

To access: From the Via Properties Dialog Box, from the 3D EM Modeling list, select
HyperLynx 3D EM Solver > Simulate
Use this dialog box to monitor simulation progress or cancel simulation. The dialog box closes
automatically when simulation completes.

Figure 33-40. HyperLynx 3D EM Full-Wave EM Simulation Dialog Box

Table 33-33. HyperLynx 3D EM Full-Wave EM Simulation Dialog Box Contents

Option Description
Cancel Stop simulation before it completes.

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 Dialog Boxes
HyperLynx 3D EM Full-Wave EM Simulation Dialog Box

Related Topics
“Via Properties Dialog Box” on page 1908

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Dialog Boxes
HyperLynx 3D EM Geometry Viewer - 3D Geometry View Dialog Box

HyperLynx 3D EM Geometry Viewer - 3D Geometry View

Dialog Box
To access: From the Via Properties Dialog Box, from the 3D EM Modeling list, select
HyperLynx 3D EM Solver > View 3D
Use this viewer to graphically display the contents of the geometry file (.GEO) that HyperLynx
3D EM uses during simulation to create the S-parameter model for the signal via. This gives
you a chance to make sure the structures and dimensions are correct before generating the
model file. The geometries can include the signal via, signal traces, metal areas and stitching
vias. See “Extracted Geometries for 3-D Electromagnetic Simulation of Signal Vias” on
page 1663.
Restrictions:
• If your design contains perforations or voids in the metal shapes next to the signal via,
they do not exist in the geometries used by 3-D electromagnetic simulation. The metal
area geometries can contain anti-pads for the signal via and stitching vias.
• This topic describes only the 3D Geometry View dialog box. While the parent
HyperLynx 3D EM Geometry Viewer has a Views menu and toolbar that enables you to
display other windows, this topic does not describe them.

Figure 33-41. HyperLynx 3D EM Geometry Viewer - 3D Geometry View Dialog

Box

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 Dialog Boxes
HyperLynx 3D EM Geometry Viewer - 3D Geometry View Dialog Box

Table 33-34. HyperLynx 3D EM Geometry Viewer - 3D Geometry View Dialog

Box Contents
Option Description
View All Fit the geometries to the window. The geometries are
automatically scaled to fit the window.

Zoom In Zoom in by a fixed increment.

Zoom Out Zoom out by a fixed increment.

Config substrate display This is a display-only option that has no effect on simulation.

No Substrate
Substrate With Frame
Substrate With Frame and Face
Change Substrate Display Margin
Change transparency This is a display-only option that has no effect on simulation.

Use layer specified Restriction: This option has no effect.

transparency
Decrease transparency Decrease the ability to see through geometries. You can see
through plane layers when viewed from the bottom.
Increase transparency Increase the ability to see through geometries. You can see
through plane layers when viewed from the bottom.
Transformation Opens the 3D Geometry View Transformation dialog box, where
you can manually enter angles, axis scale factors, and overall
zoom factors.
Default Angles Rotate the geometries to the original position and angle.

Top View Display the top of the geometries.

Front View Display the front of the geometries.

Side View Display the side of the geometries.

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HyperLynx 3D EM Geometry Viewer - 3D Geometry View Dialog Box

Table 33-34. HyperLynx 3D EM Geometry Viewer - 3D Geometry View Dialog

Box Contents (cont.)
Option Description
Show/hide axis Toggle the display of the X/Y/Z axis lines that are located at the
center of the image. The figure below shows the visible axes.

Turn on/off light Toggles the light that “shines” on the image, providing highlights
and shadows to help see subtle shapes.
Set view parameters Restriction: This button is always unavailable.

Animate Restriction: This button is always unavailable.

Change background color Opens a dialog box where you can select a background color.

Save current view to bmp Saves the current view to a bitmap file.
file

Related Topics
“Via Properties Dialog Box” on page 1908

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 Dialog Boxes
HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View Dialog Box

HyperLynx 3D EM Geometry Viewer - 3D Simulation

Current View Dialog Box
To access: From the Via Properties Dialog Box, from the 3D EM Modeling list, select
HyperLynx 3D EM Solver > View 3D Current
Use this viewer to display the average strength of the time-harmonic current density distribution
at a specific frequency. Areas of high current density indicate current crowding and higher
impedance. You can use this viewer to verify that high current density occurs in the expected
locations.
The initial plot shows the maximum current flow. Click Animate to see the current flow
over time.
The geometries can include the signal via, signal traces, metal areas and stitching vias. See
“Extracted Geometries for 3-D Electromagnetic Simulation of Signal Vias” on page 1663.
Restrictions:
• If your design contains perforations or voids in the metal shapes next to the signal via,
they do not exist in the geometries used by 3-D electromagnetic simulation. The metal
area geometries can contain anti-pads for the signal via and stitching vias.
• This topic describes only the 3D Simulation Current View dialog box. While the parent
HyperLynx 3D EM Geometry Viewer has a Views menu and toolbar that enables you to
display other windows, this topic does not describe them.

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Dialog Boxes
HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View Dialog Box

Figure 33-42. HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View

Dialog Box

Table 33-35. HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View

Dialog Box Contents
Option Description
View All Fit the geometries to the window. The geometries are
automatically scaled to fit the window.

Zoom In Zoom in by a fixed increment.

Zoom Out Zoom out by a fixed increment.

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HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View Dialog Box

Table 33-35. HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View

Dialog Box Contents (cont.)
Option Description
Config substrate display These are display-only option that have no effect on simulation.

No Substrate
Substrate With Frame
Substrate With Frame and Face
Change Substrate Display Margin
Change transparency This is a display-only option that has no effect on simulation.

Use layer specified Restriction: This option has no effect.

transparency
Decrease transparency Decrease the ability to see through geometries. You can see
through plane layers when viewed from the bottom.
Increase transparency Increase the ability to see through geometries. You can see
through plane layers when viewed from the bottom.
Transformation Opens the 3D Geometry View Transformation dialog box, where
you can manually enter angles, axis scale factors, and overall
zoom factors.
Default Angles Rotate the geometries to the original position and angle.

Top View Display the top of the geometries.

Front View Display the front of the geometries.

Side View Display the side of the geometries.

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Dialog Boxes
HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View Dialog Box

Table 33-35. HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View

Dialog Box Contents (cont.)
Option Description
Show/hide axis Toggle the display of the X/Y/Z axis lines that are located at the
center of the image. The figure below shows the visible axes.

Turn on/off light Toggles the light that “shines” on the image, providing highlights
and shadows to help see subtle shapes.
Show/hide color palette Toggles the legend near the left side of the viewer.
information bar

Show/hide port information Toggle the port information spreadsheet near the bottom of the
bar viewer.

Set view parameters Opens the Display Parameters dialog box, which this
documentation does not describe.

Advanced customers who are familiar with 3-D EM simulation

can use this dialog box to display different kinds of simulation
information.
Animate Toggles the current flow animation. Each frame represents the
state of the current distribution at a specific time at a specific
frequency.

The initial frame shows the current density at the moment of the
excitation at the ports.
Change background color Opens a dialog box where you can select a background color.

Save current view to bmp Saves the current view to a bitmap file.
file

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HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View Dialog Box

Table 33-35. HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View

Dialog Box Contents (cont.)
Option Description
Legend pane
Max E-Current Displays the maximum electric current (in Amperes per meter).

While you can toggle the display between electric and magnetic
current (by clicking Set view parameters and selecting the
Current Type option), magnetic current is not commonly used for
signal via analysis.
Legend Maps the colors in the geometry viewer to current density values.
By using dB values and Max E-Current, you can find out how
strong the current is at a specific location.
Freq Current distribution is displayed for the listed frequency.
Spreadsheet pane
Port Number of the port in the simulation circuit. A port attaches to the
signal trace and reference plane, as illustrated in the figure below.

Mag(Vs) Magnitude of the voltage source.

Ang(Vs) Angle of the voltage source.
Mag(Inc) Magnitude of the incident wave.
Ang(Inc) Angle of the incident wave.
Mag(Ref) Magnitude of the reflected wave.
Ang(Ref) Angle of the reflected wave.
Mag(V) Magnitude of the voltage.
Ang(V) Angle of the voltage.
Mag(I) Magnitude of the current.
Ang(I) Angle of the current.
Re(Zs) Real part of the source impedance.

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HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View Dialog Box

Table 33-35. HyperLynx 3D EM Geometry Viewer - 3D Simulation Current View

Dialog Box Contents (cont.)
Option Description
Im(Zs) Imaginary part of the source impedance.
Zc Normalization impedance.

Related Topics
“Via Properties Dialog Box” on page 1908

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 Dialog Boxes
HyperLynx 3D EM Project Dialog Box

HyperLynx 3D EM Project Dialog Box

To access: From the Via Properties Dialog Box, select HyperLynx 3D EM Solver > New,
from the New HyperLynx 3D EM Project Dialog Box, select OK
Use this dialog box to specify padstacks, geometric properties, 3-D electromagnetic simulation
parameters, and so on, for a signal via or differential via pair in the free-form schematic.

Figure 33-43. HyperLynx 3D EM Project Dialog Box

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HyperLynx 3D EM Project Dialog Box

Table 33-36. HyperLynx 3D EM Project Dialog Box Contents

Option Description
Via Area
Padstack Name of the padstack to use.

Edit Requirement: Set up padstacks for the schematic before

assigning them to vias. See “Managing Padstacks”.

Click Edit to edit padstack properties in the Padstack Editor. See

“Editing Padstack Properties”.
Common Anti-Pad Select to enclose both vias in a differential via with a single anti-
pad.

Restriction: This option is unavailable for single-ended vias.

Separation Distance between the centerlines of differential via barrels.

Restriction: This option is unavailable for single-ended vias.

Entry Layer Name of the stackup layer that is connected to the entry port in the
Touchstone model created by HyperLynx 3D EM.
Exit Layer Name of the stackup layer that is connected to the exit port in the
Touchstone model created by HyperLynx 3D EM.
Simulation Parameters Area
Model Type • Normal—Model all objects with actual metal stackup layer
thicknesses. This option provides the best accuracy, at the
expense of a slower run time.
• Accelerated—Model traces and vias with actual metal
stackup layer thicknesses, but model other objects (such as
metal pours and plane layers) with an infinitely thin metal
stackup layer thickness. This option provides good accuracy
and shorter run time.

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HyperLynx 3D EM Project Dialog Box

Table 33-36. HyperLynx 3D EM Project Dialog Box Contents (cont.)

Option Description
Boundary Size Distance from the edge of the geometry box used by 3-D
electromagnetic simulation to either the centerline of the stitching
via or the signal via (if there are no stitching vias).

The default value provides a good balance between model

accuracy and simulation run times for general board stackups and
signals up to the 15 - 20 GHz frequency range.

Differential and single-ended via default: 75 mils or 1.905 mm.

See “Extracted Geometries for 3-D Electromagnetic Simulation

of Signal Vias” on page 1663.
Frequencies Area

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Dialog Boxes
HyperLynx 3D EM Project Dialog Box

Table 33-36. HyperLynx 3D EM Project Dialog Box Contents (cont.)

Option Description
Minimum Lowest frequency that simulation runs and writes to the S-
parameter model.

When you clear the Minimum check box, <auto> means that
HyperLynx 3D EM Designer calculates the minimum value based
on the structure and the maximum frequency.

When you select the Minimum check box, enter the minimum
frequency. 10 MHz is good for common cases. If you are not
interested in frequency responses below 1 GHz (or higher), you
can specify a larger value.
Maximum Highest frequency that simulation runs and writes to the S-
parameter model.

You can calculate the maximum frequency from the signal rising
or falling edge time. For example, below is a popular equation:

Maximum frequency = 0.35 / (signal rise time or fall time)

Meshing Highest frequency for which simulation meshing is accurate. The
maximum model frequency cannot exceed this value.
Num Points The number of frequencies contained in the generated S-
parameter model. The frequencies are distributed linearly.

When you clear the Minimum check box, <auto> means that
HyperLynx 3D EM Designer calculates the minimum value based
on the structure and the maximum frequency.

When you select the Minimum check box, manually enter the
number of frequencies for the generated S-parameter model to
contain. Unless you want to specify a very narrow range in the
generated S-parameter model, entering values in the 100 to 200
range is good.

Note: HyperLynx 3D EM uses an advanced searching algorithm

to solve only the critical frequency points. The simulation run
times for Num Points = 100 and Num Points = 200 can be very
close because HyperLynx 3D EM solves the same number of
critical frequency points in both cases.
Feeding Traces Area

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HyperLynx 3D EM Project Dialog Box

Table 33-36. HyperLynx 3D EM Project Dialog Box Contents (cont.)

Option Description
For Layer Stackup layer(s) that receive the settings.
• <Both>—Specify the length and width values to use for
feeding traces on both the Entry Layer and Exit Layer.
• <Entry Layer>—Specify the length and width values to use
for the feeding trace located on the Entry Layer.
• <Exit Layer>—Specify the length and width values to use for
the feeding trace located on the Exit Layer.

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HyperLynx 3D EM Project Dialog Box

Table 33-36. HyperLynx 3D EM Project Dialog Box Contents (cont.)

Option Description
Length For single-ended vias, Length determines the distance between
the via centerline and the edge of the geometry box used by 3-D
L1 electromagnetic simulation.

L2

To visualize the geometry box, vias, and trace segments, click

View 3D. See “Extracted Geometries for 3-D Electromagnetic
Simulation of Signal Vias” on page 1663.

For differential vias, the L1 and L2 trace segment lengths partially

determine the distance between the via centerline and the edge of
the geometry box used by 3-D electromagnetic simulation. Other
geometries contributing to this distance include trace-to-trace and
via-to-via separation. The coupled transmission lines properties
includes the trace-to-trace separation.

Restriction: L2 is unavailable if you select Angle.

Connection traces are also known as feeding traces.

The default values provide a good balance between model

accuracy and simulation run times for general board stackups and
signals up to the 15 - 20 GHz frequency range.
• Differential via defaults: L1 = 60 mils or 1.524 mm. L2 = 30.5
mils or 0.7747 mm.
• Single-ended via defaults: L1 = 60 mils or 1.524 mm.

LineSim automatically subtracts the lengths you specify from the

transmission lines connected to the via. This subtraction takes
place during simulation and does not affect the length specified in
the transmission-line symbol.
Width Trace segment width, as defined in Edit Transmission Line
Dialog Box - Edit Coupling Regions Tab.
W

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HyperLynx 3D EM Project Dialog Box

Table 33-36. HyperLynx 3D EM Project Dialog Box Contents (cont.)

Option Description
D Trace-to-trace separation (edge to edge) for a differential pair, as
defined in Edit Transmission Line Dialog Box - Edit Coupling
Regions Tab.

Restriction: This option is unavailable for single-ended vias.

Angle The automatically calculated angle between the L1 and L2 trace
segments for a differential pair. See “Connected Trace Angle for
Differential Pairs” on page 1665.

Restriction: This option is unavailable for single-ended vias.

Stitching Vias Area
Padstack Name of the padstack to use.

Edit Requirement: Set up padstacks for the schematic before

assigning them to vias. See “Managing Padstacks”.

Click Edit to edit padstack properties in the Padstack Editor. See

“Editing Padstack Properties”.
Number Quantity of stitching vias to locate next to the signal via.
Offset Y The Y offset from the signal via to the stitching vias.

Restriction: This option is unavailable when Number is 0.

Offset X The X offset from the signal via to the stitching vias.

Restriction: This option is unavailable when Number is 0 or 2.

Connected Layers Metal stackup layers to connect with stitching vias.

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Dialog Boxes
HyperLynx 3D EM Project Dialog Box

Table 33-36. HyperLynx 3D EM Project Dialog Box Contents (cont.)

Option Description
View 3D Opens the HyperLynx 3D EM Geometry Viewer - 3D Geometry
View Dialog Box to display the geometries used by 3-D
electromagnetic simulation. The geometries can include the
signal via, signal traces, metal areas and stitching vias. See
“Extracted Geometries for 3-D Electromagnetic Simulation of
Signal Vias” on page 1663.

Restriction: If your design contains perforations or voids in the

metal shapes next to the signal via, they do not exist in the
geometries used by 3-D electromagnetic simulation. By contrast,
the metal area geometries can contain anti-pads for the signal via
and stitching vias.

Note: When you click View 3D, a read only and blank dialog box
opens before the HyperLynx 3D EM Geometry Viewer opens. Do
not close this dialog box. It closes automatically when you close
the HyperLynx 3D EM Geometry Viewer.
Simulate Opens the HyperLynx 3D EM Full-Wave EM Simulation Dialog
Box and automatically run simulation. The HyperLynx 3D EM
Full-Wave EM Simulation Dialog Box closes automatically when
simulation completes.
View Model Display the S-parameter file created by HyperLynx 3D EM
simulation.

Restriction: Run simulation to completion before clicking View

Model.

The default file name form is via_FFS_V<model_version>.s#p

where:

<model_version> automatically increments to avoid overwriting

a previously-generated model file

# is the number of model ports

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HyperLynx 3D EM Project Dialog Box

Table 33-36. HyperLynx 3D EM Project Dialog Box Contents (cont.)

Option Description
View 3D Current Opens the HyperLynx 3D EM Geometry Viewer - 3D Simulation
Current View Dialog Box to display the current density across the
geometries used by 3-D electromagnetic simulation.

The geometries can include the signal via, signal traces, metal
areas and stitching vias. See “Extracted Geometries for 3-D
Electromagnetic Simulation of Signal Vias” on page 1663.

Restrictions:
• Run simulation to completion before clicking View 3D
Current.
• If your design contains perforations or voids in the metal
shapes next to the signal via, they do not exist in the
geometries used by 3-D electromagnetic simulation. By
contrast, the metal area geometries can contain anti-pads for
the signal via and stitching vias.

Extracted Geometries for 3-D Electromagnetic Simulation of Signal Vias

Figure 33-44 shows part of a signal net that passes through a via and a pair of metal shapes, with
trace segments that enter and exit the via. The capacitor symbols show the via and trace
segments couple to the metal shapes.

Figure 33-44. Signal Via Coupling

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Dialog Boxes
HyperLynx 3D EM Project Dialog Box

The HyperLynx 3D EM solver provides the most accurate way to model these coupling effects.
Because 3-D electromagnetic simulation takes much longer to run than 2-D simulation,
HyperLynx helps you choose how much of the surrounding geometries to include in 3-D
simulation for signal vias.
See Figure 33-45. HyperLynx 3D EM runs 3-D simulation on structures inside the box formed
by the dashed lines and HyperLynx SI/PI runs 2-D simulations on structures outside the box.
HyperLynx extracts the geometries inside the box into a 3-D model (that is, a .GEO file) that
HyperLynx 3D EM uses when running 3-D electromagnetic simulation.

Figure 33-45. Geometry Box for 3-D Electromagnetic Simulation

If needed, use the HyperLynx 3D EM Project Dialog Box to adjust the size of the box. Use
Boundary Size and Feeding Traces Area options to specify the length and width of the box. The
box height is set automatically to enclose the metal structures.
HyperLynx accounts for the 3-D modeling in the overall net length by automatically removing
the portions of trace segments included in the 3-D model by shortening one or more of the
transmission lines in the 2-D model. This adjustment prevents duplicating a portion of a trace
segment in both 3-D and 2-D simulation models.
Restriction: If your design contains perforations or voids in the metal shapes next to the signal
via, they do not exist in the geometries used by 3-D electromagnetic simulation. The metal area
geometries can contain anti-pads for the signal via and stitching vias.

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HyperLynx 3D EM Project Dialog Box

Connected Trace Angle for Differential Pairs

Figure 33-46 shows the landmarks used in this section.

Figure 33-46. Connected Trace Angle for Differential Pairs

Given:
All lengths in mils
H = L2 = 30.5. L2 is the same for both vias.
Separation (distance between via centerlines) = 75
D = 10.
W=6
Note: The Edit Transmission Line Dialog Box - Edit Coupling Regions Tab provides the values
for D and W.
To calculate the angle:
Form a right triangle as shown by the black lines in Figure 33-46.
H = hypotenuse. O = opposite. A = angle.
Solve for O:
O = (Separation / 2) - (D / 2) - (W / 2)
O = (75 / 2) - (10 / 2) - (6 / 2) = 29.5
Solve for A:
A = arcsin (O / H)
A = arcsin (29.5 / 30.5) = 75.3 degrees

Related Topics
“Via Properties Dialog Box” on page 1908
“New HyperLynx 3D EM Project Dialog Box” on page 1769

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Dialog Boxes
HyperLynx File Editor

HyperLynx File Editor

To access: Edit > Plain Text File
Use the HyperLynx File Editor as a convenient way to open text files directly from BoardSim
and LineSim. HyperLynx also launches the editor to display files, such as the BoardSim batch
simulation standard report and SPICE models.
When displaying Board Wizard results for generic SI batch simulation, the editor toolbar
contains additional Find Warning Severe and Find Warning buttons to help navigate through
warnings in the report.
You can save the file currently loaded in the editor either as a DOS-formatted or UNIX-
formatted file by using the File > Save As > DOS | UNIX command.

Figure 33-47. HyperLynx File Editor

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HyperLynx IBIS-AMI Sweeps Viewer

HyperLynx IBIS-AMI Sweeps Viewer

To access:
• Run IBIS-AMI sweep simulation (dialog box automatically opens after simulation)
• Select Simulate SI > Show Previous AMI Sweeps Results
• Select Simulate SI > Run IBIS-AMI Channel Analysis and select the View Analysis
Results page > View button next to Sweep results
Use this dialog box to display IBIS-AMI sweep simulation results.
This topic contains the following:
• “GUI Overview” on page 1668
• “Menus - HyperLynx IBIS-AMI Sweeps Viewer” on page 1670
• “Toolbar - Main” on page 1674
• “Toolbar - Plot View” on page 1676
• “Plot View Pane” on page 1678
• “Spreadsheet” on page 1681
• “Plot View Options Pane” on page 1689
• “Spreadsheet Options Pane” on page 1692
• “Sliders Pane” on page 1695
• “Organizing Windows” on page 1700

Related Topics
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611
“IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page” on page 1756

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GUI Overview

GUI Overview
Figure 33-48 shows the main elements of the graphical user interface.

Figure 33-48. HyperLynx IBIS-AMI Sweeps Viewer GUI Overview

Figure 33-49 shows the cross-linking among the spreadsheet, Sliders pane, and plot contents.
Selecting a spreadsheet row updates the slider positions and plot contents. Similarly, dragging a
slider selects the corresponding spreadsheet row and updates the plot contents.

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GUI Overview

Figure 33-49. HyperLynx IBIS-AMI Sweeps Viewer Cross Linking

You can move, hide, and detach GUI objects, using the methods described in “Organizing
Windows” on page 1700.

Related Topics
“HyperLynx IBIS-AMI Sweeps Viewer” on page 1667

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Dialog Boxes
Menus - HyperLynx IBIS-AMI Sweeps Viewer

Menus - HyperLynx IBIS-AMI Sweeps Viewer

File Menu

Table 33-37. HyperLynx IBIS-AMI Sweeps Viewer - File Menu Contents

Item Description
Open Opens a simulation data storage (.SDS) file previously written by
running a IBIS-AMI sweep simulation.

For information about the location and contents of .SDS files, see
“BER and eye density plots” on page 623.
Save Saves the currently-loaded simulation data storage (.SDS) file. For
example, if you edited the eye mask in such a way that made an
eye change from a fail to a pass, the updated spreadsheet pass
value is saved to the .SDS file.
Save As Saves currently-loaded simulation data storage (.SDS) file to a
new file.

If you save the file to a new folder, the BER and eye density plots
(.TPS) files associated with the .SDS file are also copied to the
new folder.
Print Prints the spreadsheet.

For information about printing from Linux/UNIX, see “Printing

from UNIX/Linux Using MainWin”.
Print Preview Opens print preview.
Print Setup Opens the Print Setup dialog box.
<numbered_list> Displays a numbered list of previously-opened .SDS files. Click a
file to open it.
Exit Closes the viewer.

Edit Menu

Table 33-38. HyperLynx IBIS-AMI Sweeps Viewer - Edit Menu Contents

Item Description
Copy Copies selected spreadsheet cells, so you can paste the text to
another application, such as Microsoft Notepad.

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Menus - HyperLynx IBIS-AMI Sweeps Viewer

Table 33-38. HyperLynx IBIS-AMI Sweeps Viewer - Edit Menu Contents (cont.)
Item Description
Configure Eye Mask Opens the Configure Eye Mask dialog box. See “Editing Eye
Mask Properties” on page 564.

View Menu
The spreadsheet is the only major GUI element that cannot be hidden.
Table 33-39. HyperLynx IBIS-AMI Sweeps Viewer - View Menu Contents
Item Description
Status Bar Displays the status bar at the bottom of the viewer.
Main Toolbar Displays the toolbar. See Toolbar - Main.
Plot View Displays the Plot View Pane.
Plot Options Displays the Plot View Options Pane.
Spreadsheet Options Displays the Spreadsheet Options Pane.
Sliders Displays the Sliders Pane.

Spreadsheet Menu

Table 33-40. HyperLynx IBIS-AMI Sweeps Viewer - Spreadsheet Menu Contents

Item Description
Add Filter Opens the Add Filter dialog box, where you specify the filter
conditions for hiding spreadsheet rows.
Remove All Filters Permanently deletes all filters and displays all the spreadsheet
rows.
Add Sorting Opens the Add Sorting dialog box, where you specify the
conditions for sorting spreadsheet rows.
Remove All Sorting Permanently deletes all sorting.
Columns > <column_name> Select to display the named spreadsheet column. This option
also controls which sliders the Sliders pane displays.

The leftmost set of columns contain the IBIS-AMI parameters

that you enabled for sweeping on the IBIS-AMI Channel
Analyzer Wizard - Sweep AMI Model Settings Page.

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Menus - HyperLynx IBIS-AMI Sweeps Viewer

Plot Menu

Table 33-41. HyperLynx IBIS-AMI Sweeps Viewer - Plot Menu Contents

Item Description
Eye Density Formats the results as an eye density plot.

For an example plot, see Figure 33-51 on page 1678.

Bit Error Rate Formats the results as a bit error rate plot.

For an example plot, see Figure 33-52 on page 1679.

Show Eye Mask Overlays an eye mask over the plot.

To select a different eye mask or edit the selected eye mask, see
“Editing Eye Mask Properties” on page 564.
Show Grid Overlays the plot with a grid, where UI is on the X axis and
voltage is on the Y axis.

Auto fit to window Scales the simulation results to fit in the window.

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Menus - HyperLynx IBIS-AMI Sweeps Viewer

Table 33-41. HyperLynx IBIS-AMI Sweeps Viewer - Plot Menu Contents (cont.)
Item Description
Auto Range Adjusts the zoom scale and data range to fit the results to the
screen.

Related Topics
“HyperLynx IBIS-AMI Sweeps Viewer” on page 1667

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Toolbar - Main

Toolbar - Main

Table 33-42. HyperLynx IBIS-AMI Sweeps Viewer - Toolbar - Main Contents

Button Description
Open an existing Opens a simulation data storage (.SDS) file previously written by
document IBIS-AMI sweep simulation.

For information about the location and content of .SDS files, see
“BER and eye density plots” on page 623.
Save the existing Saves the currently-loaded simulation data storage (.SDS) file. For
document example, if you edited the eye mask in such a way that made an eye
change from a fail to a pass, the updated spreadsheet pass value is
saved to the .SDS file.
Copy the selection and Copies selected spreadsheet cells, so you can paste the text to another
put it on the clipboard application, such as Microsoft Notepad.

Print the active Prints the spreadsheet.

document
For information about printing from Linux/UNIX, see “Printing from
UNIX/Linux Using MainWin”.
Show or hide Plot Select to display the Plot View Pane.
View pane

Show or hide Plot Select to display the Plot View Options Pane.
Options pane

Show or hide Select to display the Spreadsheet Options Pane.

Spreadsheet Options
pane

Show or hide Sliders Select to display the Sliders Pane.

pane

Add new data filter Opens the Add Filter dialog box, where you specify the filter
conditions for hiding spreadsheet rows.
Remove all current Permanently deletes all filters and displays all the spreadsheet rows.
filters

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Toolbar - Main

Table 33-42. HyperLynx IBIS-AMI Sweeps Viewer - Toolbar - Main Contents

Button Description
Add data sorting Opens the Add Sorting dialog box, where you specify the conditions
for sorting spreadsheet rows.
Remove all current Permanently deletes all sorting and displays spreadsheet rows in the
sorting original order.

Edit eye mask Opens the Configure Eye Diagram dialog box to edit eye mask
parameters properties for eye diagram analysis. You can load existing eye masks
from a library or save new eye masks into a library.

See “Editing Eye Mask Properties” on page 564.

Display help Opens Help for this dialog box.

Related Topics
“HyperLynx IBIS-AMI Sweeps Viewer” on page 1667

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Toolbar - Plot View

Toolbar - Plot View

Use the toolbar located in the Plot View Pane to enable turn, zoom, and other view-
enhancement features. The Inspect button displays numerical results when you point to the
simulation results shape.

Figure 33-50. HyperLynx IBIS-AMI Sweeps Viewer - Toolbar - Plot View

Table 33-43. HyperLynx IBIS-AMI Sweeps Viewer - Toolbar - Plot View

Contents
Button Description
Turn Drag in the plot to rotate simulation results.

The rotation axis is in the center of the maximum X/Y extents of

the simulated geometries.

Restriction: This mode is unavailable when top view is enabled.

Pan Drag in the plot to move simulation results without zooming or
rotating.

Keyboard shortcut: Press Shift to enable.

Zoom Drag up to zoom out. Drag down to zoom in.

Use the mouse wheel to zoom in and out.

Keyboard shortcut: Press Alt to enable.

Inspect Point to a shape to display X/Y coordinates and numerical
simulation results values in a ToolTip.

Keyboard shortcut: Press Ctrl to enable.

Default View Restores initial rotation and zoom.

3-D / 2-D, Top View Only Toggles between the 3-D and 2-D views.

The 2-D view displays results as seen from above.

Fit to View Resizes the results so they fit on the screen.

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Toolbar - Plot View

Related Topics
“HyperLynx IBIS-AMI Sweeps Viewer” on page 1667

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Dialog Boxes
Plot View Pane

Plot View Pane

To access: From the HyperLynx IBIS-AMI Sweeps Viewer, select View > Plot View.
Use this pane to display IBIS-AMI simulation results. You can format the results as an eye
density plot or a bit error rate (BER) plot. Figure 33-51 and Figure 33-52 show the 2-D view. A
3-D view is also available.

Figure 33-51. Plot View Pane - Eye Density Plot

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Plot View Pane

Figure 33-52. Plot View Pane - BER Plot

Table 33-44. Plot View Pane Contents

Option Description
Toolbar Provides zoom and other view-enhancement controls. For button
descriptions, see Toolbar - Plot View.

The Inspect button displays numerical results when you

point to the simulation results shape.
Right-click menu The right-click menu duplicates some of the options located in
the Plot View Options Pane.
Eye mask Optionally overlays the plot with an eye mask that provides a
visual way to determine whether the simulation results intersect
a “keepout” area.

To load a pre-defined eye mask or edit the current eye mask,

select either:
• Edit eye mask parameters button on the main toolbar.
• Configure button on the Plot View Options pane.
Results legend Maps the color of the results to a BER.

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Plot View Pane

Table 33-44. Plot View Pane Contents (cont.)

Option Description
Coordinate grid and related Optionally overlays the plot with a grid, where UI is on the X
X/Y legends axis and voltage is on the Y axis. 1 unit interval = 1 bit interval.

To show or hide the grid, select Show grid.

Related Topics
“HyperLynx IBIS-AMI Sweeps Viewer” on page 1667

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Spreadsheet

Spreadsheet
To access: Open the HyperLynx IBIS-AMI Sweeps Viewer
Use the spreadsheet to display the combination of model parameter values, numerical
simulation results, and pass/fail results.
You can sort spreadsheet rows by Highest BER, Eye mask margin (time), and so on. See
“Right-click menu” on page 1686.
Click anywhere in a spreadsheet row to display the corresponding set of:
• Simulation results in the Plot View pane
• Values in the Sliders pane
To see how the sliders and spreadsheet rows link to each other, see Figure 33-49 on page 1669.

Figure 33-53. HyperLynx IBIS-AMI Sweeps Viewer Spreadsheet

Table 33-45. HyperLynx IBIS-AMI Sweeps Viewer Spreadsheet Contents

Object Description
Sweep parameters Columns

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Spreadsheet

Table 33-45. HyperLynx IBIS-AMI Sweeps Viewer Spreadsheet Contents (cont.)

Object Description
<swept_parameters> Displays the set of IBIS-AMI model parameters that you selected
to sweep in the IBIS-AMI Channel Analyzer Wizard - Sweep
AMI Model Settings Page.

The spreadsheet displays some sweep ranges as a list of quoted

integers, such as “0”, “2”. The integers map to spreadsheet rows
in the Sweeping Dialog Box.

Simulation results Columns

The viewer automatically calculates all the data in these columns. This means:
• The .SDS file does not store the spreadsheet results. The viewer recalculates them when you
open the .SDS file.
• The number and composition of the spreadsheet columns does not depend on the initial set
of swept parameters.
• These values depend on the eye mask parameters. If you change the eye mask or BER
threshold value, viewer recalculates all the data in these columns.

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Spreadsheet

Table 33-45. HyperLynx IBIS-AMI Sweeps Viewer Spreadsheet Contents (cont.)

Object Description
Highest BER Highest bit error rate value measured along the perimeter of the
diamond-shaped eye mask polygon.

Tips:
• You may need to widen the spreadsheet column to see the full
measurement value.
• The 0 value represents 1e-10 or lower.

If you place the eye mask over the BER plot, you can see where
the eye mask touches the BER plot. This cell reports the highest
BER measurement touched by the eye mask. For example
measurements, see “Highest BER Examples” on page 1686.

If the highest BER is less than the BER Threshold value, the
Pass/fail eye mask value is Pass. Use the Eye Mask tab on the
Configure Eye Diagram dialog box to set the BER threshold. See
step 6 in “Editing Eye Mask Properties” on page 564.
Pass/fail eye mask Pass if Highest BER is less than the BER Threshold value. Use
the Eye Mask tab on the Configure Eye Diagram dialog box to set
the BER threshold. See step 6 in “Editing Eye Mask Properties”
on page 564.

The spreadsheet always displays the pass/fail result, even if the

eye mask is not displayed.
Eye mask margin - Minimum distance, in time (in UI), between the eye plot and eye
Time, UI mask, as measured at the median voltage level (0 V).

The value is n/a if there is no gap between the eye mask and the
eye plot.

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Spreadsheet

Table 33-45. HyperLynx IBIS-AMI Sweeps Viewer Spreadsheet Contents (cont.)

Object Description
Eye mask margin - Minimum vertical distance, in voltage, between the eye plot and
Voltage, V eye mask.

The voltage margin is measured at all points on the eye mask

perimeter, not just the few places indicated in the figure below.

The value is n/a if there is no gap between the eye mask and the
eye plot.

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Spreadsheet

Table 33-45. HyperLynx IBIS-AMI Sweeps Viewer Spreadsheet Contents (cont.)

Object Description
Eye opening - Time, UI The distance in time between the right and left sides of the inner
boundary of the eye diagram, as measured at the median voltage
level (0 V).

Eye opening measurements do not include a guardband. By

contrast, test bench equipment may apply a guardband, such as
three sigma.

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Spreadsheet

Table 33-45. HyperLynx IBIS-AMI Sweeps Viewer Spreadsheet Contents (cont.)

Object Description
Eye opening - Voltage, The minimum distance in voltage from the median voltage level
V (0 V) to the top and bottom sides of the inner boundary of the eye
diagram, as measured at the eye center (0.5 UI).

The AMI specification indicates the eye center is formed by Rx

clocks and reflects the actual sampling point after CDR (clock
and data recovery).

Eye opening measurements do not include a guardband. By

contrast, test bench equipment may apply a guardband, such as
three sigma.
Right-click menu
Duplicates many of the options available from the Spreadsheet
Options Pane. Right-click anywhere in the spreadsheet to open
this menu.

Highest BER Examples

Figure 33-54 and Figure 33-55 show example measurements for the Highest BER spreadsheet
cell.

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Spreadsheet

Figure 33-54. Highest BER is 5.97e-6

Figure 33-55. Highest BER is Very Low

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Spreadsheet

Related Topics
“HyperLynx IBIS-AMI Sweeps Viewer” on page 1667

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Plot View Options Pane

Plot View Options Pane

To access: From the HyperLynx IBIS-AMI Sweeps Viewer, select View > Plot Options.
Use this pane to set display options for the Plot View Pane.

Figure 33-56. Plot View Options Pane

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Plot View Options Pane

Table 33-46. Plot View Options Pane Contents

Option Description
Graph type Area
Eye Density Select to format the simulation results as an eye density plot.
For an example plot, see Figure 33-51 on page 1678.
Bit Error Rate Select to format the simulation results as a BER plot. For an
example plot, see Figure 33-52 on page 1679.
Eye mask Area
Show eye mask Select to overlay an eye mask over the plot.
Configure Opens the Configure Eye Diagram dialog box to edit eye mask
properties for eye diagram analysis. You can load existing eye
masks from a library or save new eye masks into a library.

See “Editing Eye Mask Properties” on page 564.

UI and voltage scale Area
Auto UI and voltage Scales the simulation results to fit in the window.
UI X-axis scale. 1 unit interval = 1 bit interval.
Voltage Y-axis scale.
Range Area
Auto range Adjusts the zoom scale and data range to fit the results to the
screen.
Zoom Zoom scale.
Move Defines the lowest BER value to display. Values below this
will not display.
Coordinate grid Area

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Plot View Options Pane

Table 33-46. Plot View Options Pane Contents (cont.)

Option Description
Show grid Select to overlay the plot with a grid, where UI is on the X axis
and voltage is on the Y axis.

UI Drag the slider to select the time interval, in UI, of vertical grid
lines.
Voltage Drag the slider to select the voltage interval, in volts, of
horizontal grid lines.

Related Topics
“HyperLynx IBIS-AMI Sweeps Viewer” on page 1667

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Spreadsheet Options Pane

Spreadsheet Options Pane

To access: From the HyperLynx IBIS-AMI Sweeps Viewer, select View > Spreadsheet
Options.
Use this pane to edit display options for the spreadsheet.

Figure 33-57. Spreadsheet Options Pane

Table 33-47. Spreadsheet Options Pane Contents

Option Description
Appearance Area
Font Specifies the appearance of characters in rows containing
simulation results rows.
Sweeps color Specifies the background for the left-most group of columns for
unselected rows that pass simulation.

For information about pass/fail criteria, see Pass/fail eye mask.

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Spreadsheet Options Pane

Table 33-47. Spreadsheet Options Pane Contents (cont.)

Option Description
Results color Specifies the background color for rows that pass simulation.

For information about pass/fail criteria, see Pass/fail eye mask.

Fails color Specifies the background color for rows that fail simulation.

For information about pass/fail criteria, see Pass/fail eye mask.

Highlight color Specifies the background color of the selected spreadsheet row.
Columns Area
<various> Specifies whether to show or hide the column, and the sliders in
the Sliders pane.

Columns under the Sweep parameters heading display the set

of IBIS-AMI model parameters that you selected to sweep in
the IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model
Settings Page.
Sorting Area
Sort by Specifies one or more criteria to sort spreadsheet rows.

To remove existing sorting criteria, select <Remove> at the

bottom of the Column list.

Filtering Area

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Spreadsheet Options Pane

Table 33-47. Spreadsheet Options Pane Contents (cont.)

Option Description
New filter Specifies one or more criteria to remove spreadsheet rows.

To remove an existing filter, select <Remove> at the bottom of

the Column list.

Related Topics
“HyperLynx IBIS-AMI Sweeps Viewer” on page 1667

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Sliders Pane

Sliders Pane
To access: From the HyperLynx IBIS-AMI Sweeps Viewer, select View > Sliders.
Use a slider on this pane to automatically select the corresponding spreadsheet row and
simulation results plot. To see how the sliders and spreadsheet rows link to each other, see
Figure 33-49 on page 1669.

Figure 33-58. Sliders Pane

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Sliders Pane

Table 33-48. Sliders Pane Contents

Option Description
<swept_parameters> Displays the set of IBIS-AMI model parameters that you
selected to sweep in the IBIS-AMI Channel Analyzer
Wizard - Sweep AMI Model Settings Page.

The Sliders pane displays some sweep ranges as a list of

quoted integers, such as “0”, “2”. The integers map to
spreadsheet rows in the Sweeping Dialog Box.
Highest BER Highest bit error rate value measured along the
perimeter of the diamond-shaped eye mask polygon.

Tips:
• You may need to widen the spreadsheet column to
see the full measurement value.
• The 0 value represents 1e-10 or lower.

If you place the eye mask over the BER plot, you can
see where the eye mask touches the BER plot. This cell
reports the highest BER measurement touched by the
eye mask. For example measurements, see “Highest
BER Examples” on page 1686.

If the highest BER is less than the BER Threshold value,

the Pass/fail eye mask value is Pass. Use the Eye Mask
tab on the Configure Eye Diagram dialog box to set the
BER threshold. See step 6 in “Editing Eye Mask
Properties” on page 564.
Pass/fail eye mask Pass if Highest BER is less than the BER Threshold
value. Use the Eye Mask tab on the Configure Eye
Diagram dialog box to set the BER threshold. See step 6
in “Editing Eye Mask Properties” on page 564.

The spreadsheet always displays the pass/fail result,

even if the eye mask is not displayed.

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Sliders Pane

Table 33-48. Sliders Pane Contents (cont.)

Option Description
Eye mask margin (time) Minimum distance, in time, between the eye plot and
eye mask, as measured at the median voltage level (0 V).

The value is n/a if there is no gap between the eye mask

and the eye plot.

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Sliders Pane

Table 33-48. Sliders Pane Contents (cont.)

Option Description
Eye mask margin (voltage) Minimum vertical distance, in voltage, between the eye
plot and eye mask.

The voltage margin is measured at all points on the eye

mask perimeter, not just the few places indicated in the
figure below.

The value is n/a if there is no gap between the eye mask

and the eye plot.

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Sliders Pane

Table 33-48. Sliders Pane Contents (cont.)

Option Description
Eye opening (time) The distance in time between the right and left sides of
the inner boundary of the eye diagram, as measured at
the median voltage level (0 V).

Eye opening measurements do not include a guardband.

By contrast, test bench equipment may apply a
guardband, such as three sigma.

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Sliders Pane

Table 33-48. Sliders Pane Contents (cont.)

Option Description
Eye opening (voltage) The minimum distance in voltage from the median
voltage level (0 V) to the top and bottom sides of the
inner boundary of the eye diagram, as measured at the
eye center (0.5 UI).

The AMI specification indicates the eye center is formed

by Rx clocks and reflects the actual sampling point after
CDR (clock and data recovery).

Eye opening measurements do not include a guardband.

By contrast, test bench equipment may apply a
guardband, such as three sigma.

Related Topics
“HyperLynx IBIS-AMI Sweeps Viewer” on page 1667

Organizing Windows
You can hide, automatically hide, and detach the panes in the HyperLynx IBIS-AMI Sweeps
Viewer.
This topic contains the following:
• “Manually Hiding and Showing Panes” on page 1701
• “Automatically Hiding and Showing Panes” on page 1701
• “Detaching Panes” on page 1702
• “Attaching Panes” on page 1702

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Sliders Pane

Note
The viewer does not provide an automatic way to restore the original window layout. If
you change the layout, you can manually change it back to the original window layout.

Manually Hiding and Showing Panes

Procedure
• Use the HyperLynx PI PowerScope Toolbar or View Menu.
• From the pane title bar, either:
o Select > Hide.
o Right-click > Hide.

Automatically Hiding and Showing Panes

The panes support auto hide, where the pane automatically minimizes to a tab until you point to
it with the mouse. Figure 33-59 shows one way to enable auto hide and show a minimized pane.

Figure 33-59. Pane Auto Hide Example

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Sliders Pane

Procedure
• From the pane title bar, do any of the following:
o Select vertical pushpin to enable auto hide.
o Select horizontal pushpin to disable auto hide.
o Select > Auto Hide to toggle auto hide.
o Right-click > Auto Hide to toggle auto hide.

Detaching Panes
Use this capability to change the pane into a window that you can move outside the viewer
window.

Procedure
• From the pane title bar, do either of the following:
o Double-click the title bar.
o Right-click > Floating.

Attaching Panes
You can attach a previously-detached pane to the viewer window.

When dragging panes to attach them to the viewer, the procedures refer to landmarks identified
by Figure 33-60. These landmarks appear temporarily, as you drag the pane.

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Sliders Pane

Figure 33-60. Pane Dragging Attachment Landmarks

Procedure
• From the pane title bar, do any of the following:
o Double-click the title bar. This restores the pane to its pre-detachment location.
o Right-click > Floating. This restores the pane to its pre-detachment location.
o To attach the pane as a tab, drag the pane to an attached pane, and then drag it to a
tabbed landmark, as shown in Figure 33-61.

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Sliders Pane

Figure 33-61. Drag Pane to Make Tabbed Item

o To attach the pane to the overall viewer dialog box, drag it to an outer landmark. See
Figure 33-62.

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Sliders Pane

Figure 33-62. Drag Pane to Make New Area

o To attach the pane to another pane, drag it to an attached pane, and then drag it to an
inner landmark. See Figure 33-63.

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Sliders Pane

Figure 33-63. Drag Pane to Attach to Other Pane

Related Topics
“HyperLynx IBIS-AMI Sweeps Viewer” on page 1667

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HyperLynx PI PowerScope Dialog Box

HyperLynx PI PowerScope Dialog Box

To access: This dialog box opens automatically when power-integrity simulation completes. To
manually open the HyperLynx PI PowerScope:
• Select LineSim > Simulate PI > Run Plane-Noise Simulation.
• Select BoardSim > Simulate PI > Run Plane-Noise Simulation. The Plane Noise
Analysis dialog box opens. Click Show PowerScope.
• Select Simulate PI > Run DC Drop Simulation. The DC Drop Analysis dialog box
opens. Click Show PowerScope.
• Select Simulate Thermal > Run PI/Thermal Co-Simulation. The Batch DC Drop
Simulation dialog box opens. Click Run.

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HyperLynx PI PowerScope Dialog Box

Description
Use this dialog box to display graphical simulation results for DC drop and plane noise.

Figure 33-64. HyperLynx PI PowerScope Dialog Box Contents

The HyperLynx PI PowerScope contains the following areas:

• “HyperLynx PI PowerScope Tabs” on page 1709
• “HyperLynx PI PowerScope Toolbar” on page 1710
• “HyperLynx PI PowerScope Results and Maximum Result Areas” on page 1711
• “HyperLynx PI PowerScope Legend” on page 1712
• “HyperLynx PI PowerScope Controls” on page 1713

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HyperLynx PI PowerScope Dialog Box

HyperLynx PI PowerScope Tabs

Use tabs to display simulation results for one or more plane layers (DC drop simulation) or a
pair of plane layers (plane-noise simulation). Tab names map to stackup layer names.

Tip: For DC drop, each tab displays the voltage drop only on that stackup layer. By
contrast, the textual report contains the total voltage drop for the power-supply net. See
“Reporter Dialog Box” on page 1834.

If you rerun simulation, additional previous and compare tabs open. You can close the previous
and compare tabs by clicking the tab and clicking the X. You cannot close tabs for the current
simulation.
If you load a saved HyperLynx PI PowerScope file (.TPS), an additional “loaded” tab opens.
.TPS files are located in the <design> folder unless you have previously saved them to another
location. See “About Design Folder Locations” on page 1391.

Figure 33-65. Plane Noise Tabs - HyperLynx PI PowerScope

Figure 33-66. DC Drop Tabs - HyperLynx PI PowerScope

Note
Each tab displays the DC drop across the ports of one plane layer. If you change the VRM
resistance and re-simulate, the current and previous tabs may display the same voltage
drop values while the text output (in the Reporter Dialog Box) shows a difference in
absolute voltages. This is because the plane layer is just one of several circuit elements. If
you increase the VRM resistance, the voltage present at the output pf the VRM might
drop. However, because plane layers have relatively low resistance, this lower VRM
output voltage might not affect the DC drop across the plane layer by a noticeable
amount.

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HyperLynx PI PowerScope Dialog Box

HyperLynx PI PowerScope Toolbar

Use the toolbar to enable turn, zoom, and other view-enhancement features. The Inspect button
displays numerical results when you point to the simulation results shape.

Figure 33-67. HyperLynx PI PowerScope Toolbar

Table 33-49. HyperLynx PI PowerScope Toolbar Contents

Button Description
Turn Drag in the results display to rotate simulation results.

The rotation axis is in the center of the maximum X/Y extents of the
simulated geometries.

Restriction: This mode is unavailable when top view is enabled.

Pan Drag in the results display to move simulation results without zooming
or rotating.

Keyboard shortcut: Press Shift to enable.

Zoom Drag up to zoom out. Drag down to zoom in or use the mouse wheel to
zoom in and out

Keyboard shortcut: Press Alt to enable.

Inspect Point to a shape to display X/Y coordinates and numerical simulation
results values in a ToolTip.

Keyboard shortcut: Press Ctrl to enable.

Default View Restore initial rotation and zoom.

2D, Top View Change the view from 3D to 2D and display the top of the board.
Only

Fit to View Resize the results so they fit on the screen.

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HyperLynx PI PowerScope Dialog Box

HyperLynx PI PowerScope Results and Maximum Result Areas

The results display contains three-dimensional plane geometries, where color, height, and other
graphical indicators provide simulation results. For plane noise and decoupling capacitor
analysis, the simulation results represent the voltage difference between the two metal regions
that form the transmission plane.
In addition, you can overlay modeling and simulation results. See Grid, TPlane model, and
Meshes model in Table 33-52 on page 1716.
The maximum noise voltage (plane noise simulation) and DC drop voltage and current density
(DC drop simulation) are reported to the right of the legend. The format of the numerical results
depends on the following simulation types:
• Plane noise— The HyperLynx PI PowerScope displays the maximum noise voltage for
the overall simulation if you enable the Show Maximums option in Table 33-52 on
page 1716. The HyperLynx PI PowerScope displays the minimum and maximum noise
voltages at the simulation end time if you disable the option.
• DC drop
o DC drop voltage—Displays the sum of maximum DC drop voltages across all
stackup layers followed by the individual stackup layer with the maximum DC drop
voltage drop.
o DC current density—Displays the sum of maximum current densities across all
stackup layers followed by the individual stackup layer with the maximum DC drop
voltage drop.
The HyperLynx PI PowerScope hides numerical values if you clear the check box for a layer
and click the layer name. See Figure 33-68. While this figure shows DC drop results, the
PowerScope behaves similarly for plane noise when you clear check boxes in the T-Plane list.

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Dialog Boxes
HyperLynx PI PowerScope Dialog Box

Figure 33-68. Hidden Numerical DC Drop Maximum Value

Tip: The results display contains approximate plane geometries, but simulation uses
precise geometries. This enables fast rotating, zoom, and panning of the results image.

HyperLynx PI PowerScope Legend

The legend maps the color of the graph to numeric simulation results.
If you rerun simulation, the legend on the compare tab displays legends for both the latest and
previous results. See Figure 33-69 on page 1713.

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 Dialog Boxes
HyperLynx PI PowerScope Dialog Box

Figure 33-69. Legend with Last and Previous Columns - HyperLynx PI

PowerScope Contents

HyperLynx PI PowerScope Controls

Use controls to change the contents of the simulation results display and to run plane noise
simulation.
Click the Positioning Options, Visual Options, and Layer/T-Plane Options buttons to display
one group of controls at a time.
The HyperLynx PI PowerScope contains the following groups of controls (see HyperLynx PI
PowerScope Controls):
• Plane Noise Simulation Options
• Positioning Options
• Visual Options
• T-Plane/Layer Options
• General Options

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Dialog Boxes
HyperLynx PI PowerScope Dialog Box

Figure 33-70. HyperLynx PI PowerScope Controls

Plane Noise
Simulation Options
General Options

Positioning Options Visual Options

T-Plane/Layer Options

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 Dialog Boxes
HyperLynx PI PowerScope Dialog Box

Plane Noise Simulation Options

Table 33-50. HyperLynx PI PowerScope Controls - Plane Noise Simulation

Options
Control Description
<multiple_labels>| The button label depends on this simplified sequence:

Start Simulation Start Simulation > [Pause | Stop] > [Restart Simulation |
Restart Simulation Resume Simulation]
Resume Simulation • Click Start Simulation to launch the initial plane
Pause noise simulation.
Stop • Click Restart Simulation to launch subsequent
simulations, starting at time zero.
• Click Resume Simulation to resume a paused
simulation.

Restriction: These controls are available only for plane

noise simulation.
Time When simulation is running, this displays the current
simulation time.
Stop Specify the simulation time for plane-noise simulation.

The default stop time is usually adequate for AC models

with a rising edge or single pulse current waveform.
However if you repeat the stimulus, specify an initial
delay or wide pulse, or specify double pulses, you may
need to increase the stop time to make sure simulation
reports the maximum-amplitude plane noise. See “Assign
Power Integrity Models Dialog Box - IC Tab” on
page 1456.

The value in the Stop box has precedence over the period
length (for pulse signal types) in the AC model. For
example, if the AC model contains a repeating current
waveform that extends beyond the simulation time, the
current waveform is truncated.

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Dialog Boxes
HyperLynx PI PowerScope Dialog Box

Positioning Options

Table 33-51. HyperLynx PI PowerScope Controls - Positioning Options Area

Control Description
Span Edit the vertical scale of the results display. Drag the
slider to quickly edit the value. If you type a value, click
outside the box to update the results display.

Restriction: This item is unavailable if the Auto Span &

Origin option is enabled.
Origin Edit the vertical offset of the results display. Drag the
slider to quickly edit the value. If you type a value, click
outside the box to update the results display.

Restriction: This item is unavailable if the Auto Span &

Origin option is enabled.
Auto span & origin Display the full extents of simulation results by
automatically changing span and origin values.

When DC drop simulation results includes two or more

stackup layers, this option can make it difficult to see
relatively low-amplitude measurements. In this case,
consider displaying only one stackup layer at a time. See
Layer list in Table 33-53 on page 1719.
Thresholds (1, 2) Add horizontal reference planes to the results display, to
help you see simulation values that exceed a limit. Drag
the slider to quickly edit the value. If you type a value,
click outside the box to update the results display.
Visual Options

Table 33-52. HyperLynx PI PowerScope Controls - Visual Options Area

Control Description
Show Area
Solid fill Display simulation results in the form of a solid sheet.
Wireframe Display simulation results in the form of grid lines.
Hide invisible Do not display regions of the reference threshold planes
that are located “behind” the simulation results surface.

Restriction: This item is available only when the

Wireframe option is enabled and when the Solid Fill
option is disabled.
Background Color --

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 Dialog Boxes
HyperLynx PI PowerScope Dialog Box

Table 33-52. HyperLynx PI PowerScope Controls - Visual Options Area

Control Description
Model view Area
Grid The visible grid and simulation grid may be different.
• FDTD (AC simulations)— Visible grid equals
simulation grid.
• FEM (DC drop)—Visible grid does not equal
simulation grid. Simulation grid is much finer,
especially at the end of simulation.
TPlane model Displays board outline (as red/green rectangle) and model
ports (pins and vias) as small circles.

The top surface of the transmission-plane model is red and

the bottom is green.

Circles indicate where sink and source models attach to

the transmission-plane model.
Meshed model Displays squared copper outline and model ports.
Graph type Area
DC Drop Voltage Display simulation results as a three-dimensional surface,
whose height is determined by voltages across the plane
geometries.

Restriction: This item is available only for DC drop

simulation.
DC Current Display simulation results as two-dimensional vectors,
Distribution whose length indicate current magnitude and whose angle
indicates current flow direction.

To see the origins of the vectors, select the Meshed

model check box.

Restriction: This item is available only for DC drop

simulation.
DC Current Display simulation results as a three-dimensional surface,
Density whose height is determined by current flow across the
plane geometries.

Restriction: This item is available only for DC drop

simulation.

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HyperLynx PI PowerScope Dialog Box

Table 33-52. HyperLynx PI PowerScope Controls - Visual Options Area

Control Description
Noise voltage Display simulation results as a three-dimensional surface,
whose height is determined by voltages across the plane
geometries.

Restriction: This item is available only for plane noise

simulation.
Surface and Display simulation results as two-dimensional vectors,
capacitor currents whose length indicate current magnitude and whose angle
indicates current flow direction.

To see the origins of the vectors, select the Meshed

model check box.

Restriction: This item is available only for plane noise

simulation.
Surface currents Display simulation results as a three-dimensional surface,
whose height is determined by the amount of current
flowing across the plane geometries.

Restriction: This item is available only for plane noise

simulation.
Show maximums Display maximum amplitude result (Z axis) for every X/Y
location on the three-dimensional surface over the entire
simulation.

Restriction: This item is unavailable for DC drop

simulation and when a .TPS file is loaded into the
HyperLynx PI PowerScope.

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HyperLynx PI PowerScope Dialog Box

T-Plane/Layer Options

Table 33-53. HyperLynx PI PowerScope Controls - T-Plane/Layer List Options

Area
Control Description
Layer list Display geometries on specific stackup layers. Clear the
check box to hide geometries for that layer.

For DC drop, “<REF>” indicates the stackup layer is

automatically brought into simulation because it is a
reference net for another stackup layer being simulated.
The algorithm relies on reference nets assigned to VRM
models on IC power-supply pins. See Assign Power
Integrity Models Dialog Box - IC Tab.
Check All Display simulation results for all stackup layers.
Uncheck All Display simulation results for no stackup layers.
General Options

Table 33-54. HyperLynx PI PowerScope Controls - General Options

Control Description
Save Save numerical data from the simulation to a .TPS file.
Span, origin, and other results display options have no
effect on the contents of the file.

.TPS files are located in the <design> folder unless you

have previously saved them to another location. See
“About Design Folder Locations” on page 1391.

For plane-noise and decoupling-capacitor simulations, the

.TPS file contains information for one transmission-plane.
If multiple transmission planes exist, click the
transmission-plane tab (such as 2-3 or 3-4) to choose
which set of data to save to the .TPS file.

During plane-noise and decoupling-capacitor simulations,

the HyperLynx PI PowerScope displays the time-
dependent results in a movie-like form. However, the
.TPS file contains only one set of simulation results (and
not a movie).

If you enable the Show Maximums option (Table 33-52

on page 1716), the .TPS file contains the maximum
amplitude results instead of the last results in the
simulation.

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HyperLynx PI PowerScope Dialog Box

Table 33-54. HyperLynx PI PowerScope Controls - General Options

Control Description
Load Load a previously-saved .TPS file to a new “loaded” tab.

.TPS files are located in the <design> folder unless you

have previously saved them to another location. The
HyperLynx PI PowerScope automatically opens the folder
containing the last-opened .TPS file. See “About Design
Folder Locations” on page 1391.
Copy Save the results display to the Windows clipboard. You
can then paste the contents of the clipboard to a suitable
application, such as Microsoft Word or Wordpad.

Restriction: This button has no effect when the computer

runs Linux or UNIX.
Print --
Close --
Help --

Related Topics
“Simulating Plane Noise” on page 1037
“Simulating DC Voltage Drop” on page 963
“Example DC Drop Simulation Results” on page 1002
“Overlapping Anti-Pads That Isolate Metal Shapes” on page 1395
“PowerScope Hides Some Shapes for DC Drop” on page 985

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 Dialog Boxes
HyperLynx SI Eye Density Viewer

HyperLynx SI Eye Density Viewer

To access: The HyperLynx SI Eye Density Viewer opens automatically when you enable BER
plots on the “FastEye Channel Analyzer - View Analysis Results Page” on page 1628 or
“IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page” on page 1756, and
then click Save & Run.
Description
Use this dialog box to display eye density and bit error rate (BER) plots for FastEye and IBIS-
AMI channel analysis.

Figure 33-71. HyperLynx SI Eye Density Viewer - Part 1

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Dialog Boxes
HyperLynx SI Eye Density Viewer

Figure 33-72. HyperLynx SI Eye Density Viewer - Part 2

The HyperLynx SI Eye Density Viewer contains the following areas:

• “HyperLynx SI Eye Density Viewer Tabs” on page 1723
• “HyperLynx SI Eye Density Viewer Toolbar” on page 1723
• “HyperLynx SI Eye Density Viewer Comment Field” on page 1724

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HyperLynx SI Eye Density Viewer

• “HyperLynx SI Eye Density Viewer Legend” on page 1724

• “HyperLynx SI Eye Density Viewer Resolution” on page 1724
• “HyperLynx SI Eye Density Viewer Controls” on page 1724
HyperLynx SI Eye Density Viewer Tabs
After running multiple simulations, multiple tabs exist to contain the results. Click the tab to
display the contents for a specific simulation.
A tab can be hidden if there are many tabs (from multiple simulations) or the tabs are very wide
because the probe name is long. To display a hidden tab, use the left/right arrow buttons .
When there are multiple tabs, the close button becomes available to close a specific tab.
HyperLynx SI Eye Density Viewer Toolbar
Use the toolbar to enable turn, zoom, and other view-enhancement features. The Inspect button
displays numerical results when you point to the simulation results shape.

Figure 33-73. HyperLynx SI Eye Density Viewer Toolbar

Table 33-55. HyperLynx SI Eye Density Viewer Toolbar Contents

Button Description
Turn Drag in the results display to rotate simulation results.

The rotation axis is in the center of the maximum X/Y extents of the
simulated geometries.

Restriction: This mode is unavailable when top view is enabled.

Pan Drag in the results display to move simulation results without zooming
or rotating.

Keyboard shortcut: Press Shift to enable.

Zoom Drag up to zoom out. Drag down to zoom in or use the mouse wheel to
zoom in and out

Keyboard shortcut: Press Alt to enable.

Inspect Point to a shape to display X/Y coordinates and numerical simulation
results values in a ToolTip.

Keyboard shortcut: Press Ctrl to enable.

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Dialog Boxes
HyperLynx SI Eye Density Viewer

Table 33-55. HyperLynx SI Eye Density Viewer Toolbar Contents (cont.)

Button Description
Default View Restore initial rotation and zoom.

3-D / 2D, Top Change the view from 3D to 2D and display the top of the board.
View Only

Fit to View Resize the results so they fit on the screen.

HyperLynx SI Eye Density Viewer Comment Field

Optionally, type text into the Comment field. This text appears near the top of the simulation
results plot when you save it to the clipboard or print it.
HyperLynx SI Eye Density Viewer Legend
Use the legend to map the color of the simulation results to the BER.
To use the same color gradients for both eye density and BER plots, the eye density results are
normalized. BER is a measure of probability and its value is below 1 at any point in the plot. To
also normalize eye density results to 1, the HyperLynx SI Eye Density Viewer viewer does the
following:
1. For each pixel (or element of the matrix accumulator), count the number of times a
waveform trace crosses it.
2. When simulation is complete, find the pixel with the largest number of waveform
crossings and assign the number of waveform crossings to MaxCrossings.
3. For each pixel, divide the number of waveform crossings by MaxCrossings.
HyperLynx SI Eye Density Viewer Resolution
These values show the color grade resolution and vertical (that is, voltage) grid resolution.
The Min and Max values represent the base 10 logarithm of the BER. For example, if Min = -10
and Max = 0, the minimum BER is 1e-10 and the maximum BER is 0.
Vstep represents the vertical (that is, voltage) resolution. The vertical scale is determined
automatically and is based on the voltage swing. Vstep is a ratio of the voltage swing to the
number of points representing eye/BER matrix in vertical direction. The HyperLynx SI Eye
Density Viewer supports 601 points in vertical direction, so the voltage range is +/- 300 * Vstep.
HyperLynx SI Eye Density Viewer Controls
Use controls to change the contents of the simulation results display.

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HyperLynx SI Eye Density Viewer

Click the Positioning Options or Plot List button to display one group of controls at a time.
The HyperLynx SI Eye Density Viewer contains the following groups of controls:
• Positioning Options
• Plot List
• Appearance

Figure 33-74. HyperLynx SI Eye Density Viewer Controls

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Dialog Boxes
HyperLynx SI Eye Density Viewer

Positioning Options

Table 33-56. HyperLynx SI Eye Density Viewer Contents - Positioning Options

Area
Control Description
UI and voltage scale Area
UI X-axis scale. 1 unit interval = 1 bit interval.
Voltage Y-axis scale.
Auto fit to window Scales the simulation results to fit in the window.
Range Area
Zoom Zoom scale.
Move Defines the lowest BER value to display. Values below this will
not display.
Auto range Automatically scale the zoom scale and data range to fit the results
to the screen.
Thresholds(1,2) Select to add horizontal reference planes to the results display, to
help you see simulation values that exceed a limit. Drag the slider
Available only in 3-D to quickly edit the value. If you type a value, click outside the box
view. See HyperLynx to update the results display.
SI Eye Density Viewer
Toolbar.
Plot List

Table 33-57. HyperLynx SI Eye Density Viewer Contents - Plot List Area
Control Description
Graph type • Eye Density — Displays the density of traces in an eye
diagram.
• Bit Error Rate — Displays the BER.
Plot list Contains a list of data sets to display. Select the data set to display.
Check All Select all data.
Uncheck All Clear all data selections.
Appearance

Table 33-58. HyperLynx SI Eye Density Viewer Contents - Appearance Area

Control Description
Coordinate grid Area

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 Dialog Boxes
HyperLynx SI Eye Density Viewer

Table 33-58. HyperLynx SI Eye Density Viewer Contents - Appearance Area

Control Description
Show grid Select to overlay the graph with a grid, where UI is on the X axis
and voltage is on the Y axis.

UI Drag the slider to change the distance among the horizontal lines.

Restriction: This option is unavailable unless you enable Show

grid. Note that the numerical box is always readonly.
Voltage Drag the slider to change the distance among the vertical lines. The
numerical box is always readonly.

Restriction: This option is unavailable unless you enable Show

grid. Note that the numerical box is always readonly.
Eye mask Area
Show eye mask Select to overlay the graph with an eye mask.
Configure Click to open the Configure Eye Diagram dialog box and load a
pre-defined eye mask or edit the current eye mask.

Related Topics
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

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Dialog Boxes
HyperLynx SI Eye Density Viewer

“Simulating Signal Integrity with FastEye Channel Analysis” on page 629

“FastEye Channel Analyzer - View Analysis Results Page” on page 1628
“IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page” on page 1756

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Choose New/Saved Analysis Page

IBIS-AMI Channel Analyzer Wizard - Choose New/Saved

Analysis Page
To access: Select Simulate SI > Run IBIS-AMI Channel Analysis and select the Choose
New/Saved Analysis page
Use this page to start an all-new IBIS-AMI channel analysis, load wizard settings from a
previous analysis, and save wizard settings to a file.
Note
Wizard settings include the channel-characterization fitted-poles (.PLS) file and probe
location for a specific LineSim schematic or BoardSim selected net. If you load settings
for a different schematic or selected net, be sure to check the Loaded File and Receiver-
model input values on the IBIS-AMI Channel Analyzer Wizard - Set Up Channel
Characterizations Page.

The IBIS-AMI Channel Analyzer wizard saves its settings to the .FEW file, which is located in
the design folder unless you specify another location. If you run channel characterization, the
wizard also saves the .PLS file to the design folder. See “About Design Folder Locations” on
page 1391.

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Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Choose New/Saved Analysis Page

Figure 33-75. IBIS-AMI Channel Analyzer Wizard - Choose New/Saved Analysis

Page

Table 33-59. IBIS-AMI Channel Analyzer Wizard - Choose New/Saved Analysis

Page Contents
Option Description
New Start a new analysis using default wizard settings.

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Choose New/Saved Analysis Page

Table 33-59. IBIS-AMI Channel Analyzer Wizard - Choose New/Saved Analysis

Page Contents (cont.)
Option Description
Use last configuration Load settings from memory. Wizard settings are stored in
memory until you close HyperLynx.

Loading settings from memory may be useful when analyzing

similar structures, such as different instances of a channel.
Load saved configuration Click Load to browse to a wizard settings file (.FEW).

Loading previously-saved settings may be useful when

analyzing similar structures, such as different instances of a
channel, or to reproduce previous analysis results. After loading
the saved settings, you can edit wizard options and save them to
another file.
Save settings to file Select Save settings to file and click Browse to save wizard
settings to a new or existing file.

Note: This option is disabled every time you re-open the

wizard.

Selecting this option causes the button labels Save & Run and
Save & Exit to display near the bottom of the wizard page.
Deselecting this option causes the button labels Run and Exit to
display.

Related Topics
“IBIS-AMI Channel Analysis QuickStart” on page 612
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

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Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Configure AMI Models Page

IBIS-AMI Channel Analyzer Wizard - Configure AMI Models

Page
To access: Select Simulate SI > Run IBIS-AMI Channel Analysis and select the Configure
AMI Models page
Use this page to confirm model assignments or manually assign .AMI and .DLL (for Windows)
or .so (for Linux) files to the channel driver and receiver, and to configure .AMI file parameters.
Caution
If the Tx and Rx AMI models contain different ignore bit values, the wizard uses the
larger value.

Figure 33-76. IBIS-AMI Channel Analyzer Wizard - Configure AMI Models Page

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Configure AMI Models Page

Table 33-60. IBIS-AMI Channel Analyzer Wizard - Configure AMI Models Page
Contents
Option Description
Assign AMI Files Opens the AMI File Assignment Dialog Box so you can assign .AMI
and .DLL/.so files to transmitter and receiver pins.

If you assign IBIS models containing [Algorithmic Model] keywords

to the channel driver and receiver ICs, you can override the
assignments. The wizard settings file (.FEW) stores your changes, not
the IBIS model.
Configure Tx AMI Displays the transmitter IBIS-AMI model in the IBIS AMI Parameter
Editor.

Restriction: This button is unavailable until you assign an IBIS-AMI

model to the transmitter.
Configure Rx AMI Displays the receiver IBIS-AMI model in the IBIS AMI Parameter
Editor.

Restriction: This button is unavailable until you assign an IBIS-AMI

model to the receiver.
Edit Tx AMI DLL Display and edit the string sent to the .DLL or .so file for the
String transmitter. Edit the string to fix syntax problems, such as the usage of
quotes that do not follow the syntax in the IBIS specification.

The string consists of .AMI file parameters of the (Usage In) and
(Usage InOut) types. The string includes values of form
(<branch_name> <selected _value>). For example, (AMI_Tx
(Tx_Strength 0)(Tx_Equalization 0)(Process 0)).

Caution: Your transmitter string edits are lost when you assign
different .AMI or .DLL/.so files or reconfigure the .AMI file for the
transmitter.

Restriction: This button is available when you enable Enable AMI

DLL string editing in the Preferences Dialog Box - Advanced Tab.

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Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Configure AMI Models Page

Table 33-60. IBIS-AMI Channel Analyzer Wizard - Configure AMI Models Page
Contents (cont.)
Option Description
Edit Rx AMI DLL Display and edit the string sent to the .DLL/.so file for the receiver.
String Edit the string to fix syntax problems, such as the usage of quotes that
do not follow the syntax in the IBIS specification.

The string consists of .AMI file parameters of the (Usage In) and
(Usage InOut) types. The string includes values of form
(<branch_name> <selected _value>). For example, (AMI_Rx
(Process 0)(Rx_Bias_Mode 0)(Rx_Equalization 0)).

Caution: Your receiver string edits are lost when you assign different
.AMI or .DLL/.so files or reconfigure the .AMI file for the receiver.

Restriction: This button is available when you enable Enable AMI

DLL string editing in the Preferences Dialog Box - Advanced Tab.

Related Topics
“IBIS-AMI Channel Analysis QuickStart” on page 612
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Define AMI Stimulus Page

IBIS-AMI Channel Analyzer Wizard - Define AMI Stimulus

Page
To access: Select Simulate SI > Run IBIS-AMI Channel Analysis and select the Define
Stimulus page
Use this page to specify the stimulus to apply to the channel during IBIS-AMI channel analysis.

Figure 33-77. IBIS-AMI Channel Analyzer Wizard - Define AMI Stimulus Page

Table 33-61. IBIS-AMI Channel Analyzer Wizard - Define AMI Stimulus Page
Contents
Option Description
Total number of bits At a minimum, specify a sufficient number of bits for the transmitter and
to simulate receiver to exhibit all algorithmic behaviors, such as equalization
adjustments, clock and data recovery, and so on.

The wizard automatically calculates how many times to repeat the bit
pattern to achieve the total number of bits to simulate. The wizard
truncates the final bit pattern repetition, if needed, to simulate exactly the
number of bits you specify here.

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Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Define AMI Stimulus Page

Table 33-61. IBIS-AMI Channel Analyzer Wizard - Define AMI Stimulus Page
Contents (cont.)
Option Description
Bit interval When choosing between the Bit Interval and Bit Rate properties, use the
one that provides the best accuracy. For example, to test the channel at
Bit rate
333 Mbps, you can specify a bit rate of 0.333 Gbps instead of a bit
interval of 3.00300300300 ns. Editing the Bit Interval value updates the
Bit Rate value, and vice versa.

The values may have been previously set by any of the following
sources, sorted in descending priority:
1. The Bit interval and Bit rate values in the Channel Characterization
Dialog Box.
2. The fitted-poles (.PLS) file used to characterize the channel and
loaded on the IBIS-AMI Channel Analyzer Wizard - Set Up Channel
Characterizations Page. The .PLS file contains a comment that
specifies the bit interval.
3. The Bit interval and Bit rate values used for standard eye diagrams
and specified in the Stimulus tab of the Configure Eye Diagram
dialog box. See “Setting Up Global Stimulus for Standard-Eye
Diagrams” on page 541.
Bit pattern Area
Type Select either of the following types of bit patterns:
• PRBS—Pseudorandom binary sequence of bits
• 8B/10B—Randomly-generated sequence of characters that obey the
signaling protocol
Bit order Select the bit order to determine the number of bits in the PRBS
sequence. The number of bits is .

For example, if the bit order is 6, the number of bits is 63 .

Restriction: This option is unavailable if you select 8B/10B in the Type

list.
Eye stress Area
Stress eye by Select this option to automatically create the worst-case bit sequence that
periodically closes the eye the most and insert it periodically into the overall bit
inserting worst- pattern. Selecting this option adds very little to the overall run time.
case patterns into
simulation See “Worst-Case Bit Patterns - IBIS-AMI” on page 1737.
stimulus

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IBIS-AMI Channel Analyzer Wizard - Define AMI Stimulus Page

Table 33-61. IBIS-AMI Channel Analyzer Wizard - Define AMI Stimulus Page
Contents (cont.)
Option Description
Insert worst-case Type the number of bits in a PRBS or 8B/10B bit sequence to run before
pattern after inserting a worst-case bit pattern.
every
Transmitters and receivers can adjust equalization, clock and data
recovery, and other signal processing behaviors as simulation progresses,
so the analysis engine recalculates the worst-case bit sequence prior to
each insertion into the overall bit sequence.

The value range is 30 to 100, in thousands of bits.

Restriction: This option is unavailable unless you select Stress eye by

periodically inserting worst-case patterns into simulation stimulus.
Advanced Area
Default Select to apply the default value to the Number of bits per call to AMI
DLL option.
Samples per bit This value affects the following:
interval • Granularity of the analysis.
• Resolution of eye diagram contours and bit error rate (BER) plots
displayed in the HyperLynx SI Eye Density Viewer.

Note: Powers-of-2 values are safest, such as 32 (that is, 25). Some AMI
models fail and return strange results when using non-power-of-2 values,
even though the AMI specification requires support for all values.

Large numbers can slow analysis.

The value range is 4 to 511.

Number of bits Select the number of stimulus bits to send as a block to the AMI
per call to AMI .DLL/.so. You might change this value when advised by the model
DLL creator to optimize interaction with certain AMI .DLL or .so files.

The value range is 1 to 20, in thousands of bits.

Worst-Case Bit Patterns - IBIS-AMI

IBIS-AMI channel analysis can create the worst-case bit sequence that closes the eye the most.
This feature can help you avoid having to run simulations with 1e12-1e15 bits to evaluate rarely-
occurring ISI effects.
This feature uses the waveform simulator to periodically extract the pulse-response from the
receiver decision point, create the worst-case bit pattern from it, and then apply the worst-case
bit pattern. The normal PRBS or 8B/10B stimulus you specify resumes when the worst-case bit
sequence finishes.

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IBIS-AMI Channel Analyzer Wizard - Define AMI Stimulus Page

The extracted pulse response may not be valid after a few thousand bits because the algorithmic
model settings for Tx and Rx pins can change. Prior to inserting the worst-case bit sequence,
IBIS-AMI channel analysis extracts a new pulse response waveform and recalculates the worst-
case bit sequence.
IBIS-AMI channel analysis can create the following types of worst-case bit patterns:
• Pseudorandom bit sequence (PRBS)—Sequence of bits
• 8B/10B—Sequence of characters that complies with the encoding protocol
Related Topics
“IBIS-AMI Channel Analysis QuickStart” on page 612
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Review Simulation Sweeps Page

IBIS-AMI Channel Analyzer Wizard - Review Simulation

Sweeps Page
To access: Select Simulate SI > Run IBIS-AMI Channel Analysis and select the Review
Simulation Sweeps page
Use this page to display the combination of model parameter values for each sweep simulation,
to optionally stop sweep simulations if a simulation fails, and to report failed simulations.
Restriction: This page is unavailable if you do not specify a sweep range in the IBIS-AMI
Channel Analyzer Wizard - Sweep AMI Model Settings Page.

Figure 33-78. IBIS-AMI Channel Analyzer Wizard - Review Simulation Sweeps

Page

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Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Review Simulation Sweeps Page

Table 33-62. IBIS-AMI Channel Analyzer Wizard - Review Simulation Sweeps

Page Contents
Option Description
Spreadsheet Displays the combination of model parameter values for each
simulation.

The spreadsheet displays the parameter values within double

quotes. Those values map to spreadsheet rows in the Sweeping
Dialog Box.

An exclamation mark ! in the first column identifies a failing

sweep simulation. Point to the exclamation mark ! to display a
ToolTip with more information regarding the error.
Stop sweeping if error Enable to stop all sweep simulations if a simulation error occurs.
occurs This capability enables you to investigate the failing simulation
when it happens, instead of waiting for the remaining sweep
simulations, which may also have errors, to finish.
Simulation quantity or status Displays either of the following:
• Before simulation—The number of simulations that will run,
based on the sweep ranges you have defined and enabled.
• During and after simulation—The number of simulations that
have completed and a count of the failed simulations.
See “IBIS-AMI Sweep Simulation Calculations” on page 626.

Related Topics
“IBIS-AMI Channel Analysis QuickStart” on page 612

1740 BoardSim User Guide, v8.2

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Review Simulation Sweeps Page

“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

BoardSim User Guide, v8.2 1741

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Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Set Up Channel Characterizations Page

IBIS-AMI Channel Analyzer Wizard - Set Up Channel

Characterizations Page
To access: Select Simulate SI > Run IBIS-AMI Channel Analysis and select the Set Up
Channel Characterizations page
Use this page to set up simulation to create a new analog channel characterization, create
optional crosstalk files, or load existing characterization or crosstalk files.
The channel characterization file provides channel behavior from the analog buffer for the
transmitter, through the passive interconnect, to the analog buffer for the receiver. See “IBIS-
AMI Channel Analysis Overview” on page 617.
Note
Wizard settings include the channel-characterization file and probe location for a specific
LineSim schematic or BoardSim selected net. If you load settings for a different
schematic or selected net, be sure to update the Loaded and probe-related options on this
page.

Figure 33-79. IBIS-AMI Channel Analyzer - Set Up Channel Characterizations

Page

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Set Up Channel Characterizations Page

Table 33-63. IBIS-AMI Channel Analyzer - Set Up Channel Characterizations

Page Contents
Option Description
Transmitter probe, Receiver probe Areas
Pin Differential or single-ended channel pin to probe.

If an expected differential probe does not appear, manually

create a differential probe with the oscilloscope. See
“Manually Creating Differential Probes with the
Oscilloscope” on page 1621.

You can run IBIS-AMI channel analysis for one single-ended

or differential channel at a time.
Probe locations Area
Location Probe location. See “Locating Probes at the Die or Pin” on
page 555.
Signal (victim) channel characterization Area
New/View Open the Channel Characterization Dialog Box to do either
of the following:
• Set up simulation properties for a new channel
characterization.
• View channel characterization waveforms manually
created from the Channel Characterization Dialog Box or
automatically created when you run analysis to
completion.
New Create a new channel characterization when you run channel
analysis.

Clicking New deletes from memory a previous channel

characterization.

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IBIS-AMI Channel Analyzer Wizard - Set Up Channel Characterizations Page

Table 33-63. IBIS-AMI Channel Analyzer - Set Up Channel Characterizations

Page Contents (cont.)
Option Description
Use last Use a previous channel characterization that is still in
memory.

You might use this option when using the same channel
topology and probe locations with different analysis settings.

This option is unavailable if you do any of the following:

• Change the net topology, such as editing stackup layer
properties or the probe location
• Select another net (BoardSim only)
• Click New
• Close HyperLynx

Enabling this option makes unavailable nearly all the other

options on this page.
Loaded Browse to an existing fitted-poles (.PLS) or S-parameter file
Load (.S2P, .S4P) that contains results from a previous channel
characterization. See “External Analog Channel
Characterization Files” on page 1621.

Enabling this option makes unavailable nearly all the other

options on this page.
Include crosstalk effects from Channel characterization includes the crosstalk effects from
aggressor channels nearby aggressor channels/nets.

If you do not see any aggressors in the spreadsheet, some

likely causes are:
• None of the aggressors have enabled transmitter/driver
pins
• In BoardSim, none of the aggressors exceed the crosstalk
threshold
• You have not loaded any optional external crosstalk files

Restriction: The Crosstalk license is required to run

crosstalk simulation.

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Set Up Channel Characterizations Page

Table 33-63. IBIS-AMI Channel Analyzer - Set Up Channel Characterizations

Page Contents (cont.)
Option Description
Allow external aggressor Optionally, add crosstalk effects on the victim channel
channels receiver from a channel or net that you have characterized
outside of the wizard.

You might use this capability to use crosstalk files that

represent channel behavior measured on PCB hardware.

See “External Aggressor Channel Characterization Files” on

page 1622.
Aggressor channel driver default Area
Victim channel driver default Area
Inactive stuck state The default value to use in the spreadsheet.

See Aggressor and Victim.

Spreadsheet columns
Notes:
• The spreadsheet contains a row for each aggressor channel/net in the design with the
transmitter/driver set to output. Aggressors are characterized one at a time.
• BoardSim identifies an aggressor channel/net when it exceeds the crosstalk threshold you
set.
• LineSim identifies an aggressor channel/net when it is part of the same coupling region as
the victim channel.
• If spreadsheet cells are not visible, you can either make the dialog box larger or drag the
scroll bars.
Enable Select to either use the channel as an aggressor to or to
receive actions from the Characterize Selected or Display
Selected buttons.

This option links to the same option on the FastEye Channel

Analyzer - Set Up Crosstalk Analysis Page.

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Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Set Up Channel Characterizations Page

Table 33-63. IBIS-AMI Channel Analyzer - Set Up Channel Characterizations

Page Contents (cont.)
Option Description
Name Reference designator, pin name, and probe location for an
aggressor transmitter/driver IC pin.

The Location option determines the probe location.

Aggressor The transmitter/driver state to apply to the aggressor when it
is not being characterized. Aggressors are characterized one
a time, so if the design contains aggressors A and B,
aggressor A is set to the selected inactive state when
aggressor B is characterized.

If the value is Default, use the Inactive stuck state option

value.

For information about the role of “stuck” states in crosstalk

simulation, see “Importance of Modeling Drivers on Victim
Nets as Stuck High or Stuck Low - BoardSim”.
Victim The transmitter/driver state to apply to the victim when an
aggressor is being characterized.

If the value is Default, use the Inactive stuck state option

value.
Path Location of the file representing the crosstalk received at the
victim receiver pin and caused by a transmitter/driver
switching high or low to create a step response.

Click the cell to browse to the file.

Running analysis to completion automatically characterizes

aggressor channels internal to the design.

For external aggressor channels, you can specify SPICE

(.LIS), fitted-poles (.PLS), or Touchstone (.S2P, .S4P) files.
To delete the path to an external aggressor channel file, right-
click the cell and click Yes.

For external file requirements, see “External Aggressor

Channel Characterization Files” on page 1622.

Point to the cell with the mouse to display a ToolTip

containing the full file path.

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Set Up Channel Characterizations Page

Table 33-63. IBIS-AMI Channel Analyzer - Set Up Channel Characterizations

Page Contents (cont.)
Option Description
Port Map Click to select a port mapping for an S-parameter file.

L and R represent ports on the left and right sides of the

simulation symbol. For example, L13R24 means that ports 1
and 3 are on the left side and ports 2 and 4 are on the right
side. See “S-Parameter Port Numbering” on page 1066.

Restriction: This cell does not display port-mapping options

when you load a fitted-poles model or .LIS file in the Path
cell because they have known port mapping.
Characterize Selected Optionally, characterize a single aggressor crosstalk channel.
Aggressor channel characterization is done automatically
when you run analysis, but you may want to do this manually
to investigate the crosstalk contribution of a specific channel.

Restriction: This button is unavailable unless you enable a

spreadsheet row.
Display Selected Optionally, after you manually characterize an aggressor
crosstalk channel, you can display it.

Restriction: This button is unavailable unless you enable a

spreadsheet row.
Characterize All Optionally, characterize all the aggressor crosstalk channels.
Aggressor channel characterization is done automatically
when you run analysis, but you may want to do this manually
to investigate the crosstalk contribution of one or more
specific channels.
+ Channel Add a new spreadsheet row to add crosstalk effects on the
victim channel receiver from a channel or net that you have
characterized outside of the wizard.

You might use this capability when running channel analysis

from a set of S-parameter files that represent channel
behavior measured on PCB hardware.

Restriction: This option is unavailable if Allow external

aggressor channel is disabled.
- Channel Remove the selected spreadsheet row for a channel or net
that you have characterized outside of the wizard.

Restriction: This option is unavailable if Allow external

aggressor channel is disabled.

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IBIS-AMI Channel Analyzer Wizard - Set Up Channel Characterizations Page

Related Topics
“Channel Characterization Dialog Box” on page 1493
“IBIS-AMI Channel Analysis QuickStart” on page 612
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Set Up Crosstalk Analysis Page

IBIS-AMI Channel Analyzer Wizard - Set Up Crosstalk

Analysis Page
To access: Select SI Simulation > Run IBIS-AMI Channel Analysis and select the Set Up
Crosstalk Analysis page
Use this page to set up crosstalk options.
Restrictions:
• This page is unavailable unless you enable Include crosstalk effects from aggressor
channels on the IBIS-AMI Channel Analyzer Wizard - Set Up Channel
Characterizations Page.
• The Crosstalk license is required to run crosstalk simulation.

Figure 33-80. IBIS-AMI Channel Analyzer Wizard - Set Up Crosstalk Analysis

Page

Table 33-64. IBIS-AMI Channel Analyzer - Set Up Crosstalk Analysis Page

Contents
Option Description
Crosstalk timing Area

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IBIS-AMI Channel Analyzer Wizard - Set Up Crosstalk Analysis Page

Table 33-64. IBIS-AMI Channel Analyzer - Set Up Crosstalk Analysis Page

Contents (cont.)
Option Description
Synchronous Victim and aggressor channels are phase locked. There is a
constant phase among transitions for all aggressor and victim
channels.

This option can take into account the effects of many causes of
crosstalk, such as the mutual delays between rising/falling edges
in different channels.
Asynchronous Victim and aggressor channels are not phase locked. There is an
arbitrary phase of transitions among the aggressor and victim
channels.

This option can take into account statistically independent

sources of crosstalk.

Reports only the average crosstalk effect obtained on the final

eye diagram along the unit interval.
Analysis type Area
Time domain Select when the aggressor transmitter/output switching is non-
linear.
Statistical Select when the aggressor transmitter/output switching is linear.
Default stimulus Area—The Default value in the Stimulus column in the spreadsheet
applies values defined in this area.

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Set Up Crosstalk Analysis Page

Table 33-64. IBIS-AMI Channel Analyzer - Set Up Crosstalk Analysis Page

Contents (cont.)
Option Description
Type Select any of the following types of bit patterns:
Parameter • Random—Random binary sequence. Unlike PRBS, a
random bit pattern can produce repeating bit sequences at
any number of bits.

Parameter represents the random seed value, which can be

either of the following:
• <random>—Use to produce random sequences that are
uncorrelated to other random sequences.
• Any positive or negative integer—Use to produce random
sequences that are correlated to other random sequences
using the same seed. You can use the same seed to apply
the same random bit pattern to multiple channels or during
a future analysis session (to reproduce results).
• 8B10B—Randomly-generated 10 bit characters that obey
the signaling protocol.

Parameter represents the random seed value, which can be

either of the following:
• <random>—Use to produce 8B10 character sequences
that are uncorrelated to other random sequences.
• Any positive or negative integer—Use to produce random
sequences that are correlated to other random sequences
using the same seed. You can use the same seed to apply
the same random 8B10B character pattern to multiple
channels or during a future analysis session (to reproduce
results).
• PRBS—Pseudorandom binary sequence that does not repeat
within the number of bits you specify in the Parameter
option.

Parameter is the bit order that determines the number of bits

in the sequence. The number of bits is 2bit order - 1. For
example, if the bit order is 6, the number of bits is 63 (that is,
26 - 1).
• Bit Sequence File—Custom bit sequences loaded from a bit
stimulus (.BIT) file. See “Setting Up Custom Bit Patterns”
on page 548.

Parameter shows the location of the loaded file.

Spreadsheet columns

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Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Set Up Crosstalk Analysis Page

Table 33-64. IBIS-AMI Channel Analyzer - Set Up Crosstalk Analysis Page

Contents (cont.)
Option Description
Notes:
• The spreadsheet contains a row for each aggressor channel/net in the design with the
transmitter/driver set to output. Aggressors are characterized one at a time.
• BoardSim identifies an aggressor channel/net when it exceeds the crosstalk threshold you
set.
• LineSim identifies an aggressor channel/net when it is part of the same coupling region as
the victim channel.
• If spreadsheet cells are not visible, you can either make the dialog box larger or drag the
scroll bars.
Enable Select to use the channel as an aggressor. This option links to
the same option on the IBIS-AMI Channel Analyzer Wizard -
Set Up Channel Characterizations Page.
Name Reference designator, pin name, and probe location for an
aggressor transmitter/driver IC pin.

The Location option on the IBIS-AMI Channel Analyzer

Wizard - Set Up Channel Characterizations Page determines the
probe location.
Stimulus Default applies the stimulus specified in the Default stimulus
Parameter area. There is no Parameter for the Default stimulus type.

You can specify per-channel stimulus. For information about

the stimulus types and parameters, see Type Parameter. Note
that Bit_File in the spreadsheet is the same stimulus type as Bit
Sequence File in the Default stimulus area.

Related Topics
“IBIS-AMI Channel Analysis QuickStart” on page 612
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model Settings Page

IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model

Settings Page
To access: Select Simulate SI > Run IBIS-AMI Channel Analysis and select the Sweep AMI
Model Settings page
Use this page to define the range of AMI model parameters to use during IBIS-AMI channel
analysis. If you do not set a sweep range on this page, simulation uses the single set of
parameters from the IBIS AMI Parameter Editor.
Restrictions:
• This page is unavailable if you have not assigned IBIS-AMI models on the “IBIS-AMI
Channel Analyzer Wizard - Configure AMI Models Page” on page 1732.
• You cannot add a sweep range to single-value parameters. For example, if the .AMI file
contains a parameter defined as (Format Value 0.0), the parameter value is read-only
and you cannot add a sweep range to it. The idea is to use the one value that the model
developer declared to be valid.

Figure 33-81. IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model Settings
Page

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Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model Settings Page

Table 33-65. IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model Settings
Page Contents
Option Description
Parameter tree Displays model parameters and any sweep ranges that you add.

The parameter tree displays some sweep ranges as parameter

values within double quotes. Those values map to spreadsheet
rows in the Sweeping Dialog Box.

Add/Edit Range Opens the Sweeping Dialog Box to create a new or edit an
existing sweep range for the selected parameter tree item.
Remove Range Permanently delete the sweep range from the selected parameter
tree item.

Caution: If you use Paste Range as a Lock and delete the sweep
range for a reference item, the sweep range for dependent items
is also deleted.

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model Settings Page

Table 33-65. IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model Settings
Page Contents (cont.)
Option Description
Copy Range Copies the sweep range from the selected parameter tree item.
Paste Range Pastes the sweep range copied with the Copy Range button to the
selected parameter tree item.

This page prevents you from pasting a sweep range to an

incompatible model parameter. For example, you cannot paste a
sweep range from a transmitter strength item to a clock recovery
reference voltage item.
Paste Range as a Lock Similar to Paste Range, but synchronizes the values of parameter
tree items. For example, if the sweep range that you select and
copy from is the reference item and the sweep range that you
select and paste to is the dependent item. During sweep
simulations, a dependent item always has the same value as the
reference item.
Simulation quantity The number of simulations that will run, based on the sweep
ranges you have defined and enabled.

See “IBIS-AMI Sweep Simulation Calculations” on page 626.

Related Topics
“IBIS-AMI Channel Analysis QuickStart” on page 612
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

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Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page

IBIS-AMI Channel Analyzer Wizard - View Analysis Results

Page
To access: Select Simulate SI > Run IBIS-AMI Channel Analysis and select the View
Analysis Results page
Use this page to run simulation, view simulation results that are still in memory, or load
simulation results that you have manually saved to disk.
To save displayed results to disk, use the save features available from the dialog box that
displays the results. For example, save the BER plot from the HyperLynx SI Eye Density
Viewer.

Figure 33-82. IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page

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 Dialog Boxes
IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page

Table 33-66. IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page
Contents
Option Description
BER plots Display eye density plots or bit error rate plots in the HyperLynx SI
Eye Density Viewer.

BER plots help identify valid data sampling locations by reporting

BER as a function of the sampling location across the unit interval (UI,
same as bit interval) and voltage. The color of the contour indicates its
BER.

Restriction: This option is unavailable when you define and enable a

sweep range on the IBIS-AMI Channel Analyzer Wizard - Sweep AMI
Model Settings Page. However, you can use the HyperLynx IBIS-AMI
Sweeps Viewer to generate BER plots from sweep results.
Bathtub curves Display the Bathtub Chart Dialog Box. Use this dialog box to display
and document bathtub curves. Bathtub curves help identify valid data
sampling locations by reporting the bit error rate (BER) as a function
of the sampling location across the unit interval (UI, same as bit
interval) at several voltage offsets.

Restriction: This option is unavailable when you define and enable a

sweep range on the IBIS-AMI Channel Analyzer Wizard - Sweep AMI
Model Settings Page. However, you can use the HyperLynx IBIS-AMI
Sweeps Viewer to generate bathtub curves from sweep results.
Statistical contours Display the Statistical Contour Chart Dialog Box. Use this dialog box
to display a nested series of eye opening contours and their bit error
rate (BER). The color of the contour indicates its BER. Like bathtub
curves, statistical contours indicate the quality of sampling locations
across the unit interval (UI, same as bit interval). An advantage of
statistical contours over bathtub curves is that the inner-eye contours
display both sampling time and voltage information.

Restriction: This option is unavailable when you define and enable a

sweep range on the IBIS-AMI Channel Analyzer Wizard - Sweep AMI
Model Settings Page. However, you can use the HyperLynx IBIS-AMI
Sweeps Viewer to generate this information from sweep results.

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IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page

Table 33-66. IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page
Contents (cont.)
Option Description
Sweep results Display the HyperLynx IBIS-AMI Sweeps Viewer. Use this dialog
box to display IBIS-AMI sweep simulation results.

Restriction: This option is available when you define and enable a

sweep range on the IBIS-AMI Channel Analyzer Wizard - Sweep AMI
Model Settings Page.

To display a simulation data storage (.SDS) file outside of the wizard,

select Simulate SI > Run IBIS-AMI Sweeps Viewer > and select the
.SDS file.
View Optionally, re-open an analysis results window.

Analysis windows open automatically when analysis completes. If you

close an analysis window, you can re-display the results until you close
the wizard. There is a View button for each type of analysis output.

Some buttons are unavailable until you run analysis to completion.

Load Optionally, open previously-saved bathtub charts (*.BTD) and
statistical contour charts (*.SCD).

The default file location is the <design> folder. See “About Design
Folder Locations” on page 1391.

Related Topics
“IBIS-AMI Channel Analysis QuickStart” on page 612
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

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 Dialog Boxes
IBIS AMI Parameter Editor

IBIS AMI Parameter Editor

To access: Select Simulate SI > Run IBIS-AMI Channel Analysis, select the Configure AMI
Models Page and click Tx AMI | Rx AMI
Use this editor to display and change AMI parameter values. If you make changes, the editor
saves your changes into a new .AMI file named <original_file_name>_settings.ami or to a file
or location you specify. This behavior preserves the contents of the original .AMI file. See
Figure 13-2 on page 624.
Optionally, you can sweep IBIS-AMI parameters by specifying sweep ranges on the IBIS-AMI
Channel Analyzer Wizard - Sweep AMI Model Settings Page. Sweep simulations temporarily
override values you set here.
The IBIS specification, starting in version 5.0, defines AMI parameters and usage. Changes to
parameter values may be based on IC datasheets, design kit documentation, your own
knowledge, and so on.
You can use this editor to add and remove jitter parameters. Use a text editor to add or remove
other types of parameters.

Figure 33-83. IBIS AMI Parameter Editor

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Dialog Boxes
IBIS AMI Parameter Editor

Table 33-67. IBIS AMI Parameter Editor Contents

Option Description
IBIS AMI file Displays the path of the <original_file_name>_settings.AMI file that
contains edited parameter values. This box is blank unless you either
load an existing <original_file_name>_settings.AMI file or save your
edits to a new file.
Parameter tree area Displays the parameters in the .AMI file. Click a parameter name in the
tree to display its contents.
Parameter value area Displays the contents of the selected parameter.

Some parameters in the Reserved_Parameters branch are read-only

because the model vendor supplies information about the model .DLL
or .so file that you cannot change. For example, you cannot edit the
GetWave_Exists parameter.

Single-value parameters are also read-only. For example, if the .AMI

file contains a parameter defined as (Format Value 0.0), the parameter
value is read-only. The idea is to use the one value that the model
developer declared to be valid.

Click View/Edit Table to open the Ami Table Editor to read or change
parameter table contents. This button is available only when you click a
parameter in the tree whose contents are in the table format.
Reset Discard the current parameters and load the contents of the original
.AMI file.
Save As Save the current parameters to a new .AMI file.
Save Saves your changes into a new .AMI file named
<original_file_name>_settings.ami. This behavior preserves the
contents of the original .AMI file.
Load Load parameters from an .AMI file.

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 Dialog Boxes
IBIS AMI Parameter Editor

Table 33-67. IBIS AMI Parameter Editor Contents (cont.)

Option Description
Jitter type 1. Click Jitter type.
2. Click Gaussian, Dual Dirac, or DjRj to add jitter to the parameter
file. See “Jitter Distribution Types” on page 1379.
3. Specify jitter values with one of the following types of units:
• Fraction of 1—If the .AMI model specifies the Tx_Jitter or
Rx_Jitter parameter as the UI type, specify jitter as a fraction of
1. For example, to specify sigma as 1% of the UI, type 0.01.
Note: By contrast, FastEye channel analysis uses UI %.
• seconds—If the .AMI model specifies the Tx_Jitter or Rx_Jitter
parameter as the Float type, specify jitter in scientific notation.
For example, to specify sigma as 1ps, type 1e-12.
See “Jitter Limits for IBIS-AMI Channel Analysis” on page 1761.
See Figure 33-84 on page 1762.
4. Click None to remove jitter from the parameter file.
Save+Exit Save your edits and close the editor.

Jitter Limits for IBIS-AMI Channel Analysis

Table 33-68. Gaussian Jitter Limits for IBIS-AMI Channel Analysis

Parameter Limit
Mean -0.5 UI to 0.5 UI
Sigma 0.2 UI or less

Table 33-69. Dual Dirac Jitter Limits for IBIS-AMI Channel Analysis
Parameter Limit
Note: There are two “Mean” parameters on this dialog
box

The top one represents Mean1 and the bottom one

represents Mean2.
Mean1 -0.5 UI to 0.5 UI

Mean1 < Mean2

Mean2 -0.5 UI to 0.5 UI

Mean1 < Mean2

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Dialog Boxes
IBIS AMI Parameter Editor

Table 33-69. Dual Dirac Jitter Limits for IBIS-AMI Channel Analysis
Parameter Limit
Sigma 0.2 UI or less

Table 33-70. DjRj Jitter Limits for IBIS-AMI Channel Analysis

Parameter Limit
Min Dj -0.5 UI to 0.5 UI

Min Dj < Max Dj

Max Dj -0.5 UI to 0.5 UI

Min Dj < Max Dj

Sigma 0.2 UI or less

Figure 33-84. Units for Jitter Parameter

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IBIS AMI Parameter Editor

Related Topics
“IBIS-AMI Channel Analysis QuickStart” on page 612
“Simulating Signal Integrity with IBIS-AMI Channel Analysis” on page 611

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Dialog Boxes
Illegal Single-Pin Components Found Dialog Box

Illegal Single-Pin Components Found Dialog Box

To access: Opens automatically, if needed, when you select File > Open Board, select
.HYP/.CCE file and click Open.
Use this dialog box to convert “illegal” single-pin components to test points. The conversion
takes place in memory (so you do not have to reload the board file) and can optionally be
written to the .HYP/.CCE file on disk.
Restriction: The CCE Files option is unavailable when running the 64-bit version of
HyperLynx. On Windows, use the 32-bit version of HyperLynx (which is also installed when
you install the 64 bit version) to open CAMCAD files. Select Start > All Programs > Mentor
Graphics SDD > HyperLynx <release> 32-bit > HyperLynx Simulation Software. By contrast,
Linux installations are 64-bit only or 32-bit only.

Figure 33-85. Illegal Single-Pin Components Found Dialog Box

Table 33-71. Illegal Single-Pin Components Found Dialog Box Contents

Option Description
Fix the .HYP file on disk Fix the board both in memory and on disk.

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 Dialog Boxes
Illegal Single-Pin Components Found Dialog Box

Table 33-71. Illegal Single-Pin Components Found Dialog Box Contents

Option Description
Create backup file Save the original .HYP/.CCE file to a backup file.
Create log file Save the board file conversion report to disk.
Fix components Apply the above options and continue to load the board file.

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Dialog Boxes
Installed Options Dialog Box

Installed Options Dialog Box

To access: Setup > Options > License Checkout and Checkin
Use this dialog box to specify HyperLynx licensed features you want to acquire or release, and
to specify other license acquisition options. When HyperLynx starts, it automatically acquires
the selected licenses you select on this dialog box.
When HyperLynx is first installed, all available licensed features are selected by default. If you
have a node-locked license, this setting will probably work best for you. If you have a floating
license that is shared by several users over the network, you may want to deselect the features
that you do not plan to use, to make them available to other users.
Some licenses, such as Touchstone Viewer and Complex Pole Fitter, are acquired on demand,
and this dialog box displays no check boxes for them.

Figure 33-86. Installed Options Dialog Box

Table 33-72. Installed Options Dialog Box Contents

Option Description
Bundles Area Buttons for popular sales bundles. Click a button to enable
only the licensed features purchased by that sales bundle.
Cross Licensing If you own a cross-license, select the non-HyperLynx
product you currently use from the Cross Licensing list.

Cross-licensing availability is restricted.

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 Dialog Boxes
Installed Options Dialog Box

Table 33-72. Installed Options Dialog Box Contents (cont.)

Option Description
License expiration warning Type the license expiration warning period, in days. To
disable this check, type 0.

If any license expires within the period you specify,

HyperLynx displays a license expiration message when you
open it.
Show this dialog on startup Select Show this dialog on startup to open the dialog box
every time you open HyperLynx.

This feature helps you to manage HyperLynx licenses on a

session-by-session basis.
Signal Integrity Buttons for popular signal-integrity applications. Click a
Applications Area button to enable the licensed features needed by the
application.
Power Integrity Buttons for popular power-integrity applications. Click a
Applications Area button to enable the licensed features needed by the
application.
PCLS_OK Click PCLS_OK to open the pcls_ok utility to troubleshoot
licensing problems. pcls_ok can report key licensing
information in the environment or registry and test the
acquisition of a licensed feature.

Restriction: pcls_ok is unavailable on Linux and Solaris.

Clear All Click Clear All to check out no licenses.
Translators Click Translators to open the Installed Translators dialog
box and view license status information for the installed
translators.
Apply Click Apply to apply selections and display license status
information.

This capability enables you to verify the license is available

before closing the dialog box.
Help --
OK --
Cancel --
Pre Layout Area Select a check box to check out the license for that feature.
Post Layout Area Select a check box to check out the license for that feature.

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Dialog Boxes
Installed Options Dialog Box

Related Topics
”Configuring the HyperLynx Environment”

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 New HyperLynx 3D EM Project Dialog Box

New HyperLynx 3D EM Project Dialog Box

To access: From the Via Properties Dialog Box, select HyperLynx 3D EM Solver > New
Use this dialog box to start creating a new HyperLynx 3D EM project file (.V3D) project file
based on defaults or an existing project file. The project file contains:
• Geometric information—Such as padstack names and differential via separation
• Simulation set up information—Such as the number of ports and simulation frequency
range

Figure 34-1. New HyperLynx 3D EM Project Dialog Box

Table 34-1. New HyperLynx 3D EM Project Dialog Box Contents

Option Description
Project File Location of the project file.
Browse Browses to an existing project file.
Use Template Area
Default Select to create a new project file, based on hard-coded defaults.
File Select to base the new project file on data from an existing project
file.
Browse Browses to an existing project file.

Related Topics
“Via Properties Dialog Box” on page 1908
“HyperLynx 3D EM Project Dialog Box” on page 1655

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Dialog Boxes
PDN Model Extractor Wizard - Check Capacitor Models Page

PDN Model Extractor Wizard - Check Capacitor Models

Page
To access:
Dialog Boxes

• LineSim — Select Export > Model > PDN & Channel Model and select the Check
Capacitor Models page
• BoardSim — Select Export > PDN Model and select the Check Capacitor Models
page
Use this page to review and edit decoupling capacitor model assignments.
See “Assign Decoupling-Capacitor Models Dialog Box” on page 1453.
Related Topics
“Running Export to PDN Models” on page 1184
“Exporting PDNs to S-Parameter Models” on page 1183

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 Dialog Boxes
PDN Model Extractor Wizard - Choose Easy / Custom Page

PDN Model Extractor Wizard - Choose Easy / Custom Page

To access:
• LineSim — Select Export > Model > PDN & Channel Model and select the Choose
Easy / Custom page
• BoardSim — Select Export > PDN Model and select the Choose Easy / Custom page
Use this page to choose between default and custom export options.

Figure 34-2. PDN Model Extractor Wizard - Choose Easy / Custom Page

Table 34-2. PDN Model Extractor Wizard - Choose Easy / Custom Page
Contents
Option Description
Easy Popular analysis settings are automatically enabled on some of
the following wizard pages. Many of the automatically-enabled
settings become read only.
Custom You can edit all analysis settings on the following wizard pages

Related Topics
“Running Export to PDN Models” on page 1184
“Exporting PDNs to S-Parameter Models” on page 1183

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Dialog Boxes
PDN Model Extractor Wizard - Control Frequency Sweep Page

PDN Model Extractor Wizard - Control Frequency Sweep

Page
To access:
• LineSim — Select Export > Model > PDN & Channel Model and select the Control
Frequency Sweep page
• BoardSim — Select Export > PDN Model and select the Control Frequency Sweep
page
Use this page to edit frequency range and sampling options, both of which affect analysis run
time and the resolution of the exported S-parameter model.

Figure 34-3. PDN Model Extractor Wizard - Control Frequency Sweep Page

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 Dialog Boxes
PDN Model Extractor Wizard - Control Frequency Sweep Page

Table 34-3. PDN Model Extractor Wizard - Control Frequency Sweep Page
Contents
Option Description
Min frequency The minimum simulation frequency, in MHz.

Many ICs have in-package decoupling that provide the

main decoupling effects above a certain frequency, such
as 300 to 350 MHz. This means decoupling capacitors
and buried capacitance located in the PCB contribute
little or no decoupling above this design-dependent
frequency.
Max frequency The maximum simulation frequency, in MHz.Many ICs
have in-package decoupling that provide the main
decoupling effects above a certain frequency, such as
300 to 350 MHz. This means decoupling capacitors and
buried capacitance located in the PCB contribute little or
no decoupling above this design-dependent frequency.
Adaptive sampling Varies the sampling step size depending on model
characteristics. The adaptive scale is better than
Restriction: This option is logarithmic and linear because it increases the sampling
unavailable if you enable the Easy rate near frequencies with resonances.
option in the Via Model Extractor
Wizard - Choose Easy / Custom
Page.
Logarithmic sampling Sampling points are distributed at logarithmic intervals
across the frequency range. The intervals between
Restriction: This option is sampling points are smaller at lower frequencies and
unavailable if you enable the Easy larger for higher frequencies. With logarithmic
option in the Via Model Extractor sampling, every next frequency point is equal to the
Wizard - Choose Easy / Custom previous value times a factor K > 1. This produces a
Page. constant increase ratio, but the absolute distance
between sampling points grows.
Linear sampling Sampling points are distributed at equal intervals across
the frequency range.
Restriction: This option is
unavailable if you enable the Easy
option in the Via Model Extractor
Wizard - Choose Easy / Custom
Page.

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Dialog Boxes
PDN Model Extractor Wizard - Control Frequency Sweep Page

Table 34-3. PDN Model Extractor Wizard - Control Frequency Sweep Page
Contents (cont.)
Option Description
Accuracy at resonances For lumped analysis, enabling the High option may still
yield reasonably fast simulation run times.
Restriction: This option is
unavailable unless you enable the For distributed analysis, you should take the complexity
Adaptive sampling option on this of the design into account. If the design has large
page. numbers of power-supply nets, hundreds of decoupling
capacitors, and hundreds or thousands of stitching vias,
enabling the Low option provides preliminary results
with decreased analysis run time. After evaluating the
preliminary results, you can identify which frequency
ranges interest you the most and try running analysis
with higher accuracy on each range of interest.
Minimum number of samples in The number of samples you specify applies to flat, non-
flat, non-resonant regions resonant, regions of an impedance profile. See the
enclosed curve region Figure 32-41 on page 1513.
Restriction: This option is
unavailable unless you enable the
Adaptive sampling option on this
page.
Number of samples The number of samples you specify applies to the entire
frequency range.
Restriction: This option is
unavailable if you enable the
Adaptive sampling option on this
page.
Default Click Default to restore the initial settings.

Related Topics
“Running Export to PDN Models” on page 1184
“Exporting PDNs to S-Parameter Models” on page 1183

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 Dialog Boxes
PDN Model Extractor Wizard - Customize Settings Page

PDN Model Extractor Wizard - Customize Settings Page

To access:
• LineSim — Select Export > Model > PDN & Channel Model and select the
Customize Settings page
• BoardSim — Select Export > PDN Model and select the Customize Settings page
Use this page to enable detailed PDN-model extraction options. Extracting models with
different sets of enabled and disabled options can help you determine how individual types of
design properties contribute to PDN model impedance.

Figure 34-4. PDN Model Extractor Wizard - Customize Settings Page

Table 34-4. PDN Model Extractor Wizard - Customize Settings Page Contents
Option Description
Include capacitor mounting To determine the contribution of capacitor mounting inductance
inductance to the overall signal-via bypassing performance, you can run
analysis with this option enabled, run it again with this option
disabled, and then compare the results.
Enable stitching-via Find stitching vias that are located close together and merge their
optimization individual models into an equivalent model. This process is
repeated across the transmission plane. Reducing the number of
stitching-via models speeds up simulation and reduces memory
consumption because each model adds a variable to the systems
of equations to solve. See “Stitching-Via Optimization - PDN
Model Extractor” on page 1776.

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Dialog Boxes
PDN Model Extractor Wizard - Customize Settings Page

Stitching-Via Optimization - PDN Model Extractor

Stitching-via optimization takes advantage of the fact that when the size of objects (or groups of
them) is much smaller than the wavelength of a signal, the signal does not respond to them in
detail, and approximate models can accurately represent those objects in simulation.
The Tolerance slider controls the merging radius for optimization:
• Low—1/30th of the minimum wavelength of the signal
• Medium—1/20th of the minimum wavelength of the signal
• High—1/10th of the minimum wavelength of the signal
For example, let us say that signal-via bypassing analysis does not exceed 300 MHz and that the
wavelength of a 300 MHz signal in FR-4 is about 20 inches. In electromagnetic analysis, 1/10th
wavelength is considered to be safely “much smaller” than the wavelength of the signal and that
within a 2 inch radius, we can avoid representing individual stitching vias by modeling them
with one equivalent (or “clumped”) via.
Not all stitching vias are eligible for optimization and most optimization takes place far away
from IC and decoupling-capacitor pins. The optimization algorithm preserves individual models
for caging vias and for stitching vias that contribute significantly to transmission-plane or
decoupling-capacitor inductance. As a result, this setting may have little effect for designs
where most of the stitching vias in the transmission plane contribute significantly to
transmission-plane or decoupling-capacitor inductance.
For example, caging vias that are located very close to the IC or decoupling-capacitor pin are
always modeled individually. In other words, if you run PDN extraction run decoupling analysis
to produce Z parameters for an IC power-supply pin that uses a via with a stitching section, then
any very-nearby stitching vias are preserved as individual models to observe their full caging
effect.
Related Topics
“Running Export to PDN Models” on page 1184
“Exporting PDNs to S-Parameter Models” on page 1183

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 Dialog Boxes
PDN Model Extractor Wizard - Normalization Impedance Page

PDN Model Extractor Wizard - Normalization Impedance

Page
To access:
• LineSim — Select Export > Model > PDN & Channel Model and select the
Normalization Impedance page
• BoardSim — Select Export > PDN Model and select the Normalization Impedance
page
Use this page to specify the normalization impedance for the exported S-parameter model.

Figure 34-5. PDN Model Extractor Wizard - Normalization Impedance Page

Table 34-5. PDN Model Extractor Wizard - Normalization Impedance Page

Contents
Field Description
Normalization impedance See “Normalization impedance” on page 1903.

Related Topics
“Running Export to PDN Models” on page 1184
“Exporting PDNs to S-Parameter Models” on page 1183

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Dialog Boxes
PDN Model Extractor Wizard - Run Analysis Page

PDN Model Extractor Wizard - Run Analysis Page

To access:
• LineSim — Select Export > Model > PDN & Channel Model and select the Run
Analysis page
• BoardSim — Select Export > PDN Model and select the Run Analysis page
Use this page to choose the name of the S-parameter file created by exporting PDN models and
to choose whether to save the wizard page settings to a file.

Figure 34-6. PDN Model Extractor Wizard - Run Analysis Page

Table 34-6. PDN Model Extractor Wizard - Run Analysis Page Contents
Option Description
Save settings to file Save wizard settings to a .DAO file. The default file location is
the <design> folder. See “About Design Folder Locations” on
page 1391. You can change the file locations.

To specify another settings file location, click Browse to specify

the file name and location.

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 Dialog Boxes
PDN Model Extractor Wizard - Run Analysis Page

Table 34-6. PDN Model Extractor Wizard - Run Analysis Page Contents (cont.)
Option Description
Auto-generate output file Name the output file using form
name <design>_<simulation_iteration>.s<number_of_ports>p.

For example, test_1.s6p.

The default file location is the <design> folder. See “About

Design Folder Locations” on page 1391.

To specify another output file location, deselect Auto-generate

output file name and click Browse to specify the file name and
location.

Related Topics
“Running Export to PDN Models” on page 1184
“Files Written by PDN Model Extraction” on page 1185
“Exporting PDNs to S-Parameter Models” on page 1183

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Dialog Boxes
PDN Model Extractor Wizard - Select IC Power Pins Page

PDN Model Extractor Wizard - Select IC Power Pins Page

To access:
• LineSim— Select Export > Model > PDN & Channel Model and select the Select IC
Power Pins page
• BoardSim — Select Export > PDN Model and select the Select IC Power Pins page
Use this page to select one or more IC power-supply pins that you want to include as ports in the
exported S-parameter model.
Restriction: In LineSim, this page is unavailable for PDN Editor designs with no IC pin
symbols.

Figure 34-7. PDN Model Extractor Wizard - Select IC Power Pins Page - LineSim

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 Dialog Boxes
PDN Model Extractor Wizard - Select IC Power Pins Page

Figure 34-8. PDN Model Extractor Wizard - Select IC Power Pins Page -
BoardSim

Table 34-7. PDN Model Extractor Wizard - Select IC Power Pins Page
Option Description
Check box Select to choose the IC power pin to analyze. See
“Identifying IC Power-Supply Pins That Can Be Selected”
on page 1522.
Pin Name --
Net --
Reference Layers (BoardSim) Stackup layer(s) that provide return current in a transmission
Referred layer (LineSim) plane for the selected pin.
Group by reference designators Collapse spreadsheet rows into groups of pins with the same
reference designator.

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Dialog Boxes
PDN Model Extractor Wizard - Select IC Power Pins Page

Table 34-7. PDN Model Extractor Wizard - Select IC Power Pins Page (cont.)
Option Description
Add IC Power Pin Click Add IC Power Pin to add missing IC power-supply
pins to the spreadsheet. You assign reference nets to power-
Restriction: This option is supply pins, to make them available as S-parameter model
unavailable for LineSim. ports. If the spreadsheet does not display the added port, the
transmission plane does not enclose it with sufficient
overlap. See “Identifying IC Power-Supply Pins That Can
Be Selected” on page 1522.

The Assign Power Integrity Models dialog box opens. For

information about assigning reference nets to pins, see
“Assigning Power-Integrity Models - BoardSim”.
Check All --

Uncheck All

Restriction: This option is

unavailable for LineSim.

Related Topics
“Running Export to PDN Models” on page 1184
“Exporting PDNs to S-Parameter Models” on page 1183

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 Dialog Boxes
PDN Model Extractor Wizard - Select Signal Vias Page

PDN Model Extractor Wizard - Select Signal Vias Page

To access:
• LineSim — Select Export > Model > PDN & Channel Model and select the Select
Signal Vias page
• BoardSim — Select Export > PDN Model and select the Select Signal Vias page
Use this page to select the via to include as a port in the exported S-parameter model. In
LineSim, note that an individual member of a differential pair is modeled as a single-ended via,
unless the differential via symbol in the PDN Editor connects symmetrically to transmission-
line symbols.

Figure 34-9. PDN Model Extractor Wizard - Select Signal Vias Page - LineSim

Table 34-8. PDN Model Extractor Wizard - Select Signal Vias Page Contents -
LineSim
Option Description
NN Port numbers in the exported model. Port numbering on this page
resumes where port numbering on the PDN Model Extractor
Wizard - Select IC Power Pins Page ended.

To renumber ports, drag one or more rows to the correct location.

As you drag, a red horizontal line appears. When you release the
mouse button, the dragged rows move to the spreadsheet row
below the red line.
Check box Select to include the via or differential via pair in the exported
model.

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Dialog Boxes
PDN Model Extractor Wizard - Select Signal Vias Page

Table 34-8. PDN Model Extractor Wizard - Select Signal Vias Page Contents -
LineSim (cont.)
Option Description
Schematic Via Name --
Via 1 Connected Layer Stackup layer(s) connected to the signal via.

Point to a cell containing a plus sign + to display a ToolTip

containing the stackup layers the via connects to. Click the plus
sign + to expand the spreadsheet row to display all connected
stackup layers.
Via 2 Connected Layer Stackup layer(s) connected to the second pin in a differential
signal via pair.

Point to a cell containing a plus sign + to display a ToolTip

containing the stackup layers the via connects to. Click the plus
sign + to expand the spreadsheet row to display all connected
stackup layers.

Figure 34-10. PDN Model Extractor Wizard - Select Signal Vias Page - BoardSim

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 Dialog Boxes
PDN Model Extractor Wizard - Select Signal Vias Page

Table 34-9. PDN Model Extractor Wizard - Select Signal Vias Page Contents -
BoardSim
Field Description
NN Port numbers in the exported model. Port numbering on this page
resumes where port numbering on the PDN Model Extractor
Wizard - Select IC Power Pins Page ended.

To renumber ports, drag one or more rows to the correct location.

As you drag, a red horizontal line appears. When you release the
mouse button, the dragged rows move to the spreadsheet row
below the red line.
Check box Select to include the via or differential via pair in the exported
model.
Net Name --
Position X/Y coordinates of the signal via.
Connected Layers The complete set of stackup layers the signal via connects to.

Click the plus sign + to expand the spreadsheet row to display all
connected stackup layers.

Click the minus sign - to collapse the spreadsheet row to display

only the top-most connected stackup layer.
Select Net Temporarily enable the Select Net by Name and right-click
in board viewer > Select Net features in order to select a net.

For information about zooming and panning to display the net in

the board viewer. See “Viewing BoardSim Boards”.
Pan to To display a signal via in the center of the board viewer, click the
row header for the via to display and click Pan to.

The selected via is displayed in the center of the board viewer and
marked by white lines. If the wizard dialog box covers part of the
board viewer, the selected via is displayed in the center of the
largest visible area of the board viewer.
Check All --

Restriction: This option is

unavailable for LineSim.

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Dialog Boxes
PDN Model Extractor Wizard - Select Signal Vias Page

Table 34-9. PDN Model Extractor Wizard - Select Signal Vias Page Contents -
BoardSim (cont.)
Field Description
Uncheck All --

Restriction: This option is

unavailable for LineSim.

Related Topics
“Running Export to PDN Models” on page 1184
“Exporting PDNs to S-Parameter Models” on page 1183

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 Dialog Boxes
PDN Model Extractor Wizard - Start Analysis Page

PDN Model Extractor Wizard - Start Analysis Page

To access:
• LineSim — Select Export > Model > PDN & Channel Model and select the Start
Analysis page
• BoardSim — Select Export > PDN Model and select the Start Analysis page
Use this page to start a PDN model export or load the settings for a saved export.

Figure 34-11. PDN Model Extractor Wizard - Start Analysis Page

Table 34-10. PDN Model Extractor Wizard - Start Analysis Page Contents
Option Description
New --
Use last configuration Reuse settings from the current BoardSim/LineSim session. This
option is unavailable until you have opened and closed the wizard
in the current BoardSim/LineSim session.

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Dialog Boxes
PDN Model Extractor Wizard - Start Analysis Page

Table 34-10. PDN Model Extractor Wizard - Start Analysis Page Contents (cont.)
Option Description
Load save configuration Open a settings file (.DAO) by selecting Load save
configuration, clicking Load, browsing to the file, and then
clicking Open.

Note: If you load a .DAO file saved from LineSim in HyperLynx

8.1.1 or older, you may have to reselect power-supply nets and
pins to probe on other pages in this wizard. Starting with
HyperLynx 8.2, the PDN Editor supports customer-defined
power-supply net names, such as 1.8V. In previous releases, the
PDN Editor used only names that it created automatically, such
as __TPE_VCC__.
Save settings to file Save setup information to the settings file. By default, this file is
written to the <design> folder and named <design>.dao. See
“About Design Folder Locations” on page 1391.

Related Topics
“Running Export to PDN Models” on page 1184
“Exporting PDNs to S-Parameter Models” on page 1183

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 Dialog Boxes
PDN Net Manager Dialog Box

PDN Net Manager Dialog Box

To access: From the PDN Editor toolbar, select Net Manager
Use this dialog box to view, add, and delete power-supply nets.
For information about how the PDN Editor maps power-supply nets to metal areas, see “Power-
Supply Nets - PDN Editor”.

Figure 34-12. PDN Net Manager Dialog Box

Table 34-11. PDN Net Manager Dialog Box Contents

Option Description
Net Lists the available net names, which are either exported from
BoardSim to LineSim or created by you.
Voltage Lists the voltage associated with the net name as exported from
BoardSim to LineSim.

Note: The value listed in this column are for reference only. The
voltage values displayed in the PDN Net Manager are not used for
simulation purposes.
<new> Adds a new spreadsheet row.

Click <new>. A row is added to the table with a placeholder net

name and voltage value. Edit the net name and voltage value and
press OK.

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Dialog Boxes
PDN Net Manager Dialog Box

Related Topics
“Adding Symbols to Power-Distribution Networks”

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 Dialog Boxes
Preferences Dialog Box

Preferences Dialog Box

To access: Setup > Options > General
Use this dialog box to view and edit properties that affect how HyperLynx operates and to help
you to set up a working environment that best suits the design and the way you work.
Properties specified in this dialog box apply to all designs.
Table 34-12. Preferences Dialog Box Contents
Tab Description
Preferences Dialog Box - Use this tab to specify advanced simulation options that affect
Advanced Tab which algorithms are used during simulation in LineSim and
BoardSim.
Preferences Dialog Box - Use to specify the physical appearance of objects in the
Appearance Tab workspace for the following tools:
• BoardSim Board Viewer
• LineSim Cell-Based Schematic Editor
• LineSim Free-Form Schematic and PDN Editors
Preferences Dialog Box - Use this tab to specify BoardSim-specific preferences for vias,
BoardSim Tab net handling, crosstalk, and default trace separation.
Preferences Dialog Box - Use this tab to choose the circuit simulator, set various SPICE
Circuit Simulators Tab and S-parameter simulation options, and set options for the
SPICE Writer.
Preferences Dialog Box - Use this tab to specify the initial properties used by the
Default Padstack Tab <default> layer of new padstacks created in the Padstack
Manager dialog box in the free-form schematic editor.
Preferences Dialog Box - Use this tab to specify the properties of new layers created in
Default Stackup Tab the Stackup Editor and the stackup properties for a new
schematic.
Preferences Dialog Box - Use this tab to define general signal-integrity simulation
General Tab settings and board temperature settings.
Preferences Dialog Box - Use this tab to specify LineSim-specific preferences.
LineSim Tab
Preferences Dialog Box - Use this tab to specify the properties used by the oscilloscope
Oscilloscope Tab when it opens.
Preferences Dialog Box - Use this tab to specify options for power-integrity simulations.
Power Integrity Tab

Related Topics
Configuring the HyperLynx Environment

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Preferences Dialog Box - Advanced Tab

Preferences Dialog Box - Advanced Tab

To access: Setup > Options > General - Advanced Tab
Use this tab to specify advanced simulation options that affect which algorithms are used during
simulation in LineSim and BoardSim.
Caution
Mentor Graphics recommends against changing these options except under special
circumstances. You should contact Mentor Graphics for technical support before
changing the default settings.

Tip: To restore default settings, click Restore Defaults.

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Preferences Dialog Box - Advanced Tab

Figure 34-13. Preferences Dialog Box - Advanced Tab

Table 34-13. Preferences Dialog Box - Advanced Tab Contents

Option Description
BoardSim Area
Inform users of Select to report a warning when trying to simulate a net that contains a
zero-length zero-length routing segment in the board file (might result from a PCB-
segments layout tool which does not “clean up” its database). Since zero-length
segments rarely cause a problem, it is almost always advisable to leave
this option disabled.

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Preferences Dialog Box - Advanced Tab

Table 34-13. Preferences Dialog Box - Advanced Tab Contents (cont.)

Option Description
Treat test points as Select to assign IC models or Quick Terminators to test points on your
IC pins board.

When this option is cleared, BoardSim filters out test points at board-
load time and test points will not be available until you select this
option and reload the board.
Separate pins at the Select to simulate two or more pins with assigned models that are
same simulation shorted by their pads. To open the short during simulation, BoardSim
node temporarily adds short transmission lines between the pins.
Always treat diff Select couple differential pairs. BoardSim identifies differential pairs
pairs as coupled by inspecting driver/receiver IC model assignments. If an IBIS model
containing the [Diff Pin] keyword is assigned to either the driver or
receiver, the nets in the differential pair are known.

If this option is enabled, “crosstalk” conceptually means “random

crosstalk” and the coupling between differential pair segments is
considered a special kind of “organized” crosstalk. This means you do
not have to set the crosstalk threshold to some value that enables
BoardSim to recognize differential pair segments as coupled.
Use common anti- Select to use shared anti-pads for all differential vias that are located
pads for differential within a metal area defined by a PLANE keyword in the .HYP file.
vias

This option reduces via fringing capacitance to reference metal and

strengthens the coupling between the differential vias. The impact of
this option on simulation results can be minor.

The .HYP file syntax does not support shared anti-pads. This option
causes the simulator and board viewer to synthesize common anti-pads
for differential vias.

Restriction: This option applies only to two round anti-pads of the

same size.
HYP-file CURVE records Area

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Preferences Dialog Box - Advanced Tab

Table 34-13. Preferences Dialog Box - Advanced Tab Contents (cont.)

Option Description
Linearize When a curve has a radius that is less than this value, replace it with a
curves with line. This option works on both valid and invalid curves.
radii <
Specify 0 to disable this option.

Replacements take place in memory and the .HYP file is not changed.
Don’t load Do not load the board if it contains one or more invalid curves.
boards with
invalid curves See “CURVE Subrecords with Invalid Coordinates” on page 1798.
Convert invalid Convert invalid curves to lines.
curves to lines
Replacements take place in memory and the .HYP file is not changed.

See “CURVE Subrecords with Invalid Coordinates” on page 1798.

Load boards Keep invalid curves and load the board.
with invalid
curves See “CURVE Subrecords with Invalid Coordinates” on page 1798.
Segment threshold By default, BoardSim considers any net with 20,000 or more individual
for auto power- metal segments to be a power-supply net. However, you can modify the
supply ID identification threshold to any number of segments you want.

The change takes effect next time you load a board.

If this identification is ever wrong, and you do not want to change the
number-of-segments threshold, the misidentified net can be removed
from the power-supplies list using the power-supply editor.

See also: Editing Power-Supply Nets

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Preferences Dialog Box - Advanced Tab

Table 34-13. Preferences Dialog Box - Advanced Tab Contents (cont.)

Option Description
For EMC, ignore Some PCB autorouters have a feature that artificially increases the
traces shorter than length of a net if the user provides a "minimum length" or "minimum
delay" constraint. This is often done in an attempt to reduce clock skew,
by equalizing the lengths of two or more nets.

The increase is implemented by "serpentining or tromboning" the trace

through a series of tight, repeated turns that significantly increases the
length of the net compared to a straight route.

When BoardSim EMC simulates the radiation from a trace, it calculates

the radiation from each individual metal segment on the trace.
However, in an effort to improve simulation speed, trace segments
shorter than a certain threshold length are omitted from the calculations
(since their contributions to the overall radiation levels should be low).

If a trace is composed of nothing but short segments, the omission of

short segments will cause the predicted radiation levels to be too low.
To work around this, the short-segment threshold is available as a user-
definable parameter. If you have nets, such as the "serpentine" cases
discussed above, that are composed mostly of short segments, decrease
the threshold so that most or all of the segments on your nets are
included in analysis.
For Crosstalk, BoardSim ignores coupling from regions shorter than the specified
ignore coupling value. This results in a performance improvement with no accuracy
regions shorter than penalty (unless the value is increased to something too large) because
tiny, "short", coupling regions contribute virtually no crosstalk but may
consume significant CPU power if simulated.
Differential Via If the centerlines of two vias for a differential pair are sufficiently close,
Search Padstack simulate the vias differentially and enable the Via Visualizer to display
Size Factor both vias. A multiple of the pad diameter provides the distance
threshold.
General Area
Combine line Select to have BoardSim/LineSim combine adjoining trace segments
segments where that have the same impedance into a single, longer segment. This
possible optimization produces faster transient simulation.
High accuracy field Select to force the field solver to run with higher-than-normal spatial
solver resolution. The default, non-high-accuracy, mode has been set to give
excellent accuracy for nearly any problem on which BoardSim/LineSim
would normally run. However, in rare cases (such as extremely narrow
trace separations), the higher-accuracy mode may be preferable.
However, high-accuracy mode runs substantially slower than normal
mode, so should be enabled only when absolutely necessary.

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Preferences Dialog Box - Advanced Tab

Table 34-13. Preferences Dialog Box - Advanced Tab Contents (cont.)

Option Description
Use field-solver BoardSim/LineSim Crosstalk’s field solver normally uses a smart
cache “cache” to prevent having to re-solve cross sections which it has
already encountered and analyzed. (Such repeated cross sections occur
frequently during crosstalk analysis on a given PCB.) Disabling this
feature turns off the cache, which may seriously degrade the product’s
performance. Since there is rarely (if ever) any reason to disable the
cache, it is advisable to never disable this option.
Assume distant When this option is enabled and no plane layers exist in the stackup, the
ground if there Are field solver assumes that a distant plane layer exists during its
no plane layers calculations. The field solver knows just how far away from the signal
layers to put the “hidden” plane to get the right answers with good
speed and accuracy.

If you use double-sided or flexible boards with no plane layers,

enabling this option means that you do not have to manually create a
“fake” plane layer in the stackup to enable simulation.
Strip V-t non- We assume that some of the flat, non-switching, leading-edge time
switching time present in V-t tables for IBIS models is unimportant and can cause the
user to wait a rather perplexing amount of time until the waveform
starts to move on the oscilloscope. Also, if a model contains a lot of
non-switching leading-edge time in its V-t table, and you clock it fast
enough in the oscilloscope, the model can fail to rise before being told
to fall by the clock.

By default HyperLynx strips the non-switching time for rising and

falling waveforms. Key points of the stripping operation:
• The least amount of non-switching time is found among the V-t
tables for the typical, maximum, and minimum delay conditions.
• The least amount of non-switching time is stripped from all V-t
tables prior to simulation. This method maintains time correlation
among waveforms for typical, minimum, and maximum delay
conditions.
• Separate stripping operations are performed for each group of pins
that share the following properties:
• Reference designator
• IBIS model
- [Component] keyword value within IBIS model
- [Model Selector] keyword value (if present) within [Model]
keyword

You can also edit the IBIS model with the Visual IBIS Editor to remove
non-switching time from V-t tables. See “Removing Initial Delays from
IBIS Models” on page 414.

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Preferences Dialog Box - Advanced Tab

Table 34-13. Preferences Dialog Box - Advanced Tab Contents (cont.)

Option Description
Do not delete S- Select to retain the SPICE netlist and simulation run files that get
parameter created when exporting an S-parameter model for a schematic or net.
extraction netlists
If you do not select this option, these files are deleted when the export
process completes. These files are located in the same folder as the
schematic or board file. See “About Design Folder Locations” on
page 1391.
Enable AMI DLL Select to display the Edit Tx AMI DLL String and Edit Rx AMI DLL
string editing String buttons in the IBIS-AMI Channel Analyzer Wizard - Configure
AMI Models Page.
Maximum line- This percentage tells BoardSim/LineSim how large an error, as a
length tolerance percentage of the total delay of the segment, it can make in modeling
the propagation delay of the segment. This tolerance applies only to
very short segments, and even for short segments, is rarely invoked by
the program.
Max DC converge Tells BoardSim/LineSim the maximum number of times it can re-
iterations simulate to find a driver’s initial DC voltage. Such iterative simulation
is only required when there are multiple IBIS (any model) or
.MOD/.PML bipolar IC models present on a net. The default value is
almost always sufficient to stabilize a multi-driver DC simulation; in
very rare cases the number of iterations should be increased to give
more-accurate results.
Min DC converge Tells BoardSim/LineSim how tightly each driver’s voltage in a multi-
threshold driver DC simulation must converge before the DC simulation can
safely be considered “successful.” The default value should never be
changed unless a circuit and combination of drivers has difficulty
converging, and might benefit from a “relaxed” convergence criterion.

CURVE Subrecords with Invalid Coordinates

Translators can sometimes create .HYP files that contain CURVE subrecords (in a NET
keyword) with coordinates that do not add up. HyperLynx checks the distance between the
center point and each of the end points in the CURVE subrecord and if either of them
mismatches the specified radius by more than 5%, the arc is invalid. See Figure 34-14.

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Preferences Dialog Box - Advanced Tab

Figure 34-14. CURVE Subrecord - Distance Between Center and End Points

Even though this problem is more likely to happen for curves with very small radii, the problem
is typically caused by bad data and not numerical rounding.
For example, in the CURVE subrecord below, the distance between the center point (XC/YC)
and an end point (X1/Y1) is more than 5% different than the radius (R). The example does not
provide units.
(CURVE X1=0.149555 Y1=-0.223520 X2=0.149631 Y2=-0.223698 XC=0.149631 YC=-
0.223596 R=0.000102)

Use the following Euclidian equation to calculate the distance between XC/YC and X1/Y1:
2 2
Distance = ( XC – X1 ) + ( YC – Y1 )
Substituting values:
2 2
Distance = ( 0.149631 – 0.149555 ) + ( ( – 0.223596 ) – ( – 0.223520 ) )

Distance = 1.0748e – 4
The distance from XC/YC to X1/Y1 is 5.37% greater than the radius.
By contrast, the distance from XC/YC to X2/Y2 matches the radius.
Related Topics
Configuring the HyperLynx Environment
“Preferences Dialog Box” on page 1791

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Dialog Boxes
Preferences Dialog Box - Appearance Tab

Preferences Dialog Box - Appearance Tab

To access: Setup > Options > General - Appearance Tab
Use this tab to specify the physical appearance of objects in the workspace for the following
tools:
• BoardSim Board Viewer
• LineSim Cell-Based Schematic Editor
• LineSim Free-Form Schematic and PDN Editors

Tip: To restore all the default properties for a tool, click the appropriate Default button.

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Preferences Dialog Box - Appearance Tab

Figure 34-15. Preferences Dialog Box - Appearance Tab

Table 34-14. Appearance Tab Contents

Option Description
BoardSim board viewer Area

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Preferences Dialog Box - Appearance Tab

Table 34-14. Appearance Tab Contents (cont.)

Option Description
Color Click the Color button to change the background color
for the board viewer.

Use the Stackup Editor to edit the colors of traces and

copper pours in the board viewer. See “Changing
Stackup Layer Colors” on page 397.
Background nets Move the slider to control brightness of background
(unselected) nets. Transparent means low brightness and
Opaque means high brightness.

To disable the display of background nets, drag the

slider to the Transparent end of the scale. On very large
designs, this setting can help speed up the display of the
board.

See also: Board Viewer User Interface

LineSim cell-based schematic editor Area
Color Click the Color button to change the background color
of the schematic.
LineSim free-form schematic editor Area
Object List Select the type of object whose appearance you want to
modify.
Color Click the Color button and select a color for the object.
Font This option only displays if the object you are modifying
has text. Use it to specify the font style.
Grid step Select or type a value for the grid spacing.
Display grid Select to make the grid visible.
Snap to grid Select to force objects to align to the grid while you
move or add them. This means that when you place an
object in the schematic, it jumps to the nearest X/Y grid
coordinate as you drag it to the new location.

Clear to place objects off the grid.

PDN editor Area
Object List Select the type of object whose appearance you want to
modify.
Color Click the Color button and select a color for the object.

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Preferences Dialog Box - Appearance Tab

Table 34-14. Appearance Tab Contents (cont.)

Option Description
Font This option only displays if the object you are modifying
has text. Use it to specify the font style.
Grid step Enter a value in mils for the grid spacing.
Display grid Select to make the grid visible.
Snap to grid Select to force objects to align to the grid while you
move or add them. This means that when you place an
object in the schematic, it jumps to the nearest X/Y grid
coordinate as you drag it to the new location.

Clear to place objects off the grid.

Related Topics
“Preferences Dialog Box” on page 1791
Configuring the HyperLynx Environment
“Specifying Grid Preferences”

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Preferences Dialog Box - BoardSim Tab

Preferences Dialog Box - BoardSim Tab

To access: Setup > Options > General - BoardSim Tab
Use this tab to specify BoardSim-specific preferences for vias, net handling, crosstalk, and
default trace separation.

Figure 34-16. Preferences Dialog Box - BoardSim Tab

Table 34-15. BoardSim Tab Contents

Option Description
Vias Area

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Preferences Dialog Box - BoardSim Tab

Table 34-15. BoardSim Tab Contents (cont.)

Option Description
Synthesize missing pads This option is now rarely used and should probably never be
changed from its default value.

This option enables BoardSim, under certain conditions, to

automatically create pads of the specified diameter when they
are missing from the board file. This ability was included in
early versions of BoardSim to compensate for problems with
one or two PCB-layout vendors’ databases; those problems
have since been rectified and hence this feature is of mostly
historical value.
Pad diameter Diameter of pads that are automatically created when the
synthesize missing pads option is selected.
Synthesize missing drill holes If selected and the HYP file contains padstacks with no drill
holes, BoardSim automatically synthesizes the missing drill
holes.
Drill-hole diameter Diameter for missing drill holes.
Net Handling Area
Assume net is a power supply Specify the Number-of-Capacitors threshold for identifying
if... power-supply nets. By default, BoardSim considers any net
with three or more capacitors connected to be a power-supply
net.

If this identification is ever wrong, and you do not want to

change the number-of-capacitors threshold, the misidentified
net can be removed from the power-supplies list using the
power-supply editor.

See also: Editing Power-Supply Nets

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Preferences Dialog Box - BoardSim Tab

Table 34-15. BoardSim Tab Contents (cont.)

Option Description
Remove redundant metal from a Selecting this option cleans all signal nets, eliminating
board’s nets as the board is redundant metal and combining overlapping structures when
loaded possible into fewer, large structures, at board-loading time.

Note: BoardSim also removes redundant metal from power-

supply nets that are incorrectly identified as signal nets,
which can cause power-integrity measurement errors. If this
happens, disable this option, close the board, and then
identify all power-supply nets. See “Editing Power-Supply
Net Properties” and “Identifying Power-Supply Nets -
BoardSim”. After all power-supply nets are identified, you
can re-enable this option.

Redundant metal can exist because many PCB-layout

programs make little or no attempt to "clean up" redundant or
overlapping trace segments on a board. Such redundancy is
particularly common in designs that have been routed at least
partially by hand. Redundancy makes no difference when a
Gerber file is output, but is not acceptable to simulation tools
like BoardSim that assign electrical characteristics to all
metal structures on a signal net.

If you do not select this option, signal nets are cleaned as they
are used. This is usually quicker than cleaning them all at
once, but there is a disadvantage to cleaning signal nets only
when selected. The net lengths displayed in the Select Net by
Name dialog box are calculated at board-loading time. If net
cleaning occurs only later when nets are selected, and if some
signal nets contain large amounts of redundant metal, then
the lengths reported in the dialog box may be too long. To
avoid this problem, you can instruct BoardSim clean all
signal nets at board-loading time.

See also: “Usage Notes” on page 1807.

Crosstalk options
Maximum number of aggressor Enter the maximum number of aggressor nets per crosstalk
nets simulation.

See also: “Limiting the Number of Aggressor Nets” on

page 1234.
Default trace separations Area

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Preferences Dialog Box - BoardSim Tab

Table 34-15. BoardSim Tab Contents (cont.)

Option Description
Trace to trace Enter the default test trace separation value here. This value
is used if the .HYP file and .BUD file do not contain test trace
separation for stackup layers. For information about setting
the test trace separation in the stackup editor, see About Test
Trace Widths in BoardSim.

Note: Setting the value here also changes the Trace to trace
value on the LineSim tab.
Trace to plane Enter the default trace-to-metal-area clearance, when the
.HYP file contains anti-pads, but does not specify a
clearance.

This field is one of several sources of trace-to-metal-area

clearance values. For the prioritized list of clearance value
sources, see “Precedence Among Anti-Segment Clearances”
on page 1394.

If you set the value in the Setup Anti-Pads and Anti-

Segments Dialog Box, this value is no longer used because it
has lower priority.

Note: Setting the value here also changes the Trace to plane
value on the LineSim tab.

Usage Notes
Since your boards will load into BoardSim faster if you do NOT enable the "net cleaning during
loading" option, Mentor Graphics generally recommends that you not enable this option.
One exception would be if the net lengths reported in the Select Net by Name dialog box seems
too long, indicating that your nets contain a significant amount of redundant metal; then you
might prefer to have more-accurate lengths, at the expense of longer board-loading times.
Related Topics
“Preferences Dialog Box” on page 1791
“Precedence Among Anti-Pad Clearances - BoardSim” on page 1392
Configuring the HyperLynx Environment

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Dialog Boxes
Preferences Dialog Box - Circuit Simulators Tab

Preferences Dialog Box - Circuit Simulators Tab

To access: Setup > Options > General - Circuit Simulators Tab
Use this tab to choose the circuit simulator, set various SPICE and S-parameter simulation
options, and set options for the SPICE Writer.
The simulator you select runs the following signal-integrity simulations: interactive, generic
batch, DDRx batch, and PI/SI co-simulation.
The selected HyperLynx and SPICE simulator names are displayed in the oscilloscope, below
the Start Simulation button.
Note
The SPICE Output license is required to run the SPICE Writer.

The GHz license bundle is required to simulate S-parameter models.

The Advanced Scope and SPICE Output licenses are required to run SPICE simulation.
The GHz license bundle is required to run ADMS.

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Preferences Dialog Box - Circuit Simulators Tab

Figure 34-17. Preferences Dialog Box - Circuit Simulators Tab

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Preferences Dialog Box - Circuit Simulators Tab

Table 34-16. Circuit Simulators Tab Contents

Option Description
HyperLynx Circuit Simulator Area
Note: Simulation waveforms created by the Classic and HyperLynx SI-SPICE simulators may
contain small differences, even for identical circuits.
Classic Does not support SPICE models. Runs faster than the
HyperLynx SI-SPICE simulator.
HyperLynx SI-SPICE Supports SPICE models for passive components, but not for ICs
or other types of active components, such as transistors and
diodes.

Note: DDRx simulation automatically switches to SI-SPICE for

nets that span more than one board and pass through an
advanced MultiBoard connector with a SPICE model containing
only passive components assigned to it.

Does not support .MOD and .PML models.

HyperLynx SI-SPICE supports the same accurate interconnect

modeling technologies as Mentor Graphics’ ADMS simulator,
including an advanced multi-Debye lossy transmission line and a
complex pole fitting (CPF) algorithm for time-domain
simulation of S-parameter models. Note that the GHz license
bundle is required to simulate S-parameter models.
Eldo/HSPICE Executable Area
Eldo/ADMS You have installed and licensed full ADMS. Supports SPICE
models containing text that is encrypted for the Eldo/ADMS
simulator.

When you click Eldo/ADMS on the oscilloscope, ADMS

simulates the net.

Exception: The oscilloscope and FastEye-Diagram Wizard

automatically simulate with ADMS any nets with assigned IBIS
models, even when you enable Eldo/ADMS.

Restriction: This option is unavailable if full ADMS is not

installed.

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Preferences Dialog Box - Circuit Simulators Tab

Table 34-16. Circuit Simulators Tab Contents (cont.)

Option Description
HSPICE Select to use the HSPICE simulator, which you have separately
installed and licensed. Supports SPICE models containing text
that is encrypted for the HSPICE simulator.

When you click HSPICE on the oscilloscope, HSPICE simulates

the net.

The “Found at” box contains the path to the HSPICE simulator
software you have enabled. The path is based on the following
environment variables set by SPICE simulation software
installation:
• HSPICE (Windows)—the path is
$INSTALLDIR\bin\hspice.exe
• HSPICE (Linux/UNIX)—the path is
$INSTALLDIR/bin/hspice
MultiCPU Select to enable HSPICE to use more than one CPU. Select any
number of CPUs up to the capacity you have purchased.
• This option is available only for HSPICE.
• Older versions of HSPICE that support one CPU simply
ignore this option.
Use native HyperLynx This is a limited version of ADMS that is automatically installed
version with HyperLynx. This simulator supports SPICE models
containing text encrypted for the Eldo simulator.
Use Full ADMS Automatically installed with HyperLynx, but you have
additionally licensed full ADMS. Supports unencrypted SPICE
Requires separate license models and SPICE models containing text that is encrypted for
the Eldo simulator.
Found at Displays the location of the HSPICE simulator software that you
have enabled. The contents of this box does not apply to the
copy of ADMS that is automatically installed with HyperLynx.

The path is based on the following environment variables set by

SPICE simulation software installation:
• HSPICE (Windows)—the path is
$INSTALLDIR\bin\hspice.exe
• HSPICE (Solaris)—the path is $INSTALLDIR/bin/hspice
SPICE deck file extensions Area
SPICE deck file extensions Verify this field contains the correct list of SPICE library and S-
Field parameter/Touchstone file extensions. Make corrections as
needed and use a comma to separate the items.
Default --

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Preferences Dialog Box - Circuit Simulators Tab

Table 34-16. Circuit Simulators Tab Contents (cont.)

Option Description
General netlist options Area
Force use of lossless T SPICE Writer writes SPICE W elements for transmission lines
elements (instead of W) for to the netlist unless you select this option and one of following
uncoupled lines conditions are true:
• You are running BoardSim and have disabled crosstalk.
• You are running BoardSim, no coupled nets exceed the
crosstalk threshold voltage, and lossy is disabled.
• You are running LineSim, the schematic contains no
coupling, and lossy is disabled.
Export passive component Clear this option to exclude package parasitic resistance,
parasitics from LineSim inductance, and capacitance of passive components from the
SPICE netlist.

You can use this capability to learn the effects of passive-

component parasitics on simulation results, or to create a SPICE
netlist without the numerous elements needed to represent
passive-component parasitics.
Eldo model syntax type Area
Native Eldo Use this option if you use models with Eldo-specific syntax.
HSPICE compatible HSPICE compatible models (including Eldo encrypted)—
Use this option if you use models with HSPICE-compatible
syntax. The models may contain text encrypted for Eldo.
Caution
You cannot simulate nets with a mixture of native Eldo
syntax models and HSPICE-compatible syntax models.

Eldo method for S-parameter models Area

CPF Complex-pole fitting. See Table 33-22 on page 1603.
DSP Convolution. See Table 33-22 on page 1603.
Related Topics
“Preferences Dialog Box” on page 1791
“Running SPICE Simulations” on page 567
“Exporting Nets to SPICE Netlists” on page 1157
Configuring the HyperLynx Environment

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Preferences Dialog Box - Default Padstack Tab

Preferences Dialog Box - Default Padstack Tab

To access: Setup > Options > General - Default Padstack Tab
Use this tab to specify the initial properties used by the <default> layer of new padstacks
created in the Padstack Manager dialog box in the free-form schematic editor.

Figure 34-18. Preferences Dialog Box - Default Padstack Tab

Table 34-17. Default Padstack Tab Contents

Option Description Default
Value
Pad Area
Shape Select the pad shape. Round
• Round
• Rectangular
• Oval
• Oblong — An oblong pad is rectangular
with rounded corners.

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Preferences Dialog Box - Default Padstack Tab

Table 34-17. Default Padstack Tab Contents (cont.)

Option Description Default
Value
Width Horizontal width of pad. For round pads, this 24 mils
is the diameter.
Height Vertical height of the pad. This option is 24 mils
disabled for round pads.
Drill Area
Drill Diameter -- 13 mils
Differential Pairs Area
Separation The distance between the centers of the via 75 mils
barrels.
<Auto> Anti-Pads Area
Clearance The distance between the pad and 10 mils
automatically-created anti-pad. This value is
applied when you select <Auto> in the Anti-
pad Shape column of the spreadsheet in the
Padstack Editor. See “Editing Padstack
Properties”.
Via Barrel Plating Area
Thickness The thickness of the metal plating that forms 1 mils
the wall of via barrel.

This option is unavailable when you enable the

“Vias are conductively filled” option.
Vias are conductively filled Select if, by default, the via barrel is Cleared
completely filled with metal.

This option affects DC drop simulation. See

“Simulating DC Voltage Drop” on page 963.
Metal --

Select “Custom” to specify a metal type with a

unique resistivity.
Resistivity --

This option is read only unless you select

“Custom” in the Metal list.

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Preferences Dialog Box - Default Padstack Tab

Related Topics
“Preferences Dialog Box” on page 1791
“Editing Padstack Properties”
“Precedence Among Anti-Pad Clearances - BoardSim” on page 1392
“Precedence Among Anti-Pad Clearances - LineSim” on page 1393
Configuring the HyperLynx Environment

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Dialog Boxes
Preferences Dialog Box - Default Stackup Tab

Preferences Dialog Box - Default Stackup Tab

To access: Setup > Options > General - Default Stackup Tab
Use this tab to specify the properties of new layers created in the Stackup Editor and the stackup
properties for a new schematic.

Figure 34-19. Preferences Dialog Box - Default Stackup Tab

Table 34-18. Default Stackup Tab Contents

Option Description
Test Trace Area

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 Dialog Boxes
Preferences Dialog Box - Default Stackup Tab

Table 34-18. Default Stackup Tab Contents (cont.)

Option Description
Width Default trace width.

See “Changing Trace Widths”.

Outer metal thickness Area - Default parameters for outer metal layers.
Plating --
Base --
Inner metal thickness Area - Default parameters for inner metal layers.
Base --
Inner dielectric Area - Default parameters for inner dielectric material.
Height --
Constant (Er) --
Loss tangent --
Outer dielectric (conditional coating) Area - Default parameters for outer dielectric
material.
Height --
Constant (Er) --
Loss tangent --
Related Topics
“Preferences Dialog Box” on page 1791
Configuring the HyperLynx Environment

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Dialog Boxes
Preferences Dialog Box - General Tab

Preferences Dialog Box - General Tab

To access: Setup > Options > General
Use this tab to define general signal-integrity simulation settings and board temperature
settings.

Figure 34-20. Preferences Dialog Box - General Tab

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 Dialog Boxes
Preferences Dialog Box - General Tab

Table 34-19. General Tab Contents

Option Description
MOD IC-model best/worst scale factors Area
By default, BoardSim/LineSim scales the typical device parameters in all of the .MOD
models in a simulation up by a factor of 1.8 to create Slow-Weak operation, and down by 0.6
to create Fast-Strong. However, you can adjust these parameters, if you want, to increase or
decrease the “pessimism” of your simulations. See Setting IC Operating Parameters.
Min. scale factor --
Max. scale factor --
IC-Model Voltage References Area
When assigning a model to Connect the IC pin to a “virtual” net that is set to the internal
an IC-pin, always use the voltage specified in the IC model.
model's internal values
Use this option unless you have a compelling reason to not use
it. Enabling this option ensures the power-supply voltage does
not fall outside the voltage range specified for buffer and
clamp data in the IC model.
When assigning a model to Connect the IC pin to an external power-supply net that it
an IC-pin, use a power- automatically identifies. If BoardSim/LineSim cannot identify
supply net connected to the the power-supply net, it connects the IC pin to a “virtual” net
IC that is set to the internal voltage specified in the IC model.

Note: The IC-model power-supply voltage options on the

General tab do not apply to SPICE models. SPICE models
always connect to an external power-supply net whose voltage
is specified in the Set Power Supply Voltage and Nets dialog
box (Setup > Power-Supply Nets).

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Preferences Dialog Box - General Tab

Table 34-19. General Tab Contents (cont.)

Option Description
When simulating, vary If you enable this option, power supplies for ICs with IBIS
voltage reference values models that you specified to use internal power-supply values
with IC corners follow the IC modeling corner option on the oscilloscope.
Power supplies for other ICs use the typical value specified in
the IC model or use external power-supply net value.

If you disable this option, IC power supplies use the typical

value specified in the IC model or use the external power-
supply net value. The power-supply editor determines the
voltage for each power-supply net.

This option does not apply to the following:

• Power supplies for ICs with non-IBIS models
• Power supplies for ICs with IBIS models that you
specified to use external power-supply nets.
• Batch simulation behavior.

See “Assigning Power Supplies to ICs” on page 478 and

“What IC Operating Settings Mean” on page 552.
Analysis options Area
Board temperature Specify the temperature to use for transmission line resistance
calculations made by the HyperLynx field solver.
SPICE temperature Specify the temperature to use with a .TEMP statement in
SPICE netlists created by HyeprLynx.

This value does not have an effect on transmission line

resistance calculations made by the HyperLynx field solver.
Use in SPICE simulations Select to write a temperature statement to the SPICE netlist,
using the SPICE temperature value.

For example, if the SPICE temperature is 27 C and you select

the Eldo/ADMS simulator in the Digital Oscilloscope, the
SPICE nelist contains the following statement:

.temp 27.000000
Default Driver Characteristic Area

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 Dialog Boxes
Preferences Dialog Box - General Tab

Table 34-19. General Tab Contents (cont.)

Option Description
Rise/Fall Time Enter, in nanoseconds, the time in which the default driver IC
switches high and low (0%-100%, not 10%-90% or 20%-
80%).

Tip: If the rise and fall times differ, enter the faster of the two.

Caution: This box and the Rise/Fall Time box on the Default
IC Model Setting dialog box (BoardSim > Setup > Crosstalk
Thresholds > Change Default IC Model button) are linked.
Editing either box automatically update the value in the other
box.

HyperLynx uses the default rise/fall time for several types of

analysis. The Terminator Wizard uses this information when
evaluating nets for signal-integrity violations when no driver
has been assigned to the nets. The Via Visualizer uses this
information to calculate the knee frequency (Fknee) and other
electrical properties of a via.

See “Driver Models Versus Default Slew Rate” on page 960.

Related Topics
“Preferences Dialog Box” on page 1791
Configuring the HyperLynx Environment

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Dialog Boxes
Preferences Dialog Box - LineSim Tab

Preferences Dialog Box - LineSim Tab

To access: Setup > Options > General - LineSim Tab
Use this tab to specify LineSim-specific preferences.

Figure 34-21. Preferences Dialog Box - LineSim Tab

Table 34-20. LineSim Tab Contents

Option Description
Default trace separation Area
Trace to trace Specify the default trace-to-trace a separation to use when you
add a transmission line to a coupling region.

Note: Setting the value here also changes the Trace to trace
value on the BoardSim tab.
Trace to plane Specify the default trace-to-plane separation to use when you
add a transmission line to a coupling region.

Note: Setting the value here also changes the Trace to plane
value on the BoardSim tab.
Options for creating coupled transmission lines Area

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Preferences Dialog Box - LineSim Tab

Table 34-20. LineSim Tab Contents (cont.)

Option Description
Enable advanced coupling See Normal Versus Advanced Coupling Modes in Cell-Based
mode Schematic Editor.
Transmission line info Area
Show net name Select to display, in the free-form and cell-based schematic
editors, the net associated with each transmission line. The net
name is automatically created and you cannot edit it.

Related Topics
“Preferences Dialog Box” on page 1791
“Precedence Among Anti-Pad Clearances - LineSim” on page 1393
Configuring the HyperLynx Environment

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Dialog Boxes
Preferences Dialog Box - Oscilloscope Tab

Preferences Dialog Box - Oscilloscope Tab

To access: Setup > Options > General - Oscilloscope Tab
Use this tab to specify the properties used by the oscilloscope when it opens.

Figure 34-22. Preferences Dialog Box - Oscilloscope Tab

Table 34-21. Oscilloscope Tab Contents

Option Description
Operation Area — Controls the way waveforms display in the oscilloscope.
Standard Select to display waveforms over the full simulation time.

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Preferences Dialog Box - Oscilloscope Tab

Table 34-21. Oscilloscope Tab Contents (cont.)

Option Description
Eye Diagram Select to display waveforms over the bit interval by cutting up
the waveform into bit-interval lengths and overlaying them. Eye
diagrams are a standard way of judging communications
channels.

Requirement: The Advanced Scope license is required to run

eye diagram simulation.
Driver Waveform Area — Select the type of waveform stimulus the driver applies.
Edge / Osc • Edge — Select to set up an edge stimulus.
• Osc — If the oscilloscope operation is set to Standard, the
stimulus is a repetitive clock waveform. If the oscilloscope
operation is set to Eye Diagram, the stimulus is toggling.
Rising Edge / Falling Edge • Rising edge — Applies a rising edge waveform stimulus.
• Falling edge — Applies a falling edge waveform stimulus.
Stimulus Area — Specify stimulus options.
General Apply a global stimulus. Global stimulus is where you define a
single driver waveform and the oscilloscope automatically
assigns it to all driver pins. In BoardSim, global stimulus is
applied to all driver pins on the selected net and its associated
nets. In LineSim, global stimulus is applied to all driver pins in
the free-form or cell-based schematic.
Per net/pin Per-net/pin stimulus is where you define multiple driver
waveforms and manually assign them to specific driver nets
(BoardSim) or pins (LineSim).

Per-net/pin stimulus enables you to simulate timing relationships

among nets/pins, such as the following:
• Crosstalk investigations with different waveforms on
aggressor nets, to help examine the pattern dependency of
crosstalk
• Source-synchronous signaling, such as DDRx and similar
technologies, where one IC transmits both the clock and data
signals (as opposed to a master system clock, which is
transmitted by a different IC) with typically slightly different
timing
Restriction: The oscilloscope supports per-net/pin stimulus for
standard and eye diagram operation modes. FastEye diagrams
do not use per-net/pin stimulus.
Oscillation Parameters Area — Default oscillator properties. The oscilloscope saves
oscillator frequency and duty cycle data on a per-pin basis when you set their values
interactively.

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Preferences Dialog Box - Oscilloscope Tab

Table 34-21. Oscilloscope Tab Contents (cont.)

Option Description
Frequency Frequency of oscillator.
Duty Cycle The percentage of the period that the driver is high.
IC Modeling Area — Controls the default option for IC modeling during simulation in
the oscilloscope.
Slow-Weak See “Setting IC Operating Parameters” on page 551.
Typical See “Setting IC Operating Parameters” on page 551.
Fast-Strong See “Setting IC Operating Parameters” on page 551.
Show Area — Select objects to display in the Oscilloscope window.
Overview pane Select to display the Overview pane. The overview pane may
help you to visually relate the waveforms displayed in the main
screen to the entire simulation. The overview pane always shows
the waveforms for the entire simulation. The portion of the
overall simulation displayed in the main screen is marked by a
green hatched pattern in the overview pane.

See “Overview Pane” on page 562.

Readout text Select to display the horizontal scale, vertical scale, horizontal
delay, and vertical offset values on the main oscilloscope screen,
in white text. You can disable the settings readout to reduce
clutter on the main oscilloscope screen.
Eye mask Select to display the eye mask in the display for the oscilloscope.
Loaded results --
Previous results --
Latest results --
Mark data points Affects the size of the data points drawn on the main screen.
Typically, the data points are not visible until you zoom way in.
Vertical Area — Default display position and scale.
Position Use the vertical position option to shift the waveforms, and the
green 0.0 V ground position marker, in the main screen up or
down relative to the grid.

The vertical position creates a voltage offset by adding or

subtracting voltage to or from the simulation data. When
changing the vertical position, the grids remain stationary while
the waveforms and ground marker move up and down.
Scale Vertical voltage scale.

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Preferences Dialog Box - Oscilloscope Tab

Table 34-21. Oscilloscope Tab Contents (cont.)

Option Description
Horizontal Area — Default display delay and scale. These values affect how the
simulation runs.
Delay Enables you to align a specific simulation time to the left edge of
the main oscilloscope screen when simulation completes. For
example, if the horizontal delay was set to 25ns when you
clicked the Start Simulation (or Start Sweeps) button, the
waveforms corresponding to the simulation time of 25ns are
aligned to the left edge of the main oscilloscope screen when
simulation completes.

For standard oscilloscope operation, the Horizontal Delay

control only affects the waveform display for the next
simulation; it has no effect on the latest waveform display.

For eye diagrams, you can use the Horizontal Delay control to
center the eye in the oscilloscope.

The allowed horizontal delay range is 0ns to 1000.000ns, with a

precision of 1ps.
See also: “How Horizontal Scale and Delay Settings Affect
Simulation” on page 561
Scale The horizontal scale and horizontal delay settings together
determine the simulation end/stop time. The oscilloscope
instructs the simulator to generate data for ten horizontal time
divisions plus the horizontal delay that you specify.

When you click the Start Simulation or Start Sweeps button, the
oscilloscope calculates the number of data points the simulator
will generate based partly on your horizontal scale and
horizontal delay settings. If your computer has insufficient
memory to record the simulation results, the oscilloscope will
issue a warning and not start the simulation.

The horizontal scale setting typically does not affect the

simulation timestep because it is just one of several factors used
by BoardSim/LineSim to calculate the simulation timestep.
However, a very small horizontal scale value can decrease the
simulation timestep.

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Preferences Dialog Box - Oscilloscope Tab

Table 34-21. Oscilloscope Tab Contents (cont.)

Option Description
In Standard operation, Enable this option to record simulation results for only the
record data only for probes probes you enable prior to starting simulation. You might enable
with check marks this option to speed up simulation or avoid memory errors
caused by storing simulation results for all probes.

In standard operation, the oscilloscope automatically assigns

probes to all pins in the design (LineSim) or all pins on the
selected and associated nets (BoardSim). If you disable this
option, the oscilloscope stores waveform data for all probed pins
(even for probes that were disabled prior to starting simulation).
which enables you to view their waveform data without having
to re-simulate.

Related Topics
“Preferences Dialog Box” on page 1791
“Simulating Signal Integrity with the Oscilloscope” on page 533
Configuring the HyperLynx Environment

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 Dialog Boxes
Preferences Dialog Box - Power Integrity Tab

Preferences Dialog Box - Power Integrity Tab

To access: Setup > Options > General - Power Integrity Tab
Use this tab to specify options for power-integrity simulations.

Figure 34-23. Preferences Dialog Box - Power Integrity Tab

Table 34-22. Preferences Dialog Box - Power Integrity Tab Contents

Option Description
High-accuracy mode Make the simulation grid twice as dense as standard for all types
of power-integrity analysis, including time domain (FDTD),
frequency domain and DC Drop simulation.
DC drop options Area

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Preferences Dialog Box - Power Integrity Tab

Table 34-22. Preferences Dialog Box - Power Integrity Tab Contents (cont.)
Option Description
Separate nets if resistor In a PCB design, power-supply nets can be connected to each
exceeds other by the resistors. These resistors are either small, assuming
that both nets actually form a single power supply circuit or the
resistors are huge, to prevent DC current from flowing between
nets with different supply voltages. Nets connected by a resistor
with a value equal to or greater than the specified value are
simulated separately. Nets with resistors smaller than this value
are considered electrically connected and are simulated as one
unit.
Frequency- and time-domain analysis options (not DC drop) Area
Minimum void size Simulation ignores voids smaller than Minimum void size.
Generally, the presence of small voids does not significantly
affect wave propagation in the planar waveguides, but taking them
into account leads to a large impact on memory and performance.
A default value of 120 mils (3 mm) is chosen so that most small
voids (antipads) are ignored. However, in certain circumstances it
is interesting to see how the presence of voids (especially when
they are numerous and densely distributed) affects the simulation;
in this case it makes sense to decrease the value to, say, 10 mil and
see what happens.
Minimum metal-area size Simulation ignores metal shapes smaller than Minimum metal-
area size * Minimum metal-area size.

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Preferences Dialog Box - Power Integrity Tab

Table 34-22. Preferences Dialog Box - Power Integrity Tab Contents (cont.)
Option Description
Default separation between Define the default distance between an IC power pin and the
IC power and reference pins ground pin that provides its return current. This value is used
when distributed decoupling analysis and signal-via bypass
analysis cannot find a pin on the reference net near the pin to
which you assigned an AC current sink model. The return current
pin must be on the same component and connect to a transmission
plane that interacts with the pin with the AC current sink model.

Define a value that will exist for the power consumer ICs on the
board you are most interested about. For many BGAs you can set
this value to the ball-to-ball pitch, because most large BGA
pinouts locate at least one ground pin next to each power pin. For
example, if the BGA uses a 1 mm ball-to-ball pitch, it is very
likely that any power pin would have at least one ground pin 1
mm away.

Distributed decoupling analysis and PDN S-parameter model

exporting use this value to calculate the inductance of the
differential portion of the power-supply pin mounting vias.

In LineSim, you can override this value. See “Add/Edit IC Power

Pin(s) Dialog Box” on page 1421.
Automatically assign De-select to the make the check boxes located in the Set
reference layers Reference Nets Dialog Box available for selecting and
deselecting.

Advanced customers may want detailed control over which

reference layers to include in the PI simulation circuit.

This option applies to BoardSim only. You always manually

assign reference layers in the LineSim PDN Editor.

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Dialog Boxes
Preferences Dialog Box - Power Integrity Tab

Table 34-22. Preferences Dialog Box - Power Integrity Tab Contents (cont.)
Option Description
Pin-to-area connection decoupling capacitor mounting is the connection between
search distance (BoardSim) decoupling capacitor pins and the metal areas that form
transmission planes. The quality of this connection determines
how well the capacitor can store and release energy for the local
power-distribution network (PDN) at medium and high
frequencies.

When BoardSim creates the electrical circuit for AC power-

integrity analysis, you can use this option to influence the portion
of the circuit that represents decoupling capacitor mounting.

This option takes into account the distance between the

decoupling capacitor pin and the metal area that forms part of the
transmission plane and has the following effects on the electrical
circuit:
• If the distance is less than the specified value, BoardSim
calculates the impedance of this connection and adds it to the
electrical circuit.
• If the distance is more than the specified value, BoardSim
assumes an “ideal” connection of the pin, at its present
location, to the metal area and the related transmission plane.
In this case, “ideal” means that the electrical circuit contains
the decoupling capacitor's capacitance and not its mounting
inductance.

Similarly, if there is no physical connection between the

decoupling capacitor pin and the metal area, BoardSim
assumes an “ideal” connection of the pin, at its present
location, to the metal area and the related transmission plane.
This behavior supports the early stages of PCB layout, where
the decoupling capacitors are placed, but detailed routing
connections have not yet been made.

• If the specified value is 0.0, BoardSim calculates the

impedance of this connection, no matter how long the distance
is. It only uses an “ideal” connection to model decoupling
capacitors that have no connection to the metal area.
Advanced - Plane-noise and co-simulation grid (FDTD) Area

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 Dialog Boxes
Preferences Dialog Box - Power Integrity Tab

Table 34-22. Preferences Dialog Box - Power Integrity Tab Contents (cont.)
Option Description
Define Grid Define the grid for the FDTD simulator. The grid size affects
simulator spatial resolution and performance (more resolution =
less performance).
• Auto — Sets the grid size to a value that the simulator to a
default value that is good for most designs. Choosing Auto is
strongly recommended.
• By Cell size — Sets the grid based on the X/Y size of the cells.
• By Dimension — Sets the grid based on the number of cells
used to cover the board in the X and Y dimensions. Note that
even though you enter the X and Y dimensions separately, the
simulator adjusts them to make the cells approximately square
because geometrically unbalanced cells lead to internal trouble
during simulation.

Related Topics
“Preferences Dialog Box” on page 1791
Configuring the HyperLynx Environment

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Dialog Boxes
Reporter Dialog Box

Reporter Dialog Box

To access: This dialog box automatically opens to display simulation results or messages. To
manually open this dialog box to display individual report and log files:
• To open the most-recently displayed report for the current session, click View
Simulation Reports or select View > PI Simulation Reports > Open Most
Recent.
Restriction: This menu item is unavailable unless you have run a simulation or analysis
in the current BoardSim/LineSim session.
• To open a report for the loaded design that has been simulated in the current session,
select View > PI Simulation Reports > <simulation_or_export_type>.
Restriction: The <simulation_or_export_type> menu item, such as “DC Drop
Simulation” is unavailable if you have not run that type of simulation on the currently-
loaded design.
• To open any report, select View > PI Simulation Reports > Open.
The location of report files varies. See the following:
“Data Flow for DC Drop - Interactive Simulation” on page 991
“Data Flow for DC Drop - Batch Simulation” on page 993

Note
This dialog box automatically looks for report and log files located in the <design> folder
for the currently-loaded design. See “About Design Folder Locations” on page 1391. You
can override this behavior and browse for files located in other folders.

Description
Use this dialog box to display the contents of power-integrity simulation result (.TXT) and log
(.LOG) files. These files are formatted in pseudo-XML syntax that enables the Reporter to
cross-probe to the BoardSim board viewer, display simulation spreadsheet files, and so on.
For information about mapping DC drop simulation circuit elements to terms used in this report,
see “DC Drop Conceptual Circuits” on page 979.

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 Dialog Boxes
Reporter Dialog Box

Figure 34-24. Reporter Dialog Box

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Dialog Boxes
Reporter Dialog Box

Table 34-23. Reporter Dialog Box Contents

Control or Field Description
Report text Contains simulation messages and results. The contents and
formatting depend on the following:
• The type of simulation or analysis you have run
• The type of file: result or log

X/Y coordinates provide the location of pins and other geometric

structures in the board viewer or PDN Editor window.

In BoardSim, coordinate and component text cross-probes to the

board viewer or to the DC Drop Analysis pane (if it has focus). Click
the hyperlinked text to zoom and pan to the coordinate or component,
and then use a dashed line to highlight the component outline.

Note: To stop highlighting the component in the board viewer, right-

click an empty area in the viewer and click Unhighlight
Component.

In LineSim, coordinates and components in LineSim are plain text.

Positive current values mean that current flows into the pin or via.

Voltage values represent the absolute voltage at the pin or via.

Warnings Clear to hide warnings or information messages.
Information
Restriction: These options are unavailable for DC voltage drop
simulation results.

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 Dialog Boxes
Reporter Dialog Box

Table 34-23. Reporter Dialog Box Contents (cont.)

Control or Field Description
Units Dynamically switch between English and metric lengths.

This setting does not affect global units, which is set in the Units
Dialog Box.
Help --
Close --
Related Topics
“DC Drop Example Textual Report” on page 1005

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Dialog Boxes
Restore Session Edits Dialog Box

Restore Session Edits Dialog Box

To access: Open a BoardSim board that you previously opened and made interactive changes to.
BoardSim saves your interactive board changes, such as IC output buffer enable/disable settings
and stackup edits, to the BoardSim User Data session file (.BUD). When BoardSim has finished
loading your board, and is about to load the .BUD file, it opens this dialog box and asks you
whether you want to load the edits in the session file and, if so, which ones. This enables
BoardSim to load the contents of the board file into its database, and then supplement the
database with additional information from the session file.
BoardSim keeps the last two versions of the session file. The .BUD file contains the most recent
set of changes. The .BBD file (backup .BUD file) contains the second most recent set of
changes. When a .BUD file exists and you exit BoardSim or manually save your interactive
changes (File > Save BoardSim Session File), BoardSim renames the current .BUD file by
changing the file name extension to .BBD, and then writes the .BUD file.

Figure 34-25. Restore Session Edits Dialog Box

Table 34-24. Restore Session Edits Dialog Box Contents

Option Description
Stackup Restore stackup settings, such as geometric or
electrical property edits.
Component data Restore interactive component settings, such as
per-pin IC model assignments and passive
component value edits.

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 Dialog Boxes
Restore Session Edits Dialog Box

Table 34-24. Restore Session Edits Dialog Box Contents (cont.)

Option Description
Manhattan routes Restore Manhattan routing. See “Simulating
Unrouted Nets with Manhattan Routing”.

Restrictions:
• The Manhattan Routing check box is
unavailable when you clear the Stackup
check box. Because you can interactively
add a stackup layer, then use that new layer
for Manhattan routing, it is only safe to
restore Manhattan routing edits when the
stackup edits are also restored.
• Unrouting changes are not saved in the
.BUD file. For example, if you unroute a
net without re-routing it, the unrouting
changes will be absent when you reload
your board.
Quick Terminators Restore Quick Terminators. See “About Quick
Terminators”.
Previous Load session edits from the most recent
session file (.BUD).
Backup to previous Load session edits from the second most recent
session file (.BBD).

You might want to load the .BBD file instead

of the .BUD file if, for example, you
accidentally saved data from your last session
that you consider “throw-away”. Then the
.BUD file contains data you do not want, and
the .BBD file is preferred.

Related Topics
BoardSim Session Files

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Restore Session Edits Dialog Box

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Save Model As Dialog Box
To access:
Dialog Boxes

• From the Assign / Edit Capacitor Model Dialog Box, click Save As.
• From the Assign / Edit Capacitor Model Dialog Box, select <custom model> from the
Library list and click Save.
Use this dialog box to create new library files and to add models to existing library files.

Figure 35-1. Save Model As Dialog Box

Table 35-1. Save Model As Contents

Option Description
Library • Select the library you want to save the model to or select
<new library> to create a new library file.
• <new library> — Opens the Create new Decoupling Library
dialog box. Select the Library folder from the Select Library
folder list and enter a name for the new library in the Enter
Library name field.
Model Name Enter or select a model name. Models are saved to the selected
library file.

Related Topics
Assign / Edit Capacitor Model Dialog Box

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Dialog Boxes
Select Active Layers Dialog Box

Select Active Layers Dialog Box

To access: Click Select Active Layer(s) .
Use this dialog box to select the layer you want to place objects on in the PDN Editor and to
select which layer(s) to display. Some symbols can exist only on specific layers. For example,
when adding copper voids, you indicate on which plane layer(s) the copper void exists. To
accomplish this, you specify the active layer(s) before you add the symbol to the PDN or when
you select it for editing. For example, to locate a new void area on the stackup layer named
TOP, you set the active layer to TOP and add the void area symbol.
The following symbols use active layer settings:
• Copper Areas
• Void Areas

Figure 35-2. Select Active Layers Dialog Box

Table 35-2. Select Active Layers Dialog Box Contents

Field Description
Show Put a check mark in this column to display symbols on the
corresponding layer in the PDN Editor.
Active Put a chicanery in this column to set the layer to Active. Copper
and Void areas are placed on the active layer(s). See Adding Void
or Copper Areas.
Layer Name Displays the name of the layer.
Type Display the type of layer.
Show All Select to display all layers in the PDN Editor.

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Select Active Layers Dialog Box

Table 35-2. Select Active Layers Dialog Box Contents (cont.)

Field Description
Hide All Select to hide all layers in the PDN Editor.
All Plane Select to make all plane layers active.
All Signal Select to make all signal layers active.
Related Topics
Adding Void or Copper Areas
Defining the Power-Distribution Network

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Select Directories for IC-Model Files Dialog Box

Select Directories for IC-Model Files Dialog Box

To access: Setup > Options > Directories, from the Model library file path(s) area, click Edit.
Use this dialog box to specify one or more directories on the computer or network that contain
IC models available for use in BoardSim or LineSim.
LineSim searches the directories you specify to find connector models (.SLM files). See “Edit
Transmission Line Dialog Box - Connectors Tab” on page 1559.

Figure 35-3. Select Directories for IC-Model Files

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 Dialog Boxes
Select Directories for IC-Model Files Dialog Box

Table 35-3. Select Directories for IC-Model Files Contents

Option Description
Add Click to add a single directory. This opens the Browse for
Folder dialog box. Type or browse to the directory and click
OK.

If the added directory contains sub-directories, those sub-

directories are not added to the model-search path.
The directory is added to the bottom of the list and has the
lowest precedence.
Add with Subdirectories Click to add a directory and all of its subdirectories. This opens
the Browse for Folder dialog box. Type or browse to the
directory and click OK.

The parent directory and its subdirectories are added to the

bottom of the list and have the lowest precedence.

Restriction: The Select Directories for IC-Model Files dialog

box does not support directory/subdirectory hierarchy, which
means it assigns the parent and subdirectories to a simple flat
list of directories.
Delete Deletes the selected directories. If you delete all directories, the
default directory is used.
Up Increases the precedence of the selected directory.
Down Decreases the precedence of the selected directory.
Import Loads model directory information from another project,
computer, or design kit.

Opens the Library Path File dialog box. Do one of the

following and click Open:
• Browse to the previously-exported model path file. This
option is useful when transferring library values from one
project or computer to another.
• Browse to the BSW.INI file with a [BSW_LIBRARY]
section containing the model file directories to use. This
option is useful when transferring library values from one
installation of HyperLynx to another. BSW.INI is located
in the hyperlynx folder, such as
C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx.

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Select Directories for IC-Model Files Dialog Box

Table 35-3. Select Directories for IC-Model Files Contents (cont.)

Option Description
Export Saves model directory settings to an
<exported_model_directory_setting_file>.ini file so you can
share information with other users.

The default export directory is taken from the .HYP, .TLN, and
.FFS file path area in the Set Directories Dialog Box.
Generate Model Index Click to generate the model finder index. This generates
HyperLynxIcModels.csv. Do this whenever you add directories
or change the precedence of directories in the Select IC Model
dialog box. Generating the model finder index makes the
newly-available IC models available in the model-finder
spreadsheet.

The model finder index is a database, in comma-separated-

values format, that is named HyperLynxIcModels.CSV. When
you update the model finder index, it is written to the model
directory with the highest precedence. This behavior produces
multiple HyperLynxIcModels.csv files if you change the
model directory with highest precedence.

Related Topics
”Configuring the HyperLynx Environment”

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 Dialog Boxes
Select Directories for Stimulus Files Dialog Box

Select Directories for Stimulus Files Dialog Box

To access: Setup > Options > Directories, from the Stimulus file path(s) area, click Edit.
Use this dialog box to specify one or more directories on your computer or network that contain
stimulus files (.EDS).

Figure 35-4. Select Directories for Stimulus Files

Table 35-4. Select Directories for Stimulus Files Contents

Option Description
Add Click to add a single directory. This opens the Browse for
Folder dialog box. Type or browse to the directory and click
OK.

If the added directory contains sub-directories, those sub-

directories are not added to the model-search path.
The directory is added to the bottom of the list and has the
lowest precedence.

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Dialog Boxes
Select Directories for Stimulus Files Dialog Box

Table 35-4. Select Directories for Stimulus Files Contents (cont.)

Option Description
Add with Subdirectories Click to add a directory and all of its subdirectories.This opens
the Browse for Folder dialog box. Type or browse to the
directory and click OK.

The parent directory and its subdirectories are added to the

bottom of the list and have the lowest precedence.

Restriction: The Select Directories for Stimulus Files dialog

box does not support directory/subdirectory hierarchy, which
means it assigns the parent and subdirectories to a simple flat
list of directories.
Delete Deletes the selected directories. If you delete all directories,
the default directory is used.
Up Increases the precedence of the selected directory.
Down Decreases the precedence of the selected directory.
Import Loads stimulus directory information from another project,
computer, or design kit.

Opens the Library File Path dialog box. Do one of the

following and click Open:
• Browse to the previously-exported stimulus path file. This
option is useful when transferring library values from one
project to another.
• Browse to the BSW.INI file with a [BSW_LIBRARY]
section containing the stimulus file directories to use. This
option is useful when transferring library values from one
installation of HyperLynx to another. BSW.INI is located
in the hyperlynx folder, such as
C:\MentorGraphics\<latest_release>\SDD_HOME\hyper
lynx.
Export Opens the Library File Path dialog box. Enter a stimulus path
file name to save library paths to a file.

Related Topics
”Configuring the HyperLynx Environment”

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 Dialog Boxes
Select Method of Simulating Vias Dialog Box

Select Method of Simulating Vias Dialog Box

To access: Load a design in BoardSim and select Setup > Via Simulation Method.
BoardSim can automatically calculate via inductance and capacitance or you can manually
specify via inductance and capacitance to BoardSim. These options enable you to simulate the
effects of padstacks in the current PCB layout and to perform "what if" experiments to simulate
the effects of changed padstacks.
When you choose to include or exclude via models from simulation, all of the following
functions respect your choice:
• Interactive simulation
• Terminator Wizard
• Board Wizard
• Export to SPICE (using the SPICE Writer option)
• Export BoardSim net to LineSim
Via Visualizer results are best suited for the auto-calculate via simulation option. If you enable
either of the user-supplied via simulation options, the Via Visualizer displays approximate via
electrical properties, based on the values you supply.
BoardSim stores your via simulation settings in the session edit file. If you change the settings,
be sure to set them to the values you want to use for future sessions before exiting BoardSim.
Note
Via simulation options described in this topic apply only to BoardSim.

Caution
Via simulation options in this dialog box are ignored when you enable the “Simulate t-
planes” option in the oscilloscope. See “Co-Simulation - Modeling Interactions Between
Signal Vias and Transmission Planes” on page 577.

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Select Method of Simulating Vias Dialog Box

Figure 35-5. Select Method of Simulating Vias Dialog Box

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 Dialog Boxes
Select Method of Simulating Vias Dialog Box

Table 35-5. Select Method of Simulating Vias Dialog Box Contents

Option Description
Include via L and C Enable or disable via modeling.

You can also enable and disable via modeling by clicking the
Enable Via Modeling button on the toolbar. The Enable
Via Modeling toolbar button reflects the Include via L and C
check box value, and vice versa.

Restriction: The Via Models license is required to enable via

modeling. Otherwise BoardSim can model a via only as a
lumped capacitance. To model vias as a lumped capacitance,
select the Include via C check box, and then click OK.
Add extra capacitance for For IC pins connected to a via not (note the disagreement with
SMD pads if via-in-pad the option label) inside an SMD pad, model the capacitance of
the SMD pad. The Via Visualizer displays the via modeling
as a network of transmission lines and capacitors.

Restrictions:
• This option does not apply to IC pins that touch passive-
component pads.
• If multiple vias touch the component-pin pad, BoardSim
models only one of them.
• This extra capacitance is not included when you export the
net to LineSim.
Include via stub inductance Include the L from via stubs.
Via modeling method Area
Design file For a MultiBoard project, select the board you are specifying
settings for.

This option is only available for MultiBoard projects. You

must explicitly specify settings for each board in the project.

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Select Method of Simulating Vias Dialog Box

Table 35-5. Select Method of Simulating Vias Dialog Box Contents (cont.)
Option Description
Auto-calculate BoardSim extracts L/C values from padstack and trace
geometry data in the board file. BoardSim generates a via
model that takes into account the following geometric
properties:
• Layers on which connected traces enter and exit the via
• Layer positions and sizes of all pads in the padstack
• Positions of AC ground planes in the stackup
• Size of the antipads separating via barrels, or “tubes,”
from AC ground planes
• Fringing capacitance resulting from coupling between the
via barrel and AC ground layer
In addition, BoardSim takes into account changes in
impedance due to "differential vias," or via pairs that are
located near to each other and that are connected as a
differential pair. BoardSim recognizes that differential vias
generally have decreased L and automatically adjusts the
calculated L. BoardSim does not take into account the
reduced impedance due to local decoupling capacitors.
User-supplied global L and You supply one set of L/C values for all padstacks. The L/C
C you provide represents the L/C for each padstack, and the L/C
is converted into a transmission line with the equivalent Z0
and delay values.

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Select Method of Simulating Vias Dialog Box

Table 35-5. Select Method of Simulating Vias Dialog Box Contents (cont.)
Option Description
User-supplied padstack - For padstacks that connect two or more signal layers, you can
specific L and C choose to provide L and C yourself or have BoardSim
calculate L and C. The spreadsheet displays the calculated L
and C that you can override on a per-padstack basis.

In the spreadsheet, the calculated L and C are based on the

full length of the via barrel. This means the same L/C values
are used for all instances of the padstack, regardless of which
layers are used for traces entering and exiting the via.
The spreadsheet does not contain unused padstacks or
padstacks connecting to only one signal layer.

You can scan the spreadsheet to identify padstacks with large

L or C values.

BoardSim does not take into account which layers are used by
traces to enter and exit the via. L and C values in the
spreadsheet correspond to the full length of the via.
To obtain C for the equivalent transmission line representing
the padstack, use the following equation:
• C (padstack transmission line) = C (total) - C (entry pad) -
C (exit pad)

Where:
• C (total) represents the value in the C cell of the
spreadsheet in this dialog box.
• C (entry pad) and C (exit pad) represent C of the outside
capacitors displayed in the Via Visualizer.

See also: “Viewing Via Properties” on page 1056

Related Topics
“Effects of Vias on Signal Integrity” on page 1055
“Viewing and Simulating Signal Vias” on page 1055
“Viewing Via Properties” on page 1056

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Dialog Boxes
Set Directories Dialog Box

Set Directories Dialog Box

To access:
• Models > Edit Model Library Paths
• Setup > Options > Directories or Models > Edit Model Library Paths
Use this dialog box to set the folder location for designs, models, stimulus, reports, and so on.

Figure 35-6. Set Directories Dialog Box

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Set Directories Dialog Box

Table 35-6. Set Directories Dialog Box Contents

Option Description
HYP, TLN, and FFS file path Area
The design file directory is shared among .HYP, .TLN, .FFS, and .CCE (CADCAM Professional
compressed and encrypted) files. The directory setting is a convenience and it specifies the
default directory for the Open File dialog box.

You can navigate to any directory in the Open File dialog box. This means that you can store
BoardSim board and LineSim schematic files anywhere you want, and in multiple directories if
you want.
Browse Use to select the directory you want to use as the default.

You can also type the directory path in the HYP, TLN, and FFS
file path area.

Requirement: You must disable Use directory of last-opened file

before clicking Browse or editing the path.
Default Restores the directory to its default value.

Requirement: You must disable Use directory of last-opened file

before clicking Default.
Use directory of last-opened Select the check box to always use the directory from which you
file last loaded a .HYP/.TLN/.FFS/.CCE file (rather than a particular
"fixed" directory).

Clear the check box to modify the directory.

Model-library file path Area
Edit Opens the Select Directories for IC-Model Files Dialog Box. Use
this dialog box to specify one or more directories on the computer
or network that contain IC models available for use in BoardSim
or LineSim.
Default Deletes all existing model directory values and specifies the
directory that shipped with HyperLynx.
Boardsim qualified parts list file(s) (QPL) Area

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Set Directories Dialog Box

Table 35-6. Set Directories Dialog Box Contents (cont.)

Option Description
Add File Opens the Choose a File to Add to QPL Path dialog box. The
Choose A File To Add To QPL Path dialog box opens. Select a
file by double-clicking it, or selecting it and clicking Open. The
new file path has lowest precedence. You can also add files by
typing the .QPL file path into the Qualified Part File(s) box. If
you specify multiple file paths, use a semicolon ; to separate them.

BoardSim can read multiple .QPL files from different directories

on the computer or network. For example, you can use the files
\\central_CAD\vendorFiles\master.qpl, which is maintained by a
central CAD group, and
C:\MentorGraphics\<latest_release>\SDD_HOME\hyperlynx\Hy
pFiles\project.qpl, which supplements or corrects the CAD
group's IC mapping for your project.

Directory paths can be absolute or relative. The examples above

illustrate absolute directory paths. To use the relative path
approach, store the .QPL file(s) in the directory specified in the
Model Library File Path box in this dialog box, then precede the
.QPL file name with ".\", such as .\foo.qpl.

Precedence among the .QPL pathnames decreases from left to

right in the Qualified Part File(s) text box; the left-most .QPL
pathname has the highest precedence.
Default Erases all text in the Qualified Part File(s) text box and replaces it
by .\default.qpl. The directory is set in the Model-library file path
Area.
Use QPL file(s) to assign Enables QPL file automapping.
models
Stimulus file path(s)
Edit --
Default --
Most recently used files Area
Limit list Enter the maximum number of files to display in File > Recent
Files area.

If the box is blank, the default maximum of eight is used.

Reports and log files directory - Use this area to set the location for report and log files.
This capability enables you to use separate directories for designs and outputs from
simulation.

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Set Directories Dialog Box

Table 35-6. Set Directories Dialog Box Contents (cont.)

Option Description
Browse Select to specify a non-project directory.

Restriction: The Browse button is unavailable if the Use Project

Directory For Reports And Log Files check box is selected.
Default Restores the default directory.
Use project directory for Select the check box to use the same directory that is specified in
reports and log files the .HYP, .TLN, and .FFS file path box.

Clear the check box to specify a non-project directory. Then type

or browse to the directory.

Related Topics
”Configuring the HyperLynx Environment” - LineSim
”Configuring the HyperLynx Environment” - BoardSim

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Dialog Boxes
Set Reference Nets Dialog Box

Set Reference Nets Dialog Box

To access: Open the Assign Power Integrity Models Dialog Box - IC Tab and from the
Reference Net area click Assign
Use the Set Reference Net dialog box to identify the net that provides return current paths for
the selected power-supply pin(s).
Caution
The list of reference layers may change within a BoardSim session. If you manually
override anti-pad geometries, copper voids are re-created for POLYGON records in the
.HYP file and may cause the set of reference layers to change. See “Setup Anti-Pads and
Anti-Segments Dialog Box” on page 1860 and “Metal-Area and Padstack Usage for PI
Analysis” on page 1398.

Table 35-7. Set Reference Nets Dialog Box Contents

Field Description
Reference Net list Select the net that provides return current paths for the IC
power-supply pin(s) you selected in the Assign Power
Integrity Models Dialog Box - IC Tab.

Tip: You can use the keyboard up/down arrow keys to

navigate through the list of reference nets.

The value “multiple” appears in this list when, in the

Assign Power Integrity Models Dialog Box - IC Tab, you
select multiple IC power-supply pins that (as a group)
belong to more than one power-supply net.
Available Reference Layers Stackup layers that contain metal areas on the reference
net that can provide return current paths for the selected IC
power-supply pin(s).

The check boxes are automatically selected and are

readonly. If you want detailed control over which
reference layers to include in the PI simulation circuit, by
clearing check boxes in this dialog box, clear the
Automatically assign reference layers option in
Preferences Dialog Box - Power Integrity Tab.

If the list is empty, text in the Hint area provides the

reason.

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Set Reference Nets Dialog Box

Related Topics
“Assign Reference Nets When Assigning VRM Models and Running AC Power-Integrity
Simulation” on page 1473

“Required Power-Integrity Model Assignments” on page 348

“Assigning Power-Integrity Models - BoardSim” on page 351

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Setup Anti-Pads and Anti-Segments Dialog Box

Setup Anti-Pads and Anti-Segments Dialog Box

To access: Open Design > Setup > Anti-Objects
This menu item is unavailable for the following conditions:
• BoardSim—Both of the following conditions are true:
o The .HYP file contains no area shapes of type PLANE.
o You have not assigned a power-supply net to any plane layers in the Edit Power-
Supply Nets dialog box. See “Editing Power-Supply Nets”.
Restriction: For MultiBoard projects, the above conditions must be true for all
boards.
• LineSim—The PDN Editor window is not selected, such as when it is behind the free-
form schematic window.
Use this dialog box to specify clearances among objects on the same stackup layer. Clearances
created by anti-pads in the board file and the PDN Editor are used for accurate power-integrity
simulation and PI/SI co-simulation, and for board display. BoardSim also uses anti-segment
information when simulating and displaying boards.
In BoardSim, processing this information for a very large board can noticeably increase
simulation and viewing times, depending on the way the .HYP file defines plane shapes. You
can disable the simulation and display of anti-pads and anti-segments. You might do this
temporarily to speed up preliminary investigations and simulations.

Figure 35-7. Setup Anti-Pads and Anti-Segments Dialog Box

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Setup Anti-Pads and Anti-Segments Dialog Box

Table 35-8. Setup Anti-Pads and Anti-Segments Dialog Box Contents

Option Description
Show anti-objects in board Select to display anti-pads and anti-segments in the board
viewer (worst performance) viewer or PDN Editor.

In BoardSim, anti-pads are always displayed when the .HYP

file contains explicit anti-pad geometry information, even if
you clear this check box.

In BoardSim, this option links to the Anti-Object option in the

View Options Dialog Box, so these two options always have
the same value.
Use anti-objects in PI Select to use clearances formed by anti-pads and anti-
simulation (better accuracy, segments in power-integrity simulation.
worst performance)
Force user-defined Select to override clearance information contained in the
clearances board file or PDN Editor padstack with global values you
define. The clearances you specify are applied to all pads and
trace segments in the design.
Anti-pad clearance If you enable Force user-defined clearances, define anti-pad
clearances.

The initial value comes from the Clearance field in the

Preferences Dialog Box - Default Padstack Tab (if you change
the value in one tab, it is automatically copied to the other
tab). When you save the design settings, the value in this
dialog box is saved to the .PJH file and overrides the value in
the Preferences dialog box.
Anti-segment clearance If you enable Force user-defined clearances, specify the
anti-segment clearance.

The initial value comes from the Trace to plane field in

Preferences Dialog Box - LineSim Tab or Preferences Dialog
Box - BoardSim Tab (if you change the value in one tab, it is
automatically copied to the other tab). When you save the
design settings, the value in this dialog box is saved to the
.PJH file and overrides the value in the Preferences dialog
box.

Advanced users can override clearances defined in the design. You might do this when running
“what if” power-integrity simulations and PI/SI co-simulations to see the effects of clearances
between via anti-pads and other metal shapes. The clearance values you provide apply to all

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Setup Anti-Pads and Anti-Segments Dialog Box

pads and trace segments in the BoardSim or PDN Editor design. These clearance values are not
used for trace separations in coupling regions in the free-form schematic editor.
Figure 35-8 shows how the display of an anti-pad in the board viewer changes in response to
visibility and clearance value options.

Figure 35-8. Example Anti-Pad Visibility and Clearance Options

Figure 35-9 shows how the display of anti-segments in the board viewer changes in response to
visibility and clearance value options. The metal areas are defined in the .HYP file as PLANE
types. If the metal areas had been defined as POUR types, the visibility and clearance value
options have no effect. Both PLANE and POUR types belong to the POLYGON record, which
belongs to the NET keyword.

Figure 35-9. Example Anti-Segment Visibility and Clearance Options

Related Topics
“Precedence Among Pad Sizes and Anti-Pad Clearances” on page 1391
“Precedence Among Anti-Segment Clearances” on page 1394
“Overlapping Anti-Pads That Isolate Metal Shapes” on page 1395
”Configuring the HyperLynx Environment”

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 Dialog Boxes
Specify Device Kit for Current Design Dialog Box

Specify Device Kit for Current Design Dialog Box

To access: Select Setup > Device Kit
Device kits typically contain advanced IC models and design examples that you simulate with
HyperLynx to learn about the technologies they implement. Device kits are not configured in
the shipping version of HyperLynx. Instead, device kits are shipped and installed separately
from HyperLynx. See the documentation provided with the device kit for installation and
configuration information.
Device kits provide <device_kit>.INI (application initialization) files containing model path
information and sometimes simulator environment information. HyperLynx uses the
<device_kit>.INI file model path information to automatically edit model library path settings
in the Set Directories Dialog Box.

Figure 35-10. Specify Device Kit for Current Design Dialog Box

Related Topics
”Configuring the HyperLynx Environment” - LineSim
”Configuring the HyperLynx Environment” - BoardSim

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Dialog Boxes
Specify DFE Dialog Box

Specify DFE Dialog Box

To access: FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page > select Add DFE and
Specify taps/weights > click Details
Use this dialog box to specify tap weight values for decision-feedback equalization (DFE)
circuitry in the receiver. You can specify tap weights by typing values in the spreadsheet or by
reading in a .TAPS file containing the tap weights synthesized by a previous run of the wizard.

Figure 35-11. Specify DFE Dialog Box

Table 35-9. Specify DFE Dialog Box

Option Description
Tap The zero row represents the main tap. The positive-numbered rows
represent post-taps.

For information about the assumed implementation of the DFE

structure, see “Pre-Emphasis and DFE Structures” on page 1599.

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Specify DFE Dialog Box

Table 35-9. Specify DFE Dialog Box (cont.)

Option Description
Weight Specify values for all taps implemented by the receiver.

Requirement: Specify all tap values for the range. For example, if
the receiver implements taps 0, 1, 2 and 3, you cannot omit the
values for taps 1 and 2.
Load Browse to a file (.TAPS) containing the tap weights synthesized by
a previous run of the wizard.

Related Topics
“FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page” on page 1596

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Specify Pre-Emphasis Dialog Box

Specify Pre-Emphasis Dialog Box

To access: FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page or > select Add driver
pre-emphasis and Specify taps/weights > click Details
Use the Specify Pre-Emphasis dialog box to specify tap weight values for pre-emphasis
circuitry in the driver. You can specify tap weights by typing values in the spreadsheet or by
reading in a .TAPS file containing the tap values synthesized by a previous run of the wizard.

Figure 35-12. Specify Pre-Emphasis Dialog Box

Table 35-10. Specify Pre-Emphasis Dialog Box

Option Description
Tap Negative-numbered rows represent pre-taps. The zero row
represents the main tap. Positive-numbered rows represent post-
taps.

For information about the assumed implementation of the pre-

emphasis structure, see “Pre-Emphasis and DFE Structures” on
page 1599.

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Specify Pre-Emphasis Dialog Box

Table 35-10. Specify Pre-Emphasis Dialog Box

Option Description
Weight spreadsheet cell Specify values for all taps implemented by the driver.

Requirement: Specify all tap values for the range. For example, if
the driver has the taps -2, -1, 0, 1, 2 and 3, you cannot you cannot
omit the values for taps -1, 0, 1, or 2.
Load Browse to a file (.TAPS) containing the tap weights synthesized
by a previous run of the wizard.

Related Topics
“FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page” on page 1596

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Dialog Boxes
Statistical Contour Chart Dialog Box

Statistical Contour Chart Dialog Box

To access:
• FastEye Channel Analyzer - View Analysis Results Page > select Statistical contours
and run analysis
• IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page > select Statistical
contours and run analysis
Use this dialog box to display a nested series of eye opening contours and their bit error rate
(BER). The color of the contour indicates its BER. Like bathtub curves, statistical contours
indicate the quality of sampling locations across the unit interval (UI, same as bit interval). An
advantage of statistical contours over bathtub curves is that the inner-eye contours display both
sampling time and voltage information.
The Y axis represents the sampling voltage and the X axis represents the sampling time in terms
of the unit interval (UI).

Figure 35-13. Statistical Contour Chart Dialog Box

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 Dialog Boxes
Statistical Contour Chart Dialog Box

Table 35-11. Statistical Contour Chart Dialog Box Contents

Option Description
Print the graph with a white background, which uses less printer
ink or toner.
Print (right-click)
Zoom in by doing the following:
1. Position the mouse pointer over one corner of the zoom box
Zooming (right-click) you want to create, and then drag to define the other corner
of the zoom box.
2. Release the mouse button to magnify the contents of the
zoom box to fill the graph.
Pan by dragging the graph across the dialog box.
Panning (right-click)
Attach measurement crosshairs to a waveform by clicking the
waveform to measure.
Track Cursor (right-click)
As you move the mouse horizontally, the measurement
crosshairs tracks the selected curve.
Fit the entire curve to window.
Fit to window (right-click)
Display only lines between curve vertices (no vertice dots).

Display only curve vertices (no lines).

Display both lines and vertice dots.

Open Help for the dialog box.

Copy (right-click) Copy graph to the clipboard and use a white background.

This option uses less printer ink or toner if you print it out.

You can paste the image from the Windows clipboard into
another program such as Microsoft WordPad.

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Statistical Contour Chart Dialog Box

Table 35-11. Statistical Contour Chart Dialog Box Contents (cont.)

Option Description
Copy inverted (right-click) Copy graph to the clipboard and use a black background.

You can paste the image from the Windows clipboard into
another program such as Microsoft WordPad.
Save As Save the numerical contour data to a file. You can open the file
with a spreadsheet application, such as Microsoft Excel.

Related Topics
“FastEye Channel Analyzer - View Analysis Results Page” on page 1628
“IBIS-AMI Channel Analyzer Wizard - View Analysis Results Page” on page 1756

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 Dialog Boxes
Surface Roughness Dialog Box

Surface Roughness Dialog Box

To access: Open Design > Setup > Roughness Parameters
Use this dialog box to quantify the effects of how the copper foil surface zigzags vertically away
from an averaged smooth surface. Simulators use roughness values to calculate conductor-
related transmission line losses. Loss increases as the depth of the surface roughness approaches
the skin depth of the signal current.
Enable this option only if the board uses a dielectric material with extremely low loss. This is
because the effects of surface roughness on simulation results are negligible on dielectric
materials with higher loss. For example, if the board uses FR-4 dielectric material and the
simulation applies high frequency stimulus (at which surface roughness begins to have a
measurable effect), surface roughness losses are negligible compared to dielectric losses.
You enable this option separately from the general lossy simulation option because it is useful
only for boards with advanced dielectric materials and because detailed surface roughness
information for copper foil can be hard to obtain. See“Editing Lossy Transmission-Line
Properties” on page 534.
You can evaluate the effects of surface roughness by comparing simulations based on the
surface roughness option enabled and disabled.

Figure 35-14. Surface Roughness Dialog Box

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Surface Roughness Dialog Box

Table 35-12. Surface Roughness Dialog Box Contents

Option Description
Layer Name The name of the stackup layer.
Type Specify the surface type:
• Rolled — Copper foil formed by repeatedly squeezing a
copper billet through a pair of rollers.
• Electrodeposited — Copper foil formed by
electrodepositing copper onto a rotating steel drum. The
side of the foil contacting the drum has the surface
roughness of the (usually smooth) drum and the other
side of the foil is rough and nodular.
• Custom — If you have reliable roughness Rq (rms)
values from the PCB vendor, select this option and type
the value into cells in the Roughness column. Otherwise
select one of the other options and use their default
values. For the definition of Rq, see “About the Surface
Roughness of Copper Foil” on page 1389.
• Unknown — Use this type when you do not have
roughness information for the board. For example, for a
multiple-board project, you may have roughness
information for one board, but not for another board.
Side Select the Treated check box for each side that is treated.
• Top
• Bottom
Treated This check box identifies the side(s) of the layer with
intentionally-increased surface roughness.
Roughness If you selected Custom from the Type column, type the Rq
(rms) value provided by the PCB fabrication vendor.

A cell with a blue background is read-only.

Board Select each unique board in the multiple-board project and
specify the surface roughness parameters. When the
Restriction: This option is multiple-board project contains multiple instances of a
only available for board, BoardSim applies the surface roughness value you
MultiBoard projects. set to all the instances.

If you do not have roughness information for a board, select

it and set the Type property to Unknown.

Related Topics
“About the Surface Roughness of Copper Foil” on page 1389

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 Dialog Boxes
Sweeping Dialog Box

Sweeping Dialog Box

To access: Double-click a tree item in either the IBIS-AMI Channel Analyzer Wizard - Sweep
AMI Model Settings Page or Sweep Manager dialog box
Use the Sweeping dialog box to define sweep ranges. The format of this dialog box depends on
whether the design property is swept by numerical values or by named values. For example, use
numerical values to sweep dielectric thicknesses and use named lists to sweep IC process
corners.
You can type values in decimal, scientific notation, or decimal scale format. For example, 0.02,
2e-2, or 20m. Scientific notation values are automatically converted to decimal scale format.
See “Decimal Scaling Suffixes for Sweeps” on page 1876.
You do not need to type units because units are pre-assigned and not editable. If you delete or
change unit text, the original units are restored when you re-open the dialog box.

Figure 35-15. Sweeping Dialog Box - Numerical Values

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Dialog Boxes
Sweeping Dialog Box

Figure 35-16. Sweeping Dialog Box - Named Values

Table 35-13. Sweeping Dialog Box Contents

Option Description
Information area Names the swept design property or IBIS-AMI model parameter.

For IBIS-AMI sweeps, this area also displays the contents of the
Description statement in the .AMI model, if it exists.

By initial / final values Begin sweep simulation at initial sweep range value and end at
the final value. Use either Simulation count or Increment to
determine the number of steps.
Initial Starting and ending values of the sweep range.
Final
Note: Values in the Initial and Final boxes do not have to be in
any particular order. If the value in the Final box is less than the
value in the Initial box, the Increment box label automatically
changes to Decrement.

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 Dialog Boxes
Sweeping Dialog Box

Table 35-13. Sweeping Dialog Box Contents (cont.)

Option Description
Simulation count Number of simulations.

When you specify the number of simulations or step size, the

dialog box automatically calculates the other value when you
click outside the current box.
Increment Step size.

When you specify the number of simulations or step size, the

dialog box automatically calculates the other value when you
click outside the current box.
By tolerance Begin sweep simulation at (Value - Tolerance) and end at (Value
+ Tolerance). Use either Simulation count or Increment to
determine the number of steps.

If you specify a negative increment value, the sweep range begins

at the center value plus the tolerance and ends at the center value
minus the tolerance.
Value Center value of the sweep range.
Simulation count Number of simulations.

When you specify the number of simulations or step size, the

dialog box automatically calculates the other value when you
click outside the current box.
Tolerance Maximum deviation from the center value.
Increment Step size.

When you specify the number of simulations or step size, the

dialog box automatically calculates the other value when you
click outside the current box.

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Dialog Boxes
Sweeping Dialog Box

Table 35-13. Sweeping Dialog Box Contents (cont.)

Option Description
By list Begin sweep simulation at the first list item and run simulation
for each item in the list.

When you define the sweep range by By initial / final values or

By tolerance, this area displays the individual design property
values. To save simulation time, you can delete unwanted design
property values by enabling By list and deleting values.

Notes:
• Some types of IC models, such as SPICE models, do not
respond to IC operating condition values.
• For IBIS and MOD IC models, sweeping models assigned to
a specific IC pin is restricted to models located in the current
model library file.
• Sweeping models for programmable IC buffers is restricted to
models located in the [Model Selector] keyword in the current
IBIS model. When sweeping pins in a reference designator
that map to a [Model Selector] keyword, all the pins receive
the same model assignment for each simulation. If the [Model
Selector] keyword contains a description of each model, the
second column displays the description.
Simulation count The number of simulations that will run, based on the sweep
range you have defined.

Decimal Scaling Suffixes for Sweeps

Table 35-14 shows the decimal scaling suffixes supported by this dialog box.
Table 35-14. Supported Scaling Factor Suffixes for Sweeps
Suffix Name Scale
M mega 1,000,000x
K or k kilo 1,000x
m milli 0.001x
u or U micro 1e-6x
n or N nano 1e-9x
p or P pico 1e-12x

Related Topics
“IBIS-AMI Channel Analyzer Wizard - Sweep AMI Model Settings Page” on page 1753
“Simulating Signal Integrity with Sweeps” on page 601

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 Dialog Boxes
Synthesize DFE Dialog Box

Synthesize DFE Dialog Box

To access: FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page > select Add DFE and
Synthesize optimal values > click Details
Use this dialog box to specify how many taps exist in the receiver equalization circuitry.

Figure 35-17. Synthesize DFE Dialog Box

Table 35-15. Synthesize DFE Dialog Box

Option Description
Total number of taps Specify the number of taps contained in the receiver equalization
circuitry.

For information about the assumed implementation of the DFE structure,

see “Pre-Emphasis and DFE Structures” on page 1599.

Related Topics
“FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page” on page 1596

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Dialog Boxes
Synthesize Pre-Emphasis Dialog Box

Synthesize Pre-Emphasis Dialog Box

To access: FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page > select Add driver pre-
emphasis and Synthesize optimal values > click Details
Use this dialog box to specify how many taps exist in the driver pre-emphasis circuitry and how
many of them are pre-taps.

Figure 35-18. Synthesize Pre-Emphasis Dialog Box

Table 35-16. Synthesize Pre-Emphasis Dialog Box

Option Description
Total number of taps Specify the overall number of taps in the driver pre-emphasis
circuitry.

For information about the assumed implementation of the pre-

emphasis structure, see “Pre-Emphasis and DFE Structures” on
page 1599.
Number of pre-taps Area
Don’t care Have the wizard choose the number of pre-taps.
Number Manually specify the number of pre-taps.

Related Topics
“FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page” on page 1596

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 Dialog Boxes
Synthesized DFE Weights Dialog Box

Synthesized DFE Weights Dialog Box

To access: FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page > select Add DFE >
select Synthesize optimal values > FastEye Channel Analyzer - View Analysis Results
Page > select Synthesized taps > run analysis
Use this dialog box to display optimum decision-feedback equalization (DFE) tap weight values
and to save them to a file (.TAPS).
Note
If you close this dialog box, you must rerun FastEye channel analysis to re-open it.

Figure 35-19. Synthesized DFE Weights Dialog Box

Table 35-17. Synthesized DFE Weights Dialog Box Contents

Option Description
Tap The zero row represents the main tap. The positive-numbered
rows represent post-taps.

For information about the assumed implementation of the DFE

structure, see “Pre-Emphasis and DFE Structures” on page 1599.

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Dialog Boxes
Synthesized DFE Weights Dialog Box

Table 35-17. Synthesized DFE Weights Dialog Box Contents (cont.)

Option Description
Weight The optimum weight values for the DFE circuitry.
Save As Save the tap and weight values to a tap weights file (.TAPS).

Related Topics
“FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page” on page 1596
“FastEye Channel Analyzer - View Analysis Results Page” on page 1628

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 Dialog Boxes
Synthesized Pre-Emphasis Weights Dialog Box

Synthesized Pre-Emphasis Weights Dialog Box

To access: FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page > select Add driver pre-
emphasis > select Synthesize optimal values > FastEye Channel Analyzer - View Analysis
Results Page > select Synthesized taps > run analysis
Use this dialog box to display optimum pre-emphasis tap weight values and to save them to a
file (.TAPS).
Note
If you close this dialog box, you must rerun FastEye channel analysis to re-open it.

Figure 35-20. Synthesized Pre-Emphasis Weights Dialog Box

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Synthesized Pre-Emphasis Weights Dialog Box

Table 35-18. Synthesized Pre-Emphasis Weights Dialog Box Contents

Option Description
Tap Negative-numbered rows represent pre-taps. The zero row
represents the main tap. Positive-numbered rows represent post-
taps.

For information about the assumed implementation of the pre-

emphasis structure, see “Pre-Emphasis and DFE Structures” on
page 1599.
Weight The optimum weight values for the pre-emphasis circuitry.
Save As Save the tap and weight values to a tap weights file (.TAPS).

Related Topics
“FastEye Channel Analyzer - Add Pre-Emphasis/DFE Page” on page 1596
“FastEye Channel Analyzer - View Analysis Results Page” on page 1628

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 Dialog Boxes
Target-Z Wizard - Finish Page

Target-Z Wizard - Finish Page

To access: Select Simulate PI > Analyze Decoupling > Set the Target Impedance page >
Calculator button
Use this page to read the output of the target-Z calculation.

Figure 35-21. Target-Z Wizard - Finish Page

Table 35-19. Target-Z Wizard - Finish Page Contents

Field Description
Target Z Displays the output of the target-Z calculation.

Related Topics
“Analyzing Decoupling” on page 1013
“Analyzing Signal-Via Bypassing” on page 1051

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Dialog Boxes
Target-Z Wizard - Specify Peak Transient Current Page

Target-Z Wizard - Specify Peak Transient Current Page

To access: Select Simulate PI > Analyze Decoupling > Set the Target Impedance page >
Calculator button
Use this page to specify the peak transient current transmitted through the pair of power-supply
nets.
If you run distributed decoupling analysis and include the series inductance that is unique to IC
power-supply pins, consider specifying in this dialog box the amount of peak transient current
that you specify one of the AC PI models. You calculate this by taking the overall peak transient
current for the IC and dividing it by the number of power pins with AC power pin models. The
effect of this calculation is to increase the target impedance. See “Remove series inductance
unique to each power pin, to see plane decoupling more clearly” on page 1516 and “Assign
Power Integrity Models Dialog Box - IC Tab” on page 1456.

Figure 35-22. Target-Z Wizard - Specify Peak Transient Current Page

Table 35-20. Target-Z Wizard - Specify Peak Transient Current Page Contents
Field Description
Peak transient current You can obtain peak transient current values by any of the
following ways:
• Catalog IC— View the datasheet or ask the vendor
Datasheets may provide parameter values that vary by system
operation mode.
• FPGA— Run the power calculator provided by the FPGA
development system
• ASIC— Ask the in-house IC designers at your company

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 Dialog Boxes
Target-Z Wizard - Specify Peak Transient Current Page

Related Topics
“Analyzing Decoupling” on page 1013
“Analyzing Signal-Via Bypassing” on page 1051

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Dialog Boxes
Target-Z Wizard - Specify Supply Voltage and Max Ripple Page

Target-Z Wizard - Specify Supply Voltage and Max Ripple

Page
To access: Select Simulate PI > Analyze Decoupling > Set the Target Impedance page >
Calculator button
Use this page to specify the nominal voltage provided by the voltage-regulator module (VRM)
and its ripple.

Figure 35-23. Target-Z Wizard - Specify Supply Voltage and Max Ripple Page

Table 35-21. Target-Z Wizard - Specify Supply Voltage and Max Ripple Page
Contents
Field Description
Nominal supply voltage --
Max. percentage ripple Specify ripple as an offset from the nominal DC voltage. Do not
specify ripple as the peak-to-peak range of the nominal DC
voltage. See Usage Notes.

Usage Notes
You may allocate 30% (or some other value) of the power budget for DC drop and the rest for
AC. To map this to a ripple value, if you have a 5% ripple budget, then you would assign 1.5%
(that is, 5% times 30%) to DC drop and 3.5% to AC impedance.
The 30% value for the DC drop share of the power budget may not apply to your design. If the
design has very good AC impedance, you can allocate less to AC impedance and more to DC
drop. Similarly, if the design has few DC drop problems, you can allocate more to AC
impedance and less to DC drop.

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 Dialog Boxes
Target-Z Wizard - Specify Supply Voltage and Max Ripple Page

Related Topics
“Analyzing Decoupling” on page 1013
“Analyzing Signal-Via Bypassing” on page 1051

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Dialog Boxes
Units Dialog Box

Units Dialog Box

To access: Setup > Options > Units
Use this dialog box to set the measurement units displayed in the Stackup Editor, board viewer
(BoardSim), and Edit Transmission Line dialog box (LineSim), and other dialog boxes that
display geometric information. For metal layer thickness, you can select between thickness or
weight units. For all other dimensions, you can select between English or metric units.
The default settings are English and weight, meaning dimensions are displayed in inches (or
mils for dielectric thickness) and metal thickness is displayed in ounces. International users may
prefer metric and length, meaning dimensions are displayed in centimeters (or microns for
dielectric thickness) and metal thickness is displayed in microns.
Note
For HyperLynx Thermal, the English option maps to mixed units and the Metric option
maps to SI units. See “Units”.

Figure 35-24. Units Dialog Box

Related Topics
”Configuring the HyperLynx Environment” - LineSim
”Configuring the HyperLynx Environment” - BoardSim
“Setting Measurement Units” on page 401

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 Dialog Boxes
Via Model Extractor Wizard - Check Capacitor Models Page

Via Model Extractor Wizard - Check Capacitor Models Page

To access:
• LineSim — Select Export > Model > Signal-Via Model and select the Check
Capacitor Models page
• BoardSim — Select Export > Signal-Via Model and select the Check Capacitor
Models page
Use this page to review and edit decoupling capacitor model assignments.
See “Assign / Edit Capacitor Model Dialog Box” on page 1442.
Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Exporting Signal Vias to S-Parameter Models” on page 1180

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Dialog Boxes
Via Model Extractor Wizard - Choose Easy / Custom Page

Via Model Extractor Wizard - Choose Easy / Custom Page

To access:
• LineSim — Select Export > Model > Signal-Via Model and select the Choose Easy /
Custom page
• BoardSim — Select Export > Signal-Via Model and select the Choose Easy / Custom
page
Use this page to choose between default and custom export options.

Figure 35-25. Via Model Extractor Wizard - Choose Easy / Custom Page

Table 35-22. Via Model Extractor Wizard - Choose Easy / Custom Page
Contents
Option Description
Easy Popular analysis settings are automatically enabled on some of
the following wizard pages. Many of the automatically-enabled
settings become read only.
Custom You can edit all analysis settings on the following wizard pages

Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Exporting Signal Vias to S-Parameter Models” on page 1180

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 Dialog Boxes
Via Model Extractor Wizard - Control Frequency Sweep Page

Via Model Extractor Wizard - Control Frequency Sweep

Page
To access:
• LineSim — Select Export > Model > Signal-Via Model and select the Control
Frequency Sweep page
• BoardSim — Select Export > Signal-Via Model and select the Control Frequency
Sweep page
Use this page to edit frequency range and sampling options, both of which affect analysis run
time and the resolution of the exported S-parameter model.

Figure 35-26. Via Model Extractor Wizard - Control Frequency Sweep Page

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Via Model Extractor Wizard - Control Frequency Sweep Page

Table 35-23. Via Model Extractor Wizard - Control Frequency Sweep Page
Contents
Option Description
Min frequency The minimum simulation frequency, in MHz.

Many ICs have in-package decoupling that provide the

main decoupling effects above a certain frequency, such
as 300 to 350 MHz. This means decoupling capacitors
and buried capacitance located in the PCB contribute
little or no decoupling above this design-dependent
frequency.
Max frequency The maximum simulation frequency, in MHz.Many ICs
have in-package decoupling that provide the main
decoupling effects above a certain frequency, such as
300 to 350 MHz. This means decoupling capacitors and
buried capacitance located in the PCB contribute little or
no decoupling above this design-dependent frequency.
Adaptive sampling Varies the sampling step size depending on model
characteristics. The adaptive scale is better than
Restriction: This option is logarithmic and linear because it increases the sampling
unavailable if you enable the Easy rate near frequencies with resonances.
option in the Via Model Extractor
Wizard - Choose Easy / Custom
Page.
Logarithmic sampling Sampling points are distributed at logarithmic intervals
across the frequency range. The intervals between
Restriction: This option is sampling points are smaller at lower frequencies and
unavailable if you enable the Easy larger for higher frequencies. With logarithmic
option in the Via Model Extractor sampling, every next frequency point is equal to the
Wizard - Choose Easy / Custom previous value times a factor K > 1. This produces a
Page. constant increase ratio, but the absolute distance
between sampling points grows.
Linear sampling Sampling points are distributed at equal intervals across
the frequency range.
Restriction: This option is
unavailable if you enable the Easy
option in the Via Model Extractor
Wizard - Choose Easy / Custom
Page.

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 Dialog Boxes
Via Model Extractor Wizard - Control Frequency Sweep Page

Table 35-23. Via Model Extractor Wizard - Control Frequency Sweep Page
Contents (cont.)
Option Description
Accuracy at resonances For lumped analysis, enabling the High option may still
yield reasonably fast simulation run times.
Restriction: This option is
unavailable unless you enable the For distributed analysis, you should take the complexity
Adaptive sampling option on this of the design into account. If the design has large
page. numbers of power-supply nets, hundreds of decoupling
capacitors, and hundreds or thousands of stitching vias,
enabling the Low option provides preliminary results
with decreased analysis run time. After evaluating the
preliminary results, you can identify which frequency
ranges interest you the most and try running analysis
with higher accuracy on each range of interest.
Minimum number of samples in The number of samples you specify applies to flat, non-
flat, non-resonant regions resonant, regions of an impedance profile. See the
enclosed curve region Figure 32-41 on page 1513.
Restriction: This option is
unavailable unless you enable the
Adaptive sampling option on this
page.
Number of samples The number of samples you specify applies to the entire
frequency range.
Restriction: This option is
unavailable if you enable the
Adaptive sampling option on this
page.
Default Click Default to restore the initial settings.

Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Exporting Signal Vias to S-Parameter Models” on page 1180

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Dialog Boxes
Via Model Extractor Wizard - Customize Settings Page

Via Model Extractor Wizard - Customize Settings Page

To access:
• LineSim — Select Export > Model > Signal-Via Model and select the Customize
Settings page
• BoardSim — Select Export > Signal-Via Model and select the Customize Settings
page
Use this page to enable detailed signal-via-model extraction options. Extracting models with
different sets of enabled and disabled options can help you determine how individual types of
design properties contribute to via model impedance.
Restriction: If you enabled the “Easy” option on the Via Model Extractor Wizard - Choose
Easy / Custom Page, you cannot edit options on this page.

Figure 35-27. Via Model Extractor Wizard - Customize Settings Page

Table 35-24. Via Model Extractor Wizard - Customize Settings Page Contents
Option Description
Include capacitor mounting To determine the contribution of capacitor mounting inductance
inductance to the overall signal-via bypassing performance, you can run
analysis with this option enabled, run it again with this option
disabled, and then compare the results.

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 Dialog Boxes
Via Model Extractor Wizard - Customize Settings Page

Table 35-24. Via Model Extractor Wizard - Customize Settings Page Contents
Option Description
Enable stitching-via Find stitching vias that are located close together and merge their
optimization individual models into an equivalent model. This process is
repeated across the transmission plane. Reducing the number of
stitching-via models speeds up simulation and reduces memory
consumption because each model adds a variable to the systems
of equations to solve. See “Stitching-Via Optimization - Via
Model Extractor” on page 1895.
Stitching-Via Optimization - Via Model Extractor
Stitching-via optimization takes advantage of the fact that when the size of objects (or groups of
them) is much smaller than the wavelength of a signal, the signal does not respond to them in
detail, and approximate models can accurately represent those objects in simulation.
The Tolerance slider controls the merging radius for optimization:
• Low—1/30th of the minimum wavelength of the signal
• Medium—1/20th of the minimum wavelength of the signal
• High—1/10th of the minimum wavelength of the signal
For example, let us say that signal-via bypassing analysis does not exceed 300 MHz and that the
wavelength of a 300 MHz signal in FR-4 is about 20 inches. In electromagnetic analysis, 1/10th
wavelength is considered to be safely “much smaller” than the wavelength of the signal and that
within a 2 inch radius, we can avoid representing individual stitching vias by modeling them
with one equivalent (or “clumped”) via.
Not all stitching vias are eligible for optimization and most optimization takes place far away
from IC and decoupling-capacitor pins. The optimization algorithm preserves individual models
for caging vias and for stitching vias that contribute significantly to transmission-plane or
decoupling-capacitor inductance. As a result, this setting may have little effect for designs
where most of the stitching vias in the transmission plane contribute significantly to
transmission-plane or decoupling-capacitor inductance.
For example, caging vias that are located very close to the IC or decoupling-capacitor pin are
always modeled individually. In other words, if you run decoupling analysis to produce Z
parameters for an IC power-supply pin that uses a via with a stitching section, then any very-
nearby stitching vias are preserved as individual models to observe their full caging effect.
Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Exporting Signal Vias to S-Parameter Models” on page 1180

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Dialog Boxes
Via Model Extractor Wizard - Run Analysis Page

Via Model Extractor Wizard - Run Analysis Page

To access:
• LineSim — Select Export > Model > Signal-Via Model and select the Run Analysis
page
• BoardSim — Select Export > Signal-Via Model and select the Run Analysis page
Use this page to choose the name of the S-parameter file created by via model exporting and to
choose whether to save the wizard page settings to a file.

Figure 35-28. Via Model Extractor Wizard - Run Analysis Page

Table 35-25. Via Model Extractor Wizard - Run Analysis Page Contents
Option Description
Save settings to file Save wizard settings to a .DAO file. The default file location is
the <design> folder. See “About Design Folder Locations” on
page 1391. You can change the file locations.

To specify another settings file location, click Browse to specify

the file name and location.

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Via Model Extractor Wizard - Run Analysis Page

Table 35-25. Via Model Extractor Wizard - Run Analysis Page Contents (cont.)
Option Description
Auto-generate output file Name the output file using form
name <design>_<simulation_iteration>.s<number_of_ports>p.

For example, test_1.s6p.

The default file location is the <design> folder. See “About

Design Folder Locations” on page 1391.

To specify another output file location, deselect Auto-generate

output file name and click Browse to specify the file name and
location.

Related Topics
“Running Signal-Via Bypass Analysis” on page 1053
“Files Written by Signal-Via Model Extraction” on page 1182
“Exporting Signal Vias to S-Parameter Models” on page 1180

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Dialog Boxes
Via Model Extractor Wizard - Select Signal Via Page

Via Model Extractor Wizard - Select Signal Via Page

To access:
• LineSim — Select Export > Model > Signal-Via Model and select the Select Signal
Via page
• BoardSim — Select Export > Signal-Via Model and select the Select Signal Via page
Use this page to select the single signal via or differential signal via pair to export.
Restrictions:
• You can export a model for one via or differential via pair at a time.
• In LineSim, you can export models only for vias connected to stackup type (coupled or
uncoupled) transmission lines.
• In BoardSim, both differential vias must connect to the same two stackup layers.

Figure 35-29. Via Model Extractor Wizard - Select Signal Via Page - LineSim

Table 35-26. Via Model Extractor Wizard - Select Signal Via Page Contents -
LineSim
Option Description
Check box Select to choose the signal via or via pair to analyze.
Schematic Via Name Reference designator for the signal via symbol.

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 Dialog Boxes
Via Model Extractor Wizard - Select Signal Via Page

Table 35-26. Via Model Extractor Wizard - Select Signal Via Page Contents -
LineSim (cont.)
Option Description
Via 1 Connected Layers The complete set of stackup layers the signal via connects to.

Click the plus sign + to expand the spreadsheet row to display all
connected stackup layers.

Click the minus sign - to collapse the spreadsheet row to display

only the top-most connected stackup layer.
Via 2 Connected Layers Applies to second via of a differential via pair.

Otherwise this spreadsheet cell has the same behavior as “Via 1

Connected Layers” option.

Figure 35-30. Via Model Extractor Wizard - Select Signal Via Page - BoardSim -
Single-Ended Via

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Dialog Boxes
Via Model Extractor Wizard - Select Signal Via Page

Figure 35-31. Via Model Extractor Wizard - Select Signal Via Page - BoardSim -
Differential Via

Table 35-27. Via Model Extractor Wizard - Select Signal Via Page Contents -
BoardSim
Option Description
Single via Click Single via to export a single-ended via.
Differential via Click Differential via to export a differential via.
Pan to Click Pan to to display the selected single via or differential via
pair is displayed in the center of the board viewer and marked by
white lines. If the wizard dialog box covers much of the board
viewer, the selected via is displayed in the center of the largest
visible area of the board viewer.
Net Name of the net that contains the selected signal via.

This field is blank until you select a signal via in the board
viewer.

To select a signal via:

1. Display the via in the board viewer, zooming and panning if
needed. See “Viewing BoardSim Boards”.
2. Either double-click the via or Right-click via > Select Via.

To replace an existing via selection, select a different via.

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 Dialog Boxes
Via Model Extractor Wizard - Select Signal Via Page

Table 35-27. Via Model Extractor Wizard - Select Signal Via Page Contents -
BoardSim (cont.)
Option Description
Position The X/Y coordinates of the selected signal via.

Restriction: This field is

displayed only for single-
ended vias.
Connected layers The complete set of stackup layers the signal via connects to.

Related Topics
“Running Export to Signal-Via Models” on page 1181
“Exporting Signal Vias to S-Parameter Models” on page 1180

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Dialog Boxes
Via Model Extractor Wizard - Set Model Type Page

Via Model Extractor Wizard - Set Model Type Page

To access:
• LineSim — Select Export > Model > Signal-Via Model and select the Set Model
Type page
• BoardSim — Select Export > Signal-Via Model and select the Set Model Type page
Use this page to edit the normalization impedance for the exported S-parameter model and for
differential vias only to select the propagation mode information to include in the exported S-
parameter model.

Figure 35-32. Via Model Extractor Wizard - Set Model Type Page

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 Dialog Boxes
Via Model Extractor Wizard - Set Model Type Page

Table 35-28. Via Model Extractor Wizard - Set Model Type Page Contents
Option Description
Normalization impedance The normalization impedance for the exported S-
parameter model.

Specifying the exact normalization impedance is not a

simulation problem because simulators produce identical
results whether the S-parameter model has a 50-ohm
impedance or another impedance.

However models with different normalization impedances

can make them harder to understand visually when they
are displayed in the Touchstone Viewer. For example, if
you export two S-parameter models for the same
differential via pair, but specify 25 ohms normalization
impedance for one model and 50 ohms for the other, the S-
parameter data may look different. See Figure 35-33 on
page 1904.
4-port standard model Select the propagation mode information to include in the
2-port differential-mode model exported S-parameter model for a differential signal-via
2-port differential-mode model pair. See “Choosing a Propagation Mode for Exported
Differential Models” on page 1904 and “Mapping Ports
Restriction: These options are Between Differential Vias and Standard S-Parameter
unavailable unless you select a Models” on page 1905.
differential signal via.

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Via Model Extractor Wizard - Set Model Type Page

Normalization Impedance for S-Parameter Models

Figure 35-33. Exported S-Parameter Models for Same Via Pair at 25 and 50
Ohms

Choosing a Propagation Mode for Exported Differential Models

“Standard” exported differential via models contain both differential and common propagation-
mode information. Standard differential via models are good for both simulation and viewing.
These models have four ports and are easy to add to free-form schematics.
You can also export via models containing only differential-mode information or only common-
mode information, which are good for viewing, but not for simulation. Comparing these models
to standard via models can show the contribution of individual differential and common modes
to signal loss. Asymmetric geometries or asymmetric differential signal transitions can cause
some of the signal energy to convert to common mode.
Note
Via models containing only differential-mode information do not account for the effects
of stitching vias. Advanced users can use third-party 3-D simulation software to create
via models containing only differential-mode information, and then use the Touchstone
Viewer to combine them with common-mode models exported from BoardSim/LineSim.
See “Combine to Standard Mode Dialog Box” on page 1121.

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 Dialog Boxes
Via Model Extractor Wizard - Set Model Type Page

Mapping Ports Between Differential Vias and Standard S-Parameter Models

The DV.log file maps model ports to vias in the design. See “DV.log” on page 1182.
Figure 35-34 shows how the ports for a differential via in LineSim map to the ports of the
exported S-parameter model (“standard” propagation mode).

Figure 35-34. Port Mapping for Differential Via Symbols and Exported S-
Parameter Models - LineSim

Figure 35-35 shows how the ports for a differential via in BoardSim map to the ports of the
exported S-parameter model (“standard” propagation mode).

Figure 35-35. Port Mapping for Differential Via Symbols and Exported S-
Parameter Models - BoardSim

Related Topics
“Running Export to Signal-Via Models” on page 1181
“Exporting Signal Vias to S-Parameter Models” on page 1180

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Via Model Extractor Wizard - Start Analysis Page

Via Model Extractor Wizard - Start Analysis Page

To access:
• LineSim — Select Export > Model > Signal-Via Model and select the Start Analysis
page
• BoardSim — Select Export > Signal-Via Model and select the Start Analysis page
Use this page to start new export or load the settings for a saved export.
Editing the setting on this page also edits the same setting on the Via Model Extractor Wizard -
Run Analysis Page page.

Figure 35-36. Via Model Extractor Wizard - Start Analysis Page

Table 35-29. Via Model Extractor Wizard - Start Analysis Page Contents
Option Description
New --
Use last configuration Reuse settings from the current BoardSim/LineSim session. This
option is unavailable until you have opened and closed the wizard
in the current BoardSim/LineSim session.

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 Dialog Boxes
Via Model Extractor Wizard - Start Analysis Page

Table 35-29. Via Model Extractor Wizard - Start Analysis Page Contents (cont.)
Option Description
Load save configuration Open a settings file (.DAO) by selecting Load save
configuration, clicking Load, browsing to the file, and then
clicking Open.

Note: If you load a .DAO file saved from LineSim in HyperLynx

8.1.1 or older, you may have to reselect power-supply nets on
other pages in this wizard. Starting with HyperLynx 8.2, the PDN
Editor supports customer-defined power-supply net names, such
as 1.8V. In previous releases, the PDN Editor used only names
that it created automatically, such as __TPE_VCC__.
Save settings to file Save setup information to the settings file. By default, this file is
written to the <design> folder and named <design>.dao. See
“About Design Folder Locations” on page 1391.

Related Topics
“Running Export to Signal-Via Models” on page 1181
“Exporting Signal Vias to S-Parameter Models” on page 1180

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Dialog Boxes
Via Properties Dialog Box

Via Properties Dialog Box

To access: Double-click via or differential via pair in free-form schematic
Use this dialog box to specify the type of electrical model for a signal via or differential via pair
in the free-form schematic.
Signal vias do not show significant 3-D electromagnetic effects for signals below 3 GHz. In this
case, selecting None for the 3D EM Modeling option provides good simulation results and short
simulation run times.
For vias transmitting signals above 3-6 GHz, consider using a 3-D electromagnetic solver to
create an S-parameter model representing the behavior of the signal via, adjacent stitching vias,
and short sections of the connected signal traces. In this case, selecting HyperLynx 3D EM
Solver automatically runs 3-D EM simulation to create an S-parameter model and assign it to
the signal via.
Note
Note that the frequency threshold to choose a 3-D electromagnetic solver is not an
arbitrary number and can depend on design properties, such as stackup layer thickness.

Restrictions:

• The Via Models license is required to use via symbols.

• The 3D Via Model Export license is required to export via models to HyperLynx 3D
EM.
• Free-form schematics simulate signal vias, but not decoupling vias, stitching vias, and
vias with thermal spokes.
• Signal vias are not shared between the PDN Editor and free-form schematic editor
unless you add them to the PDN Editor first. If you are setting up for power-integrity
simulation and want the signal via in the free-form schematic to interact with the PDN,
use the PDN Editor to add the via. See "Defining the Power-Distribution Network" and
“Add Signal Via Dialog Box” on page 1436.
The content of this dialog box depends on the 3D EM Modeling option value.
• None—See “Via Properties Dialog Box - No 3-D Solver” on page 1909.
• HyperLynx 3D EM Solver—See “Via Properties Dialog Box - HyperLynx 3D EM
Solver” on page 1910.

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 Dialog Boxes
Via Properties Dialog Box

Via Properties Dialog Box - No 3-D Solver

Figure 35-37. Via Properties Dialog Box - No 3-D Solver

Table 35-30. Via Properties Dialog Box - No 3-D Solver

Option Description
3D EM Modeling Type of electrical via model.
• None—Use 2-D decomposition and field solvers. See “Via
Electrical Modeling” on page 1060.
• HyperLynx 3D EM Solver—Use the built-in version of
HyperLynx 3D EM to extract via geometries and create an S-
parameter model to represent them. Adds a “3D” label to the
via symbol in the free-form schematic.
Restriction: You must connect the via to transmission lines on
two stackup layers before you can select HyperLynx 3D EM
Solver.
Connected Layers Number of stackup layers connected to the via. This value
determines how many ports appear on the via symbol in the
schematic editor.
Padstack Name of the padstack to use.

Requirement: Set up padstacks for the schematic before assigning

them to vias. See “Managing Padstacks”.
Edit Edit padstack properties in the Padstack Editor. See “Editing
Padstack Properties”.

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Via Properties Dialog Box

Table 35-30. Via Properties Dialog Box - No 3-D Solver (cont.)

Option Description
Common Anti-Pad A single anti-pad that encloses both vias in a differential via.

Restriction: This option is unavailable for single-ended vias.

View Display padstack properties in the Via Visualizer. See “Viewing
Via Properties” on page 1056.
Via Separation Distance between the centerlines of differential via barrels.

Restriction: This option is unavailable for single-ended vias.

Via Properties Dialog Box - HyperLynx 3D EM Solver

Figure 35-38. Via Properties Dialog Box - HyperLynx 3D EM Solver

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 Dialog Boxes
Via Properties Dialog Box

Table 35-31. Via Properties Dialog Box - HyperLynx 3D EM Solver Contents

Option Description
3D EM Modeling Type of electrical via model.
• None—Use 2-D decomposition and field solvers. See “Via
Electrical Modeling” on page 1060.
• HyperLynx 3D EM Solver—Use the built-in version of
HyperLynx 3D EM to extract via geometries and create an S-
parameter model to represent them. Adds a “3D” label to the
via symbol in the free-form schematic.
Restriction: You must connect the via to transmission lines on
two stackup layers before you can select HyperLynx 3D EM
Solver.
Connected Layers Number of stackup layers connected to the via. This value
determines how many ports appear on the via symbol in the
schematic editor.
HyperLynx 3D EM Location of the HyperLynx 3D EM project file (.V3D). The
project file contains geometric information, such as “feeding trace”
Open lengths and the stitching via configuration, and simulation set up
information, such as number of ports and simulation frequency
Browse range.

The default file naming convention is:

via_FFS_<via_reference_designator>_<file_version>.v3d

where:

<via_reference_designator> is the reference designator located

next to the via symbol in the schematic

<file_version> is an integer starting from 01

The design folder is the default project file location. See “About
Design Folder Locations” on page 1391.

Click Open to open the project file currently displayed in the field.

Click Browse to browse to another existing project file.

See “Via Project File and S-Parameter File Reuse” on page 1912.
New Opens the New HyperLynx 3D EM Project Dialog Box, to start the
process of creating a new HyperLynx 3D EM project file (.V3D).

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Via Properties Dialog Box

Via Project File and S-Parameter File Reuse

You can directly reuse the via project file (.V3D) and its associated S-parameter file in other
free-form schematics.
• If you locate the pair of files in a shared folder, then changing the via project file or S-
parameter file affects all the free-form schematics that use them.
• If you collect via project files into a central location on the network, be sure to copy the
associated S-parameter files to the same folder. For example, copy both
via_FFS_V1.v3d and via_FFS_V1.s4p to the same folder.
• If there are parameter mismatches between the schematic and via project file,
HyperLynx warns you and does not attempt to automatically change any parameters.
For example, a parameter mismatch occurs when the schematic uses trace width X, but
the via project file uses trace width Y.
You can use an existing via project file as a template to quickly create new via design.
Related Topics
“Modeling Vias in Free-Form Schematics”

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 Dialog Boxes
View Options Dialog Box

View Options Dialog Box

To access: View > Options
Use this dialog box and right-click menus to control how the board viewer displays objects. You
can perform the following operations from this dialog box or the right-click menu for an object
in the board viewer:
• View or hide reference designator labels
• Emphasize the appearance of objects
• Highlight objects on the fly
• View or hide pads and anti-pads
• Remove highlighting for all nets

Figure 35-39. View Options Dialog Box

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View Options Dialog Box

Table 35-32. View Options Dialog Box Contents

Option Description
Show reference designators Select the type of components you want to display reference
for designators for. You can also right-click in the board viewer
and select Show Reference Designators and select the items
to display or hide.

To help you identify components, the board viewer normally

displays the reference designator label next to the component
outline. On very dense boards, or when a board is viewed at a
distance (zoomed far out), the reference designator labels
may crowd together and overlap. In this case, you can
improve layout legibility by hiding reference designator
labels by object type.
Emphasize objects by The board viewer displays a selected net at full brightness,
brightness while displaying other objects at reduced brightness. You can
also display at full brightness other types of nets related to
the selected net.
• None — All objects display the same.
• Selected net and highlighted nets — Display selected
net and highlighted nets at full brightness and all other
objects at reduced brightness.
• Associated nets — Displays nets associated to selected
net by conductivity and differential IBIS models in full
brightness.
Note: This option is unavailable if the Selected Net and
Highlighted Nets check box is cleared.
• Coupled nets — Displays nets associated to selected
nets by coupling.
Note: This option is unavailable if the Associated nets
check box is cleared or you do not have the BoardSim
Crosstalk license.
You can adjust the brightness level for background objects.
See “Preferences Dialog Box - Appearance Tab” on
page 1800.

If nets appear to be too complicated or seem to be connected

to other nets they should not be, you probably have
undetected power-supply nets. Turning off associated-net
viewing only removes the extraneous nets from the board
viewer, not from the simulation database.

See also: Editing Power-Supply Net Properties, Viewing All

Nets Simultaneously

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 Dialog Boxes
View Options Dialog Box

Table 35-32. View Options Dialog Box Contents (cont.)

Option Description
Highlight on the fly Some objects in the board viewer can temporarily change
color, or highlight, when you move the pointer over them. In
a crowded area in the layout, this feature can help you
accurately position the pointer for right-click operations,
such as selecting a net for interactive simulation. You can
control on-the-fly highlighting by object type.
Select the objects to enable highlighting on the fly.
Show objects You can choose to view or hide anti-pads generated by
BoardSim. Anti-pads, however, are always displayed when
the .HYP file contains explicit anti-pad geometry
information.
• Pads—Display pads connected to vias or pins.
• Anti-pads—Display the BoardSim-generated clearance
between an object, such as a pad, trace, or via, and the
plane layer on which it resides.
This check box is unavailable when the .HYP file does
not contain copper pour information.
This option links to the Show Anti-Objects In Board
Viewer option in the Setup Anti-Pads and Anti-Segments
Dialog Box, so these two options always have the same
value.
See also: “About Pour and Void Terminology” on page 398
Remove Highlights Click to remove highlighting for all nets.

Related Topics
“Setting Layer Display Options for the Board Viewer in BoardSim” on page 396

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Viewing Filter Dialog Box

Viewing Filter Dialog Box

To access: Right-click over an empty area in the board viewer and click Show Viewing Filter.
Use this dialog box to control the visibility of individual stackup layers and highlighted nets in
the board viewer.
On dense boards with many layers in the PCB stackup, it can be difficult to view objects on
inner layers because they be obscured by objects on outer layers. In these situations, you can
temporarily hide the outer layers.
For example, in a dense 10-layer stackup, you might have trouble seeing the details on inner
layers 5 and 6. To work around this, you could use this dialog box to hide layers 1-4 and 7-10 in
the board viewer.

Tip: Drag a dialog box edge to change its height or width.

Figure 35-40. Viewing Filter Dialog Box

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 Dialog Boxes
Viewing Filter Dialog Box

Table 35-33. Viewing Filter Dialog Box Contents

Control Description
Stackup Layers pane Display/hide stackup layers by selecting/clearing the
check box.

If a MultiBoard project is open, expand the tree for a

specific board to edit its layer visibility options.

Edit the color of the stackup layer by clicking the color

square.
• Show all Display all stackup layers.

If a MultiBoard project is open, applies to all boards.

• Hide all Hide all stackup layers.

If a MultiBoard project is open, applies to all boards.

Highlighted Nets pane Display/hide highlighted nets by selecting/clearing the
check box. If you hide stackup layers in the Stackup
Layers pane, geometries on hidden layers are not
displayed for nets you highlight in this pane.

If a MultiBoard project is open, expand the tree for a

specific board to edit the visibility options for highlighted
nets on that board.
• Show all Display all highlighted nets.

If a MultiBoard project is open, applies to all boards.

• Hide all Hide all highlighted nets.

If a MultiBoard project is open, applies to all boards.

• Highlight Net Opens Highlight Net dialog box. See Board Viewer
Operations.
• Disable Dimming Displays all objects in board viewer at full brightness.

Another way to disable dimming is to right-click over an

empty area in the board viewer and click Disable
Dimming.

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Viewing Filter Dialog Box

Related Topics
“Setting Layer Display Options for the Board Viewer in BoardSim” on page 396
“Setting Signal or Plane Layer Visibility” on page 397

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 Appendix 36
What’s New

This appendix briefly lists many of the new and enhanced features, and provides links to related
information. The list is limited to features with new or significantly-changed writing.

• “Signal-Integrity and SERDES Analysis Features” on page 1919

• “Power-Integrity Analysis Features” on page 1921
• “Thermal Analysis Features” on page 1921
• “3-D Electromagnetic Analysis Features” on page 1922
• “Flow Integration Features” on page 1922

Related Topics
“Documentation Enhancements” on page 1923

Signal-Integrity and SERDES Analysis Features

Table 36-1. Signal-Integrity and SERDES Analysis Features

New or Enhanced Feature Links to Writing
IBIS-AMI and FastEye Channel Analysis
IBIS-AMI channel analysis—Sweep AMI • “IBIS-AMI Channel Analyzer Wizard -
model parameters Sweep AMI Model Settings Page” on
page 1753
• “IBIS-AMI Channel Analyzer Wizard -
Review Simulation Sweeps Page” on
page 1739
• “HyperLynx IBIS-AMI Sweeps Viewer”
on page 1667
FastEye and IBIS-AMI channel analysis— • “FastEye Channel Analysis Overview” on
Crosstalk from aggressor nets can be page 635
included during channel characterization • “IBIS-AMI Channel Analysis Overview”
on page 617
Eye Density Viewer supports eye masks, See the “Show eye mask” and “Show grid”
overlay of multiple eyes, and scale axes. options in the HyperLynx SI Eye Density
Viewer.

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What’s New
Signal-Integrity and SERDES Analysis Features

Table 36-1. Signal-Integrity and SERDES Analysis Features (cont.)

New or Enhanced Feature Links to Writing
Touchstone Viewer
Cascade (or chain) with high accuracy • “Cascading Multiple S-Parameter Models
multiple 4-port S-parameter models into in Series” on page 1105
one S-parameter model. • “Cascade 4-Port S-Parameter Models
Dialog Box” on page 1118
Apply stimulus to the loaded Touchstone “Time-Domain Response Dialog Box” on
model and display a time-domain response. page 1142
Display an impedance over time plot for “TDR Impedance Plot Dialog Box” on
the loaded Touchstone model. page 1133
and toolbar buttons to convert S- “Convert Mode Dialog Box” on page 1122
parameter files between mixed-mode and
differential mode.
Add horizontal thresholds to the curve “Adding Guidelines” on page 1078
display, to help you see curves that cross a
limit.
Identify differential pairs in BoardSim based • “Differential Pair Net Suffixes Dialog
on net name suffixes. This feature enables Box” on page 1541
BoardSim to form differential pairs without • “Differential Pairs Dialog Box” on
assigning IBIS IC models or using parallel page 1543
termination.
Generic SI batch simulation • “Constraint Definitions”
• Measure minimum rise/fall ringback, • “Opening Reports Automatically”
maximum rise/fall dynamic rail overshoot
• Report limits and margins in new report
spreadsheet columns
Find component utility in BoardSim. View > “Find Component Dialog Box” on page 1640
Find Component.
Power-supply nets exported from BoardSim “Naming Convention Change for Power-
have the same name in the free-form schematic Supply Nets Exported to LineSim” on
as they do in BoardSim. Previously, exported page 1164
power-supply net names were of form
__TPE_<BoardSim_net_name>__.
Display top view of via pads and antipads. • “Steps to View Via Properties” on
page 1056 (see step 5)
• “Contents of the Graphical Display” (see
step 3)
• “Adding Vias” (see step 3c in the
procedure)

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 What’s New
Power-Integrity Analysis Features

Power-Integrity Analysis Features

Table 36-2. Power-Integrity Analysis Features

New or Enhanced Feature Links to Writing
DC voltage drop co-simulation with “Running DC Drop Batch Simulation” on
HyperLynx Thermal. This feature increases the page 995
accuracy of DC voltage drop analysis by
iteratively co-simulating with the HL Thermal
engine. You can now see the metal-
temperature increase that results from high DC
current densities, and better predict fusing and
other PCB damage.

Restriction: This feature is available only for

batch DC voltage drop simulation in
BoardSim.
PDN Editor supports electrical nets, which See the “Net” and “Ref Net” options in the
supports PI simulation of PDNs with more following dialog boxes:
than one power-supply net on a stackup layer. • Add/Edit Decoupling Capacitor(s) Dialog
Box
• Add/Edit IC Power Pin(s) Dialog Box
• Add/Edit VRM or DC to DC Converter
Dialog Box
Also see PDN Net Manager Dialog Box.

Thermal Analysis Features

Table 36-3. Thermal Analysis Features

New or Enhanced Feature Links to Writing
Integration of HyperLynx Thermal and its See “Getting Started with HyperLynx
ThermalSim window into BoardSim. Thermal”.

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What’s New
3-D Electromagnetic Analysis Features

3-D Electromagnetic Analysis Features

Table 36-4. 3-D Electromagnetic Analysis Features

New or Enhanced Feature Links to Writing
3-D electromagnetic signal via modeling in • “Via Properties Dialog Box” on page 1908
LineSim free-form schematics. • “What If Simulation Methods for Vias” on
page 1058
You can design single-ended and differential • “Via Modeling Work Flow - LineSim”
vias in LineSim, pass the via geometries to a
special built-in version of HyperLynx 3D EM
that automatically creates an S-parameter
model to represent via behavior.

You can use this via model in SI simulation.

Export BoardSim topology to HyperLynx 3D • “Exporting BoardSim Topologies to
EM. HyperLynx 3D EM Designer” on
page 1165
• “Export to HyperLynx 3D EM Dialog
Box” on page 1588

Flow Integration Features

Table 36-5. Flow Integration Features

New or Enhanced Feature Links to Writing
.CCE file support

Restriction: Support for these files is unavailable when running the 64-bit version of
HyperLynx. On Windows, use the 32-bit version of HyperLynx (which is also installed
when you install the 64 bit version) to open CAMCAD files. Select Start > All Programs >
Mentor Graphics SDD > HyperLynx <release> 32-bit > HyperLynx Simulation Software.
By contrast, Linux installations are 64-bit only or 32-bit only.
BoardSim can open and simulate “Opening BoardSim Boards”
CAMCAD Professional encrypted and
compressed files (.CCE) that contain layout
data exported from Expedition PCB or
CAMCAD Professional. These files
support custom-shape pads that .HYP files
do not support.

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 What’s New
Documentation Enhancements

Table 36-5. Flow Integration Features (cont.)

New or Enhanced Feature Links to Writing
eDxD/eExp View can display layout data “eDxD/eExp View” on page 1584
exported as a CAMCAD file from
Expedition PCB or CAMCAD
Professional.

Use this feature to display artwork layers

and other data not supported by the .HYP
file format.

You can select a net in eDxD/eExp View to

simulate in BoardSim, if the same board is
loaded in BoardSim as a .HYP file.

Documentation Enhancements

Table 36-6. Documentation Enhancements

New or Enhanced Writing Links
Added SI and PI tutorial chapters that use “LineSim Tutorials”
designs and models that ship with HyperLynx. “BoardSim Tutorials”
DC drop conceptual circuits with several new “DC Drop Conceptual Circuits” on page 979
images
Updated constraint definitions and waveform “Constraint Definitions”
measurement figures for SI batch simulation in
BoardSim.

Can you please provide documentation feedback to help us plan future writing projects? If so,
do the following:

1. Select Help > Open HyperLynx SI/PI Help.

2. Near the upper-right corner of the browser window, click . and fill out the form.

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What’s New
Documentation Enhancements

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 Appendix 37
Menus

This section contains reference information for the following menus:

• “File Menu” on page 1926

• “Setup Menu” on page 1928
• “Edit Menu” on page 1932
• “View Menu” on page 1933
• “Models Menu” on page 1934
• “Select Menu” on page 1937
• “Simulate SI Menu” on page 1938
• “Simulate PI Menu” on page 1941
• “Simulate Thermal Menu” on page 1943
• “Export Menu” on page 1944
• “Windows Menu” on page 1947

Note
This chapter applies to HyperLynx SI/PI menus. For information about HyperLynx
Thermal menus, see “ThermalSim Menus and Toolbars”.

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Menus
File Menu

File Menu

Table 37-1. File Menu Contents

Menu Item Description
New Free-Form Schematic Creates a new Free-Form Schematic.
New Cell-Based Schematic Creates a new Cell-Based Editor.
New Board (Run PCB Use this to translate a design to a BoardSim board. Opens
Translator) the Choose a File to Translate dialog box. Select a design
file and click Open. This opens the Translate File dialog
box.

See “Creating BoardSim Boards”.

New MultiBoard Project Use to create a new MultiBoard Project. This opens the
MultiBoard Project Wizard.

See “Creating MultiBoard Projects”.

Open Schematic Opens the Open LineSim File dialog box. Select a file to
open a LineSim schematic.

See “Opening LineSim Schematics”.

Open Board Opens an existing BoardSim board.

See “Opening BoardSim Boards”.

Open MultiBoard Project Opens an existing MultiBoard project.

See “Opening MultiBoard Projects”.

Save BoardSim Session File Saves interactive edits to the “BoardSim User Data”
(.BUD) (.BUD) session file.

(BoardSim Only) See “BoardSim Session Files”.

Save --

(LineSim Only)
Save As --

(LineSim Only)
Close Closes the schematic, but does not close HyperLynx.

(LineSim Only)

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File Menu

Table 37-1. File Menu Contents (cont.)

Menu Item Description
Print Prints the schematic.

(LineSim Only)
Run eDxD/eExp View Opens eDxD/eExp View, to view layout designs stored in
.CCE (CADCAM Professional, encrypted and
compressed) format.
Recent Files Lists the last files you opened in HyperLynx. Select a file
to open it.
Exit Closes HyperLynx.

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Setup Menu

Setup Menu

Table 37-2. Setup Menu Contents

Menu Item Description
Stackup • Edit — Opens the Stackup Editor. See Creating and
Editing Stackups.
• Import — Loads stackup information from a STK file.
See “Exporting and Importing Stackups” on
page 1177.
• Export — Saves the stackup information for the
current design to a file. See “Exporting and Importing
Stackups” on page 1177.
• Check — Opens the Stackup Verifier, which displays
stackup error and per-layer metal usage information.
See “Reporting and Correcting Stackup Errors” on
page 366.
Power Supplies • BoardSim — Opens the Edit Power-Supply Nets
dialog box. Use this to edit power-supply net
properties. See “Editing Power-Supply Nets”.
• LineSim — Opens the Set Power-Supply Voltages and
Nets dialog box. Use this to add power-supply nets and
assign voltages. See “Editing Power-Supply Net
Properties”.
Stimulus Opens the Assign Stimulus dialog box. Use the Assign
Stimulus dialog box to assign stimulus to specific pins or
nets in the design.

See “Assigning Stimulus to Specific Pins or Nets” on

page 546.
Padstacks Opens the Padstack Manager dialog box. Use the Padstack
Manager dialog box to create, edit, copy, delete, and
(LineSim Only) rename padstacks in free-form schematics.

See “Managing Padstacks”.

Anti-Objects Opens the Setup Anti-Pads and Anti-Segments Dialog
Box. Use the Setup Anti-Pads & Anti-Segments dialog
box to specify clearances among objects on the same
stackup layer.

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Table 37-2. Setup Menu Contents (cont.)

Menu Item Description
Differential Pairs When a board or schematic is not loaded, select to open
the Differential Pair Net Suffixes Dialog Box. Use this
(BoardSim Only) dialog box to help BoardSim automatically identify
differential pairs by using net name suffixes.

When a board is loaded, select to open the Differential

Pairs Dialog Box. Use this dialog box to help BoardSim
automatically identify differential pairs by using net name
suffixes. You can also use this dialog box to review and
temporarily edit the list of differential pairs.
Enable Crosstalk Select to enable interactive crosstalk simulation in
Simulation BoardSim.

(BoardSim Only) Requirement: The Crosstalk license is required to enable

crosstalk and differential-pair simulation in BoardSim.

BoardSim automatically identifies as coupled differential

pairs any nets driven by IBIS model pins listed in a [Diff
Pin] keyword. You can disable coupling for this type of
differential pair by disabling the “Always treat diff pairs
as coupled” option on the Advanced tab of the Preferences
dialog box. Coupling for this type of differential pair is not
affected by Setup menu > Enable Crosstalk Simulation
settings, by crosstalk threshold voltages, or whether you
have checked out a crosstalk license.

For other types of nets, BoardSim couples nets when you

enable crosstalk simulation and set the crosstalk threshold
voltage to a value lower than the simulated crosstalk
voltage.

See “Running Interactive Crosstalk Simulations in

BoardSim”.
Crosstalk Thresholds Opens the Set Crosstalk Thresholds dialog box. Whenever
you enable interactive crosstalk simulation you should
(BoardSim Only) immediately check and set the crosstalk threshold. The
threshold is used by BoardSim Crosstalk to automatically
identify which other nets are coupled to the selected net. If
the threshold is not set to match the amount of crosstalk
you are concerned about, you could easily run your
simulations with too many or too few aggressor nets.

See “How to Set the Crosstalk Threshold”.

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Table 37-2. Setup Menu Contents (cont.)

Menu Item Description
Enable Lossy Simulation Select to enable lossy modeling to take dielectric and
metal losses into account during signal integrity or power
integrity simulation.

Requirement: The Lossy Lines license is required to

enable lossy simulation.

Restriction: Surface roughness losses are enabled

separately from dielectric losses. See “Surface Roughness
Dialog Box” on page 1871.

See "Editing Lossy Transmission-Line Properties", and

“About Lossy Transmission-Line Modeling”.
Enable Surface Roughness Select to take into account surface roughness losses in
lossy simulation.

Requirement: The Via Models license is required to

enable lossy simulation.

See “About Lossy Transmission-Line Modeling” and

“Surface Roughness Dialog Box” on page 1871.
Roughness Parameters Opens the Surface Roughness Dialog Box. Use this dialog
box to quantify the effects of how the copper foil surface
zigzags vertically away from an averaged smooth surface.

Requirement: The Via Models license is required to

enable lossy simulation.
Via Simulation Method Opens the Select Method of Simulating Vias Dialog Box.
Toggle (select and clear) options in this dialog box to
(BoardSim Only) perform "what if" experiments to see the effects of various
via modeling options on simulation results.

Requirement: The Via Models license is required to

enable advanced via modeling.
Device Kit Opens the Specify Device Kit for Current Design Dialog
Box. Use this dialog box to specify a device kit for the
current design. Device kits typically contain advanced IC
models and design examples that you simulate with
HyperLynx to learn about the technologies they
implement.
Thermal Environment Opens the “Environment Condition Definition Dialog
Box”. Use this dialog box to specify conditions that are
external to the board, such as air temperature and flow.

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Setup Menu

Table 37-2. Setup Menu Contents (cont.)

Menu Item Description
Options Directories—Opens the Set Directories Dialog Box. Use
this dialog box to set the folder location for designs,
models, stimulus, reports, and so on.

General—Opens the Preferences Dialog Box. Use this

dialog box to view and edit properties that affect how
HyperLynx operates and to help you to set up a working
environment that best suits the design and the way you
work.

Reference Designator Mappings—Opens the Edit

Reference Designator Mappings Dialog Box. Use this
dialog box to edit, add, delete, and restore default
reference-designator mappings. Reference-designator
mappings are global and apply to all designs.

Units—Opens the Units Dialog Box. Use this dialog box

to set the measurement units displayed in the Stackup
Editor, board viewer (BoardSim), and Edit Transmission
Line dialog box (LineSim), and other dialog boxes that
display geometric information. For metal layer thickness,
you can select between thickness or weight units. For all
other dimensions, you can select between English or
metric units.

License Checkout and Checkin—Opens the Installed

Options Dialog Box. You must close all open designs to
open this dialog box. Use this dialog box to specify
HyperLynx licensed features you want to acquire or
release, and to specify other license acquisition options.
When HyperLynx starts, it automatically acquires the
selected licenses you select on this dialog box.

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Edit Menu

Edit Menu

Table 37-3. Edit Menu Contents

Menu Item Description
Copy Picture Copies the contents of the Free-Form Schematic Editor to
the windows clipboard.
(LineSim Only)
Copy, Cut, Paste, Delete, --
Rotate, Flip, Undo, Redo

(LineSim Only Commands)

Auto Place LineSim can automatically rearrange symbols in the free-
form schematic to make the schematic more compact or
(LineSim Free-Form visually appealing.
Schematic Editor Only)
Auto Snap Select to move all objects to grid. This automatically
moves all objects that are currently placed off grid so they
(LineSim Free-Form are on grid.
Schematic Editor Only)
Specify grid preferences in the Preferences Dialog Box -
Appearance Tab.
Constraint Template Opens the Define Constraint Template Dialog Box. Use
this dialog box to specify the detailed constraints to export
(LineSim Only) to CES.
Multiboard Project Opens the Open MultiBoard Project File dialog box.

See “Opening MultiBoard Projects”.

Connect Nets with Opens the Connect Nets with Manhattan Routing Dialog
Manhattan Routing Box. Use this dialog box to route an unrouted net with
Manhattan routing, or to unroute a routed net and then
(BoardSim Only) immediately re-route it with Manhattan routing.
Unroute Routed Nets Opens the Unroute Routed Nets Dialog Box. Use this
dialog box to unroute a routed net, partially routed net, or
(BoardSim Only) a net routed with Manhattan routing.
Trace Widths Opens the Change Trace Widths dialog box. You can
perform "what if" signal-integrity simulations by editing
(BoardSim Only) trace widths to vary the impedance of traces on the board.

See “Editing Trace Widths in BoardSim”.

Plain Text File Opens the HyperLynx File Editor. Use this to view and
modify text files.

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View Menu

View Menu
The BoardSim and LineSim viewing operation topics describe these menu items. See “Board
Viewer Operations” and “Schematic Viewing Operations”.

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Models Menu

Models Menu

Table 37-4. Models Menu Contents

Menu Item Description
Assign Models/Values by Opens the Edit Symbol Type Values dialog box for the
Component selected component.

(LineSim Only) Restriction: This option is unavailable if you select more

than one symbol.

See Selecting Models.

Assign Models/Values by Opens the Assign Models dialog box. Use this dialog box
Net to interactively select IC and ferrite bead models, and to
edit resistor and capacitor values. This dialog box also
(BoardSim Only) displays connectivity among bus switch pins.

See Selecting Models and Values for Individual Pins.

Assign Models/Values by Opens the REF-File Editor. Use the .REF file to assign
Reference Designator (.REF .EBD and series bus switch models to reference
File) designators in BoardSim or symbols in the LineSim
schematic. While you can also assign .IBIS, .MOD, and
.PML models with the .REF file, you probably will assign
them interactively.

See “Selecting Models Using the REF File”.

Assign Models/Values by Opens the QPL-File Editor. Use this to create or edit .QPL
Part Name (.QPL File) automapping files, which are used to assign models and
values to components with specific part names.
(BoardSim Only)
See “QPL File Editor”.
Assign Quick Terminator Opens the Assign Models dialog box - Quick Terminator
tab. Use this tab to add a Quick Terminator model to your
(BoardSim Only) board.

See Terminating Nets.

Assign Thermal Models
Library > Master Opens the “Edit Master Library Dialog Box”. Use this
dialog box to display the contents of the master library of
models for HyperLynx Thermal.
Library > Working Opens the “Edit Working Library Dialog Box”. Use this
dialog box to display the contents of the working library
of models for HyperLynx Thermal.

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Table 37-4. Models Menu Contents (cont.)

Menu Item Description
Library > Material Opens the “Edit Material Library Dialog Box”. Use this
dialog box to display the contents of the board materials
library for HyperLynx Thermal.
Set Defaults (Height, Opens the “Set Defaults Dialog Box”. Use this dialog box
Power) to set default board properties for thermal simulation.
Import IDF Opens the Import dialog box. Use this dialog box to
import IDF files into the HyperLynx Thermal design.

See “Importing IDF Files”.

Import Power Map Opens a power map file created by DC drop or DC
drop/thermal co-simulation.

See “Running DC Drop Batch Simulation” on page 995.

Import Power & Th- Opens a file that assigns power dissipation values to many
Resist components.

See“Power and Thermal Resistance Parameter Files”.

Edit IBIS IC Models (.IBS) Opens the HyperLynx Visual IBIS Editor. Use this to
create, edit, verify, and maintain IBIS (I/O Buffer
Information Specification) device models.

See “Creating and Editing IBIS Models”.

Edit Databook IC Models Opens the Edit .MOD Model (Databook Format) dialog
(.MOD) box. Use this dialog box to modify IC models created in
the .MOD format.

See “Editing MOD IC Models”.

Edit Touchstone Models Opens the HyperLynx Touchstone and Fitted-Poles
(.SnP, .ZnP, .YnP) Viewer. Use this to judge the quality and understand the
contents of Touchstone and fitted-poles models.

See “Viewing and Converting Touchstone and Fitted-

Poles Models” on page 1065.
Edit DDRx Timing Models Opens the HyperLynx Timing Model Editor. HyperLynx
(.V) timing models specify net-to-net timing requirements for
signals in the DDRx memory interface. DDRx batch
(BoardSim Only) simulation reports net pairs that do not satisfy net-to-net
timing requirements contained in HyperLynx timing
models.

See “HyperLynx Timing Model Format”.

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Table 37-4. Models Menu Contents (cont.)

Menu Item Description
Run DDRx Controller Opens the HyperLynx Timing Model Wizard. This wizard
Timing Model Wizard helps you create a timing model for a DDRx memory
controller.
(BoardSim Only)
Assign Power Integrity Opens the Assign Power Integrity dialog box. Use this
Models dialog box to assign power-integrity models to IC power-
supply pins. The types of models you assign depend on the
(BoardSim Only) type of power-integrity simulation you plan to run.

See “Assigning Power-Integrity Models - BoardSim”.

Edit Decoupling-Capacitor Opens the Assign Decoupling-Capacitor Groups Dialog
Groups Box. Use this dialog box to override the automatic
assignments by adding/removing individual capacitors
(BoardSim Only) to/from groups. BoardSim automatically assigns
decoupling capacitors with the same capacitance and
maximum pin-to-pin dimensions to the same group.
Edit Decoupling-Capacitor Opens the Assign Decoupling-Capacitor Models Dialog
Models Box. Use this dialog box or Check Capacitor Models page
in various wizards to assign models to decoupling
(BoardSim Only) capacitors. You can temporarily disable model
assignments in order to judge decoupling-capacitor
effectiveness by running power-integrity simulations with
and without the model assignments.
Edit Model Library Paths Opens the Set Directories Dialog Box. Use this dialog box
to set the folder location for designs, models, stimulus,
reports, and so on.
Generate Model Finder Generates the model finder index. This generates
Index HyperLynxIcModels.csv. Do this whenever you add
directories or change the precedence of directories in the
Select IC Model dialog box. Generating the model finder
index makes the newly-available IC models available in
the model-finder spreadsheet.

The model finder index is a database, in comma-

separated-values format, that is named
HyperLynxIcModels.CSV. When you update the model
finder index, it is written to the model directory with the
highest precedence. This behavior produces multiple
HyperLynxIcModels.csv files if you change the model
directory with highest precedence.

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Select Menu

Select Menu
Restriction: This menu is available only in BoardSim.

Table 37-5. Select Menu Contents

Menu Item Description
Net by Name for SI Opens the Select Net by Name dialog box. Use the Select
Analysis Net by Name dialog box to select the name of the net you
want to simulate or display in the board viewer.

See “Selecting Nets by Name”.

Net by Reference Opens the Select Net by Reference Designator dialog box.
Designator for SI Analysis Use the Select Net by Reference Designator dialog box to
select by reference designator and pin number the net you
want to simulate or display in the board viewer.

See “Selecting Nets by Reference Designator”.

Net for PI Analysis Displays a message about selecting nets for power
integrity simulation.

See “Simulations Overview - Post-Layout Tasks”.

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Simulate SI Menu

Simulate SI Menu
Table 37-6. Simulate SI Menu Contents
Menu Item Description
Run Interactive Simulation Opens the Digital Oscilloscope for interactive simulation.
(SI Oscilloscope) Use the oscilloscope to interactively simulate signal
integrity and display the waveforms or eye diagrams. In
BoardSim, you simulate the selected net and its associated
nets. In LineSim, you simulate all the nets in the
schematic that have an enabled driver.

See “Simulating Signal Integrity with the Oscilloscope”

on page 533.
Run Simulation Sweeps Opens the Sweep Manager. Use sweeps to automatically
(Sweep Manager) vary and simulate design property values over a range that
you specify. Sweeps enable you to study the effects of
varying electrical and geometric design properties.

See “Simulating Signal Integrity with Sweeps” on

page 601.
Run Generic Batch Opens the Batch Simulation Wizard. Use generic batch
Simulation simulation to evaluate signal-integrity for an entire board
or group of nets. This capability enables you to screen an
(BoardSim Only) entire board for problems, simulate in detail a group of
critical nets, or verify that design revisions have not
introduced problems on critical nets.

See “Simulating SI for Entire Boards or Multiple Nets”.

Run DDRx Batch Opens the DDRx Batch Simulation Wizard. Use DDRx
Simulation batch simulation to analyze the standard DDR, DDR2,
DDR3, LPDDR, or LPDDR2 memory interface between a
(BoardSim Only) memory controller device and its memory devices.

See “Simulating DDRx Memory Interfaces”.

Run IBIS-AMI Channel Opens the IBIS-AMI Channel Analyzer to simulate
Analysis SERDES channels in the time domain with millions of
bits in a relatively short amount of time.

See “Simulating Signal Integrity with IBIS-AMI Channel

Analysis” on page 611.

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Table 37-6. Simulate SI Menu Contents (cont.)

Menu Item Description
Show Previous AMI Opens the HyperLynx IBIS-AMI Sweeps Viewer, from
Sweeps Results which you can open an .SDS (simulation data storage) file
to display previous IBIS-
AMI sweep simulation results.

See “Simulating Signal Integrity with IBIS-AMI Channel

Analysis” on page 611
Run FastEye Channel Opens the FastEye Channel Analyzer. Use the FastEye™
Analysis Channel Analyzer to create eye diagrams, statistical
nested-contour eye diagrams, worst-case bit stimulus, and
optimum tap weight values for pre-emphasis and decision-
feedback equalization (DFE) circuits.

See “Simulating Signal Integrity with FastEye Channel

Analysis” on page 629.
Generate Worst-Case Eye Opens the FastEye Channel Analyzer to generate a worst-
Stimulus case eye stimulus file. See “FastEye Channel Analyzer -
FastEye/Worst-Case Analysis Page” on page 1612.
Optimize Termination Opens the Terminator Wizard. Use the Terminator Wizard
dialog box to display information about current and
recommended termination for a net. You can also apply
the recommend termination, using Quick Terminators,
from this dialog box.

See “Optimizing Termination with the Terminator

Wizard” on page 945.
Attach Spectrum Analyzer Opens the Set Spectrum Analyzer Probe (EMC) dialog
Probe box. In LineSim EMC/BoardSim EMC, the "probe"
means either an antenna or a current probe. The antenna
measures electric-field strength like you would in an EMC
lab. The current probe gives you a way of viewing the
current flowing at a point in your circuit.

See “Setting Up the EMC Antenna or Current Probe” on

page 906.
Run Interactive EMC Opens the Spectrum Analyzer. Use the Spectrum
Simulation (Spectrum Analyzer to run interactive electromagnetic compatibility
Analyzer) (EMC) simulation on the selected net.

See “Simulating EMC with the Spectrum Analyzer” on

page 887.

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Related Topics
“Simulations Overview - Pre-Layout Tasks”
“Simulation Overview - Post-Layout Tasks”

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Simulate PI Menu

Simulate PI Menu
Restriction: This menu is unavailable when a cell-based LineSim schematic is open.

Table 37-7. Simulate PI Menu Contents

Menu Item Description
Run DC Drop Simulation Opens the DC Drop Analysis dialog box. Use the DC
(HyperLynx PI Drop Analysis dialog box to simulate DC drop for power-
PowerScope) supply nets.

See “Simulating DC Voltage Drop” on page 963.

Run DC Drop Batch Opens the Batch DC Drop Simulation dialog box. Use the
Simulation Batch DC Drop Simulation dialog box to simulate DC
drop in BoardSim for multiple power-supply nets at a
(BoardSim Only) time.

See “Running DC Drop Batch Simulation” on page 995.

Show Previous DC Drop Displays the results from the last DC Drop analysis.
Results (HyperLynx PI
PowerScope) See “Simulating DC Voltage Drop” on page 963.

(LineSim Only)
Analyze Decoupling Opens the Decoupling Wizard. Decoupling analysis helps
(Decoupling Wizard) you evaluate the ability of the power-distribution network
(PDN) to provide low-impedance paths for IC current
loads.

See “Analyzing Decoupling” on page 1013.

Analyze Signal-Via Opens the Bypass Wizard. Bypass analysis helps you
Bypassing (Bypass Wizard) evaluate the ability of the power-distribution network
(PDN) to provide low-impedance return current paths for
signals transmitted through a single-ended via.

See “Analyzing Signal-Via Bypassing” on page 1051.

Run Plane-Noise Opens the Plane Noise Analysis dialog box. Plane-noise
Simulation (HyperLynx PI simulation shows how noise propagates across plane
PowerScope) regions of the power-distribution network (PDN) when IC
power-supply pins draw large amounts of transient
current.

See “Simulating Plane Noise” on page 1037

Related Topics
“Simulations Overview - Pre-Layout Tasks”

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“Simulations Overview - Post-Layout Tasks”

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Simulate Thermal Menu

Simulate Thermal Menu

Restriction: The Thermal license is required to run thermal simulation.

Table 37-8. Simulate Thermal Menu Contents

Menu Item Description
Run Thermal Simulation Runs thermal-only analysis on the BoardSim board.
Run PI/Thermal Co- Opens the Batch DC Drop Simulation dialog box, to set up
simulation thermal/DC drop co-simulation.

Related Topics
“Thermal QuickStart”
“Simulations Overview - Post-Layout Tasks”

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Export Menu

Export Menu
This section contains the following topics:
• BoardSim Export Menu Contents
• LineSim Export Menu Contents

Table 37-9. BoardSim Export Menu Contents

Menu Item Description
Net to • Free-Form Schematic — Opens the Export to LineSim
Free-Form Schematic dialog box. Use this to export a
selected net to LineSim. See “Exporting BoardSim
Nets to LineSim” on page 1161.
• SPICE Netlist — Opens the Export to SPICE Netlist
dialog box. You must select a net before you select this
option. See “Exporting Nets to SPICE Netlists” on
page 1157.
• S-Parameter Model — Opens the Extract S-Parameter
Model dialog box. Use the Extract S-Parameter Model
dialog box to export passive networks, such as
BoardSim nets to S-parameter models representing
equivalent circuits. See “Exporting Nets to S-
Parameter Models” on page 1152.

Requirement: The SPICE Output and Advance Scope

licenses are required to export nets to S-parameter
models.
Board To • IBIS .EBD File — Requirement: The EBD Writer
license is required to generate IBIS .EBD models from
BoardSim board files. See “Exporting BoardSim
Boards to IBIS EBD Models” on page 1169.
• ICX NDD File — Opens the Export To ICX dialog
box. Run Export to ICX to create the files needed to
simulate the board in ICX. See “Exporting BoardSim
Boards to ICX” on page 1172.
HyperLynx 3D EM Opens the Export to HyperLynx 3D EM Dialog Box.
Topology
See “Exporting BoardSim Topologies to HyperLynx 3D
EM Designer” on page 1165.

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Export Menu

Table 37-9. BoardSim Export Menu Contents (cont.)

Menu Item Description
Signal-Via Model Opens the Via Model Extractor Wizard. Use this to export
a signal via to an S-Parameter model.

Requirement: The Signal-Via Bypass Models license is

required to export via models.

See “Exporting Signal Vias to S-Parameter Models” on

page 1180.
PDN Model Opens the PDN Model Extractor Wizard. Use this to
export a detailed model of the entire power-distribution
network (PDN), with external ports at your choice of IC
power-supply pin and signal via locations.

Requirement: The PDN Model Export license is required

to export PDN models.

See “Exporting PDNs to S-Parameter Models” on

page 1183.
ECO Back-Annotation File Opens the Generate Back-Annotation File/Data dialog
box. This dialog box allows you to choose the types of
changes that you want to back annotate to your PCB CAD
program, and to indicate whether you want to dynamically
transfer the back annotation to your PCB CAD program.

See “Back-Annotating Board Changes”.

Reports • Net Statistics — Opens the Statistics for Selected Net
dialog box. See “Reporting Net Properties”.
• Board Statistics — Opens the Statistics for Selected
Board dialog box. This creates a report containing the
total number of nets, segments, pins, and vias on the
board.
BoardSim reads the .HYP file to generate the report.
Depending on how the .HYP-file translator for your
PCB-layout package works, there may be small
discrepancies from similar totals reported by your
layout software.
• Design Change Summary — Opens the Design
Changes dialog box. Use the Design Changes dialog
box to generate a concise report of all the component
changes you have made on your board to improve
signal quality or lower radiated emissions (EMC). See
“Reporting Design Changes”.

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Export Menu

Table 37-9. BoardSim Export Menu Contents (cont.)

Menu Item Description
Design Archive Opens the Archive Design Dialog Box. Use the Archive
Design dialog box to automatically gather and compress
the design simulation files for your board.

Table 37-10. LineSim Export Menu Contents

Menu Item Description
BoardSim Board (.HYP Restriction: The Via Models license is required to export
File) vias to BoardSim.
SPICE Netlist See “Exporting Nets to SPICE Netlists” on page 1157.
S-Parameter Model Use the Extract S-Parameter Model dialog box to export
passive networks, such as LineSim schematics, to S-
parameter models representing equivalent circuits. See
“Exporting Nets to S-Parameter Models” on page 1152.
Constraint Template Opens the Export Constraint Template dialog box. Use the
Export Constraint Template dialog box to set up and
export a constraint template file that is based on the
properties of a net in the free-form schematic.

See “Exporting Constraint Templates from LineSim” on

page 1175.
Model • Signal-Via Model — Opens the Via Model Extractor
Wizard. See “Exporting Signal Vias to S-Parameter
Models” on page 1180.
• PDN & Channel Model — Opens the PDN Model
Extractor Wizard. See “Exporting PDNs to S-
Parameter Models” on page 1183.
Design Archive Opens the Archive Design Dialog Box. Use the Archive
Design dialog box to automatically gather and compress
the design simulation files for your schematic.

Related Topics
“Exporting Design and Model Data” on page 1151

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Windows Menu

Windows Menu
Use the Windows menu in LineSim to switch between a free-form schematic and a PDN layout.

Restriction: You need the DC Drop, Decoupling, or Plane Noise license to enable the PDN
Editor and the Windows menu.

Cell-based LineSim and BoardSim do not display this menu.

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Glossary

—A—
aggressor net
A net transmitting signals and causing unwanted voltage noise (crosstalk) on nearby (victim)
nets.

anti-pad
An isolation shape providing clearance between a pad and surrounding metal, such as an AC
ground plane or area fill. An anti-pad defines the shape and size of the clearance area (copper
void) that should be created while pouring around a pin or via if it intersects a copper pour
polygon.

anti-segment
An isolation shape providing clearance between a trace segment and surrounding metal, such as
an AC ground plane or area fill. An anti-segment defines the shape and size of the clearance area
(copper void) that should be created while pouring around a trace if it intersects a copper pour
polygon.

antipad
See anti-pad.

antisegment
See anti-segment.

associated net
A net electrically connected to one or more other nets by conduction or coupling (crosstalk).
See also: electrical net

attenuation
A reduction of the amplitude of a signal due to losses in the net carrying the signal.

automapping
A method that assigns an IC model or passive component value to all the eligible pins on a PCB
component with a specific reference designator or part type.
.REF automapping files assign a model or value to pins on a component with a specific reference
designator.
.QPL (qualified parts list) automapping files assign a model or value to pins on all components
with a specific part name, regardless of its reference designator.

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—B—
backward crosstalk
The coupling (crosstalk) on a victim net that flows in the direction opposite of the signal
transmitted by a nearby aggressor net. Backward crosstalk flows toward the IC pin on the victim
net located closest to the switching driver on the aggressor net. The waveform usually has no
resemblance to the coupled signal.
Also known as “near-end crosstalk”.
See also: aggressor net, victim net

barrel
In a via, the round metal tube (plated hole) that penetrates PCB layers.
See also: via
bathtub curve
A graph showing the probability of bit errors at a receiver for various sampling locations across
the bit interval. Bathtub curves indicate the quality of sampling locations by plotting the
probability of a bit-transmission failure at each sampling location. "Bathtub curves" are so-
named because their overall appearance resembles the cross-section of a bathtub.

Bathtub Curve

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BEM
See boundary-element method (BEM).

bit error rate (BER)

The probability of a bit error at a receiver at a specific sampling location in the bit interval. Bit
error rates can be calculated by analysis or test equipment. When measured with test equipment,
the bit error rate is (number_of_incorrectly_received_bits / number_of_total_sent_bits).
See also: bathtub curve

bit error ratio (BER)

See bit error rate (BER).

bit interval
The duration of an individual bit transmitted in a data stream. Also known as unit interval (UI).

blind via
A via connecting a trace on a surface PCB layer to a trace on an inner PCB layer. Blind vias do
not penetrate through the entire board to both surface layers.
See also: via

boundary-element method (BEM)

Type of field solver used to perform power-integrity analysis in the frequency domain.

BUD file
A file containing interactive design changes for a BoardSim board, such as stackup edits and
interactive IC model assignments.

buried microstrip
A trace routed on an inner layer of the PCB, with a dielectric layer and air on one side and a
dielectric plus a plane layer on the other side.

Buried Microstrip

See also: microstrip, stripline

buried capacitance
A pair of plane layers in a PCB separated only by a dielectric layer, so that no signal layer is
between them. For high-speed designs where one plane layer is ground and the other is power,
the dielectric layer can be made sufficiently thin to provide a bypass path for return currents.

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buried via
A via completely contained within the inner layers of a board and that does not penetrate either
surface of the PCB.
See also: via

bypass capacitor
A capacitor connected to a transmission plane that is used to provide a low-impedance path for
return currents for a digital signal to move between transmission-plane layers.
A bypass capacitor can also act as a decoupling capacitor.
See also: transmission plane, power-distribution network (PDN), decoupling capacitor

—C—
causality error
Data in a Touchstone model that indicate a propagation speed faster than physics allow, or a
reversal in the phase trajectory.

channel - data channel

A set of drivers, receivers, and physical interconnections of a net configured to transmit data
according to a communications interface standard, such as DDR2 and PCI Express.

characteristic impedance - Z0
Resistance to current flow caused by the resistive, inductive and capacitive effects of a
transmission line. Impedance is affected by layer stackup dimensions and materials, and trace
dimensions and clearances.
Characteristic impedance is a property unique to the distributed nature of transmission lines.
Because transmission lines consist of a continuous mixture of capacitance and inductance, they
"look" instantaneously like a resistance to a transmitted signal.

common mode
A current or voltage transmitted at the same time by both members of a differential pair.

constraints
A set of rules that define how PCB component pins are to be connected, such as maximum
propagation delay, net scheduling, and so on.

copper pour
A shape created by poured metal on a PCB layer. Sometimes also called “pour outline” or “plane
area.” The pouring operation implemented by the PCB design system automatically creates
clearance areas around pins, traces, and vias on other nets.
See also: anti-pad, plane area, pour outline

copper void
A polygon-shaped area inside a copper pour that is kept free of metal when pouring occurs.
A copper void is sometimes also called a “pour cutout.”

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coupled transmission lines

Two or more conductors sufficiently close together to exchange energy with each other when
transmitting signals. For differential pairs, coupling provides a way to control signal impedance
and to reject interference from nearby aggressor nets.

coupling region
A two-dimensional cross section of the PCB that contains two or more coupled conductors, and
assumed to have constant geometry over some specified length.

Coupling Region

crosstalk
The unwanted coupling of voltages and currents among neighboring nets that are transmitting
signals.
See also: backward crosstalk, forward crosstalk

cutout
See copper void and pour cutout.

—D—
databook model
See MOD model.
decision-feedback equalization (DFE)
The circuitry of an IC receiver that restores the high-frequency content of a signal that is lost
when the signal is transmitted through the channel.

decoupling capacitor
A capacitor connected to a transmission plane that is used to quickly store and release energy for
local power-distribution network (PDN) delivery and to lower transmission-plane impedance.
A decoupling capacitor can also act as a bypass capacitor.
See also: transmission plane, power-distribution network (PDN), bypass capacitor

design rule check (DRC)

An analysis of the geometric and electrical properties of a PCB design that reports the location of
structures and layout configurations that can produce operational failures or degrade signal
integrity, power integrity, electromagnetic compatibility (EMC), and so on. Design rule checking

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takes into account routing, component placement, copper pours and voids, stackup, and electrical
properties.
A design rule check can use both the layout data and connectivity data of the PCB design to
locate design rule violations. Design rule checks can also include specific design rules specified
in a rule file.

DFE
See decision-feedback equalization (DFE).

dielectric
A material that does not conduct electricity and is used in PCB designs to insulate conductors
and encapsulate components.

dielectric constant
Ratio of the charge stored by air to the charge stored by a specific material. A dielectric constant
indicates the ability of a material to store a charge.

differential impedance
For a pair of symmetric-coupled traces, the differential impedance is the trace-to-trace resistance
that will properly terminate a pair of signals driven in differential mode.

differential net
A special kind of electrical net, used by a differential pair, formed by the paired combination of
two other electrical nets.
See also: electrical net

differential pair
Two conductors deliberately routed parallel to each other and with a constant trace-to-trace gap
to provide uniform impedance and noise immunity from neighboring aggressor nets.

driver
An IC pin transmitting a signal on the net.

—E—
edge rate
The speed at which a device transitions from one logic state to the other, specified as volts/time.
Rise and fall time depend on the edge rate, plus other factors affecting signal integrity.

effective series inductance

See equivalent series inductance (ESL).

effective series resistance

See equivalent series resistance (ESR).

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electrical board description (EBD)

An extension of the IBIS specification that describes the electrical behavior of a complicated
interconnection. An EBD model contains physical information, such as trace length and stackup,
but not electrical properties, such as coupling.
See also: IBIS

electrical net
A set of nets on the PCB that are connected only by passive components, such as resistors and
capacitors.
See also: differential net, associated net

electromagnetic compatibility (EMC)

Determining whether the radiated emissions of a design fall below government limits at every
frequency. Excessive radiated emissions can cause electromagnetic interference in nearby
devices, possibly affecting their operation. Government limits include U.S. FCC, European
CISPR, and Japanese VCCI.

electromagnetic interference (EMI)

See electromagnetic compatibility (EMC).

equivalent series inductance (ESL)

In a capacitor simulation model, ESL includes the effects of the inductance of the terminal leads.
ESL and the capacitor capacitance value determine the self-resonance frequency of the capacitor.
F = 1/(2*pi*sqrt(LC)).

equivalent series resistance (ESR)

In a capacitor simulation model, ESR includes the effects of the resistance of the dielectric and
plate materials, electrolytic solution, and terminal leads.

eye diagram
Cutting up a waveform into bit interval lengths and overlaying the waveform fragments to see
how much the timing variation of the waveform crossover points erodes the range of valid data
sampling locations. The waveform crossover points cluster around the bit interval boundaries,
and the overall visual effect vaguely resembles a human eye.
Signal distortion related to ISI is typically caused by high-frequency signal attenuation and by
residual transient responses, such as crosstalk and reflections, to previous signal transitions on
the interconnect.

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Eye Diagram

See also: inter-symbol interference (ISI), FastEye diagram

eye diagram mask

The “keep out” areas that waveforms in an eye diagram should avoid. Waveforms crossing into
keep out areas may violate signal-protocol requirements or other performance requirements.

Eye Diagram Mask

—F—
fall time
The time it takes for a signal to switch from the logic one state to the logic zero state.

FastEye diagram
An eye diagram produced by analyzing the response of a net to a step stimulus and a pulse
stimulus. By contrast, “standard” eye diagrams are specially-formatted waveforms created by
time-domain simulations.
See also: eye diagram

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FFS file
Geometric and electrical PCB design information in a format that can be read by the free-form
schematic editor in HyperLynx LineSim. FFS files contain nets, active component (IC) names,
passive component values, stackup, pad stacks, and so on.
See also: TLN file

field solver
A simulation program that reports the electrical characteristics of a system of conductors and
dielectrics, using one or more of the basic equations of electromagnetic theory, such as
"Maxwell's equations." Field solvers can report the capacitances, inductances, propagation
velocities, and characteristic impedances of a coupling region cross section.
See also: coupling region

finite-difference time-domain (FDTD)

The type of simulator to perform electromagnetic field analysis using finite-difference modeling
in time domain. One of its applications is plane-noise analysis.

flight time
The time it takes for a signal to propagate from a driver, through the net, to a receiver. Flight
time, sometimes also called interconnect delay, begins when the transitioning signal passes
through Vmeasure on the driver pin and ends when the signal passes through Vih (rising edge) or
Vil (falling edge) on the receiver pin.
See also: flight-time compensation

flight-time compensation
Mathematically adjusting the calculated interconnect delay to account for the driver switching
into the actual PCB interconnect load, as opposed to the driver switching into an arbitrary test
fixture load specified by the IC model or component datasheet.
See also: flight time

fknee
See knee frequency.

forward crosstalk
The coupling (crosstalk) on a victim net that flows in the same direction of the signal transmitted
by a nearby aggressor net, as seen at the end of the victim net farthest from the signal source of
the aggressor. Forward crosstalk flows toward the IC pin on the victim net located away from the
the switching driver on the aggressor net.
Also known as “far-end crosstalk.”
See also: aggressor net and victim net

FDTD
See finite-difference time-domain (FDTD).

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—G—
glitch
A non-monotonic area of a waveform caused by ringing, reflections, or other signal integrity
factors. A glitch passing through the threshold voltage of a receiver can cause system operational
failure.
See also: non-monotonic

—H—
HYP file
Geometric and electrical PCB design information in a format that can be read by HyperLynx
BoardSim. .HYP files contain nets, active component (IC) names, passive component values,
stackup, pad stacks, and so on.

—I—
IBIS
IBIS stands for “I/O Buffer Information Specification” and is an industry-standard IC model
format that describes IC behavior without revealing how the IC is implemented.

IBIS-AMI
IBIS-AMI is an industry standard that uses algorithmic code to model the complex and non-
linear transformations of signal waveforms inside transmitters and receivers. Shared executable
library files (.DLL) implement the algorithmic code and protect intellectual property (IP).
Typical AMI .DLL files contain proprietary algorithms for transmitter pre-emphasis, receiver
equalization and DFE, and receiver clock and data recovery. The algorithmic modeling interface
(AMI) standard first appeared in I/O Buffer Information Specification (IBIS) version 5.0.

IC automapping
See automapping.

impulse response
A time derivative of the step response. The behavior does not come directly from simulation.
Instead the process of finding the impulse response includes simulating the step response and
taking the derivative numerically. This term applies to IBIS-AMI and FastEye channel analysis.
See also: pulse response, step response

insertion loss
A reduction of the amplitude of a signal due to adding a device to the net carrying the signal. In
terms of S-parameters, insertion loss results when the absolute voltage of the incident signal is
more than the absolute voltage of the transmitted voltage.
value of the transmitted voltage is less than the absolute value of the incident voltage

interconnect delay
See flight time.

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inter-symbol interference (ISI)

A form of signal distortion in very fast digital signaling, where the effects of a previous bit linger
or persist on a net while more bits are sent. In slower digital signaling, where the time length of a
bit was much longer than the delay on the net, it was common that whenever a bit was sent, that
its signal on the receiver pin would look identical to the previous and next time it was sent. But
when digital signaling speed increases to the point where the length of a bit is shorter than the
delay of its net, multiple bits can co-exist on the net and interfere with each other.
The result is that the rising or falling edge for a signal is no longer guaranteed to look the same
every time it arrives at a receiver pin. Specifically, its arrival delay might be a little longer or
shorter, and its voltage amplitude might be a little larger or smaller.
ISI can spread the arrival time of individual data bits in a net so much that the receiver cannot
reliably distinguish among them. Signal distortion that is related to ISI is typically caused by
high-frequency signal attenuation and by residual transient responses, such as crosstalk and
reflections, to previous signal transitions on the interconnect. In an eye diagram, ISI-related
signal distortion can appear as jitter, voltage overshoot or undershoot, and so on.
See also: eye diagram, FastEye diagram

—J—
jitter
The distribution of signal transition times away from the ideal time.

—K—
knee frequency
The frequency at which the band width of the net begins to significantly attenuate the energy
content of a switching signal.

—L—
lossy
The attenuation of the energy in a switching signal due to the skin effect (resistance caused by
currents crowding the surface of the conductor) and dielectric loss (resistance caused by heating
of the dielectric material).

—M—
Manhattan routing
Routing traces only on the X-Y routing tracks on the PCB. All corners are 90 degree angles.

memory controller
The memory Controller is the component on the main board that interfaces between the DRAMs
and the central-processing-unit (CPU). The memory controller can also be of different
technology types: FPGA, microcontroller or chipsets. In some of the latest CPUs, the memory
controller circuitry has been integrated into the core. Memory controllers come in different
packages with variations in pin-counts.

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microstrip
A trace routed on the PCB surface. It has air on one side and a dielectric plus a plane layer on the
other side.

Microstrip

See also: buried microstrip, stripline

microvia
A very narrow and short via. Microvias enable high-density interconnect by increasing routing
density and decreasing signal load. Microvias are typically drilled by a laser.

mixed plane layer

See partial plane layer.

MOD model
A HyperLynx IC model format that includes silicon behavior and package pin capacitance, but
not package pin inductance. MOD models are inherently bidirectional. Sometimes known as
“databook model.”
See also: PML (package model library) file

—N—
non-monotonic
Data that reverse a trend of an ever-increasing or ever-decreasing numeric sequence.

Non-monotonic

—O—
overshoot
The portion of a signal transition that extends beyond the steady-state voltage (overshoot-signal
integrity) or the power rail voltage (overshoot).

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Rising Overshoot - Signal Integrity

Falling Overshoot - Signal Integrity

—P—
pad
A shape that connects a component pin or a via to a metal layer in the PCB. Pads of through-pin
components have plated through-holes in them. Pads of surface mount components have no
drilled holes in them.
See also: pad clearance

pad clearance
The minimum gap or space between the pad and other conductive objects on the same metal
layer.

padstack
A round metal tube (plated hole) and set of pads penetrating some or all PCB layers, that
electrically connects pads on different board layers.
A via is a specific instance of a padstack.
See also: via

PAK file
A HyperLynx package model format describing the electrical connections in resistor and
capacitor network packages.

partial plane layer

A stackup layer containing both signals and AC ground regions.

passivity error
A passivity error exists if the sum of energy coming out of the ports exceeds the energy going
into one of the ports. Touchstone models for passive components, such as a connectors, should
be passive. Any number of model-generation problems can produce passivity errors.

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PCB stackup
A set of metal and dielectric layers stacked over one another, like a deck of cards, to form a
printed circuit board (PCB).

PCB Stackup

power-delivery network
See power-distribution network (PDN).

power-distribution network (PDN)

A network of PCB elements providing power to ICs and passive components, and providing
return current paths for digital signals and IC power-supply pins.
PDNs consist of metal areas (like copper fills or plane layers), IC packages, vias,
bypass/decoupling capacitors (and their mounting), trace segments, buried capacitances, and so
on.

power-distribution system (PDS)

See power-distribution network (PDN).

PJH file
HyperLynx project file. For individual LineSim schematics or BoardSim boards, the PJH file
contains various simulation settings and preferences. For BoardSim MultiBoard projects, the
PJH file contains the list of boards in the project, electrical properties for board-to-board
interconnections, and various simulation settings.

plane area
See copper pour.

plane layer
A solid or patterned metal layer in the PCB stackup that is tied to a DC voltage, such as VCC or
ground. Plane layers provide return current paths and electromagnetic shielding.

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PML (package model library) file

An extension of the MOD IC model format that adds component pin out and package parasitic
information. A PML model defines a MOD model, directionality, and parasitic R/L/C for each
pin.
See also: MOD model

pour cutout
See copper void.

pour outline
See copper pour.

power integrity
Maintaining a constant power source voltage with little or no voltage drop or electromagnetic
interference between points on a printed circuit board or within a circuit. Power integrity can
become a greater problem for designs operating at high switching speeds.
See also: voltage drop

pre-emphasis
The circuitry of an IC driver that increases the high-frequency content of the transmitted signal,
to help overcome the high-frequency losses imposed by the channel on the signal.

prepreg
A PCB stackup layer that is spongy or lacks stiffness until it is cured. A prepreg layer is typically
adjacent to a rigid layer.

pulse response
A response of a channel on an isolated bit, where the bit causes a rising and falling transition,
such as in a 00000000001000000000 bit sequence. This behavior is also known as a bit response.
This term applies to IBIS-AMI and FastEye channel analysis.
See also: step response, impulse response

—Q—
QPL (qualified parts list) file
See automapping.

quick terminator
A simulation-only termination component. Quick terminators are used during “what if”
experiments in HyperLynx BoardSim, to identify termination configurations that improve the
signal integrity of the net.

—R—
rank
A group of DDRx DRAMs that are tied to a single, unique, chip select signal. The number of
chip select signals on the memory controller determines the supported number of memory ranks.

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A rank is usually made up of 64 bits in a DDRx interface. The number of DRAMs that makes up
a rank depends on the width of the DRAMs used. For example, if you use x16 DRAMs, 4
DRAMs make up a rank. Note that if you have two sided DIMMs, this does not mean you have
two ranks per DIMM.

receiver
An IC pin that observes signals transmitted by a driver on the net.

REF file
See automapping.

reference designator
A unique name identifying a specific instance of a physical component in the design. Reference
designators typically consist of an alphabetic prefix corresponding to the function of the
component, and a sequential numeric suffix identifying the instance of the component. In
software, reference designators are often stored as the value of the REF property associated with
a specific component or package.
Common conventions for reference designator alphabetic prefixes include U to represent IC
components, R to represent resistors, and C to represent capacitors. Thus, a component with a U4
reference designator represents a specific IC in the design. Similarly, R17 represents a specific
resistor, and C35 represents a specific capacitor. Reference designators are sometimes (but not
always) assigned on a grid system according their physical location on the printed circuit board.

reference plane
A plane layer in the PCB that is tied to a DC voltage, and through which return current flows for
digital signals and IC current sinks.
A signal might switch reference planes when it passes through a via or passes over a gap or slot
in the current reference plane, if another plane layer provides a return current path with a lower
impedance.

reflection
The portion of energy in a high-speed signal that is sent back toward the driver as the signal
meets an impedance change in the transmission line. Reflections can cause ringing and
overshoot.

return current
Return current flows from the load to the source through structures located in the power-
distribution network (PDN).

ringback
How much the waveform returns toward the timing threshold voltage, after initially passing
through it. Excessive ringback can cause unwanted switching at the receiver, because the
waveform passes through the timing threshold more than once.
The figure below shows how far the rising waveform “falls back” after first passing through the
receiver logic high timing threshold.

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Ringback High Example

ripple
DC voltage is often generated by using a power supply whose output is a stepped down,
rectified, and filtered AC source voltage. Any remaining super-imposed alternating voltage on
top of the DC voltage is called the ripple voltage.

rise time
The time it takes for a signal to transition from the logic low state to the logic high state.

round robin
A driver-enabling algorithm that produces a series of simulations, where each simulation
represents a specific driver on the net taking a turn driving the net. Only one driver is enabled for
each simulation. Nets with multiple bidirectional, three-state, open-drain, or open-collector IC
pins are simulated multiple times, once for each driver driving the net.
In the following figure, round robin runs the simulations listed in the table, one simulation for
each driver taking its turn to drive the net.

Round Robin

Round Robin - Sequence of Enabled Drivers

Simulation U3.13 Driver U6.13 Driver U7.13 Driver
1 enabled disabled disabled
2 disabled enabled disabled

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Round Robin - Sequence of Enabled Drivers (cont.)

Simulation U3.13 Driver U6.13 Driver U7.13 Driver
3 disabled disabled enabled

—S—
segment
The portion of a trace between two vertices on the same layer.

signal integrity
The quality of a signal at a receiver pin. Signal integrity can be judged by measuring
delay/timing, ringing, overshoot, multiple threshold transitions, and so on.

signal layer
A stackup layer used to route signal traces instead of serving as a ground or fixed voltage
function.
See also: mixed plane layer

SLM model
HyperLynx single-transmission line model used to model uncoupled connectors. SLM stands for
“single (transmission-)line model.”

solder mask
A screened or laminated dielectric coating on the surface of a PCB. The coating prevents solder
from adhering to selected areas and forming bridges (unwanted conductive paths) between traces
and pads during soldering. Solder mask is also known as "conformal coating" and "SMOBC"
(solder mask over bare copper).

source synchronous
A method that adds clock information to the data stream. This method avoids using a global
clock signal, which can introduce skew and jitter problems. Communication interface protocols,
such as DDRx, determine how to add/remove clock information to/from the data stream.
split plane layer
A plane layer with isolated areas tied to different DC voltages.
See also: plane layer

step response
A response of a channel on an isolated transition, such as a logic 0 to a logic 1. This behavior is
also known as an edge response. This term applies to IBIS-AMI and FastEye channel analysis.
See also: step response, impulse response

stitching via
A stitching (or shorting or caging) via is one which shorts together metal on two plane layers. In
a sense, a stitching via is a perfect capacitor; it provides an extremely low-impedance, high-
bandwidth connection between planes.

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stripline
A trace routed on an inner layer of the PCB, with plane layers on both sides.

Stripline

See also: buried microstrip and microstrip

surface mount device (SMD)

A component whose pins attach to the surface of a circuit board rather than running through the
circuit board. A surface mount component does not require component holes on the circuit board.
Surface mount components also allow you to place two components at the same x,y location on
the circuit board; that is, one surface mount component on the top surface and one surface mount
component on the bottom surface.
See also: through-hole device

stub signal trace

A branch off the main path of the signal trace, typically leading to a secondary load such as a
terminator.

Stub Signal Trace

stub via
A portion of the via barrel that is not used to transmit the signal. Stubs are formed when the via
barrel extends beyond the signal layers used to transmit the signal.
See also: via

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—T—
terminator
One or more components added to the net to improve signal integrity. Terminators work by
absorbing or redistributing reflected energy caused by impedance mismatches in the circuit.

test point
A pad or via added to the board whose purpose is to apply or sense a signal for testing by an
automated test process or for manual contact.

through-hole device
A component whose pins run through the circuit board (and usually come out the opposite side)
rather than staying only on the surface.
See also: surface mount device (SMD)

time of flight
See flight time.

TLN file
Geometric and electrical PCB design information in a format that can be read by the cell-based
schematic editor in HyperLynx LineSim. Like FFS files, TLN files contain nets, active
component (IC) names, passive component values, stackup, and so on.
See also: FFS file

topology
The geometric or logical layout of traces, signal layers, IC pins, vias, and so on used to
implement a net in a PCB.

Touchstone model
A model using n-port network parameter data to represent passive interconnect networks and
active devices. Touchstone models containing S-, Y-, or Z-parameter data are often used to
represent equivalent circuits for backplane connectors and IC packages. Part of this popularity
resulted because vectored network analyzers (VNAs) make it relatively easy to collect n-port
network parameter data for a circuit and create a Touchstone model for it.
The Touchstone model format was originally developed by Agilent Corporation and has been
adopted by the EIA/IBIS Open Forum.

transmission line
Any form of conductor that carries a signal from a source to a load. The transmission time is
usually long compared to the speed or rise time of the signal, so that coupling, impedance, and
terminators are important to preserving signal integrity.
A model of a well-behaved signal-transmission path, commonly formed by a series of routed
PCB trace segments which have a well-defined return-current path in near proximity.

1968 BoardSim User Guide, v8.2

February 2012
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

transmission plane
A cavity formed by two metal planes or metal regions on a PCB that stores and propagates
energy to IC power-supply pins. The metal regions are not mechanically connected. If the metal
regions have different X/Y geometries, the transmission plane exists where the metal regions
overlap each other.

Transmission Plane - Model

The figure below shows three transmission planes formed by four plane layers. For visual clarity,
the figure does not contain geometries that create additional transmission planes, such as splits
on plane layers and copper pours on signal layers.

BoardSim User Guide, v8.2 1969

February 2012
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Transmission Plane - Three T-Planes in an Eight-Layer Stackup

See also: “About Transmission Planes” on page 1373

tube
See barrel.

—U—
unit interval (UI)
See bit interval.

unrouted net
A net whose pin-to-pin connections are defined, but whose pin-to-pin routing is not fully
defined.

—V—
via
For signal integrity and traditional usage, a via is an instance of a padstack that connects traces
on different metal layers on a circuit board, connects traces to a component pin, or shorts
together AC ground planes. A via enables a net to connect to another layer of the circuit board.
For power integrity, a via is any object that can transmit current vertically through a transmission
plane. Examples of power-integrity vias include signal vias, stitching vias, mounting pins of
decoupling and bypassing capacitors, and IC power-supply pins.

1970 BoardSim User Guide, v8.2

February 2012
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Via

See also: padstack, transmission plane

victim net
A net receiving unwanted noise (crosstalk voltage) from nearby (aggressor) coupled nets that are
transmitting signals.

voltage drop
The decrease in voltage due to Ohm’s law operating on the current and resistance through the
power network. Voltage drop occurs through the package pins, bond wires and pads, and on the
metal layers of the PCB.

voltage-regulator-module (VRM) model

A switching power supply providing power to ICs and other PCB components. A VRM is a type
of DC-to-DC converter.
Depending on the electrical requirements, VRMs can range from large plug-in boards to much
smaller, integrated, components.

—W—
waveform
A graph showing the voltage of a circuit pin at various points in time.

Waveform

BoardSim User Guide, v8.2 1971

February 2012
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

—X—
—Y—
—Z—
See characteristic impedance - Z0.

1972 BoardSim User Guide, v8.2

February 2012
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CUSTOMER’S COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND
CONDITIONS SET FORTH IN THIS AGREEMENT. ANY ADDITIONAL OR DIFFERENT PURCHASE
ORDER TERMS AND CONDITIONS SHALL NOT APPLY.

END-USER LICENSE AGREEMENT (“Agreement”)

This is a legal agreement concerning the use of Software (as defined in Section 2) and hardware (collectively
“Products”) between the company acquiring the Products (“Customer”), and the Mentor Graphics entity that
issued the corresponding quotation or, if no quotation was issued, the applicable local Mentor Graphics entity
(“Mentor Graphics”). Except for license agreements related to the subject matter of this license agreement which
are physically signed by Customer and an authorized representative of Mentor Graphics, this Agreement and the
applicable quotation contain the parties' entire understanding relating to the subject matter and supersede all
prior or contemporaneous agreements. If Customer does not agree to these terms and conditions, promptly return
or, in the case of Software received electronically, certify destruction of Software and all accompanying items
within five days after receipt of Software and receive a full refund of any license fee paid.

1. ORDERS, FEES AND PAYMENT.

1.1. To the extent Customer (or if agreed by Mentor Graphics, Customer’s appointed third party buying agent) places and
Mentor Graphics accepts purchase orders pursuant to this Agreement (“Order(s)”), each Order will constitute a contract
between Customer and Mentor Graphics, which shall be governed solely and exclusively by the terms and conditions of this
Agreement, any applicable addenda and the applicable quotation, whether or not these documents are referenced on the
Order. Any additional or conflicting terms and conditions appearing on an Order will not be effective unless agreed in
writing by an authorized representative of Customer and Mentor Graphics.
1.2. Amounts invoiced will be paid, in the currency specified on the applicable invoice, within 30 days from the date of such
invoice. Any past due invoices will be subject to the imposition of interest charges in the amount of one and one-half
percent per month or the applicable legal rate currently in effect, whichever is lower. Prices do not include freight,
insurance, customs duties, taxes or other similar charges, which Mentor Graphics will state separately in the applicable
invoice(s). Unless timely provided with a valid certificate of exemption or other evidence that items are not taxable, Mentor
Graphics will invoice Customer for all applicable taxes including, but not limited to, VAT, GST, sales tax and service tax.
Customer will make all payments free and clear of, and without reduction for, any withholding or other taxes; any such
taxes imposed on payments by Customer hereunder will be Customer’s sole responsibility. If Customer appoints a third
party to place purchase orders and/or make payments on Customer’s behalf, Customer shall be liable for payment under
Orders placed by such third party in the event of default.
1.3. All Products are delivered FCA factory (Incoterms 2000), freight prepaid and invoiced to Customer, except Software
delivered electronically, which shall be deemed delivered when made available to Customer for download. Mentor
Graphics retains a security interest in all Products delivered under this Agreement, to secure payment of the purchase price
of such Products, and Customer agrees to sign any documents that Mentor Graphics determines to be necessary or
convenient for use in filing or perfecting such security interest. Mentor Graphics’ delivery of Software by electronic means
is subject to Customer’s provision of both a primary and an alternate e-mail address.

2. GRANT OF LICENSE. The software installed, downloaded, or otherwise acquired by Customer under this Agreement,
including any updates, modifications, revisions, copies, documentation and design data (“Software”) are copyrighted, trade
secret and confidential information of Mentor Graphics or its licensors, who maintain exclusive title to all Software and retain
all rights not expressly granted by this Agreement. Mentor Graphics grants to Customer, subject to payment of applicable
license fees, a nontransferable, nonexclusive license to use Software solely: (a) in machine-readable, object-code form (except
as provided in Subsection 5.2); (b) for Customer’s internal business purposes; (c) for the term of the license; and (d) on the
computer hardware and at the site authorized by Mentor Graphics. A site is restricted to a one-half mile (800 meter) radius.
Customer may have Software temporarily used by an employee for telecommuting purposes from locations other than a
Customer office, such as the employee's residence, an airport or hotel, provided that such employee's primary place of
employment is the site where the Software is authorized for use. Mentor Graphics’ standard policies and programs, which vary
depending on Software, license fees paid or services purchased, apply to the following: (a) relocation of Software; (b) use of
Software, which may be limited, for example, to execution of a single session by a single user on the authorized hardware or for
a restricted period of time (such limitations may be technically implemented through the use of authorization codes or similar
devices); and (c) support services provided, including eligibility to receive telephone support, updates, modifications, and
revisions. For the avoidance of doubt, if Customer requests any change or enhancement to Software, whether in the course of
 receiving support or consulting services, evaluating Software, performing beta testing or otherwise, any inventions, product
improvements, modifications or developments made by Mentor Graphics (at Mentor Graphics’ sole discretion) will be the
exclusive property of Mentor Graphics.

3. ESC SOFTWARE. If Customer purchases a license to use development or prototyping tools of Mentor Graphics’ Embedded
Software Channel (“ESC”), Mentor Graphics grants to Customer a nontransferable, nonexclusive license to reproduce and
distribute executable files created using ESC compilers, including the ESC run-time libraries distributed with ESC C and C++
compiler Software that are linked into a composite program as an integral part of Customer’s compiled computer program,
provided that Customer distributes these files only in conjunction with Customer’s compiled computer program. Mentor
Graphics does NOT grant Customer any right to duplicate, incorporate or embed copies of Mentor Graphics’ real-time operating
systems or other embedded software products into Customer’s products or applications without first signing or otherwise
agreeing to a separate agreement with Mentor Graphics for such purpose.

4. BETA CODE.
4.1. Portions or all of certain Software may contain code for experimental testing and evaluation (“Beta Code”), which may not
be used without Mentor Graphics’ explicit authorization. Upon Mentor Graphics’ authorization, Mentor Graphics grants to
Customer a temporary, nontransferable, nonexclusive license for experimental use to test and evaluate the Beta Code
without charge for a limited period of time specified by Mentor Graphics. This grant and Customer’s use of the Beta Code
shall not be construed as marketing or offering to sell a license to the Beta Code, which Mentor Graphics may choose not to
release commercially in any form.
4.2. If Mentor Graphics authorizes Customer to use the Beta Code, Customer agrees to evaluate and test the Beta Code under
normal conditions as directed by Mentor Graphics. Customer will contact Mentor Graphics periodically during Customer’s
use of the Beta Code to discuss any malfunctions or suggested improvements. Upon completion of Customer’s evaluation
and testing, Customer will send to Mentor Graphics a written evaluation of the Beta Code, including its strengths,
weaknesses and recommended improvements.
4.3. Customer agrees to maintain Beta Code in confidence and shall restrict access to the Beta Code, including the methods and
concepts utilized therein, solely to those employees and Customer location(s) authorized by Mentor Graphics to perform
beta testing. Customer agrees that any written evaluations and all inventions, product improvements, modifications or
developments that Mentor Graphics conceived or made during or subsequent to this Agreement, including those based
partly or wholly on Customer’s feedback, will be the exclusive property of Mentor Graphics. Mentor Graphics will have
exclusive rights, title and interest in all such property. The provisions of this Subsection 4.3 shall survive termination of this
Agreement.

5. RESTRICTIONS ON USE.
5.1. Customer may copy Software only as reasonably necessary to support the authorized use. Each copy must include all
notices and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics. All
copies shall remain the property of Mentor Graphics or its licensors. Customer shall maintain a record of the number and
primary location of all copies of Software, including copies merged with other software, and shall make those records
available to Mentor Graphics upon request. Customer shall not make Products available in any form to any person other
than Customer’s employees and on-site contractors, excluding Mentor Graphics competitors, whose job performance
requires access and who are under obligations of confidentiality. Customer shall take appropriate action to protect the
confidentiality of Products and ensure that any person permitted access does not disclose or use it except as permitted by
this Agreement. Customer shall give Mentor Graphics written notice of any unauthorized disclosure or use of the Products
as soon as Customer learns or becomes aware of such unauthorized disclosure or use. Except as otherwise permitted for
purposes of interoperability as specified by applicable and mandatory local law, Customer shall not reverse-assemble,
reverse-compile, reverse-engineer or in any way derive any source code from Software. Log files, data files, rule files and
script files generated by or for the Software (collectively “Files”), including without limitation files containing Standard
Verification Rule Format (“SVRF”) and Tcl Verification Format (“TVF”) which are Mentor Graphics’ proprietary syntaxes
for expressing process rules, constitute or include confidential information of Mentor Graphics. Customer may share Files
with third parties, excluding Mentor Graphics competitors, provided that the confidentiality of such Files is protected by
written agreement at least as well as Customer protects other information of a similar nature or importance, but in any case
with at least reasonable care. Customer may use Files containing SVRF or TVF only with Mentor Graphics products. Under
no circumstances shall Customer use Software or Files or allow their use for the purpose of developing, enhancing or
marketing any product that is in any way competitive with Software, or disclose to any third party the results of, or
information pertaining to, any benchmark.
5.2. If any Software or portions thereof are provided in source code form, Customer will use the source code only to correct
software errors and enhance or modify the Software for the authorized use. Customer shall not disclose or permit disclosure
of source code, in whole or in part, including any of its methods or concepts, to anyone except Customer’s employees or
contractors, excluding Mentor Graphics competitors, with a need to know. Customer shall not copy or compile source code
in any manner except to support this authorized use.
5.3. Customer may not assign this Agreement or the rights and duties under it, or relocate, sublicense or otherwise transfer the
Products, whether by operation of law or otherwise (“Attempted Transfer”), without Mentor Graphics’ prior written
consent and payment of Mentor Graphics’ then-current applicable relocation and/or transfer fees. Any Attempted Transfer
without Mentor Graphics’ prior written consent shall be a material breach of this Agreement and may, at Mentor Graphics’
option, result in the immediate termination of the Agreement and/or the licenses granted under this Agreement. The terms
 of this Agreement, including without limitation the licensing and assignment provisions, shall be binding upon Customer’s
permitted successors in interest and assigns.
5.4. The provisions of this Section 5 shall survive the termination of this Agreement.

6. SUPPORT SERVICES. To the extent Customer purchases support services, Mentor Graphics will provide Customer updates
and technical support for the Products, at the Customer site(s) for which support is purchased, in accordance with Mentor
Graphics’ then current End-User Support Terms located at http://supportnet.mentor.com/about/legal/.

7. AUTOMATIC CHECK FOR UPDATES; PRIVACY. Technological measures in Software may communicate with servers
of Mentor Graphics or its contractors for the purpose of checking for and notifying the user of updates and to ensure that the
Software in use is licensed in compliance with this Agreement. Mentor Graphics will not collect any personally identifiable data
in this process and will not disclose any data collected to any third party without the prior written consent of Customer, except to
Mentor Graphics’ outside attorneys or as may be required by a court of competent jurisdiction.

8. LIMITED WARRANTY.
8.1. Mentor Graphics warrants that during the warranty period its standard, generally supported Products, when properly
installed, will substantially conform to the functional specifications set forth in the applicable user manual. Mentor
Graphics does not warrant that Products will meet Customer’s requirements or that operation of Products will be
uninterrupted or error free. The warranty period is 90 days starting on the 15th day after delivery or upon installation,
whichever first occurs. Customer must notify Mentor Graphics in writing of any nonconformity within the warranty period.
For the avoidance of doubt, this warranty applies only to the initial shipment of Software under an Order and does not
renew or reset, for example, with the delivery of (a) Software updates or (b) authorization codes or alternate Software under
a transaction involving Software re-mix. This warranty shall not be valid if Products have been subject to misuse,
unauthorized modification or improper installation. MENTOR GRAPHICS’ ENTIRE LIABILITY AND CUSTOMER’S
EXCLUSIVE REMEDY SHALL BE, AT MENTOR GRAPHICS’ OPTION, EITHER (A) REFUND OF THE PRICE
PAID UPON RETURN OF THE PRODUCTS TO MENTOR GRAPHICS OR (B) MODIFICATION OR
REPLACEMENT OF THE PRODUCTS THAT DO NOT MEET THIS LIMITED WARRANTY, PROVIDED
CUSTOMER HAS OTHERWISE COMPLIED WITH THIS AGREEMENT. MENTOR GRAPHICS MAKES NO
WARRANTIES WITH RESPECT TO: (A) SERVICES; (B) PRODUCTS PROVIDED AT NO CHARGE; OR (C) BETA
CODE; ALL OF WHICH ARE PROVIDED “AS IS.”
8.2. THE WARRANTIES SET FORTH IN THIS SECTION 8 ARE EXCLUSIVE. NEITHER MENTOR GRAPHICS NOR
ITS LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS, IMPLIED OR STATUTORY, WITH RESPECT TO
PRODUCTS PROVIDED UNDER THIS AGREEMENT. MENTOR GRAPHICS AND ITS LICENSORS
SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY.

9. LIMITATION OF LIABILITY. EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE

VOID OR INEFFECTIVE UNDER APPLICABLE LAW, IN NO EVENT SHALL MENTOR GRAPHICS OR ITS
LICENSORS BE LIABLE FOR INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES (INCLUDING
LOST PROFITS OR SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY OTHER LEGAL THEORY, EVEN
IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN
NO EVENT SHALL MENTOR GRAPHICS’ OR ITS LICENSORS’ LIABILITY UNDER THIS AGREEMENT EXCEED
THE AMOUNT RECEIVED FROM CUSTOMER FOR THE HARDWARE, SOFTWARE LICENSE OR SERVICE GIVING
RISE TO THE CLAIM. IN THE CASE WHERE NO AMOUNT WAS PAID, MENTOR GRAPHICS AND ITS LICENSORS
SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER. THE PROVISIONS OF THIS SECTION 9 SHALL
SURVIVE THE TERMINATION OF THIS AGREEMENT.

10. HAZARDOUS APPLICATIONS. CUSTOMER ACKNOWLEDGES IT IS SOLELY RESPONSIBLE FOR TESTING ITS
PRODUCTS USED IN APPLICATIONS WHERE THE FAILURE OR INACCURACY OF ITS PRODUCTS MIGHT
RESULT IN DEATH OR PERSONAL INJURY (“HAZARDOUS APPLICATIONS”). NEITHER MENTOR GRAPHICS
NOR ITS LICENSORS SHALL BE LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNECTION WITH
THE USE OF MENTOR GRAPHICS PRODUCTS IN OR FOR HAZARDOUS APPLICATIONS. THE PROVISIONS OF
THIS SECTION 10 SHALL SURVIVE THE TERMINATION OF THIS AGREEMENT.

11. INDEMNIFICATION. CUSTOMER AGREES TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND
ITS LICENSORS FROM ANY CLAIMS, LOSS, COST, DAMAGE, EXPENSE OR LIABILITY, INCLUDING
ATTORNEYS’ FEES, ARISING OUT OF OR IN CONNECTION WITH THE USE OF PRODUCTS AS DESCRIBED IN
SECTION 10. THE PROVISIONS OF THIS SECTION 11 SHALL SURVIVE THE TERMINATION OF THIS
AGREEMENT.

12. INFRINGEMENT.
12.1. Mentor Graphics will defend or settle, at its option and expense, any action brought against Customer in the United States,
Canada, Japan, or member state of the European Union which alleges that any standard, generally supported Product
acquired by Customer hereunder infringes a patent or copyright or misappropriates a trade secret in such jurisdiction.
Mentor Graphics will pay costs and damages finally awarded against Customer that are attributable to the action. Customer
understands and agrees that as conditions to Mentor Graphics’ obligations under this section Customer must: (a) notify
Mentor Graphics promptly in writing of the action; (b) provide Mentor Graphics all reasonable information and assistance
 to settle or defend the action; and (c) grant Mentor Graphics sole authority and control of the defense or settlement of the
action.
12.2. If a claim is made under Subsection 12.1 Mentor Graphics may, at its option and expense, (a) replace or modify the Product
so that it becomes noninfringing; (b) procure for Customer the right to continue using the Product; or (c) require the return
of the Product and refund to Customer any purchase price or license fee paid, less a reasonable allowance for use.
12.3. Mentor Graphics has no liability to Customer if the action is based upon: (a) the combination of Software or hardware with
any product not furnished by Mentor Graphics; (b) the modification of the Product other than by Mentor Graphics; (c) the
use of other than a current unaltered release of Software; (d) the use of the Product as part of an infringing process; (e) a
product that Customer makes, uses, or sells; (f) any Beta Code or Product provided at no charge; (g) any software provided
by Mentor Graphics’ licensors who do not provide such indemnification to Mentor Graphics’ customers; or
(h) infringement by Customer that is deemed willful. In the case of (h), Customer shall reimburse Mentor Graphics for its
reasonable attorney fees and other costs related to the action.
12.4. THIS SECTION 12 IS SUBJECT TO SECTION 9 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTOR
GRAPHICS AND ITS LICENSORS FOR DEFENSE, SETTLEMENT AND DAMAGES, AND CUSTOMER’S SOLE
AND EXCLUSIVE REMEDY, WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT
OR TRADE SECRET MISAPPROPRIATION BY ANY PRODUCT PROVIDED UNDER THIS AGREEMENT.

13. TERMINATION AND EFFECT OF TERMINATION. If a Software license was provided for limited term use, such license
will automatically terminate at the end of the authorized term.
13.1. Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement immediately upon written
notice if Customer: (a) exceeds the scope of the license or otherwise fails to comply with the licensing or confidentiality
provisions of this Agreement, or (b) becomes insolvent, files a bankruptcy petition, institutes proceedings for liquidation or
winding up or enters into an agreement to assign its assets for the benefit of creditors. For any other material breach of any
provision of this Agreement, Mentor Graphics may terminate this Agreement and/or any license granted under this
Agreement upon 30 days written notice if Customer fails to cure the breach within the 30 day notice period. Termination of
this Agreement or any license granted hereunder will not affect Customer’s obligation to pay for Products shipped or
licenses granted prior to the termination, which amounts shall be payable immediately upon the date of termination.
13.2. Upon termination of this Agreement, the rights and obligations of the parties shall cease except as expressly set forth in this
Agreement. Upon termination, Customer shall ensure that all use of the affected Products ceases, and shall return hardware
and either return to Mentor Graphics or destroy Software in Customer’s possession, including all copies and
documentation, and certify in writing to Mentor Graphics within ten business days of the termination date that Customer no
longer possesses any of the affected Products or copies of Software in any form.

14. EXPORT. The Products provided hereunder are subject to regulation by local laws and United States government agencies,
which prohibit export or diversion of certain products and information about the products to certain countries and certain
persons. Customer agrees that it will not export Products in any manner without first obtaining all necessary approval from
appropriate local and United States government agencies.

15. U.S. GOVERNMENT LICENSE RIGHTS. Software was developed entirely at private expense. All Software is commercial
computer software within the meaning of the applicable acquisition regulations. Accordingly, pursuant to US FAR 48 CFR
12.212 and DFAR 48 CFR 227.7202, use, duplication and disclosure of the Software by or for the U.S. Government or a U.S.
Government subcontractor is subject solely to the terms and conditions set forth in this Agreement, except for provisions which
are contrary to applicable mandatory federal laws.

16. THIRD PARTY BENEFICIARY. Mentor Graphics Corporation, Mentor Graphics (Ireland) Limited, Microsoft Corporation
and other licensors may be third party beneficiaries of this Agreement with the right to enforce the obligations set forth herein.

17. REVIEW OF LICENSE USAGE. Customer will monitor the access to and use of Software. With prior written notice and
during Customer’s normal business hours, Mentor Graphics may engage an internationally recognized accounting firm to
review Customer’s software monitoring system and records deemed relevant by the internationally recognized accounting firm
to confirm Customer’s compliance with the terms of this Agreement or U.S. or other local export laws. Such review may include
FLEXlm or FLEXnet (or successor product) report log files that Customer shall capture and provide at Mentor Graphics’
request. Customer shall make records available in electronic format and shall fully cooperate with data gathering to support the
license review. Mentor Graphics shall bear the expense of any such review unless a material non-compliance is revealed. Mentor
Graphics shall treat as confidential information all information gained as a result of any request or review and shall only use or
disclose such information as required by law or to enforce its rights under this Agreement. The provisions of this Section 17
shall survive the termination of this Agreement.

18. CONTROLLING LAW, JURISDICTION AND DISPUTE RESOLUTION. The owners of certain Mentor Graphics
intellectual property licensed under this Agreement are located in Ireland and the United States. To promote consistency around
the world, disputes shall be resolved as follows: excluding conflict of laws rules, this Agreement shall be governed by and
construed under the laws of the State of Oregon, USA, if Customer is located in North or South America, and the laws of Ireland
if Customer is located outside of North or South America. All disputes arising out of or in relation to this Agreement shall be
submitted to the exclusive jurisdiction of the courts of Portland, Oregon when the laws of Oregon apply, or Dublin, Ireland when
the laws of Ireland apply. Notwithstanding the foregoing, all disputes in Asia arising out of or in relation to this Agreement shall
be resolved by arbitration in Singapore before a single arbitrator to be appointed by the chairman of the Singapore International
 Arbitration Centre (“SIAC”) to be conducted in the English language, in accordance with the Arbitration Rules of the SIAC in
effect at the time of the dispute, which rules are deemed to be incorporated by reference in this section. This section shall not
restrict Mentor Graphics’ right to bring an action against Customer in the jurisdiction where Customer’s place of business is
located. The United Nations Convention on Contracts for the International Sale of Goods does not apply to this Agreement.

19. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid,
unenforceable or illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in full
force and effect.

20. MISCELLANEOUS. This Agreement contains the parties’ entire understanding relating to its subject matter and supersedes all
prior or contemporaneous agreements, including but not limited to any purchase order terms and conditions. Some Software
may contain code distributed under a third party license agreement that may provide additional rights to Customer. Please see
the applicable Software documentation for details. This Agreement may only be modified in writing by authorized
representatives of the parties. Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent
consent, waiver or excuse.

Rev. 100615, Part No. 246066