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Crosslinkplus Family: Preliminary Data Sheet

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CrossLinkPlus Family

Preliminary Data Sheet

FPGA-DS-02054-0.92

March 2021
CrossLinkPlus Family
Preliminary Data Sheet

Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely
with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been
subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the
same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s
product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this
document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any
products at any time without notice.

© 2019-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

2 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

Contents
Acronyms in This Document ................................................................................................................................................. 6
1. General Description ...................................................................................................................................................... 7
1.1. Features .............................................................................................................................................................. 7
2. Product Feature Summary ............................................................................................................................................ 8
3. Architecture Overview .................................................................................................................................................. 9
3.1. MIPI D-PHY Blocks ............................................................................................................................................. 10
3.2. Programmable I/O Banks .................................................................................................................................. 14
3.3. sysI/O Buffers .................................................................................................................................................... 16
3.3.1. Programmable PULLMODE Settings ............................................................................................................. 16
3.3.2. Output Drive Strength .................................................................................................................................. 16
3.3.3. On-Chip Termination .................................................................................................................................... 16
3.4. Programmable FPGA Fabric .............................................................................................................................. 17
3.4.1. PFU Blocks..................................................................................................................................................... 17
3.4.2. Slice ............................................................................................................................................................... 18
3.5. Clocking Structure ............................................................................................................................................. 21
3.5.1. sysCLK PLL ..................................................................................................................................................... 21
3.5.2. Primary Clocks .............................................................................................................................................. 22
3.5.3. Edge Clocks ................................................................................................................................................... 22
3.5.4. Dynamic Clock Enables ................................................................................................................................. 23
3.5.5. Internal Oscillator (OSCI) .............................................................................................................................. 23
3.6. Embedded Block RAM Overview....................................................................................................................... 24
3.7. Power Management Unit .................................................................................................................................. 25
3.7.1. PMU State Machine ...................................................................................................................................... 25
3.8. User I2C IP .......................................................................................................................................................... 26
3.9. Programming and Configuration ....................................................................................................................... 26
4. DC and Switching Characteristics ............................................................................................................................... 28
4.1. Absolute Maximum Ratings .............................................................................................................................. 28
4.2. Recommended Operating Conditions ............................................................................................................... 28
4.3. Power Supply Ramp Rates ................................................................................................................................ 29
4.4. Power-On-Reset Voltage Levels ........................................................................................................................ 29
4.5. Electro-Static Discharge (ESD) Performance ..................................................................................................... 29
4.6. DC Electrical Characteristics .............................................................................................................................. 30
4.7. CrossLinkPlus Supply Current ............................................................................................................................ 30
4.8. Power Management Unit (PMU) Timing ........................................................................................................... 31
4.9. sysI/O Recommended Operating Conditions .................................................................................................... 32
4.10. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 32
4.11. sysI/O Differential Electrical Characteristics ..................................................................................................... 33
4.11.1. LVDS/subLVDS/SLVS200 ........................................................................................................................... 33
4.11.2. Hardened MIPI D-PHY I/O ........................................................................................................................ 34
4.12. CrossLinkPlus Maximum General Purpose I/O Buffer Speed ............................................................................ 35
4.13. CrossLinkPlus External Switching Characteristics.............................................................................................. 36
4.14. sysCLOCK PLL Timing ......................................................................................................................................... 42
4.15. Hardened MIPI D-PHY Performance ................................................................................................................. 42
4.16. Internal Oscillators (HFOSC, LFOSC) .................................................................................................................. 43
4.17. User I2C .............................................................................................................................................................. 43
4.18. CrossLinkPlus sysCONFIG Port Timing Specifications ........................................................................................ 44
4.19. SRAM Configuration Time from internal Flash.................................................................................................. 44
4.20. Flash Programming/Erase Specifications .......................................................................................................... 44
4.21. Switching Test Conditions ................................................................................................................................. 45
5. Signal Descriptions...................................................................................................................................................... 46
5.1. Dual Function Pin Descriptions ......................................................................................................................... 46
5.2. Dedicated Function Pin Descriptions ................................................................................................................ 47

FPGA-DS-02054-0.92 3
CrossLinkPlus Family
Preliminary Data Sheet

5.3. Pin Information Summary .................................................................................................................................47

6. CrossLinkPlus Part Number Description .....................................................................................................................48
6.1. Ordering Part Numbers .....................................................................................................................................48
References ..........................................................................................................................................................................49
Technical Support ...............................................................................................................................................................50
Revision History ..................................................................................................................................................................51

Figures
Figure 3.1. CrossLinkPlus Device Block Diagram ...................................................................................................................9
Figure 3.2. CrossLinkPlus sysI/O Banking ............................................................................................................................10
Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module .....................................................................................11
Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module ..................................................................................12
Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module.......................................................................................13
Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module ....................................................................................14
Figure 3.7. CrossLinkPlus Device Simplified Block Diagram (Top Level) .............................................................................17
Figure 3.8. CrossLinkPlus PFU Diagram ...............................................................................................................................18
Figure 3.9. Slice Diagram ....................................................................................................................................................19
Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8 ...................................................................................20
Figure 3.11. CrossLinkPlus PLL Block Diagram ....................................................................................................................21
Figure 3.12. CrossLinkPlus Clocking Structure ....................................................................................................................22
Figure 3.13. CrossLinkPlus Edge Clock Sources per Bank ...................................................................................................23
Figure 3.14. CrossLinkPlus OSCI Component Symbol .........................................................................................................23
Figure 3.15. CrossLinkPlus MIPI D-PHY Block......................................................................................................................25
Figure 3.16. CrossLinkPlus PMU State Machine .................................................................................................................26
Figure 4.1. Receiver RX.CLK.Centered Waveforms .............................................................................................................40
Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms ......................................................................................................40
Figure 4.3. Transmit TX.CLK.Centered Output Waveforms ................................................................................................40
Figure 4.4. Transmit TX.CLK.Aligned Waveforms ................................................................................................................41
Figure 4.5. DDRX71, DDRX141 Video Timing Waveforms...................................................................................................41
Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................45

4 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

Tables
Table 2.1. CrossLinkPlus Feature Summary .......................................................................................................................... 8
Table 3.1. CrossLinkPlus Output Support per Bank Basis ................................................................................................... 15
Table 3.2. CrossLinkPlus Input Support per Bank Basis ...................................................................................................... 15
Table 3.3. Drive Strength Values ........................................................................................................................................ 16
Table 3.4. Slice Signal Descriptions ..................................................................................................................................... 20
Table 3.5. CrossLinkPlus PLL Port Definition ....................................................................................................................... 21
Table 3.6. OSCI Component Port Definition ....................................................................................................................... 23
Table 3.7. OSCI Component Attribute Definition ............................................................................................................... 23
Table 3.8. sysMEM Block Configurations ............................................................................................................................ 24
Table 3.9. CrossLinkPlus sysCONFIG Pins ............................................................................................................................ 27
Table 4.1. Absolute Maximum Ratings 1, 2, 3 ........................................................................................................................ 28
Table 4.2. Recommended Operating Conditions 1, 2 ........................................................................................................... 28
Table 4.3. Power Supply Ramp Rates* ............................................................................................................................... 29
Table 4.4. Power-On-Reset Voltage Levels 1, 3, 4.................................................................................................................. 29
Table 4.5. DC Electrical Characteristics ............................................................................................................................... 30
Table 4.6. CrossLinkPlus Supply Current ............................................................................................................................. 30
Table 4.7. PMU Timing*...................................................................................................................................................... 31
Table 4.8. sysI/O Recommended Operating Conditions1 ................................................................................................... 32
Table 4.9. sysI/O Single-Ended DC Electrical Characteristics1............................................................................................. 32
Table 4.10. LVDS/subLVDS1/SLVS200 1, 2 ............................................................................................................................ 33
Table 4.11. MIPI D-PHY ....................................................................................................................................................... 34
Table 4.12. CrossLinkPlus Maximum I/O Buffer Speed ...................................................................................................... 35
Table 4.13. CrossLinkPlus External Switching Characteristics 3,4 ........................................................................................ 36
Table 4.14. sysCLOCK PLL Timing ........................................................................................................................................ 42
Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s) ............ 42
Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s) ............ 42
Table 4.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s) ................ 43
Table 4.18. Internal Oscillators ........................................................................................................................................... 43
Table 4.19. User I2C 1 .......................................................................................................................................................... 43
Table 4.20. CrossLinkPlus sysCONFIG Port Timing Specifications....................................................................................... 44
Table 4.21. SRAM Configuration Time from internal Flash ................................................................................................ 44
Table 4.22. Flash Programming/Erase Specifications ......................................................................................................... 44
Table 4.23. Test Fixture Required Components, Non-Terminated Interfaces* .................................................................. 45
Table 5.1. Dual Function Pin Descriptions .......................................................................................................................... 46
Table 5.2. Dedicated Function Pin Descriptions ................................................................................................................. 47
Table 5.3. Pin Information Summary .................................................................................................................................. 47

FPGA-DS-02054-0.92 5
CrossLinkPlus Family
Preliminary Data Sheet

Acronyms in This Document

A list of acronyms used in this document.
Acronym Definition
AR Augmented Reality
ASIC Application-Specific Integrated Circuit
CMOS Complementary Metal Oxide Semiconductor
CSI Camera Serial Interface
DBI Display Bus Interface
DDR Double Data Rate
DPI Display Pixel Interface
DSI Display Serial Interface
EBR Embedded Block RAM
ECLK Edge Clock
ESD Electro-Static Discharge
FPGA Field-Programmable Gate Array
FPD Flat Panel Display
GPIO General-Purpose Input/Output
HFOSC High Frequency Oscillator
HiSPi High-Speed Pixel Interface
HMI Human Machine Interface
I2C Inter-Integrated Circuit
ISM Industrial, Scientific, Medical
LFOSC Low Frequency Oscillator
LUT Look Up Table
LVCMOS Low-Voltage Complementary Metal Oxide Semiconductor
LVDS Low-Voltage Differential Signaling
LVTTL Low Voltage Transistor-Transistor Logic
MIPI Mobile Industry Processor Interface
OpenLDI Open LVDS Display Interface
OTP One Time Programmable
PCLK Primary Clock
PFU Programmable Functional Unit
PLL Phase Locked Loops
PMU Power Management Unit
RAM Random Access Memory
Rx Receive
SDR Single Data Rate
SLVS Scalable Low-Voltage Signaling
SPI Serial Peripheral Interface
SRAM Static Random Access Memory
TransFR Transparent Field Reconfiguration
Tx Transmit
UHD Ultra-High-Definition, 3840 x 2160
VR Virtual Reality

6 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

 Programmable architecture
1. General Description  5936 LUTs
CrossLinkPlus™ from Lattice Semiconductor is a  180 kb block RAM
programmable video bridging device that supports a  47 kb distributed RAM
variety of protocols and interfaces for mobile image
 Two hardened 4-lane MIPI D-PHY interfaces
sensors and displays. The device is based on Lattice
mobile FPGA 40-nm technology with embedded flash.  Transmit and receive
It is a low power FPGA with small footprint and instant  6 Gb/s per D-PHY interface
boot up time (< 10 ms).  Programmable source synchronous I/O
CrossLinkPlus supports video interfaces including MIPI ®  MIPI D-PHY Rx, LVDS Rx, LVDS Tx, subLVDS Rx,
DPI, MIPI DBI, CMOS camera, and display interfaces, SLVS200 Rx, HiSPi Rx
OpenLDI, FPD-Link, FLATLINK, MIPI D-PHY, MIPI CSI-2,  Up to 1200 Mb/s per I/O
MIPI DSI, SLVS200, subLVDS, HiSPi, and more.  Four high-speed clock inputs
Lattice Semiconductor provides many pre-engineered  Programmable CMOS I/O
Intellectual Property (IP) modules for CrossLinkPlus. By  LVTTL and LVCMOS
using these configurable soft core IPs as standardized 3.3 V, 2.5 V, 1.8 V and 1.2 V (outputs)
blocks, you are free to concentrate on the unique  LVCMOS differential outputs
aspects of your design, increasing the productivity.  Flexible device configuration
The Lattice Diamond® design software allows large  On-chip reconfigurable Flash
complex designs to be efficiently implemented using  Master SPI boot from external flash
CrossLinkPlus. Synthesis library support for
Dual image booting supported
CrossLinkPlus devices is available for popular logic
synthesis tools. The Diamond tools use the synthesis  I2C programming
tool output along with the constraints from its floor  SPI programming
planning tools to place and route the design in the  TransFR™ I/O for simple field updates
CrossLinkPlus device. The tools extract the timing from  Enhanced system level support
the routing and back-annotate it into the design for  Reveal logic analyzer
timing verification.  TraceID for system tracking
Interfaces on CrossLinkPlus provide a variety of  On-chip hardened I2C block
bridging solutions for smart phone, tablets, wearables,  Applications examples
VR, AR, Drone, Smart Home, HMI as well as adjacent  Dual MIPI CSI-2 to Single MIPI CSI-2
ISM markets. The device is capable of supporting Aggregation
high-resolution, high-bandwidth content for mobile
 Quad MIPI CSI-2 to Single MIPI CSI-2
cameras and displays at UHD and beyond.
Aggregation
 Single MIPI DSI to Single MIPI DSI Repeater
1.1. Features  Single MIPI CSI-2 to Single MIPI CSI-2 Repeater
 Ultra-low power  Single MIPI DSI to Dual MIPI DSI Splitter
 Sleep mode support  Single MIPI CSI-2 to Dual MIPI CSI-2 Splitter
 Normal Operation – from 5 mW to 150 mW  MIPI DSI to OpenLDI/FPD-Link/LVDS Translator
 Ultra small footprint packages  OpenLDI/FPD-Link/LVDS to MIPI DSI Translator
 64-ball ucfBGA (12 mm2)  MIPI DSI/CSI-2 to CMOS Translator
 80-ball ckfBGA (49 mm2)  CMOS to MIPI DSI/CSI-2 Translator
 subLVDS to MIPI CSI-2 Translator

FPGA-DS-02054-0.92 7
CrossLinkPlus Family
Preliminary Data Sheet

2. Product Feature Summary

Table 2.1 lists CrossLinkPlus device information and packages.
Table 2.1. CrossLinkPlus Feature Summary
Device CrossLinkPlus
LUTs 5936
sysMEM Blocks (9 kb) 20
Embedded Memory (kb) 180
Distributed RAM Bits (kb) 47
General Purpose PLL 1
Flash (Mb) 2
2
Embedded I C 2
Oscillator (10 kHz) 1
Oscillator (48 MHz) 1
Hardened MIPI D-PHY 2*
Packages (Footprint, Pitch) I/O
64 ucfBGA (3.5 × 3.5 mm2, 0.4 mm) 29
80 ckfBGA (7.0 x 7.0 mm2, 0.65 mm) 37
*Note: Additional D-PHY Rx interfaces are available using programmable I/O.

8 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

3. Architecture Overview
CrossLinkPlus is designed as a flexible, chip-to-chip bridging solution which supports a wide variety of applications. The
device provides three key building blocks for these bridging applications:
 Two embedded Hard D-PHY blocks
 Two banks of flexible programmable I/O supporting a variety of standards including D-PHY Rx, subLVDS, SLVS200,
LVDS, and CMOS
 A programmable logic core providing the LUTs, memory, and system resources to implement a wide range of
bridging operations
In addition to these blocks, CrossLinkPlus also provides key system resources including a Power Management Unit,
flexible configuration interface, additional CMOS GPIO, user I2C blocks, and internal Flash.
The block diagram for the device is shown in Figure 3.1.

Programmable I/O
MIPI D-PHY
Rx: D-PHY / subLVDS /
LVDS / SLVS200 / CMOS 6 Gb/s
Programmable FPGA Fabric Rx and Tx
Tx: LVDS / CMOS 5,936 LUTs
180 kbits block RAM 4 Data Lanes
Up to 1.2 Gb/s per Lane 47 kbits distributed RAM 1 Clock Lane
10 I/O / 5 Pairs

Enough FPGA resources to handle video:

Muxing
Merging
Programmable I/O Demuxing
Arbitration MIPI D-PHY
Rx: D-PHY / subLVDS / Splitting
LVDS / SLVS200 / CMOS Data Conversion 6 Gb/s
Custom Protocol Design Rx and Tx
Tx: LVDS / CMOS
4 Data Lanes
Up to 1.2 Gb/s per Lane 1 Clock Lane
12 I/O / 6 Pairs

Power Management Unit GPIOs FLASH I2C / SPI*

Figure 3.1. CrossLinkPlus Device Block Diagram

*Note: I2C and SPI configuration modes are supported. User mode hardened I2C is also supported.

FPGA-DS-02054-0.92 9
CrossLinkPlus Family
Preliminary Data Sheet

3.1. MIPI D-PHY Blocks

The top side of the device, as shown in Figure 3.2, includes two hard MIPI D-PHY quads. The D-PHY can be configured
to support both camera interface (CSI-2) and display interface (DSI) applications. Below is a summary of the features
supported by the hard D-PHY quads.
 Transmit and receive compliant to MIPI Alliance Specification for D-PHY Revision 1.1
 High-Speed (HS) and Low-Power (LP) mode support (including built-in contention detect)
 Supports continuous clock mode or low power clock mode
 Up to 6 Gb/s per quad (1500 Mb/s data rate per lane)
 Dedicated PLL for Transmit Frequency Synthesis
 Dedicated Serializer and De-Serializer blocks for fabric interfacing.
Lattice Semiconductor provides a set of pre-engineered IP modules which include the full implementation and control
of the hard D-PHY blocks to enable designers to focus on unique aspects of their design.
Figure 3.3 to Figure 3.6 show the signals connected to the fabric and the automatic settings when the hardened D-PHY
is configured for the DSI/CSI-2 transmit and receive modes. Refer to CrossLinkPlus High-Speed I/O Interface
(FPGA-TN-02102) for more information on the Hard D-PHY quads.

Figure 3.2. CrossLinkPlus sysI/O Banking

10 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

MIPIDPHYA
Bidirectional clk and data
CLKP
CLKN
DP[3:1]
DN[3:1]
DP0
DN0

RX - Data LP ports D0_RXLPP

D0_RXLPN

D0_TXHSEN TX – Data HS ports

TXHSBYTECLK
Dy_HSTXDATA[15:0]

D0_TXLPEN TX – Data LP ports

D0_TXLPP
D0_TXLPN
Dx_TXLPP
Dx_TXLPN

TX – CLK HS ports
CLK_TXHSEN
CLK_TXHSGATE

TX – CLK LP ports
CLK_TXLPP
CLK_TXLPN

Control Ports
USRSTDBY
PDPLL

PLL Ports
REFCLK LOCK
* x = 1, 2, 3
y = 0, 1, 2, 3

Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module

FPGA-DS-02054-0.92 11
CrossLinkPlus Family
Preliminary Data Sheet

MIPIDPHYA
Bidirectional clk and data
CLKP
CLKN
DP[3:1]
DN[3:1]
DP0
DN0

D0_TXHSEN TX – Data HS ports

TXHSBYTECLK
Dy_HSTXDATA[15:0]

D0_TXLPEN TX – Data LP ports

TX – CLK HS ports
CLK_TXHSEN
CLK_TXHSGATE

TX – CLK LP ports
CLK_TXLPP
CLK_TXLPN

CLK_TXLPEN
Control Ports
USRSTDBY
PDPLL

PLL Ports
REFCLK LOCK

* x = 1, 2, 3
y = 0, 1, 2, 3

Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module

12 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

MIPIDPHYA
CLKP Bidirectional clk and data
CLKN
DPx
DNx
DP0
DN0

RX - Data HS ports
DO_RXHSEN Dy_HSRXDATA[15:0]
RXHSBYTECLK

RX - Data LP ports D0_RXLPP

DO_RXLPEN D0_RXLPN
D0_CD

RX - CLK HS ports
CLKRXHSEN CLKHSBYTE
RX - CLK LP ports
CLK_RXLPP
CLKRXLPEN CLK_RXLPN
CLK_CD
TX – Data LP ports

D0_TXLPP
D0_TXLPN

Control Ports
USRSTDBY

* x = 1, 2, 3
y = 0, 1, 2, 3

Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module

FPGA-DS-02054-0.92 13
CrossLinkPlus Family
Preliminary Data Sheet

MIPIDPHYA
Bidirectional clk and data
CLKP
CLKN
DPx
DNx
DP0
DN0
RX - Data HS ports
Dy_HSRXDATA[15:0]
RXHSBYTECLK

RX - Data LP ports D0_RXLPP

D0_RXLPN
D0_CD

RX - CLK HS ports
CLKHSBYTE
RX - CLK LP ports CLK_RXLPP
CLK_RXLPN
CLK_CD
Control Ports
USRSTDBY
* x = 1, 2, 3
y = 0, 1, 2, 3

Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module

3.2. Programmable I/O Banks

CrossLinkPlus devices provide programmable I/O which can be used to interface to a variety of external standards on
Banks 1 and Bank 2. CrossLinkPlus devices also provide dedicated CMOS GPIOs on Bank 0. Bank 0 GPIOs only support
Single Data Rate (SDR) interfaces, while Bank 1 and Bank 2 support both SDR and Double Data Rate (DDR) interfaces.
The GPIOs on Bank 0 do not include differential signaling capabilities. The location of the three Banks and their
associated supplies are shown in Figure 3.2.
Bank 0 features:
 Support for the following single ended standards
 LVCMOS33
 LVCMOS25
 LVCMOS18
 LVTTL33

14 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

 Tri-state control for output

 Input/output register blocks
 Open-drain option and programmable input hysteresis
 Internal pull-up resistors with configurable values of 3.3 kΩ, 6.8 kΩ, and 10 kΩ
Bank 1 and Bank 2 features:
 Built-in support for the following differential standards
 LVDS – Tx and Rx
 SLVS200 – Rx
 subLVDS – Rx
 MIPI – Rx (both LP and HS receive on a single differential pair)
 Support for the following single ended standards
 LVCMOS33
 LVCMOS25
 LVCMOS18
 LVCMOS12 (Outputs Only)
 LVTTL33
 Independent voltage levels per bank based on VCCIO supply
 Input/output gearboxes per LVDS pair supporting several ratios for video interface applications
 DDRX1, DDRX2, DDRX4, DDRX8 and DDRX71, DDRX141
 Programmable delay cells to support edge-aligned and center-aligned interfaces
 Programmable differential termination (~ 100 Ω) with dynamic enable control
 Tri-state control for output
 Input/output register blocks
 Single-ended standards support open-drain and programmable input hysteresis
 Optional weak pull-up resistors
Table 3.1. CrossLinkPlus Output Support per Bank Basis
OUTPUT BANK 0 BANK 1 BANK 2
LVCMOS12 —  
LVCMOS18   
LVCMOS25   
LVCMOS33   
LVTTL33   
LVDS25 —  

Table 3.2. CrossLinkPlus Input Support per Bank Basis

INPUT BANK 0 BANK 1 BANK 2
LVCMOS12 — — —
LVCMOS18   
LVCMOS25   
LVCMOS33   
LVTTL33   
LVDS25 —  
MIPI D-PHY —  
SLVS200 —  
subLVDS —  

FPGA-DS-02054-0.92 15
CrossLinkPlus Family
Preliminary Data Sheet

3.3. sysI/O Buffers

The CrossLinkPlus sysI/O buffers are distributed across three banks located at the bottom of the CrossLinkPlus device
as shown in Figure 3.2. The sysI/O buffers support a wide variety of standards to interface to a range of systems
including LVDS, subLVDS, LVCMOS, LVTTL, SLVS200, and MIPI. CrossLinkPlus supports single-ended buffers on all three
banks. Differential I/O is supported on Bank 1 and Bank 2.

3.3.1. Programmable PULLMODE Settings

The CrossLinkPlus sysI/O buffers offer multiple programmable value pull-up resistors on the three banks. The pull-up
values are programmable on a per-pin basis. The default state of the I/O pins prior to configuration is tri-stated with a
weak pull-up to VCCIOx. The I/O pins convert to the software user-defined settings after the configuration bitstream has
been successfully downloaded to the device. Each sysI/O buffer can be programmed with a 100 kΩ (weak pull-up),
3.3 kΩ, 6.8 kΩ, 10 kΩ, or no pull-up. These pull-up options allow an I2C interface to be placed on the majority of the
pins on the device. These options are not exclusively for I2C protocol and may be used for other functions.

3.3.2. Output Drive Strength

Each CrossLinkPlus output can have its own individual drive strength setting, but is predefined based on the VCCIOx
setting. Table 3.3 lists the drive settings for the corresponding I/O type.
Table 3.3. Drive Strength Values
VCCIOx (V) I/O Type Drive Strength (mA)
3.3 LVTTL33 8
3.3 LVCMOS33 8
2.5 LVCMOS25 6
1.8 LVCMOS18 4
1.2 LVCMOS12 2

3.3.3. On-Chip Termination

Bank 1 and Bank 2 of CrossLinkPlus support LVDS, SLVS200 subLVDS and MIPI D-PHY inputs. These two banks support
on-chip 100 Ω input differential termination between LVDS, SLVS200, and subLVDS pairs. For MIPI D-PHY inputs, the
on-chip 100 Ω termination is dynamically enabled based on the High Speed Select (HSSEL) signal.
Refer to the CrossLinkPlus High-Speed I/O Interface (FPGA-TN-02102) and CrossLinkPlus sysI/O Usage Guide
(FPGA-TN-02108) for details.

16 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

3.4. Programmable FPGA Fabric

CrossLinkPlus is built around a programmable logic fabric consisting of 5936 four input lookup tables (LUT4) arranged
alongside dedicated registers in Programmable Functional Units (PFU). These PFU blocks are the building blocks for
logic, arithmetic, RAM, and ROM functions. The PFU blocks are connected via a programmable routing network. The
Lattice Diamond design software configures the PFU blocks and the programmable routing for each unique design.
Interspersed between rows of PFU are rows of sysMEM™ Embedded Block RAM (EBR), with programmable I/O banks,
embedded I2C and embedded MIPI D-PHY arranged on the top and bottom of the device as shown in Figure 3.7.

I2C1
I2C0

MIPI D-PHY 0 MIPI D-PHY 1

PFU PFU PFU PFU PFU

4 EBR Blocks (9 kb each) 4 EBR Blocks (9 kb each) 4 EBR Blocks (9 kb each) 4 EBR Blocks (9 Kb each) 4 EBR Blocks (9 kb each)

PFU PFU PFU PFU PFU

Clocking PMU

DDR DLL1
DDR DLL2

Bank 2 PLL Bank 1 Bank 0

CONFIG
OSC

FLASH

Figure 3.7. CrossLinkPlus Device Simplified Block Diagram (Top Level)

3.4.1. PFU Blocks

The core of the CrossLinkPlus device consists of PFU blocks. Each PFU block consists of four interconnected slices numbered
0–3 as shown in Figure 3.8. Each slice contains two LUTs. All the interconnections to and from PFU blocks are from routing.
The PFU block can be used in Distributed RAM or ROM function, or used to perform Logic, Arithmetic, or ROM functions.

FPGA-DS-02054-0.92 17
CrossLinkPlus Family
Preliminary Data Sheet

From
Routing

LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 &
CARRY CARRY CARRY CARRY CARRY CARRY CARRY CARRY

Slice 0 Slice 1 Slice 2 Slice 3

D D D D D D D D

FF FF FF FF FF FF FF FF

To
Routing

Figure 3.8. CrossLinkPlus PFU Diagram

3.4.2. Slice
Each slice contains two LUT4s feeding two registers. Each PFU contains logic that allows the LUTs to be combined to
perform functions such as LUT5, LUT6, LUT7, and LUT8. There is control logic to perform set/reset functions
(programmable as synchronous/asynchronous), clock select, chip-select, and wider RAM/ROM functions. Figure 3.9
shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative
and edge triggered or level sensitive clocks.
Each slice has 14 input signals: 13 signals from routing and 1 signal from the carry-chain routed from the adjacent slice
or PFU. There are five outputs: four to routing and one to carry-chain (to the adjacent PFU). There are two inter
slice/PFU output signals that are used to support wider LUT functions, such as LUT6, LUT7, and LUT8. Table 3.4 and
Figure 3.10 list the signals associated with all the slices. Figure 3.8 shows the connectivity of the inter-slice/PFU signals
that support LUT5, LUT6, LUT7, and LUT8.

18 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

FCO

FXA
FXB
M1
M0
A1
B1 LUT4 &
C1 CARRY*
D1

F1
F1
FF

A0
B0 LUT4 &
C0 CARRY*
D0

F0
F0
FF

Q0
CE
CLK
LSR

FCI From Different Slice/PFU

Notes: For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2
WAD [A:D] is a 4-bit address from slice 2 LUT input

Figure 3.9. Slice Diagram

FPGA-DS-02054-0.92 19
CrossLinkPlus Family
Preliminary Data Sheet

PFU Col(n-1) PFU Col(n) PFU Col(n+1)

A1 A1 A1
LUT8 LUT8 LUT8
B1 F1 B1 F1 B1 F1
C1 C1 C1

3
3
D1 Q1 D1 Q1 D1 Q1
A0 A0 A0
B0 LUT5

SLICE
B0 LUT5 B0 LUT5

SLICE
SLICE
C0 F0 C0 F0 C0 F0
D0 D0 D0
FXB Q0 FXB Q0 FXB Q0
LUT7 Output FXA FXA FXA LUT7 Output
To Next PFU From Previous PFU

A1 A1 LUT6 A1
LUT6 LUT6
B1 F1 B1 F1 B1 F1
C1 C1 C1

2
2

D1 Q1 D1 Q1 D1 Q1
A0 A0 A0
B0 LUT5 LUT5

SLICE
B0 LUT5 B0

SLICE
SLICE

C0 F0 C0 F0 C0 F0
D0 D0 D0
FXB Q0 FXB Q0 FXB Q0
FXA FXA FXA

A1 A1 A1
LUT7 LUT7 LUT7
B1 F1 B1 F1 B1 F1
C1 C1 C1

1
1

D1 Q1 D1 Q1 D1 Q1
A0 A0 A0
B0 LUT5
SLICE
B0 LUT5 B0 LUT5

SLICE
SLICE

C0 F0 C0 F0 C0 F0
D0 D0 D0
FXB Q0 FXB Q0 FXB Q0
FXA FXA FXA

A1 A1 LUT6 A1
LUT6 LUT6
B1 F1 B1 F1 B1 F1
C1 C1 C1
0

0
0

D1 Q1 D1 Q1 D1 Q1
A0 A0 A0
LUT5 B0 LUT5 LUT5
SLICE

B0 B0

SLICE
SLICE

C0 F0 C0 F0 C0 F0
D0 D0 D0
FXB Q0 FXB Q0 FXB Q0
FXA FXA FXA

Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8

Table 3.4. Slice Signal Descriptions

Function Type Signal Names Description
Input Data signal A0, B0, C0, D0 Inputs to LUT4
Input Data signal A1, B1, C1, D1 Inputs to LUT4
Input Multi-purpose M0 Multipurpose Input
Input Multi-purpose M1 Multipurpose Input
Input Control signal CE Clock Enable
Input Control signal LSR Local Set/Reset
Input Control signal CLK System Clock
Input Inter-PFU signal FCI Fast Carry-in1
Input Inter-slice signal FXA Intermediate signal to generate LUT6, LUT7 and LUT82
Input Inter-slice signal FXB Intermediate signal to generate LUT6, LUT7 and LUT82
Output Data signals F0, F1 LUT4 output register bypass signals
Output Data signals Q0, Q1 Register outputs
Output Inter-PFU signal FCO Fast carry chain output1
Notes:
1. See Figure 3.9 for connection details.
2. Requires two adjacent PFUs.

20 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

3.5. Clocking Structure

The CrossLinkPlus device family provides resources to support a wide range of clocking requirements for
programmable video bridging. These resources are described below. For details, refer to CrossLinkPlus sysCLOCK
PLL/DLL Design and Usage Guide (FPGA-TN-02109).

3.5.1. sysCLK PLL

The CrossLinkPlus sysCLK PLL provides the ability to synthesize clock frequencies. See Table 4.14 for input frequency
range. The PLL provides features such as dynamic selectable clock input, clock injection delay removal, independent
dynamic output enable control, and programmable output phase adjustment. The architecture of the PLL is shown in
Figure 3.11.

Figure 3.11. CrossLinkPlus PLL Block Diagram

Table 3.5 provides a description of the signals in the PLL block.
Table 3.5. CrossLinkPlus PLL Port Definition
Signal I/O Description
CLKI I Input clock to PLL
CLKFB I Feedback clock
USRSTDBY I User port to put the PLL to sleep mode
PHASESEL[1:0] I Select the output affected by Dynamic Phase adjustment
PHASEDIR I Dynamic phase adjustment direction
PHASESTEP I Dynamic phase adjustment step
PHASELOADREG I Load dynamic phase adjustment values into PLL
RST I Resets the whole PLL
ENCLKOP I Enable PLL output CLKOP
ENCLKOS I Enable PLL output CLKOS
ENCLKOS2 I Enable PLL output CLKOS2
ENCLKOS3 I Enable PLL output CLKOS3
PLLWAKESYNC I Enable PLL switching from internal to user feedback path when PLL wake up
CLKOP O PLL main output clock
CLKOS O PLL output clock
CLKOS2 O PLL output clock
CLKOS3 O PLL output clock
LOCK O PLL LOCK to CLKI, asynchronous signal. Active high indicates PLL lock

FPGA-DS-02054-0.92 21
CrossLinkPlus Family
Preliminary Data Sheet

3.5.2. Primary Clocks

The primary clock routing network is made up of low skew clock routing resources with connectivity to every
synchronous element of the device. Primary clock sources are selected in the center mux and distributed on the
primary clock routing to clock the synchronous elements in the FPGA fabric. CrossLinkPlus family of devices provide up
to eight unique global primary clocks. Primary clock sources are:
 LVDS PIO pins
 GPIO pins
 PLL outputs
 Clock dividers
 Fabric internally generated clock signal
 Divided down clock from DPHY
 OSCI
The routing clock structure is shown in Figure 3.12.

MIPI_DPHY0 MIPI_DPHY1
CLK_HS_BYTE_0 HS_BYTE_CLK0 (RX and TX) HS_BYTE_CLK1 (RX and TX) CLK_HS_BYTE_0

2 2

Center Mux
(8 PCLKs out)

Fabric
Entry
Fabric
Entry

2 2

OSC_HF OSC_LF
OSC PLL

CLKDIV CLKDIV CLKDIV CLKDIV

Edge Clock s Edge Clock s

Bank 2 Bank 1 Bank 0
LVDS LVDS LVDS LVDS LVDS LVDS
GRPIO GRPIO GPIO GPIO
PIO PIO PIO PIO PIO PIO

Figure 3.12. CrossLinkPlus Clocking Structure

3.5.3. Edge Clocks

The CrossLinkPlus device has Edge Clocks (ECLK) at the bottom two banks (Bank 1 and Bank 2) of the device
(Figure 3.12). The CrossLinkPlus device has two edge clocks per Programmable I/O bank. These clocks, which have low
injection time and skew, are used to clock I/O registers. Edge clock resources are designed for high speed I/O interfaces
with high fan-out capability. The sources of edge clocks are:
 Dedicated Clock (PCLK) pins muxed with the DLLDEL output
 PLL outputs (CLKOP and CLKOS)
 Internal nodes
ELCK input MUX collects all clock sources as shown in Figure 3.13 below. There are two ECLK Input MUXs, one on each
bank. It drives the ECLK SYNC modules and the ECLK Clock Divider through a 2 to 1 MUX.

22 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

From ECLKSYNC of
other bank on
same side
Bank 1 or Bank 2 LVDS PCLK Pin

Bank 1 or Bank 2 DLLDEL Output

ECLK Tree
PLL CLKOP
ECLKSYNCB
PLL CLKOS

From Routing
To ECLK of other
bank on same side

Figure 3.13. CrossLinkPlus Edge Clock Sources per Bank

3.5.4. Dynamic Clock Enables

Each PLL output has a user input signal to dynamically enable/disable its output to provide a glitch free clock. When the
clock enable signal is set to logic 0, the corresponding output clock is held to logic 0. This allows you to save power by
stopping the corresponding output clock when not in use.

3.5.5. Internal Oscillator (OSCI)

The OSCI element performs multiple functions on the CrossLinkPlus device. It is used for configuration and available
during user mode. OSCI element has the following features in user mode:
 Always-on low frequency clock output (LFCLKOUT) with nominal frequency of 10 kHz
 High-frequency clock output (HFCLKOUT) with nominal frequency of 48 MHz that can be enabled or disabled using
HFOUTEN input
 Programmable output dividers (HFCLKDIV) for 48 MHz, 24 MHz, 12 MHz, or 6 MHz HFCLKOUT output
 Both output clocks have a direct connection to primary clock routing
Figure 3.14, Table 3.6, and Table 3.7 show the OSCI definitions.

Figure 3.14. CrossLinkPlus OSCI Component Symbol

Table 3.6. OSCI Component Port Definition
Port Name I/O Description
HFOUTEN I High frequency clock output enable
HFCLKOUT O High frequency clock output
LFCLKOUT O Low Frequency clock output

Table 3.7. OSCI Component Attribute Definition

Defparam Name Description Value Default
HFCLKDIV Configure HF oscillator output divider 1, 2, 4, 8 1

FPGA-DS-02054-0.92 23
CrossLinkPlus Family
Preliminary Data Sheet

3.6. Embedded Block RAM Overview

CrossLinkPlus devices contain sysMEM Embedded Block RAM (EBR). The EBR consists of a 9-kb RAM with memory core,
dedicated input registers and output registers with separate clock and clock enable.
Support for different memory configurations:
 Single Port
 True Dual Port
 Pseudo Dual Port
 ROM
 FIFO (logic wrapper added automatically by design tools)
Flexible customization features:
 Initialization of RAM/ROM
 Memory cascading (handled automatically by design tools)
 Optional parity bit support
 Byte-enable
 Multiple block size options
 RAM modes support optional Write Through or Read-Before-Write modes
For details, refer to CrossLinkPlus Memory Usage Guide (FPGA-TN-02110).
Table 3.8. sysMEM Block Configurations
Memory Mode Memory Size Configurations
8,192 x 1
4,096 x 2
Single Port 2,048 x 4
1,024 x 9
512 x 18
8,192 x 1
4,096 x 2
True Dual Port
2,048 x 4
1,024 x 9

8,192 x 1
4,096 x 2
Pseudo Dual Port 2,048 x 4
1,024 x 9
512 x 18

8,192 x 1
4,096 x 2
ROM 2,048 x 4
1,024 x 9
512 x 18

24 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

3.7. Power Management Unit

The embedded Power Management Unit (PMU) allows low-power Sleep State of the device. Figure 3.15 is the block
diagram of the PMU IP.
When instantiated in the design, PMU is always on, and uses the low-speed clock from oscillator of the device to
perform its operations.
The typical use case for the PMU is through a user implemented state machine that controls the sleep and wake up of
the device. The state machine implemented in the FPGA fabric identifies when the device needs to go into sleep mode,
issues the command through PMU FPGA fabric interface, assigns the parameters for sleep (time to wake up and so on)
and issues Sleep command.
The device can be woken up externally using the PMU Wake-Up (USRWKUP) pin, or from the PMU Watch Dog Timer
expiry or from I2C0 (address decoding detection or FIFO full in one of hardened I2C).

Power Management Unit (PMU)

PMU Clock (From Oscillator)

(PMUCLK)
External User Wake-up
(USRWKUPN)
PMU Wake-up from I2C0
(PMUWKUP)
Power Control Unit
8-bit Addressable Fabric Interface
PMU Sleep Signal, SLEEP

PMU Control
Register

Watch Dog
Timer

Watch Dog Timer

User Mode Signals

From FPGA Fabric

Figure 3.15. CrossLinkPlus MIPI D-PHY Block

3.7.1. PMU State Machine

PMU can place the device in two mutually exclusive states – Normal State and Sleep State. Figure 3.16 shows the PMU
State Machine triggers for transition from one state to the other.
 Normal State – All elements of the device are active to the extent required by the design. In this state, the device
is at fully active and performing as required by the application. Note that the power consumption of the device is
the highest in this state.
 Sleep State – The device is power gated such that the device is not operational. The configuration of the device
and the EBR contents are retained; thus in Sleep mode, the device does not lose configuration SRAM and EBR
contents. When it transitions to Normal state, device operates with these contents preserved.
The PMU is active along with the associated GPIOs. The power consumption of the device is lowest in this state.
This helps reduce the overall power consumption for the device.

FPGA-DS-02054-0.92 25
CrossLinkPlus Family
Preliminary Data Sheet

User Logic Initiated

Sleep Mode Normal Mode

User I2C/
External Wake-up/
WDT Expiry Wake-up

Figure 3.16. CrossLinkPlus PMU State Machine

For more details, refer to Power Management and Calculation for CrossLinkPlus Devices (FPGA-TN-02111).

3.8. User I2C IP

CrossLinkPlus devices have two I2C IP cores that can be configured either as an I2C master or as an I2C slave. The I2C0
core has pre-assigned pins, and supports PMU wakeup over I2C. The pins for the I2C1 interface are not pre-assigned –
you can use any General Purpose I/O pins.
The I2C cores support the following functionality:
 Master and Slave operation
 7-bit and 10-bit addressing
 Multi-master arbitration support
 Clock stretching
 Up to 1 MHz data transfer speed
 General call support
 Optionally delaying input or output data, or both
 Optional FIFO mode
 Transmit FIFO size is 10 bits x 16 bytes, receive FIFO size is 10 bits x 32 bytes
For further information on the User I2C, refer to CrossLinkPlus Hardened IP Usage Guide (FPGA-TN-02112).

3.9. Programming and Configuration

CrossLinkPlus is an SRAM-based programmable logic device that includes an internal Flash, as well as flexible SPI and
I2C configuration modes. CrossLinkPlus provides four modes for loading the configuration data into the SRAM memory.
 Self-Download Mode – CrossLinkPlus retrieves bitstream from the internal Flash
 Master SPI Mode – CrossLinkPlus retrieves bitstream from an external SPI Flash
 Slave SPI Mode – System microprocessor writes bitstream to CrossLinkPlus through SPI port
 Slave I2C Mode – System microprocessor writes bitstream to CrossLinkPlus through I2C port
CrossLinkPlus provides a set of sysCONFIG I/O pins to program and configure the FPGA. The sysCONFIG pins are
grouped together to create ports (I2C, SSPI, or MSPI) that are used to interact with the FPGA for programming,
configuration, and access of resources inside the FPGA. The sysCONFIG pins in a configuration group, as shown in
Table 3.9, may be active and used for programming the FPGA. Or, they can be reconfigured to act as general purpose
I/O.

26 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

Table 3.9. CrossLinkPlus sysCONFIG Pins

Pin Name Associated sysCONFIG Port
CRESET_B Self Download Mode/SSPI/MSPI/I2C
CDONE Self Download Mode/SSPI/MSPI/I2C
SPI_SCK/MCK/SDA SSPI/MSPI/I2C
SPI_SS/CSN/SCL SSPI/MSPI/I2C
MOSI SSPI/MSPI
MISO SSPI/MSPI

As external power ramps up, a Power On Reset (POR) circuit inside the FPGA becomes active. When POR conditions are
met, the POR circuit releases an internal reset strobe, allowing the device to begin its initialization process. After
CrossLinkPlus drives CDONE low, CrossLinkPlus enters the memory initialization phase where it clears all of the SRAM
memory inside the FPGA. CrossLinkPlus remains in initialization state until the CRESET_B pin is deasserted (HIGH) or
after SSPI/SI2C activation code is received.
 After CRESET_B goes from low to high, the Configuration Logic puts the device into master auto booting mode
where it boots either from the internal Flash or an external SPI boot PROM.
 Holding the CRESET_B low postpones the master auto-booting event and allows the slave configuration ports
(Slave SPI or Slave I2C) to detect a Slave Active condition where the SPI or I2C Master sends an Activation Key code
to CrossLinkPlus. To prevent the device from entering Master Auto Boot Mode during power-up, CRESET_B must
be asserted within 9.5 ms from Vcc min (Table 4.2). Once CRESET_B is asserted, the Activation Keys can be written
to CrossLinkPlus at any time as long as CRESET_B is asserted.
 Sources should not drive output to CrossLinkPlus until configuration has been completed to ensure CrossLinkPlus is
in a known state.
In addition to the flexible configuration modes, the CrossLinkPlus configuration engine supports the following special
features:
 TransFR (Transparent Field Reconfiguration) allowing you to update logic in field without interrupting system
operation by freezing I/O states during configuration
 Dual-Boot Support for primary and golden bitstreams provides automatic recovery from configuration failures.
One image is in the internal Flash and second image is in the external Flash.
 Security and One-Time Programmable (OTP) modes protect bitstream integrity and prevent read back
 64-bit unique TraceID per device
For more information, refer to CrossLinkPlus Programming and Configuration Usage Guide (FPGA-TN-02103).

FPGA-DS-02054-0.92 27
CrossLinkPlus Family
Preliminary Data Sheet

4. DC and Switching Characteristics

4.1. Absolute Maximum Ratings

Table 4.1. Absolute Maximum Ratings 1, 2, 3
Symbol Parameter Min Max Unit
VCC Core Supply Voltage –0.5 1.32 V
VCCGPLL PLL Supply Voltage –0.5 1.32 V
VCCAUX Auxiliary Supply Voltage for Bank 1, Bank 2, and Flash –0.5 3.63 V
VCCIO I/O Driver Supply Voltage for Banks 0, 1, 2 –0.5 3.63 V
— Input or I/O Transient Voltage Applied –0.5 3.63 V
VCCA_DPHYx
VCCPLL_DPHY MIPI D-PHY Supply Voltages –0.5 1.32 V
VCCMU_DPHY1
— Voltage Applied on MIPI D-PHY Pins –0.5 1.32 V
TA Storage Temperature (Ambient) –65 150 °C
TJ Junction Temperature (TJ) — +125 °C
Notes:
1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.

4.2. Recommended Operating Conditions

Table 4.2. Recommended Operating Conditions 1, 2
Symbol Parameter Min Max Unit
VCC Core Supply Voltage 1.14 1.26 V
VCCGPLL PLL Supply Voltage 1.14 1.26 V
Auxiliary Supply Voltage for Bank 1, Bank 2, and Flash – @ 2.5 V 2.375 2.625 V
VCCAUX
Auxiliary Supply Voltage for Bank 1, Bank 2, and Flash – @ 3.3 V 3.135 3.465 V
VCCIO0 I/O Driver Supply Voltage for Bank 0 1.71 3.465 V
VCCIO1/2 I/O Driver Supply Voltage for Bank 1, Bank 2 1.14 3.465 V
TJIND Junction Temperature, Industrial Operation –40 100 °C
D-PHY External Power Supply
VCCA_DPHYx Analog Supply Voltage for D-PHY 1.14 1.26 V
VCCPLL_DPHYx PLL Supply voltage for D-PHY 1.14 1.26 V
Notes:
1. For correct operation, all supplies must be held in their valid operation range.
2. Like power supplies, must be tied together if they are at the same supply voltage. Follow the noise filtering recommendations in
CrossLinkPlus Hardware Checklist (FPGA-TN-02105).

28 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

4.3. Power Supply Ramp Rates

Over recommended operating conditions.
Table 4.3. Power Supply Ramp Rates*
Symbol Parameter Min Max Unit
tRAMP Power supply ramp rates for all power supplies 0.6 10 V/ms
*Note: Assume monotonic ramp rates.

4.4. Power-On-Reset Voltage Levels

Table 4.4. Power-On-Reset Voltage Levels 1, 3, 4
Symbol Parameter Min Typ Max Unit
VCC — 0.95 — V
Power-On-Reset ramp up trip point
VPORUP VCCIO02 0.87 — 1.50 V
(Monitoring VCC, VCCIO0, and VCCAUX)
VCCAUX — 2.10 — V
VCC — 0.825 — V
VPORDN Power-On-Reset ramp down trip point VCCIO02 — — 1.50 V
(Monitoring VCC, VCCIO0, and VCCAUX)
VCCAUX — 1.90 — V
Notes:
1. These POR ramp up trip points are only provided for guidance. Device operation is only characterized for power supply voltages
specified under recommended operating conditions.
2. Only VCCIO0 (Config Bank) has a Power-On-Reset ramp up trip point. All other VCCIOs do not have Power-On-Reset ramp up
detection.
3. VCCIO supplies should be powered-up before or together with the VCC and VCCAUX supplies.
4. Configuration starts after VCC, VCCIO0, and VCCAUX reach VPORUP. For details, see tCONFIGURATION time in Table 4.21.

4.5. Electro-Static Discharge (ESD) Performance

Refer to the LIFMDF Product Family Qualification Summary for complete qualification data, including the ESD
performance.

FPGA-DS-02054-0.92 29
CrossLinkPlus Family
Preliminary Data Sheet

4.6. DC Electrical Characteristics

Over recommended operating conditions.
Table 4.5. DC Electrical Characteristics
Symbol Parameter Condition Min Typ Max Unit
1, 4, 5 Input or I/O Leakage 0 ≤ VIN ≤ VCCIO −10 — +10 µA
IIL, IIH
VCCIO = 1.8 V between 0 ≤ VIN ≤ 0.65 * VCCIO −3 — −31 µA
IPU4 Internal Pull-Up Current VCCIO = 2.5 V between 0 ≤ VIN ≤ 0.65 * VCCIO −8 — −72 µA
VCCIO = 3.3 V between 0 ≤ VIN ≤ 0.65 * VCCIO −11 — −128 µA
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.2 V,
C1 2 I/O Capacitance2 — 6 — pF
VCC = 1.2 V, VIO = 0 to VIH (MAX)
Dedicated Input VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.2 V,
C2 2 — 6 — pF
Capacitance2 VCC = 1.2 V, VIO = 0 to VIH (MAX)
MIPI D-PHY High Speed VCCIO = 2.5V,VCC = 1.2V, VCC*_DPHY = 1.2V , VIO
C3 2 — 5 — pF
I/O Capacitance = 0 to VIH (MAX)
Hysteresis for Single- VCCIO = 3.3 V, 2.5 V, 1.8 V
VHYST3 — 200 — mV
Ended Inputs VCC = 1.2 V, VIO = 0 to VIH (MAX)
Notes:
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is
not measured with the output driver active. Bus maintenance circuits are disabled.
2. TA = 25 oC, f = 1.0 MHz.
3. Hysteresis is not available for VCCIO = 1.2 V.
4. Weak pull-up setting. Programmable pull-up resistors on Bank 0 sees higher current. Refer to CrossLinkPlus sysI/O Usage Guide
(FPGA-TN-02108) for details on programmable pull-up resistors.
5. Input pins are clamped to VCCIO and GND by a diode. When input is higher than VCCIO, or lower than GND, the Input Leakage
current is higher than the IIL and IIH.

4.7. CrossLinkPlus Supply Current

Over recommended operating conditions.
Table 4.6. CrossLinkPlus Supply Current
Symbol Parameter Typ Unit
Normal Operation 1
ICC VCC Power Supply Current 7 mA
ICCPLL PLL Power Supply Current 50 µA
ICCAUX Auxiliary Power Supply Current for Bank 1, 2 and Flash Programming Supply Current 3 mA
ICCIOx Bank x Power Supply Current (per Bank) 60 µA
ICCA_DPHYx VCCA_DPHYx Power Supply Current 8.5 mA
ICCPLL_DPHYx VCCPLL_DPHYx Power Supply Current 1.5 mA
Standby Current2
ICC_STDBY VCC Power Supply Standby Current 4 mA
ICCPLL_STDBY PLL Power Supply Standby Current 10 µA
ICCAUX_STDBY Auxiliary Power Supply Current for Bank 1, 2 and Flash Programming Supply Standby Current 0.2 mA
ICCIOx_STDBY Bank Power Supply Standby Current (per Bank) 6 µA
ICCA_DPHYx_STDBY VCCA_DPHYx Power Supply Standby Current 6 µA
ICCPLL_DPHYx_STDBY VCCPLL_DPHYx Power Supply Standby Current 4 µA
Sleep/Power Down Mode Current 3
ICC_SLEEP VCC Power Supply Sleep Current 0.2 mA
ICCPLL_SLEEP PLL Power Supply Current 10 µA
ICCAUX_SLEEP Auxiliary Power Supply Current for Bank 1, 2 and Flash Programming Supply Current 20 µA

30 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

Symbol Parameter Typ Unit

ICCIOx_SLEEP Bank Power Supply Current (per Bank) 6 µA
ICCA_DPHY_SLEEP VCCA_DPHYx Power Supply Sleep Current 6 µA
ICCPLL_DPHY_SLEEP VCCPLL_DPHYx Power Supply Sleep Current 4 µA
Notes:
1. Normal Operation
2:1 MIPI CSI-2 Image Sensor Aggregator Bridge design under the following conditions:
a. TJ = 25 °C, all power supplies at nominal voltages.
b. Typical processed device in ucfBGA64 package.
c. To determine power for all other applications and operating conditions, use Power Calculator in Lattice Diamond design
software.
2. Standby Operation
A typically processed device in ucfBGA64 package with “blank” pattern programmed. A “blank” pattern configured the part to
the following conditions:
a. All outputs are tri-stated, all inputs are held at either VCCIO, or GND.
b. All clock inputs are at 0 MHz.
c. TJ = 25 °C, all power supplies at nominal voltages.
d. No pull-ups on I/O.
3. Sleep/Power Down Mode
2:1 MIPI CSI-2 Image Sensor Aggregator Bridge design under the following conditions:
a. Design is put into Sleep/Power Down Mode with user logic powers down D-PHY, and enters into Sleep Mode in PMU.
b. TJ = 25 °C, all power supplies at nominal voltages.
c. Typical processed device in ucfBGA64 package.
4. For ucfBGA64 package
a. VCCA_DPHY0 and VCCA_DPHY1 are tied together as VCCA_DPHYx.
b. VCCPLL_DPHY0 and VCCPLL_DPHY1 are tied together as VCCPLL_DPHYx.
5. To determine the CrossLinkPlus start-up peak current, use the Power Calculator tool in the Lattice Diamond design software.

4.8. Power Management Unit (PMU) Timing

Over recommended operating conditions.
Table 4.7. PMU Timing*
Symbol Parameter Device Max Unit
tPMUWAKE Time for PMU to wake from Sleep mode All Devices 0.5 ms
*Note: For details on PMU usage, refer to Power Management and Calculation for CrossLinkPlus Devices (FPGA-TN-02111).

FPGA-DS-02054-0.92 31
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Preliminary Data Sheet

4.9. sysI/O Recommended Operating Conditions

Over recommended operating conditions.
Table 4.8. sysI/O Recommended Operating Conditions1
VCCIO
Standard
Min Typ Max
LVCMOS33/LVTTL33 3.135 3.30 3.465
LVCMOS25 2.375 2.50 2.625
LVCMOS18 1.710 1.80 1.890
LVCMOS12 (Output only) 2 1.140 1.20 1.260
1.710 1.80 1.890
subLVDS (Input only) 2.375 2.50 2.625
3.135 3.30 3.465
1.140 1.20 1.260
1.710 1.80 1.890
SLVS200 (Input only) 3
2.375 2.50 2.625
3.135 3.30 3.465
1.710 1.80 1.890
LVDS (Input only) 2.375 2.50 2.625
3.135 3.30 3.465
LVDS (Output only) 2.375 2.50 2.625
MIPI (Input only) 1.140 1.20 1.260
Notes:
1. For input voltage compatibility, refer to CrossLinkPlus sysI/O Usage Guide (FPGA-TN-02108).
2. For VCCIO1 and VCCIO2 only.
3. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section.

4.10. sysI/O Single-Ended DC Electrical Characteristics

Over recommended operating conditions.
Table 4.9. sysI/O Single-Ended DC Electrical Characteristics1
Input/Output VIL VIH VOL Max VOH Min IOL IOH
Standard Min (V) Max (V) Min (V) Max (V) (V) (V) (mA) (mA)
LVCMOS33/ 0.40 VCCIO − 0.4 8 –8
–0.3 0.8 2.0 VCCIO+0.2
LVTTL33 0.20 VCCIO − 0.2 0.1 –0.1
0.40 VCCIO − 0.4 6 –6
LVCMOS25 –0.3 0.7 1.7 VCCIO+0.2
0.20 VCCIO − 0.2 0.1 –0.1
0.40 VCCIO − 0.4 4 –4
LVCMOS18 –0.3 0.35 VCCIO 0.67 VCCIO VCCIO+0.2
0.20 VCCIO − 0.2 0.1 –0.1
LVCMOS12(2) 0.40 VCCIO − 0.4 2 –2
— — — —
(Output only) 0.20 VCCIO − 0.2 0.1 –0.1
Notes:
1. VCCIO in the table follows the VCCIO power rail setting of the respective bank.
2. For VCCIO1 and VCCIO2 only.

32 FPGA-DS-02054-0.92
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Preliminary Data Sheet

4.11. sysI/O Differential Electrical Characteristics

4.11.1. LVDS/subLVDS/SLVS200
Over recommended operating conditions.
Table 4.10. LVDS/subLVDS1/SLVS200 1, 2
Parameter Description Test Conditions Min Typ Max Unit
VINP, VINN Input Voltage — 0.00 — 2.40 V
VCM Input Common Mode Voltage Half the sum of the two inputs 0.05 — 2.35 V
VTHD(LVDS) Differential Input Threshold ǀVINP - VINNǀ 100 — — mV
VTHD(subLVDS) Differential Input Threshold ǀVINP - VINNǀ 90 — — mV
VTHD(SLVS200) Differential Input Threshold ǀVINP - VINNǀ 70 — — mV
Normal Mode −10 — 10 µA
IIN Input Current
Standby Mode −10 — 10 µA
VOH Output High Voltage for VOP or VOM RT = 100 Ω — 1.43 1.60 V
VOL Output Low Voltage for VOP or VOM RT = 100 Ω 0.90 1.08 — V
VOD Output Voltage Differential |VOP - VOM|, RT = 100 Ω 250 350 450 mV
Change in VOD between High and
∆VOD — — — 50 mV
Low
Output Voltage Offset (Common (VOP + VOM)/2, RT = 100 Ω
VOS Mode Voltage) 1.125 1.250 1.375 V

∆VOS Change in VOS between H and L — — — 50 mV

VOD = 0 V driver outputs shorted to
ISAB Output Short Circuit Current — — 12 mA
each other
Notes:
1. Inputs only for subLVDS and SLVS200.
2. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section.

FPGA-DS-02054-0.92 33
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Preliminary Data Sheet

4.11.2. Hardened MIPI D-PHY I/O

Over recommended operating conditions.
Table 4.11. MIPI D-PHY
Symbol Description Min Typ Max Unit
Receiver
High Speed
VCMRX Common-Mode Voltage HS Receive Mode 70 — 330 mV
VIDTH Differential Input High Threshold — — 70 mV
VIDTL Differential Input Low Threshold −70 — — mV
VIHHS Single-ended input High Voltage — — 460 mV
VILHS Single-ended Input Low Voltage −40 — — mV
VTERM-EN Single-ended Threshold for HS Termination Enable — — 450 mV
ZID Differential Input Impedance 80 100 125 Ω
Low Power
VIH Logic 1 Input Voltage 880 — — mV
VIL Logic 0 Input Voltage, not in ULP State — — 550 mV
VIL-ULPS Logic 0 Input Voltage, in ULP State — — 300 mV
VHYST Input Hysteresis 25 — — mV
Transmitter
High Speed
VCMTX HS Transmit Static Common Mode Voltage 150 200 250 mV
VOD HS Transmit Differential Voltage 140 200 270 mV
VOHHS HS Single-ended Output High Voltage — — 360 mV
ZOS Single-ended Output Impedance 40 50 62.5 Ω
ΔZOS Single-ended Output Impedance Mismatch — — 10 %
Low Power
VOH Output High Voltage 1.1 1.2 1.3 V
VOL Output Low Voltage −50 — 50 mV
ZOLP Output Impedance in LP Mode 110 — — Ω

34 FPGA-DS-02054-0.92
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Preliminary Data Sheet

4.12. CrossLinkPlus Maximum General Purpose I/O Buffer Speed

Over recommended operating conditions.
Table 4.12. CrossLinkPlus Maximum I/O Buffer Speed
Buffer Description Max Unit
Maximum Input Frequency
LVDS25 LVDS, VCCIO = 2.5 V 600 MHz
subLVDS subLVDS, VCCIO = 2.5 V 600 MHz
6,7 MIPI D-PHY 600 MHz
MIPI D-PHY (HS)
MIPI D-PHY (LP)7 MIPI D-PHY 5 MHz
SLVS2007 SLVS200, VCCIO=2.5 V 600 MHz
LVCMOS33/LVTTL33 LVCMOS/LVTTL, VCCIO = 3.3 V 300 MHz
LVCMOS25D Differential LVCMOS, VCCIO = 2.5 V 300 MHz
LVCMOS25 LVCMOS, VCCIO = 2.5 V 300 MHz
LVCMOS18 LVCMOS, VCCIO = 1.8 V 155 MHz
Maximum Output Frequency
LVDS25 LVDS, VCCIO = 2.5 V 600 MHz
LVCMOS33/LVTTL33 LVCMOS/LVTTL, VCCIO = 3.3 V 300 MHz
LVTTL33D Differential LVTTL, VCCIO = 3.3 V 300 MHz
LVCMOS33D Differential LVCMOS, 3.3 V 300 MHz
LVCMOS25 LVCMOS, 2.5 V 300 MHz
LVCMOS25D Differential LVCMOS, 2.5 V 300 MHz
LVCMOS18 LVCMOS, 1.8 V 155 MHz
LVCMOS12 LVCMOS, VCCIO1/2 = 1.2 V 70 MHz
Notes:
1. These maximum speeds are characterized but not tested on every device.
2. Maximum I/O speed for differential output standards emulated with resistors depends on the layout.
3. LVCMOS timing is measured with the load specified in Table 4.23.
4. Actual system operation may vary depending on user logic implementation.
5. Maximum data rate equals two times the clock rate when utilizing DDR.
6. This is the maximum MIPI D-PHY input rate on the programmable I/O Bank 1 and Bank 2. The hardened MIPI D-PHY input and
output rates are described in Hardened MIPI D-PHY Performance section. For SLVS200/MIPI interface I/O placement, see the
Programmable I/O Banks section.
7. Implement the following guideline for I/O placement when MIPI Rx inputs are present on the programmable I/O banks to
ensure optimal performance:
Bank 1 Bank 2
SLVS200/MIPI Rx on Bank 1 No LVCMOS Outputs No LVCMOS Outputs
SLVS200/MIPI Rx on Bank 2 No LVCMOS Outputs No LVCMOS Outputs
SLVS200/MIPI Rx on Bank 1 & Bank 2 No LVCMOS Outputs No LVCMOS Outputs

FPGA-DS-02054-0.92 35
CrossLinkPlus Family
Preliminary Data Sheet

4.13. CrossLinkPlus External Switching Characteristics

Over recommended operating conditions.
Table 4.13. CrossLinkPlus External Switching Characteristics 3,4
–6
Parameter Description Conditions Unit
Min Max
Clocks
Primary Clock
fMAX_PRI Frequency for Primary Clock Tree — — 150 MHz
tW_PRI Clock Pulse Width for Primary Clock — 0.8 — ns
tSKEW_PRI Primary Clock Skew Within a Clock — — 450 ps
Edge Clock
fMAX_EDGE Frequency for Edge Clock Tree — — 600 MHz
tW_EDGE Clock Pulse Width for Edge Clock — 0.783 — ns
tSKEW_EDGE Edge Clock Skew Within a Bank — — 120 ps
Generic DDR Interfaces 1
Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Centered at General Purpose Pins (GDDRX8_RX/TX.ECLK.Centered
or GDDRX4_RX/TX.ECLK.Centered or GDDRX2_RX/TX.ECLK.Centered)
Input Data Set-Up Before CLK Rising
tSU_GDDRX2_4_8_CENTERED — 0.167 — ns
and Falling edges
Input Data Hold After CLK Rising and
tHD_GDDRX2_4_8_CENTERED — 0.167 — ns
Falling edges
Output Data Valid Before CLK Output Data Rate = 1.2 Gb/s 0.297 — ns
tDVB_GDDRX2_4_8_CENTERED
Rising and Falling edges Other Data Rates −0.120 — ns+1/2UI
Output Data Valid After CLK Output Data Rate = 1.2 Gb/s 0.297 — ns
tDVA_GDDRX2_4_8_CENTERED
Rising and Falling edges Other Data Rates −0.120 — ns+1/2UI
GDDRX2 — 300 MHz
fMAX_GDDRX2_4_8_CENTERED Frequency for ECLK2
GDDRX4 and GDDRX8 — 600 MHz

36 FPGA-DS-02054-0.92
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Preliminary Data Sheet

Table 4.13. CrossLinkPlus External Switching Characteristics 3.4(Continued)

–6
Parameter Description Conditions Unit
Min Max
Generic DDR Interfaces 1

Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Centered at General Purpose Pins (GDDRX8_RX/TX.ECLK.Centered
or GDDRX4_RX/TX.ECLK.Centered or GDDRX2_RX/TX.ECLK.Centered)
Generic DDRX1 I/O with Clock and Data Centered at General Purpose Pins (GDDRX1_RX/TX.SCLK.Centered)
Input Data Set-Up Before CLK
tSU_GDDRX1_CENTERED Rising and Falling edges — 0.917 — ns

Input Data Hold After CLK Rising

tHD_GDDRX1_CENTERED — 0.917 — ns
and Falling edges
Data Rate =
Output Data Valid Before CLK 1.217 — ns
tDVB_GDDRX1_CENTERED 300 Mb/s
Output Rising and Falling edges
Other Data Rates -0.450 — ns+1/2UI
Data Rate =
Output Data Valid After CLK 1.217 — ns
tDVA_GDDRX1_CENTERED 300 Mb/s
Output Rising and Falling edges
Other Data Rates -0.450 — ns+1/2UI
fMAX_GDDRX1_CENTERED Frequency for PCLK2 — — 150 MHz
Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Aligned at General Purpose Pins (GDDRX8_RX/TX.ECLK.Aligned or
GDDRX4_RX/TX.ECLK.Aligned or GDDRX2_RX/TX.ECLK.Aligned)
Data Rate =
— 0.188 ns
Input Data Valid After CLK Rising 1.2 Gb/s
tSU_GDDRX2_4_8_ALIGNED
and Falling edges
Other Data Rates — −0.229 ns+1/2UI

Data Rate =
0.646 — ns
Input Data Hold After CLK Rising 1.2 Gb/s
tHD_GDDRX2_4_8_ALIGNED
and Falling edges
Other Data Rates 0.229 — ns+1/2UI

Output Data Invalid After CLK

tDIA_GDDRX2_4_8_ALIGNED — — 0.120 ns
Rising and Falling edges Output
Output Data Invalid Before CLK
tDIB_GDDRX2_4_8_ALIGNED — — 0.120 ns
Output Rising and Falling edges
GDDRX2 — 300 MHz
fMAX_GDDRX2_4_8_ALIGNED Frequency for ECLK2
GDDRX4 and GDDRX8 — 600 MHz

FPGA-DS-02054-0.92 37
CrossLinkPlus Family
Preliminary Data Sheet

Table 4.13. CrossLinkPlus External Switching Characteristics 3,4(Continued)

–6
Parameter Description Conditions Unit
Min Max
Generic DDR Interfaces 1
Generic DDRX1 I/O with Clock and Data Aligned at General Purpose Pins (GDDRX1_RX/TX.SCLK.Aligned)

Data Rate =
— 0.750 ns
Input Data Valid After CLK Rising 300 Mb/s
tSU_GDDRX1_ALIGNED
and Falling edges
Other Data Rates — -0.917 ns+1/2UI

Data Rate =
2.583 — ns
Input Data Hold After CLK Rising 300 Mb/s
tHD_GDDRX1_ALIGNED
and Falling edges
Other Data Rates 0.916 — ns+1/2UI

Output Data Invalid After CLK

tDIA_GDDRX1_ALIGNED — — 0.450 ns
Rising and Falling edges Output

Output Data Invalid Before CLK

tDIB_GDDRX1_ALIGNED — — 0.450 ns
Output Rising and Falling edges
fMAX_GDDRX1_ALIGNED Frequency for ECLK2 — — 150 MHz
General Purpose I/O MIPI D-PHY Rx with 1:8 or 1:16 Gearing
842 Mb/s < Data Rate ≤
1.2 Gb/s &
0.200 — UI
VIDTH = 140 mV
VIDTL = -140 mV

473 Mb/s < Data Rate ≤

tSU_GDDRX_MP Input Data Set-Up Before CLK 842 Mb/s & 0.150 — UI
VIDTH = 140 mV
VIDTL = -140 mV

Data Rate ≤ 473 Mb/s &

VIDTH = 70 mV 0.150 — UI
VIDTL = -70 mV

842 Mb/s < Data Rate ≤

1.2 Gb/s &
0.200 — UI
VIDTH = 140 mV
VIDTL = -140 mV

473 Mb/s < Data Rate ≤

tHD_GDDRX_MP Input Data Hold After CLK 842 Mb/s &
0.150 — UI
VIDTH = 140 mV
VIDTL = -140 mV

Data Rate ≤ 473 Mb/s &

VIDTH = 70 mV 0.150 — UI
VIDTL = -70 mV

fMAX_GDDRX_MP Frequency for ECLK2 — — 600 MHz

38 FPGA-DS-02054-0.92
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Preliminary Data Sheet

Table 4.13. CrossLinkPlus External Switching Characteristics 3,4 Continued)

–6
Parameter Description Conditions Unit
Min Max
Generic DDRX71 or DDRX141 Inputs (GDDRX71_RX.ECLK or GDDRX141_RX.ECLK)
Input Valid Bit "i" switching from — — 0.3 UI
tRPBi_DVA CLK Rising Edge ns+
("i" = 0 to 6, 0 aligns with CLK) — — −0.222
(i+ 1/2)*UI

Input Hold Bit "i" switching from — 0.7 — UI

tRPBi_DVE CLK Rising Edge ns+
("i" = 0 to 6, 0 aligns with CLK) — 0.222 —
(i+ 1/2)*UI
fMAX_RX71_141 DDR71/DDR141 ECLK Frequency2 — — 450 MHz
Generic DDR Interfaces 1
Generic DDRX71 Outputs with Clock and Data Aligned at Pin (GDDRX71_TX.ECLK)
Data Output Valid Bit "i" switching
tTPBi_DOV from CLK Rising Edge ("i" = 0 to 6, — — 0.143 ns+i*UI
0 aligns with CLK)

Data Output Invalid Bit "i"

tTPBi_DOI switching from CLK Rising Edge ("i" — −0.143 — ns+i*UI
= 0 to 6, 0 aligns with CLK)

tTPBi_skew_UI Tx skew in UI — — 0.15 UI

fMAX_TX71 — 2 — 525 MHz
DDR71 ECLK Frequency
Generic DDRX141 Outputs with Clock and Data Aligned at Pin (GDDRX141_TX.ECLK)
Data Output Valid Bit "i" switching
tTPBi_DOV from CLK Rising Edge ("i" = 0 to 6, — — 0.125 ns+i*UI
0 aligns with CLK)
Data Output Invalid Bit "i"
tTPBi_DOI switching from CLK Rising Edge ("i" — −0.125 — ns+i*UI
= 0 to 6, 0 aligns with CLK)
tTPBi_skew_UI TX skew in UI — — 0.15 UI
fMAX_TX141 DDR141 ECLK Frequency 2 — — 600 MHz
Notes:
1. Generic DDRX8, DDRX71 and DDRX141 timing numbers based on LVDS I/O.
2. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
3. These numbers are generated using best case PLL location.
4. All numbers are generated with the Lattice Diamond design software.

FPGA-DS-02054-0.92 39
CrossLinkPlus Family
Preliminary Data Sheet

Rx CLK (in)

Rx DATA (in)

tSU/tDVBDQ tSU/tDVBDQ

tHD/tDVADQ tHD/tDVADQ

Figure 4.1. Receiver RX.CLK.Centered Waveforms

1/2 UI 1/2 UI

Rx CLK (in) 1 UI

Rx DATA (in)

tSU
tSU
tHD
tHD

Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms

1/2 UI 1/2 UI 1/2 UI 1/2 UI

Tx CLK (out)

Tx DATA (out)

tDVB tDVB

tDVA tDVA

Figure 4.3. Transmit TX.CLK.Centered Output Waveforms

40 FPGA-DS-02054-0.92
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Preliminary Data Sheet

1 UI
Tx CLK (out)

Tx DATA (out)

tDIB tDIB

tDIA tDIA

Figure 4.4. Transmit TX.CLK.Aligned Waveforms

Figure 4.5. DDRX71, DDRX141 Video Timing Waveforms

FPGA-DS-02054-0.92 41
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Preliminary Data Sheet

4.14. sysCLOCK PLL Timing

Over recommended operating conditions.
Table 4.14. sysCLOCK PLL Timing
Parameter Descriptions Conditions Min Max Unit
fIN Input Clock Frequency (CLKI, CLKFB) — 10 400 MHz
fPD Phase Detector Input Clock Frequency — 10 400 MHz
fOUT Output Clock Frequency (CLKOP, CLKOS) — 4.6875 600 MHz
fVCO PLL VCO Frequency — 600 1200 MHz
AC Characteristics
tDT Output Clock Duty Cycle — 45 55 %
tPH Output Phase Accuracy — −5 5 %
fOUT ≥ 100 MHz — 100 ps p-p
Output Clock Period Jitter 3
fOUT < 100 MHz — 0.025 UIPP
fOUT ≥ 100 MHz — 200 ps p-p
tOPJIT1 Output Clock Cycle-to-Cycle Jitter 3
fOUT < 100 MHz — 0.05 UIPP
fPD > 100 MHz — 200 ps p-p
Output Clock Phase Jitter
fPD < 100 MHz — 0.05 UIPP
tSPO Static Phase Offset Divider ratio = integer — 400 ps p-p
2 PLL Lock-in Time — — 15 ms
tLOCK
tUNLOCK PLL Unlock Time — — 50 ns
fPD ≥ 20 MHz — 500 ps p-p
tIPJIT Input Clock Period Jitter
fPD < 20 MHz — 0.02 UIPP
tHI Input Clock High Time 90% to 90% 0.5 — ns
tLO Input Clock Low Time 10% to 10% 0.5 — ns
Notes:
1. Jitter sample is taken over 10,000 samples for Periodic jitter, and 2,000 samples for Cycle-to-Cycle jitter of the primary PLL
output with clean reference clock with no additional I/O toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPD ≥ 10 MHz. For fPD < 10 MHz, the jitter numbers may not be
met in certain conditions.

4.15. Hardened MIPI D-PHY Performance

Over recommended operating conditions.
Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s)
Parameter Description Min Max Unit
tSU_MIPIX8 Input Data Setup before CLK 0.227 — UI
tHD_MIPIX8 Input Data Hold after CLK 0.305 — UI
tDVB_MIPIX8 Output Data Valid before CLK Output 0.200 — UI
tDVA_MIPIX8 Output Data Valid after CLK Output 0.200 — UI

Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s)
Parameter Description Min Max Unit
tSU_MIPIX4 Input Data Setup before CLK 0.200 — UI
tHD_MIPIX4 Input Data Hold after CLK 0.200 — UI
tDVB_MIPIX4 Output Data Valid before CLK Output 0.200 — UI
tDVA_MIPIX4 Output Data Valid after CLK Output 0.200 — UI

42 FPGA-DS-02054-0.92
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Preliminary Data Sheet

Table 4.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s)
Parameter Description Min Max Unit
tSU_MIPIX4 Input Data Setup before CLK 0.150 — UI
tHD_MIPIX4 Input Data Hold after CLK 0.150 — UI
tDVB_MIPIX4 Output Data Valid before CLK Output 0.150 — UI
tDVA_MIPIX4 Output Data Valid after CLK Output 0.150 — UI

4.16. Internal Oscillators (HFOSC, LFOSC)

Over recommended operating conditions.
Table 4.18. Internal Oscillators
Parameter Parameter Description Min Typ Max Unit
fCLKHF HFOSC CLKK Clock Frequency 43.2 48 52.8 MHz
fCLKLF LFOSC CLKK Clock Frequency 9 10 11 kHz
DCHCLKHF HFOSC Duty Cycle (Clock High Period) 45 50 55 %
DCHCLKLF LFOSC Duty Cycle (Clock High Period) 45 50 55 %

4.17. User I2C

Over recommended operating conditions.
Table 4.19. User I2C 1
STD Mode FAST Mode FAST Mode Plus2
Symbol Parameter Units
Min Typ Max Min Typ Max Min Typ Max
SCL Clock — — —
fscl — 100 — 400 — 10002 kHz
Frequency
Optional delay
TDELAY — 62 — — 62 — — 62 — ns
through delay block
Notes:
1. Refer to the I2C Specification for timing requirements.
2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I2C bus. Internal pull up may not be
sufficient to support the maximum speed.

FPGA-DS-02054-0.92 43
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Preliminary Data Sheet

4.18. CrossLinkPlus sysCONFIG Port Timing Specifications

Over recommended operating conditions.
Table 4.20. CrossLinkPlus sysCONFIG Port Timing Specifications
Symbol Parameter Min Max Unit
All Configuration Mode
tPRGM3 Minimum CRESET_B LOW pulse width required to ns
290 —
restart configuration (from falling edge to rising edge)
Slave SPI1
fCCLK SPI_SCK Input Clock Frequency — 110 MHz
tSTSU MOSI Setup Time 0.5 — ns
tSTH MOSI Hold Time 2.0 — ns
tSTCO SPI_SCK Falling Edge to Valid MISO Output — 13.3 ns
tSCS Chip Select HIGH Time 25 — ns
tSCSS Chip Select Setup Time 0.5 — ns
tSCSH Chip Select Hold Time 0.5 — ns
Master SPI
fCCLK MCK Output Clock Frequency — 26.4 MHz
I2C 2
fMAX Maximum SCL Clock Frequency (Fast-Mode Plus) — 1 MHz
Notes:
1. Refer to CrossLinkPlus Programming and Configuration Usage Guide (FPGA-TN-02103), for timing requirements to enable
CrossLinkPlus SSPI Mode.
2. Refer to the I2C specification for timing requirements when configuring with I2C port.
3. tPRGM minimum time does not apply when SLAVE_SPI_PORT, MASTER_SPI_PORT and I2C_PORT are disabled through Diamond
Software. Contact your Lattice Sales Representatives for details.

4.19. SRAM Configuration Time from internal Flash

Over recommended operating conditions.
Table 4.21. SRAM Configuration Time from internal Flash
Symbol Parameter Typ Unit
TCONFIGURATION * 5 ms
POR/CRESET_B to Device I/O Active
*Note: Before and during configuration, the I/O are held in tristate with weak internal pull-ups enabled. I/O are released to user
functionality when the device has finished configuration.

4.20. Flash Programming/Erase Specifications

Over recommended operating conditions.
Table 4.22. Flash Programming/Erase Specifications
Symbol Parameter Min Max1 Unit
Flash programming cycles per TRETENTION — TBD
NPROGCYC Cycles
Flash Write/Erase cycles2 — TBD
Data retention at 100 ⁰C junction temperature 10 —
TRETENTION Years
Data retention at 85 ⁰C junction temperature 20 —
Notes:
1. Maximum Flash memory reads are limited to TBD cycles over the lifetime of the product.
2. A Write/Erase cycle is defined as any number of writes over time followed by any erase cycle.

44 FPGA-DS-02054-0.92
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Preliminary Data Sheet

4.21. Switching Test Conditions

Figure 4.6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are listed in Table 4.23.

R1
DUT Test Point

R2 CL*

*CL Includes Test Fixture and Probe Capacitance

Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards

Table 4.23. Test Fixture Required Components, Non-Terminated Interfaces*

Test Condition R1 R2 CL Timing Ref. VT
LVCMOS 3.3 = 1.5 V —
LVCMOS 2.5 = VCCIO/2 —
LVTTL and other LVCMOS settings (L ≥ H, H ≥ L) ∞ ∞ 0 pF
LVCMOS 1.8 = VCCIO/2 —
LVCMOS 1.2 = VCCIO/2 —
LVCMOS 2.5 I/O (Z ≥ H) ∞ 1 MΩ 0 pF VCCIO/2 —
LVCMOS 2.5 I/O (Z ≥ L) 1 MΩ ∞ 0 pF VCCIO/2 VCCIO
LVCMOS 2.5 I/O (H ≥ Z) ∞ 100 0 pF VOH – 0.10 —
LVCMOS 2.5 I/O (L ≥ Z) 100 ∞ 0 pF VOL + 0.10 VCCIO
*Note: Output test conditions for all other interfaces are determined by the respective standards.

FPGA-DS-02054-0.92 45
CrossLinkPlus Family
Preliminary Data Sheet

5. Signal Descriptions

5.1. Dual Function Pin Descriptions

The following table describes the dual functions available to certain pins on the CrossLinkPlus device. These pins may
alternatively be used as general purpose I/O when the described dual function is not enabled.
Table 5.1. Dual Function Pin Descriptions
Signal Name I/O Description
General Purpose
USER_SCL I/O User Slave I2C0 clock input and Master I2C0 clock output. Enables PMU
wake-up via I2C0.
USER_SDA I/O User Slave I2C0 data input and Master I2C0 data output. Enables PMU
wakeup via I2C0.
PMU_WKUPN — This pin wakes the PMU from sleep mode when toggled low.
Clock Functions
GPLL2_0[T, C]_IN I General Purpose PLL (GPLL) input pads: T = true and C = complement. These
pins can be used to input a reference clock directly to the General Purpose
PLL. These pins do not provide direct access to the primary clock network.
GR_PCLK[Bank]0 I These pins provide a short General Routing path to the primary clock
network, but should only be used when the design has used up all the PCLK
pins. These pins should only be used for low speed clocks that are not
sensitive to skew. Refer to CrossLinkPlus sysCLOCK PLL/DLL Design and
Usage Guide (FPGA-TN-02109) for details.
PCLK[T/C][Bank]_[num] I/O General Purpose Primary CLK pads: [T/C] = True/Complement, [Bank] = (0, 1
and 2). These pins provide direct access to the primary and edge clock
networks.
MIPI_CLK[T/C][Bank]_0 I/O MIPI D-PHY Reference CLK pads: [T/C] = True/Complement, [Bank] = (0, 1
and 2). These pins can be used to input a reference clock directly to the
D-PHY PLLs. These pins do not provide direct access to the primary clock
network.
Configuration
CDONE I/O Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress. Holding CDONE delays configuration.
SPI_SCK I Input Configuration Clock for configuring CrossLinkPlus in Slave SPI mode
(SSPI).
MCK O Output Configuration Clock for configuring CrossLinkPlus in Master SPI mode
(MSPI).
SPI_SS I Input Chip Select for configuring CrossLinkPlus in Slave SPI mode (SSPI).
CSN O Output Chip Select for configuring CrossLinkPlus in Master SPI mode (MSPI).
MOSI I/O Data Output when configuring CrossLinkPlus in Master SPI mode (MSPI),
data input when configuring CrossLinkPlus in Slave SPI mode (SSPI).
MISO I/O Data Input when configuring CrossLinkPlus in Master SPI mode (MSPI), data
output when configuring CrossLinkPlus in Slave SPI mode (SSPI).
SCL I/O Slave I2C clock I/O when configuring CrossLinkPlus in I2C mode.
SDA I/O Slave I2C data I/O when configuring CrossLinkPlus in I2C mode.

46 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

5.2. Dedicated Function Pin Descriptions

Table 5.2. Dedicated Function Pin Descriptions
Signal Name I/O Description
Configuration
CRESET_B I Configuration Reset, active LOW.
MIPI D-PHY
DPHY[num]_CK[P/N] I/O MIPI D-PHY Clock [num] = D-PHY 0 or 1, P = Positive, N = Negative.
DPHY[num]_D[P/N][lane] I/O MIPI D-PHY Data [num] = D-PHY 0 or 1, P = Positive, N = Negative,
Lane = data lane in the D-PHY block 0, 1, 2 or 3.

5.3. Pin Information Summary

Table 5.3. Pin Information Summary
CrossLinkPlus
Pin Type
ucfBGA64 ckfBGA80
Total General Purpose I/O 29 37
VCC/VCCIOx/VCCAUX/VCCGPLL 8 9
GND 3 6
D-PHY Clock/Data 20 20
D-PHY VCC 2 4
D-PHY GND 1 3
CRESET_B 1 1
Total Balls 64 80
Bank 0 7 7
Bank 1 10 14
Bank 2 12 16
Total General Purpose Single Ended I/O 29 37
Bank 0 0 0
Bank 1 5 7
Bank 2 6 8
Total General Purpose Differential I/O Pairs 11 15

FPGA-DS-02054-0.92 47
CrossLinkPlus Family
Preliminary Data Sheet

6. CrossLinkPlus Part Number Description

LIF-MD F XXXX - X XXXXX X TR

Device Family
Tape & Reel
CrossLinkPlus FPGA
< blank >= No Tape & Reel
TR = Tape & Reel
Logic Capacity
6000 = 6000 LUTs Grade
I = Industrial
Speed Package
6 = Fastest UMG 64 = 64- ball uc fBGA
KMG 80 = 80- ball ckfBGA

6.1. Ordering Part Numbers

Industrial
Part Number Grade Package Pins Temp. LUTs (K)
LIF-MDF6000-6UMG64I –6 Lead free ucfBGA 64 Industrial 5.9
LIF-MDF6000-6KMG80I –6 Lead free ckfBGA 80 Industrial 5.9

48 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

References
For more information, refer to the following technical notes:
 CrossLinkPlus High-Speed I/O Interface (FPGA-TN-02102)
 CrossLinkPlus Hardware Checklist (FPGA-TN-02105)
 CrossLinkPlus Programming and Configuration Usage Guide (FPGA-TN-02103)
 CrossLinkPlus sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN-02109)
 CrossLinkPlus sysI/O Usage Guide (FPGA-TN-02108)
 CrossLinkPlus Memory Usage Guide (FPGA-TN-02110)
 Power Management and Calculation for CrossLinkPlus Devices (FPGA-TN-02111)
 CrossLinkPlus I2C Hardened IP Usage Guide (FPGA-TN-02112)
 Advanced CrossLinkPlus I2C Hardened IP Reference Guide (FPGA-TN-02135)
For package information, refer to the following technical notes:
 PCB Layout Recommendations for BGA Packages (FPGA-TN-02024)
 Solder Reflow Guide for Surface Mount Devices (FPGA-TN-02041)
 Wafer-Level Chip-Scale Package Guide (TN1242)
 Thermal Management (FPGA-TN-02044)
 Package Diagrams (FPGA-DS-02053)
For further information on interface standards refer to the following websites:
 JEDEC Standards (LVTTL, LVCMOS): www.jedec.org
 MIPI Standards (D-PHY): www.mipi.org

FPGA-DS-02054-0.92 49
CrossLinkPlus Family
Preliminary Data Sheet

Technical Support
For assistance, submit a technical support case at www.latticesemi.com/techsupport.

50 FPGA-DS-02054-0.92
CrossLinkPlus Family
Preliminary Data Sheet

Revision History
Revision 0.92, March 2021
Section Change Summary
General Description  Added 80-ball ckfBGA (49 mm2) under Ultra small footprint packages in
the Features section.
 Added 80-ball ckfBGA in Table 2.1. CrossLinkPlus Feature Summary.
Signal Descriptions Added 80-ball ckfBGA in Table 5.3. Pin Information Summary.
CrossLinkPlus Part Number Added LIF-MDF6000-6KMG80I in Ordering Part Numbers.
Description

Revision 0.91, January 2020

Section Change Summary
Acronyms in This Document Added/revised acronyms and descriptions.
Architecture Overview  In the section introduction, mentioned internal Flash as key system
resource.
 In the Programming and Configuration sub-section, updated information
on CRESET_B pin and Dual Boot Support.
DC and Switching  Updated VCCAUX information in and removed footnote from Table 4.1.
Characteristics Absolute Maximum Ratings.
 Removed footnote from Table 4.2. Recommended Operating Conditions.
 Updated values in Table 4.4. Power-On-Reset Voltage Levels.
 Updated footnote 7 in Table 4.12. CrossLinkPlus Maximum I/O Buffer
Speed.
— Minor formatting and editorial changes.

Revision 0.90, September 2019

Section Change Summary
All Preliminary release.

FPGA-DS-02054-0.92 51
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