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FPGA DS 02049 2 1 CrossLink NX Family

The CrossLink-NX Family Data Sheet provides detailed information about Lattice Semiconductor's FPGA products, including architecture, features, and electrical characteristics. It includes disclaimers regarding the accuracy and suitability of the products for high-risk applications, emphasizing that buyers must independently verify product suitability. The document also outlines the structure of the data sheet, covering various technical specifications and ordering information.

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20 views172 pages

FPGA DS 02049 2 1 CrossLink NX Family

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CrossLink-NX Family

Data Sheet

FPGA-DS-02049-2.1

September 2024
CrossLink-NX Family
Data Sheet

Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS, with all faults, and all associated risk is the responsibility entirely of the
Buyer. The information provided herein is for informational purposes only and may contain technical inaccuracies or omissions, and may be otherwise
rendered inaccurate for many reasons, and Lattice assumes no obligation to update or otherwise correct or revise this information. Products sold by
Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test
and verify the same. LATTICE PRODUCTS AND SERVICES ARE NOT DESIGNED, MANUFACTURED, OR TESTED FOR USE IN LIFE OR SAFETY CRITICAL
SYSTEMS, HAZARDOUS ENVIRONMENTS, OR ANY OTHER ENVIRONMENTS REQUIRING FAIL-SAFE PERFORMANCE, INCLUDING ANY APPLICATION IN
WHICH THE FAILURE OF THE PRODUCT OR SERVICE COULD LEAD TO DEATH, PERSONAL INJURY, SEVERE PROPERTY DAMAGE OR ENVIRONMENTAL
HARM (COLLECTIVELY, "HIGH-RISK USES"). FURTHER, BUYER MUST TAKE PRUDENT STEPS TO PROTECT AGAINST PRODUCT AND SERVICE FAILURES,
INCLUDING PROVIDING APPROPRIATE REDUNDANCIES, FAIL-SAFE FEATURES, AND/OR SHUT-DOWN MECHANISMS. LATTICE EXPRESSLY DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY OF FITNESS OF THE PRODUCTS OR SERVICES FOR HIGH-RISK USES. The information provided in this document
is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.

Inclusive Language
This document was created consistent with Lattice Semiconductor’s inclusive language policy. In some cases, the language in underlying tools and
other items may not yet have been updated. Please refer to Lattice’s inclusive language FAQ 6878 for a cross reference of terms. Note in some cases
such as register names and state names it has been necessary to continue to utilize older terminology for compatibility.

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

2 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Contents
Contents ............................................................................................................................................................................... 3
Figures .................................................................................................................................................................................. 6
Tables .................................................................................................................................................................................... 8
Abbreviations in This Document......................................................................................................................................... 11
1. General Description .................................................................................................................................................... 13
1.1. Features ............................................................................................................................................................ 13
2. Architecture ................................................................................................................................................................ 17
2.1. Overview ........................................................................................................................................................... 17
2.2. PFU Blocks ......................................................................................................................................................... 19
2.2.1. Slice .......................................................................................................................................................... 19
2.2.2. Modes of Operation ................................................................................................................................. 22
2.3. Routing .............................................................................................................................................................. 23
2.4. Clocking Structure ............................................................................................................................................. 23
2.4.1. Global PLL ................................................................................................................................................. 23
2.4.2. Clock Distribution Network ...................................................................................................................... 24
2.4.3. Primary Clocks .......................................................................................................................................... 25
2.4.4. Edge Clock ................................................................................................................................................ 26
2.4.5. Clock Dividers ........................................................................................................................................... 26
2.4.6. Clock Center Multiplexer Blocks ............................................................................................................... 27
2.4.7. Dynamic Clock Select ................................................................................................................................ 27
2.4.8. Dynamic Clock Control ............................................................................................................................. 28
2.4.9. DDRDLL ..................................................................................................................................................... 28
2.5. SGMII Tx/Rx ....................................................................................................................................................... 29
2.6. sysMEM Memory .............................................................................................................................................. 30
2.6.1. sysMEM Memory Block ............................................................................................................................ 30
2.6.2. Bus Size Matching ..................................................................................................................................... 31
2.6.3. RAM Initialization and ROM Operation .................................................................................................... 31
2.6.4. Memory Cascading ................................................................................................................................... 31
2.6.5. Single, Dual and Pseudo-Dual Port Modes ............................................................................................... 31
2.6.6. Memory Output Reset .............................................................................................................................. 31
2.7. Large RAM ......................................................................................................................................................... 32
2.8. sysDSP ............................................................................................................................................................... 32
2.8.1. sysDSP Approach Compared to General DSP ........................................................................................... 32
2.8.2. sysDSP Architecture Features ................................................................................................................... 33
2.9. Programmable I/O (PIO).................................................................................................................................... 35
2.10. Programmable I/O Cell (PIC) ............................................................................................................................. 35
2.10.1. Input Register Block .................................................................................................................................. 37
2.10.2. Output Register Block ............................................................................................................................... 38
2.11. Tri-state Register Block ..................................................................................................................................... 39
2.12. DDR Memory Support ....................................................................................................................................... 40
2.12.1. DQS Grouping for DDR Memory ............................................................................................................... 40
2.12.2. DLL Calibrated DQS Delay and Control Block (DQSBUF)........................................................................... 41
2.13. sysI/O Buffer ..................................................................................................................................................... 43
2.13.1. Supported sysI/O Standards ..................................................................................................................... 43
2.13.2. sysI/O Banking Scheme ............................................................................................................................ 44
2.13.3. sysI/O Buffer Configurations .................................................................................................................... 47
2.14. Analog Interface ................................................................................................................................................ 47
2.14.1. Analog to Digital Converters..................................................................................................................... 47
2.14.2. Continuous Time Comparators................................................................................................................. 47
2.14.3. Internal Junction Temperature Monitoring Diode ................................................................................... 47
2.15. IEEE 1149.1-Compliant Boundary Scan Testability ........................................................................................... 47
2.16. Device Configuration ......................................................................................................................................... 48

FPGA-DS-02049-2.1 3
CrossLink-NX Family
Data Sheet

2.16.1. Enhanced Configuration Options..............................................................................................................48

2.17. Single Event Upset (SEU) Handling ....................................................................................................................49
2.18. On-Chip Oscillator .............................................................................................................................................49
2.19. User I2C IP .........................................................................................................................................................49
2.20. Trace ID .............................................................................................................................................................50
2.21. Density Shifting .................................................................................................................................................50
2.22. MIPI D-PHY Blocks .............................................................................................................................................50
2.23. Peripheral Component Interconnect Express (PCIe) .........................................................................................51
2.24. Cryptographic Engine ........................................................................................................................................52
3. DC and Switching Characteristics for Commercial and Industrial ...............................................................................53
3.1. Absolute Maximum Ratings ..............................................................................................................................53
3.2. Recommended Operating Conditions1, 2, 3.........................................................................................................54
3.3. Power Supply Ramp Rates .................................................................................................................................55
3.4. Power up Sequence ...........................................................................................................................................55
3.5. On-Chip Programmable Termination ................................................................................................................55
3.6. Hot Socketing Specifications .............................................................................................................................56
3.7. ESD Performance ...............................................................................................................................................56
3.8. DC Electrical Characteristics ..............................................................................................................................57
3.9. Supply Currents .................................................................................................................................................58
3.10. sysI/O Recommended Operating Conditions ....................................................................................................59
3.11. sysI/O Single-Ended DC Electrical Characteristics .............................................................................................60
3.12. sysI/O Differential DC Electrical Characteristics ................................................................................................62
3.12.1. LVDS ..........................................................................................................................................................62
3.12.2. LVDS25E (Output Only) .............................................................................................................................63
3.12.3. SubLVDS (Input Only)................................................................................................................................64
3.12.4. SubLVDSE/SubLVDSEH (Output Only) ......................................................................................................64
3.12.5. SLVS ..........................................................................................................................................................65
3.12.6. Soft MIPI D-PHY ........................................................................................................................................66
3.12.7. Differential HSTL15D (Output Only) .........................................................................................................70
3.12.8. Differential SSTL135D, SSTL15D (Output Only) ........................................................................................70
3.12.9. Differential HSUL12D (Output Only) .........................................................................................................70
3.12.10. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only) ...........................................................70
3.13. Maximum sysI/O Buffer Speed..........................................................................................................................70
3.14. Typical Building Block Function Performance ...................................................................................................72
3.15. LMMI .................................................................................................................................................................73
3.16. Derating Timing Tables ......................................................................................................................................74
3.17. External Switching Characteristics ....................................................................................................................74
3.18. sysCLOCK PLL Timing (VCC = 1.0 V) – Commercial/Industrial .............................................................................82
3.19. Internal Oscillators Characteristics ....................................................................................................................83
3.20. User I2C Characteristics.....................................................................................................................................84
3.21. Analog-Digital Converter (ADC) Block Characteristics .......................................................................................84
3.22. Comparator Block Characteristics .....................................................................................................................85
3.23. Digital Temperature Readout Characteristics ...................................................................................................85
3.24. Hardened MIPI D-PHY Characteristics ...............................................................................................................86
3.25. Hardened PCIe Characteristics ..........................................................................................................................89
3.25.1. PCIe (2.5 Gbps) .........................................................................................................................................89
3.25.2. PCIe (5 Gbps) ............................................................................................................................................90
3.26. SGMII Characteristics ........................................................................................................................................92
3.26.1. SGMII Specifications .................................................................................................................................92
3.27. sysCONFIG Port Timing Specifications ..............................................................................................................92
3.28. JTAG Port Timing Specifications ........................................................................................................................99
3.29. Switching Test Conditions ...............................................................................................................................100
4. DC and Switching Characteristics for Automotive ....................................................................................................101
4.1. Absolute Maximum Ratings ............................................................................................................................101

4 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

4.2. Recommended Operating Conditions1, 2, 3 ...................................................................................................... 102

4.3. Power Supply Ramp Rates .............................................................................................................................. 103
4.4. Power up Sequence ........................................................................................................................................ 103
4.5. On-Chip Programmable Termination .............................................................................................................. 103
4.6. Hot Socketing Specifications ........................................................................................................................... 104
4.7. ESD Performance ............................................................................................................................................ 104
4.8. DC Electrical Characteristics ............................................................................................................................ 105
4.9. Supply Currents ............................................................................................................................................... 106
4.10. sysI/O Recommended Operating Conditions .................................................................................................. 107
4.11. sysI/O Single-Ended DC Electrical Characteristics3 .......................................................................................... 108
4.12. sysI/O Differential DC Electrical Characteristics .............................................................................................. 110
4.12.1. LVDS........................................................................................................................................................ 110
4.12.2. LVDS25E (Output Only) .......................................................................................................................... 111
4.12.3. SubLVDS (Input Only) ............................................................................................................................. 111
4.12.4. SubLVDSE/SubLVDSEH (Output Only) .................................................................................................... 112
4.12.5. SLVS ........................................................................................................................................................ 113
4.12.6. Soft MIPI D-PHY ...................................................................................................................................... 114
4.12.7. Differential HSTL15D (Output Only) ....................................................................................................... 117
4.12.8. Differential SSTL135D, SSTL15D (Output Only) ...................................................................................... 117
4.12.9. Differential HSUL12D (Output Only) ...................................................................................................... 117
4.12.10. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only) ......................................................... 117
4.13. Maximum sysI/O Buffer Speed ....................................................................................................................... 118
4.14. Typical Building Block Function Performance ................................................................................................. 120
4.15. LMMI ............................................................................................................................................................... 121
4.16. Derating Timing Tables.................................................................................................................................... 121
4.17. External Switching Characteristics .................................................................................................................. 122
4.18. sysCLOCK PLL Timing (VCC = 1.0 V) – Automotive ............................................................................................ 130
4.19. Internal Oscillators Characteristics.................................................................................................................. 131
4.20. User I2C Characteristics .................................................................................................................................. 131
4.21. Analog-Digital Converter (ADC) Block Characteristics..................................................................................... 132
4.22. Comparator Block Characteristics ................................................................................................................... 133
4.23. Digital Temperature Readout Characteristics ................................................................................................. 133
4.24. Hardened MIPI D-PHY Characteristics............................................................................................................. 133
4.25. Hardened PCIe Characteristics ........................................................................................................................ 137
4.25.1. PCIe (2.5 Gbps) ....................................................................................................................................... 137
4.25.2. PCIe (5 Gbps) .......................................................................................................................................... 138
4.26. Hardened SGMII Characteristics ..................................................................................................................... 140
4.26.1. SGMII Specifications ............................................................................................................................... 140
4.27. sysCONFIG Port Timing Specifications ............................................................................................................ 140
4.28. JTAG Port Timing Specifications ...................................................................................................................... 147
4.29. Switching Test Conditions ............................................................................................................................... 148
5. Pinout Information ................................................................................................................................................... 149
5.1. Signal Descriptions .......................................................................................................................................... 149
5.2. Pin Information Summary ............................................................................................................................... 155
5.2.1. CrossLink-NX Family ............................................................................................................................... 155
6. Ordering Information ............................................................................................................................................... 158
6.1. Part Number Description ................................................................................................................................ 158
6.2. Ordering Part Numbers ................................................................................................................................... 159
6.2.1. Commercial ............................................................................................................................................ 159
6.2.2. Industrial................................................................................................................................................. 159
6.2.3. Automotive ............................................................................................................................................. 160
References ........................................................................................................................................................................ 161
Technical Support Assistance ........................................................................................................................................... 162
Revision History ................................................................................................................................................................ 163

FPGA-DS-02049-2.1 5
CrossLink-NX Family
Data Sheet

Figures
Figure 2.1. Simplified Block Diagram, CrossLink-NX-40 Device (Top Level) ........................................................................18
Figure 2.2. Simplified Block Diagram, CrossLink-NX-17 Device (Top Level) ........................................................................18
Figure 2.3. PFU Diagram .....................................................................................................................................................19
Figure 2.4. Slice Diagram ....................................................................................................................................................20
Figure 2.5. Slice Configuration for LUT4 and LUT5 .............................................................................................................21
Figure 2.6. General Purpose PLL Diagram ...........................................................................................................................24
Figure 2.7. Clocking .............................................................................................................................................................25
Figure 2.8. Edge Clock Sources per Bank ............................................................................................................................26
Figure 2.9. DCS_CMUX Diagram .........................................................................................................................................27
Figure 2.10. DCS Waveforms ..............................................................................................................................................28
Figure 2.11. DLLDEL Functional Diagram ............................................................................................................................29
Figure 2.12. DDRDLL Architecture ......................................................................................................................................29
Figure 2.13. SGMII CDR IP ...................................................................................................................................................30
Figure 2.14. Memory Core Reset ........................................................................................................................................32
Figure 2.15. Comparison of General DSP and CrossLink-NX Approaches ...........................................................................33
Figure 2.16. DSP Functional Block Diagram ........................................................................................................................34
Figure 2.17. Group of Two High Performance Programmable I/O Cells .............................................................................36
Figure 2.18. Wide Range Programmable I/O Cells ..............................................................................................................36
Figure 2.19. Input Register Block for PIO on Top, Left, and Right Sides of the Device .......................................................37
Figure 2.20. Input Register Block for PIO on Bottom Side of the Device ............................................................................38
Figure 2.21. Output Register Block on Top, Left, and Right Sides ......................................................................................38
Figure 2.22. Output Register Block on Bottom Side ...........................................................................................................39
Figure 2.23. Tri-state Register Block on Top, Left, and Right Sides.....................................................................................39
Figure 2.24. Tri-state Register Block on Bottom Side .........................................................................................................40
Figure 2.25. DQS Grouping on the Bottom Edge ................................................................................................................41
Figure 2.26. DQS Control and Delay Block (DQSBUF) .........................................................................................................42
Figure 2.27. sysI/O Banking ................................................................................................................................................45
Figure 2.28. PCIe Core .........................................................................................................................................................51
Figure 2.29. PCIe Soft IP Wrapper.......................................................................................................................................52
Figure 2.30. Cryptographic Engine Block Diagram ..............................................................................................................52
Figure 3.1. On-Chip Termination ........................................................................................................................................55
Figure 3.2. LVDS25E Output Termination Example ............................................................................................................64
Figure 3.3. SubLVDS Input Interface ...................................................................................................................................64
Figure 3.4. SubLVDS Output Interface ................................................................................................................................65
Figure 3.5. SLVS Interface ...................................................................................................................................................66
Figure 3.6. MIPI Interface ...................................................................................................................................................67
Figure 3.7. Receiver RX.CLK.Centered Waveforms .............................................................................................................80
Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms .........................................................................80
Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ...................................................................80
Figure 3.10. Transmit TX.CLK.Aligned Waveforms ..............................................................................................................81
Figure 3.11. DDRX71 Video Timing Waveforms ..................................................................................................................81
Figure 3.12. Receiver DDRX71_RX Waveforms ...................................................................................................................82
Figure 3.13. Transmitter DDRX71_TX Waveforms ..............................................................................................................82
Figure 3.14. Controller SPI POR/REFRESH Timing ...............................................................................................................95
Figure 3.15. Target SPI/I2C/I3C POR/REFRESH Timing .......................................................................................................95
Figure 3.16. Controller SPI PROGRAMN Timing ..................................................................................................................96
Figure 3.17. Target SPI/I2C/I3C PROGRAMN Timing ..........................................................................................................96
Figure 3.18. Controller SPI Configuration Timing ...............................................................................................................97
Figure 3.19. Target SPI Configuration Timing .....................................................................................................................97
Figure 3.20. I2C /I3C Configuration Timing .........................................................................................................................97
Figure 3.21. Controller SPI Wake-Up Timing ......................................................................................................................98
Figure 3.22. Target SPI/I2C/I3C Wake-Up Timing ...............................................................................................................98

6 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Figure 3.23. Configuration Error Notification ..................................................................................................................... 98

Figure 3.24. JTAG Port Timing Waveforms ......................................................................................................................... 99
Figure 3.25. Output Test Load, LVTTL and LVCMOS Standards ........................................................................................ 100
Figure 4.1. On-Chip Termination ...................................................................................................................................... 103
Figure 4.2. LVDS25E Output Termination Example .......................................................................................................... 111
Figure 4.3. SubLVDS Input Interface ................................................................................................................................. 112
Figure 4.4. SubLVDS Output Interface .............................................................................................................................. 113
Figure 4.5. SLVS Interface ................................................................................................................................................. 114
Figure 4.6. MIPI Interface ................................................................................................................................................. 115
Figure 4.7. Receiver RX.CLK.Centered Waveforms ........................................................................................................... 127
Figure 4.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms ....................................................................... 128
Figure 4.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ................................................................. 128
Figure 4.10. Transmit TX.CLK.Aligned Waveforms ........................................................................................................... 128
Figure 4.11. DDRX71 Video Timing Waveforms ............................................................................................................... 129
Figure 4.12. Receiver DDRX71_RX Waveforms ................................................................................................................ 129
Figure 4.13. Transmitter DDRX71_TX Waveforms ............................................................................................................ 130
Figure 4.14. Controller SPI POR/REFRESH Timing ............................................................................................................. 142
Figure 4.15. Target SPI/I2C/I3C POR/REFRESH Timing ..................................................................................................... 143
Figure 4.16. Controller SPI PROGRAMN Timing ................................................................................................................ 143
Figure 4.17. Target SPI/I2C/I3C PROGRAMN Timing ........................................................................................................ 144
Figure 4.18. Controller SPI Configuration Timing ............................................................................................................. 144
Figure 4.19. Target SPI Configuration Timing ................................................................................................................... 145
Figure 4.20. I2C /I3C Configuration Timing ....................................................................................................................... 145
Figure 4.21. Controller SPI Wake-Up Timing .................................................................................................................... 146
Figure 4.22. Target SPI/I2C/I3C Wake-Up Timing ............................................................................................................. 146
Figure 4.23. Configuration Error Notification ................................................................................................................... 146
Figure 4.24. JTAG Port Timing Waveforms ....................................................................................................................... 147
Figure 4.25. Output Test Load, LVTTL and LVCMOS Standards ........................................................................................ 148

FPGA-DS-02049-2.1 7
CrossLink-NX Family
Data Sheet

Tables
Table 1.1. CrossLink-NX Commercial/Industrial Family Selection Guide ............................................................................15
Table 1.2. CrossLink-NX Automotive Family Selection Guide .............................................................................................15
Table 2.1. Resources and Modes Available per Slice ..........................................................................................................19
Table 2.2. Slice Signal Descriptions .....................................................................................................................................21
Table 2.3. Number of Slices Required to Implement Distributed RAM ..............................................................................22
Table 2.4. sysMEM Block Configurations ............................................................................................................................31
Table 2.5. Maximum Number of Elements in a sysDSP block .............................................................................................35
Table 2.6. Input Block Port Description ..............................................................................................................................37
Table 2.7. Output Block Port Description ...........................................................................................................................39
Table 2.8. Tri-state Block Port Description .........................................................................................................................40
Table 2.9. DQSBUF Port List Description .............................................................................................................................42
Table 2.10. Single-Ended I/O Standards .............................................................................................................................43
Table 2.11. Differential I/O Standards ................................................................................................................................44
Table 2.12. Single-Ended I/O Standards Supported on Various Sides ................................................................................46
Table 2.13. Differential I/O Standards Supported on Various Sides ...................................................................................46
Table 3.1. Absolute Maximum Ratings ...............................................................................................................................53
Table 3.2. Recommended Operating Conditions ................................................................................................................54
Table 3.3. Power Supply Ramp Rates .................................................................................................................................55
Table 3.4. Power-On Reset .................................................................................................................................................55
Table 3.5. On-Chip Termination Options for Input Modes .................................................................................................56
Table 3.6. Hot Socketing Specifications for GPIO ...............................................................................................................56
Table 3.7. DC Electrical Characteristics – Wide Range ........................................................................................................57
Table 3.8. DC Electrical Characteristics – High Speed .........................................................................................................57
Table 3.9. Capacitors – Wide Range ...................................................................................................................................57
Table 3.10. Capacitors – High Performance ........................................................................................................................58
Table 3.11. Single Ended Input Hysteresis – Wide Range ...................................................................................................58
Table 3.12. Single Ended Input Hysteresis – High Performance .........................................................................................58
Table 3.13. sysI/O Recommended Operating Conditions ...................................................................................................59
Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O .....................................................................................60
Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O ...........................................................................61
Table 3.16. I/O Resistance Characteristics ..........................................................................................................................61
Table 3.17. VIN Maximum Overshoot/Undershoot Allowance – Wide Range1, 2 ................................................................62
Table 3.18. VIN Maximum Overshoot/Undershoot Allowance – High Performance1, 2 .......................................................62
Table 3.19. LVDS DC Electrical Characteristics1 ..................................................................................................................63
Table 3.20. LVDS25E DC Conditions ....................................................................................................................................63
Table 3.21. SubLVDS Input DC Electrical Characteristics ....................................................................................................64
Table 3.22. SubLVDS Output DC Electrical Characteristics .................................................................................................65
Table 3.23. SLVS Input DC Characteristics ..........................................................................................................................65
Table 3.24. SLVS Output DC Characteristics .......................................................................................................................65
Table 3.25. Soft D-PHY Input Timing and Levels .................................................................................................................68
Table 3.26. Soft D-PHY Output Timing and Levels ..............................................................................................................68
Table 3.27. Soft D-PHY Clock Signal Specification ...............................................................................................................69
Table 3.28. Soft D-PHY Data-Clock Timing Specifications ...................................................................................................69
Table 3.29. Maximum I/O Buffer Speed 1, 2, 3, 4, 7 ..................................................................................................................70
Table 3.30. Pin-to-Pin Performance ....................................................................................................................................72
Table 3.31. Register-to-Register Performance....................................................................................................................73
Table 3.32. LMMI FMAX Summary ........................................................................................................................................73
Table 3.33. External Switching Characteristics (VCC = 1.0 V) ...............................................................................................74
Table 3.34. sysCLOCK PLL Timing (VCC = 1.0 V) – Commercial/Industrial ............................................................................82
Table 3.35. Internal Oscillators (VCC = 1.0 V) .......................................................................................................................83
Table 3.36. User I2C Specifications (VCC = 1.0 V) .................................................................................................................84
Table 3.37. ADC Specifications1 ..........................................................................................................................................84

8 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Table 3.38. Comparator Specifications1.............................................................................................................................. 85

Table 3.39. DTR Specifications1, 2 ........................................................................................................................................ 85
Table 3.40. Hardened D-PHY Input Timing and Levels ....................................................................................................... 86
Table 3.41. Hardened D-PHY Output Timing and Levels .................................................................................................... 87
Table 3.42. Hardened D-PHY Pin Characteristic Specifications .......................................................................................... 88
Table 3.43. Hardened D-PHY Clock Signal Specification ..................................................................................................... 88
Table 3.44. Hardened D-PHY Data-Clock Timing Specifications ......................................................................................... 88
Table 3.45. PCIe (2.5 Gbps) ................................................................................................................................................. 89
Table 3.46. PCIe (5 Gbps) .................................................................................................................................................... 90
Table 3.47. SGMII................................................................................................................................................................ 92
Table 3.48. sysCONFIG Port Timing Specifications ............................................................................................................. 92
Table 3.49. JTAG Port Timing Specifications ....................................................................................................................... 99
Table 3.50. Test Fixture Required Components, Non-Terminated Interfaces .................................................................. 100
Table 4.1. Absolute Maximum Ratings ............................................................................................................................. 101
Table 4.2. Recommended Operating Conditions .............................................................................................................. 102
Table 4.3. Power Supply Ramp Rates ............................................................................................................................... 103
Table 4.4. Power-On Reset ............................................................................................................................................... 103
Table 4.5. On-Chip Termination Options for Input Modes ............................................................................................... 104
Table 4.6. Hot Socketing Specifications for GPIO ............................................................................................................. 104
Table 4.7. DC Electrical Characteristics – Wide Range...................................................................................................... 105
Table 4.8. DC Electrical Characteristics – High Speed ....................................................................................................... 105
Table 4.9. Capacitors – Wide Range ................................................................................................................................. 105
Table 4.10. Capacitors – High Performance ..................................................................................................................... 106
Table 4.11. Single Ended Input Hysteresis – Wide Range ................................................................................................. 106
Table 4.12. Single Ended Input Hysteresis – High Performance ....................................................................................... 106
Table 4.13. sysI/O Recommended Operating Conditions ................................................................................................. 107
Table 4.14. sysI/O DC Electrical Characteristics – Wide Range I/O .................................................................................. 108
Table 4.15. sysI/O DC Electrical Characteristics – High Performance I/O3 ....................................................................... 109
Table 4.16. I/O Resistance Characteristics ........................................................................................................................ 109
Table 4.17. VIN Maximum Overshoot/Undershoot Allowance – Wide Range1, 2 .............................................................. 110
Table 4.18. VIN Maximum Overshoot/Undershoot Allowance – High Performance1, 2..................................................... 110
Table 4.19. LVDS DC Electrical Characteristics1 ................................................................................................................ 110
Table 4.20. LVDS25E DC Conditions.................................................................................................................................. 111
Table 4.21. SubLVDS Input DC Electrical Characteristics .................................................................................................. 112
Table 4.22. SubLVDS Output DC Electrical Characteristics ............................................................................................... 112
Table 4.23. SLVS Input DC Characteristics ........................................................................................................................ 113
Table 4.24. SLVS Output DC Characteristics ..................................................................................................................... 113
Table 4.25. Soft D-PHY Input Timing and Levels ............................................................................................................... 115
Table 4.26. Soft D-PHY Output Timing and Levels ............................................................................................................ 116
Table 4.27. Soft D-PHY Clock Signal Specification ............................................................................................................ 117
Table 4.28. Soft D-PHY Data-Clock Timing Specifications ................................................................................................. 117
Table 4.29. Maximum I/O Buffer Speed 1, 2, 3, 4, 7 ................................................................................................................ 118
Table 4.30. Pin-to-Pin Performance.................................................................................................................................. 120
Table 4.31. Register-to-Register Performance ................................................................................................................. 120
Table 4.32. LMMI FMAX Summary ...................................................................................................................................... 121
Table 4.33. External Switching Characteristics (VCC = 1.0 V) ............................................................................................. 122
Table 4.34. sysCLOCK PLL Timing (VCC = 1.0 V) – Automotive ........................................................................................... 130
Table 4.35. Internal Oscillators (VCC = 1.0 V) ..................................................................................................................... 131
Table 4.36. User I2C Specifications (VCC = 1.0 V) ............................................................................................................... 131
Table 4.37. ADC Specifications3 ........................................................................................................................................ 132
Table 4.38. Comparator Specifications ............................................................................................................................. 133
Table 4.39. DTR Specifications1, 2 ...................................................................................................................................... 133
Table 4.40. Hardened D-PHY Input Timing and Levels ..................................................................................................... 133
Table 4.41. Hardened D-PHY Output Timing and Levels .................................................................................................. 134

FPGA-DS-02049-2.1 9
CrossLink-NX Family
Data Sheet

Table 4.42. Hardened D-PHY Pin Characteristic Specifications ........................................................................................136

Table 4.43. Hardened D-PHY Clock Signal Specification ...................................................................................................136
Table 4.44. Hardened D-PHY Data-Clock Timing Specifications .......................................................................................136
Table 4.45. PCIe (2.5 Gbps) ...............................................................................................................................................137
Table 4.46. PCIe (5 Gbps) ..................................................................................................................................................138
Table 4.47. SGMII ..............................................................................................................................................................140
Table 4.48. sysCONFIG Port Timing Specifications ...........................................................................................................140
Table 4.49. JTAG Port Timing Specifications .....................................................................................................................147
Table 4.50. Test Fixture Required Components, Non-Terminated Interfaces ..................................................................148

10 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Abbreviations in This Document

A list of abbreviations used in this document.
Abbreviation Definition
AES Advanced Encryption Standard
ADC Analog to Digital Converter
BGA Ball Grid Array
CDR Clock and Data Recovery
CRC Cycle Redundancy Code
CSI Camera Serial Interface
DCC Dynamic Clock Control
DCS Dynamic Clock Select
DDR Double Data Rate
DLL Delay Locked Loop
DSI Display Serial Interface
DSP Digital Signal Processing
DTR Digital Temperature Readout
EBR Embedded Block RAM
ECC Error Correction Coding
ECLK Edge Clock
FFT Fast Fourier Transform
FIFO First In First Out
FIR Finite Impulse Response
HFOSC High Frequency Oscillator
HSP High Speed Port
LFOSC Low Frequency Oscillator
LC Logic Cell
LRAM Large RAM
LVCMOS Low-Voltage Complementary Metal Oxide Semiconductor
LVDS Low-Voltage Differential Signaling
LVPECL Low Voltage Positive Emitter Coupled Logic
LVTTL Low Voltage Transistor-Transistor Logic
LUT Look Up Table
MAC Message Authentication Codes
PCI Peripheral Component Interconnect
PCS Physical Coding Sublayer
PCLK Primary Clock
PDPR Pseudo Dual Port RAM
PFU Programmable Functional Unit
PIC Programmable I/O Cells
PLL Phase Locked Loop
POR Power On Reset
SED Soft Error Detection
SER Soft Error Rate
SEU Single Event Upset
SHA Secure Hashing Algorithm
SLVS Scalable Low-Voltage Signaling
SPI Serial Peripheral Interface
SPR Single Port RAM

FPGA-DS-02049-2.1 11
CrossLink-NX Family
Data Sheet

Abbreviation Definition
SRAM Static Random-Access Memory
TAP Test Access Port
TDM Time Division Multiplexing
TLP Transaction Layer Packet
TRNG True Random Number Generator
UCFG User Configuration Space Register Interface

12 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

1. General Description 1.1. Features

• Available in Commercial, Industrial and
The CrossLink™-NX family of low-power FPGAs can be
Automotive temperature grades.
used in a wide range of applications and are optimized
for bridging and processing needs in Embedded Vision • Programmable Architecture
applications – supporting a variety of high bandwidth • 17k to 39k logic cells
sensor and display interfaces, video processing and • 24 to 56 multipliers (18 × 18) in sysDSP™
machine learning inferencing. It is built on the Lattice blocks
Nexus FPGA platform, using low-power 28 nm FD-SOI • 2.5 to 2.9 Mb of embedded memory (EBR,
technology. It combines the extreme flexibility of an LRAM)
FPGA with the low power and high reliability (due to • 36 to 192 programmable sysI/O
extremely low SER) of FD-SOI technology and offers (High Performance and Wide Range I/O)
small footprint package options. • MIPI D-PHY
CrossLink-NX supports a variety of interfaces including • Up to two hardened 4-lane MIPI D-PHY
MIPI D-PHY (CSI-2, DSI), LVDS, SLVS, subLVDS, PCI • Up to eight lanes total
Express (Gen1, Gen2), SGMII (Gigabit Ethernet), and • Transmit or receive
more. • Supports CSI-2, DSI
Processing features of CrossLink-NX include up to 39k • 20 Gbps aggregate bandwidth
Logic Cells, 56 multipliers (18 × 18), 2.9 Mb of • 2.5 Gbps per lane, 10 Gbps per
embedded memory (consisting of EBR and LRAM D-PHY interface
blocks), distributed memory, DRAM interfaces • Additional Soft D-PHY interfaces supported by
(supporting DDR3, DDR3L, and LPDDR2 up to 1066 High Performance (HP) sysI/O
Mbps × 16-bit data width).
• Transmit or receive
CrossLink-NX FPGAs support fast configuration of its • Supports CSI-2, DSI
reconfigurable SRAM-based logic fabric, and ultra-fast • Up to 1.5 Gbps per lane
configuration of its programmable sysI/O™. Security • Programmable sysI/O supports wide variety
features to secure user designs include bitstream of interfaces
encryption and password protection. In addition to the
• High Performance (HP) on bottom I/O
high reliability inherent to FD-SOI technology (due to
dual rank
its extremely low SER), active reliability features such
as built-in frame-based SED/SEC (for SRAM-based logic • Supports up to 1.8 V VCCIO
fabric), and ECC (for EBR and LRAM) are also • Mixed voltage support (1.0 V, 1.2 V, 1.5 V,
supported. Dual 12-bit ADCs are available in each 1.8 V)
device for system monitoring functions. • High-speed differential up to 1.5 Gbps
• Supports soft D-PHY (Tx/Rx), LVDS 7:1
The Lattice Radiant™ design software allows large
(Tx/Rx), SLVS (Tx/Rx), subLVDS (Rx)
complex user designs to be efficiently implemented in
• Supports SGMII (Gb Ethernet)
the CrossLink-NX FPGA family. Synthesis library
Two channels (Tx/Rx) @ 1.25 Gbps
support for CrossLink-NX devices is available for
popular logic synthesis tools. Radiant tools use the • Dedicated DDR3/DDR3L and LPDDR2
synthesis tool output along with constraints from its memory support with DQS logic, up to
floor planning tools to place and route the user design 1066 Mbps data rate and 16-bit data
in the CrossLink-NX device. The tools extract timing width
from the routing and back-annotate it into the design • Wide Range (WR) on Left, Right and Top
for timing verification. I/O Banks
Lattice provides many pre-engineered IP (Intellectual • Supports up to 3.3 V VCCIO
Property) modules for the CrossLink-NX family. By • Mixed voltage support (1.2 V, 1.5 V, 1.8 V,
using these configurable soft IP cores as standardized 2.5 V, 3.3 V)
blocks, users are free to concentrate on the unique • Programmable slew rate (slow, med, fast)
aspects of the design, increasing productivity. • Controlled impedance mode
• Emulated LVDS support
• Hot Socketing Support

FPGA-DS-02049-2.1 13
CrossLink-NX Family
Data Sheet

• Power Modes – Low Power versus High- • Configuration – Fast, Secure

Performance • SPI – x1, x2, x4 up to 150 MHz
• User selectable • Controller and Target SPI support
• Low-Power mode for power and/or thermal • JTAG
challenges • I2C and I3C
• High-Performance mode for faster processing • Ultrafast I/O configuration for instant-on
• Small footprint package options support (under 3 ms)
• 4 mm × 4 mm to 10 mm × 10 mm package • Less than 15 ms full device configuration for
options LIFCl-40
• 2x SGMII CDR at up to 1.25 Gbps – to support 2 • Bitstream Security
channels SGMII using HP I/O • Encryption
• CDR for RX • Authentication
• 10b/8b decoding • Cryptographic engine
• Independent Loss of Lock (LOL) detector for • Bitstream encryption – using AES-256
each CDR block • Bitstream authentication – using ECDSA
• sysCLOCK™ analog PLLs • Hashing algorithms – SHA, HMAC
• Three in 39k LC and two in 17k LC device • True Random Number Generator
• Six outputs per PLL • AES 128/256 Encryption
• Fractional N • Single Event Upset (SEU) Mitigation Support
• Programmable and dynamic phase control • Extremely low Soft Error Rate (SER) due to FD-
• sysDSP Enhanced DSP blocks SOI technology
• Hardened pre-adder • Soft Error Detect – Embedded hard macro
• Dynamic Shift for AI/ML support • Soft Error Correction – Without stopping user
• Four 18 × 18, eight 9 × 9, two 18 × 36, or operation
36 × 36 multipliers • Soft Error Injection – Emulate SEU event to
• Advanced 18 × 36, two 18 × 18, or four 8 × 8 debug system error handling
MAC • Dual ADCs – 1 MSPS, 12-bit SAR with Simultaneous
• Flexible memory resources Sampling1
• Up to 1.5 Mb sysMEM™ Embedded Block RAM • Two ADCs per device
(EBR) • Three Continuous-time Comparators
• Programmable width • Simultaneous Sampling
• ECC* • System Level Support
• Single or dual clock FIFO • IEEE 1149.1 and IEEE 1532 compliant
• 80k to 240k bits distributed RAM • Reveal Logic Analyzer
• Large RAM Blocks • On-chip oscillator for initialization and
• 0.5 Mbits per block general use
• Up to five blocks (2.5 Mb total) per device • 1.0 V core power supply
• SerDes – PCIe Gen2 x1 channel (Tx/Rx) hard IP in Notes:
39k LC device 1. Available in select speed grades. See Ordering
• Hard IP supports Information section.
• Gen1, Gen2, Multi-Function, End Point
• Internal bus interface support
• APB control bus
• AHB-Lite for data bus
• AXI4-streaming

14 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Table 1.1. CrossLink-NX Commercial/Industrial Family Selection Guide

Device LIFCL-17 LIFCL-40
Logic Cells¹ 17k 39k
Embedded Memory (EBR) Blocks (18 kb) 24 84
Embedded Memory (EBR) Bits (kb) 432 1,512
Distributed RAM Bits (kb) 108 252
Large Memory (LRAM) Blocks 5 2
Large Memory (LRAM) Bits (kb) (512 kb each) 2560 1024
18 × 18 Multipliers 24 56
ADC Blocks3 1 1
450 MHz High Frequency Oscillator 1 1
128 kHz Low Power Oscillator 1 1
GPLL 2 3
Hardened 10 Gbps D-PHY Quads² 2 2
Hardened 2.5 Gbps D-PHY Data Lanes (total)² 8 8
PCIe Gen2 Hard IP — 1
Total I/O (Wide Range, High Performance, ADC ) (D-PHY Quads5,
4
Packages (Size, Ball Pitch)
PCIe6 Lane)
72 WLCSP (3.8 mm × 4.1 mm, 0.4 mm) 45 (15, 24, 6) (1, 0) —
72 QFN (10 mm × 10 mm, 0.5 mm) 46 (18, 22, 6) (1, 0) 44 (17, 22, 6) (1, 0)
121 csfBGA (6 mm × 6 mm, 0.5 mm) 77 (23, 48, 6) (2, 0) 77 (23, 48, 6) (2, 0)
256 caBGA (14 mm × 14 mm, 0.8 mm) 77 (23, 48, 6) (2, 0) 162 (82, 74, 6) (2, 1)
289 csBGA (9.5 mm × 9.5 mm, 0.5 mm) — 179 (99, 74, 6) (2, 1)
400 caBGA (17 mm × 17 mm, 0.8 mm) — 191 (111, 74, 6) (2, 1)
Notes:
1. Logic Cells = LUTs × 1.2 effectiveness.
2. Additional soft D-PHY Tx/Rx interfaces (at up to 1.5 Gbps per lane) are available using sysI/O.
3. Available in –8 and –9 speed grades.
4. Each ADC pin count reflects using dedicated complement pair and vRef.
5. Each D-PHY quad consists of 4 D-PHY data lanes.
6. Each PCIe lane consists of a Tx and Rx complement pair.

Table 1.2. CrossLink-NX Automotive Family Selection Guide

Device LIFCL-17 LIFCL-40

Logic Cells¹ 17k 39k

Embedded Memory (EBR) Blocks (18 kb) 24 84

Embedded Memory (EBR) Bits (kb) 432 1,512

Distributed RAM Bits (kb) 80 240

Large Memory (LRAM) Blocks 5 2

Large Memory (LRAM) Bits (kb) 2560 1024
18 × 18 Multipliers 24 56
ADC Blocks3 2 2
450 MHz High Frequency Oscillator 1 1
128 kHz Low Power Oscillator 1 1
GPLL 2 3
Hardened 10 Gbps D-PHY Quads² 2 2
Hardened 2.5 Gbps D-PHY Data Lanes (total)² 8 8

FPGA-DS-02049-2.1 15
CrossLink-NX Family
Data Sheet

Device LIFCL-17 LIFCL-40

PCIe Gen2 Hard IP — 1

Total I/O (Wide Range, High Performance, ADC4) (D-PHY Quads5,
Packages (Size, Ball Pitch)
PCIe6 Lane)
121 csfBGA (6 mm × 6 mm, 0.5 mm) 77 (23, 48, 6) (2, 0) 77 (23, 48, 6) (2, 0)
256 caBGA (14 mm × 14 mm, 0.8 mm) 77 (23, 48, 6) (2, 0) 179 (99, 74, 6) (2, 1)
Notes:
1. Logic Cells = LUTs × 1.2 effectiveness.
2. Additional soft D-PHY Tx/Rx interfaces (at up to 1.5 Gbps per lane) are available using sysI/O.
3. Available in –7 speed grade.
4. Each ADC pin count reflects using dedicated complement pair and vRef.
5. Each D-PHY quad consists of 4 D-PHY data lanes.
6. Each PCIe lane consists of a Tx and Rx complement pair.

16 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

2. Architecture

2.1. Overview
Each CrossLink-NX device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed
between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) and rows of sysDSP Digital Signal
Processing blocks, as shown in Figure 2.1. The CrossLink-NX-40 devices have two rows of DSP blocks and contain three
rows of sysMEM EBR blocks. In addition, CrossLink-NX-40 devices includes two Large SRAM blocks. The sysMEM EBR
blocks are large, dedicated 18 kb fast memory blocks and have built-in ECC and FIFO support. Each sysMEM block can
be configured to a single, pseudo dual or true dual port memory in a variety of depths and widths as RAM or ROM.
Each DSP block supports a variety of multiplier and adder configurations with one 108-bit or two 54-bit accumulators
supported, which are the building blocks for complex signal processing capabilities.
Each PIC block encompasses two PIO (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the
CrossLink-NX devices are arranged in seven banks allowing the implementation of a wide variety of I/O standards. The
Wide Range (WR) I/O banks that are located on the top, left and right sides of the device provide flexible ranges of
general purpose I/O configurations up to 3.3 V VCCIOs. The banks located on the bottom side of the device are
dedicated to High Performance (HP) interfaces such as LVDS, MIPI, DDR3, and LPDDR2 supporting up to 1.8 V VCCIOs.
The Programmable Functional Unit (PFU) contains the building blocks for logic, arithmetic, RAM and ROM functions.
The PFU block is optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic
Blocks are arranged in a two-dimensional array. The registers in the PFU and sysI/O blocks in CrossLink-NX devices can
be configured to be SET or RESET. After power up and configuration, it enters into user mode with these registers
SET/RESET according to the user design, allowing the device to power up in a known state for predictable system
function.
In addition, CrossLink-NX-40 devices provide various system level hard IP functional and interface blocks such as PCIe,
D-PHY, I2C, SGMII/CDR, and ADC blocks. The PCIe hard IP supports PCIe Generation 2.0 and the D-PHY supports up to
2.5 Gbps per lane. CrossLink-NX devices also provide security features to help protect user designs and deliver more
robust reliability by offering enhanced frame based SED/SEC functions.
Other blocks provided include PLLs, DLLs, and configuration functions. The PLL and DLL blocks are located at the
corners of each device. CrossLink-NX devices also include Lattice Memory Mapped Interface (LMMI) which is a Lattice
standard to support simple read and write operations to control internal IP.
Every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error detect
capability. The CrossLink-NX devices use 1.0 V as their core voltage.

FPGA-DS-02049-2.1 17
CrossLink-NX Family
Data Sheet

I/O Bank (Bank 0)

PLL D-PHY (4 Lanes) D-PHY (4 Lanes) PCIe

OSC Configuration & Security

I/O Bank Large I/O Bank

(Bank 7) RAM (Bank 1)

Large
RAM

I/O Bank
(Bank 6)
I/O Bank
(Bank 2)

ADC
(2Ch)

CDR
(2Ch)

PLL I/O Bank (Bank 5) I/O Bank (Bank 4) I/O Bank (Bank 3) PLL

Figure 2.1. Simplified Block Diagram, CrossLink-NX-40 Device (Top Level)

I/O Bank (Bank 0)

D-PHY (4 Lanes) D-PHY (4 Lanes)

OSC Configuration and Security

Large
RAM
I/O Bank
(Bank 1)

Large
RAM
Large
RAM

Large
Large
RAM
RAM
ADC
(2Ch)

CDR
(2Ch)

I/O Bank (Bank 5) I/O Bank (Bank 4) I/O Bank (Bank 3) PLL
PLL

Figure 2.2. Simplified Block Diagram, CrossLink-NX-17 Device (Top Level)

18 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

2.2. PFU Blocks

The core of the CrossLink-NX device consists of PFU blocks. Each PFU block consists of four interconnected slices
numbered 0-3 as shown in Figure 2.3. Each slice contains two LUTs. All the interconnections to and from PFU blocks are
from routing.
The PFU block can be used to perform Logical, Arithmetic, RAM or ROM functions. Table 2.1 shows the functions each
slice can perform in either Distributed SRAM or non-distributed SRAM modes.

From
Routing

LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 &
CARRY CARRY CARRY CARRY CARRY CARRY CARRY CARRY

Slice 0 Slice 1 Slice 2 Slice 3

D D D D D D D D

FF FF FF FF FF FF FF FF

To
Routing

Figure 2.3. PFU Diagram

2.2.1. Slice
Each slice contains two LUT4s feeding two registers. In Distributed SRAM mode, Slice 0 and Slice 1 are configured as
distributed memory and Slice 2 is not available as it is used to support Slice 0 and Slice 1, while Slice 3 is available as
Logic or ROM. Table 2.1 shows the capability of the slices along with the operation modes they enable. In addition,
each Slice contains logic that allows the LUTs to be combined to perform a LUT5 function. There is control logic to
perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select, and wider
RAM/ROM functions.
Table 2.1. Resources and Modes Available per Slice
PFU (Used as Distributed SRAM) PFU (Not used as Distributed SRAM)
Slice
Resources Modes Resources Modes
Slice 0 2 LUT4s and 2 Registers RAM 2 LUT4s and 2 Registers Logic, Ripple, ROM
Slice 1 2 LUT4s and 2 Registers RAM 2 LUT4s and 2 Registers Logic, Ripple, ROM
Slice 2 2 LUT4s and 2 Registers RAM 2 LUT4s and 2 Registers Logic, Ripple, ROM
Slice 3 2 LUT4s and 2 Registers Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM

Figure 2.4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for
positive/negative edge clocking.
Each slice has 17 input signals: 16 signals from routing and one from the carry-chain (from the adjacent slice or PFU).
Three of them are used for FF control and shared between two slices (0/1 or 2/3). There are five outputs: four to
routing and one to carry-chain (to the adjacent PFU). Table 2.2 and Figure 2.4 list the signals associated with all the
slices. Figure 2.5 shows the slice signals that support a LUT5 or two LUT5 functions. F0 can be configured to have a
LUT4 or LUT5 output while F1 is for a LUT4 output.

FPGA-DS-02049-2.1 19
CrossLink-NX Family
Data Sheet

LUT5
and
Carry

Figure 2.4. Slice Diagram

20 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

F1
B1

LUT4
C1

1
F0

SEL

LUT4
C0

*Note: In RAM mode, LUT4s use the following signals:

QWD0/1
QWDN0/1
QWAS00~03, QWAS10~13

Figure 2.5. Slice Configuration for LUT4 and LUT5

Table 2.2. Slice Signal Descriptions

Function Type Signal Names Description
Input Data signal A0, B0, C0, D0 Inputs to LUT4
Input Data signal A1, B1, C1, D1 Inputs to LUT4
Input Data signal M0, M1 Direct input to FF from fabric
Input Control signal SEL LUT5 mux control input
Input Data signal DI0, DI1 Inputs to FF from LUT4 F0/F1 outputs
Input Control signal CE Clock Enable
Input Control signal LSR Local Set/Reset
Input Control signal CLKIN System Clock
Input Inter-PFU signal FCI Fast Carry-in1
Output Data signals F0 LUT4/LUT5 output signal
Output Data signals F1 LUT4 output signal
Output Data signals Q0, Q1 Register outputs
Output Inter-PFU signal FCO Fast carry chain output1
Note:
1. See Figure 2.4 for connection details.

FPGA-DS-02049-2.1 21
CrossLink-NX Family
Data Sheet

2.2.2. Modes of Operation

Slices 0-2 have up to four potential modes of operation: Logic, Ripple, RAM and ROM. Slice 3 is not needed for RAM
mode, it can be used in Logic, Ripple, or ROM modes.
Logic Mode
In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible
input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are
two LUT4s per slice, a LUT5 can be constructed within one slice.
Ripple Mode
Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following
functions can be implemented by each slice:
• Addition 2-bit
• Subtraction 2-bit
• Add/Subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Up/Down counter with asynchronous clear 2-bit using dynamic control
• Up/Down counter with preload (sync) 2-bit using dynamic control
• Comparator functions of A and B inputs 2-bit
• A greater-than-or-equal-to B
• A not-equal-to B
• A less-than-or-equal-to B
• Up/Down counter with A greater-than-or-equal-to B comparator 2-bit using dynamic control
• Up/Down counter with A less-than-or-equal-to B comparator 2-bit using dynamic control
• Multiplier support Ai×Bj+1 + Ai+1×Bj in one logic cell with 2 logic cells per slice
• Serial divider 2-bit mantissa, shift 1bit/cycle
• Serial multiplier 2-bit, shift 1bit/cycle or 2bit/cycle
Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this
configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are
generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.
RAM Mode
In this mode, a 16 × 4-bit distributed single or pseudo dual port RAM can be constructed in one PFU using each LUT
block in Slice 0 and Slice 1 as a 16 × 2-bit memory in each slice. Slice 2 is used to provide memory address and control
signals. CrossLink-NX devices support distributed memory initialization.
The Lattice design tools support the creation of a variety of different sized memories. Where appropriate, the software
constructs these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 lists the
number of slices required to implement different distributed RAM primitives. For more information about using RAM in
CrossLink-NX devices, refer to Memory User Guide for Nexus Platform (FPGA-TN-02094).
Table 2.3. Number of Slices Required to Implement Distributed RAM
SPR 16 × 4 PDPR 16 × 4
Number of slices 3 3
Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
ROM Mode
ROM mode uses the LUT logic; hence, Slice 0 through Slice 3 can be used in ROM mode. Preloading is accomplished
through the programming interface during PFU configuration.
For more information, refer to Memory User Guide for Nexus Platform (FPGA-TN-02094).

22 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

2.3. Routing
There are many resources provided in the CrossLink-NX devices to route signals individually or as buses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The CrossLink-NX family has an enhanced routing architecture that produces a compact design. The Radiant software
tool takes the output of the synthesis tool and places and routes the design.

2.4. Clocking Structure

The CrossLink-NX clocking structure consists of clock synthesis blocks (PLLs), balanced clock tree networks (PCLK and
ECLK), and efficient clock logic modules: Clock Dividers (PCLKDIV and ECLKDIV), Dynamic Clock Selection (DCS), Dynamic
Clock Control (DCC), and DDRDLLs. Each of these functions is described as follows.

2.4.1. Global PLL

The Global PLLs (GPLL) provide the ability to synthesize clock frequencies. The devices in the CrossLink-NX family
support two or three full-featured General Purpose GPLLs.
The architecture of the GPLL is shown in Figure 2.6. A description of the GPLL functionality follows.
REFCLK is the reference frequency input to the PLL and its source can come from external CLK inputs or from internal
routing. The CLKI input feeds into the input Clock Divider block.
CLKFB is the feedback signal to the GPLL which can come from a path internal to the PLL or from FPGA routing. The
feedback divider is used to multiply the reference frequency and thus synthesize a higher or lower frequency clock
output.
The PLL has six clock outputs CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, and CLKOS5. Each output has its own output
divider, thus allowing the GPLL to generate different frequencies for each output. The output dividers can have a value
from 1 to 128. Each GPLL output can be used to drive the primary clock or edge clock networks.
The setup and hold times of the device can be improved by programming a phase shift into the output clocks which
advances or delays the output clock with reference to the un-shifted output clock. This phase shift can be either
programmed during configuration or can be adjusted dynamically using the DIRSEL, DIR, DYNROTATE, and LOADREG
ports.
The LOCK signal is asserted when the GPLL determines it has achieved lock and deasserted if a loss of lock is detected.
The LOCK signal is asynchronous to the PLL clock outputs.

FPGA-DS-02049-2.1 23
CrossLink-NX Family
Data Sheet

(To bypass muxes)

Figure 2.6. General Purpose PLL Diagram

For more details on the PLL, refer to the sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).

2.4.2. Clock Distribution Network

There are two main clock distribution networks for any member of the CrossLink-NX product family, namely Primary
Clock (PCLK) and Edge Clock (ECLK). These clock networks can be driven from many different sources, such as Clock
Pins, PLL outputs, DLLDEL outputs, Clock Divider outputs, SerDes/PCS clocks and user logic. There are Clock Divider
blocks (ECLKDIV and PCLKDIV) to provide a slower clock from these clock sources.
CrossLink-NX supports glitchless Dynamic Clock Control (DCC) for the PCLK Clock to save dynamic power. There are also
Dynamic Clock Selection logic to allow glitchless selection between two clocks for the PCLK network (DCS).
An overview of the Clocking Network is shown in Figure 2.7 for CrossLink-NX device. The shaded blocks (PCIe and upper
left PLL) are not available in the 17k Logic Cell device.

24 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

PLL MIPI_DPHY0 MIPI_DPHY1 BANK 0 PCLK OSC

TMID

BANK 1 PCLK
16 DCC

RMID
LMID

12 DCC

BANK 2 PCLK
18 DCC

BMID

PLL BANK 5 PCLK ECLK BANK 4 PCLK ECLK BANK 3 PCLK ECLK PLL

Figure 2.7. Clocking

2.4.3. Primary Clocks

The CrossLink-NX device family provides low-skew, high fan-out clock distribution to all synchronous elements in the
FPGA fabric through the Primary Clock Network. The CrossLink-NX PCLK clock network is a balanced clock structure
which is designed to minimize the clock skew across all destinations in the FPGA core.
The primary clock network is divided into two clock domains depending on the device density. Each of these domains
has 16 clocks that can be distributed to the fabric in the domain.
The Lattice Radiant software can automatically route each clock to one of the domains up to a maximum of 16 clocks
per domain. You can change how the clocks are routed by specifying a preference in the Lattice Radiant software to
locate the clock to a specific domain. The CrossLink-NX device provides the user with a maximum of 64 unique clock
input sources that can be routed to the primary Clock network.
Primary clock sources are:
• Dedicated clock input pins
• PLL outputs
• PCLKDIV, ECLKDIV outputs
• Internal FPGA fabric entries (with minimum general routing)
• SGMII-CDR, D-PHY, PCIe clocks
• OSC clock
These sources are routed to each of four clock switches called a Mid Mux (LMID, RMID, TMID, BMID). The outputs of
the Mid MUX are routed to the center of the FPGA where additional clock switches (DSC_CMUX) are used to route the
primary clock sources to primary clock distribution to the CrossLink-NX fabric. These routing muxs are shown in
Figure 2.7. There are potentially 64 unique clock domains that can be used in the largest CrossLink-NX Device. For more
information about the primary clock tree and connections, refer to sysCLOCK PLL Design and User Guide for Nexus
Platform (FPGA-TN-02095).

FPGA-DS-02049-2.1 25
CrossLink-NX Family
Data Sheet

2.4.4. Edge Clock

CrossLink-NX FPGAs have several high-speed edge clocks that are intended for use with the PIO in the implementation
of high-speed interfaces. There are four (4) ECLK networks per bank I/O on the Bottom side of the device. The Edge
clock network is powered by a separate power domain (to reduce power noise injection from the core and reduce
overall noise induced jitter) while controlled by the same logic that gates the FPGA core and PCLK domains for power
management.
Each Edge Clock can be sourced from the following:
• Dedicated PIO Clock input pins (PCLK)
• DLLDEL output (PIO Clock delayed by 90°)
• PLL outputs (CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, and CLKOS5)
• Internal Nodes
Figure 2.8 illustrates the various ECLK sources. Bank 3 is shown in the example. Bank 4 and Bank 5 are similar.

From Banks 4, 5
Bank 3 PCLK Pin (even) ECLKSYNC
2

DLLDEL

Bottom 6
Left GPLL

Bank 3 ECLK Tree

From Fabric
ECLKSYNC

ECLKDIV BMID
Bottom 6
Right GPLL

2
Bank 3 PCLK Pin (odd)

To Banks 4,5 Muxes

Figure 2.8. Edge Clock Sources per Bank

The edge clocks have low injection delay and low skew. They are typically used for DDR Memory or Generic DDR
interfaces. For detailed information on Edge Clock connections, refer to sysCLOCK PLL Design and User Guide for Nexus
Platform (FPGA-TN-02095).

2.4.5. Clock Dividers

CrossLink-NX devices have two distinct types of clock divider, Primary and Edge. There are from one (1) to eight (8)
Primary Clock Dividers (PCLKDIV) and which are located in the DCS_CMUX block(s) at the center of the device. There
are twelve (12) ECLKDIV dividers per device, locate near the bottom high-speed I/O banks.
The PCLKDIV supports ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128, and ÷1 (bypass) operation. The PCLKDIV is fed from a DCSMUX
within the DCS_CMUX block. The clock divider output drives one input of the DCS Dynamic Clock Select within the
DSC_CMUX block. The Reset (RST) control signal is asynchronous and forces all outputs to low. The divider output starts
at next cycle after the reset is synchronously released. The PCLKDIV is shown in context in Figure 2.9.
The ECLKDIV is intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in
a ÷2, ÷3.5, ÷4, or ÷5 mode and maintains a known phase relationship between the divided down clock and the high-
speed clock based on the release of its reset signal. The ECLKDIV can be fed from selected PLL outputs, external primary
clock pins (with or without DLLDEL Delay) or from routing. The clock divider outputs feed into the Bottom Mid-mux
(BMID). The Reset (RST) control signal is asynchronous and forces all outputs to low. The divider output starts at next
cycle after the reset is synchronously released.
The ECLKDIV block is shown in context in Figure 2.8. For further information on clock dividers, refer to sysCLOCK PLL
Design and User Guide for Nexus Platform (FPGA-TN-02095).

26 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

2.4.6. Clock Center Multiplexer Blocks

All clock sources are selected and combined for primary clock routing through the Dynamic Clock Selector Center
Multiplexer logic (DCS_CMUX). There are one (1) or two (2) DCS_CMUX blocks per device. Each DCS_CMUX block
contains two DCSMUX blocks, one PCLKDIV, one DCS block, and 1 or 2 CMUX blocks. See Figure 2.9 for a representative
DCS_CMUX block diagram.
The heart of the DCS_CMUX is the Center Multiplexer (CMUX) block. It can accept up to 64 input clock sources (Mid-
muxes (RMID, LMID, TMIC, BMID) and DCC) and to drive up to 16 primary clock trunk lines.
Up to two (2) clock inputs to the DCS_CMUX can be routed through a Dynamic Clock Select block then routed to the
CMUX. One (1) input to the DCS can be optionally divided by the Primary Clock Divider (PCLKDIV). For more information
about the DCS_CMUX, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).

16 16

16x (partial 16x (partial

(16/64):1) (16/64):1)
CMUX CMUX
16 16

DCS_CMUX dcs2cmux0
DCS
62 dcs1 dcs0

PCLKDIV

DCMUX DCMUX
(62:1) (62:1)
62 62
62 62

Figure 2.9. DCS_CMUX Diagram

2.4.7. Dynamic Clock Select

The Dynamic Clock Select (DCS) is a smart multiplexer function available in the primary clock routing. It switches
between two independent input clock sources. Depending on the operational mode, it switches between two (2)
independent input clock sources either with or without any glitches. This is achieved regardless of when the select
signal is toggled. Both input clocks must be running to achieve a functioning glitchless DCS output clock, but running
clocks are not required when used as a non-glitchless normal clock multiplexer.
There are one (1) or two (2) DCS blocks per device that feed all clock domains. The DCS blocks are located in the
DCS_MUX block. The inputs to the DCS blocks come from MIDMUX outputs and user logic clocks through DCC
elements. The DCS elements are located at the center of the PLC array core. The output of the DCS is connected to the
inputs of Primary Clock Center MUXs (CMUX).
Figure 2.10 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to
other modes. For more information about the DCS, refer to sysCLOCK PLL Design and User Guide for Nexus Platform
(FPGA-TN-02095).

FPGA-DS-02049-2.1 27
CrossLink-NX Family
Data Sheet

CLK0

clk0
pos
CLK1

clk1 clk1
pos neg
SEL

clk0
neg

DCSOUT

Figure 2.10. DCS Waveforms

2.4.8. Dynamic Clock Control

The Dynamic Clock Control (DCC), Domain Clock enable/disable feature allows internal logic control of the domain
primary clock network. When a clock network is disabled, the clock signal is static and does not toggle. All the logic fed
by that clock also does not toggle, reducing the overall power consumption of the device. The disable function is
glitchless, and does not increase the clock latency on the primary clock network.
Four additional DCC elements control the clock inputs from the CrossLink-NX domain logic to the Center MUX elements
(DSC_CMUX).
This DCC controls the clock sources from the Primary CLOCK MIDMUX before they are fed to the Primary Center MUXs
that drive the domain clock network. For more information about the DCC, refer to sysCLOCK PLL Design and User
Guide for Nexus Platform (FPGA-TN-02095).

2.4.9. DDRDLL
CrossLink-NX has two identical DDRDLL blocks, located in the lower left and lower right corners of the device. Each
DDRDLL (Controller DLL block) can generate a 9-bit phase shift value corresponding to a 90 degree phase shift of the
reference clock input and provide this value to every DQS block and DLLDEL Target delay element. The reference clock
can be either from a PLL, or an input pin. The DQSBUF uses this value to control the delay of the DQS inputs from a DDR
memory interface to achieve a 90-degree shift in order to clock DQ inputs at the center of the data eye.
• The value is also sent to another Target DLL, DLLDEL, which takes a primary clock input and generates a 90-degree
shifted clock output to drive the clocking structure. This is useful in an edge-aligned Generic DDR interface, where
90-degree clocking needs to be created. Not all primary clock inputs have associated DLLDEL control. Figure 2.11
shows DDRDLL connectivity to a DLLDEL block (connectivity to DQSBUF blocks is similar).

28 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

To both BMID and

ECLKINMUX

PCLK Input
+
- DLLDEL

code1

code2
9 Right DDRDLL

9
Left DDRDLL

Figure 2.11. DLLDEL Functional Diagram

Each DDRDLL can generate a delay value based on the reference clock frequency. The Target DLLs (DQSBUF and
DLLDEL) use the value (code) to either create phase shifted inputs from the DDR memory or create a 90 degree shifted
clock. Figure 2.12 shows the connections between the DDRDLL and the Target DLLs.

Left Right
DDRDLL DDRDLL
Digital Delay Code (L) Digital Delay Code (R)

Refclk Sel Refclk Sel

DLLDEL DLLDEL DQS0 DQS1 DLLDEL DQS0 DQS1

BANK5 ECLK BANK4 ECLK BANK3 ECLK

Figure 2.12. DDRDLL Architecture

2.5. SGMII Tx/Rx

The CrossLink-NX device utilizes different components/resources for the transmit and receive paths of Serial Gigabit
Media Independent Interface (SGMII). For the SGMII transmit path, generic DDR I/O with x5 gearing are used. For more
information, refer to GDDRX5_TX.ECLK.Aligned Interface on the CrossLink-NX High-Speed I/O Interface (FPGA-TN-
02097).
For the SGMII receive path, one of the two available hardened CDR (Clock and Data Recovery) components can be
used.
There are three main blocks in each CDR: the CDR, deserializer, and FIFO. Each CDR features two loops. The first loop is
locked to the reference clock. Once locked, the loop switches to the data path loop where the CDR tracks the data
signals to generate the correcting signals needed to achieve and maintain phase lock with the data. The data is then
passed through a deserializer which deserialize the data to 10-bit parallel data. The 10-bit parallel data is then sent to
the FIFO bridge, which allows the CDR to interface with the rest of the FPGA.
Figure 2.13 shows a block diagram of the SGMII CDR IP.

FPGA-DS-02049-2.1 29
CrossLink-NX Family
Data Sheet

The two hardened blocks are located at the bottom left of the chip and uses the high speed I/O Bank 5 for the
differential pair input. It is recommended that the reference clock should be entered through a GPIO that has
connection to the PLL on the lower left corner as well.
For more information about how to implement the hardened CDR for SGMII solution, refer to the SGMII and Gb
Ethernet PCS IP Core (FPGA-IPUG-02077).

SGMII CDR IP

lmmi_dk
lmmi_request
lmmi_wrdn
lmmi_rdata[7:0]
lmmi_offset[3:0]
lmmi_rdata_valid
lmmi_wdata[7:0]
lmmi_ready
lmmi_reset
ip_ready

sgmii_cdr_icnst<1:0>

sgmii_rxd<9:0>
rxd<9:0>
sgmii_in rxd_des
DUAL_LOOP
DESERIALIZER FIFO
CDR

rclk_des
dco_calib_rst
dco_facq_rst
rrst

sgmii_refclk(125 MHz) sgmii_pclk

sgmii_rclk

Figure 2.13. SGMII CDR IP

2.6. sysMEM Memory

CrossLink-NX devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18 kb RAM with
memory core, dedicated input registers and output registers as well as optional pipeline registers at the outputs. Each
EBR includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM and built in FIFO. In
CrossLink-NX, unused EBR blocks is powered down to minimize power consumption.

2.6.1. sysMEM Memory Block

The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a
variety of depths and widths as listed in Table 2.4. FIFOs can be implemented using the built in read and write address
counters and programmable full, almost full, empty and almost empty flags. The EBR block facilitates parity checking by
supporting an optional parity bit for each data byte. EBR blocks provide byte-enable support for configurations with 18-
bit and 36-bit data widths. For more information, refer to Memory User Guide for Nexus Platform (FPGA-TN-02094).
EBR also provides a build in ECC engine, which is available in Commercial/Industrial –8 and –9 speed grades and
Automotive –7 speed grade. The ECC engine supports a write data width of 32 bits and it can be cascaded for larger
data widths such as x64. The ECC parity generator creates and stores parity data for each 32-bit word written. When a
read operation is performed, it compares the data with its associated parity data and report back if any Single Event
Upset (SEU) event has disturbed the data. Any single bit data disturb is automatically corrected at the data output. In
addition, two dedicated error flags indicate if a single-bit or two-bit error has occurred.

30 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Table 2.4. sysMEM Block Configurations

Memory Mode Configurations
Single Port 16,384 × 1
8,192 × 2
4,096 × 4
2,048 × 9
1,024 × 18
512 × 36
True Dual Port 16,384 × 1
8,192 × 2
4,096 × 4
2,048 × 9
1,024 × 18
Pseudo Dual Port 16,384 × 1
8,192 × 2
4,096 × 4
2,048 × 9
1,024 × 18
512 × 36

2.6.2. Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports (except ECC mode, which only
supports a write data width of 32 bits). The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word
1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each
port.

2.6.3. RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during
the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM.

2.6.4. Memory Cascading

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade
memory transparently, based on specific design inputs.

2.6.5. Single, Dual and Pseudo-Dual Port Modes

In all the sysMEM RAM modes, the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.

2.6.6. Memory Output Reset

The EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA
and RSTB are local signals, which reset the output latches associated with Port A and Port B, respectively. The Global
Reset (GSRN) signal can reset both ports. The output data latches and associated resets for both ports are as shown in
Figure 2.14. The optional Pipeline Registers at the outputs of both ports are also reset in the same way.

FPGA-DS-02049-2.1 31
CrossLink-NX Family
Data Sheet

Memory Core
SET
D Q Port A[17:0]
LCLR

Output Data
Latches
D
SET
Q Port B[17:0]
LCLR

RSTA

RSTB

GSRN

Programmable Disable

Figure 2.14. Memory Core Reset

For further information on the sysMEM EBR block, see the list of technical documentation in the References section.

2.7. Large RAM

The CrossLink-NX device includes additional memory resources in the form of Large Random-Access Memory (LRAM)
blocks.
The LRAM is designed to work as Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM, and ROM memories. It is
meant to function as additional memory resources for users beyond what is available in the EBR and PFU.
Each individual Large RAM block contains 0.5 Mbits of memory, and has a programmable data width of up to 32 bits.
Cascading Large RAM blocks allows data widths of up to 64 bits. Additionally, there is the ability to use either Error
Correction Coding (ECC) or byte enable.

2.8. sysDSP
The CrossLink-NX family provides an enhanced sysDSP architecture, making it ideally suited for low-cost, high-
performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse
Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders
and decoders. These complex signal processing functions use similar building blocks such as multiply-adders and
multiply-accumulators.

2.8.1. sysDSP Approach Compared to General DSP

Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed
data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher
clock speeds. In the CrossLink-NX device family, there are many DSP blocks that can be used to support different data
widths. This allows users to use highly parallel implementations of DSP functions. You can optimize DSP performance
versus area by choosing appropriate levels of parallelism. Figure 2.15 compares the fully serial implementation to the
mixed parallel and serial implementation.

32 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Operand Operand Operand

A A A

Operand Operand Operand

B B B
Operand Operand
A B

X X X m/k
loops
Single M loops Multiplier Multiplier
Multiplier
Multiplier X 0 1
k

Accumulator

Function Implemented in General

(k adds)
+
Purpose DSP

m/k
accumulate

Output

Function Implemented in
CrossLink-NX

Figure 2.15. Comparison of General DSP and CrossLink-NX Approaches

2.8.2. sysDSP Architecture Features

The CrossLink-NX sysDSP block contains two sysDSP slices. The CrossLink-NX sysDSP Slice has been significantly
enhanced to provide functions needed for advanced processing applications. These enhancements provide improved
flexibility and resource utilization.
The CrossLink-NX sysDSP block (two sysDSP slices) supports many functions that include the following:
• Symmetry support. The primary target application is wireless. 1D Symmetry is useful for many applications that
use FIR filters when their coefficients have symmetry or asymmetry characteristics. The main motivation for using
1D symmetry is cost/size optimization. The expected size reduction is up to 2x.
• Odd Mode – Filter with Odd number of taps
• Even Mode – Filter with Even number of taps
• Two dimensional (2D) Symmetry Mode – Supports 2D filters for mainly video applications
• Dual-multiplier architecture. Lower accumulator overhead to half and the latency to half compared to single
multiplier architecture.
• Fully cascadable DSP across slices. Support for symmetric, asymmetric and non-symmetric filters.
• Multiply (36 × 36, two 18 × 36, four 18 × 18 or eight 9 × 9)
• Multiply Accumulate (supports one 18 × 36 multiplier result accumulation, two 18 × 18 multiplier result
accumulation or four 9 × 9 multiplier result accumulation)
• Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18 × 18
Multiplies feed into an accumulator that can accumulate up to 54 bits)
• Pipeline registers
• 1D Symmetry support. The coefficients of FIR filters have symmetry or negative symmetry characteristics.
• Odd Mode – Filter with Odd number of taps
• Even Mode – Filter with Even number of taps

FPGA-DS-02049-2.1 33
CrossLink-NX Family
Data Sheet

• 2D Symmetry support. The coefficients of 2D FIR filters have symmetry or negative symmetry characteristics.
• 3 × 3 and 3 × 5 – Internal DSP Slice support
• 5 × 5 and larger size 2D blocks – Semi internal DSP Slice support
• Flexible saturation and rounding options to satisfy a diverse set of applications situations
• Flexible cascading DSP blocks
• Minimizes fabric use for common DSP functions
• Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only
• Provides matching pipeline registers
• Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade chains
• RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy users
• Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require
processor-like flexibility that enables different functions for each clock cycle
For most cases, as shown in Figure 2.16, the CrossLink-NX sysDSP block is backwards-compatible with the LatticeECP3™
sysDSP block, such that, legacy applications can be targeted to CrossLink-NX sysDSP. Figure 2.16 shows the diagram of
sysDSP block.

Input Input Input Input Input Input Input Input

B1 B1 B1 B1 B1 B1 B1 B1
Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input
C B2 C B2 C B2 C B2 C B2 C B2 C B2 C B2

9+9 9+9 9+9 9+9 9+9 9+9 9+9 9+9

Input Input Input Input Input Input Input Input

REG REG REG REG REG REG REG REG
A1 A1 A1 A1 A1 A1 A1 A1
Input Input Input Input Input Input Input Input
A2 A2 A2 A2 A2 A2 A2 A2

9x9 9x9 9x9 9x9 9x9 9x9 9x9 9x9

18 X 18 18 X 18 18 X 18 18 X 18
18 X 36 (CSA) 18 X 36 (CSA)
36 X 36 (CSA)

REG 18 REG 18 REG 18 REG 18 REG 18 REG 18 REG 18 REG 18

ACC54 ACC54

Output Register Output Register

Note : All Registers inside the DSP Block are Bypassable via Configuration Setting

Figure 2.16. DSP Functional Block Diagram

The CrossLink-NX sysDSP block supports the following basic elements.

• MULT (Multiply)
• MAC (Multiply, Accumulate)
• MULTADDSUB (Multiply, Addition/Subtraction)
• MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation)

34 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Table 2.5 shows the capabilities of CrossLink-NX sysDSP block versus the above functions.
Table 2.5. Maximum Number of Elements in a sysDSP block
Width of Multiply x9 x18 x36
MULT 8 4 1
MAC 2 2 —
MULTADDSUB 2 2 —
MULTADDSUBSUM 2 2 —

Some options are available in the four elements. The input register in all the elements can be directly loaded or can be
loaded as a shift register from previous operand registers. By selecting dynamic operation, the following operations are
possible:
• In the Add/Sub option, the Accumulator can be switched between addition and subtraction on every cycle.
• The loading of operands can switch between parallel and serial operations.
For further information, refer to sysDSP User Guide for Nexus Platform (FPGA-TN-02096).

2.9. Programmable I/O (PIO)

The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective
sysI/O buffers and pads.
On all CrossLink-NX devices, two adjacent PIO can be combined to provide a complementary output driver pair.

2.10. Programmable I/O Cell (PIC)

The programmable I/O cells (PIC) provides I/O function and necessary gearing logic associated with PIO. CrossLink-NX
consists of base PIC and gearing PIC.
Base PICs contain three blocks: an input register block, output register block, and tri-state register block. These blocks
contain registers for operating in a variety of modes along with the necessary clock and selection logic. Base PICs cover
the top and left/right bank. Gearing PICs contain gearing logic and edge monitor used for locating the center of data
window. Gearing PICs cover the bottom banks to support DDR operation.

FPGA-DS-02049-2.1 35
CrossLink-NX Family
Data Sheet

PIC

PIO A
Input
Register
Block

Output and
Tristate Pin
Register A
Block

Core
Logic/ Input and Output
Routing Gearbox

PIO B
Input
Register
Block

Output and
Tristate Pin
Register B
Block

Figure 2.17. Group of Two High Performance Programmable I/O Cells

PIC

PIO A
Input
Register
Block

Output and
Tristate Pin
Register A
Block

Core
Logic/
Routing

PIO B
Input
Register
Block

Output and
Tristate Pin
Register B
Block

Figure 2.18. Wide Range Programmable I/O Cells

36 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

2.10.1. Input Register Block

The input register blocks for the PIO on all edges contain delay elements and registers that can be used to condition
high-speed interface signals before they are passed to the device core. In addition, the input register blocks for the PIO
on the bottom edges include built-in FIFO logic to interface to DDR and LPDDR memory.
The Input register block on the bottom side includes gearing logic and registers to implement IDDRX1, IDDRX2, IDDRX4,
IDDRX5 gearing functions. With two PICs sharing the DDR register path, it can also implement the IDDRX71 function
used for 7:1 LVDS interfaces. It uses three sets of registers – shift, update, and transfer to implement gearing and the
clock domain transfer. The first stage registers sample the high-speed input data by the high-speed edge clock on its
rising and falling edges. The second stage registers perform data alignment based on the control signals. The third
stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. For more
information on gearing function, refer to CrossLink-NX High-Speed I/O Interface (FPGA-TN-02097).
Input FIFO
The CrossLink-NX PIO has a dedicated input FIFO per single-ended pin for input data register for DDR Memory
interfaces. The FIFO resides before the gearing logic. It transfers data from DQS domain to continuous ECLK domain. On
the Write side of the FIFO, it is clocked by DQS clock, which is the delayed version of the DQS Strobe signal from DDR
memory. On the Read side of FIFO, it is clocked by ECLK. ECLK may be any high-speed clock with identical frequency as
DQS (the frequency of the memory chip). Each DQS group has one FIFO control block. It distributes FIFO read/write
pointers to every PIC in same DQS group. DQS Grouping and the DQS Control Block is described in DDR Memory
Support section.
Table 2.6. Input Block Port Description
Name Type Description
D Input High Speed Data Input
Q[1:0]/Q[3:0]/Q[6:0]/Q[7:0]/Q[9:0] Output Low Speed Data to the device core
RST Input Reset to the Output Block
SCLK Input Slow Speed System Clock
ECLK Input High Speed Edge Clock
DQS Input Clock from DQS control Block used to clock DDR memory data
ALIGNWD Input Data Alignment signal from device core.

Figure 2.19 shows the input register block for the PIO on the top, left, and right edges.

INCK
Programmable INFF
D Delay Cell
INFF Q

SCLK IDDRX1 Q[1:0]

RST

Figure 2.19. Input Register Block for PIO on Top, Left, and Right Sides of the Device

FPGA-DS-02049-2.1 37
CrossLink-NX Family
Data Sheet

Figure 2.20 shows the input register block for the PIO located on the bottom edge.

I N CK

IN FF
Programmable
D
Delay Cell

I N FF Q

Generic

IDDRX1

FIFO IDDRX2
Q[1:0]/
IDDRX4 Q[3:0]/
Delayed DQS ECLK
IDDRX5 Q[6:0]* /
IDDRX71* Q[7:0]/
Q[9:0]
Memory
ECLK
IDDRX2
SCLK IDDRX4
RST

ALIGNWD

*For 7:1 LVDS interface only. It is required to use PIO pair pins (PIOA/B or PIOC/D).

Figure 2.20. Input Register Block for PIO on Bottom Side of the Device

2.10.2. Output Register Block

The output register block registers signals from the core of the device before they are passed to the sysI/O buffers.
The CrossLink-NX output data path has programmable registers and output gearing logic. On the bottom side, the
output register block can support 1x, 2x, x4, x5, and 7:1 gearing enabling high speed DDR and DDR memory interfaces.
On the top, left, and right sides, the banks support 1x gearing. The CrossLink-NX output data path diagram is shown in
Figure 2.21. The programmable delay cells are also available in the output data path.
For a detailed description of the output register block modes and usage, refer to CrossLink-NX High-Speed I/O Interface
(FPGA-TN-02097).

Programmable
D Delay Cell Q
OUTFF

RST
SCLK Generic
ODDRX1
D[1:0]

Figure 2.21. Output Register Block on Top, Left, and Right Sides

38 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Programmable
D Delay Cell
Q
OUT FF

RST Generic
SCLK ODD RX1/
ODD RX2/
ECLK ODD RX4
DQSW ODD RX5
ODD R71*
DQSW270
Memory
Q[1:0]/
ODD RX2
Q[3:0]/ OSHX2
Q[6:0]* / ODD RX4
Q[7:0]/
Q[9:0]

*For 7:1 LVDS interface only. It is required to use PIO pair pins PIOA/B.

Figure 2.22. Output Register Block on Bottom Side

Table 2.7. Output Block Port Description

Name Type Description
Q Output High Speed Data Output
D Input Data from core to output SDR register
Q[1:0]/Q[3:0]/Q[6:0]/Q[7:0]/Q[9:0] Input Low Speed Data from device core to output DDR register
RST Input Reset to the Output Block
SCLK Input Slow Speed System Clock
ECLK Input High Speed Edge Clock
DQSW Input Clock from DQS control Block used to generate DDR memory DQS output
DQSW270 Input Clock from DQS control Block used to generate DDR memory DQ output

2.11. Tri-state Register Block

The tri-state register block registers tri-state control signals from the core of the device before they are passed to the
sysI/O buffers. The block contains a register for SDR operation. In SDR, the TD input feeds one of the flip-flops that then
feeds the output. In DDR, operations used mainly for DDR memory interfaces can be implemented on the bottom side
of the device. Here, two inputs feed the tri-state registers clocked by both ECLK and SCLK.
Figure 2.23 and Figure 2.24 show the Tri-state Register Block functions on the device. For a detailed description of the
tri-state register block modes and usage, refer to CrossLink-NX High-Speed I/O Interface (FPGA-TN-02097).

TQ
TD
RST TSFF
SCLK

Figure 2.23. Tri-state Register Block on Top, Left, and Right Sides

FPGA-DS-02049-2.1 39
CrossLink-NX Family
Data Sheet

TQ
TD
TSFF

RST
SCLK
ECLK
THSX2
DQSW
DQSW270
T[1:0]

Figure 2.24. Tri-state Register Block on Bottom Side

Table 2.8. Tri-state Block Port Description

Name Type Description
TD Input Tri-state Input to Tri-state SDR Register
RST Input Reset to the Tri-state Block
T[1:0] Input Tri-state input to TSHX2 function
SCLK Input Slow Speed System Clock
ECLK Input High Speed Edge Clock
DQSW Input Clock from DQS control Block used to generate DDR memory DQS output
DQSW270 Input Clock from DQS control Block used to generate DDR memory DQ output
TQ Output Output of the Tri-state block

2.12. DDR Memory Support

2.12.1. DQS Grouping for DDR Memory
Certain PICs have additional circuitry to allow the implementation of high-speed source synchronous and DDR3/DDR3L,
LPDDR2 memory interfaces. The support varies by the edge of the device as detailed below.
PICs on the bottom side have fully functional elements supporting DDR3/DDR3L, LPDDR2 memory interfaces. Every 16
PIO on the bottom side are grouped into one DQS group, as shown in Figure 2.25. Within each DQS group, there are
two pre-placed pins for DQS and DQS# signals. The rest of the pins in the DQS group can be used as DQ signals and DM
signal. The number of pins in each DQS group bonded out is package dependent. DQS groups with less than 11 pins
bonded out can only be used for LPDDR2/3 Command/ Address busses. In DQS groups with more than 11 pins bonded
out, up to two pre-defined pins are assigned to be used as virtual VCCIO, by driving them high to make extra
connections to the VCCIO power supply. These soft connections to VCCIO help reduce SSO noise. For details, refer to
CrossLink-NX High-Speed I/O Interface (FPGA-TN-02097).

40 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

DQS

PIO B

PIO A

PIO B

PIO A

PIO B

PIO A

PIO B

PIO A
PIO B

PIO A

PIO B

PIO A

PIO B

PIO A

PIO B

PIO A

DQSBUF
sysIO Buffer

sysIO Buffer

sysIO Buffer
Delay
Pad B

Pad A

Pad B

Pad A

Pad B

Pad A

Pad B

Pad A
Pad B (C)

Pad B (C)

Pad B (C)
Pad A (T)

Pad A (T)

Figure 2.25. DQS Grouping on the Bottom Edge

2.12.2. DLL Calibrated DQS Delay and Control Block (DQSBUF)

To support DDR memory interfaces (DDR3/DDR3L, LPDDR2/3), the DQS strobe signal from the memory must be used to
capture the data (DQ) in the PIC registers during memory reads. This signal is output from the DDR memory device
aligned to data transitions and must be time shifted before it can be used to capture data in the PIC. This time shift is
achieved by using the DQSBUF programmable delay line in the DQS Delay Block (DQS read circuit). The DQSBUF is
implemented as a Target delay line and works in conjunction with a Controller DDRDLL.
This block also includes a slave delay line to generate delayed clocks used during writes to generate DQ and DQS with
correct phases within one DQS group. There is a third delay line inside this block used to provide write leveling for DDR
write if needed.
Each of the read and write side delays can be dynamically shifted using margin control signals from the core logic.
The FIFO Control Block included here generates the Read and Write Pointers for the FIFO inside the Input Register
Block. These pointers are generated to control the DQS to ECLK domain crossing using the FIFO module.

FPGA-DS-02049-2.1 41
CrossLink-NX Family
Data Sheet

BURST_DET
DQS
Preamble/Postamble Management
READ[1:0]
READ_CLK_SEL[2:0]

WRPNTR[2:0]
SCLK FIFO Control and Data Valid
Generation RDPNTR[2:0]
ECLK
DATAVALID

DQSR90
RD_CODN, RD_DIRECTION, RD_MOVE Slave Delay Line (RD) with RD_cout
Adjustment/Margin Test

WR_COUT
WRITE_LEVELING_LOADN
WRITE_LEVELING_DIRECTION
DQSW270
WRITE_LEVELING_MOVE Slave Delay (WR) with
Adjustment/Margin Test and Write Leveling DQSW
WR_LOADN, WR_DIRECTION, WR_MOVE

DELAYCODE_I[8:0]
RST
DELAYCODE_O[8:0]
DONE_GWE
GSR

Figure 2.26. DQS Control and Delay Block (DQSBUF)

Table 2.9. DQSBUF Port List Description

Name Type Description
DQS Input DDR memory DQS strobe
READ[1:0] Input Read Input from DDR Controller
READCLKSEL[2:0] Input Read pulse selection
SCLK Input Slow System Clock
ECLK Input High Speed Edge Clock (same frequency as DDR memory)
RDLOADN, RDMOVE, RDDIRECTION Input Dynamic Margin Control ports for Read delay
WRLOADN, WRMOVE, WRDIRECTION Input Dynamic Margin Control ports for Write delay
DELAYCODE_I[8:0] Input Dynamic Delay Control
WRITE_LEVELING_LOADN, Input Write Leveling Control
WRITE_LEVELING_DIRECTION,
WRITE_LEVELING_MOVE
DQSR90 Output 90 delay DQS used for Read
DQSW270 Output 90 delay clock used for DQ Write
DQSW Output Clock used for DQS Write
RDPNTR[2:0] Output Read Pointer for IFIFO module
WRPNTR[2:0] Output Write Pointer for IFIFO module
DATAVALID Output Signal indicating start of valid data
BURSTDET Output Burst Detect indicator
RD_COUT Output Read Count
WR_COUT Output Write Count
DELAYCODE_O[8:0] Output Dynamic Delay Control

42 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

2.13. sysI/O Buffer

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement a wide variety of
standards that are found in today’s systems including LVDS, HSUL, SSTL Class I and II, LVCMOS, LVTTL, and MIPI.
The CrossLink-NX family contains multiple Programmable I/O Cell (PIC) blocks. Each PIC contains two Programmable
I/O, PIOA and PIOB. Each PIO includes a sysI/O buffer and I/O logic. Two adjacent PIO can be joined to provide a
differential I/O pair referred to as True and Comp, where True Pad is associated with the positive side of the differential
I/O, and the complement with the negative.
The top, left and right side banks support I/O standards from 3.3 V to 1.0 V while the bottom supports I/O standards
from 1.8 V to 1.0 V. Every pair of I/O on the bottom bank also have a true LVDS and SLVS Tx Driver. In addition, the
bottom bank supports single-ended input termination. Both static and dynamic termination are supported. Dynamic
termination is used to support the DDR/LPDDR interface standards. For more information about DDR implementation
in I/O Logic and DDR memory interface support, refer to CrossLink-NX High-Speed I/O Interface (FPGA-TN-02097).

2.13.1. Supported sysI/O Standards

CrossLink-NX sysI/O buffers support both single-ended differential and differential standards. Single-ended standards
can be further subdivided into internally ratioed standards such as LVCMOS, LVTTL, and externally referenced
standards such as HSUL and SSTL. The buffers support the LVTTL, LVCMOS 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V
standards. Differential standards supported include LVDS, SLVS, differential LVCMOS, differential SSTL, and differential
HSUL. For better support of video standards, subLVDS and MIPI_D-PHY are also supported. Table 2.10 and Table 2.11
provide a list of sysI/O standards supported in CrossLink-NX devices.
Table 2.10. Single-Ended I/O Standards
Standard Input Output Bi-directional
LVTTL33 Yes Yes Yes
LVCMOS33 Yes Yes Yes
LVCMOS25 Yes Yes Yes
LVCMOS18 Yes Yes Yes
LVCMOS15 Yes Yes Yes
LVCMOS12 Yes Yes Yes
LVCMOS10 Yes No No
HTSL15 I Yes Yes Yes
SSTL 15 I Yes Yes Yes
SSTL 135 I Yes Yes Yes
HSUL12 Yes Yes Yes
LVCMOS18H Yes Yes Yes
LVCMOS15H Yes Yes Yes
LVCMOS12H Yes Yes Yes
LVCMOS10H Yes Yes Yes
LVCMOS10R Yes — Yes1
Note:
1. Output supported by LVCMOS10H.

FPGA-DS-02049-2.1 43
CrossLink-NX Family
Data Sheet

Table 2.11. Differential I/O Standards

Standard Input Output Bi-directional
LVDS Yes Yes Yes
SUBLVDS Yes No —
SLVS Yes Yes —
SUBLVDSE — Yes —
SUBLVDSEH — Yes —
LVDSE — Yes —
MIPI_D-PHY Yes Yes Yes
HSTL15D_I Yes Yes Yes
SSTL15D_I Yes Yes Yes
SSTL15D_II Yes Yes Yes
SSTL135D_I Yes Yes Yes
SSTL135D_II Yes Yes Yes
HSUL12D Yes Yes Yes
LVTTL33D — Yes —
LVCMOS33D — Yes —
LVCMOS25D — Yes —

2.13.2. sysI/O Banking Scheme

CrossLink-NX devices have up to eight banks in total. For 40K device, there are one bank on top, two banks each at left
and right side of device, and three on the bottom side of device. For 17k device, one bank on top, one on right side and
three on the bottom side of device. The higher density CrossLink-NX device has more pins in each bank. Bank 0, Bank 1,
Bank 2, Bank 6, and Bank 7 support up to VCCIO 3.3 V while Bank 3, Bank 4, and Bank 5 support up to VCCIO 1.8 V. In
addition, Bank 3, Bank 4, and Bank 5 support two VREF inputs for flexibility to receive two different referenced input
levels on the same bank. Figure 2.27 shows the location of each bank.

44 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

VCCIO(0)

GND

Bank 0

GND GND
VCCIO(7) Bank 7* Bank 1 VCCIO(1)

GND GND
VCCIO(6) Bank 6* Bank 2* VCCIO(2)

Bank 5 Bank 4 Bank 3

GND GND GND

VREF1(5)
VCCIO(5)

VREF2(5)

VREF1(4)

VREF1(3)
VCCIO(4)

VREF2(4)

VCCIO(3)

VREF2(3)
*Note: Bank not available in LIFCL-17.

Figure 2.27. sysI/O Banking

Typical sysI/O Behavior During Power-up

The internal Power-On-Reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the
POR signal is deactivated the FPGA core logic becomes active. It is the responsibility of the user to ensure that all other
VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are
critical to the application. For more information about controlling the output logic state with valid input logic levels
during power-up in CrossLink-NX devices, see the list of technical documentation in the References section.
VCC and VCCAUX supply the power to the FPGA core fabric, whereas VCCIO supplies power to the I/O buffers. In order to
simplify the system design while providing consistent and predictable I/O behavior, it is recommended that the I/O
buffers be powered-up prior to the FPGA core fabric. For the different power supply voltage levels supported by the
I/O banks, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for detailed information.
VREF1 and VREF2
Bank 3, Bank 4, and Bank 5 can support two separate VREF input voltages, VREF1, and VREF2. To assign a VREF driver,
use IO_Type = VREF1_DRIVER or VREF2_DRIVER. To assign VREF to a buffer, use VREF1_LOAD or VREF2_LOAD.
sysI/O Standards Supported by I/O Bank
All banks can support multiple I/O standards under the VCCIO rules discussed above. Table 2.12 and Table 2.13
summarize the I/O standards supported on various sides of the CrossLink-NX device.

FPGA-DS-02049-2.1 45
CrossLink-NX Family
Data Sheet

Table 2.12. Single-Ended I/O Standards Supported on Various Sides

Standard Top Left1 Right Bottom
LVTTL33 Yes Yes Yes —
LVCMOS33 Yes Yes Yes —
LVCMOS25 Yes Yes Yes —
LVCMOS18 Yes Yes Yes —
LVCMOS15 Yes Yes Yes —
LVCMOS12 Yes Yes Yes —
LVCMOS10 Yes Yes Yes —
LVCMOS18H — — — Yes
LVCMOS15H — — — Yes
LVCMOS12H — — — Yes
LVCMOS10H — — — Yes
LVCMOS10R — — — Yes
HTSL15 I — — — Yes
SSTL 15 I, II — — — Yes
SSTL 135 I, II — — — Yes
HSUL12 — — — Yes
Note:
1. Left bank is not available in LIFCL-17.

Table 2.13. Differential I/O Standards Supported on Various Sides

Standard Top Left1 Right Bottom
LVDS — — — Yes
SUBLVDS — — — Yes
SLVS — — — Yes
SUBLVDSE Yes Yes Yes —
SUBLVDSEH — — — Yes
LVDSE Yes Yes Yes —
MIPI_D-PHY — — — Yes
HSTL15D_I — — — Yes
SSTL15D_I — — — Yes
SSTL15D_II — — — Yes
SSTL135D_I — — — Yes
SSTL135D_II — — — Yes
HSUL12D — — — Yes
LVTTL33D Yes Yes Yes —
LVCMOS33D Yes Yes Yes —
LVCMOS25D Yes Yes Yes —
Note:
1. Left bank is not available in LIFCL-17.
Hot Socketing
The CrossLink-NX devices have been carefully designed to ensure predictable behavior during power-up and power-
down. During power-up and power-down sequences, the I/O remain in tri-state until the power supply voltage is high
enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. Bank 0,
Bank 1, Bank 2, Bank 6, and Bank 7 wide range I/O (excluding MCLK/MCSN/MOSI/INITN/DONE) are hot socketable.
Bank 3, Bank 4, and Bank 5 do not support hot socketing.

46 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

2.13.3. sysI/O Buffer Configurations

This section describes the various sysI/O features available on the CrossLink-NX device. Refer to sysI/O User Guide for
Nexus Platform (FPGA-TN-02067) for detailed information.

2.14. Analog Interface

The CrossLink-NX family can provide an analog interface consisting of two Analog Digital (ADC), three continuous time
comparators, and an internal junction temperature monitoring diode. This feature is available in Commercial/Industrial
–8 and –9 speed grades and Automotive –7 speed grade. The two ADCs can operate either sequentially or
simultaneously.

2.14.1. Analog to Digital Converters

The Analog to Digital Converter is a 12-bit, 1 MSPS SAR (Successive Approximation Register) architecture converter. The
ADC supports both continuous and single shot conversion modes.
Each ADC input can be selected among eight GPIO (General Purpose I/O) input pairs, one designated analog input pair,
and three internal signals used to monitor voltage rails or an internal junction temperature sensing diode. The input
signal can be converted in either uni-polar or bi-polar mode.
The reference voltage is selectable between the 1.2 V internal reference generator and an external reference. The ADC
can convert up to a 1.8 V input signal with a 1.8 V external reference voltage. The ADC has an auto-calibration function
which calibrates the gain and offset.

2.14.2. Continuous Time Comparators

The continuous-time comparator can be used to monitor a dedicated input pair or a GPIO input pair. The output of the
comparator is provided as continuous and latched outputs.

2.14.3. Internal Junction Temperature Monitoring Diode

On-die junction temperature can be monitored using the internal junction temperature monitoring diode. The PTAT
(proportional to absolute temperature) diode voltage can be monitored by the ADC to provide a digital temperature
readout. Refer to ADC User Guide for Nexus Platform (FPGA-TN-02129) for more details.

2.15. IEEE 1149.1-Compliant Boundary Scan Testability

All CrossLink-NX devices contain various ports that can be used for configuration, including a Test Access Port (TAP).
This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can
access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded
directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of
dedicated I/O: TDI, TDO, TCK, and TMS. The test access port uses VCCIO1 for power supply. The test access port is
supported for VCCIO1 = 1.8 V - 3.3 V.
For more information, refer to sysCONFIG User Guide for Nexus Platform (FPGA-TN-02099).

FPGA-DS-02049-2.1 47
CrossLink-NX Family
Data Sheet

2.16. Device Configuration

All CrossLink-NX devices contain two ports that can be used for device configuration. The Test Access Port (TAP), which
supports bit-wide configuration, and the sysCONFIG port, support serial, quad, and byte configuration. The TAP
supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System
Configuration specification. JTAG_EN is the only dedicated configuration pin. PPROGRAMN/INITN/DONE are enabled by
default, but can be turned into GPIO. The remaining sysCONFIG pins are used as dual function pins. Refer to sysCONFIG
User Guide for Nexus Platform (FPGA-TN-02099) for more information about using the dual-use pins as general
purpose I/O.
There are various ways to configure a CrossLink-NX device:
• JTAG (TAP)
• Controller Serial Peripheral Interface (SPI) – to load from external SPI flash using x1, x2, or x4 (QSPI) interfaces.
• Inter-Integrated Circuit Bus (I2C)
• Improved Inter-Integrated Circuit Bus (I3C)
• Target SPI from a system host
• Lattice Memory Mapped Interface (LMMI), refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for
more details.
• JTAG, SSPI, MSPI, I2C, and I3C are supported for VCCIO = 1.8 V - 3.3 V
On power-up, based on the voltage level (high or low) of the PROGRAMN pin, the FPGA SRAM is configured by the
appropriate sysCONFIG port. If PROGRAMN pin is low, the FPGA is in Target configuration mode (Target SPI, Target I2C
or Target I3C) and is waiting for the correct Target Configuration port activation key. PROGRAMN must be driven high
within 50 ns of the end of transmission of the Target Configuration port activation key, that is, the deassertion of SCSN.
If no Target port is declared active before the PROGRAMN pin is sensed HIGH, the FPGA is in Master SPI booting mode.
In Controller SPI booting mode, the FPGA boots from an external SPI flash. Once a configuration port is activated, it
remains active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by
enabling the JTAG_EN pin and sending the appropriate command through the TAP port.

2.16.1. Enhanced Configuration Options

CrossLink-NX devices have enhanced configuration features such as:
• Early I/O release
• Bitstream Decryption
• Decompression Support
• Watchdog Timer support
• Dual and Multi-boot image support
Early I/O Release is a new configuration feature in which certain I/O banks are released earlier so that customer
systems have minimal disruption. For more details, refer to sysCONFIG User Guide for Nexus Platform (FPGA-TN-
02099).
Watchdog Timer is a new configuration feature that helps users add a programmable timer option for timeout
applications.
Dual-Boot and Multi-Boot Image Support
Dual-boot and multi-boot images are supported for applications requiring reliable remote updates of configuration
data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded
remotely and stored in a separate location in the configuration storage device. Any time after the update the CrossLink-
NX devices can be re-booted from this new configuration file. If there is a problem, such as corrupt data during
download or incorrect version number with this new boot image, the CrossLink-NX device can revert to the original
backup golden configuration and try again. This all can be done without power cycling the system. For more
information, refer to sysCONFIG User Guide for Nexus Platform (FPGA-TN-02099).

48 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

2.17. Single Event Upset (SEU) Handling

CrossLink-NX devices are unique in that the underlying technology used to build these devices is much more robust and
less prone to soft errors.
CrossLink-NX devices have an improved, hardware implemented, Soft Error Detection (SED) circuit which can be used
to detect SRAM errors so they can be corrected. There are two layers of SED implemented in CrossLink-NX making it
more robust and reliable.
The SED hardware in CrossLink-NX devices is part of the Configuration block. The SED module in CrossLink-NX is an
enhanced version as compared to the SED modules implemented in other Lattice devices. The configuration data is
divided into frames so that the entire FPGA can be programmed precisely with ease. The SED hardware reads data
from the FPGAs configuration memory and performs an Error Correcting Code (ECC) calculation on every frame of
configuration data (see Figure 2.1). Once an error is detected, a notification is generated and SED resumes operation.
For single bit errors, the corrected value is rewritten to the particular frame using ECC information. If more than one-bit
error is detected within one frame of configuration data, an error message is generated. CrossLink-NX devices also
have dedicated logic to perform Cycle Redundancy Code (CRC) checks for the entire bitstream, which runs in parallel
along with ECC.
After the ECC is calculated on all frames of configuration data, CRC is calculated and checked for the entire bitstream.
ECC and CRC checks do not include the contents of RAMs (EBR, Large RAM, and distributed RAM).
For further information on SED support, refer to Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus
Platform (FPGA-TN-02076).

2.18. On-Chip Oscillator

The CrossLink-NX device features two on board oscillators. Both Oscillators are controlled with internally generated
current.
The Low Frequency Oscillator (LFOSC) is tailored for low power operation and runs at a nominal frequency of 128 kHz.
The LFOSC always runs and can be used to perform always on functions with the lowest possible power. The High
Frequency Oscillator (HFOSC) runs at a nominal frequency of 450 MHz, but can be divided down to a range of 256 MHz
to 2 MHz by user attributes.

2.19. User I2C IP

The CrossLink-NX device has one hard I2C interface, which can be configured either as a controller or a Target . The
pins for the I²C interface are pre-assigned.
The interface core has the option to delay the either the input or the output data (SDA), or both, by 50 ns nominal,
using dedicated on-chip delay elements. This provides an easier interface to any external I2C components. In addition,
50 ns glitch filters are available for both SDA and SCL.
When the IP interface is configured as controller, it is able to control other devices on the I2C bus through the pre-
assigned pins. When the core is configured as a Target , the device is able to provide, for example, I/O expansion to an
I²C controller. The I²C core supports the following functionality:
• Ccontroller and Target operation
• 7-bit and 10-bit addressing
• Multi-controller arbitration support
• Clock stretching
• Up to 1 MHz data transfer speed (Standard-Mode, Fast-Mode, Fast-Mode Plus)
• General Call support
• Optional receive and transmit data FIFOs with programmable sizes
• Optionally 50 ns delay on input or output data (SDA), or both
• Hard-Connection and Programmable I/O Connection Support
• Programmable to a mode compliant with I3C requirements on legacy I2C Target Devices.
• Fast-Mode and Fast-Mode Plus Support

FPGA-DS-02049-2.1 49
CrossLink-NX Family
Data Sheet

• Disabled Clock Stretching

• 50 ns SCL and SDA Glitch Filters
• Programmable 7-bit Address
For further information on the User I²C, refer to I2C Hardened IP User Guide for Nexus Platform (FPGA-TN-02142).

2.20. Trace ID
Each CrossLink-NX device contains a unique (per device) TraceID that can be used for tracking purposes or for IP
security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits are
factory-programmed. The TraceID is accessible through the SPI, I2C, or JTAG interfaces. For further information on
TraceID, refer to Using TraceID (FPGA-TN-02084).

2.21. Density Shifting

The CrossLink-NX family is designed to ensure that different density devices in the same family and in the same
package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design
migration from lower density devices to higher density devices. In many cases, it is also possible to shift a low
utilization design targeted for a high-density device to a lower density device. However, the exact details of the final
resource utilization impact the likelihood of success in each case. An example is that some user I/O may become No
Connects in smaller devices in the same package. Refer to the CrossLink-NX Pin Migration Tables and Lattice Radiant
software for specific restrictions and limitations.

2.22. MIPI D-PHY Blocks

The top side of the device includes two hardened MIPI D-PHYs. The hardened D-PHY can be configured to support
either Camera Serial Interface (CSI-2) or Display Serial Interface (DSI) applications as either transmitter or receiver.
Below is a summary of the features supported by the hardened D-PHYs.
• Transmit and receive compliant to the MIPI Alliance D-PHY specification version 1.2
• High-Speed (HS) and Low-Power (LP) mode support (including build-in contention detection)
• Supports continuous clock mode or low power (non-continuous) clock mode
• Up to 10 Gbps per D-PHY (2500 Mbps data rate per lane)
• Supports up to four data lanes and one clock lane per hardened D-PHY
CrossLink-NX’s programmable I/O can also be configured as soft MIPI D-PHYs. The soft D-PHY can be configured to
support either Camera Serial Interface (CSI-2) or Display Serial Interface (DSI) applications as either transmitter or
receiver. Below is a summary of the features supported by the soft D-PHY.
• Transmit and receive compatible to the MIPI Alliance D-PHY specification version 1.1
• High-Speed (HS) and Low-Power (LP) mode support (does not support contention detection)
• Supports continuous clock mode or low power (non-continuous) clock mode
• Up to 6 Gbps per port (1500 Mbps data rate per lane) in 121 csfBGA package
• Up to 5 Gbps per port (1250 Mbps data rate per lane) in other packages
• Supports up to four data lanes and one clock lane per port

50 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

2.23. Peripheral Component Interconnect Express (PCIe)

The CrossLink-NX-40 Device features one lane of hardened PCIe on the top side of the device. The PCIe block
implements all three layers defined by the PCI Express Specification: Physical, Data Link, and Transaction as shown in
Figure 2.28. Below is a summary of the features supported by the PCIe block:
• Gen 1 (2.5 Gbps) and Gen 2 (5.0 Gbps) speed
• PCIe Express Base Specification 3.0 compliant including compliance with earlier PCI Express Specifications
• Multi-function support with up to four physical functions
• Endpoint
• Type 0 Configuration Registers in Endpoint Mode
• Complete Error-Handling Support
• 32-bit Core Data Width
• Many power management features including power budgeting

PCI Express Core

PHY TX

Tx
PHY Interface (PIPE)

Tx Tx
Data VC0_TX
PHY Trans
Layer Link
Layer
Layer

PHY RX Rx Rx
Rx VC0_RX
PHY Data
Trans
Layer Link
Layer
Layer

Power Management
Error Reporting (AER)
CLK, CONFIGURATION, AND MANAGEMENT
LMMI
CONFIGURATION REGISTERS

Figure 2.28. PCIe Core

The hardened PCIe block can be instantiated with the primitive PCIe through Lattice Radiant software however, it is not
recommended to directly instantiate the PCIe primitive itself. It is highly recommended to generate the PCIe Endpoint
Soft IP through the Radiant IP Catalog and IP Block Wizard instead. In Figure 2.29, the PCIe core is configured as an
Endpoint using a soft IP wrapper that provides useful functions such as bridging support for bus interfaces and DMA
applications. In addition to the standard Transaction Layer Packet (TLP) interface, the data interface can also be
configured to be AXI4 or AHB-Lite as well. The PCIe hardened block also features a register interface for LMMI and User
Configuration Space Register Interface (UCFG). The PCIe block has many registers which contain information about the
current status of the PCIe block as well as the capability to dynamically switch PCIe settings. One easy way to access
these registers is through the Reveal Controller Tool.
For more information about the PCIe soft IP, refer to the PCIe Endpoint IP Core document.

FPGA-DS-02049-2.1 51
CrossLink-NX Family
Data Sheet

Top

Soft Logic PCIe Hard IP rxp_i/

AHB-Lite Rx TLP rxpn_i
/AXI-4
Data Interface Conversion Tx TLP

txp_o/
Transaction txpn_o
Link Layer PHY Layer
Layer
LMMI
AHB-Lite
/APB refclkp_i/
Register Interface Conversion UCFG refclkn_i

Figure 2.29. PCIe Soft IP Wrapper

2.24. Cryptographic Engine

The CrossLink-NX family of devices support several cryptographic features that helps customer secure their design.
Some of the key cryptographic features include Advanced Encryption Standard (AES), Hashing Algorithms and True
Random Number Generator (TRNG). The CrossLink-NX device also features bitstream encryption (using AES-256), used
for protecting confidential FPGA bitstream data, and bitstream authentication (using ECDSA), which maintains
bitstream integrity and protects the FPGA design bitstream from copying and tampering.
The Cryptographic Engine (CRE) is the main engine, which is responsible for the bitstream encryption as well as
authentication of the CrossLink-NX device. Once the bitstream is authenticated and the device is ready for user
functions, the CRE is available for users to implement various cryptographic functions in the FPGA design. To enable
specific cryptographic function, the CRE has to be configured by setting a few registers.
The Cryptographic Engine supports the below user-mode features:
• True Random Number generator (TRNG)
• Secure Hashing Algorithm (SHA)-256 bit
• Message Authentication Codes (MACs) – HMAC
• Lattice Memory Mapped Interface (LMMI) interface to user logic
• High Speed Port (HSP) for FIFO-based streaming data transfer

Cryptographic Engine (CRE)

Unique ID
Control Register
LMMI / True Random Number Generator (TRNG)
FPGA High Speed Port
CRE Registers Advanced Encryption Standard (AES)
Fabric

SHA256
Bitstream Encryption
HMAC SHA256
Bitstream Authentication

Figure 2.30. Cryptographic Engine Block Diagram

52 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

3. DC and Switching Characteristics for Commercial and

Industrial
All specifications in this Chapter are characterized within recommended operating conditions unless otherwise
specified.

3.1. Absolute Maximum Ratings

Table 3.1. Absolute Maximum Ratings
Symbol Parameter Min Max Unit
VCC, VCCECLK Supply Voltage –0.5 1.10 V
VCCAUX, VCCAUXA, Supply Voltage –0.5 1.98 V
VCCAUXH3, VCCAUXH4,
VCCAUXH5
VCCIO0, 1, 2, 6, 7 I/O Supply Voltage –0.5 3.63 V
VCCIO3, 4, 5 I/O Supply Voltage –0.5 1.98 V
VCCPLL_DPHY0, 1 Hardened D-PHY PLL Supply Voltage –0.5 1.10 V
VCCPLLSD0 SerDes Block PLL Supply Voltage –0.5 1.98 V
VCCA_DPHY0, 1 Analog Supply Voltage for Hardened D-PHY –0.5 1.98 V
VCC_DPHY0, 1 Digital Supply Voltage for Hardened D-PHY –0.5 1.10 V
VCCSD0 SerDes Supply Voltage –0.5 1.10 V
VCCADC18 ADC Block 1.8 V Supply Voltage –0.5 1.98 V
VCCAUXSD SerDes and AUX Supply Voltage –0.5 1.98 V
— Input or I/O Voltage Applied, Bank 0, Bank –0.5 3.63 V
1,Bank 2, Bank 6, Bank 7
— Input or I/O Voltage Applied, Bank 3, Bank 4, –0.5 1.98 V
Bank 5
— Voltage Applied on SerDes Pins –0.5 1.98 V
TA Storage Temperature (Ambient) –65 +150 °C
TJ Junction Temperature — +125 °C
Notes:
1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. All VCCAUX should be connected on PCB.

FPGA-DS-02049-2.1 53
CrossLink-NX Family
Data Sheet

3.2. Recommended Operating Conditions1, 2, 3

Table 3.2. Recommended Operating Conditions
Symbol Parameter Conditions Min Typ. Max Unit
VCC, VCCECLK Core Supply Voltage VCC = 1.0 0.95 1.00 1.05 V
Bank 0, Bank 1, Bank 2, Bank 6,
VCCAUX Auxiliary Supply Voltage 1.746 1.80 1.89 V
Bank 7
VCCAUXH3/4/5 Auxiliary Supply Voltage Bank 3, Bank 4, Bank 5 1.746 1.80 1.89 V
Auxiliary Supply Voltage for
VCCAUXA — 1.746 1.80 1.89 V
core logic
VCCIO = 3.3 V, Bank 0, Bank 1,
3.135 3.30 3.465 V
Bank 2, Bank 6, Bank 7
VCCIO = 2.5 V, Bank 0, Bank 1,
2.375 2.50 2.625 V
Bank 2, Bank 6, Bank 7
VCCIO = 1.8 V, All Banks 1.71 1.80 1.89 V
VCCIO I/O Driver Supply Voltage VCCIO = 1.5 V, All Banks4 1.425 1.50 1.575 V
VCCIO = 1.35 V, All Banks (For
1.2825 1.35 1.4175 V
DDR3L Only)
VCCIO = 1.2 V, All Banks4 1.14 1.20 1.26 V
VCCIO = 1.0 V, Bank 3, Bank 4,
0.95 1.00 1.05 V
Bank 5
D-PHY External Power Supplies
D-PHY Analog Power
VCCA_D-PHY — 1.71 1.80 1.89 V
Supply
VCC_D-PHY D-PHY Digital Power Supply — 0.95 1.00 1.05 V
VCCPLL_D-PHY D-PHY PLL Power Supply — 0.95 1.00 1.05 V
ADC External Power Supplies
VCCADC18 ADC 1.8 V Power Supply — 1.71 1.80 1.89 V
SerDes Block External Power Supplies
Supply Voltage for SerDes
VCCSD0 — 0.95 1.00 1.05 V
Block and SerDes I/O
SerDes Block PLL Supply
VCCPLLSD0 — 1.71 1.80 1.89 V
Voltage
SerDes Block Auxiliary
VCCAUXSD — 1.71 1.80 1.89 V
Supply Voltage
Operating Temperature
Junction Temperature,
tJCOM — 0 — 85 °C
Commercial Operation
Junction Temperature,
tJIND — –40 — 100 °C
Industrial Operation
Notes:
1. For correct operation, all supplies must be held in their valid operation voltage range.
2. All supplies with same voltage should be from the same voltage source. Proper isolation filters are needed to properly isolate
noise from each other.
3. Common supply rails must be tied together except SerDes.
4. MSPI (Bank0) and JTAG, SSPI, I2C, and I3C (Bank 1) ports are supported for VCCIO = 1.8 V to 3.3 V.

54 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

3.3. Power Supply Ramp Rates

Table 3.3. Power Supply Ramp Rates
Symbol Parameter Min Typ Max Unit
tRAMP Power Supply ramp rates for all supplies 1 0.1 — 50 V/ms
Notes:
1. Assumes monotonic ramp rates.
2. All supplies need to be in the operating range as defined in Recommended Operating Conditions1, when the device has
completed configuration and entering into User Mode. Supplies that are not in the operating range needs to be adjusted to
faster ramp rate, or users have to delay configuration or wake up.

3.4. Power up Sequence

Power-On-Reset (POR) puts the CrossLink-NX device into a reset state. There is no power up sequence required for the
CrossLink-NX device.
Table 3.4. Power-On Reset
Symbol Parameter Min Typ Max Unit
Power-On-Reset ramp-up trip VCC 0.73 — 0.83 V
VPORUP point (Monitoring VCC, VCCAUX, VCCAUX 1.34 — 1.71 V
VCCI00, and VCCI01) VCCIO0,VCCI01 0.89 — 1.05 V
Power-On-Reset ramp-up trip VCC 0.51 — 0.81 V
VPORDN
point (Monitoring VCC and VCCAUX) VCCAUX 1.38 — 1.54 V

3.5. On-Chip Programmable Termination

The CrossLink-NX devices support a variety of programmable on-chip terminations options, including:
• Dynamically switchable Single-Ended Termination with programmable resistor values of 40 Ω, 50 Ω, 60 Ω, or 75 Ω.
• Common mode termination of 100 Ω for differential inputs.

V CCI O Zo = 50
TERM
Zo = 40 , 50 , 60 , or 75
control
to VCCIO /2
Zo
Zo +
2Zo -
Zo +
- Zo
VREF

OFF-chip ON-chip OFF-chip ON-chip

Parallel Single-Ended Input Differential Input

Figure 3.1. On-Chip Termination

See Table 3.5 for termination options for input modes.

FPGA-DS-02049-2.1 55
CrossLink-NX Family
Data Sheet

Table 3.5. On-Chip Termination Options for Input Modes

IO_TYPE Differential Termination Resistor1, 2 Terminate to VCCIO/21, 2
subLVDS 100, OFF OFF
SLVS 100, OFF OFF
MIPI_DPHY 100 OFF
HSTL15D_I 100, OFF OFF
SSTL15D_I 100, OFF OFF
SSTL135D_I 100, OFF OFF
HSUL12D 100, OFF OFF
LVCMOS15H OFF OFF
LVCMOS12H OFF OFF
LVCMOS10H OFF OFF
LVCMOS12H OFF OFF
LVCMOS10H OFF OFF
LVCMOS18H OFF OFF, 40, 50, 60, 75
HSTL15_I OFF 50
SSTL15_I OFF OFF, 40, 50, 60, 75
SSTL135_I OFF OFF, 40, 50, 60, 75
HSUL12 OFF OFF, 40, 50, 60, 75
Notes:
1. TERMINATE to VCCIO/2 (Single-Ended) and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have one setting per
bank. Only left and right banks have this feature.
2. Use of TERMINATE to VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip
termination tolerance –10%/+60%.
Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for on-chip termination usage and value ranges.

3.6. Hot Socketing Specifications

Table 3.6. Hot Socketing Specifications for GPIO
Symbol Parameter Condition Min Typ Max Unit
Input or I/O Leakage Current for 0 < VIN < VIH(max)
Wide Range I/O (excluding 0 < VCC < VCC(max)
IDK MCLK/MCSN/MOSI/INITN/DONE) -1.5 — 1.5 mA
0 < VCCIO < VCCIO (max)
0 < VCCAUX < VCCAUX (max)
Notes:
• IDK is additive to IPU, IPD, or IBH.
• Hot socketing specs are defined at a device junction temperature of 85 °C or below. When the device junction temperature is
above 85 oC, the IDK current can exceed the above spec.
• Going beyond the hot socketing ranges specified here will cause exponentially higher Leakage currents and potential reliability
issues. A total of 64 mA per 8 I/O should not be exceeded.

3.7. ESD Performance

Refer to the CrossLink-NX Product Family Qualification Summary for complete Commercial and Industrial grade
qualification data, including ESD performance.

56 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

3.8. DC Electrical Characteristics

Table 3.7. DC Electrical Characteristics – Wide Range
Symbol Parameter Condition Min Typ Max Unit
Input or I/O Leakage current
IIL, IIH1 0 ≤ VIN ≤ VCCIO — — 10 µA
(Commercial/Industrial)
IIH2 Input or I/O Leakage current VCCIO ≤ VIN ≤ VIH (max) — — 100 µA
I/O Weak Pull-up Resistor
IPU 0 ≤ VIN ≤ 0.7 × VCCIO –30 — –150 µA
Current
I/O Weak Pull-down Resistor
IPD VIL (max) ≤ VIN ≤ VCCIO 30 — 150 µA
Current
IBHLS Bus Hold Low Sustaining Current VIN = VIL (max) 30 — µA
IBHHS Bus Hold High Sustaining Current VIN = 0.7 × VCCIO –30 — µA
IBHLO Bus hold low Overdrive Current 0 ≤ VIN ≤ VCCIO — — 150 µA
IBHHO Bus hold high Overdrive Current 0 ≤ VIN ≤ VCCIO — — –150 µA
VBHT Bus Hold Trip Points — VIL (max) — VIH (min) V
Notes:
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus
Maintenance circuits are disabled.
2. The input leakage current IIH is the worst case input leakage per GPIO when the pad signal is high and also higher than the bank
VCCIO. This is considered a mixed mode input.

Table 3.8. DC Electrical Characteristics – High Speed

Symbol Parameter Condition Min Typ Max Unit
IIL, IIH1 Input or I/O Leakage 0 ≤ VIN ≤ VCCIO — — 10 µA
I/O Weak Pull-up Resistor —
IPU 0 ≤ VIN ≤ 0.7 × VCCIO –30 –150 µA
Current
I/O Weak Pull-down Resistor —
IPD VIL (max) ≤ VIN ≤ VCCIO 30 150 µA
Current
IBHLS Bus Hold Low Sustaining Current VIN = VIL (max) 30 — — µA
IBHHS Bus Hold High Sustaining Current VIN = 0.7 × VCCIO –30 — — µA
IBHLO Bus hold low Overdrive Current 0 ≤ VIN ≤ VCCIO — — 150 µA
IBHHO Bus hold high Overdrive Current 0 ≤ VIN ≤ VCCIO — — –150 µA
VIL
VBHT Bus Hold Trip Points — — VIH (min) V
(max)
Note:
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus
Maintenance circuits are disabled.

Table 3.9. Capacitors – Wide Range

Symbol Parameter Condition Min Typ Max Unit
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
C11 I/O Capacitance1 — 6 — pF
VCC = typ., VIO = 0 to VCCIO + 0.2V
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
C21 Dedicated Input Capacitance1 — 6 — pF
VCC = typ., VIO = 0 to VCCIO + 0.2V
Note:
1. TA 25 oC, f = 1.0 MHz.

FPGA-DS-02049-2.1 57
CrossLink-NX Family
Data Sheet

Table 3.10. Capacitors – High Performance

Symbol Parameter Condition Min Typ Max Unit
VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ.,
C11 I/O Capacitance1 — 6 — pF
VIO = 0 to VCCIO + 0.2V
VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ.,
C21 Dedicated Input Capacitance1 — 6 — pF
VIO = 0 to VCCIO + 0.2V
VCCA_D-PHY = 1.8 V, VCC = typ., VIO = 0
C31 D-PHY I/O Capacitance — 5 — pF
to VCCA_D-PHY + 0.2V
VCCSD0 = 1.0 V, VCC = typ., VIO = 0 to
C41 SerDes I/O Capacitance — 5 — pF
VCCSD0 + 0.2 V
Note:
1. TA 25 oC, f = 1.0 MHz.

Table 3.11. Single Ended Input Hysteresis – Wide Range

IO_TYPE VCCIO TYP Hysteresis
LVCMOS33 3.3 V 250 mV
3.3 V 200 mV
LVCMOS25
2.5 V 250 mV
LVCMOS18 1.8 V 180 mV
LVCMOS15 1.5 V 50 mV
LVCMOS12 1.2 V 0
LVCMOS10 1.2 V 0

Table 3.12. Single Ended Input Hysteresis – High Performance

IO_TYPE VCCIO TYP Hysteresis
LVCMOS18H 1.8 V 180 mV
1.8 V 50 mV
LVCMOS15H
1.5 V 150 mV
LVCMOS12H 1.2 V 0
LVCMOS10H 1.0 V 0
MIPI-LP-RX 1.2 V >25 mV

3.9. Supply Currents

For estimating and calculating current, use Power Calculator in Lattice Design software.
This operating and peak current is design dependent, and can be calculated in Lattice Design Software. Some blocks
can be placed into low current standby modes. Refer to Power Management and Calculation for CrossLink-NX Devices
(FPGA-TN-02075).

58 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

3.10. sysI/O Recommended Operating Conditions

Table 3.13. sysI/O Recommended Operating Conditions
Support Banks VCCIO (Input) VCCIO (Output)
Standard
Typ. Typ.
Single-Ended
LVCMOS33 0, 1, 2, 6, 7 3.3 3.3
LVTTL33 0, 1, 2, 6, 7 3.3 3.3
LVCMOS25¹, ² 0, 1, 2, 6, 7 2.5, 3.3 2.5
LVCMOS18¹, ² 0, 1, 2, 6, 7 1.2, 1.5, 1.8, 2.5, 3.3 1.8
LVCMOS18H 3, 4, 5 1.8 1.8
LVCMOS15¹, ² 0, 1, 2, 6, 7 1.2, 1.5, 1.8, 2.5, 3.3 1.5
LVCMOS15H¹ 3, 4, 5 1.5, 1.8 1.5
LVCMOS12¹, ² 0, 1, 2, 6, 7 1.2, 1.5, 1.8, 2.5, 3.3 1.2
LVCMOS12H¹ 3, 4, 5 1.2, 1.357, 1.5, 1.8 1.2
LVCMOS10¹ 0, 1, 2, 6, 7 1.2, 1.5, 1.8, 2.5, 3.3 —
LVCMOS10H¹ 3, 4, 5 1.0, 1.2, 1.357, 1.5, 1.8 1.0
LVCMOS10R¹ 3, 4, 5 1.0, 1.2, 1.357, 1.5, 1.8 —
SSTL135_I, SSTL135_II3 3, 4, 5 1.357 1.35
SSTL15_I, SSTL15_II3 3, 4, 5 1.58 1.58
HSTL15_I3 3, 4, 5 1.58 1.58
HSUL123 3, 4, 5 1.2 1.2
MIPI D-PHY LP Input6 3, 4, 5 1.2 1.2
Differential6
LVDS 3, 4, 5 1.2, 1.35, 1.5, 1.8 1.8
LVDSE5 0, 1, 2, 6, 7 — 2.5
subLVDS 3, 4, 5 1.2, 1.35, 1.5, 1.8 —
subLVDSE5 0, 1, 2, 6, 7 — 1.8
subLVDSEH5 3, 4, 5 — 1.8
SLVS6 3, 4, 5 1.0, 1.2, 1.357, 1.5, 1.84 1.2, 1.357, 1.5, 1.8 4
MIPI D-PHY6 3, 4, 5 1.2 1.2
LVCMOS33D5 0, 1, 2, 6, 7 — 3.3
LVTTL33D5 0, 1, 2, 6, 7 — 3.3
LVCMOS25D5 0, 1, 2, 6, 7 — 2.5
SSTL135D_I, SSTL135D_II5 3, 4, 5 — 1.357
SSTL15D_I, SSTL15D_II5 3, 4, 5 — 1.5
HSTL15D_I5 3, 4, 5 — 1.5
HSUL12D5 3, 4, 5 — 1.2
Notes:
1. Single-ended input can mix into I/O Banks with VCCIO different from the standard requires due to some of these input standards
use internal supply voltage source (VCC, VCCAUX) to power the input buffer, which makes them to be independent of V CCIO
voltage. For more details, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067). The following is a brief guideline to
follow:
a. Weak pull-up on the I/O must be set to OFF.
b. Bank 3, Bank 4, and Bank 5 I/O can only mix into banks with VCCIO higher than or equal to the pin standard, due to
clamping diode on the pin in these banks. Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 does not have this restriction.
c. LVCMOS25 uses VCCIO supply on input buffer in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7. It can be supported with VCCIO =
3.3 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO. Hysteresis has to be disabled
when using 3.3 V supply voltage.
d. LVCMOS15 uses VCCIO supply on input buffer in Bank 3, Bank 4, and Bank 5. It can be supported with VCCIO = 1.8 V to meet
the VIH and VIL requirements, but there is additional current drawn on VCCIO.

FPGA-DS-02049-2.1 59
CrossLink-NX Family
Data Sheet

2. Single-ended LVCMOS inputs can mixed into I/O Banks with different VCCIO, providing weak pull-up is not used.
For additional information on Mixed I/O in Bank VCCIO, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067).
3. These inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses VCCAUXH
power supply. These inputs require the VREF pin to provide the reference voltage in the Bank. Refer to sysI/O User Guide for
Nexus Platform (FPGA-TN-02067) for details.
4. All differential inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses
VCCAUXH power supply. There is no differential input signaling supported in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7.
5. These outputs are emulating differential output pair with single-ended output drivers with true and complement outputs
driving on each of the corresponding true and complement output pair pins. The common mode voltage, VCM, is ½ × VCCIO. Refer
to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details.
6. Soft MIPI D-PHY HS using sysI/O is supported with SLVS input and output that can be placed in banks with VCCIO voltage shown
in SLVS. D-PHY with HS and LP modes supported needs to be placed in banks with VCCIO voltage = 1.2 V. Soft MIPI D-PHY LP input
and output using sysI/O are supported with LVCMOS12.
7. VCCIO = 1.35 V is only supported in Bank 3, Bank 4, and Bank 5, for use with DDR3L interface in the bank. These Input and Output
standards can fit into the same bank with the VCCIO = 1.35 V.
8. LVCMOS15 input uses VCCIO supply voltage. If VCCIO is 1.8 V, the DC levels for LVCMOS15 are still met, but there could be increase
in input buffer current.

3.11. sysI/O Single-Ended DC Electrical Characteristics

Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O
Input/Output VIL VIH VOL Max VOH Min
IOL(mA) IOH(mA)
Standard2 Min (V) Max (V) Min (V) Max (V) (V) (V)
— 2, 4, 8, -2, -4, -8,
LVTTL33
0.8 2.0 3.4654 0.4 VCCIO – 0.4 12, 16, -12, -16,
LVCMOS33
“50RS”3 “50RS”3
— 2, 4, 8, -2, -4, -8,
LVCMOS25 0.7 1.7 3.4654 0.4 VCCIO – 0.45 10, -10,
“50RS”3 “50RS”3
— 3.4654 2, 4, 8, -2, -4, -8,
LVCMOS18 0.35 × VCCIO 0.65 × VCCIO 0.4 VCCIO – 0.45
“50RS”3 “50RS”3
LVCMOS15 — 0.35 × VCCIO 0.65 × VCCIO 3.4654 0.4 VCCIO – 0.4 2, 4 -2, -4
LVCMOS12 — 0.35 × VCCIO 0.65 × VCCIO 3.4654 0.4 VCCIO – 0.4 2, 4 -2, -4
LVCMOS10 — 0.35 × VCCIO 0.65 × VCCIO 3.4654 No O/P Support
Notes:
1. For electro-migration, the average DC current drawn by the I/O pads within a bank of I/O shall not exceed 10 mA per I/O
average.
2. For the types of I/O standard supported in which bank, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for
details.
3. Select “50RS” in driver strength is selecting 50 Ω series impedance driver.
4. VIH (MAX) for inputs on these standards (in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7) can go up to 3.465 V if the input clamp is
OFF. Otherwise, the input cannot be higher than VCCIO + 0.3 V.

60 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O

Input/Output VIL VIH VOL Max VOH Min
IOL (mA) IOH (mA)
Standard2 Min (V) Max (V) Min (V) Max (V) (V) (V)
-2, -4, -8,
0.35 × VCCIO + 2, 4, 8, 12,
LVCMOS18H — 0.65 × VCCIO 0.4 VCCIO – 0.45 -12,
VCCIO 0.3 “50RS”3
“50RS”3
0.35 × VCCIO + 2, 4, 8, -2, -4, -8,
LVCMOS15H — 0.65 × VCCIO 0.4 VCCIO – 0.4
VCCIO 0.3 “50RS”3 “50RS”3
0.35 × VCCIO + 2, 4, 8, -2, -4, -8,
LVCMOS12H — 0.65 × VCCIO 0.4 VCCIO – 0.4
VCCIO 0.3 “50RS”3 “50RS”3
0.35 × VCCIO + 0.27 ×
LVCMOS10H — 0.65 × VCCIO 0.75 × VCCIO 2, 4 -2, -4
VCCIO 0.3 VCCIO
VCCIO +
SSTL15_I — VREF – 0.10 VREF + 0.1 0.30 VCCIO – 0.30 7.5 –7.5
0.3
VCCIO +
SSTL15_II — VREF – 0.10 VREF + 0.1 0.30 VCCIO – 0.30 8.8 –8.8
0.3
VCCIO +
HSTL15_I — VREF – 0.10 VREF + 0.1 0.40 VCCIO – 0.40 8 –8
0.3
VCCIO +
SSTL135_I — VREF – 0.09 VREF + 0.09 0.27 VCCIO – 0.27 6.75 –6.75
0.3
VCCIO +
SSTL135_II — VREF – 0.09 VREF + 0.09 0.27 VCCIO – 0.27 8 –8
0.3
VCCIO +
LVCMOS10R — VREF – 0.10 VREF + 0.10 — — — —
0.3
VCCIO + 8.8, 7.5, -8.8, -7.5,
HSUL12 — VREF – 0.10 VREF + 0.10 0.3 VCCIO – 0.3
0.3 6.25, 5 -6.25, -5
Notes:
1. For electro-migration, the average DC current drawn by the I/O pads within a bank of I/O shall not exceed 10 mA per I/O
average.
2. For the types of I/O standard supported in which bank, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for
details.
3. Select “50RS” in driver strength is selecting 50 Ω series impedance driver.

Table 3.16. I/O Resistance Characteristics

Parameter Description Test Conditions Min Typ Max Unit
Output Drive Resistance when 50RS
50RS VCCIO = 1.8 V, 2.5 V, or 3.3 V — 50 — Ω
Drive Strength Selected
Input Differential Termination Bank 3, Bank 4, and Bank 5 for I/O
RDIFF — 100 — Ω
Resistance selected to be differential
36 40 64
SE Input Input Single Ended Termination Bank 3, Bank 4, and Bank 5 for I/O 46 50 80
Ω
Termination Resistance selected to be Single Ended 56 60 96
71 75 120

FPGA-DS-02049-2.1 61
CrossLink-NX Family
Data Sheet

Table 3.17. VIN Maximum Overshoot/Undershoot Allowance – Wide Range1, 2

AC Voltage Overshoot % of UI at –40 °C to 100 °C AC Voltage Undershoot % of UI at –40 °C to 100 °C
VCCIO + 0.4 100.0% –0.4 100.0%
VCCIO + 0.5 100.0% –0.5 44.2%
VCCIO + 0.6 94.0% –0.6 10.1%
VCCIO + 0.7 21.0% –0.7 1.3%
VCCIO + 0.8 10.2% –0.8 0.3%
VCCIO + 0.9 2.5% –0.9 0.1%
Notes:
1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the
values in this table.
2. For UI less than 20 µs.

Table 3.18. VIN Maximum Overshoot/Undershoot Allowance – High Performance1, 2

AC Voltage Overshoot % of UI at –40 °C to 100 °C AC Voltage Undershoot % of UI at –40 °C to 100 °C
VCCIO + 0.5 100.0% –0.5 100.0%
VCCIO + 0.6 47.3% –0.6 47.3%
VCCIO + 0.7 10.9% –0.7 10.9%
VCCIO + 0.8 2.7% –0.8 2.7%
VCCIO + 0.9 0.7% –0.9 0.7%
Notes:
1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the
values in this table.
2. For UI less than 20 µs.

3.12. sysI/O Differential DC Electrical Characteristics

3.12.1. LVDS
LVDS input buffer on CrossLink-NX is powered by VCCAUX = 1.8 V, and protected by the bank VCCIO. Therefore, the LVDS
input voltage cannot exceed the bank VCCIO voltage. LVDS output buffer is powered by the Bank VCCIO at 1.8 V.
LVDS can only be supported in Bank 3, Bank 4, and Bank 5. LVDS25 output can be emulated with LVDS25E in Bank 0,
Bank 1, Bank 2, Bank 6, and Bank 7. This is described in LVDS25E (Output Only) section.

62 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Table 3.19. LVDS DC Electrical Characteristics1

Parameter Description Test Conditions Min Typ Max Unit
VINP, VINM Input Voltage — 0 — 1.603 V
VICM Input Common Mode Voltage Half the sum of the two Inputs 0.05 — 1.55 2 V
VTHD Differential Input Threshold Difference between the two Inputs ±100 — — mV
IIN Input Current Power On or Power Off — — ±10 µA
VOH Output High Voltage for VOP or VOM RT = 100 Ω — 1.425 1.60 V
VOL Output Low Voltage for VOP or VOM RT = 100 Ω 0.9 V 1.075 — V
VOD Output Voltage Differential (VOP - VOM), RT = 100 Ω 250 350 450 mV
Change in VOD Between High and
VOD — — — 50 mV
Low
VOCM Output Common Mode Voltage (VOP + VOM)/2, RT = 100 Ω 1.125 1.25 1.375 V
VOCM Change in VOCM, VOCM(MAX) - VOCM(MIN) — — — 50 mV
VOD = 0 V Driver outputs shorted to
ISAB Output Short Circuit Current — — 12 mA
each other
VOS Change in VOS between H and L — — — 50 mV
Notes:
1. LVDS input or output are supported in Bank 3, Bank 4, and Bank 5. LVDS input uses VCCAUX on the differential input comparator,
and can be located in any VCCIO voltage bank. LVDS output uses VCCIO on the differential output driver, and can only be located in
bank with VCCIO = 1.8 V.
2. VICM is depending on VID, input differential voltage, so the voltage on pin cannot exceed VINP/INM(min/max) requirements. VICM(min) =
VINP/ INM (min) + ½ VID, VICM(max) = VINP/ INM (max) – ½ VID. Values in the table is based on minimum VID of +/- 100 mV.
3. VINP and VINM (max) must be less than or equal to VCCIO in all cases.

3.12.2. LVDS25E (Output Only)

Three sides of the CrossLink-NX devices, Top, Left and Right, support LVDS25 outputs with emulated complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3.2 is
one possible solution for point-to-point signals.
Table 3.20. LVDS25E DC Conditions
Parameter Description Typical Unit
VCCIO Output Driver Supply (±5%) 2.50 V
ZOUT Driver Impedance 20 Ω
RS Driver Series Resistor (±1%) 158 Ω
RP Driver Parallel Resistor (±1%) 140 Ω
RT Receiver Termination (±1%) 100 Ω
VOH Output High Voltage 1.43 V
VOL Output Low Voltage 1.07 V
VOD Output Differential Voltage 0.35 V
VCM Output Common Mode Voltage 1.25 V
ZBACK Back Impedance 100.5 Ω
IDC DC Output Current 6.03 mA

FPGA-DS-02049-2.1 63
CrossLink-NX Family
Data Sheet

VCCIO = 2.5 V (± 5%)

RS = 158
(± 1%)
8 mA
LVCMOS25

RP = 140 RT = 100 +
VCCIO = 2.5 V (± 5%) -
RS = 158 (± 1%) (± 1%)
(± 1%)

8 mA
LVCMOS25
Transmission line, Zo = 100 differential

ON-chip OFF-chip OFF-chip ON-chip

Figure 3.2. LVDS25E Output Termination Example

3.12.3. SubLVDS (Input Only)

SubLVDS is a reduced-voltage form of LVDS signaling, very similar to LVDS. It is a standard used in many camera types
of applications. Being similar to LVDS, the CrossLink-NX devices can support the subLVDS input signaling with the same
LVDS input buffer. The output for subLVDS is implemented in subLVDSE/subLVDSEH with a pair of LVCMOS18 output
drivers (see SubLVDSE/SubLVDSEH (Output Only) section).
Table 3.21. SubLVDS Input DC Electrical Characteristics
Parameter Description Test Conditions Min Typ Max Unit
VID Input Differential Threshold Voltage Over VICM range 70 150 200 mV
VICM Input Common Mode Voltage Half the sum of the two Inputs 0.4 0.9 1.41 V
Note:
1. VICM + 1/2 VID cannot exceed the bank VCCIO in all cases.

Sub-LVDS Driver PCB Traces, Connectors or Cables

Z0 = 50

+ +
RT = 100
100 differential ± 1%*

– –
Z0 = 50

Off-chip On-chip

Figure 3.3. SubLVDS Input Interface

3.12.4. SubLVDSE/SubLVDSEH (Output Only)

64 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Table 3.22. SubLVDS Output DC Electrical Characteristics

Parameter Description Test Conditions Min Typ Max Unit
VOD Output Differential Voltage Swing — — 150 — mV
VOCM Output Common Mode Voltage Half the sum of the two Outputs — 0.9 — V

VCCIO = +1.8 V PCB Traces, Connectors or Cables

Z0 = 50
Rs = 267 ±1%
+ +
SubLVDS Output
Rp = 121 ±1% 100 diff erential RT = 100 ±1% Sub-LVDS Recev ier
SubLVDSE
SubLVDSEH
– –
Rs = 267 ±1%
Z0 = 50

On-chip Off-chip On-chip Off-chip

Figure 3.4. SubLVDS Output Interface

3.12.5. SLVS
Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13
(SLVS-400) standard. This standard evolved from the traditional LVDS standard with smaller voltage swings and a lower
common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power.
The CrossLink-NX devices receive SLVS differential input with the LVDS input buffer. This LVDS input buffer is design to
cover wide input common mode range that can meet the SLVS input standard specified by the JEDEC standard.
Table 3.23. SLVS Input DC Characteristics
Parameter Description Test Conditions Min Typ Max Unit
VID Input Differential Threshold Voltage Over VICM range 70 — — mV
VICM Input Common Mode Voltage Half the sum of the two Inputs 70 200 330 mV

The SLVS output on CrossLink-NX is supported with the LVDS drivers found in Bank 3, Bank 4, and Bank 5. The LVDS
driver on CrossLink-NX is a current controlled driver. It can be configured as LVDS driver, or configured with the 100 Ω
differential termination with center-tap set to VOCM at 200 mV. This means the differential output driver can be placed
into bank with VCCIO = 1.2 V, 1.5 V, or 1.8 V, even if it is powered by VCCIO.
Table 3.24. SLVS Output DC Characteristics
Parameter Description Test Conditions Min Typ Max Unit
1.2,
VCCIO Bank VCCIO — –5% 1.5, + 5% V
1.8
VOD Output Differential Voltage Swing — 140 200 270 mV
VOCM Output Common Mode Voltage Half the sum of the two Outputs 150 200 250 mV
ZOS Single-Ended Output Impedance — 37.5 50 80 Ω

FPGA-DS-02049-2.1 65
CrossLink-NX Family
Data Sheet

Figure 3.5. SLVS Interface

3.12.6. Soft MIPI D-PHY

When Soft D-PHY is implemented inside the FPGA logic, the I/O interface needs to use sysI/O buffers to connect to
external D-PHY pins.
The CrossLink-NX sysI/O provides support for SLVS, as described in SLVS section, plus the LVCMOS12 input / output
buffers together to support the High Speed (HS) and Low Power (LP) mode as defined in MIPI Alliance Specification for
D-PHY.
To support MIPI D-PHY with SLVS (LVDS) and LVCMOS12, the bank VCCIO cannot be set to 1.5 V or 1.8 V. It has to
connect to 1.2 V or 1.1 V.
All other DC parameters are the same as listed in SLVS section. DC parameters for the LP driver and receiver are the
same as listed in LVCMOS12.

66 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

LVCMOS12
LP Data_P

LPenable
HSenable MIPI Receiver

100 Diff
+ +
HS Data Z0=50
- -
SLVS

LPenable

LP Data_N
LVCMOS12

MIPI_LP_RX
On-Chip
RXLP_P

MIPI Divider

+ +
HS Data Z0=50
- -
LVDS

MIPI_LP_RX

RXLP_N

Figure 3.6. MIPI Interface

FPGA-DS-02049-2.1 67
CrossLink-NX Family
Data Sheet

Table 3.25. Soft D-PHY Input Timing and Levels

Symbol Description Conditions Min Typ Max Unit
High Speed (Differential) Input DC Specifications
VCMRX(DC) Common-mode Voltage in High Speed Mode — 70 — 330 mV
VIDTH Differential Input HIGH Threshold — 70 — — mV
VIDTL Differential Input LOW Threshold — — — -70 mV
VIHHS Input HIGH Voltage (for HS mode) — — — 460 mV
VILHS Input LOW Voltage — –40 — — mV
VTERM-EN Single-ended voltage for HS Termination Enable4 — — — 450 mV
ZID Differential Input Impedance — 80 100 125 Ω
High Speed (Differential) Input AC Specifications
ΔVCMRX(HF)1 Common-mode Interference (>450 MHz) — — — 100 mV
ΔVCMRX(LF)2, 3 Common-mode Interference (50 MHz - 450 MHz) — –50 — 50 mV
CCM Common-mode Termination — 60 pF
Low Power (Single-Ended) Input DC Specifications
VIH Low Power Mode Input HIGH Voltage — 740 — — mV
VIL Low Power Mode Input LOW Voltage — — — 480 mV
VIL-ULP Ultra Low Power Input LOW Voltage — — — 300 mV
VHYST Low Power Mode Input Hysteresis — 25 — — mV
℮SPIKE Input Pulse Rejection — — — 300 V∙ps
TMIN-RX Minimum Pulse Width Response — 20 — — ns
VINT Peak Interference Amplitude — — — 200 mV
fINT Interference Frequency — 450 — — MHz
Notes:
1. This is peak amplitude of sine wave modulated to the receiver inputs.
2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs.
3. Exclude any static ground shift of 50 mV.
4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage.

Table 3.26. Soft D-PHY Output Timing and Levels

Symbol Description Conditions Min Typ Max Unit
High Speed (Differential) Output DC Specifications
VCMTX Common-mode Voltage in High Speed Mode — 150 200 250 mV
VCMTX Mismatch Between Differential HIGH —
|ΔVCMTX(1,0)| — — 5 mV
and LOW
|D-PHY-P – D-PHY-
|VOD| Output Differential Voltage 140 200 270 mV
N|
VOD Mismatch Between Differential HIGH and —
|ΔVOD| — — 10 mV
LOW
VOHHS Single-Ended Output HIGH Voltage — — — 360 mV
ZOS Single Ended Output Impedance — 37.5 50 80 Ω
ΔZOS ZOS mismatch — — — 20 %
High Speed (Differential) Output AC Specifications
ΔVCMTX(LF) Common-Mode Variation, 50 MHz–450 MHz — — — 25 mVRMS
ΔVCMTX(HF) Common-Mode Variation, above 450 MHz — — — 15 mVRMS
0.08 Gbps ≤ tR ≤ 1.00
— — 0.30 UI
Output 20%–80% Rise Time Gbps
tR
Output 80%–20% Fall Time 1.00 Gbps < tR ≤ 1.50
— — 0.35 UI
Gbps

68 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Symbol Description Conditions Min Typ Max Unit

0.08 Gbps ≤ tF ≤ 1.00
— — 0.30 UI
Gbps
tF Output Data Valid After CLK Output
1.00 Gbps < tF ≤ 1.50
— — 0.35 UI
Gbps
Low Power (Single-Ended) Output DC Specifications
VOH Low Power Mode Output HIGH Voltage 0.08 Gbps – 1.5 Gbps 1.07 1.2 1.3 V
VOL Low Power Mode Input LOW Voltage — –50 — 50 mV
ZOLP Output Impedance in Low Power Mode — 110 — — Ω
Low Power (Single-Ended) Output AC Specifications
tRLP 15%–85% Rise Time — — — 25 ns
tFLP 85%–15% Fall Time — — — 25 ns
tREOT HS – LP Mode Rise and Fall Time, 30%–85% — — — 35 ns
First LP XOR Clock
Pulse after STOP
40 — — ns
TLP-PULSE-TX Pulse Width of the LP Exclusive-OR Clock State or Last Pulse
before STOP State
All Other Pulses 20 — — ns
TLP-PER-TX Period of the LP Exclusive-OR Clock — 90 — — ns
CLOAD Load Capacitance — 0 — 70 pF

Table 3.27. Soft D-PHY Clock Signal Specification

Symbol Description Conditions Min Typ Max Unit
Clock Signal Specification
UI —
UIINST — — 12.5 ns
Instantaneous
— –10% — 10% UI
UI Variation ∆UI
— –5% — 5% UI

Table 3.28. Soft D-PHY Data-Clock Timing Specifications

Symbol Description Conditions Min Typ Max Unit
Data-Clock Timing Specifications
0.08 Gbps ≤ TSKEW[TX]
-0.15 — 0.15 UIINST
≤ 1.00 Gbps
TSKEW[TX] Data to Clock Skew
1.00 Gbps < TSKEW[TX]
-0.20 — 0.20 UIINST
≤ 1.50 Gbps
0.08 Gbps ≤ TSKEW[TLIS]
-0.20 — 0.20 UIINST
≤ 1.00 Gbps
TSKEW[TLIS] Data to Clock Skew
1.00 Gbps < TSKEW[TLIS]
-0.10 — 0.10 UIINST
≤ 1.50 Gbps
0.08 Gbps ≤ TSETUP[RX]
0.15 — — UI
≤ 1.00 Gbps
TSETUP[RX] Input Data Setup Before CLK
1.00 Gbps < TSETUP[RX]
0.20 — — UI
≤ 1.50 Gbps
0.08 Gbps ≤ THOLD[RX]
0.15 — — UI
≤ 1.00 Gbps
THOLD[RX] Input Data Hold After CLK
1.00 Gbps < THOLD[RX]
0.20 — — UI
≤ 1.50 Gbps

FPGA-DS-02049-2.1 69
CrossLink-NX Family
Data Sheet

3.12.7. Differential HSTL15D (Output Only)

Differential HSTL outputs are implemented as a pair of complementary single-ended HSTL outputs.

3.12.8. Differential SSTL135D, SSTL15D (Output Only)

Differential SSTL is used for differential clock in DDR3/DDR3L memory interface. All differential SSTL outputs are
implemented as a pair of complementary single-ended SSTL outputs. All allowable single-ended output classes (class I
and class II) are supported.

3.12.9. Differential HSUL12D (Output Only)

Differential HSUL is used for differential clock in LPDDR2 memory interface. All differential HSUL outputs are
implemented as a pair of complementary single-ended HSUL12 outputs. All allowable single-ended drive strengths are
supported.

3.12.10. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only)

Differential LVCMOS and LVTTL outputs are implemented as a pair of complementary single-ended outputs. All
allowable single-ended output drive strengths are supported.

3.13. Maximum sysI/O Buffer Speed

Table 3.29. Maximum I/O Buffer Speed1, 2, 3, 4, 7
Buffer Description Banks Max Unit
Maximum sysI/O Input Frequency
Single-Ended
LVCMOS33 LVCMOS33, VCCIO = 3.3 V 0, 1, 2, 6, 7 200 MHz
LVTTL33 LVTTL33, VCCIO = 3.3 V 0, 1, 2, 6, 7 200 MHz
LVCMOS25 LVCMOS25, VCCIO = 2.5 V 0, 1, 2, 6, 7 200 MHz
LVCMOS18 5 LVCMOS18, VCCIO = 1.8 V 0, 1, 2, 6, 7 200 MHz
LVCMOS18H LVCMOS18, VCCIO = 1.8 V 3, 4, 5 200 MHz
LVCMOS15 5 LVCMOS15, VCCIO = 1.5 V 0, 1, 2, 6, 7 100 MHz
LVCMOS15H 5 LVCMOS15, VCCIO = 1.5 V 3, 4, 5 150 MHz
LVCMOS12 5 LVCMOS12, VCCIO = 1.2 V 0, 1, 2, 6, 7 50 MHz
LVCMOS12H 5 LVCMOS12, VCCIO = 1.2 V 3, 4, 5 100 MHz
LVCMOS10 5 LVCMOS 1.0, VCCIO = 1.2 V 0, 1, 2, 6, 7 50 MHz
LVCMOS10H 5 LVCMOS 1.0, VCCIO = 1.0 V 3, 4, 5 50 MHz
LVCMOS10R LVCMOS 1.0, VCCIO independent 3, 4, 5 50 MHz
SSTL15_I, SSTL15_II SSTL_15, VCCIO = 1.5 V 3, 4, 5 1066 Mbps
SSTL135_I, SSTL135_II SSTL_135, VCCIO = 1.35 V 3, 4, 5 1066 Mbps
HSUL12 HSUL_12, VCCIO = 1.2 V 3, 4, 5 1066 Mbps

HSTL15 HSTL15, VCCIO = 1.5 V 3, 4, 5 250 Mbps

MIPI D-PHY (LP Mode) MIPI, Low Power Mode, VCCIO = 1.2 V 3, 4, 5 10 Mbps
Differential8
LVDS LVDS, VCCIO independent QFN72, caBGA256, 3, 4, 5 1250 Mbps
csBGA289, and caBGA400
LVDS, VCCIO independent csfBGA121 3, 4, 5 1500 Mbps

70 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Buffer Description Banks Max Unit

subLVDS subLVDS, VCCIO independent QFN72, 3, 4, 5 1250 Mbps
caBGA256, csBGA289, and caBGA400

subLVDS, VCCIO independent csfBGA121 3, 4, 5 1500 Mbps

SLVS SLVS similar to MIPI HS, VCCIO independent 3, 4, 5 1250 Mbps

QFN72, caBGA256, csBGA289, caBGA400

SLVS similar to MIPI HS, VCCIO independent 3, 4, 5 1500 Mbps

csfBGA121

MIPI D-PHY (HS Mode) MIPI, High Speed Mode, VCCIO = 1.2 V 3, 4, 5 1250 Mbps
QFN72

MIPI, High Speed Mode, VCCIO = 1.2 V 3, 4, 5 1500 Mbps

csfBGA121, caBGA256, csBGA289, caBGA400
SSTL15D Differential SSTL15, VCCIO independent 3, 4, 5 1066 Mbps
SSTL135D Differential SSTL135, VCCIO independent 3, 4, 5 1066 Mbps

HUSL12D Differential HSUL12, VCCIO independent 3, 4, 5 1066 Mbps

HSTL15D Differential HSTL15, VCCIO independent 3, 4, 5 250 Mbps

Maximum sysI/O Output Frequency

Single-Ended
LVCMOS33 (all drive strengths) LVCMOS33, VCCIO = 3.3 V 0, 1, 2, 6, 7 200 MHz
LVCMOS33 (RS50) LVCMOS33, VCCIO = 3.3 V, RSERIES = 50 Ω 0, 1, 2, 6, 7 200 MHz
LVTTL33 (all drive strengths) LVTTL33, VCCIO = 3.3 V 0, 1, 2, 6, 7 200 MHz
LVTTL33 (RS50) LVTTL33, VCCIO = 3.3 V, RSERIES = 50 Ω 0, 1, 2, 6, 7 200 MHz
LVCMOS25 (all drive strengths) LVCMOS25, VCCIO = 2.5 V 0, 1, 2, 6, 7 200 MHz
LVCMOS25 (RS50) LVCMOS25, VCCIO = 2.5 V, RSERIES = 50 Ω 0, 1, 2, 6, 7 200 MHz
LVCMOS18 (all drive strengths) LVCMOS18, VCCIO = 1.8 V 0, 1, 2, 6, 7 200 MHz
LVCMOS18 (RS50) LVCMOS18, VCCIO = 1.8 V, RSERIES = 50 Ω 0, 1, 2, 6, 7 200 MHz
LVCMOS18H (all drive strengths) LVCMOS18, VCCIO = 1.8 V 3, 4, 5 200 MHz
LVCMOS18H (RS50) LVCMOS18, VCCIO = 1.8 V, RSERIES = 50 Ω 3, 4, 5 200 MHz
LVCMOS15 (all drive strengths) LVCMOS15, VCCIO = 1.5 V 0, 1, 2, 6, 7 100 MHz
LVCMOS15H (all drive strengths) LVCMOS15, VCCIO = 1.5 V 3, 4, 5 150 MHz
LVCMOS12 (all drive strengths) LVCMOS12, VCCIO = 1.2 V 0, 1, 2, 6, 7 50 MHz
LVCMOS12H (all drive strengths) LVCMOS12, VCCIO = 1.2 V 3, 4, 5 100 MHz
LVCMOS10H (all drive strengths) LVCMOS12, VCCIO = 1.2 V 3, 4, 5 50 MHz
SSTL15_I, SSTL15_II SSTL_15, VCCIO = 1.5 V 3, 4, 5 1066 Mbps
SSTL135_I, SSTL135_II SSTL_135, VCCIO = 1.35 V 3, 4, 5 1066 Mbps
HSUL12 (all drive strengths) HSUL_12, VCCIO = 1.2 V 3, 4, 5 1066 Mbps
HSTL15 HSTL15, VCCIO = 1.5 V 3, 4, 5 250 Mbps
MIPI D-PHY (LP Mode) MIPI, Low Power Mode, VCCIO = 1.2 V 3, 4, 5 10 Mbps
Differential8
LVDS LVDS, VCCIO = 1.8 V QFN72, caBGA256, 3, 4, 5 1250 Mbps
csBGA289, and caBGA400
LVDS, VCCIO = 1.8 V csfBGA121 3, 4, 5 1500 Mbps
LVDS25E6 LVDS25, Emulated, VCCIO = 2.5 V 0, 1, 2, 6, 7 400 Mbps
SubLVDSE6 subLVDS, Emulated, VCCIO = 1.8 V 0, 1, 2, 6, 7 400 Mbps
SubLVDSEH6 subLVDS, Emulated, VCCIO = 1.8 V 3, 4, 5 800 Mbps

FPGA-DS-02049-2.1 71
CrossLink-NX Family
Data Sheet

Buffer Description Banks Max Unit

SLVS SLVS similar to MIPI, VCCIO = 1.2 V Mbps
QFN72, caBGA256, csBGA289, caBGA400 3, 4, 5 1250

SLVS similar to MIPI, VCCIO = 1.2 V Mbps

3, 4, 5 1500
csfBGA121
MIPI D-PHY (HS Mode) MIPI, High Speed Mode, VCCIO = 1.2 V Mbps
QFN72 3, 4, 5 1250

MIPI, High Speed Mode, VCCIO = 1.2 V Mbps

3, 4, 5 1500
csfBGA121, caBGA256, csBGA289, caBGA400
SSTL15D Differential SSTL15, VCCIO = 1.5 V 3, 4, 5 1066 Mbps
SSTL135D Differential SSTL135, VCCIO = 1.35 V 3, 4, 5 1066 Mbps
HUSL12D Differential HSUL12, VCCIO = 1.2 V 3, 4, 5 1066 Mbps
HSTL15D Differential HSTL15, VCCIO = 1.5 V 3, 4, 5 250 Mbps
Notes:
1. Maximum I/O speed is the maximum switching rate of the I/O operating within the guidelines of the defining standard. The
actual interface speed performance using the I/O also depends on other factors, such as internal and external timing.
2. These numbers are characterized but not test on every device.
3. Performance is specified in MHz, as defined in clock rate when the sysI/O is used as pin. For data rate performance, this can be
converted to Mbps, which equals to 2 times the clock rate.
4. LVCMOS and LVTTL are measured with load specified in Table 3.50.
5. These LVCMOS inputs can be placed in different VCCIO voltage. Performance may vary. Please refer to Lattice Design Software
6. These emulated outputs performance is based on externally properly terminated as described in LVDS25E (Output Only) and
SubLVDSE/SubLVDSEH (Output Only).
7. All speeds are measured with fast slew.
8. For maximum differential I/O performance only Differential I/O should be placed in the bottom I/O banks. If this is not possible,
the following will impact on maximum performance:
a. If Fast Slew Rate LVCMOS I/O are used, they should be limited to no more than nine I/O (adjacent), four I/O (same bank),
55 I/O (left/right banks) to keep degradation below 50%.
b. If non-Differential I/O (SLOW SLEW) are placed on the bottom but not within the same bank as differential I/O, then the
maximum Differential performance is degraded to 70% of original when 21 aggressors are toggling.
c. If non-Differential I/O (SLOW SLEW) are placed within the same bank as Differential I/O then the maximum performance is
degraded to 50% of original when 16 aggressor are toggling.
d. No performance impact if MIPI LP and MIPI HS are in the same bank.
e. If Differential RX/TX I/O are both placed within the same bank then the maximum performance is degraded to 90%.
f. For DDR3/3L, LPDDR2/3 separate DQ/DQS groups from Address/Commands/CLK groups into separate banks.

3.14. Typical Building Block Function Performance

These building block functions can be generated using Lattice Design software tool. Exact performance may vary with
the device and the design software tool version. The design software tool uses internal parameters that have been
characterized but are not tested on every device.
Table 3.30. Pin-to-Pin Performance
Typ. @ VCC =
Function Unit
1.0 V
16-bit Decoder (I/O configured with LVCMOS18, Left and Right Banks) 5.5 ns
16-bit Decoder (I/O configured with HSTL15_I, Bottom Banks) 5.1 ns
16:1 Mux (I/O configured with LVCMOS18, Left and Right Banks) 6 ns
16:1 Mux (I/O configured with HSTL15_I, Bottom Banks) 6.1 ns
Note: These functions are generated using Lattice Radiant Design software tool. Exact performance may vary with the device and
the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested
on every device.

72 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Table 3.31. Register-to-Register Performance

Typ. @ VCC =
Function Unit
1.0 V
Basic Functions
16-bit Adder 5002 MHz
32-bit Adder 496 MHz
16-bit Counter 402 MHz
32-bit Counter 371 MHz
Embedded Memory Functions
512 × 36 Single Port RAM, with Output Register 5002 MHz
1024 × 18 True-Dual Port RAM using same clock, with EBR Output Registers 5002 MHz
1024 × 18 True-Dual Port RAM using asynchronous clocks, with EBR Output Registers 5002 MHz
Large Memory Functions
32k × 32 Single Port RAM, with Output Register 1652 MHz
32k × 32 Single Port RAM with ECC, with Output Register 1302 MHz
32k × 32 True-Dual Port RAM using same clock, with Output Registers 157.183 2 MHz
Distributed Memory Functions
16 × 4 Single Port RAM (One PFU) 5002 MHz
16 × 2 Pseudo-Dual Port RAM (One PFU) 5002 MHz
16 × 4 Pseudo-Dual Port (Two PFUs) 5002 MHz
DSP Functions
9 × 9 Multiplier with Input Output Registers 376 MHz
18 × 18 Multiplier with Input/Output Registers 287 MHz
36 × 36 Multiplier with Input/Output Registers 200 MHz
MAC 18 × 18 with Input/Output Registers 203 MHz
MAC 18 × 18 with Input/Pipelined/Output Registers 287 MHz
MAC 36 × 36 with Input/Output Registers 119 MHz
MAC 36 × 36 with Input/Pipelined/Output Registers 155 MHz
Notes:
1. The Clock port is configured with LVDS I/O type. Performance Grade: 9_High-Performance_1.0V.
2. Limited by the Minimum Pulse Width of the component
3. These functions are generated using Lattice Radiant design software. Exact performance may vary with the device and the
design software tool version. The design software tool uses internal parameters that have been characterized but are not
tested on every device.
4. For the Pipelined designs, the number of pipeline stages used are 2.

3.15. LMMI
Table 3.32 summarizes the performance of the LMMI interface with supported IPs. Additional timing requirement and
constraint can be identified through the Lattice Radiance design tools.
Table 3.32. LMMI FMAX Summary
IP FMAX (MHz)
CDR0 73
CDR1 70
DPHY0 67
DPHY1 55
CRE 54
I2C 38
PCIe 57

FPGA-DS-02049-2.1 73
CrossLink-NX Family
Data Sheet

IP FMAX (MHz)
PLL_ULC 59
PLL_LLC 55
PLL_LRC 37

3.16. Derating Timing Tables

Logic timing provided in the following sections of this data sheet and the Lattice Radiant design tools are worst case
numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much
better than the values given in the tables. The Lattice Radiant design tool can provide logic timing numbers at a
particular temperature and voltage.

3.17. External Switching Characteristics

Over recommended commercial operating conditions.
Table 3.33. External Switching Characteristics (VCC = 1.0 V)
–9 –8 –7
Parameter Description Unit
Min Max Min Max Min Max
Clocks
Primary Clock
fMAX_PRI Frequency for Primary Clock — 400 — 325.2 — 276 MHz
tW_PRI Clock Pulse Width for Primary Clock 1.125 — 1.384 — 1.63 — ns
tSKEW_PRI6 Primary Clock Skew Within a Device — 450 — 554 — 653 ps
Edge Clock
fMAX_EDGE Frequency for Edge Clock Tree — 800 — 650.4 — 551.7 MHz
tW_EDGE Clock Pulse Width for Edge Clock 0.537 — 0.661 — 0.779 — ns
tSKEW_EDGE6 Edge Clock Skew Within a Device — 120 — 148 — 174 ps
Generic SDR Input
General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL
tCO Clock to Output - PIO Output Register — 6.45 — 6.64 — 7.83 ns
tSU Clock to Data Setup - PIO Input Register 0 — 0 — 0 — ns
tH Clock to Data Hold - PIO Input Register 2.94 — 3.32 — 3.92 — ns
Clock to Data Setup - PIO Input Register
tSU_DEL 1.84 — 1.84 — 1.84 — ns
with Data Input Delay
Clock to Data Hold - PIO Input Register with
tH_DEL 0.16 — 0.16 — 0.16 — ns
Data Input Delay
General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL
tCOPLL Clock to Output - PIO Output Register — 4.02 — 4.67 — 5.51 ns
tSUPLL Clock to Data Setup - PIO Input Register 1.23 — 1.23 — 1.23 — ns
tHPLL Clock to Data Hold - PIO Input Register 0.98 — 1.21 — 1.42 — ns
tSU_DELPLL Clock to Data Setup - PIO Input Register
4.74 — 4.74 — 4.74 — ns
with Data Input Delay
tH_DELPLL Clock to Data Hold - PIO Input Register with
0 — 0 — 0 — ns
Data Input Delay
Generic DDR Input/Output
Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input –
Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 – Figure 3.7 and Figure 3.9
0.917 — 0.917 — 0.917 — ns
tSU_GDDR1 Input Data Setup Before CLK
0.275 — 0.275 — 0.275 — UI

74 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

–9 –8 –7
Parameter Description Unit
Min Max Min Max Min Max
tHO_GDDR1 Input Data Hold After CLK 0.917 — 0.917 — 0.917 — ns
1.217 — 1.113 — 1.014 — ns
tDVB_GDDR1 Output Data Valid After CLK Output
-0.45 — -0.554 — -0.653 — ns + 1/2 UI
1.217 — 1.113 — 1.014 — ns
tDQVA_GDDR1 Output Data Valid After CLK Output
-0.45 — -0.554 — -0.653 — ns + 1/2 UI
fDATA_GDDRX1 Input/Output Data Rate — 300 — 300 — 300 Mbps
fMAX_GDDRX1 Frequency of PCLK — 150 — 150 — 150 MHz
½ UI Half of Data Bit Time, or 90 degree 1.667 — 1.667 — 1.667 — ns
Output TX to Input RX Margin per Edge 0.3 — 0.197 — 0.097 — ns
Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input –
Bank 0, Bank 1, Bank 2, Bank 6,and Bank 7 – Figure 3.8 and Figure 3.10
— -0.917 — -0.917 — -0.917 ns + 1/2 UI
tDVA_GDDR1 Input Data Valid After CLK — 0.75 — 0.75 — 0.75 ns
— 0.225 — 0.225 — 0.225 UI
0.917 — 0.917 — 0.917 — ns + 1/2 UI
tDVE_GDDR1 Input Data Hold After CLK 2.583 — 2.583 — 2.583 — ns
0.775 — 0.775 — 0.775 — UI
tDIA_GDDR1 Output Data Invalid After CLK Output — 0.45 — 0.554 — 0.653 ns
tDIB_GDDR1 Output Data Invalid Before CLK Output — 0.45 — 0.554 — 0.653 ns
Input/Output Data Rate
fDATA_GDDRX1 — 300 — 300 — 300 Mbps

fMAX_GDDRX1 Frequency for PCLK — 150 — 150 — 150 MHz

½ UI Half of Data Bit Time, or 90 degree 1.667 — 1.667 — 1.667 — ns

Output TX to Input RX Margin per Edge 0.3 — 0.197 — 0.098 — ns

Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input –
Bank 3, Bank 4, and Bank 5 – Figure 3.7 and Figure 3.9
0.55 — 0.55 — 0.648 — ns
tSU_GDDR1 Input Data Setup Before CLK
0.275 — 0.275 — 0.275 — UI
tHO_GDDR1 Input Data Hold After CLK 0.55 — 0.55 — 0.648 — ns

0.7 — 0.631 — 0.744 — ns

tDVB_GDDR1 Output Data Valid After CLK Output
-0.300 — -0.369 — -0.435 — ns + 1/2 UI

0.7 — 0.631 — 0.744 — ns

tDQVA_GDDR1 Output Data Valid After CLK Output
-0.300 — -0.369 — -0.435 — ns + 1/2 UI

fDATA_GDDRX1 Input/Output Data Rate — 500 — 500 — 424 Mbps

fMAX_GDDRX1 Frequency of PCLK — 250 — 250 — 212 MHz

½ UI Half of Data Bit Time, or 90 degree — — 1 — 1.179 — ns

Output TX to Input RX Margin per Edge 0.15 — 0.081 — 0.095 — ns

FPGA-DS-02049-2.1 75
CrossLink-NX Family
Data Sheet

–9 –8 –7
Parameter Description Unit
Min Max Min Max Min Max
Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input –
Bank 3, Bank 4, and Bank 5 – Figure 3.8 and Figure 3.10
— -0.55 — -0.550 — -0.648 ns + 1/2 UI

tDVA_GDDR1 Input Data Valid After CLK — 0.45 — 0.45 — 0.53 ns

— 0.225 — 0.225 — 0.225 UI

0.55 — 0.55 — 0.648 — ns + 1/2 UI

tDVE_GDDR1 Input Data Hold After CLK 1.55 — 1.55 — 1.827 — ns

0.775 — 0.775 — 0.775 — UI

tDIA_GDDR1 Output Data Invalid After CLK Output — 0.3 — 0.369 — 0.435 ns

tDIB_GDDR1 Output Data Invalid Before CLK Output — 0.3 — 0.369 — 0.435 ns

fDATA_GDDRX1 Input/Output Data Rate — 500 — 500 — 424 Mbps

fMAX_GDDRX1 Frequency for PCLK — 250 — 250 — 212 MHz

½ UI Half of Data Bit Time, or 90 degree 1 — 1 — 1.179 — ns

Output TX to Input RX Margin per Edge 0.15 — 0.081 — 0.095 — ns

Generic DDRX2 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX2_RX/TX.ECLK.Centered) using PCLK Clock Input -
Figure 3.7 and Figure 3.9
0.175 — 0.175 — 0.206 — ns
tSU_GDDRX2 Data Setup before CLK Input
0.175 — 0.175 — 0.175 — UI
tHO_GDDRX2 Data Hold after CLK Input 0.177 — 0.177 — 0.206 — ns
0.380 — 0.352 — 0.415 — ns
tDVB_GDDRX2 Output Data Valid Before CLK Output
-0.120 — -0.148 — -0.174 — ns + 1/2 UI
0.380 — 0.352 — 0.415 — ns
tDQVA_GDDRX2 Output Data Valid After CLK Output
-0.120 — -0.148 — -0.174 — ns + 1/2 UI
fDATA_GDDRX2 Input/Output Data Rate — 1000 — 1000 — 848 Mbps
fMAX_GDDRX2 Frequency for ECLK — 500 — 500 — 424 MHz
½ UI Half of Data Bit Time, or 90 degree 0.500 — 0.500 — 0.589 — ns
fPCLK PCLK frequency — 250.0MHz — 250.0 — 212.1
Output TX to Input RX Margin per Edge 0.230 — 0.202 — 0.239 — ns
Generic DDRX2 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX2_RX/TX.ECLK.Aligned) using PCLK Clock Input -
Figure 3.8 and Figure 3.10
— -0.275 — -0.275 — -0.324 ns + 1/2 UI
tDVA_GDDRX2 Input Data Valid After CLK — 0.225 — 0.225 — 0.265 ns
— 0.225 — 0.225 — 0.225 UI
0.275 — 0.275 — 0.324 — ns + 1/2 UI
tDVE_GDDRX2 Input Data Hold After CLK 0.775 — 0.775 — 0.914 — ns
0.775 — 0.775 — 0.775 — UI
tDIA_GDDRX2 Output Data Invalid After CLK Output — 0.120 — 0.148 — 0.174 ns
tDIB_GDDRX2 Output Data Invalid Before CLK Output — 0.120 — 0.148 — 0.174 ns
fDATA_GDDRX2 Input/Output Data Rate — 1000 — 1000 — 848 Mbps
fMAX_GDDRX2 Frequency for ECLK — 500 — 500 — 424 MHz
½ UI Half of Data Bit Time, or 90 degree 0.500 — 0.500 — 0.589 — ns

76 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

–9 –8 –7
Parameter Description Unit
Min Max Min Max Min Max
fPCLK PCLK frequency — 250.0 — 250.0 — 212.1 MHz
Output TX to Input RX Margin per Edge 0.105 — 0.077 — 0.091 — ns
Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input -
Figure 3.7 and Figure 3.9
0.168 — 0.210 — 0.244 — ns
tSU_GDDRX4 Input Data Set-Up Before CLK
0.252 — 0.252 — 0.252 — UI
tHO_GDDRX4 Input Data Hold After CLK 0.174 — 0.210 — 0.244 — ns
0.213 — 0.269 — 0.309 — ns
tDVB_GDDRX4 Output Data Valid Before CLK Output
-0.120 — -0.148 — -0.174 — ns + 1/2UI
0.213 — 0.269 — 0.309 — ns
tDQVA_GDDRX4 Output Data Valid After CLK Output
-0.120 — -0.148 — -0.174 — ns + 1/2UI
fDATA_GDDRX4 Input/Output Data Rate — 1500 — 1200 — 1034 Mbps
fMAX_GDDRX4 Frequency for ECLK — 750.0 — 600 — 517 MHz
½ UI Half of Data Bit Time, or 90 degree 0.333 — 0.417 — 0.483 — ns
fPCLK PCLK Frequency — 187.5 — 150.0 — 129.3 MHz
Output TX to Input RX Margin per Edge 0.080 — 0.102 — 0.116 — ns
Generic DDRX4 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX4_RX/TX.ECLK.Aligned) using PCLK Clock Input, Left
and Right sides Only - Figure 3.8 and Figure 3.10
— -0.183 — -0.229 — -0.266 ns + 1/2 UI
tDVA_GDDRX4 Input Data Valid After CLK — 0.150 — 0.188 — 0.218 ns
— 0.225 — 0.225 — 0.225 UI
0.183 — 0.229 — 0.266 — ns + 1/2 UI
tDVE_GDDRX4 Input Data Hold After CLK 0.517 — 0.646 — 0.749 — ns
0.775 — 0.775 — 0.775 — UI

tDIA_GDDRX4 Output Data Invalid After CLK Output — 0.120 — 0.148 — 0.17 ns

tDIB_GDDRX4 Output Data Invalid Before CLK Output — 0.120 — 0.148 — 0.174 ns

fDATA_GDDRX4 Input/Output Data Rate — 1500 — 1200 — 1034 Mbps

fMAX_GDDRX4 Frequency for ECLK — 750 — 600 — 517 MHz

½ UI Half of Data Bit Time, or 90 degree 0.333 — 0.417 — 0.483 — ns

fPCLK PCLK frequency — 187.5 — 150.0 — 129.3 MHz

Output TX to Input RX Margin per Edge 0.030 — 0.040 — 0.044 — ns
Generic DDRX5 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX5_RX/TX.ECLK.Centered) using PCLK Clock Input -
Figure 3.7 and Figure 3.9
0.179 — 0.187 — 0.224 — ns
tSU_GDDRX5 Input Data Set-Up Before CLK
0.224 — 0.224 — 0.224 — UI
tHO_GDDRX5 Input Data Hold After CLK 0.181 — 0.187 — 0.224 — ns
tWINDOW_GDDRX5C Input Data Valid Window 0.36 — 0.374 — 0.448 — ns
0.280 — 0.269 — 0.326 — ns
tDVB_GDDRX5 Output Data Valid Before CLK Output
-0.120 — -0.148 — -0.174 — ns+1/2UI
0.280 — 0.269 — 0.326 — ns
tDQVA_GDDRX5 Output Data Valid After CLK Output
-0.120 — -0.148 — -0.174 — ns+1/2UI
fDATA_GDDRX5 Input/Output Data Rate — 1250 — 1200 — 1000 Mbps
fMAX_GDDRX5 Frequency for ECLK — 625 — 600 — 500 MHz

FPGA-DS-02049-2.1 77
CrossLink-NX Family
Data Sheet

–9 –8 –7
Parameter Description Unit
Min Max Min Max Min Max
½ UI Half of Data Bit Time, or 90 degree 0.400 — 0.417 — 0.500 — ns
fPCLK PCLK frequency — 125.0 — 120.0 — 100.0 MHz
Output TX to Input RX Margin per Edge 0.120 — 0.102 — 0.126 — ns
Generic DDRX5 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX5_RX/TX.ECLK.Aligned) using PCLK Clock Input -
Figure 3.8 and Figure 3.10
— -0.220 — -0.229 — -0.275 ns + 1/2 UI
tDVA_GDDRX5 Input Data Valid After CLK — 0.180 — 0.188 — 0.225 ns
— 0.225 — 0.225 — 0.225 UI
0.220 — 0.229 — 0.275 — ns + 1/2 UI
tDVE_GDDRX5 Input Data Hold After CLK 0.620 — 0.646 — 0.775 — ns
0.775 — 0.775 — 0.775 — UI
tWINDOW_GDDRX5A Input Data Valid Window 0.440 — 0.458 — 0.550 — ns
tDIA_GDDRX5 Output Data Invalid After CLK Output — 0.120 — 0.148 — 0.174 ns
tDIB_GDDRX5 Output Data Invalid Before CLK Output — 0.120 — 0.148 — 0.174 ns
fDATA_GDDRX5 Input/Output Data Rate — 1250 — 1200 — 1000 Mbps
fMAX_GDDRX5 Frequency for ECLK — 625 — 600 — 500 MHz
½ UI Half of Data Bit Time, or 90 degree 0.400 — 0.417 — 0.500 — ns
fPCLK PCLK frequency — 125.0 — 120.0 — 100.0 MHz
Output TX to Input RX Margin per Edge 0.060 — 0.040 — 0.051 — ns
Soft D-PHY DDRX4 Inputs/Outputs with Clock and Data Centered at Pin, using PCLK Clock Input
Input Data Set-Up Before CLK 0.133 — 0.167 — 0.193 — ns
tSU_GDDRX4_MP
0.2 — 0.2 — 0.2 — UI
tHO_GDDRX4_MP Input Data Hold After CLK 0.133 — 0.167 — 0.193 — ns
Output Data Valid Before CLK Output 0.133 — 0.167 — 0.193 — ns
tDVB_GDDRX4_MP
0.2 — 0.2 — 0.2 — UI
Output Data Valid After CLK Output 0.133 — 0.167 — 0.193 — ns
tDQVA_GDDRX4_MP
0.2 — 0.2 — 0.2 — UI
WLCSP72 — — — 1000 — —
QFN72 — 1250 — 1000 — 861
Input Data Bit Rate
csfBGA121,
fDATA_GDDRX4_MP Mbps
for MIPI PHY caBGA256,
— 1500 — 1200 — 1034
csBGA289,
caBGA400
½ UI Half of Data Bit Time, or 90 degree 0.333 — 0.417 — 0.483 — ns
fPCLK PCLK frequency — 187.5 — 150.0 — 129.3 MHz
Output TX to Input RX Margin per Edge 0.067 0.083 0.097 ns
Video DDRX71 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) using PLL Clock Input - Figure 3.12 and
Figure 3.13
Input Valid Bit "i" switch from CLK Rising — 0.264 — 0.264 — 0.3 UI
tRPBi_DVA
Edge ("i" = 0 to 6, 0 aligns with CLK) — -0.250 — -0.250 — -0.249 ns+(1/2+i)×UI
Input Hold Bit "i" switch from CLK Rising 0.722 — 0.722 — 0.7 — UI
tRPBi_DVE
Edge ("i" = 0 to 6, 0 aligns with CLK) 0.235 — 0.235 — 0.249 — ns+(1/2+i)×UI
Data Output Valid Bit "i" switch from CLK
tTPBi_DOV — 0.159 — 0.159 — 0.187 ns+i×UI
Rising Edge ("i" = 0 to 6, 0 aligns with CLK)
Data Output Invalid Bit "i" switch from CLK
tTPBi_DOI -0.159 — -0.159 — -0.187 — ns+(i+ 1) ×UI
Rising Edge ("i" = 0 to 6, 0 aligns with CLK)
tTPBi_skew_UI TX skew in UI — 0.150 — 0.150 — 0.150 UI
tB Serial Data Bit Time, = 1 UI 1.058 — 1.058 — 1.247 — ns

78 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

–9 –8 –7
Parameter Description Unit
Min Max Min Max Min Max
fDATA_TX71 DDR71 Serial Data Rate — 945 — 945 — 802 Mbps
fMAX_TX71 DDR71 ECLK Frequency — 473 — 473 — 401 MHz
fCLKIN 7:1 Clock (PCLK) Frequency — 135.0 — 135.0 — 114.5 MHz
Output TX to Input RX Margin per Edge 0.159 — 0.159 — 0.187 — ns
Memory Interface
DDR3/DDR3L/LPDDR2 READ (DQ Input Data are Aligned to DQS) - Figure 3.8
tDVBDQ_DDR3
tDVBDQ_DDR3L Data Input Valid before DQS Input — -0.235 — -0.235 — -0.277 ns + 1/2 UI
tDVBDQ_LPDDR2
tDVADQ_DDR3
tDVADQ_DDR3L Data Input Valid after DQS Input 0.235 — 0.235 — 0.277 — ns + 1/2 UI
tDVADQ_LPDDR2
fDATA_DDR3
fDATA_DDR3L DDR Memory Data Rate — 1066 — 1066 — 904 Mb/s
fDATA_LPDDR2
fMAX_ECLK_DDR3
fMAX_ECLK_DDR3L DDR Memory ECLK Frequency — 533 — 533 — 452 MHz
fMAX_ECLK_LPDDR2
fMAX_SCLK_DDR3
fMAX_SCLK_DDR3L DDR Memory SCLK Frequency — 133.3 — 133.3 — 113 MHz
fMAX_SCLK_LPDDR2
DDR3/DDR3L/LPDDR2 WRITE (DQ Output Data are Centered to DQS) - Figure 3.11
tDQVBS_DDR3
tDQVBS_DDR3L Data Output Valid before DQS Output — -0.235 — -0.235 — -0.277 ns + 1/2 UI
tDQVBS_LPDDR2
tDQVAS_DDR3
tDQVAS_DDR3L Data Output Valid after DQS Output 0.235 — 0.235 — 0.277 — ns + 1/2 UI
tDQVAS_LPDDR2
fDATA_DDR3
fDATA_DDR3L DDR Memory Data Rate — 1066 — 1066 — 904 Mb/s
fDATA_LPDDR2
fMAX_ECLK_DDR3
fMAX_ECLK_DDR3L DDR Memory ECLK Frequency — 533 — 533 — 452 MHz
fMAX_ECLK_LPDDR2
fMAX_SCLK_DDR3
fMAX_SCLK_DDR3L DDR Memory SCLK Frequency — 133.3 — 133.3 — 113 MHz
fMAX_SCLK_LPDDR2
Notes:
1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Lattice Radiant
software.
2. General I/O timing numbers are based on LVCMOS 1.8, 8 mA, Fast Slew Rate, 0 pF load.
Generic DDR timing are numbers based on LVDS I/O.
DDR3 timing numbers are based on SSTL15.
LPDDR2 timing numbers are based on HSUL12.
3. Uses LVDS I/O standard for measurements.
4. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
5. All numbers are generated with the Lattice Radiant software.
6. This clock skew is not the internal clock network skew. The Nexus family devices have very low internal clock network skew that
can be approximated to 0 ps. These tSKEW values measured externally at system level includes additional skew added by the I/O,
wire bonding and package ball.

FPGA-DS-02049-2.1 79
CrossLink-NX Family
Data Sheet

Rx CLK (in)

Rx DATA (in)

tSU tSU

tHD tHD

Figure 3.7. Receiver RX.CLK.Centered Waveforms

½ UI
½ UI
1 UI
Rx CLK (in)
or DQS input

Rx DATA (in)
or DQS input

tDVA/tDVADQ
tDVA/tDVADQ
tDVE/tDVEDQ
tDVE/tDVEDQ

Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms

1/2 UI 1/2 UI 1/2 UI 1/2 UI

Tx CLK (out)
or DQS Output

Tx DATA (out)
or DQ Output

tDVB/tDQVBS tDVB/tDQVBS

tDVA/tDQVA tDVA/tDQVAS

Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms

80 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

1 UI
Tx CLK (out)

Tx DATA (out)

tDIB tDIB
tDIA tDIA

Figure 3.10. Transmit TX.CLK.Aligned Waveforms

Receiver – Shown for one LVDS Channel

# of Bits
Data In
756 Mb/s
Clock In
108 MHz

Bit # Bit # Bit # Bit #

0x 10 – 1 20 – 8 30 – 15 40 – 22
0x 11 – 2 21 – 9 31 – 16 41 – 23
For each Channel: 12 – 3
0x 22 – 10 32 – 17 42 – 24
7-bit Output Words 13 – 4 23 – 11 33 – 18
0x 43 – 25
to FPGA Fabric 0x 14 – 5 24 – 12 34 – 19 44 – 26
0x 15 – 6 25 – 13 35 – 20 45 – 27
0x 16 – 7 26 – 14 36 – 21 46 – 28

Transmitter – Shown for one LVDS Channel

# of Bits
Data Out
756 Mb/s

Clock Out
108 MHz

Bit # Bit # Bit # Bit #

For each Channel: 00 – 1 10 – 8 20 – 15 30 – 22
00 – 2 11 – 9 21 – 16 31 – 23
7-bit Output Words
00 – 3 12 – 10 22 – 17 32 – 24
to FPGA Fabric 00 – 4 13 – 11 33 – 25
23 – 18
00 – 5 14 – 12 24 – 19 34 – 26
00 – 6 15 – 13 25 – 20 35 – 27
00 – 7 16 – 14 26 – 21 36 – 28

Figure 3.11. DDRX71 Video Timing Waveforms

FPGA-DS-02049-2.1 81
CrossLink-NX Family
Data Sheet

Bit 0 Bit 1 Bit i

1/2 UI 1/2 UI

CLK (in) 1 UI

DATA (in)

tSU_0
tHD_0
tSU_i
tHD_i

Figure 3.12. Receiver DDRX71_RX Waveforms

Bit 0 Bit 1 Bit i

1 UI
CLK (out)

DATA (out)

tDIB_0
tDIA_0
tDIB_i

tDIA_i
Figure 3.13. Transmitter DDRX71_TX Waveforms

3.18. sysCLOCK PLL Timing (VCC = 1.0 V) – Commercial/Industrial

Table 3.34. sysCLOCK PLL Timing (VCC = 1.0 V) – Commercial/Industrial
Parameter Descriptions Conditions Min Typ. Max Units
fIN Input Clock Frequency (CLKI, CLKFB) — 18 — 500 MHz
fOUT Output Clock Frequency — 6.25 — 800 MHz
fVCO PLL VCO Frequency — 800 — 1600 MHz
Without Fractional-N
18 — 500 MHz
Enabled
fPFD Phase Detector Input Frequency
With Fractional-N
18 — 100 MHz
Enabled
AC Characteristics

tDT Output Clock Duty Cycle — 45 — 55 %

tPH4 Output Phase Accuracy — –5 — 5 %

82 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Parameter Descriptions Conditions Min Typ. Max Units

fOUT ≥ 200 MHz — — 250 ps p-p
Output Clock Period Jitter
fOUT < 200 MHz — — 0.05 UIPP
fOUT ≥ 200 MHz — — 250 ps p-p
Output Clock Cycle-to-Cycle Jitter
fOUT < 200 MHz — — 0.05 UIPP
fPFD ≥ 200 MHz — — 250 ps p-p
60 MHz ≤ fPFD < 200 MHz — — 350 ps p-p
Output Clock Phase Jitter
tOPJIT1 30 MHz ≤ fPFD < 60 MHz — — 450 ps p-p
18 MHz ≤ fPFD < 30 MHz — — 650 ps p-p
fOUT ≥ 200 MHz — — 350 ps p-p
Output Clock Period Jitter (Fractional-N)
fOUT < 200 MHz — — 0.07 UIPP

Output Clock Cycle-to-Cycle Jitter fOUT ≥ 200 MHz — — 400 ps p-p

(Fractional-N) fOUT < 200 MHz — — 0.08 UIPP
fBW 3 PLL Loop Bandwidth — 0.45 — 13 MHz
tLOCK2 PLL Lock-in Time — — — 10 ms
tUNLOCK PLL Unlock Time (from RESET goes HIGH) — — — 50 ns
fPFD ≥ 20 MHz — — 0.01 UIPP
tIPJIT Input Clock Period Jitter
fPFD < 20 MHz — — 500 ps p-p
tHI Input Clock High Time 90% to 90% 0.5 — — ns
tLO Input Clock Low Time 10% to 10% 0.5 — — ns
tRST RST/ Pulse Width — 1 — — ms
fSSC_MOD Spread Spectrum Clock Modulation — 20 — 200 kHz
Frequency
Spread Spectrum Clock Modulation
fSSC_MOD_AMP — 0.25 — 2.00 %
Amplitude Range

Spread Spectrum Clock Modulation

fSSC_MOD_STEP — — 0.25 — %
Amplitude Step Size
Notes:
1. Jitter sample is taken over 10,000 samples for Period jitter, and 1,000 samples for Cycle-to-Cycle jitter of the primary PLL output
with clean reference clock with no additional I/O toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Result from Lattice Radiant software.
4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency.

3.19. Internal Oscillators Characteristics

Table 3.35. Internal Oscillators (VCC = 1.0 V)
Symbol Parameter Description Min Typ Max Unit
fCLKHF HFOSC CLKK Clock Frequency 418.5 450 481.5 MHz
fCLKLF LFOSC CLKK Clock Frequency 25.6 32 38.4 kHz
DCHCLKHF HFOSC Duty Cycle (Clock High Period) 45 50 55 %
DCHCLKLF LFOSC Duty Cycle (Clock High Period) 45 50 55 %

FPGA-DS-02049-2.1 83
CrossLink-NX Family
Data Sheet

3.20. User I2C Characteristics

Table 3.36. User I2C Specifications (VCC = 1.0 V)
Parameter STD Mode FAST Mode FAST Mode Plus2
Symbol Units
Description Min Typ Max Min Typ Max Min Typ Max
SCL Clock
fscl — — 100 — — 400 — — 1000 kHz
Frequency
Optional delay
TDELAY1 — — 62 — — 62 — — 62 ns
through delay block
Notes:
1. Refer to the I2C Specification for timing requirements. User design should set constraints in Lattice Design software to meet this
industrial I2C Specification.
2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I2C bus. Internal pull up may not be
sufficient to support the maximum speed.

3.21. Analog-Digital Converter (ADC) Block Characteristics

Table 3.37. ADC Specifications1
Symbol Description Condition Min Typ Max Unit
ADC Internal Reference —
VREFINT_ADC 1.142 1.2 1.262 V
Voltage4
ADC External Reference —
VREFEXT_ADC 1.0 — 1.8 V
Voltage
NRES_ADC ADC Resolution — — 12 — bits
ENOBADC Effective Number of Bits — 9.9 11 — bits
VCM_ADC ― VCM_ADC +
Bipolar Mode, Internal VREF VCM_ADC V
VREFINT_ADC/4 VREFINT_ADC/4
VCM_ADC ― VCM_ADC +
VSR_ADC ADC Input Range Bipolar Mode, External VREF VREFEXT_ADC V
VREFEXT_ADC/4 VREFEXT_ADC/4
Uni-polar Mode, Internal VREF 0 — VREFINT_ADC V
Uni-polar Mode, External VREF 0 — VREFEXT_ADC V
ADC Input Common Internal VREF — VREFINT_ADC/2 — V
VCM_ADC Mode Voltage (for fully
differential signals) External VREF — VREFEXT_ADC/2 — V
fCLK_ADC ADC Clock Frequency — — 25 50 MHz
@ Sampling Frequency = 1
fINPUT_ADC ADC Input Frequency — — 500 kHz
Mbps
FSADC ADC Sampling Rate — — 1 — MS/s
NTRACK_ADC ADC Input Tracking Time — 4 — — cycles3
ADC Input Equivalent
RIN_ADC — — 116 — kΩ
Resistance
tCAL_ADC ADC Calibration Time — — — 6500 cycles3
Includes minimum tracking
LOUTput_ADC ADC Conversion Time 25 — — cycles3
time of four cycles
ADC Differential —
DNLADC –1 — 1 LSB
Nonlinearity
ADC Integral —
INLADC –22 — 2.21 LSB
Nonlinearity
ADC Spurious Free —
SFDRADC 67.7 77 — dBc
Dynamic Range
ADC Total Harmonic —
THDADC — –76 –66.8 dB
Distortion

84 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Symbol Description Condition Min Typ Max Unit

ADC Signal to Noise —
SNRADC 61.9 68 — dB
Ratio
ADC Signal to Noise Plus —
SNDRADC 61.7 67 — dB
Distortion Ratio
ERRGAIN_ADC ADC Gain Error — –0.5 — 0.5 % FSADC
ERROFFSET_ADC ADC Offset Error — –2 — 2 LSB
ADC Input Equivalent —
CIN_ADC — 2 — pF
Capacitance
Notes:
1. ADC is available in Commercial/Industrial –8 and –9 speed grades.
2. Not tested; guaranteed by design.
3. ADC Sample Clock cycles. See ADC User Guide for Nexus Platform (FPGA-TN-02129) for more details.
4. The internal voltage reference is only for internal testing purposes. It is not recommended for customer design. The user should
always use the part with external voltage.

3.22. Comparator Block Characteristics

Table 3.38. Comparator Specifications1
Symbol Description Min Typ Max Unit
fIN_COMP Comparator Input Frequency — — 10 MHz
VIN_COMP Comparator Input Voltage 0 — VCCADC18 V
VOFFSET_COMP Comparator Input Offset –23 — 24 mV

VHYST_COMP Comparator Input Hysteresis 10 — 31 mV

VLATENCY_COMP Comparator Latency — — 31 ns

Note:
1. Comparator is available in select speed grades. See Ordering Information.

3.23. Digital Temperature Readout Characteristics

Digital temperature Readout (DTR) is implemented in one of the channels of ADC1.
Table 3.39. DTR Specifications1, 2
Symbol Description Condition Min Typ Max Unit
DTR Detect Temperature — °C
DTRRANGE –40 — 100
Range
with external voltage1
DTRACCURACY DTR Accuracy reference range of 1.0 V –13 ±4 13 °C

to 1.8 V
with external voltage °C
DTRRESOLUTION DTR Resolution –0.3 — 0.3
reference
Notes:
1. External voltage reference (VREF) should be 0.1% accurate or better. DTR sensitivity to VREF is -4.1 °C per VREF per-cent (for
example, if the VREF is 1 % low, then the DTR will read +4.1 °C high).
2. DTR is available in Commercial/Industrial –8 and –9 speed grades.

FPGA-DS-02049-2.1 85
CrossLink-NX Family
Data Sheet

3.24. Hardened MIPI D-PHY Characteristics

Table 3.40. Hardened D-PHY Input Timing and Levels
Symbol Description Conditions Min Typ Max Unit
High Speed (Differential) Input DC Specifications
Common-mode Voltage in High Speed
VCMRX(DC) — 70 — 330 mV
Mode
0.08 Gbps ≤ VIDTH ≤ 1.5 Gbps 70 — — mV
VIDTH Differential Input HIGH Threshold
1.5 Gbps < VIDTH ≤ 2.5 Gbps 40 — — mV
0.08 Gbps ≤ VIDTL ≤ 1.5 Gbps — — –70 mV
VIDTL Differential Input LOW Threshold
1.5 Gbps < VIDTL ≤ 2.5 Gbps — — –40 mV
VIHHS Input HIGH Voltage (for HS mode) — — — 460 mV
VILHS Input LOW Voltage — –40 — — mV
Single-ended voltage for HS Termination
VTERM-EN — — — 450 mV
Enable4
ZID Differential Input Impedance — 80 100 125 Ω
High Speed (Differential) Input AC Specifications
0.08 Gbps ≤ ∆VCMRX(HF) ≤ 1.5
— — 100 mV
Gbps
ΔVCMRX(HF) 1 Common-mode Interference (>450 MHz)
1.5 Gbps < ∆VCMRX(HF) ≤ 2.5
— — 50 mV
Gbps
0.08 Gbps ≤ ∆VCMRX(LF) ≤ 1.5
–50 — 50 mV
Common-mode Interference (50 MHz–450 Gbps
ΔVCMRX(LF) 2, 3
MHz) 1.5 Gbps < ∆VCMRX(LF) ≤ 2.5
–25 — 25 mV
Gbps

CCM Common-mode Termination — — — 60 pF

Low Power (Single-Ended) Input DC Specifications

VIH Low Power Mode Input HIGH Voltage — 760 — — mV
VIL Low Power Mode Input LOW Voltage — — — 550 mV
VIL-ULP Ultra Low Power Input LOW Voltage — — — 300 mV
VHYST Low Power Mode Input Hysteresis — 25 — — mV
℮SPIKE Input Pulse Rejection — — — 300 V∙ps
TMIN-RX Minimum Pulse Width Response — 20 — — ns
VINT Peak Interference Amplitude — — — 200 mV
fINT Interference Frequency — 450 — — MHz
Contention Detector (LP-CD) DC Specifications
VIHCD Contention Detect HIGH Voltage — 450 — — mV
VILCD Contention Detect LOW Voltage — — — 200 mV
Notes:
1. This is peak amplitude of sine wave modulated to the receiver inputs.
2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs.
3. Exclude any static ground shift of 50 mV.
4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage.

86 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Table 3.41. Hardened D-PHY Output Timing and Levels

Symbol Description Conditions Min Typ Max Unit
High Speed (Differential) Output DC Specifications
Common-mode Voltage in High Speed
VCMTX — 150 200 250 mV
Mode
VCMTX Mismatch Between Differential
|ΔVCMTX(1,0)| — — — 5 mV
HIGH and LOW
|D-PHY-P – D-PHY-
|VOD| Output Differential Voltage 140 200 270 mV
N|
VOD Mismatch Between Differential HIGH
|ΔVOD| — — — 14 mV
and LOW
VOHHS Single-Ended Output HIGH Voltage — — — 360 mV
ZOS Single Ended Output Impedance — 40 50 68 Ω
ΔZOS ZOS mismatch — — — 20 %
High Speed (Differential) Output AC Specifications
Common-Mode Variation, 50 MHz – 450 —
ΔVCMTX(LF) — — 25 mVRMS
MHz
ΔVCMTX(HF) Common-Mode Variation, above 450 MHz — — — 15 mVRMS
0.08 Gbps ≤ tR ≤ 1
— — 0.30 UI
Gbps
1 Gbps < tR ≤ 1.5
— — 0.35 UI
Gbps
tR Output 20%–80% Rise Time
tR ≤ 1.5 Gbps 100 — — ps
1.5 Gbps < tR ≤ 2.5
— — 0.40 UI
Gbps
tR > 1.5 Gbps 50 — — ps
0.08 Gbps ≤ tF ≤ 1
— — 0.30 UI
Gbps
1 Gbps < tF ≤ 1.5
— — 0.35 UI
Gbps
tF Output 80%–20% Fall Time
tF ≤ 1.5 Gbps 100 — — ps
1.5 Gbps < tF ≤ 2.5
— — 0.40 UI
Gbps
tF > 1.5 Gbps 50 — — ps
Low Power (Single-Ended) Output DC Specifications
0.08 Gbps ≤ VOH ≤
1.1 1.2 1.3 V
VOH Low Power Mode Output HIGH Voltage 1.50 Gbps
VOH > 1.50 Gbps 0.95 — 1.3 V
VOL Low Power Mode Input LOW Voltage — –50 — 50 mV
ZOLP Output Impedance in Low Power Mode — 106 — — Ω
Low Power (Single-Ended) Output AC Specifications
tRLP 15%–85% Rise Time — — — 25 ns
tFLP 85%–15% Fall Time — — — 25 ns
HS – LP Mode Rise and Fall Time, 30%–
tREOT — — — 35 ns
85%
First LP XOR Clock
Pulse after STOP
40 — — ns
TLP-PULSE-TX Pulse Width of the LP Exclusive-OR Clock State or Last Pulse
before STOP State
All Other Pulses 20 — — ns
TLP-PER-TX Period of the LP Exclusive-OR Clock — 90 — — ns
δV/δtSR Slew Rate @ CLOAD = 0 pF — — — 500 mV/ns

FPGA-DS-02049-2.1 87
CrossLink-NX Family
Data Sheet

Symbol Description Conditions Min Typ Max Unit

Slew Rate @ CLOAD = 5 pF — — — 300 mV/ns
Slew Rate @ CLOAD = 20 pF — — — 250 mV/ns
Slew Rate @ CLOAD = 70 pF — — — 150 mV/ns
Slew Rate @ CLOAD = 0 to 70 pF (Falling — 30 — — mV/ns
Edge Only) — 25 — — mV/ns
Slew Rate @ CLOAD = 0 to 70 pF (Rising — 30 — — mV/ns
Edge Only) — 25 — — mV/ns
30 - 0.075 ×
— — — mV/ns
Slew Rate @ CLOAD = 0 to 70 pF (Rising (VO,INST - 700)
Edge Only) 25 - 0.0625 ×
— — — mV/ns
(VO,INST - 550)
CLOAD Load Capacitance — 0 — 70 pF

Table 3.42. Hardened D-PHY Pin Characteristic Specifications

Symbol Description Conditions Min Typ Max Unit
Pin Characteristic Specifications
VPIN Pin Signal Voltage Range — –50 — 1350 mV
VPIN_LVLP Pin Signal Voltage Range in LVLP Operation — –50 — 1150 mV
ILEAK Pin Leakage Current — –100 — 100 µA
VGNDSH Ground Shift — –50 — 50 mV
VPIN(absmax) Transient Pin Voltage Level — –0.15 — 1.45 V
Maximum Transient Time above VPIN(max) or
TVPIN(absmax) — — — 20 ns
below VPIN(min)

Table 3.43. Hardened D-PHY Clock Signal Specification

Symbol Description Conditions Min Typ Max Unit
Clock Signal Specification
UI
UIINST — — — 12.5 ns
Instantaneous
— –10% — 10% UI
UI Variation ∆UI
— –5% — 5% UI

Table 3.44. Hardened D-PHY Data-Clock Timing Specifications

Symbol Description Conditions Min Typ Max Unit
Data-Clock Timing Specifications
0.08 Gbps ≤ TSKEW[TX]
–0.15 — 0.15 UIINST
≤ 1.00 Gbps
TSKEW[TX] Data to Clock Skew
1.00 Gbps < TSKEW[TX]
–0.20 — 0.20 UIINST
≤ 1.50 Gbps
0.08 Gbps ≤ TSETUP[RX]
0.15 — — UI
≤ 1.00 Gbps
TSETUP[RX] Input Data Setup Before CLK
1.00 Gbps < TSETUP[RX]
0.20 — — UI
≤ 1.50 Gbps
0.08 Gbps ≤ THOLD[RX]
0.15 — — UI
≤ 1.00 Gbps
THOLD[RX] Input Data Hold After CLK
1.00 Gbps < THOLD[RX]
0.20 — — UI
≤ 1.50 Gbps
FIN_DPHY Input frequency to Hardened D-PHY PLL — 24 200 MHz

88 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Symbol Description Conditions Min Typ Max Unit

TSKEW[TX]
Dynamic Data to Clock Skew (Tx) > 1.5 Gbps –0.15 — 0.15 UIINST
Dynamic
ISI Channel ISI > 1.5 Gbps — — 0.20 UIINST
TSETUP[RX] +
Dynamic Data to Clock Skew Window Rx
THOLD[RX] > 1.5 Gbps 0.50 — — UIINST
Tolerance
Dynamic

3.25. Hardened PCIe Characteristics

3.25.1. PCIe (2.5 Gbps)
Table 3.45. PCIe (2.5 Gbps)
Symbol Description Condition Min. Typ. Max. Unit
Transmitter1
UI Unit Interval — 399.88 400 400.12 ps
BWTX Tx PLL bandwidth — 1.5 — 22 MHz
Differential p-p Tx voltage
VTX-DIFF-PP — 0.8 — 1.2 Vp-p
swing
Low power differential p-p Tx
VTX-DIFF-PP-LOW — 0.4 — 1.2 Vp-p
voltage swing
Tx de-emphasis level ratio at
VTX-DE-RATIO-3.5dB — 3 — 4 dB
3.5 dB
TTX-RISE-FALL Transmitter rise and fall time — 0.125 — — UI
Transmitter Eye, including all
TTX-EYE — 0.75 — — UI
jitter sources
Max. time between jitter
TTX-EYE-MEDIAN-to-MAX-
median and max deviation — — — 0.125 UI
JITTER
from the median
Tx Differential Return Loss, —
RLTX-DIFF 10 — — dB
including pkg and silicon
Tx Common Mode Return Loss,
RLTX-CM 50 MHz < freq < 2.5 GHz 6 — — dB
including pkg and silicon
ZTX-DIFF-DC DC differential Impedance — 80 — 120 Ω
Tx AC peak common mode mV,
VTX-CM-AC-P — — — 20
voltage, RMS RMS
Transmitter short-circuit
ITX-SHORT — — — 90 mA
current
Transmitter DC common-mode
VTX-DC-CM — 0 — 1.2 V
voltage
Electrical Idle Output peak
VTX-IDLE-DIFF-AC-p — — — 20 mV
voltage
Voltage change allowed during
VTX-RCV-DETECT — — — 600 mV
Receiver Detect
TTX-IDLE-MIN Min. time in Electrical Idle — 20 — — ns
Max. time from EI Order Set to
TTX-IDLE-SET-TO-IDLE — — — 8 ns
valid Electrical Idle
Max. time from Electrical Idle
TTX-IDLE-TO-DIFF-DATA — — — 8 ns
to valid differential output
500 ps
LTX-SKEW Lane-to-Lane output skew — — — ps
+ 2 UI

FPGA-DS-02049-2.1 89
CrossLink-NX Family
Data Sheet

Symbol Description Condition Min. Typ. Max. Unit

Receiver2
UI Unit Interval — 399.88 400 400.12 ps
Differential Rx peak-peak
VRX-DIFF-PP — 0.175 — 1.2 Vp-p
voltage
TRX-EYE3 Receiver eye opening time — 0.4 — — UI
Max time delta between
TRX-EYE-MEDIAN-to-MAX-
3 median and deviation from — — — 0.3 UI
JITTER
median
Receiver differential Return
RLRX-DIFF — 10 — — dB
Loss, package plus silicon
Receiver common mode Return
RLRX-CM — 6 — — dB
Loss, package plus silicon
Receiver DC single ended
ZRX-DC — 40 — 60 Ω
impedance
Receiver DC differential
ZRX-DIFF-DC — 80 — 120 Ω
impedance
Receiver DC single ended
ZRX-HIGH-IMP-DC impedance when powered — 200k — — Ω
down
Rx AC peak common mode mV,
VRX-CM-AC-P3 — — — 150
voltage peak
VRX-IDLE-DET-DIFF-PP Electrical Idle Detect Threshold — 65 — 175 mVp-p
LRX-SKEW Receiver –lane-lane skew — — 20 ps
Notes:
1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters.
2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters.
3. Spec compliant requirement

3.25.2. PCIe (5 Gbps)

Table 3.46. PCIe (5 Gbps)
Symbol Description Test Conditions Min Typ Max Unit
Transmit1
UI Unit Interval — 199.94 200 200.06 ps
Tx PLL bandwidth
BWTX-PKG-PLL1 — 8 — 16 MHz
corresponding to PKGTX-PLL1
Tx PLL bandwidth
BWTX-PKG-PLL2 — 5 — 16 MHz
corresponding to PKGTX-PLL2
Tx PLL Peaking
PKGTX-PLL1 — — — 3 dB
corresponding to PKGTX-PLL1
Tx PLL Peaking
PKGTX-PLL2 — — — 1 dB
corresponding to PKGTX-PLL2
Differential p-p Tx voltage
VTX-DIFF-PP — 0.8 — 1.2 V, p-p
swing
Low power differential p-p Tx
VTX-DIFF-PP-LOW — 0.4 — 1.2 V, p-p
voltage swing
Tx de-emphasis level ratio at
VTX-DE-RATIO-3.5dB — 3 — 4 dB
3.5 dB
Tx de-emphasis level ratio at
VTX-DE-RATIO-6dB — 5.5 — 6.5 dB
6 dB
TMIN-PULSE Instantaneous lone pulse width — 0.9 — — UI
TTX-RISE-FALL Transmitter rise and fall time — 0.15 — — UI

90 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Symbol Description Test Conditions Min Typ Max Unit

Transmitter Eye, including all
TTX-EYE — 0.75 — — UI
jitter sources
Tx deterministic jitter > 1.5
TTX-DJ — — — 0.15 UI
MHz
ps,
TTX-RJ Tx RMS jitter < 1.5 MHz — — — 3
RMS
TRF-MISMATCH Tx rise/fall time mismatch — — — 0.1 UI
Tx Differential Return Loss, 50 MHz < freq < 1.25 GHz 10 — — dB
RLTX-DIFF
including package and silicon 1.25 GHz < freq < 2.5 GHz 8 — — dB
Tx Common Mode Return Loss,
RLTX-CM 50 MHz < freq < 2.5 GHz 6 — — dB
including package and silicon
ZTX-DIFF-DC DC differential Impedance — — — 120 Ω
Tx AC peak common mode mV,
VTX-CM-AC-PP — — — 150
voltage, peak-peak p-p
Transmitter short-circuit
ITX-SHORT — — — 90 mA
current
Transmitter DC common-mode
VTX-DC-CM — 0 — 1.2 V
voltage
Electrical Idle Output DC
VTX-IDLE-DIFF-DC — 0 — 5 mV
voltage
Electrical Idle Differential
VTX-IDLE-DIFF-AC-p — — — 20 mV
Output peak voltage
Voltage change allowed during
VTX-RCV-DETECT — — — 600 mV
Receiver Detect
TTX-IDLE-MIN Min. time in Electrical Idle — 20 — — ns
Max. time from EI Order Set to
TTX-IDLE-SET-TO-IDLE — — — 8 ns
valid Electrical Idle
Max. time from Electrical Idle
TTX-IDLE-TO-DIFF-DATA — — — 8 ns
to valid differential output
Receive2
500 + 4
LTX-SKEW Lane-to-Lane output skew — — — ps
UI
UI Unit Interval — 199.94 200 200.06 ps
Differential Rx peak-peak
VRX-DIFF-PP — 0.343 — 1.2 V, p-p
voltage
Receiver random jitter 1.5 MHz – 100 MHz ps,
TRX-RJ-RMS — — 4.2
tolerance (RMS) Random noise RMS
Receiver deterministic jitter
TRX-DJ — — — 88 ps
tolerance
Receiver differential Return 50 MHz < freq < 1.25 GHz 10 — — dB
RLRX-DIFF
Loss, package plus silicon 1.25 GHz < freq < 2.5 GHz 8 — — dB
Receiver common mode
RLRX-CM Return Loss, package plus — 6 — — dB
silicon
Receiver DC single ended
ZRX-DC — 40 — 60 Ω
impedance
Receiver DC single ended
ZRX-HIGH-IMP-DC impedance when powered — 200K — — Ω
down
Rx AC peak common mode mV,
VRX-CM-AC-P3 — — — 150
voltage peak
VRX-IDLE-DET-DIFF-PP Electrical Idle Detect Threshold — 65 — 1753 mv, pp

FPGA-DS-02049-2.1 91
CrossLink-NX Family
Data Sheet

Symbol Description Test Conditions Min Typ Max Unit

LRX-SKEW Receiver –lane-lane skew — — — 8 ns
Notes:
1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters.
2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters.
3. Spec compliant requirement

3.26. SGMII Characteristics

3.26.1. SGMII Specifications
Table 3.47. SGMII
Symbol Description Test Conditions Min Typ Max Unit
fDATA SGMII Data Rate — — 1250 — MHz
SGMII Reference Clock Frequency (Data
fREFCLK — — 125 — MHz
Rate / 10)
Periodic jitter
JTOL_Dj Jitter Tolerance, Deterministic — — 0.11 UI
< 300 kHz
Periodic jitter
JTOL_Tj Jitter Tolerance, Total — — 0.31 UI
< 300 kHz
Δf/f Data Rate and Reference Clock Accuracy — –300 — 300 ppm
Notes:
1. JTOT can meet the following jitter mask specification: 0 to 3.5 kHz: 10 UI; 3.5 to 700 kHz: log-log slope 10 UI to 0.05 UI; above
700 kHz: 0.05 UI.
2. SGMII is not supported on 72-pin packages (QFN and WLCSP).

3.27. sysCONFIG Port Timing Specifications

Table 3.48. sysCONFIG Port Timing Specifications
Symbol Parameter Device Min Typ. Max Unit
Controller SPI POR/REFRESH Timing

REFRESH command executed, to the rising

tICFG — — — 30 µs
edge of INITN (bulk-erase off)

Time from rising edge of INITN to the valid

tVMC — — — 5 µs
Controller MCLK
fMCLK_DEF Default MCLK frequency (Before MCLK — — 3.5 — MHz
frequency selection in bitstream)

Time during POR, from VCC, VCCAUX, VCCIO0,

tICFG_POR or VCCIO1 (whichever is the last) pass POR trip — — — 5 ms
voltage, to the rising edge if INITN

Target SPI/I2C/I3C POR

Time during POR, from VCC, VCCAUX, VCCIO0 or

VCCIO1 (whichever is the last) pass POR trip
tMSPI_INH — — — 1 µs
voltage, to pull PROGRAMN LOW to prevent
entering MSPI mode

Minimum time driving PROGRAMN HIGH after 50

tACT_PROGRAMN_H — — — ns
last activation clock
Minimum time to start driving CCLK (SSPI) 50
tCONFIG_CCLK — — — ns
after PROGRAMN HIGH

92 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Symbol Parameter Device Min Typ. Max Unit

Minimum time to start driving SCL (I2C/I3C) 50
tCONFIG_SCL — — — ns
after PROGRAMN HIGH
PROGRAMN Configuration Timing
tPROGRAMN_L PROGRAMN LOW pulse accepted — 50 — — ns
tPROGRAMN_H PROGRAMN HIGH pulse accepted — 60 — — ns
tPROGRAMN_RJ PROGRAMN LOW pulse rejected — — — 25 ns
tINIT_LOW PROGRAMN LOW to INITN LOW — — — 100 ns
PROGRAMN LOW to INITN HIGH (bulk-erase
tINIT_HIGH — — — 40 µs
off)
tDONE_LOW PROGRAMN LOW to DONE LOW — — — 55 µs
tDONE_HIGH2 PROGRAMN HIGH to DONE HIGH — — 2 s
tIODISS PROGRAMN LOW to I/O Disabled — — — 125 ns
Controller SPI
fMCLK1 Max selected MCLK output frequency — — 150 165 MHz
fMCLK_DC MCLK output clock duty cycle — 40 — 60 %
tMCLKH MCLK output clock pulse width HIGH — 3 — — ns
tMCLKL MCLK output clock pulse width LOW — 3 — — ns
tSU_MSI MSI to MCLK setup time — 3 — — ns
tHD_MSI MSI to MCLK hold time — 0.5 — — ns
tCO_MSO2 MCLK to MSO delay — — — 12 ns
Target SPI
fCCLK_W CCLK input clock frequency — — — 135 MHz
(For write transaction)4
fCCLK_R CCLK input clock frequency — — — —6 MHz
(For read transaction)5
tCCLKH CCLK input clock pulse width HIGH — 3.5 — — ns
tCCLKL CCLK input clock pulse width LOW — 3.5 — — ns
tVMC_SLAVE Time from rising edge of INITN to Target CCLK — 50 — — ns
driven
tVMC_MASTER CCLK input clock duty cycle — 40 — 60 %
tSU_SSI SSI to CCLK setup time — 3.2 — — ns
tHD_SSI SSI to CCLK hold time — 1.9 — — ns
tCO_SSO CCLK falling edge to valid SSO output — 3.07 — 167 ns
tEN_SSO CCLK falling edge to SSO output enabled — 3.07 — 167 ns
tDIS_SSO CCLK falling edge to SSO output disabled — 3.07 — 167 ns
tHIGH_SCSN SCSN HIGH time — 74 — — ns
tSU_SCSN SCSN to CCLK setup time — 3.5 — — ns
tHD_SCSN SCSN to CCLK hold time — 1.6 — — ns
I2C/I3C
fSCL_I2C SCL input clock frequency for I2C — — — 1 MHz
fSCL_I3C SCL input clock frequency for I3C — — — 12 MHz
tSCLH_I2C SCL input clock pulse width HIGH for I2C — 400 — — ns
tSCLL_I2C SCL input clock pulse width LOW for I2C — 400 — — ns
tSU_SDA_I2C SDA to SCL setup time for I2C — 250 — — ns
tHD_SDA_I2C SDA to SCL hold time for I2C — 50 — — ns
tSU_SDA_I3C SDA to SCL setup time for I3C — 30 — — ns
tHD_SDA_I3C SDA to SCL hold time for I3C — 30 — — ns

FPGA-DS-02049-2.1 93
CrossLink-NX Family
Data Sheet

Symbol Parameter Device Min Typ. Max Unit

tCO_SDA SCL falling edge to valid SDA output — — — 200 ns
tEN_SDA SCL falling edge to SDA output enabled — — — 200 ns
tDIS_SDA SCL falling edge to SDA output disabled — — — 200 ns
Wake-Up Timing
Last configuration clock cycle to DONE going
tWAKEUP_DONE_HIGH2 — — — 60 µs
HIGH
LIFCL-40 — — 31184 cycles
tFIO_EN2 User I/O enabled in Early I/O Mode
LIFCL-17 — — 20688 cycles
tIOEN2 Config clock to user I/O enabled — 130 — — ns
tMCLKZ2, 3 Controller MCLK to Hi-Z — — — 2.5 µs
Notes:
1. fMCLK has a dependency on HFOSC and is 1/3 of fCLKHF.
2. Based on 30k uncompressed/unauthenticated/default MCLK timing (3.5 MHz)/x1. Other permutations result in different values.
3. Measure using LVCMOS18, default MCLK frequency, slow slew rate.
4. Supported input clock frequency for bursting in configuration bitstream to the device.
5. Supported input clock frequency for reading out data transactions from the device.
6. Refer to the following equations to determine the supported input clock frequency for read transaction. Assumption: The skew
between CCLK and SSO on board is zero.
½ 𝐶𝐶𝐿𝐾 – 𝑡𝐶𝑂(𝑚𝑎𝑥) – 𝑇𝑠𝑢 > 0

𝐶𝐶𝐿𝐾 > 2(𝑡𝐶𝑂(𝑚𝑎𝑥) + 𝑇𝑠𝑢)

CCLK – Input clock period. fCCLK_R = 1/CCLK.

tCO(max) – Equivalent to tCO_SSO or tEN_SSO max value.
Tsu – Setup time requirement for host controller I/O.

For customer that can only use single clock for read/write operation, the Fmax will be limited by the Fmax for read operation.
For example: tCO(max)=30ns and Tsu=2ns.
𝐶𝐶𝐿𝐾 > 2(𝑡𝐶𝑂(𝑚𝑎𝑥) + 𝑇𝑠𝑢)

𝐶𝐶𝐿𝐾 > 2(30𝑛𝑠 + 2𝑛𝑠)

𝐶𝐶𝐿𝐾 > 64𝑛𝑠

𝑓𝐶𝐶𝐿𝐾_𝑅 = 1/64𝑛𝑠 = 15.62𝑀𝐻𝑧

For customer that want to do the programming at 135Mhz or faster than Fmax for read operation:
• Have a mechanism in the host controller to switch between read clock and write clock for read/write transaction. For
example refer to SPI specification to switch between read and write clock by changing the SPI Baud Rate Register (SPIBR) if
standard SPI controller is used as the host.
• or implementing a mechanism to adjust/calibrate the sampling clock edge when the valid data becomes available.
7. Based on SLOW(default) slew rate control on Config output pins.

94 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

REFRESH Command tICFG

VCC/VCCAUX/
VCCIO0/VCCIO1 tICFG_POR

INITN

DONE

PROGRAMN fMCLK_DEF
tVMC
MCLK

MSI

Figure 3.14. Controller SPI POR/REFRESH Timing

VCC/VCCAUX/
VCCIO0/VCCIO1 tICFG_POR

REFRESH Command tICFG

INITN

DONE
tMSPI_INH tACT_CRESETB_N
PROGRAMN Slave Activation

tACT_CCLK fCCLK tCONFIG_CCLK

CCLK

SSI
tACT_SCL fSCL tACT_CRESETB_N
tCONFIG_SCL
SCL

SDA

Figure 3.15. Target SPI/I2C/I3C POR/REFRESH Timing

FPGA-DS-02049-2.1 95
CrossLink-NX Family
Data Sheet

Figure 3.16. Controller SPI PROGRAMN Timing

Figure 3.17. Target SPI/I2C/I3C PROGRAMN Timing

96 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

fMCLK
tMCLKH
tMCLKL
MCLK tHD_MISO
tSU_MISO
MSI
tCO_MOSI

MSO

Figure 3.18. Controller SPI Configuration Timing

fCCLK
tCCLKH
CCLK tCCLKL

tSU_SSI tHD_SSI

SSI

tSU_SCSN tHD_SCSN

SCSN
tHIGH_SCSN

tCO_SSO

SSO
tEN_SSO tDIS_SSO

SSO

Figure 3.19. Target SPI Configuration Timing

fSCL
tSCLH
SCL
tSCLL
tSU_SDA tHD_SDA

SDA (input)

tCO_SDA
SDA (output)

tDIS_SDA
tEN_SDA
SDA (output)

Figure 3.20. I2C /I3C Configuration Timing

FPGA-DS-02049-2.1 97
CrossLink-NX Family
Data Sheet

CRESET_B

INITN
tWAK EUP_DONE_HIG H Device Wake-Up

DONE
CONFIG tMWC
Starts fMCLK_def fMCLK tMCLKZ
MCLK

tFIO_EN
USER I/O tIOEN
(FAST I/O)

tIOEN
USER I/O

Figure 3.21. Controller SPI Wake-Up Timing

CRESET_B

INITN
tWAK EUP_DONE_HIG H Device Wake-Up

DONE
CONFIG
Starts

CCLK/SCL
tFIO_EN
USER I/O tIOEN
(FAST I/Os)

tIOEN
USER I/O

Figure 3.22. Target SPI/I2C/I3C Wake-Up Timing

tINIT _HIGH tPR OGR AM_H

MSPI
Configuration
PROGRAMN tPR OGR AM_L SSPI/I2C/I3C
Configuration
tINIT L Configuration tINIT _HIGH
Error
INITN tINIT _HIGH Restart
Configuration
Configuration
DONE Started

Figure 3.23. Configuration Error Notification

98 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

3.28. JTAG Port Timing Specifications

Table 3.49. JTAG Port Timing Specifications
Symbol Parameter Min Typ. Max Units
fMAX TCK clock frequency — — 25 MHz
tBTCPH TCK clock pulse width high 20 — — ns
tBTCPL TCK clock pulse width low 20 — — ns
tBTS TCK TAP setup time 5 — — ns
tBTH TCK TAP hold time 5 — — ns
tBTRF TAP controller TDO rise/fall time1 100 — — mV/ns
tBTCO TAP controller falling edge of clock to valid output — — 14 ns
tBTCODIS TAP controller falling edge of clock to valid disable — — 14 ns
tBTCOEN TAP controller falling edge of clock to valid enable — — 14 ns
tBTCRS BSCAN test capture register setup time 8 — — ns
tBTCRH BSCAN test capture register hold time 25 — — ns
tBUTCO BSCAN test update register, falling edge of clock to valid output — — 25 ns
tBTUODIS BSCAN test update register, falling edge of clock to valid disable — — 25 ns
tBTUPOEN BSCAN test update register, falling edge of clock to valid enable — — 25 ns
Note:
1. Based on default I/O setting of slow slew rate.

TMS

TDI

tBTS tBTH

tBTCPH tBTCPL tBTCP

TCK

tBTCOEN tBTCO tBTCODIS

TDO V a lid D a ta V a lid D a ta

tBTCRH
tBTCRS
Data to be
Captured Data Captured
from I/O

tBTUPOEN tBUTCO tBTUODIS

Data to be
driven out V a lid D a ta V a lid D a ta
to I/O

Figure 3.24. JTAG Port Timing Waveforms

FPGA-DS-02049-2.1 99
CrossLink-NX Family
Data Sheet

3.29. Switching Test Conditions

Figure 3.25 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are listed in Table 3.50.

R1
DUT Test Point

R2 CL*

*CL Includes Test Fixture and Probe Capacitance

Figure 3.25. Output Test Load, LVTTL and LVCMOS Standards

Table 3.50. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition R1 R2 CL Timing Ref. VT
LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)   0 pF LVCMOS 3.3 = 1.5 V —
LVCMOS 2.5 = VCCIO/2 —
LVCMOS 1.8 = VCCIO/2 —
LVCMOS 1.5 = VCCIO/2 —
LVCMOS 1.2 = VCCIO/2 —
LVCMOS 2.5 I/O (Z ≥ H)  1 MΩ 0 pF VCCIO/2 —
LVCMOS 2.5 I/O (Z ≥ L) 1 MΩ  0 pF VCCIO/2 VCCIO
LVCMOS 2.5 I/O (H ≥ Z)  100 0 pF VOH – 0.10 —
LVCMOS 2.5 I/O (L ≥ Z)  0 pF 100 VOL + 0.10 VCCIO
Note:
1. Output test conditions for all other interfaces are determined by the respective standards.

100 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

4. DC and Switching Characteristics for Automotive

All specifications in this Chapter are characterized within recommended operating conditions unless otherwise
specified.

4.1. Absolute Maximum Ratings

Table 4.1. Absolute Maximum Ratings
Symbol Parameter Min Max Unit
VCC, VCCECLK Supply Voltage –0.5 1.10 V
VCCAUX, VCCAUXA, Supply Voltage –0.5 1.98 V
VCCAUXH3, VCCAUXH4,
VCCAUXH5
VCCIO0, 1, 2, 6, 7 I/O Supply Voltage –0.5 3.63 V
VCCIO3, 4, 5 I/O Supply Voltage –0.5 1.98 V
VCCPLL_DPHY0, 1 Hardened D-PHY PLL Supply Voltage –0.5 1.10 V
VCCPLLSD0 SerDes Block PLL Supply Voltage –0.5 1.98 V
VCCA_DPHY0, 1 Analog Supply Voltage for Hardened D-PHY –0.5 1.98 V
VCC_DPHY0, 1 Digital Supply Voltage for Hardened D-PHY –0.5 1.10 V
VCCSD0 SerDes Supply Voltage –0.5 1.10 V
VCCADC18 ADC Block 1.8 V Supply Voltage –0.5 1.98 V
VCCAUXSD SerDes and AUX Supply Voltage –0.5 1.98 V
— Input or I/O Voltage Applied, Bank 0, Bank –0.5 3.63 V
1,Bank 2, Bank 6, Bank 7
— Input or I/O Voltage Applied, Bank 3, Bank 4, –0.5 1.98 V
Bank 5
— Voltage Applied on SerDes Pins –0.5 1.98 V
TA Storage Temperature (Ambient) –65 +150 °C
TJ Junction Temperature — +125 °C
Notes:
1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. All VCCAUX should be connected on PCB.

FPGA-DS-02049-2.1 101
CrossLink-NX Family
Data Sheet

4.2. Recommended Operating Conditions1, 2, 3

Table 4.2. Recommended Operating Conditions
Symbol Parameter Conditions Min Typ. Max Unit
VCC, VCCECLK Core Supply Voltage VCC = 1.0 0.95 1.00 1.05 V
Bank 0, Bank 1, Bank 2, Bank 6,
VCCAUX Auxiliary Supply Voltage 1.746 1.80 1.89 V
Bank 7
VCCAUXH3/4/5 Auxiliary Supply Voltage Bank 3, Bank 4, Bank 5 1.746 1.80 1.89 V
Auxiliary Supply Voltage for
VCCAUXA — 1.746 1.80 1.89 V
core logic
VCCIO = 3.3 V, Bank 0, Bank 1,
3.135 3.30 3.465 V
Bank 2, Bank 6, Bank 7
VCCIO = 2.5 V, Bank 0, Bank 1,
2.375 2.50 2.625 V
Bank 2, Bank 6, Bank 7
VCCIO = 1.8 V, All Banks 1.71 1.80 1.89 V
VCCIO I/O Driver Supply Voltage VCCIO = 1.5 V, All Banks4 1.425 1.50 1.575 V
VCCIO = 1.35 V, All Banks (For
1.2825 1.35 1.4175 V
DDR3L Only)
VCCIO = 1.2 V, All Banks4 1.14 1.20 1.26 V
VCCIO = 1.0 V, Bank 3, Bank 4,
0.95 1.00 1.05 V
Bank 5
D-PHY External Power Supplies
D-PHY Analog Power
VCCA_D-PHY — 1.71 1.80 1.89 V
Supply
VCC_D-PHY D-PHY Digital Power Supply — 0.95 1.00 1.05 V
VCCPLL_D-PHY D-PHY PLL Power Supply — 0.95 1.00 1.05 V
ADC External Power Supplies
VCCADC18 ADC 1.8 V Power Supply — 1.71 1.80 1.89 V
SerDes Block External Power Supplies
Supply Voltage for SerDes
VCCSD0 — 0.95 1.00 1.05 V
Block and SerDes I/O
SerDes Block PLL Supply
VCCPLLSD0 — 1.71 1.80 1.89 V
Voltage
SerDes Block Auxiliary
VCCAUXSD — 1.71 1.80 1.89 V
Supply Voltage
Operating Temperature
Junction Temperature,
tJAUTO — –40 — 125 °C
Automotive Operation
Notes:
1. For correct operation, all supplies must be held in their valid operation voltage range.
2. All supplies with same voltage should be from the same voltage source. Proper isolation filters are needed to properly isolate
noise from each other.
3. Common supply rails must be tied together except SerDes.
4. MSPI (Bank 0) and JTAG, SSPI, I2C, and I3C (Bank 1) ports are supported for VCCIO = 1.8 V to 3.3 V.

102 FPGA-DS-02049-2.1
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Data Sheet

4.3. Power Supply Ramp Rates

Table 4.3. Power Supply Ramp Rates
Symbol Parameter Min Typ Max Unit
tRAMP Power Supply ramp rates for all supplies 1 0.1 — 50 V/ms
Notes:
1. Assumes monotonic ramp rates.
2. All supplies need to be in the operating range as defined in Recommended Operating Conditions1, when the device has
completed configuration and entering into User Mode. Supplies that are not in the operating range needs to be adjusted to
faster ramp rate, or users have to delay configuration or wake up.

4.4. Power up Sequence

Power-On-Reset (POR) puts the CrossLink-NX device into a reset state. There is no power up sequence required for the
CrossLink-NX device.
Table 4.4. Power-On Reset
Symbol Parameter Min Typ Max Unit
Power-On-Reset ramp-up trip VCC 0.72 — 0.84 V
VPORUP point (Monitoring VCC, VCCAUX, VCCAUX 1.30 — 1.71 V
VCCI00, and VCCI01) VCCIO0,VCCI01 0.87 — 1.07 V
Power-On-Reset ramp-up trip VCC 0.48 — 0.85 V
VPORDN
point (Monitoring VCC and VCCAUX) VCCAUX 1.36 — 1.57 V

4.5. On-Chip Programmable Termination

V CCI O Zo = 50
TERM
Zo = 40 , 50 , 60 , or 75
control
to VCCIO /2
Zo
Zo +
2Zo -
Zo +
- Zo
VREF

OFF-chip ON-chip OFF-chip ON-chip

Parallel Single-Ended Input Differential Input

Figure 4.1. On-Chip Termination

See Table 4.5 for termination options for input modes.

FPGA-DS-02049-2.1 103
CrossLink-NX Family
Data Sheet

Table 4.5. On-Chip Termination Options for Input Modes

4.6. Hot Socketing Specifications

Table 4.6. Hot Socketing Specifications for GPIO
Symbol Parameter Condition Min Typ Max Unit
0 < VIN < VIH(max)
Input or I/O Leakage Current for
0 < VCC < VCC(max)
IDK Wide Range I/O (excluding -1.5 — 1.5 mA
0 < VCCIO < VCCIO (max)
MCLK/MCSN/MOSI/INITN/DONE)
0 < VCCAUX < VCCAUX (max)
Notes:
• IDK is additive to IPU, IPD, or IBH.
• Hot socketing specs are defined at a device junction temperature of 85 °C or below. When the device temperature is above
85 oC, the IDK current can exceed the above spec.
• Going beyond the hot socketing ranges specified here will cause exponentially higher Leakage currents and potential reliability
issues. A total of 64 mA per 8 I/O should not be exceeded.

4.7. ESD Performance

Refer to the CrossLink-NX Product Family Qualification Summary for complete Automotive grade qualification data,
including ESD performance.

104 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

4.8. DC Electrical Characteristics

Table 4.7. DC Electrical Characteristics – Wide Range
Symbol Parameter Condition Min Typ Max Unit
Input or I/O Leakage current
IIL, IIH1 0 ≤ VIN ≤ VCCIO — — 10 µA
(Commercial/Industrial)
IIH2 Input or I/O Leakage current VCCIO ≤ VIN ≤ VIH (max) — — 100 µA
I/O Weak Pull-up Resistor
IPU 0 ≤ VIN ≤ 0.7 × VCCIO –30 — –150 µA
Current
I/O Weak Pull-down Resistor
IPD VIL (max) ≤ VIN ≤ VCCIO 30 — 150 µA
Current
IBHLS Bus Hold Low Sustaining Current VIN = VIL (max) 30 — µA
IBHHS Bus Hold High Sustaining Current VIN = 0.7 × VCCIO –30 — µA
IBHLO Bus Hold Low Overdrive Current 0 ≤ VIN ≤ VCCIO — — 150 µA
IBHHO Bus Hold High Overdrive Current 0 ≤ VIN ≤ VCCIO — — –150 µA
VBHT Bus Hold Trip Points — VIL (max) — VIH (min) V
Notes:
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus
Maintenance circuits are disabled.
2. The input leakage current IIH is the worst case input leakage per GPIO when the pad signal is high and also higher than the bank
VCCIO. This is considered a mixed mode input.

Table 4.8. DC Electrical Characteristics – High Speed

Symbol Parameter Condition Min Typ Max Unit
IIL, IIH1 Input or I/O Leakage 0 ≤ VIN ≤ VCCIO — — 10 µA
I/O Weak Pull-up Resistor —
IPU 0 ≤ VIN ≤ 0.7 × VCCIO –30 –150 µA
Current
I/O Weak Pull-down Resistor —
IPD VIL (max) ≤ VIN ≤ VCCIO 30 150 µA
Current
IBHLS Bus Hold Low Sustaining Current VIN = VIL (max) 30 — — µA
IBHHS Bus Hold High Sustaining Current VIN = 0.7 × VCCIO –30 — — µA
IBHLO Bus Hold low Overdrive Current 0 ≤ VIN ≤ VCCIO — — 150 µA
IBHHO Bus Hold high Overdrive Current 0 ≤ VIN ≤ VCCIO — — –150 µA
VIL
VBHT Bus Hold Trip Points — — VIH (min) V
(max)
Note:
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus
Maintenance circuits are disabled.

Table 4.9. Capacitors – Wide Range

FPGA-DS-02049-2.1 105
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Data Sheet

Table 4.10. Capacitors – High Performance

Table 4.11. Single Ended Input Hysteresis – Wide Range

IO_TYPE VCCIO TYP Hysteresis
LVCMOS33 3.3 V 250 mV
3.3 V 200 mV
LVCMOS25
2.5 V 250 mV
LVCMOS18 1.8 V 180 mV
LVCMOS15 1.5 V 50 mV
LVCMOS12 1.2 V 0
LVCMOS10 1.2 V 0

Table 4.12. Single Ended Input Hysteresis – High Performance

IO_TYPE VCCIO TYP Hysteresis
LVCMOS18H 1.8 V 180 mV
1.8 V 50 mV
LVCMOS15H
1.5 V 150 mV
LVCMOS12H 1.2 V 0
LVCMOS10H 1.0 V 0
MIPI-LP-RX 1.2 V >25 mV

4.9. Supply Currents

For estimating and calculating current, use Power Calculator in Lattice Design software.
This operating and peak current is design dependent, and can be calculated in Lattice Design software. Some blocks can
be placed into low current standby modes. Refer to Power Management and Calculation for CrossLink-NX Devices
(FPGA-TN-02075).

106 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

4.10. sysI/O Recommended Operating Conditions

Table 4.13. sysI/O Recommended Operating Conditions
Support Banks VCCIO (Input) VCCIO (Output)
Standard
Typ. Typ.
Single-Ended
LVCMOS33 0, 1, 2, 6, 7 3.3 3.3
LVTTL33 0, 1, 2, 6, 7 3.3 3.3
LVCMOS25¹, ² 0, 1, 2, 6, 7 2.5, 3.3 2.5
LVCMOS18¹, ² 0, 1, 2, 6, 7 1.2, 1.5, 1.8, 2.5, 3.3 1.8
LVCMOS18H 3, 4, 5 1.8 1.8
LVCMOS15¹, ² 0, 1, 2, 6, 7 1.2, 1.5, 1.8, 2.5, 3.3 1.5
LVCMOS15H¹ 3, 4, 5 1.5, 1.8 1.5
LVCMOS12¹, ² 0, 1, 2, 6, 7 1.2, 1.5, 1.8, 2.5, 3.3 1.2
LVCMOS12H¹ 3, 4, 5 1.2, 1.357, 1.5, 1.8 1.2
LVCMOS10¹ 0, 1, 2, 6, 7 1.2, 1.5, 1.8, 2.5, 3.3 —
LVCMOS10H¹ 3, 4, 5 1.0, 1.2, 1.357, 1.5, 1.8 1.0
LVCMOS10R¹ 3, 4, 5 1.0, 1.2, 1.357, 1.5, 1.8 —
SSTL135_I, SSTL135_II3 3, 4, 5 1.357 1.35
SSTL15_I, SSTL15_II3 3, 4, 5 1.58 1.58
HSTL15_I3 3, 4, 5 1.58 1.58
HSUL123 3, 4, 5 1.2 1.2
MIPI D-PHY LP Input6 3, 4, 5 1.2 1.2
Differential6
LVDS 3, 4, 5 1.2, 1.35, 1.5, 1.8 1.8
LVDSE5 0, 1, 2, 6, 7 — 2.5
subLVDS 3, 4, 5 1.2, 1.35, 1.5, 1.8 —
subLVDSE5 0, 1, 2, 6, 7 — 1.8
subLVDSEH5 3, 4, 5 — 1.8
SLVS6 3, 4, 5 1.0, 1.2, 1.357, 1.5, 1.84 1.2, 1.357, 1.5, 1.8 4
MIPI D-PHY6 3, 4, 5 1.2 1.2
LVCMOS33D5 0, 1, 2, 6, 7 — 3.3
LVTTL33D5 0, 1, 2, 6, 7 — 3.3
LVCMOS25D5 0, 1, 2, 6, 7 — 2.5
SSTL135D_I, SSTL135D_II5 3, 4, 5 — 1.357
SSTL15D_I, SSTL15D_II5 3, 4, 5 — 1.5
HSTL15D_I5 3, 4, 5 — 1.5
HSUL12D5 3, 4, 5 — 1.2
Notes:
1. Single-ended input can mix into I/O Banks with VCCIO different from the standard requires due to some of these input standards
use internal supply voltage source (VCC, VCCAUX) to power the input buffer, which makes them to be independent of V CCIO
voltage. For more details, please refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067). The following is a brief
guideline to follow:
a. Weak pull-up on the I/O must be set to OFF.
b. Bank 3, Bank 4, and Bank 5 I/O can only mix into banks with VCCIO higher than the pin standard, due to clamping diode on
the pin in these banks. Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 does not have this restriction.
c. LVCMOS25 uses VCCIO supply on input buffer in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7. It can be supported with V CCIO =
3.3 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO. Hysteresis has to be disabled
when using 3.3 V supply voltage.
d. LVCMOS15 uses VCCIO supply on input buffer in Bank 3, Bank 4, and Bank 5. It can be supported with VCCIO = 1.8 V to meet
the VIH and VIL requirements, but there is additional current drawn on VCCIO.

FPGA-DS-02049-2.1 107
CrossLink-NX Family
Data Sheet

2. Single-ended LVCMOS inputs can mixed into I/O Banks with different VCCIO, providing weak pull-up is not used.
For additional information on Mixed I/O in Bank VCCIO, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067).
3. These inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses V CCAUXH
power supply. These inputs require the VREF pin to provide the reference voltage in the Bank. Refer to sysI/O User Guide for
Nexus Platform (FPGA-TN-02067) for details.
4. All differential inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses
VCCAUXH power supply. There is no differential input signaling supported in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7.
5. These outputs are emulating differential output pair with single-ended output drivers with true and complement outputs
driving on each of the corresponding true and complement output pair pins. The common mode voltage, V CM, is ½ × VCCIO. Refer
to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details.
6. Soft MIPI D-PHY HS using sysI/O is supported with SLVS input and output that can be placed in banks with V CCIO voltage shown
in SLVS. D-PHY with HS and LP modes supported needs to be placed in banks with VCCIO voltage = 1.2 V. Soft MIPI D-PHY LP input
and output using sysI/O are supported with LVCMOS12.
7. VCCIO = 1.35 V is only supported in Bank 3, Bank 4, and Bank 5, for use with DDR3L interface in the bank. These Input and Output
standards can fit into the same bank with the VCCIO = 1.35 V.
8. LVCMOS15 input uses VCCIO supply voltage. If VCCIO is 1.8 V, the DC levels for LVCMOS15 are still met, but there could be increase
in input buffer current.

4.11. sysI/O Single-Ended DC Electrical Characteristics3

Table 4.14. sysI/O DC Electrical Characteristics – Wide Range I/O
Input/Output VIL VIH VOL Max VOH Min
IOL(mA) IOH(mA)
Standard2 Min (V) Max (V) Min (V) Max (V) (V) (V)
— 2, 4, 8, -2, -4, -8,
LVTTL33
0.8 2.0 3.4654 0.4 VCCIO – 0.4 12, 16, -12, -16,
LVCMOS33
“50RS”3 “50RS”3
— 2, 4, 8, -2, -4, -8,
LVCMOS25 0.7 1.7 3.4654 0.4 VCCIO – 0.45 10, -10,
“50RS”3 “50RS”3
— 2, 4, 8, -2, -4, -8,
LVCMOS18 0.35 × VCCIO 0.65 × VCCIO 3.4654 0.4 VCCIO – 0.45
“50RS”3 “50RS”3
LVCMOS15 — 0.35 × VCCIO 0.65 × VCCIO 3.4654 0.4 VCCIO – 0.4 2, 4 -2, -4
LVCMOS12 — 0.35 × VCCIO 0.65 × VCCIO 3.4654 0.4 VCCIO – 0.4 2, 4 -2, -4
LVCMOS10 — 0.35 × VCCIO 0.65 × VCCIO 3.4654 No O/P Support
Notes:
1. For electro-migration, the average DC current drawn by the I/O pads within a bank of I/O shall not exceed 10 mA per I/O
average.
2. For the types of I/O standard supported in which bank, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for
details.
3. Select “50RS” in driver strength is selecting 50 Ω series impedance driver.
4. VIH (MAX) for inputs on these standards (in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7) can go up to 3.465 V if the input clamp is
OFF. Otherwise, the input cannot be higher than VCCIO + 0.3 V.

108 FPGA-DS-02049-2.1
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Data Sheet

Table 4.15. sysI/O DC Electrical Characteristics – High Performance I/O3

Input/Output VIL VIH VOL Max VOH Min
IOL (mA) IOH (mA)
Standard2 Min (V) Max (V) Min (V) Max (V) (V) (V)
-2, -4, -8,
0.35 × VCCIO + 2, 4, 8, 12,
LVCMOS18H — 0.65 × VCCIO 0.4 VCCIO – 0.45 -12,
VCCIO 0.3 “50RS”3
“50RS”3
0.35 × VCCIO + 2, 4, 8, -2, -4, -8,
LVCMOS15H — 0.65 × VCCIO 0.4 VCCIO – 0.4
VCCIO 0.3 “50RS”3 “50RS”3
0.35 × VCCIO + 2, 4, 8, -2, -4, -8,
LVCMOS12H — 0.65 × VCCIO 0.4 VCCIO – 0.4
VCCIO 0.3 “50RS”3 “50RS”3
0.35 × VCCIO + 0.27 ×
LVCMOS10H — 0.65 × VCCIO 0.75 × VCCIO 2, 4 -2, -4
VCCIO 0.3 VCCIO
VCCIO +
SSTL15_I — VREF – 0.10 VREF + 0.1 0.30 VCCIO – 0.30 7.5 –7.5
0.3
VCCIO +
SSTL15_II — VREF – 0.10 VREF + 0.1 0.30 VCCIO – 0.30 8.8 –8.8
0.3
VCCIO +
HSTL15_I — VREF – 0.10 VREF + 0.1 0.40 VCCIO – 0.40 8 –8
0.3
VCCIO +
SSTL135_I — VREF – 0.09 VREF + 0.09 0.27 VCCIO – 0.27 6.75 –6.75
0.3
VCCIO +
SSTL135_II — VREF – 0.09 VREF + 0.09 0.27 VCCIO – 0.27 8 –8
0.3
VCCIO +
LVCMOS10R — VREF – 0.10 VREF + 0.10 — — — —
0.3
VCCIO + 8.0, 7.5, -8.0, -7.5,
HSUL12 — VREF – 0.10 VREF + 0.10 0.3 VCCIO – 0.3
0.3 6.25, 5 -6.25, -5
Notes:
For electro-migration, the average DC current drawn by the I/O pads within a bank of I/O shall not exceed 10 mA per I/O average.
1. For the types of I/O standard supported in which bank, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for
details.
2. Select “50RS” in driver strength is selecting 50 Ω series impedance driver.

Table 4.16. I/O Resistance Characteristics

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Data Sheet

Table 4.17. VIN Maximum Overshoot/Undershoot Allowance – Wide Range1, 2

AC Voltage Overshoot % of UI at –40 °C to 125 °C AC Voltage Undershoot % of UI at –40 °C to 125 °C
VCCIO + 0.4 100.0% –0.4 100.0%
VCCIO + 0.5 100.0% –0.5 44.2%
VCCIO + 0.6 94.0% –0.6 10.1%
VCCIO + 0.7 21.0% –0.7 1.3%
VCCIO + 0.8 10.2% –0.8 0.3%
VCCIO + 0.9 2.5% –0.9 0.1%
Notes:
1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the
values in this table.
2. For UI less than 20 µs.

Table 4.18. VIN Maximum Overshoot/Undershoot Allowance – High Performance1, 2

AC Voltage Overshoot % of UI at –40 °C to 125 °C AC Voltage Undershoot % of UI at –40 °C to 125 °C
VCCIO + 0.5 100.0% –0.5 100.0%
VCCIO + 0.6 47.3% –0.6 47.3%
VCCIO + 0.7 10.9% –0.7 10.9%
VCCIO + 0.8 2.7% –0.8 2.7%
VCCIO + 0.9 0.7% –0.9 0.7%
Notes:
1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the
values in this table.
2. For UI less than 20 µs.

4.12. sysI/O Differential DC Electrical Characteristics

4.12.1. LVDS
LVDS input buffer on CrossLink-NX is operating with VCCAUX = 1.8 V and independent of Bank VCCIO voltage. LVDS output
buffer is powered by the Bank VCCIO at 1.8 V.
LVDS can only be supported in Bank 3, Bank 4, and Bank 5. LVDS25 output can be emulated with LVDS25E in Bank 0,
Bank 1, Bank 2, Bank 6, and Bank 7. This is described in LVDS25E (Output Only) section.
Table 4.19. LVDS DC Electrical Characteristics1
Parameter Description Test Conditions Min Typ Max Unit
VINP, VINM Input Voltage — 0 — 1.60 V
VICM Input Common Mode Voltage Half the sum of the two Inputs 0.05 — 1.55 2 V
VTHD Differential Input Threshold Difference between the two Inputs ±100 — — mV
IIN Input Current Power On or Power Off — — ±10 µA
VOH Output High Voltage for VOP or VOM RT = 100 Ω — 1.425 1.60 V
VOL Output Low Voltage for VOP or VOM RT = 100 Ω 0.9 1.075 — V
VOD Output Voltage Differential (VOP - VOM), RT = 100 Ω 250 350 450 mV
Change in VOD Between High and
VOD — — — 50 mV
Low
VOCM Output Common Mode Voltage (VOP + VOM)/2, RT = 100 Ω 1.125 1.25 1.375 V
VOCM Change in VOCM, VOCM(MAX) - VOCM(MIN) — — — 50 mV
VOD = 0 V Driver outputs shorted to
ISAB Output Short Circuit Current — — 12 mA
each other
VOS Change in VOS between H and L — — — 50 mV

110 FPGA-DS-02049-2.1
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Data Sheet

Notes:
1. LVDS input or output are supported in Bank 3, Bank 4, and Bank 5. LVDS input uses V CCAUX on the differential input comparator,
and can be located in any VCCIO voltage bank. LVDS output uses VCCIO on the differential output driver, and can only be located in
bank with VCCIO = 1.8 V.
2. VICM is depending on VID, input differential voltage, so the voltage on pin cannot exceed V INP/INN(min/max) requirements. VICM(min) =
VINP/INN(min) + ½ VID, VICM(max) = VINP/INN(max) – ½ VID. Values in the table is based on minimum VID of +/- 100 mV.

4.12.2. LVDS25E (Output Only)

Three sides of the CrossLink-NX devices, Top, Left and Right, support LVDS25 outputs with emulated complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 4.2 is
one possible solution for point-to-point signals.
Table 4.20. LVDS25E DC Conditions
Parameter Description Typical Unit
VCCIO Output Driver Supply (±5%) 2.50 V
ZOUT Driver Impedance 20 Ω
RS Driver Series Resistor (±1%) 158 Ω
RP Driver Parallel Resistor (±1%) 140 Ω
RT Receiver Termination (±1%) 100 Ω
VOH Output High Voltage 1.43 V
VOL Output Low Voltage 1.07 V
VOD Output Differential Voltage 0.35 V
VCM Output Common Mode Voltage 1.25 V
ZBACK Back Impedance 100.5 Ω
IDC DC Output Current 6.03 mA

VCCIO = 2.5 V (± 5%)

RS = 158
(± 1%)
8 mA
LVCMOS25

RP = 140 RT = 100 +
VCCIO = 2.5 V (± 5%) -
RS = 158 (± 1%) (± 1%)
(± 1%)

8 mA
LVCMOS25
Transmission line, Zo = 100 differential

ON-chip OFF-chip OFF-chip ON-chip

Figure 4.2. LVDS25E Output Termination Example

4.12.3. SubLVDS (Input Only)

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Data Sheet

Table 4.21. SubLVDS Input DC Electrical Characteristics

Parameter Description Test Conditions Min Typ Max Unit
VID Input Differential Threshold Voltage Over VICM range 70 150 200 mV
VICM Input Common Mode Voltage Half the sum of the two Inputs 0.4 0.9 1.4 V

Sub-LVDS Driver PCB Traces, Connectors or Cables

Z0 = 50

+ +
RT = 100
100 differential ± 1%*

– –
Z0 = 50

Off-chip On-chip

Figure 4.3. SubLVDS Input Interface

4.12.4. SubLVDSE/SubLVDSEH (Output Only)

SubLVDS output uses a pair of LVCMOS18 drivers with True and Complement outputs. The VCCIO of the bank used for
subLVDSE or subLVDSEH needs to be powered by 1.8 V. SubLVDSE is for Bank 0, Bank 1, Bank 2, Bank 5, and Bank 6;
and subLVDSEH is for Bank 3, Bank 4, and Bank 5.
Performance of the subLVDSE/subLVDSEH driver is limited to the performance of LVCMOS18.
Table 4.22. SubLVDS Output DC Electrical Characteristics
Parameter Description Test Conditions Min Typ Max Unit
VOD Output Differential Voltage Swing — — 150 — mV
VOCM Output Common Mode Voltage Half the sum of the two Outputs — 0.9 — V

112 FPGA-DS-02049-2.1
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Data Sheet

VCCIO = +1.8 V PCB Traces, Connectors or Cables

Z0 = 50
Rs = 267 ±1%
+ +
SubLVDS Output
Rp = 121 ±1% 100 diff erential RT = 100 ±1% Sub-LVDS Recev ier
SubLVDSE
SubLVDSEH
– –
Rs = 267 ±1%
Z0 = 50

On-chip Off-chip On-chip Off-chip

Figure 4.4. SubLVDS Output Interface

4.12.5. SLVS
Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13
(SLVS-400) standard. This standard evolved from the traditional LVDS standard with smaller voltage swings and a lower
common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power.
The CrossLink-NX devices receive SLVS differential input with the LVDS input buffer. This LVDS input buffer is design to
cover wide input common mode range that can meet the SLVS input standard specified by the JEDEC standard.
Table 4.23. SLVS Input DC Characteristics
Parameter Description Test Conditions Min Typ Max Unit
VID Input Differential Threshold Voltage Over VICM range 70 — — mV
VICM Input Common Mode Voltage Half the sum of the two Inputs 70 200 330 mV

The SLVS output on CrossLink-NX is supported with the LVDS drivers found in Bank 3, Bank 4, and Bank 5. The LVDS
driver on CrossLink-NX is a current controlled driver. It can be configured as LVDS driver, or configured with the 100 Ω
differential termination with center-tap set to VOCM at 200 mV. This means the differential output driver can be placed
into bank with VCCIO = 1.2 V, 1.5 V, or 1.8 V, even if it is powered by VCCIO.
Table 4.24. SLVS Output DC Characteristics
Parameter Description Test Conditions Min Typ Max Unit
1.2,
VCCIO Bank VCCIO — –5% 1.5, + 5% V
1.8
VOD Output Differential Voltage Swing — 140 200 270 mV
VOCM Output Common Mode Voltage Half the sum of the two Outputs 150 200 250 mV
ZOS Single-Ended Output Impedance — 37.5 50 80 Ω

FPGA-DS-02049-2.1 113
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Data Sheet

Figure 4.5. SLVS Interface

4.12.6. Soft MIPI D-PHY

When Soft D-PHY is implemented inside the FPGA logic, the I/O interface needs to use sysI/O buffers to connect to
external D-PHY pins.
The CrossLink-NX sysI/O provides support for SLVS, as described in SLVS section, plus the LVCMOS12 input / output
buffers together to support the High Speed (HS) and Low Power (LP) mode as defined in MIPI Alliance Specification for
D-PHY.
To support MIPI D-PHY with SLVS (LVDS) and LVCMOS12, the bank VCCIO cannot be set to 1.5 V or 1.8 V. It must connect
to 1.2 V or 1.1 V.
All other DC parameters are the same as listed in SLVS section. DC parameters for the LP driver and receiver are the
same as listed in LVCMOS12.

114 FPGA-DS-02049-2.1
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Data Sheet

LVCMOS12
LP Data_P

LPenable
HSenable MIPI Receiver

100 Diff
+ +
HS Data Z0=50
- -
SLVS

LPenable

LP Data_N
LVCMOS12

MIPI_LP_RX
On-Chip
RXLP_P

MIPI Divider

+ +
HS Data Z0=50
- -
LVDS

MIPI_LP_RX

RXLP_N

Figure 4.6. MIPI Interface

Table 4.25. Soft D-PHY Input Timing and Levels

FPGA-DS-02049-2.1 115
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Data Sheet

Symbol Description Conditions Min Typ Max Unit

TMIN-RX Minimum Pulse Width Response — 20 — — ns
VINT Peak Interference Amplitude — — — 200 mV
fINT Interference Frequency — 450 — — MHz
Notes:
1. This is peak amplitude of sine wave modulated to the receiver inputs.
2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs.
3. Exclude any static ground shift of 50 mV.
4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage.

Table 4.26. Soft D-PHY Output Timing and Levels

Symbol Description Conditions Min Typ Max Unit
High Speed (Differential) Output DC Specifications
VCMTX Common-mode Voltage in High Speed Mode — 135 200 250 mV
VCMTX Mismatch Between Differential HIGH —
|ΔVCMTX(1,0)| — — 15 mV
and LOW
|D-PHY-P – D-PHY-
|VOD| Output Differential Voltage 100 200 270 mV
N|
VOD Mismatch Between Differential HIGH and —
|ΔVOD| — — 50 mV
LOW
VOHHS Single-Ended Output HIGH Voltage — — — 385 mV
ZOS Single Ended Output Impedance — 37.5 50 80 Ω
ΔZOS ZOS mismatch — — — 20 %
High Speed (Differential) Output AC Specifications
ΔVCMTX(LF) Common-Mode Variation, 50 MHz–450 MHz — — — 30 mVRMS
ΔVCMTX(HF) Common-Mode Variation, above 450 MHz — — — 17 mVRMS
Output 20%–80% Rise Time 0.08 Gbps ≤ tR ≤ 1.00
tR — — 0.35 UI
Output 80%–20% Fall Time Gbps
0.08 Gbps ≤ tF ≤ 1.00
tF Output Data Valid After CLK Output — — 0.27 UI
Gbps
Low Power (Single-Ended) Output DC Specifications
VOH Low Power Mode Output HIGH Voltage 0.08 Gbps – 1.5 Gbps 1.07 1.2 1.3 V
VOL Low Power Mode Input LOW Voltage — –50 — 50 mV
ZOLP Output Impedance in Low Power Mode — 110 — — Ω
Low Power (Single-Ended) Output AC Specifications
tRLP 15%–85% Rise Time — — — 25 ns
tFLP 85%–15% Fall Time — — — 25 ns
tREOT HS – LP Mode Rise and Fall Time, 30%–85% — — — 35 ns

116 FPGA-DS-02049-2.1
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Data Sheet

Symbol Description Conditions Min Typ Max Unit

First LP XOR Clock
Pulse after STOP
40 — — ns
TLP-PULSE-TX Pulse Width of the LP Exclusive-OR Clock State or Last Pulse
before STOP State
All Other Pulses 20 — — ns
TLP-PER-TX Period of the LP Exclusive-OR Clock — 90 — — ns
CLOAD Load Capacitance — 0 — 70 pF

Table 4.27. Soft D-PHY Clock Signal Specification

Symbol Description Conditions Min Typ Max Unit
Clock Signal Specification
UI —
UIINST — — 12.5 ns
Instantaneous
— –10% — 10% UI
UI Variation ∆UI
— –5% — 5% UI

Table 4.28. Soft D-PHY Data-Clock Timing Specifications

Symbol Description Conditions Min Typ Max Unit
Data-Clock Timing Specifications
0.08 Gbps ≤ TSKEW[TX]
TSKEW[TX] Data to Clock Skew -0.15 — 0.158 UIINST
≤ 1.00 Gbps
0.08 Gbps ≤ TSKEW[TLIS]
TSKEW[TLIS] Data to Clock Skew -0.20 — 0.20 UIINST
≤ 1.00 Gbps
0.08 Gbps ≤ TSETUP[RX]
TSETUP[RX] Input Data Setup Before CLK 0.173 — — UI
≤ 1.00 Gbps
0.08 Gbps ≤ THOLD[RX]
THOLD[RX] Input Data Hold After CLK 0.195 — — UI
≤ 1.00 Gbps

4.12.7. Differential HSTL15D (Output Only)

Differential HSTL outputs are implemented as a pair of complementary single-ended HSTL outputs.

4.12.8. Differential SSTL135D, SSTL15D (Output Only)

4.12.9. Differential HSUL12D (Output Only)

4.12.10. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only)

Differential LVCMOS and LVTTL outputs are implemented as a pair of complementary single-ended outputs. All
allowable single-ended output drive strengths are supported.

FPGA-DS-02049-2.1 117
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Data Sheet

4.13. Maximum sysI/O Buffer Speed

Table 4.29. Maximum I/O Buffer Speed1, 2, 3, 4, 7
Buffer Description Banks Max Unit
Maximum sysI/O Input Frequency
Single-Ended
LVCMOS33 LVCMOS33, VCCIO = 3.3 V 0, 1, 2, 6, 7 200 MHz
LVTTL33 LVTTL33, VCCIO = 3.3 V 0, 1, 2, 6, 7 200 MHz
LVCMOS25 LVCMOS25, VCCIO = 2.5 V 0, 1, 2, 6, 7 200 MHz
LVCMOS18 5 LVCMOS18, VCCIO = 1.8 V 0, 1, 2, 6, 7 200 MHz
LVCMOS18H LVCMOS18, VCCIO = 1.8 V 3, 4, 5 200 MHz
LVCMOS15 5 LVCMOS15, VCCIO = 1.5 V 0, 1, 2, 6, 7 100 MHz
LVCMOS15H 5 LVCMOS15, VCCIO = 1.5 V 3, 4, 5 150 MHz
LVCMOS12 5 LVCMOS12, VCCIO = 1.2 V 0, 1, 2, 6, 7 50 MHz
LVCMOS12H 5 LVCMOS12, VCCIO = 1.2 V 3, 4, 5 100 MHz
LVCMOS10 5 LVCMOS 1.0, VCCIO = 1.2 V 0, 1, 2, 6, 7 50 MHz
LVCMOS10H 5 LVCMOS 1.0, VCCIO = 1.0 V 3, 4, 5 50 MHz
LVCMOS10R LVCMOS 1.0, VCCIO independent 3, 4, 5 50 MHz
SSTL15_I, SSTL15_II SSTL_15, VCCIO = 1.5 V 3, 4, 5 1066 Mbps
SSTL135_I, SSTL135_II SSTL_135, VCCIO = 1.35 V 3, 4, 5 1066 Mbps
HSUL12 HSUL_12, VCCIO = 1.2 V 3, 4, 5 1066 Mbps

HSTL15 HSTL15, VCCIO = 1.5 V 3, 4, 5 250 Mbps

subLVDS subLVDS, VCCIO independent QFN72, 3, 4, 5 1250 Mbps

caBGA256, csBGA289, and caBGA400

subLVDS, VCCIO independent csfBGA121 3, 4, 5 1500 Mbps

SLVS SLVS similar to MIPI HS, VCCIO independent 3, 4, 5 1250 Mbps

QFN72, caBGA256, csBGA289, caBGA400

SLVS similar to MIPI HS, VCCIO independent 3, 4, 5 1500 Mbps

csfBGA121

MIPI D-PHY (HS Mode) MIPI, High Speed Mode, VCCIO = 1.2 V 3, 4, 5 1250 Mbps
QFN72

MIPI, High Speed Mode, VCCIO = 1.2 V 3, 4, 5 1500 Mbps

csfBGA121, caBGA256, csBGA289, caBGA400
SSTL15D Differential SSTL15, VCCIO independent 3, 4, 5 1066 Mbps
SSTL135D Differential SSTL135, VCCIO independent 3, 4, 5 1066 Mbps

HUSL12D Differential HSUL12, VCCIO independent 3, 4, 5 1066 Mbps

HSTL15D Differential HSTL15, VCCIO independent 3, 4, 5 250 Mbps

118 FPGA-DS-02049-2.1
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Data Sheet

Buffer Description Banks Max Unit

Maximum sysI/O Output Frequency
Single-Ended
LVCMOS33 (all drive strengths) LVCMOS33, VCCIO = 3.3 V 0, 1, 2, 6, 7 200 MHz
LVCMOS33 (RS50) LVCMOS33, VCCIO = 3.3 V, RSERIES = 50 Ω 0, 1, 2, 6, 7 200 MHz
LVTTL33 (all drive strengths) LVTTL33, VCCIO = 3.3 V 0, 1, 2, 6, 7 200 MHz
LVTTL33 (RS50) LVTTL33, VCCIO = 3.3 V, RSERIES = 50 Ω 0, 1, 2, 6, 7 200 MHz
LVCMOS25 (all drive strengths) LVCMOS25, VCCIO = 2.5 V 0, 1, 2, 6, 7 200 MHz
LVCMOS25 (RS50) LVCMOS25, VCCIO = 2.5 V, RSERIES = 50 Ω 0, 1, 2, 6, 7 200 MHz
LVCMOS18 (all drive strengths) LVCMOS18, VCCIO = 1.8 V 0, 1, 2, 6, 7 200 MHz
LVCMOS18 (RS50) LVCMOS18, VCCIO = 1.8 V, RSERIES = 50 Ω 0, 1, 2, 6, 7 200 MHz
LVCMOS18H (all drive strengths) LVCMOS18, VCCIO = 1.8 V 3, 4, 5 200 MHz
LVCMOS18H (RS50) LVCMOS18, VCCIO = 1.8 V, RSERIES = 50 Ω 3, 4, 5 200 MHz
LVCMOS15 (all drive strengths) LVCMOS15, VCCIO = 1.5 V 0, 1, 2, 6, 7 100 MHz
LVCMOS15H (all drive strengths) LVCMOS15, VCCIO = 1.5 V 3, 4, 5 150 MHz
LVCMOS12 (all drive strengths) LVCMOS12, VCCIO = 1.2 V 0, 1, 2, 6, 7 50 MHz
LVCMOS12H (all drive strengths) LVCMOS12, VCCIO = 1.2 V 3, 4, 5 100 MHz
LVCMOS10H (all drive strengths) LVCMOS12, VCCIO = 1.2 V 3, 4, 5 50 MHz
SSTL15_I, SSTL15_II SSTL_15, VCCIO = 1.5 V 3, 4, 5 1066 Mbps
SSTL135_I, SSTL135_II SSTL_135, VCCIO = 1.35 V 3, 4, 5 1066 Mbps
HSUL12 (all drive strengths) HSUL_12, VCCIO = 1.2 V 3, 4, 5 1066 Mbps
HSTL15 HSTL15, VCCIO = 1.5 V 3, 4, 5 250 Mbps
MIPI D-PHY (LP Mode) MIPI, Low Power Mode, VCCIO = 1.2 V 3, 4, 5 10 Mbps
Differential8
LVDS LVDS, VCCIO = 1.8 V QFN72, caBGA256, 3, 4, 5 1250
Mbps
csBGA289, and caBGA400
LVDS, VCCIO = 1.8 V csfBGA121 3, 4, 5 1500 Mbps
LVDS25E6 LVDS25, Emulated, VCCIO = 2.5 V 0, 1, 2, 6, 7 400 Mbps
SubLVDSE6 subLVDS, Emulated, VCCIO = 1.8 V 0, 1, 2, 6, 7 400 Mbps
SubLVDSEH6 subLVDS, Emulated, VCCIO = 1.8 V 3, 4, 5 800 Mbps
SLVS
SLVS similar to MIPI, VCCIO = 1.2 V
3, 4, 5 1250 Mbps
QFN72, caBGA256, csBGA289, caBGA400

SLVS similar to MIPI, VCCIO = 1.2 V

3, 4, 5 1500 Mbps
csfBGA121
MIPI D-PHY (HS Mode)
MIPI, High Speed Mode, VCCIO = 1.2 V
3, 4, 5 1250 Mbps
QFN72

MIPI, High Speed Mode, VCCIO = 1.2 V

3, 4, 5 1500 Mbps
csfBGA121, caBGA256, csBGA289, caBGA400
SSTL15D Differential SSTL15, VCCIO = 1.5 V 3, 4, 5 1066 Mbps
SSTL135D Differential SSTL135, VCCIO = 1.35 V 3, 4, 5 1066 Mbps
HUSL12D Differential HSUL12, VCCIO = 1.2 V 3, 4, 5 1066 Mbps
HSTL15D Differential HSTL15, VCCIO = 1.5 V 3, 4, 5 250 Mbps
Notes:
1. Maximum I/O speed is the maximum switching rate of the I/O operating within the guidelines of the defining standard. The
actual interface speed performance using the I/O also depends on other factors, such as internal and external timing.
2. These numbers are characterized but not test on every device.

FPGA-DS-02049-2.1 119
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Data Sheet

3. Performance is specified in MHz, as defined in clock rate when the sysI/O is used as pin. For data rate performance, this can be
converted to Mbps, which equals to 2 times the clock rate.
4. LVCMOS and LVTTL are measured with load specified in Table 4.50.
5. These LVCMOS inputs can be placed in different VCCIO voltage. Performance may vary. Please refer to Lattice Design Software
6. These emulated outputs performance is based on externally properly terminated as described in LVDS25E (Output Only) and
SubLVDSE/SubLVDSEH (Output Only).
7. All speeds are measured with fast slew.
8. For maximum differential I/O performance only Differential I/O should be placed in the bottom I/O banks. If this is not possible,
the following will impact on maximum performance:
a. If Fast Slew Rate LVCMOS I/O are used, they should be limited to no more than nine I/O (adjacent), four I/O (same bank),
55 I/O (left/right banks) to keep degradation below 50%.
b. If non-Differential I/O (SLOW SLEW) are placed on the bottom but not within the same bank as differential I/O, then the
maximum Differential performance is degraded to 70% of original when 21 aggressors are toggling.
c. If non-Differential I/O (SLOW SLEW) are placed within the same bank as Differential I/O then the maximum performance is
degraded to 50% of original when 16 aggressors are toggling.
d. No performance impact if MIPI LP and MIPI HS are in the same bank.
e. If Differential RX/TX I/O are both placed within the same bank then the maximum performance is degraded to 90%.
f. For DDR3/3L, LPDDR2/3 separate DQ/DQS groups from Address/Commands/CLK groups into separate banks.

4.14. Typical Building Block Function Performance

These building block functions can be generated using Lattice Design Software Tool. Exact performance may vary with
the device and the design software tool version. The design software tool uses internal parameters that have been
characterized but are not tested on every device.
Table 4.30. Pin-to-Pin Performance
Typ. @ VCC =
Function Unit
1.0 V
16-bit Decoder (I/O configured with LVCMOS18, Left and Right Banks) 5.5 ns
16-bit Decoder (I/O configured with HSTL15_I, Bottom Banks) 5.1 ns
16:1 Mux (I/O configured with LVCMOS18, Left and Right Banks) 6 ns
16:1 Mux (I/O configured with HSTL15_I, Bottom Banks) 6.1 ns
Note: These functions are generated using Lattice Radiant Design Software tool. Exact performance may vary with the device and
the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested
on every device.

Table 4.31. Register-to-Register Performance

120 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Typ. @ VCC =
Function Unit
1.0 V
Distributed Memory Functions
16 × 4 Single Port RAM (One PFU) 5002 MHz
16 × 2 Pseudo-Dual Port RAM (One PFU) 5002 MHz
16 × 4 Pseudo-Dual Port (Two PFUs) 5002 MHz
DSP Functions
9 × 9 Multiplier with Input Output Registers 340 MHz
18 × 18 Multiplier with Input/Output Registers 260 MHz
36 × 36 Multiplier with Input/Output Registers 184 MHz
MAC 18 × 18 with Input/Output Registers 189 MHz
MAC 18 × 18 with Input/Pipelined/Output Registers 260 MHz
MAC 36 × 36 with Input/Output Registers 111 MHz
MAC 36 × 36 with Input/Pipelined/Output Registers 145 MHz
Notes:
1. The Clock port is configured with LVDS I/O type. Performance Grade: 9_High-Performance_1.0V.
2. Limited by the Minimum Pulse Width of the component
3. These functions are generated using Lattice Radiant Design software tool. Exact performance may vary with the device and the
design software tool version. The design software tool uses internal parameters that have been characterized but are not
tested on every device.
4. For the Pipelined designs, the number of pipeline stages used are 2.

4.15. LMMI
Table 4.32 summarizes the performance of the LMMI interface with supported IPs. Additional timing requirement and
constraint can be identified through the Lattice Radiance design tools.
Table 4.32. LMMI FMAX Summary
IP FMAX (MHz)
CDR0 73
CDR1 70
DPHY0 67
DPHY1 55
CRE 54
I2C 38
PCIe 57
PLL_ULC 59
PLL_LLC 55
PLL_LRC 37

4.16. Derating Timing Tables

FPGA-DS-02049-2.1 121
CrossLink-NX Family
Data Sheet

4.17. External Switching Characteristics

Over recommended commercial operating conditions.
Table 4.33. External Switching Characteristics (VCC = 1.0 V)
–7 Auto
Parameter Description Unit
Min Max
Clocks
Primary Clock
fMAX_PRI Frequency for Primary Clock — 276 MHz
tW_PRI Clock Pulse Width for Primary Clock 1.59 — ns
tSKEW_PRI6 Primary Clock Skew Within a Device — 653 ps
Edge Clock
fMAX_EDGE Frequency for Edge Clock Tree — 551.7 MHz
tW_EDGE Clock Pulse Width for Edge Clock 0.761 — ns
tSKEW_EDGE6 Edge Clock Skew Within a Device — 174 ps
Generic SDR Input
General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL
tCO Clock to Output – PIO Output Register — 7.91 ns
tSU Clock to Data Setup – PIO Input Register 0 — ns
tH Clock to Data Hold – PIO Input Register 3.95 — ns
tSU_DEL Clock to Data Setup – PIO Input Register with Data Input Delay 1.86 — ns
tH_DEL Clock to Data Hold – PIO Input Register with Data Input Delay 0.26 — ns
General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL
tCOPLL Clock to Output – PIO Output Register — 5.57 ns
tSUPLL Clock to Data Setup – PIO Input Register 1.31 — ns
tHPLL Clock to Data Hold - PIO Input Register 1.44 — ns
tSU_DELPLL Clock to Data Setup - PIO Input Register with Data Input Delay 4.99 — ns
tH_DELPLL Clock to Data Hold - PIO Input Register with Data Input Delay 0 — ns
Generic DDR Input/Output
Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input –
Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 – Figure 4.7 and Figure 4.9
0.917 — ns
tSU_GDDR1 Input Data Setup Before CLK
0.275 — UI
0.917 — ns
tHO_GDDR1 Input Data Hold After CLK
0.275 — UI
1.008 — ns
tDVB_GDDR1 Output Data Valid After CLK Output
–0.659 — ns + 1/2 UI
1.008 — ns
tDQVA_GDDR1 Output Data Valid After CLK Output
–0.659 — ns + 1/2 UI
fDATA_GDDRX1 Input/Output Data Rate — 300 Mbps
fMAX_GDDRX1 Frequency of PCLK — 150 MHz
½ UI Half of Data Bit Time, or 90 degree 1.667 — ns
Output TX to Input RX Margin per Edge 0.091 — ns
Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input –
Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 – Figure 4.8 and Figure 4.10
— -0.917 ns + 1/2 UI
tDVA_GDDR1 Input Data Valid After CLK — 0.75 ns
— 0.225 UI

122 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

–7 Auto
Parameter Description Unit
Min Max
0.917 — ns + 1/2 UI
tDVE_GDDR1 Input Data Hold After CLK 2.583 — ns
0.775 — UI
tDIA_GDDR1 Output Data Invalid After CLK Output — 0.659 ns
tDIB_GDDR1 Output Data Invalid Before CLK Output — 0.659 ns

fDATA_GDDRX1 Input/Output Data Rate — 300 Mbps

fMAX_GDDRX1 Frequency for PCLK — 150 MHz

½ UI Half of Data Bit Time, or 90 degree 1.667 — ns

Output TX to Input RX Margin per Edge 0.091 — ns

Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input –
Bank 3, Bank 4, and Bank 5 – Figure 4.7 and Figure 4.9
0.917 — ns
tSU_GDDR1 Input Data Setup Before CLK
0.275 — UI
tHO_GDDR1 Input Data Hold After CLK 0.917 — ns
1.227 — ns
tDVB_GDDR1 Output Data Valid After CLK Output
–0.439 — ns + 1/2 UI
1.227 — ns
tDQVA_GDDR1 Output Data Valid After CLK Output
–0.439 — ns + 1/2 UI
fDATA_GDDRX1 Input/Output Data Rate — 300 Mbps

fMAX_GDDRX1 Frequency of PCLK — 150 MHz

½ UI Half of Data Bit Time, or 90 degree 1.667 — ns
Output TX to Input RX Margin per Edge 0.311 — ns
Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input –
Bank 3, Bank 4, and Bank 5 – Figure 4.8 and Figure 4.10
— -0.9167 ns + 1/2 UI
tDVA_GDDR1 Input Data Valid After CLK — 0.75 ns
— 0.225 UI

0.9167 — ns + 1/2 UI
tDVE_GDDR1 Input Data Hold After CLK 2.5833 — ns
0.775 — UI
tDIA_GDDR1 Output Data Invalid After CLK Output — 0.439 ns

tDIB_GDDR1 Output Data Invalid Before CLK Output — 0.439 ns

fDATA_GDDRX1 Input/Output Data Rate — 300 Mbps

fMAX_GDDRX1 Frequency for PCLK — 150 MHz

½ UI Half of Data Bit Time, or 90 degree 1.667 — ns

Output TX to Input RX Margin per Edge 0.311 — ns

FPGA-DS-02049-2.1 123
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Data Sheet

–7 Auto
Parameter Description Unit
Min Max
Generic DDRX2 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX2_RX/TX.ECLK.Centered) using PCLK Clock Input –
Figure 4.7 and Figure 4.9
0.270 — ns
tSU_GDDRX2 Data Setup before CLK Input
0.162 — UI
tHO_GDDRX2 Data Hold after CLK Input 0.270 — ns
0.658 — ns
tDVB_GDDRX2 Output Data Valid Before CLK Output
–0.176 — ns + 1/2 UI
0.658 — ns
tDQVA_GDDRX2 Output Data Valid After CLK Output
–0.176 — ns + 1/2 UI
fDATA_GDDRX2 Input/Output Data Rate — 600 Mbps
fMAX_GDDRX2 Frequency for ECLK — 300 MHz
½ UI Half of Data Bit Time, or 90 degree 0.833 — ns
fPCLK PCLK frequency — 209.97 MHz
Output TX to Input RX Margin per Edge 0.408 — ns
Generic DDRX2 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX2_RX/TX.ECLK.Aligned) using PCLK Clock Input –
Figure 4.8 and Figure 4.10
— –0.458 ns + 1/2 UI
tDVA_GDDRX2 Input Data Valid After CLK — 0.375 ns
— 0.225 UI
0.458 — ns + 1/2 UI
tDVE_GDDRX2 Input Data Hold After CLK 1.292 — ns
0.775 — UI
tDIA_GDDRX2 Output Data Invalid After CLK Output — 0.176 ns
tDIB_GDDRX2 Output Data Invalid Before CLK Output — 0.176 ns
fDATA_GDDRX2 Input/Output Data Rate — 600 Mbps
fMAX_GDDRX2 Frequency for ECLK — 300 MHz
½ UI Half of Data Bit Time, or 90 degree 0.589 — ns
fPCLK PCLK frequency — 209.97 MHz
Output TX to Input RX Margin per Edge 0.091 — ns
Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input –
Figure 4.7 and Figure 4.9
0.220 — ns
tSU_GDDRX4 Input Data Set-Up Before CLK
0.220 — UI
tHO_GDDRX4 Input Data Hold After CLK 0.220 — ns
0.324 — ns
tDVB_GDDRX4 Output Data Valid Before CLK Output
–0.176 — ns + 1/2UI
0.324 — ns
tDQVA_GDDRX4 Output Data Valid After CLK Output
–0.176 — ns + 1/2UI
fDATA_GDDRX4 Input/Output Data Rate — 1000 Mbps
fMAX_GDDRX4 Frequency for ECLK — 500 MHz
½ UI Half of Data Bit Time, or 90 degree 0.5 — ns
fPCLK PCLK frequency — 125 MHz
Output TX to Input RX Margin per Edge 0.124 — ns
Generic DDRX4 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX4_RX/TX.ECLK.Aligned) using PCLK Clock Input, Left
and Right sides Only – Figure 4.8 and Figure 4.10
— –0.275 ns + 1/2 UI
tDVA_GDDRX4 Input Data Valid After CLK — 0.225 ns
— 0.225 UI

124 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

–7 Auto
Parameter Description Unit
Min Max
0.275 — ns + 1/2 UI
tDVE_GDDRX4 Input Data Hold After CLK 0.775 — ns
0.775 — UI
—
tDIA_GDDRX4 Output Data Invalid After CLK Output 0.176 ns

—
tDIB_GDDRX4 Output Data Invalid Before CLK Output 0.176 ns

fDATA_GDDRX4 Input/Output Data Rate — 1000 Mbps

fMAX_GDDRX4 Frequency for ECLK — 500 MHz

½ UI Half of Data Bit Time, or 90 degree 0.5 — ns

fPCLK PCLK frequency — 125 MHz

Output TX to Input RX Margin per Edge 0.049 — ns
Generic DDRX5 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX5_RX/TX.ECLK.Centered) using PCLK Clock Input –
Figure 4.7 and Figure 4.9
0.22 — ns
tSU_GDDRX5 Input Data Set-Up Before CLK
0.22 — UI
tHO_GDDRX5 Input Data Hold After CLK 0.22 — ns
tWINDOW_GDDRX5C Input Data Valid Window 0.44 — ns
0.324 — ns
tDVB_GDDRX5 Output Data Valid Before CLK Output
–0.176 — ns+1/2UI
0.324 — ns
tDQVA_GDDRX5 Output Data Valid After CLK Output
–0.176 — ns+1/2UI
fDATA_GDDRX5 Input/Output Data Rate — 1000 Mbps
fMAX_GDDRX5 Frequency for ECLK — 500 MHz
½ UI Half of Data Bit Time, or 90 degree 0.5 — ns
fPCLK PCLK frequency — 100 MHz
Output TX to Input RX Margin per Edge 0.124 — ns
Generic DDRX5 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX5_RX/TX.ECLK.Aligned) using PCLK Clock Input, Left
and Right sides Only – Figure 4.8 and Figure 4.10
— –0.275 ns + 1/2 UI
tDVA_GDDRX5 Input Data Valid After CLK — 0.225 ns
— 0.225 UI
0.275 — ns + 1/2 UI
tDVE_GDDRX5 Input Data Hold After CLK 0.775 — ns
0.775 — UI
tWINDOW_GDDRX5A Input Data Valid Window 0.55 — ns
tDIA_GDDRX5 Output Data Invalid After CLK Output — 0.176 ns
tDIB_GDDRX5 Output Data Invalid Before CLK Output — 0.176 ns
fDATA_GDDRX5 Input/Output Data Rate — 1000 Mbps
fMAX_GDDRX5 Frequency for ECLK — 500 MHz
½ UI Half of Data Bit Time, or 90 degree 0.5 — ns
fPCLK PCLK frequency — 100 MHz
Output TX to Input RX Margin per Edge 0.049 — ns

FPGA-DS-02049-2.1 125
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Data Sheet

–7 Auto
Parameter Description Unit
Min Max
Soft D-PHY DDRX4 Inputs/Outputs with Clock and Data Centered at Pin, using PCLK Clock Input
0.21 — ns
tSU_GDDRX4_MP Input Data Set-Up Before CLK
0.21 — UI
0.2 — ns
tHO_GDDRX4_MP Input Data Hold After CLK
0.2 — UI
0.3 — ns
tDVB_GDDRX4_MP Output Data Valid Before CLK Output
0.3 — UI
0.3 — ns
tDQVA_GDDRX4_MP Output Data Valid After CLK Output
0.3 — UI

csfBGA121 — 1000 Mbps

fDATA_GDDRX4_MP Input Data Bit Rate for MIPI PHY
caBGA256 — 1000 Mbps

½ UI Half of Data Bit Time, or 90 degree 0.5 — ns

fPCLK PCLK frequency — 125 MHz
Output TX to Input RX Margin per Edge 0.1 — ns
Video DDRX71 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) using PLL Clock Input – Figure 4.12 and
Figure 4.13
Input Valid Bit "i" switch from CLK Rising Edge ("i" = 0 to 6, 0 aligns with — 0.277 UI
tRPBi_DVA
CLK) — –0.278 ns+(1/2+i)×UI
Input Hold Bit "i" switch from CLK Rising Edge ("i" = 0 to 6, 0 aligns with 0.711 — UI
tRPBi_DVE
CLK) 0.263 — ns+(1/2+i)×UI
Data Output Valid Bit "i" switch from CLK Rising Edge ("i" = 0 to 6, 0 aligns
tTPBi_DOV — 0.187 ns+i×UI
with CLK)
Data Output Invalid Bit "i" switch from CLK Rising Edge ("i" = 0 to 6, 0 aligns
tTPBi_DOI -0.187 — ns+(i+ 1)×UI
with CLK)
tTPBi_skew_UI TX skew in UI — 0.150 UI
tB Serial Data Bit Time, = 1UI 1.247 — ns
fDATA_TX71 DDR71 Serial Data Rate — 802 Mbps
fMAX_TX71 DDR71 ECLK Frequency — 401 MHz
fCLKIN 7:1 Clock (PCLK) Frequency — 113.4 MHz
Output TX to Input RX Margin per Edge 0.187 — ns
Memory Interface
DDR3/DDR3L/LPDDR2 READ (DQ Input Data are Aligned to DQS) – Figure 4.8
tDVBDQ_DDR3
tDVBDQ_DDR3L Data Input Valid before DQS Input — –0.277 ns + 1/2 UI
tDVBDQ_LPDDR2
tDVADQ_DDR3
tDVADQ_DDR3L Data Input Valid after DQS Input 0.277 — ns + 1/2 UI
tDVADQ_LPDDR2
fDATA_DDR3
fDATA_DDR3L DDR Memory Data Rate — 904 Mb/s
fDATA_LPDDR2
fMAX_ECLK_DDR3
fMAX_ECLK_DDR3L DDR Memory ECLK Frequency — 452 MHz
fMAX_ECLK_LPDDR2
fMAX_SCLK_DDR3
fMAX_SCLK_DDR3L DDR Memory SCLK Frequency — 113 MHz
fMAX_SCLK_LPDDR2

126 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

–7 Auto
Parameter Description Unit
Min Max
DDR3/DDR3L/LPDDR2 WRITE (DQ Output Data are Centered to DQS) – Figure 4.11
tDQVBS_DDR3
tDQVBS_DDR3L Data Output Valid before DQS Output — –0.277 ns + 1/2 UI
tDQVBS_LPDDR2
tDQVAS_DDR3
tDQVAS_DDR3L Data Output Valid after DQS Output 0.277 — ns + 1/2 UI
tDQVAS_LPDDR2
fDATA_DDR3
fDATA_DDR3L DDR Memory Data Rate — 904 Mb/s
fDATA_LPDDR2
fMAX_ECLK_DDR3
fMAX_ECLK_DDR3L DDR Memory ECLK Frequency — 452 MHz
fMAX_ECLK_LPDDR2
fMAX_SCLK_DDR3
fMAX_SCLK_DDR3L DDR Memory SCLK Frequency — 113 MHz
fMAX_SCLK_LPDDR2
Notes:
1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Lattice Radiant
software.
2. General I/O timing numbers are based on LVCMOS 1.8, 8 mA, Fast Slew Rate, 0 pF load.
Generic DDR timing are numbers based on LVDS I/O.
DDR3 timing numbers are based on SSTL15.
LPDDR2 timing numbers are based on HSUL12.
3. Uses LVDS I/O standard for measurements.
4. Maximum clock frequencies are tested under best case conditions. System performance may vary depending on the user
environment.
5. All numbers are generated with the Lattice Radiant software.
6. This clock skew is not the internal clock network skew. The Nexus family devices have very low internal clock network skew that
can be approximated to 0 ps. These tSKEW values measured externally at system level includes additional skew added by the I/O,
wire bonding and package ball.

Rx CLK (in)

Rx DATA (in)

tSU tSU

tHD tHD

Figure 4.7. Receiver RX.CLK.Centered Waveforms

FPGA-DS-02049-2.1 127
CrossLink-NX Family
Data Sheet

½ UI
½ UI
1 UI
Rx CLK (in)
or DQS input

Rx DATA (in)
or DQS input

tDVA/tDVADQ
tDVA/tDVADQ
tDVE/tDVEDQ
tDVE/tDVEDQ

Figure 4.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms

1/2 UI 1/2 UI 1/2 UI 1/2 UI

Tx CLK (out)
or DQS Output

Tx DATA (out)
or DQ Output

tDVB/tDQVBS tDVB/tDQVBS

tDVA/tDQVA tDVA/tDQVAS

Figure 4.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms

1 UI
Tx CLK (out)

Tx DATA (out)

tDIB tDIB
tDIA tDIA

Figure 4.10. Transmit TX.CLK.Aligned Waveforms

128 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Receiver – Shown for one LVDS Channel

# of Bits
Data In
756 Mb/s
Clock In
108 MHz

Bit # Bit # Bit # Bit #

Transmitter – Shown for one LVDS Channel

# of Bits
Data Out
756 Mb/s

Clock Out
108 MHz

Bit # Bit # Bit # Bit #

Figure 4.11. DDRX71 Video Timing Waveforms

Bit 0 Bit 1 Bit i

1/2 UI 1/2 UI

CLK (in) 1 UI

DATA (in)

tSU_0
tHD_0
tSU_i
tHD_i

Figure 4.12. Receiver DDRX71_RX Waveforms

FPGA-DS-02049-2.1 129
CrossLink-NX Family
Data Sheet

Bit 0 Bit 1 Bit i

1 UI
CLK (out)

DATA (out)

tDIB_0
tDIA_0
tDIB_i

tDIA_i
Figure 4.13. Transmitter DDRX71_TX Waveforms

4.18. sysCLOCK PLL Timing (VCC = 1.0 V) – Automotive

Table 4.34. sysCLOCK PLL Timing (VCC = 1.0 V) – Automotive
Parameter Descriptions Conditions Min Typ. Max Units
fIN Input Clock Frequency (CLKI, CLKFB) — 18 — 500 MHz
fOUT Output Clock Frequency — 6.25 — 800 MHz
fVCO PLL VCO Frequency — 800 — 1600 MHz
Without Fractional-N
18 — 500 MHz
Enabled
fPFD Phase Detector Input Frequency
With Fractional-N
18 — 100 MHz
Enabled
AC Characteristics

tDT Output Clock Duty Cycle — 45 — 55 %

tPH4 Output Phase Accuracy — –5 — 5 %

fOUT ≥ 200 MHz — — 250 ps p-p
Output Clock Period Jitter
fOUT < 200 MHz — — 0.05 UIPP
fOUT ≥ 200 MHz — — 250 ps p-p
Output Clock Cycle-to-Cycle Jitter
fOUT < 200 MHz — — 0.05 UIPP
fPFD ≥ 200 MHz — — 250 ps p-p
60 MHz ≤ fPFD < 200 MHz — — 400 ps p-p
Output Clock Phase Jitter
30 MHz ≤ fPFD < 60 MHz — — 500 ps p-p
18 MHz ≤ fPFD < 30 MHz — — 725 ps p-p
tOPJIT1
fOUT ≥ 200 MHz — — 350 ps p-p
Output Clock Period Jitter (Fractional-N)
fOUT < 200 MHz — — 0.07 UIPP

fOUT ≥ 200 MHz — — 400 ps p-p

Output Clock Cycle-to-Cycle Jitter (Fractional-
N)
fOUT < 200 MHz — — 0.08 UIPP

130 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Parameter Descriptions Conditions Min Typ. Max Units

fBW 3 PLL Loop Bandwidth — 0.45 — 13 MHz
tLOCK2 PLL Lock-in Time — — — 10 ms
tUNLOCK PLL Unlock Time (from RESET goes HIGH) — — — 50 ns
fPFD ≥ 20 MHz — — 0.01 UIPP
tIPJIT Input Clock Period Jitter
fPFD < 20 MHz — — 500 ps p-p
tHI Input Clock High Time 90% to 90% 0.5 — — ns
tLO Input Clock Low Time 10% to 10% 0.5 — — ns
tRST RST/ Pulse Width — 1 — — ms
fSSC_MOD Spread Spectrum Clock Modulation Frequency — 20 — 200 kHz

Spread Spectrum Clock Modulation Amplitude

fSSC_MOD_AMP — 0.25 — 2.00 %
Range

Spread Spectrum Clock Modulation Amplitude

fSSC_MOD_STEP — — 0.25 — %
Step Size
Notes:
1. Jitter sample is taken over 10,000 samples for Period jitter, and 1,000 samples for Cycle-to-Cycle jitter of the primary PLL output
with clean reference clock with no additional I/O toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Result from Lattice Radiant software.
4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency.

4.19. Internal Oscillators Characteristics

Table 4.35. Internal Oscillators (VCC = 1.0 V)
Symbol Parameter Description Min Typ Max Unit
fCLKHF HFOSC CLKK Clock Frequency 418.5 450 481.5 MHz
fCLKLF LFOSC CLKK Clock Frequency 18.2 32 45.8 kHz
DCHCLKHF HFOSC Duty Cycle (Clock High Period) 43 50 57 %
DCHCLKLF LFOSC Duty Cycle (Clock High Period) 45 50 55 %

4.20. User I2C Characteristics

Table 4.36. User I2C Specifications (VCC = 1.0 V)
Parameter STD Mode FAST Mode FAST Mode Plus2
Symbol Units
Description Min Typ Max Min Typ Max Min Typ Max
SCL Clock
fscl — — 100 — — 400 — — 1000 kHz
Frequency
Optional delay
TDELAY1 — — 62 — — 62 — — 62 ns
through delay block
Notes:
1. Refer to the I2C Specification for timing requirements. User design should set constraints in Lattice Design Software to meet
this industrial I2C Specification.
2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I2C bus. Internal pull up may not be
sufficient to support the maximum speed.

FPGA-DS-02049-2.1 131
CrossLink-NX Family
Data Sheet

4.21. Analog-Digital Converter (ADC) Block Characteristics

Table 4.37. ADC Specifications3
Symbol Description Condition Min Typ Max Unit
ADC Internal Reference —
VREFINT_ADC 1.141 1.2 1.261 V
Voltage4
ADC External Reference —
VREFEXT_ADC 1.0 — 1.8 V
Voltage
NRES_ADC ADC Resolution — — 12 — bits
ENOBADC Effective Number of Bits — 9.9 11 — bits
Bipolar Mode, Internal VCM_ADC ― VCM_ADC +
VCM_ADC V
VREF VREFINT_ADC/4 VREFINT_ADC/4
Bipolar Mode, External VCM_ADC ― VCM_ADC +
VREFEXT_ADC V
VREF VREFEXT_ADC/4 VREFEXT_ADC/4
VSR_ADC ADC Input Range
Uni-polar Mode, Internal
0 — VREFINT_ADC V
VREF
Uni-polar Mode, External
0 — VREFEXT_ADC V
VREF
ADC Input Common Mode Internal VREF — VREFINT_ADC/2 — V
VCM_ADC Voltage (for fully
differential signals) External VREF — VREFEXT_ADC/2 — V
fCLK_ADC ADC Clock Frequency — — 25 50 MHz
@ Sampling Frequency
fINPUT_ADC ADC Input Frequency — — 500 kHz
1 Mbps
FSADC ADC Sampling Rate — — 1 — MS/s
NTRACK_ADC ADC Input Tracking Time — 4 — — cycles2
ADC Input Equivalent
RIN_ADC — — 116 — kΩ
Resistance
tCAL_ADC ADC Calibration Time — — — 6500 cycles2
Includes minimum
LOUTput_ADC ADC Conversion Time tracking time of four 25 — — cycles2
cycles
ADC Differential —
DNLADC –1 — 1 LSB
Nonlinearity
INLADC ADC Integral Nonlinearity — –21 — 2.21 LSB
ADC Spurious Free —
SFDRADC 65.8 77 — dBc
Dynamic Range
ADC Total Harmonic —
THDADC — –76 –66.4 dB
Distortion
SNRADC ADC Signal to Noise Ratio — 61.6 68 — dB
ADC Signal to Noise Plus —
SNDRADC 61.5 67 — dB
Distortion Ratio
ERRGAIN_ADC ADC Gain Error — –0.5 — 0.5 % FSADC
ERROFFSET_ADC ADC Offset Error — –2 — 2 LSB
ADC Input Equivalent
CIN_ADC — — 2 — pF
Capacitance
Notes:
1. Not tested; guaranteed by design.
2. ADC Sample Clock cycles. See ADC User Guide for Nexus Platform (FPGA-TN-02129) for more details.
3. ADC is available in Automotive –7 speed grade.
4. Internal voltage reference is only for internal testing purpose. It is not recommended for customer design. User should always
use the part with external reference voltage.

132 FPGA-DS-02049-2.1
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4.22. Comparator Block Characteristics

Table 4.38. Comparator Specifications
Symbol Description Min Typ Max Unit
fIN_COMP Comparator Input Frequency — — 10 MHz
VIN_COMP Comparator Input Voltage 0 — VCC_ADC18 V
VOFFSET_COMP Comparator Input Offset –34.3 — 36.44 mV

VHYST_COMP Comparator Input Hysteresis 10 — 31.62 mV

VLATENCY_COMP Comparator Latency — — 31.24 ns

4.23. Digital Temperature Readout Characteristics

Digital temperature Readout (DTR) is implemented in one of the channels of ADC1.
Table 4.39. DTR Specifications1, 2
Symbol Description Condition Min Typ Max Unit
DTR Detect Temperature — °C
DTRRANGE –40 — 125
Range
with external voltage
DTRACCURACY DTR Accuracy reference range of 1.0 V –16 ±6 16 °C

4.24. Hardened MIPI D-PHY Characteristics

Table 4.40. Hardened D-PHY Input Timing and Levels
Symbol Description Conditions Min Typ Max Unit
High Speed (Differential) Input DC Specifications
Common-mode Voltage in High Speed
VCMRX(DC) — 70 — 330 mV
Mode
0.08 Gbps ≤ VIDTH ≤ 1.5 Gbps 70 — — mV
VIDTH Differential Input HIGH Threshold
1.5 Gbps < VIDTH ≤ 2.5 Gbps 40 — — mV
0.08 Gbps ≤ VIDTL ≤ 1.5 Gbps — — –70 mV
VIDTL Differential Input LOW Threshold
1.5 Gbps < VIDTL ≤ 2.5 Gbps — — –40 mV
VIHHS Input HIGH Voltage (for HS mode) — — — 460 mV
VILHS Input LOW Voltage — –40 — — mV
Single-ended voltage for HS Termination
VTERM-EN — — — 450 mV
Enable4
ZID Differential Input Impedance — 80 100 125 Ω
High Speed (Differential) Input AC Specifications
0.08 Gbps ≤ ∆VCMRX(HF) ≤ 1.5
— — 100 mV
Gbps
ΔVCMRX(HF)1 Common-mode Interference (>450 MHz)
1.5 Gbps < ∆VCMRX(HF) ≤ 2.5
— — 50 mV
Gbps

FPGA-DS-02049-2.1 133
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Data Sheet

Symbol Description Conditions Min Typ Max Unit

0.08 Gbps ≤ ∆VCMRX(LF) ≤ 1.5
–50 — 50 mV
Common-mode Interference (50 MHz–450 Gbps
ΔVCMRX(LF) 2, 3
MHz) 1.5 Gbps < ∆VCMRX(LF) ≤ 2.5
–25 — 25 mV
Gbps

CCM Common-mode Termination — — — 60 pF

Low Power (Single-Ended) Input DC Specifications

VIH Low Power Mode Input HIGH Voltage — 780 — — mV
VIL Low Power Mode Input LOW Voltage — — — 540 mV
VIL-ULP Ultra Low Power Input LOW Voltage — — — 300 mV
VHYST Low Power Mode Input Hysteresis — 21 — — mV
℮SPIKE Input Pulse Rejection — — — 300 V∙ps
TMIN-RX Minimum Pulse Width Response — 20 — — ns
VINT Peak Interference Amplitude — — — 200 mV
fINT Interference Frequency — 450 — — MHz
Contention Detector (LP-CD) DC Specifications
VIHCD Contention Detect HIGH Voltage — 450 — — mV
VILCD Contention Detect LOW Voltage — — — 200 mV
Notes:
1. This is peak amplitude of sine wave modulated to the receiver inputs.
2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs.
3. Exclude any static ground shift of 50 mV.
4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage.

Table 4.41. Hardened D-PHY Output Timing and Levels

Symbol Description Conditions Min Typ Max Unit
High Speed (Differential) Output DC Specifications
VCMTX Common-mode Voltage in High Speed Mode — 130 200 250 mV
VCMTX Mismatch Between Differential HIGH
|ΔVCMTX(1,0)| — — — 7 mV
and LOW
|D-PHY-P – D-
|VOD| Output Differential Voltage 120 200 270 mV
PHY-N|
VOD Mismatch Between Differential HIGH and
|ΔVOD| — — — 14 mV
LOW
VOHHS Single-Ended Output HIGH Voltage — — — 375 mV
ZOS Single Ended Output Impedance — 35 50 75 Ω
ΔZOS ZOS mismatch — — — 20 %
High Speed (Differential) Output AC Specifications
ΔVCMTX(LF) Common-Mode Variation, 50 MHz – 450 MHz — — — 25 mVRMS
ΔVCMTX(HF) Common-Mode Variation, above 450 MHz — — — 15 mVRMS
0.08 Gbps ≤ tR ≤ 1
— — 0.35 UI
Gbps
1 Gbps < tR ≤ 1.5
— — 0.525 UI
Gbps
tR Output 20%–80% Rise Time
tR ≤ 1.5 Gbps 65 — — ps
1.5 Gbps < tR
— — 0.875 UI
≤ 2.5 Gbps
tR > 1.5 Gbps 50 — — ps

134 FPGA-DS-02049-2.1
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Data Sheet

Symbol Description Conditions Min Typ Max Unit

0.08 Gbps ≤ tF ≤ 1
— — 0.33 UI
Gbps
1 Gbps < tF ≤ 1.5
— — 0.495 UI
Gbps
tF Output 80%–20% Fall Time
tF ≤ 1.5 Gbps 80 — — ps
1.5 Gbps < tF
— — 0.825 UI
≤ 2.5 Gbps
tF > 1.5 Gbps 50 — — ps
Low Power (Single-Ended) Output DC Specifications
0.08 Gbps ≤ VOH ≤
0.75 — 1.5 V
VOH Low Power Mode Output HIGH Voltage 1.50 Gbps
VOH > 1.50 Gbps 0.75 — 1.5 V
VOL Low Power Mode Input LOW Voltage — –50 — 50 mV
ZOLP Output Impedance in Low Power Mode — 106 — — Ω
Low Power (Single-Ended) Output AC Specifications
tRLP 15%–85% Rise Time — — — 25 ns
tFLP 85%–15% Fall Time — — — 25 ns
tREOT HS – LP Mode Rise and Fall Time, 30%–85% — — — 35 ns
Firstt LP XOR
Clock Pulse after
STOP State or 40 — — ns
TLP-PULSE-TX Pulse Width of the LP Exclusive-OR Clock Last Pulse before
STOP State
All Other Pulses 20 — — ns
TLP-PER-TX Period of the LP Exclusive-OR Clock — 90 — — ns
Slew Rate @ CLOAD = 0 pF — — — 500 mV/ns
Slew Rate @ CLOAD = 5 pF — — — 300 mV/ns
Slew Rate @ CLOAD = 20 pF — — — 250 mV/ns
Slew Rate @ CLOAD = 70 pF — — — 250 mV/ns
Slew Rate @ CLOAD = 0 to 70 pF (Falling Edge — 7 — — mV/ns
Only) — 7 — — mV/ns
δV/δtSR Slew Rate @ CLOAD = 0 to 70 pF (Rising Edge — 7 — — mV/ns
Only) — 7 — — mV/ns
— 7 - 0.075 ×
(VO,INST - — — mV/ns
Slew Rate @ CLOAD = 0 to 70 pF (Rising Edge 700)
Only) — 7 - 0.0625 ×
(VO,INST - — — mV/ns
550)
CLOAD Load Capacitance — 0 — 70 pF

FPGA-DS-02049-2.1 135
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Table 4.42. Hardened D-PHY Pin Characteristic Specifications

Table 4.43. Hardened D-PHY Clock Signal Specification

Symbol Description Conditions Min Typ Max Unit
Clock Signal Specification
UI
UIINST — — — 12.5 ns
Instantaneous
— –10% — 10% UI
UI Variation ∆UI
— –5% — 5% UI

Table 4.44. Hardened D-PHY Data-Clock Timing Specifications

Symbol Description Conditions Min Typ Max Unit
Data-Clock Timing Specifications
0.08 Gbps ≤ TSKEW[TX]
–0.15 — 0.15 UIINST
≤ 1.00 Gbps
TSKEW[TX] Data to Clock Skew
1.00 Gbps < TSKEW[TX]
–0.20 — 0.20 UIINST
≤ 1.50 Gbps
0.08 Gbps ≤ TSETUP[RX]
0.247 — — UI
≤ 1.00 Gbps
TSETUP[RX] Input Data Setup Before CLK
1.00 Gbps < TSETUP[RX]
0.37 — — UI
≤ 1.50 Gbps
0.08 Gbps ≤ THOLD[RX]
0.2 — — UI
≤ 1.00 Gbps
THOLD[RX] Input Data Hold After CLK
1.00 Gbps < THOLD[RX]
0.3 — — UI
≤ 1.50 Gbps
FIN_DPHY Input frequency to Hardened D-PHY PLL — 24 200 MHz
TSKEW[TX]
Dynamic Data to Clock Skew (Tx) > 1.5 Gbps –0.15 — 0.15 UIINST
Dynamic
ISI Channel ISI > 1.5 Gbps — — 0.20 UIINST
TSETUP[RX] +
Dynamic Data to Clock Skew Window Rx
THOLD[RX] > 1.5 Gbps 0.57 — — UIINST
Tolerance
Dynamic

136 FPGA-DS-02049-2.1
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Data Sheet

4.25. Hardened PCIe Characteristics

4.25.1. PCIe (2.5 Gbps)
Table 4.45. PCIe (2.5 Gbps)
Symbol Description Condition Min. Typ. Max. Unit
Transmitter1
UI Unit Interval — 399.88 400 400.12 ps
BWTX Tx PLL bandwidth — 1.5 — 22 MHz
Differential p-p Tx voltage
VTX-DIFF-PP — 0.8 — 1.2 Vp-p
swing
Low power differential p-p Tx
VTX-DIFF-PP-LOW — 0.4 — 1.2 Vp-p
voltage swing
Tx de-emphasis level ratio at
VTX-DE-RATIO-3.5dB — 3 — 4 dB
3.5 dB
TTX-RISE-FALL Transmitter rise and fall time — 0.125 — — UI
Transmitter Eye, including all
TTX-EYE — 0.75 — — UI
jitter sources
Max. time between jitter
TTX-EYE-MEDIAN-to-MAX-
median and max deviation — — — 0.125 UI
JITTER
from the median
Tx Differential Return Loss, —
RLTX-DIFF 10 — — dB
including pkg and silicon
Tx Common Mode Return Loss,
RLTX-CM 50 MHz < freq < 2.5 GHz 6 — — dB
including pkg and silicon
ZTX-DIFF-DC DC differential Impedance — 80 — 120 Ω
Tx AC peak common mode mV,
VTX-CM-AC-P — — — 20
voltage, RMS RMS
Transmitter short-circuit
ITX-SHORT — — — 90 mA
current
Transmitter DC common-mode
VTX-DC-CM — 0 — 1.2 V
voltage
Electrical Idle Output peak
VTX-IDLE-DIFF-AC-p — — — 20 mV
voltage
Voltage change allowed during
VTX-RCV-DETECT — — — 600 mV
Receiver Detect
TTX-IDLE-MIN Min. time in Electrical Idle — 20 — — ns
Max. time from EI Order Set to
TTX-IDLE-SET-TO-IDLE — — — 8 ns
valid Electrical Idle
Max. time from Electrical Idle
TTX-IDLE-TO-DIFF-DATA — — — 8 ns
to valid differential output
500 ps
LTX-SKEW Lane-to-Lane output skew — — — ps
+ 2 UI
Receiver2
UI Unit Interval — 399.9 400 400.12 ps
Differential Rx peak-peak
VRX-DIFF-PP — 0.175 — 1.2 Vp-p
voltage
TRX-EYE3 Receiver eye opening time — 0.4 — — UI
Max time delta between
TRX-EYE-MEDIAN-to-MAX-
3 median and deviation from — — — 0.3 UI
JITTER
median
Receiver differential Return
RLRX-DIFF — 10 — — dB
Loss, package plus silicon

FPGA-DS-02049-2.1 137
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Data Sheet

Symbol Description Condition Min. Typ. Max. Unit

Receiver common mode Return
RLRX-CM — 6 — — dB
Loss, package plus silicon
Receiver DC single ended
ZRX-DC — 40 — 60 Ω
impedance
Receiver DC differential
ZRX-DIFF-DC — 80 — 120 Ω
impedance
Receiver DC single ended
ZRX-HIGH-IMP-DC impedance when powered — 200 — — kΩ
down
Rx AC peak common mode mV,
VRX-CM-AC-P3 — — — 150
voltage peak
VRX-IDLE-DET-DIFF-PP Electrical Idle Detect Threshold — 65 — 175 mVp-p
LRX-SKEW Receiver –lane-lane skew — — — 20 ps
Notes:
1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters.
2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters.
3. Spec compliant requirement

4.25.2. PCIe (5 Gbps)

Table 4.46. PCIe (5 Gbps)
Symbol Description Test Conditions Min Typ Max Unit
Transmit1
UI Unit Interval — 199.94 200 200.06 ps
Tx PLL bandwidth
BWTX-PKG-PLL1 — 8 — 16 MHz
corresponding to PKGTX-PLL1
Tx PLL bandwidth
BWTX-PKG-PLL2 — 5 — 16 MHz
corresponding to PKGTX-PLL2
Tx PLL Peaking
PKGTX-PLL1 — — — 3 dB
corresponding to PKGTX-PLL1
Tx PLL Peaking
PKGTX-PLL2 — — — 1 dB
corresponding to PKGTX-PLL2
Differential p-p Tx voltage
VTX-DIFF-PP — 0.8 — 1.2 V, p-p
swing
Low power differential p-p Tx
VTX-DIFF-PP-LOW — 0.4 — 1.2 V, p-p
voltage swing
Tx de-emphasis level ratio at
VTX-DE-RATIO-3.5dB — 3 — 4 dB
3.5 dB
Tx de-emphasis level ratio at
VTX-DE-RATIO-6dB — 5.5 — 6.5 dB
6 dB
TMIN-PULSE Instantaneous lone pulse width — 0.9 — — UI
TTX-RISE-FALL Transmitter rise and fall time — 0.15 — — UI
Transmitter Eye, including all
TTX-EYE — 0.75 — — UI
jitter sources
Tx deterministic jitter > 1.5
TTX-DJ — — — 0.15 UI
MHz
ps,
TTX-RJ Tx RMS jitter < 1.5 MHz — — — 3
RMS
TRF-MISMATCH Tx rise/fall time mismatch — — — 0.1 UI
Tx Differential Return Loss, 50 MHz < freq < 1.25 GHz 10 — — dB
RLTX-DIFF
including package and silicon 1.25 GHz < freq < 2.5 GHz 8 — — dB

138 FPGA-DS-02049-2.1
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Data Sheet

Symbol Description Test Conditions Min Typ Max Unit

Tx Common Mode Return Loss,
RLTX-CM 50 MHz < freq < 2.5 GHz 6 — — dB
including package and silicon
ZTX-DIFF-DC DC differential Impedance — — — 120 Ω
Tx AC peak common mode mV,
VTX-CM-AC-PP — — — 150
voltage, peak-peak p-p
Transmitter short-circuit
ITX-SHORT — — — 90 mA
current
Transmitter DC common-mode
VTX-DC-CM — 0 — 1.2 V
voltage
Electrical Idle Output DC
VTX-IDLE-DIFF-DC — 0 — 5 mV
voltage
Electrical Idle Differential
VTX-IDLE-DIFF-AC-p — — — 20 mV
Output peak voltage
Voltage change allowed during
VTX-RCV-DETECT — — — 600 mV
Receiver Detect
TTX-IDLE-MIN Min. time in Electrical Idle — 20 — — ns
Max. time from EI Order Set to
TTX-IDLE-SET-TO-IDLE — — — 8 ns
valid Electrical Idle
Max. time from Electrical Idle
TTX-IDLE-TO-DIFF-DATA — — — 8 ns
to valid differential output
500 + 4
LTX-SKEW Lane-to-Lane output skew — — — ps
UI
Receive2
UI Unit Interval — 199.94 200 200.06 ps
Differential Rx peak-peak
VRX-DIFF-PP — 0.343 — 1.2 V, p-p
voltage
Receiver random jitter 1.5 MHz – 100 MHz ps,
TRX-RJ-RMS — — 4.2
tolerance (RMS) Random noise RMS
Receiver deterministic jitter
TRX-DJ — — — 88 ps
tolerance
Receiver differential Return 50 MHz < freq < 1.25 GHz 10 — — dB
RLRX-DIFF
Loss, package plus silicon 1.25 GHz < freq < 2.5 GHz 8 — — dB
Receiver common mode
RLRX-CM Return Loss, package plus — 6 — — dB
silicon
Receiver DC single ended
ZRX-DC — 40 — 60 Ω
impedance
Receiver DC single ended
ZRX-HIGH-IMP-DC impedance when powered — 200 — — kΩ
down
Rx AC peak common mode mV,
VRX-CM-AC-P3 — — — 150
voltage peak
VRX-IDLE-DET-DIFF-PP Electrical Idle Detect Threshold — 65 — 1753 mv, pp
LRX-SKEW Receiver –lane-lane skew — — — 8 ns
Notes:
1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters.
2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters.
3. Spec compliant requirement

FPGA-DS-02049-2.1 139
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Data Sheet

4.26. Hardened SGMII Characteristics

4.26.1. SGMII Specifications
Table 4.47. SGMII
Symbol Description Test Conditions Min Typ Max Unit
fDATA SGMII Data Rate — — 1250 — MHz
SGMII Reference Clock Frequency (Data
fREFCLK — — 125 — MHz
Rate / 10)
Periodic jitter
JTOL_Dj Jitter Tolerance, Deterministic — — 0.11 UI
< 300 kHz
Periodic jitter
JTOL_Tj Jitter Tolerance, Total — — 0.31 UI
< 300 kHz
Δf/f Data Rate and Reference Clock Accuracy — –300 — 300 ppm
Notes:
1. JTOT can meet the following jitter mask specification: 0 to 3.5 kHz: 10 UI; 3.5 to 700 kHz: log-log slope 10 UI to 0.05 UI; above
700 kHz: 0.05 UI.
2. SGMII is not supported on 72-pin packages (QFN and WLCSP).

4.27. sysCONFIG Port Timing Specifications

Table 4.48. sysCONFIG Port Timing Specifications
Symbol Parameter Device Min Typ. Max Unit
Controller SPI POR/REFRESH Timing

REFRESH command executed, to the last rising

tICFG — — — 30 µs
edge of INITN (bulk-erase off)

Time from last rising edge of INITN to the valid

tVMC — — — 5 µs
Controller MCLK
fMCLK_DEF Default MCLK frequency (Before MCLK — — 3.5 — MHz
frequency selection in bitstream)
tICFG_POR Time during POR, from VCC, VCCAUX, VCCIO0, — — — 5 ms
or VCCIO1 (whichever is the last) pass POR trip
voltage, to the rising edge if INITN
Target SPI/I2C/I3C POR

Time during POR, from VCC, VCCAUX, VCCIO0 or

VCCIO1 (whichever is the last) pass POR trip
tMSPI_INH — — — 1 µs
voltage, to pull PROGRAMN LOW to prevent
entering MSPI mode

Minimum time driving PROGRAMN HIGH after

tACT_PROGRAMN_H — 50 — — ns
last activation clock
Minimum time to start driving CCLK (SSPI)
tCONFIG_CCLK — 50 — — ns
after PROGRAMN HIGH
Minimum time to start driving SCL (I2C/I3C)
tCONFIG_SCL — 50 — — ns
after PROGRAMN HIGH
PROGRAMN Configuration Timing
tPROGRAMN_L PROGRAMN LOW pulse accepted — 50 — — ns
tPROGRAMN_H PROGRAMN HIGH pulse accepted — 60 — — ns
tPROGRAMN_RJ PROGRAMN LOW pulse rejected — — — 25 ns
tINIT_LOW PROGRAMN LOW to INITN LOW — — — 100 ns
PROGRAMN LOW to INITN HIGH (bulk-erase
tINIT_HIGH — — — 50 µs
off)

140 FPGA-DS-02049-2.1
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Data Sheet

Symbol Parameter Device Min Typ. Max Unit

tDONE_LOW PROGRAMN LOW to DONE LOW — — — 55 µs
tDONE_HIGH2 PROGRAMN HIGH to DONE HIGH — — — 2 s
tIODISS PROGRAMN LOW to I/O Disabled — — — 125 ns
Controller SPI
fMCLK1 Max selected MCLK output frequency — — 112.5 124 MHz
fMCLK_DC MCLK output clock duty cycle — 40 — 60 %
tMCLKH MCLK output clock pulse width HIGH — 3.5 — — ns
tMCLKL MCLK output clock pulse width LOW — 3.5 — — ns
tSU_MSI MSI to MCLK setup time — 3 — — ns
tHD_MSI MSI to MCLK hold time — 0.5 — — ns
tCO_MSO 2 MCLK to MSO delay — — — 12 ns
Target SPI
fCCLK_W CCLK input clock frequency (For write — — — 120 MHz
transaction)4
fCCLK_R CCLK input clock frequency (For write — — — —6 MHz
transaction)5
tCCLKH CCLK input clock pulse width HIGH — 3.5 — — ns
tCCLKL CCLK input clock pulse width LOW — 3.5 — — ns
tVMC_SLAVE Time from rising edge of INITN to Target CCLK — 50 — — ns
driven
tVMC_MASTER CCLK input clock duty cycle — 40 — 60 %
tSU_SSI SSI to CCLK setup time — 3.2 — — ns
tHD_SSI SSI to CCLK hold time — 1.9 — — ns
tCO_SSO CCLK falling edge to valid SSO output — 3.07 — 307 ns
tEN_SSO CCLK falling edge to SSO output enabled — 3.07 — 307 ns
tDIS_SSO CCLK falling edge to SSO output disabled — 3.07 — 307 ns
tHIGH_SCSN SCSN HIGH time — 74 — — ns
tSU_SCSN SCSN to CCLK setup time — 3.5 — — ns
tHD_SCSN SCSN to CCLK hold time — 1.6 — — ns
I2C/I3C
fSCL_I2C SCL input clock frequency for I2C — — — 1 MHz
fSCL_I3C SCL input clock frequency for I3C — — — 12 MHz
tSCLH_I2C SCL input clock pulse width HIGH for I2C — 400 — — ns
tSCLL_I2C SCL input clock pulse width LOW for I2C — 400 — — ns
tSU_SDA_I2C SDA to SCL setup time for I2C — 250 — — ns
tHD_SDA_I2C SDA to SCL hold time for I2C — 50 — — ns
tSU_SDA_I3C SDA to SCL setup time for I3C — 30 — — ns
tHD_SDA_I3C SDA to SCL hold time for I3C — 30 — — ns
tCO_SDA SCL falling edge to valid SDA output — — — 200 ns
tEN_SDA SCL falling edge to SDA output enabled — — — 200 ns
tDIS_SDA SCL falling edge to SDA output disabled — — — 200 ns
Wake-Up Timing
Last configuration clock cycle to DONE going
tWAKEUP_DONE_HIGH2 — — — 60 µs
HIGH

tFIO_EN2 User I/O enabled in Early I/O Mode LIFCL-40 — 31184 cycles

FPGA-DS-02049-2.1 141
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Data Sheet

Symbol Parameter Device Min Typ. Max Unit

LIFCL-17 — — 20688 cycles

tIOEN2 Config clock to user I/O enabled — 150 — — ns

tMCLKZ2, 3 Controller MCLK to Hi-Z — — — 2.5 µs
Notes:
1. fMCLK has a dependency on HFOSC and is 1/3 of fCLKHF.
2. Based on 30k uncompressed/unauthenticated/default MCLK timing (3.5 MHz)/x1. Other permutations result in different values.
3. Measured using LVCMOS18, default MCLK frequency, slow slew rate.
4. Supported input clock frequency for bursting in configuration bitstream to the device.
5. Supported input clock frequency for reading out data transactions from the device.
6. Refer to the following equations to determine the supported input clock frequency for read transaction. Assumption: The skew
between CCLK and SSO on board is zero.
½ 𝐶𝐶𝐿𝐾 – 𝑡𝐶𝑂(𝑚𝑎𝑥) – 𝑇𝑠𝑢 > 0

𝐶𝐶𝐿𝐾 > 2(𝑡𝐶𝑂(𝑚𝑎𝑥) + 𝑇𝑠𝑢)

CCLK – Input clock period. fCCLK_R = 1/CCLK.

tCO(max) – Equivalent to tCO_SSO or tEN_SSO max value.
Tsu – Setup time requirement for host controller I/O.

𝐶𝐶𝐿𝐾 > 2(30𝑛𝑠 + 2𝑛𝑠)

𝐶𝐶𝐿𝐾 > 64𝑛𝑠

𝑓𝐶𝐶𝐿𝐾_𝑅 = 1/64𝑛𝑠 = 15.62𝑀𝐻𝑧

REFRESH Command tICFG

VCC/VCCAUX/
VCCIO0/VCCIO1 tICFG_POR

INITN

DONE

PROGRAMN fMCLK_DEF
tVMC
MCLK

MSI

Figure 4.14. Controller SPI POR/REFRESH Timing

142 FPGA-DS-02049-2.1
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Data Sheet

VCC/VCCAUX/
VCCIO0/VCCIO1 tICFG_POR

REFRESH Command tICFG

INITN

DONE
tMSPI_INH tACT_CRESETB_N
PROGRAMN Slave Activation

tACT_CCLK fCCLK tCONFIG_CCLK

CCLK

SSI
tACT_SCL fSCL tACT_CRESETB_N
tCONFIG_SCL
SCL

SDA

Figure 4.15. Target SPI/I2C/I3C POR/REFRESH Timing

Figure 4.16. Controller SPI PROGRAMN Timing

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Figure 4.17. Target SPI/I2C/I3C PROGRAMN Timing

fMCLK
tMCLKH
tMCLKL
MCLK tSU_MISO tHD_MISO

MSI
tCO_MOSI

MSO

Figure 4.18. Controller SPI Configuration Timing

144 FPGA-DS-02049-2.1
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Data Sheet

fCCLK
tCCLKH
CCLK tCCLKL

tSU_SSI tHD_SSI

SSI

tSU_SCSN tHD_SCSN

SCSN
tHIGH_SCSN

tCO_SSO

SSO
tEN_SSO tDIS_SSO

SSO

Figure 4.19. Target SPI Configuration Timing

fSCL
tSCLH
SCL
tSCLL
tSU_SDA tHD_SDA

SDA (input)

tCO_SDA
SDA (output)

tDIS_SDA
tEN_SDA
SDA (output)

Figure 4.20. I2C /I3C Configuration Timing

FPGA-DS-02049-2.1 145
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Data Sheet

CRESET_B

INITN
tWAK EUP_DONE_HIG H Device Wake-Up

DONE
CONFIG tMWC
Starts fMCLK_def fMCLK tMCLKZ
MCLK

tFIO_EN
USER I/O tIOEN
(FAST I/O)

tIOEN
USER I/O

Figure 4.21. Controller SPI Wake-Up Timing

CRESET_B

INITN
tWAK EUP_DONE_HIG H Device Wake-Up

DONE
CONFIG
Starts

CCLK/SCL
tFIO_EN
USER I/O tIOEN
(FAST I/Os)

tIOEN
USER I/O

Figure 4.22. Target SPI/I2C/I3C Wake-Up Timing

tINIT _HIGH tPR OGR AM_H

MSPI
Configuration
PROGRAMN tPR OGR AM_L SSPI/I2C/I3C
Configuration
tINIT L Configuration tINIT _HIGH
Error
INITN tINIT _HIGH Restart
Configuration
Configuration
DONE Started

Figure 4.23. Configuration Error Notification

146 FPGA-DS-02049-2.1
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Data Sheet

4.28. JTAG Port Timing Specifications

Table 4.49. JTAG Port Timing Specifications
Symbol Parameter Min Typ. Max Units
fMAX TCK clock frequency — — 25 MHz
tBTCPH TCK clock pulse width high 20 — — ns
tBTCPL TCK clock pulse width low 20 — — ns
tBTS TCK TAP setup time 5 — — ns
tBTH TCK TAP hold time 5 — — ns
tBTRF TAP controller TDO rise/fall time1 100 — — mV/ns
tBTCO TAP controller falling edge of clock to valid output — — 14 ns
tBTCODIS TAP controller falling edge of clock to valid disable — — 14 ns
tBTCOEN TAP controller falling edge of clock to valid enable — — 14 ns
tBTCRS BSCAN test capture register setup time 8 — — ns
tBTCRH BSCAN test capture register hold time 25 — — ns
tBUTCO BSCAN test update register, falling edge of clock to valid output — — 25 ns
tBTUODIS BSCAN test update register, falling edge of clock to valid disable — — 25 ns
tBTUPOEN BSCAN test update register, falling edge of clock to valid enable — — 25 ns
Note:
1. Based on default I/O setting of slow slew rate.

TMS

TDI

tBTS tBTH

tBTCPH tBTCPL tBTCP

TCK

tBTCOEN tBTCO tBTCODIS

TDO V a lid D a ta V a lid D a ta

tBTCRH
tBTCRS
Data to be
Captured Data Captured
from I/O

tBTUPOEN tBUTCO tBTUODIS

Data to be
driven out V a lid D a ta V a lid D a ta
to I/O

Figure 4.24. JTAG Port Timing Waveforms

FPGA-DS-02049-2.1 147
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Data Sheet

4.29. Switching Test Conditions

Figure 3.25 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are listed in Table 4.50.

R1
DUT Test Point

R2 CL*

*CL Includes Test Fixture and Probe Capacitance

Figure 4.25. Output Test Load, LVTTL and LVCMOS Standards

Table 4.50. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition R1 R2 CL Timing Ref. VT
LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)   0 pF LVCMOS 3.3 = 1.5 V —
LVCMOS 2.5 = VCCIO/2 —
LVCMOS 1.8 = VCCIO/2 —
LVCMOS 1.5 = VCCIO/2 —
LVCMOS 1.2 = VCCIO/2 —
LVCMOS 2.5 I/O (Z ≥ H)  1 MΩ 0 pF VCCIO/2 —
LVCMOS 2.5 I/O (Z ≥ L) 1 MΩ  0 pF VCCIO/2 VCCIO
LVCMOS 2.5 I/O (H ≥ Z)  100 0 pF VOH – 0.10 —
LVCMOS 2.5 I/O (L ≥ Z)  0 pF 100 VOL + 0.10 VCCIO
Note: Output test conditions for all other interfaces are determined by the respective standards.

148 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

5. Pinout Information

5.1. Signal Descriptions

Signal Name Bank Type Description
Power and GND
Vss — GND Ground for internal FPGA logic and I/O
VSSA_D-PHY — GND Analog Ground for D-PHY blocks
VSSSD — GND Ground for SerDes blocks
VCC — Power Power supply pins for core logic. VCC is connected to 1.0 V (nom.)
supply voltage. Power On Reset (POR) monitors this supply voltage.
VCCAUXA — Power Auxiliary power supply pin for internal analog circuitry. This supply is
connected to 1.8 V (nom.) supply voltage. POR monitors this supply
voltage.
VCCAUX — Power Auxiliary power supply pin for I/O Bank 0, Bank 1, Bank 2, Bank 6, and
Bank 7. This supply is connected to 1.8 V (nom.) supply voltage, and is
used for generating stable drive current for the I/O.
VCCAUXHx — Power Auxiliary power supply pin for I/O Bank 3, Bank 4, and Bank 5. This
supply is connected to 1.8 V (nom.) supply voltage, and is used for
generating stable current for the differential input comparators.
VCCIOx 0-7 Power Power supply pins for I/O bank x.
For x = 0, 1, 2, 6, and 7, VCCIO can be connected to (nom.) 1.2 V, 1.5 V,
1.8 V, 2.5 V, or 3.3 V.
For x = 3, 4, and 5, VCCIO can be connected to (nom.) 1.0 V, 1.2 V,
1.35 V, 1.5 V, or 1.8 V.
There are dedicated and shared configuration pins in banks 0 and 1.
POR monitors these banks supply voltages.
VCC_D-PHYx — Power 1.0 V (nom.) digital power supply for the hardened D-PHY blocks.
X = 0, 1
VCCA_D-PHYx — Power 1.8 V (nom.) analog power supply for the hardened D-PHY blocks.
X = 0, 1
VCCPLL_D-PHYx — Power 1.0 V (nom.) power supply for the hardened D-PHY blocks.
X = 0, 1
VCCADC182, 3 — Power 1.8 V (nom.) power supply for the ADC block.
VCCSD0 — Power 1.0 V (nom.) power supply for the SerDes block.
VCCPLLSD0 — Power 1.8 V (nom.) power supply for the PLL in the SerDes block.
VCCAUXSD — Power 1.8 V (nom.) auxiliary power supply for the SerDes block.
Dedicated Pins
Dedicated Configuration I/O Pin
JTAG_EN 1 Input LVCMOS input pin. This input selects the JTAG shared GPIO to be used
for JTAG
0 = GPIO
1 = JTAG
Dedicated ADC I/O Pins2
ADC_REF[0, 1] — Input ADC reference voltage, for each of the two ADC converters. If not used,
tie to ground.
ADC_DP/N[0, 1] — Input Dedicated ADC input pairs, for each of the two ADC converters. If not
used, tie to ground.

FPGA-DS-02049-2.1 149
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Data Sheet

Signal Name Bank Type Description

Dedicated High Speed I/O Pins
SD0_RXDP/N — Input High Speed Data Differential Input Pairs

SD0_TXDP/N — Output High Speed Data Differential Output Pairs

SD0_REFCLKP/N — Input High Speed Reference Clock Differential Input Pairs

SD0_REXT — Input High Speed External Reference Resistor Input. Resistor connects
between to this pin and SD0_REFRET pin. This is used to adjust the on-
chip differential termination impedance, based on the external
resistance value:
REXT = 909 Ω, RDIFF = 80 Ω
REXT = 976 Ω, RDIFF = 85 Ω
REXT = 1.02 kΩ, RDIFF = 90 Ω
REXT = 1.15 kΩ, RDIFF = 100 Ω
SD0_REFRET — Input High Speed Reference Return Input. These pins should be AC coupled
to the VCCPLLSD0 supply
Dedicated D-PHY I/O Pins
D-PHY[0-1]_DP/N[0-3] — Input, Hardened D-PHY Data Input/Output Pairs, for each of the 4 High Speed
Output lanes in the 2 Hardened D-PHY Blocks
D-PHY[0-1]_CKP/N — Input, Hardened D-PHY Clock Input/Output Pairs, for each of the 2 Hardened
Output D-PHY Blocks
Misc Pins
NC — — No connect.
RESERVED — — This pin is reserved and should not be connected to anything on the
General Purpose I/O Pins board.
P[T/B/L/R] [Number]_[A/B] T=0 Input, Programmable User I/O:
R = 1, 2 Output, [T/B/L/R] indicates the package pin/ball is in T (Top), B (Bottom), L
B = 3, 4, 5 Bi-Dir (Left), or R (Right) edge of the device.
L = 6. 7 [Number] identifies the PIO [A/B] pair.
[A/B] shows the package pin/ball is A or B signal in the pair. PIO A and
PIO B are grouped as a pair.
Each A/B pair in the bottom banks supports true differential input and
output buffers. When configured as differential input, differential
termination of 100 Ω can be selected.
Each A/B pair in the top, left and right banks does not support true
differential input or output buffer. It supports all single-ended inputs
and outputs, and can be used for emulated differential output buffer.
Some of these user-programmable I/O are used during configuration,
depending on the configuration mode. You need to make appropriate
connection on the board to isolate the two different functions
before/after configuration.
Some of these user-programmable I/O are shared with special function
pins. These pins, when not used as special purpose pins, can be
programmed as I/O for user logic.
During configuration the user-programmable I/O are tri-stated with an
internal weak pull-down resistor enabled. If any pin is not used (or not
bonded to a package pin), it is tri-stated and default to have weak pull-
down enabled after configuration.

150 FPGA-DS-02049-2.1
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Data Sheet

Signal Name Bank Type Description

Shared Configuration Pins
1. These pins can be used for configuration during configuration mode. When configuration is completed, these pins can be
used as GPIO, or shared function in GPIO. When these pins are used in dual function, users need to isolate the signal
paths for the dual functions on the board.
2. The pins used are defined by the configuration modes detected. Target SPI or I2C/I3C modes are detected during Target
activation. Pins that are not used in the configuration mode selected are tri-stated during configuration, and can connect
directly as GPIO in user’s function.

PRxxx /SDA/USER_SDA 1 Input, Configuration:

Output, I2C/I3C Mode: SDA signal
Bi-Dir User Mode:
PRxxx: GPIO
User_SDA: SDA signal for I2C/I3C interface
PRxxx /SCL/USER_SCL 1 Input, Configuration:
Output, I2C/I3C Mode: SCL signal
Bi-Dir User Mode:
PRxxx: GPIO
User_SDA: SCL signal for I2C/I3C interface
PRxxx/TDO/SSO 1 Input, Configuration:
Output, Target SPI Mode: Target Serial Output
Bi-Dir User Mode:
PRxxx: GPIO
TDO: When JTAG_EN = 1, used as TDO signal for JTAG
PRxxx/TDI/SSI 1 Input, Configuration:
Output, Target SPI Mode: Target Serial Input
Bi-Dir User Mode:
PRxxx: GPIO
TDI: When JTAG_EN = 1, used as TDI signal for JTAG
PRxxx/TMS/SCSN 1 Input, Configuration:
Output, Target SPI Mode: Target Chip Select
Bi-Dir User Mode:
PRxxx: GPIO
TMS: When JTAG_EN = 1, used as TMS signal for JTAG
PRxxx/TCK/SCLK 1 Input, Configuration:
Output, Target SPI Mode: Target Clock Input
Bi-Dir User Mode:
PRxxx: GPIO
TCK: When JTAG_EN = 1, used as TCK signal for JTAG
PTxxx/MCSNO 0 Input, Configuration:
Output, Flow-through Daisy Chain Mode: Chip Select Output
Bi-Dir User Mode:
PTxxx: GPIO

PTxxx/MD3 0 Input, Configuration:

Output, Controller Quad SPI Mode: I/O3
Bi-Dir User Mode:
PTxxx: GPIO

PTxxx/MD2 0 Input, Configuration:

Output, Controller Quad SPI Mode: I/O2
Bi-Dir User Mode:
PTxxx: GPIO

FPGA-DS-02049-2.1 151
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Data Sheet

Signal Name Bank Type Description

PTxxx/MSI/MD1 0 Input, Configuration:
Output, Controller SPI Mode: Controller Serial Input
Bi-Dir Controller Quad SPI Mode: I/O1
User Mode:
PTxxx: GPIO
PTxxx/MSO/MD0 0 Input, Configuration:
Output, Controller SPI Mode: Controller Serial Output
Bi-Dir Controller Quad SPI Mode: I/O0
User Mode:
PTxxx: GPIO
PTxxx/MCSN/PCLKT0_1 0 Input, Configuration:
Output, Controller SPI Mode: Controller Chip Select Output
Bi-Dir User Mode:
PTxxx: GPIO
PCLKT0_0: Top PCLK Input
PTxxx/MCLK/PCLKT0_0 0 Input, Configuration:
Output, Controller SPI Mode: Controller Clock Output
Bi-Dir User Mode:
PTxxx: GPIO
PCLKT0_1: Top PCLK Input
PTxxx/PROGRAMN 0 Input, Configuration:
Output, PROGRAMN: Initiate configuration sequence when asserted LOW.
Bi-Dir User Mode:
PTxxx: GPIO
PTxxx/INITN 0 Input, Configuration:
Output, INITN: Open Drain I/O pin. This signal is driven to LOW when
Bi-Dir configuration sequence is started, to indicate the device is in
initialization state. This signal is released after initialization is
completed, and the configuration download can start. You can keep
drive this signal LOW to delay configuration download to start.
User Mode:
PTxxx: GPIO
PTxxx/DONE 0 Input, Configuration:
Output, DONE: Open Drain I/O pin. This signal is driven to LOW during
Bi-Dir configuration time. It is released to indicate the device has completed
configuration. You can keep drive this signal LOW to delay the device to
wake up from configuration.
User Mode:
PTxxx: GPIO
Shared User GPIO Pins
1. Shared User GPIO pins are pins that can be used as GPIO, or functional pins that connect directly to specific functional
blocks, when device enters into User Mode.
2. Declaring on assigning the pin as GPIO or specific functional pin is done by configuration bitstream, except JTAG pins.
3. JTAG pins are controlled by JTAG_EN signal. When JTAG_EN = 1, the pins are used for JTAG interface. When JTAG = 0, the
pins are used as GPIO or specific functional pin defined by configuration bitstream.
4. Refer to package pin file.

152 FPGA-DS-02049-2.1
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Data Sheet

Signal Name Bank Type Description

Shared JTAG Pins
PRxxx/EIO 1,2,6,7 Input, User Mode:
Output, PRxxx: GPIO
Bi-Dir EIO: Early I/O Release, for more information refer to sysCONFIG User
Guide for Nexus Platform (FPGA-TN-02099) Section 5.5.

PLxxx/EIO 1,2,6,7 Input, User Mode:

Output, PLxxx: GPIO
Bi-Dir EIO: Early I/O Release, for more information refer to sysCONFIG User
Guide for Nexus Platform (FPGA-TN-02099) Section 5.5.

PRxxx/TDO/ yyyy 1 Input, User Mode:

Output, PRxxx: GPIO
Bi-Dir TDO: When JTAG_EN = 1, used as TDO signal for JTAG
yyyy: Other possible selectable specific functional

PRxxx/TDI/yyyy 1 Input, User Mode:

Output, PRxxx: GPIO
Bi-Dir TDI: When JTAG_EN = 1, used as TDI signal for JTAG
yyyy: Other possible selectable specific functional

PRxxx/TMS/ yyyy 1 Input, User Mode:

Output, PRxxx: GPIO
Bi-Dir TMS: When JTAG_EN = 1, used as TMS signal for JTAG
yyyy: Other possible selectable specific functional

PRxxx/TCK/ yyyy 1 Input, User Mode:

Output, PRxxx: GPIO
Bi-Dir TCK: When JTAG_EN = 1, used as TCK signal for JTAG
Yyyy: Other possible selectable specific functional

Shared CLOCK Pins

1. Some PCLK pins can also be used as GPLL reference clock input pin. Refer to sysCLOCK PLL Design and User Guide for
Nexus Platform (FPGA-TN-02095).
PBxxx/PCLK[T,C][3,4,5]_[0- 3, 4, 5 Input, User Mode:
3]/yyyy Output, PBxxx: GPIO
Bi-Dir PCLK: Primary Clock or GPLL Refclk signal
[T,C] = True/Complement when using differential signaling
[3,4,5] = Bank
[0-3] Up to 4 signals in the bank
yyyy: Other possible selectable specific functional
PTxxx/PCLKT0_[0-1]/yyyy 0 Input, User Mode:
Output, PTxxx: GPIO
Bi-Dir PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)
[0-1] Up to 2 signals in the bank
yyyy: Other possible selectable specific functional
PRxxx/PCLKT[1,2]_[0-2]/yyyy 1, 2 Input, User Mode:
Output, PRxxx: GPIO
Bi-Dir PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)
[0-2] Up to 3 signals in the bank
yyyy: Other possible selectable specific functional

FPGA-DS-02049-2.1 153
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Data Sheet

Signal Name Bank Type Description

PLxxx/PCLKT[6,7]_[0-2]/yyyy 6, 7 Input, User Mode:
Output, PLxxx: GPIO
Bi-Dir PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)
[0-2] Up to 3 signals in the bank
yyyy: Other possible selectable specific functional
PBxxx/LRC_GPLL[T,C]_IN/yyyy 3 Input, User Mode:
Output, PBxxx: GPIO
Bi-Dir LRC_GPLL: Lower Right GPLL Refclk signal (PLLCK)
[T,C] = True/Complement when using differential signaling
yyyy: Other possible selectable specific functional
PBxxx/LLC_GPLL[T,C]_IN/yyyy 5 Input, User Mode:
Output, PBxxx: GPIO
Bi-Dir LLC_GPLL: Lower Left GPLL Refclk signal (PLLCK)
[T,C] = True/Complement when using differential signaling
yyyy: Other possible selectable specific functional
PLxxx/ULC_GPLLT_IN/yyyy 7 Input, User Mode:
Output, PLxxx: GPIO
Bi-Dir ULC_GPLL: Upper Left GPLL Refclk signal (Only Single Ended) (PLLCK)
yyyy: Other possible selectable specific functional

Shared VREF Pins

PBxxx/VREF[3,4,5]_[1-2]/yyyy 3, 4, 5 Input, User Mode:
Output, PBxxx: GPIO
Bi-Dir VREF: Reference Voltage for DDR memory function
[3,4,5] = Bank
[1-2] Up to VREFs for each bank
yyyy: Other possible selectable specific functional
Shared ADC Pins
PBxxx/ADC_C[P,N]nn/yyyy 3, 4, 5 Input, User Mode:
Output, PBxxx: GPIO
Bi-Dir ADC_C: ADC Channel Inputs
[P,N] = Positive or Negative Input
nn = ADC Channel number (0 – 15)
yyyy: Other possible selectable specific functional
Shared Comparator Pins
PBxxx/COMP[1-3][P,N]/yyyy 3, 5 Input, User Mode:
Output, PBxxx: GPIO
Bi-Dir COMP: Differential Comparator Input
[P,N] = Positive or Negative Input
[1-3] = Input to Comparators 1-3
yyyy: Other possible selectable specific functional
Shared SGMII Pins
PBxxx/SGMII_RX[P,N][0- 3, 5 Input, User Mode:
1]/yyyy Output, PBxxx: GPIO
Bi-Dir SGMII_RX: Differential SGMII RX Inputs
[P,N] = Positive or Negative Input
[0-1] = Input to SGMII RX0 or RX1
yyyy: Other possible selectable specific functional
Notes:
1. Not all signals are available as external pins in all packages. Refer to the Pinout List file for various package details.
2. ADC is available in Commercial/Industrial –8 and –9 speed grades and Automotive –7 speed grade.
3. On devices that do not support the ADC, this pin may be powered or left floating.

154 FPGA-DS-02049-2.1
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Data Sheet

5.2. Pin Information Summary

5.2.1. CrossLink-NX Family
Pin Information LIFCL-17 LIFCL-40
Summary 72 QFN 72WLCSP 121csfBGA 256caBGA 72 QFN 121csfBGA 256caBGA 289csBGA 400caBGA
User I/O Pins
Bank 0 10 8 12 12 10 12 12 12 12
Bank 1 7 7 11 11 7 11 20 19 21
General Bank 2 0 0 0 0 0 0 13 24 28
Purpose Bank 3 12 12 16 16 12 16 32 32 32
Inputs/Outputs Bank 4 0 0 16 16 0 22 32 32 32
per Bank Bank 5 10 12 16 16 10 10 10 10 10
Bank 6 0 0 0 0 0 0 26 28 28
Bank 7 0 0 0 0 0 0 11 16 22
Total Single-Ended User
39 39 71 71 39 71 156 173 185
I/O
Bank 0 0 0 0 0 0 0 0 0 0
Bank 1 0 0 0 0 0 0 0 0 0
Bank 2 0 0 0 0 0 0 0 0 0
Differential Bank 3 12 12 16 16 12 16 32 32 32
Input / Output
Pairs Bank 4 0 0 16 16 0 22 32 32 32
Bank 5 10 12 16 16 10 10 10 10 10
Bank 6 0 0 0 0 0 0 0 0 0
Bank 7 0 0 0 0 0 0 0 0 0
Total Differential I/O 22 24 48 48 22 48 74 74 74
Power Pins
VCC, VCCECLK 8 3 3 5 8 3 5 6 8
VCCAUXA 0 0 0 0 0 0 1 1 1
VCCAUX 2 2 1 3 2 1 2 2 3
VCCAUXHx 2 2 3 3 2 3 3 3 3
VCCAUXSD 0 0 0 0 0 0 1 1 1
Bank 0 1 1 1 1 1 1 1 1 1
Bank 1 1 1 1 1 1 1 1 2 2
Bank 2 0 0 0 0 0 0 1 2 2
Bank 3 2 1 1 1 2 1 1 2 2
VCCIO
Bank 4 0 0 1 1 0 1 1 2 2
Bank 5 1 1 1 1 1 1 1 1 1
Bank 6 0 0 0 0 0 0 1 2 2
Bank 7 0 0 0 0 0 0 1 2 2
VCC_D-PHYx 2 1 2 2 2 2 2 2 2
VCCA_D-PHYx 1 1 2 2 1 2 2 2 2
VCCPLL_D-PHYx 1 1 2 2 1 2 2 2 2
VCCSD0 0 0 0 0 0 0 1 2 2
VCCPLLSD0 0 0 0 0 0 0 1 1 1
VCCADC181 1 03 03 1 1 03 1 1 1
Total Power Pins 22 14 18 23 22 18 29 37 40

FPGA-DS-02049-2.1 155
CrossLink-NX Family
Data Sheet

Pin Information LIFCL-17 LIFCL-40

Summary 72 QFN 72WLCSP 121csfBGA 256caBGA 72 QFN 121csfBGA 256caBGA 289csBGA 400caBGA
GND Pins
Vss 0 5 6 20 0 6 22 26 37
VSSADC 0 0 0 1 0 0 1 1 1
VSSSD 0 0 0 0 0 0 5 8 12
VSSA_D-PHY 0 3 5 8 0 5 8 9 7
Total GND Pins 0 8 11 29 0 11 36 44 57
Dedicated Pins
Dedicated ADC Channels 0 0 0 2 0 0 2 2 2
(pairs)1
Dedicated ADC Reference 0 0 0 2 0 0 2 2 2
Voltage Pins1
Dedicated D-PHY Data 4 4 8 8 4 8 8 8 8
Channels (pairs)
Dedicated D-PHY Clock 1 1 2 2 1 2 2 2 2
(pairs)
Dedicated Misc Pins
JTAGEN 1 1 1 1 1 1 1 1 1
NC 0 0 0 106 0 0 0 0 83
RESERVED 0 0 0 0 0 0 0 0 0
Total Dedicated Pins 11 11 21 133 6 11 17 17 17
Shared Pins
Bank 0 10 8 10 10 10 10 10 10 10
Bank 1 0 0 0 0 6 6 6 6 6
Bank 2 0 0 0 0 0 0 0 0 0
Shared Bank 3 0 0 0 0 0 0 0 0 0
Configuration
Pins Bank 4 0 0 0 0 0 0 0 0 0
Bank 5 0 0 0 0 0 0 0 0 0
Bank 6 0 0 0 0 0 0 0 0 0
Bank 7 0 0 0 0 0 0 0 0 0
Bank 0 0 0 0 0 0 0 0 0 0
Bank 1 4 4 4 4 4 4 4 4 4
Bank 2 0 0 0 0 0 0 0 0 0
Shared JTAG Bank 3 0 0 0 0 0 0 0 0 0
Pins Bank 4 0 0 0 0 0 0 0 0 0
Bank 5 0 0 0 0 0 0 0 0 0
Bank 6 0 0 0 0 0 0 0 0 0
Bank 7 0 0 0 0 0 0 0 0 0
Bank 0 0 0 2 2 2 2 2 2 2
Bank 1 0 0 3 3 0 3 3 3 3
Bank 2 0 0 0 0 0 0 3 3 3
Shared PCLK Bank 3 8 8 8 8 8 8 8 8 8
Pins Bank 4 0 0 8 8 0 8 8 8 8
Bank 5 8 8 8 8 8 8 8 8 8
Bank 6 0 0 0 0 0 0 3 3 3
Bank 7 0 0 0 0 0 0 3 3 3

156 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Pin Information LIFCL-17 LIFCL-40

Summary 72 QFN 72WLCSP 121csfBGA 256caBGA 72 QFN 121csfBGA 256caBGA 289csBGA 400caBGA
Bank 0 0 0 0 0 0 0 0 0 0
Bank 1 0 0 0 0 0 0 0 0 0
Bank 2 0 0 0 0 0 0 0 0 0
Shared GPLL Bank 3 2 2 2 2 2 2 2 2 2
Pins Bank 4 0 0 0 0 0 0 0 0 0
Bank 5 2 2 2 2 2 2 2 2 2
Bank 6 0 0 0 0 0 0 0 0 0
Bank 7 0 0 0 0 0 0 2 2 2
Bank 0 0 0 0 0 0 0 0 0 0
Bank 1 0 0 0 0 0 0 0 0 0
Bank 2 0 0 0 0 0 0 0 0 0
Shared VREF Bank 3 2 2 2 2 2 2 2 2 2
Pins Bank 4 0 0 2 2 0 1 2 2 2
Bank 5 2 2 2 2 2 2 2 2 2
Bank 6 0 0 0 0 0 0 0 0 0
Bank 7 0 0 0 0 0 0 0 0 0
Bank 0 0 0 0 0 0 0 0 0 0
Bank 1 0 0 0 0 0 0 0 0 0
Bank 2 0 0 0 0 0 0 0 0 0
Shared ADC Bank 3 5 5 7 7 5 7 12 12 12
Channels
(pairs)1 Bank 4 0 0 0 0 0 0 0 0 0
Bank 5 4 4 4 4 4 4 4 4 4
Bank 6 0 0 0 0 0 0 0 0 0
Bank 7 0 0 0 0 0 0 0 0 0
Bank 0 0 0 0 0 0 0 0 0 0
Bank 1 0 0 0 0 0 0 0 0 0
Bank 2 0 0 0 0 0 0 0 0 0
Shared
Comparator Bank 3 0 0 0 0 0 0 3 3 3
Channels Bank 4 0 0 0 0 0 0 0 0 0
(pairs)1, 2 0 0 0 0 0 0 3 3 3
Bank 5
Bank 6 0 0 0 0 0 0 0 0 0
Bank 7 0 0 0 0 0 0 0 0 0
Bank 0 0 0 0 0 0 0 0 0 0
Bank 1 0 0 0 0 0 0 0 0 0
Bank 2 0 0 0 0 0 0 0 0 0
Shared SGMII Bank 3 0 0 0 0 0 0 0 0 0
Channels (pairs) Bank 4 0 0 0 0 0 0 0 0 0
Bank 5 2 2 2 2 2 2 2 2 2
Bank 6 0 0 0 0 0 0 0 0 0
Bank 7 0 0 0 0 0 0 0 0 0
Notes:
1. ADC is available in Commercial/Industrial –8 and –9 speed grades and Automotive –7 speed grade.
2. Comparator inputs are selected in the software to be separate (Bank 3) or combined with ADC Channels (Bank 5).
3. ADC is powered by VCCAUX.

FPGA-DS-02049-2.1 157
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Data Sheet

6. Ordering Information
Lattice provides a wide variety of services for its products including custom marking, factory programming, known good
die, and application specific testing. Contact the local sales representatives for more details.

6.1. Part Number Description

LIFCL - 40 - X XXXX X
Grade
Device Family
C = Commercial
CrossLink-NX FPGA
I = Industrial
A = Automotive

Logic Capacity
40 = 39 k Logic Cells
Package
SG72 = 72-pin QFN
MG121 = 121-ball csfBGA
BG256 = 256-ball caBGA
MG289 = 289-ball csBGA
BG400 = 400-ball caBGA

Speed (same number for HP and LP)*

7 = Slowest
8
9 = Fastest

LIFCL - 17 - X XXXX X
Device Family Grade
CrossLink-NX FPGA C = Commercial
I = Industrial
A = Automotive
Logic Capacity
17 = 17 k Logic Cells
Package
UWG72 = 72-ball WLCSP
SG72 = 72-pin QFN
MG121 = 121-ball csfBGA
BG256 = 256-ball caBGA

Speed (same number for HP and LP)*

7 = Slowest
8
9 = Fastest

*
Note: Input Comparator, ADC, EBR ECC, and DTR are only available in –7 (-A), –8 (-C/I), and –9 (-C/I) speed and grade.

158 FPGA-DS-02049-2.1
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Data Sheet

6.2. Ordering Part Numbers

6.2.1. Commercial
Part Number Speed Package Pins Temp. Logic Cells (k)
LIFCL-17-7UWG72C –7 Lead free WLCSP 72 Commercial 17
LIFCL-17-8UWG72C –8 Lead free WLCSP 72 Commercial 17
LIFCL-17-7SG72C –7 Lead free QFN 72 Commercial 17
LIFCL-17-8SG72C –8 Lead free QFN 72 Commercial 17
LIFCL-17-9SG72C –9 Lead free QFN 72 Commercial 17
LIFCL-17-7MG121C –7 Lead free csfBGA 121 Commercial 17
LIFCL-17-8MG121C –8 Lead free csfBGA 121 Commercial 17
LIFCL-17-9MG121C –9 Lead free csfBGA 121 Commercial 17
LIFCL-17-7BG256C –7 Lead free caBGA 256 Commercial 17
LIFCL-17-8BG256C –8 Lead free caBGA 256 Commercial 17
LIFCL-17-9BG256C –9 Lead free caBGA 256 Commercial 17
LIFCL-40-7SG72C –7 Lead free QFN 72 Commercial 39
LIFCL-40-8SG72C –8 Lead free QFN 72 Commercial 39
LIFCL-40-9SG72C –9 Lead free QFN 72 Commercial 39
LIFCL-40-7MG121C –7 Lead free csfBGA 121 Commercial 39
LIFCL-40-8MG121C –8 Lead free csfBGA 121 Commercial 39
LIFCL-40-9MG121C –9 Lead free csfBGA 121 Commercial 39
LIFCL-40-7MG289C –7 Lead free csBGA 289 Commercial 39
LIFCL-40-8MG289C –8 Lead free csBGA 289 Commercial 39
LIFCL-40-9MG289C –9 Lead free csBGA 289 Commercial 39
LIFCL-40-7BG256C –7 Lead free caBGA 256 Commercial 39
LIFCL-40-8BG256C –8 Lead free caBGA 256 Commercial 39
LIFCL-40-9BG256C –9 Lead free caBGA 256 Commercial 39
LIFCL-40-7BG400C –7 Lead free caBGA 400 Commercial 39
LIFCL-40-8BG400C –8 Lead free caBGA 400 Commercial 39
LIFCL-40-9BG400C –9 Lead free caBGA 400 Commercial 39

6.2.2. Industrial
Part Number Speed Package Pins Temp. Logic Cells (k)
LIFCL-17-8UWG72I –8 Lead free WLCSP 72 Industrial 17
LIFCL-17-7SG72I –7 Lead free QFN 72 Industrial 17
LIFCL-17-8SG72I –8 Lead free QFN 72 Industrial 17
LIFCL-17-9SG72I –9 Lead free QFN 72 Industrial 17
LIFCL-17-7MG121I –7 Lead free csfBGA 121 Industrial 17
LIFCL-17-8MG121I –8 Lead free csfBGA 121 Industrial 17
LIFCL-17-9MG121I –9 Lead free csfBGA 121 Industrial 17
LIFCL-17-7BG256I –7 Lead free caBGA 256 Industrial 17
LIFCL-17-8BG256I –8 Lead free caBGA 256 Industrial 17
LIFCL-17-9BG256I –9 Lead free caBGA 256 Industrial 17
LIFCL-40-7SG72I –7 Lead free QFN 72 Industrial 39
LIFCL-40-8SG72I –8 Lead free QFN 72 Industrial 39
LIFCL-40-9SG72I –9 Lead free QFN 72 Industrial 39
LIFCL-40-7MG121I –7 Lead free csfBGA 121 Industrial 39
LIFCL-40-8MG121I –8 Lead free csfBGA 121 Industrial 39

FPGA-DS-02049-2.1 159
CrossLink-NX Family
Data Sheet

Part Number Speed Package Pins Temp. Logic Cells (k)

LIFCL-40-9MG121I –9 Lead free csfBGA 121 Industrial 39
LIFCL-40-7MG289I –7 Lead free csBGA 289 Industrial 39
LIFCL-40-8MG289I –8 Lead free csBGA 289 Industrial 39
LIFCL-40-9MG289I –9 Lead free csBGA 289 Industrial 39
LIFCL-40-7BG256I –7 Lead free caBGA 256 Industrial 39
LIFCL-40-8BG256I –8 Lead free caBGA 256 Industrial 39
LIFCL-40-9BG256I –9 Lead free caBGA 256 Industrial 39
LIFCL-40-7BG400I –7 Lead free caBGA 400 Industrial 39
LIFCL-40-8BG400I –8 Lead free caBGA 400 Industrial 39
LIFCL-40-9BG400I –9 Lead free caBGA 400 Industrial 39

6.2.3. Automotive
Part Number Speed Package Pins Temp. Logic Cells (k)
LIFCL-17-7MG121A –7 Lead free csfBGA 121 Automotive 17
LIFCL-17-7BG256A –7 Lead free caBGA 256 Automotive 17
LIFCL-40-7MG121A –7 Lead free csfBGA 121 Automotive 39
LIFCL-40-7BG256A –7 Lead free caBGA 256 Automotive 39

160 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

References
A variety of technical notes for the CrossLink-NX family are available.
• sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02028)
• Thermal Management (FPGA-TN-02044)
• sysI/O User Guide for Nexus Platform (FPGA-TN-02067)
• Power Management and Calculation for CrossLink-NX Devices (FPGA-TN-02075)
• Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform (FPGA-TN-02076)
• CrossLink-NX Hardened D-PHY User Guide (FPGA-TN-02081)
• Using TraceID (FPGA-TN-02084)
• Memory User Guide for Nexus Platform (FPGA-TN-02094)
• sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095)
• sysDSP User Guide for Nexus Platform (FPGA-TN-02096)
• CrossLink-NX High-Speed I/O Interface (FPGA-TN-02097)
• sysCONFIG User Guide for Nexus Platform (FPGA-TN-02099)
• ADC User Guide for Nexus Platform (FPGA-TN-02129)
• I2C Hardened IP User Guide for Nexus Platform (FPGA-TN-02142)
• Multi-Boot User Guide for Nexus Platform (FPGA-TN-02145)
• High-Speed PCB Design Considerations (FPGA-TN-02178)
• CrossLink-NX Hardware Checklist (FPGA-TN-02149)
• CrossLink-NX Single Event Upset (SEU) Report (FPGA-TN-02174)
• Lattice Memory Mapped Interface and Lattice Interrupt Interface User Guide (FPGA-UG-02039)
For further information on interface standards refer to the following websites:
• JEDEC Standards (LVTTL, LVCMOS, SSTL) – www.jedec.org
• PCI – www.pcisig.com
For more info on this FPGA device, refer to the following:
• CrossLink-NX FPGA web page
• Lattice Radiant Software FPGA web page
• Lattice Insights for Lattice Semiconductor training courses and learning plans

FPGA-DS-02049-2.1 161
CrossLink-NX Family
Data Sheet

Technical Support Assistance

Submit a technical support case through www.latticesemi.com/techsupport.
For frequently asked questions, refer to the Lattice Answer Database at ww.latticesemi.com/Support/AnswerDatabase.

162 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Revision History
Revision 2.1, September 2024
Section Change Summary
All • Removed The Root Complex reference.
• Renamed Supplemental Information section to References section.
• Changed Master to Controller.
• Changed Slave to Target.
Abbreviations in This document • Added the definition of SHA: Secure Hashing Algorithm.
• Changed Acronyms to Abbreviations.
General Description Added the following in the Feature section:
• Available in Commercial, Industrial and Automotive temperature grades.
DC and Switching Characteristics • Removed the statement, and follow the SMIA 1.0, Part 2: CCP2 Specification in Section
for Commercial and Industrial 3.12.3 SubLVDS (Input Only).
• Updated the following descriptions in Table 3.33. External Switching Characteristics (VCC
= 1.0 V) under Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin
(GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input:
• tDQVA_GDDRX4: Output Data Valid After CLK Output
• fDATA_GDDRX4: Input/Output Data Rate
• FMAX_GDDRX4: Frequency for ECLK
• fPCLK: PCLK frequency
• Added the following units in Table 3.33. External Switching Characteristics (VCC = 1.0 V)
under Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin
(GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input:
• tDVB_GDDRX4: ns, and ns + 1/2UI
• tDQVA_GDDRX4: ns, and ns + 1/2UI
• Updated the tIPJIT specification in Table 3.34. sysCLOCK PLL Timing (VCC = 1.0 V) –
Commercial/Industrial to:
• fPFD ≥ 20MHz : 0.01 UIPP
• fPFD<20MHz : 500 ps p-p
• Added table note 4 to Table 3.37. ADC Specifications1.
• Updated the following values in Table 3.37. ADC Specifications1:
• ADC Clock Frequency: Max→ 50 MHz
• ADC Input Frequency: Condition → @Sampling frequency = 1 Mbps
• ADC Input Equivalent Resistance: Condition → ---- (removed value)
• Removed ADC Clock Duty Cycle from the table
• Updated the following in Table 3.48. sysCONFIG Port Timing Specifications:
• Updated tPROGRAMN specification
• Renamed tPROGRAMN to tPROGRAMN_L and tPROGRAMN_H
• Updated Target SPI Specification
• Added table notes 4-7
• Removed the LIFCL-40 and LIFCL-17 devices in the tINIT_HIGH specification. One
tINIT_HIGH specification is applicable to all CrossLink-NX devices
• Updated the tINIT_HIGH specification to 40µs (Max)
• Updated the following Max values:
• tCO_SSO: 16 ns
• tEN_SSO: 16 ns
• tDIS_SSO: 16 ns
• Updated the following symbols in Figure 3.19. Target SPI Configuration Timing:
• tCO_MISO to tCO_SSO
• tEN_MISO to tEN_SSO
• tDIS_MISO to tDIS_SSO
• tSU_MOSI to tSU_SSI

FPGA-DS-02049-2.1 163
CrossLink-NX Family
Data Sheet

Section Change Summary

• tHD_MOSI to tHD_SSI
• Added Figure 3.23. Configuration Error Notification.
DC and Switching Characteristics • Removed the statement, and follow the SMIA 1.0, Part 2: CCP2 Specification in Section
for Automotive 4.12.3 SubLVDS (Input Only).
• Updated the following descriptions in Table 4.33. External Switching Characteristics (VCC
= 1.0 V) under Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin
(GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input:
• tDQVA_GDDRX4: Output Data Valid After CLK Output
• fDATA_GDDRX4: Input/Output Data Rate
• FMAX_GDDRX4: Frequency for ECLK
• fPCLK: PCLK frequency
• Added the following units in in Table 4.33. External Switching Characteristics (VCC = 1.0
V) under Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin
(GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input.
• tDVB_GDDRX4: ns, and ns + 1/2UI
• tDQVA_GDDRX4: ns, and ns + 1/2UI
• Updated the tIPJIT specification in Table 4.34. sysCLOCK PLL Timing (VCC = 1.0 V) –
Automotive to:
• fPFD ≥ 20MHz : 0.01 UIPP
• fPFD<20MHz : 500 ps p-p
• Added table note 4 in Table 4.37. ADC Specifications3.
• Updated the following values in Table 4.37. ADC Specifications3:
• ADC Clock Frequency: Max→ 50 MHz
• ADC Input Frequency: Condition → @Sampling frequency = 1 Mbps
• ADC Input Equivalent Resistance: Condition → ---- (removed value)
• Removed ADC Clock Duty Cycle from the table
• Updated the following in Table 4.48. sysCONFIG Port Timing Specifications:
• Updated tPROGRAMN specification
• Renamed tPROGRAMN to tPROGRAMN_L and tPROGRAMN_H
• Updated Target SPI Specification
• Added table notes 4-7
• Removed the LIFCL-40 and LIFCL-17 devices in the tINIT_HIGH specification. One
tINIT_HIGH specification is applicable to all CrossLink-NX devices
• Updated the tINIT_HIGH specification to 50µs (Max)
• Updated the following symbols in Figure 4.19. Target SPI Configuration Timing:
• tCO_MISO to tCO_SSO
• tEN_MISO to tEN_SSO
• tDIS_MISO to tDIS_SSO
• tSU_MOSI to tSU_SSI
• tHD_MOSI to tHD_SSI
• Added Figure 4.23. Configuration Error Notification.

164 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Revision 2.0, October 2023

Section Change Summary
Disclaimers Updated with the latest disclaimers.

Revision 1.9, September 2023

Section Change Summary
All Deleted all mentions of LPDD3 in below sections:
• General Description
• Overview
• DQS Grouping for DDR Memory
• Differential HSUL12D (Output Only)
• External Switching Characteristics
• Differential HSUL12D (Output Only)
• External Switching Characteristics
General Description • Updated below information in Table 1.1. CrossLink-NX Commercial/Industrial Family
Selection Guide:
• Updated the value of ADC Blocks from 2 to 1.
• Changed the title of the cell from D-PHY Quads (D-PHY Data Lanes) / Wide Range
(WR) GPIO (Top/Left/Right Banks) / High Performance (HP) GPIOs (Bottom Banks) to
Total I/O (Wide Range, High Performance, ADC4) (D-PHY Quads5, PCIe6 Lane).
• Updated the format of the values from 1(4)/15/24 to 45 (15, 24, 6) (1, 0).
• Added footnote 4, 5 and 6 for ADC and PCIe clarity as given below:
• Each ADC pin count reflects using dedicated complement pair and vRef.
• Each D-PHY quad consists of 4 D-PHY data lanes.
• Each PCIe lane consists of a Tx and Rx complement pair.
• Updated below information in Table 1.2. CrossLink-NX Automotive Family Selection
Guide:
• Changed the title of the cell from Wide Range D-PHY Quads (D-PHY Data Lanes) /
Wide Range (WR) GPIO (Top/Left/Right Banks) / High Performance (HP) GPIOs
(Bottom Banks) to Total I/O (Wide Range, High Performance, ADC4) (D-PHY Quads5,
PCIe6 Lane).
• Updated the format of the values from 2(8)/23/48 to 77 (23, 48, 6) (2, 0).
• Added footnote 4, 5 and 6 for ADC and PCIe clarity as given below:
• Each ADC pin count reflects using dedicated complement pair and vRef.
• Each D-PHY quad consists of 4 D-PHY data lanes.
• Each PCIe lane consists of a Tx and Rx complement pair.
DC and Switching Characteristics Updated the value of 32k × 32 True-Dual Port RAM using same clock, with Output Registers
for Commercial and Industrial from 340 to 157.183 in Table 3.31. Register-to-Register Performance.
DC and Switching Characteristics Updated the value of 32k × 32 True-Dual Port RAM using same clock, with Output Registers
for Automotive from 340 to 154.883 in Table 4.31. Register-to-Register Performance.
Pinout Information • Updated the value of Bank 0 of LIFCL-17 QFN72 under Pin Information from 11 to 10 in
CrossLink-NX Family section.
• Added signals PRxxx/EIO and PLxxx/EIO in Signal Descriptions section.
Supplemental Information Added links for CrossLink-NX, Lattice Radiant, and Lattice Insight web pages.

FPGA-DS-02049-2.1 165
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Data Sheet

Revision 1.8, March 2023

Section Change Summary
DC and Switching Characteristics Changed the Note 1.b information from Bank 3, Bank 4, and Bank 5 I/O can only mix into
for Commercial and Industrial banks with VCCIO higher than the pin standard, due to clamping diode on the pin in these
banks. Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 does not have this restriction
to Bank 3, Bank 4, and Bank 5 I/O can only mix into banks with VCCIO higher than or equal to
the pin standard, due to clamping diode on the pin in these banks. Bank 0, Bank 1, Bank 2,
Bank 6, and Bank 7 does not have this restriction in Table 3.13. sysI/O Recommended
Operating Conditions.

Revision 1.7, March 2023

Section Change Summary
Acronyms in This Document Deleted Acronym “MLDVS’ and its definition “Multipoint Low-Voltage Differential Signaling”
in Acronyms in This Document table.
Supplemental Information Added link for High Speed PCB Design Considerations (FPGA-TN-02178).
Technical Support Assistance Added Technical Support Assistance section.

Revision 1.6, January 2023

Section Change Summary
Architecture Adjustment in formatting to move Clocking Structure as sub-section under the Architecture
section.
DC and Switching Characteristics Updated the following in Table 3.33. External Switching Characteristics (VCC = 1.0 V):
for Commercial and Industrial • Added footnote for tSKEW_PRI and tSKEW_EDGE.
Updated fDATA_GDDRX4_MP in Soft D-PHY DDRX4 group to add packages.
DC and Switching Characteristics Updated the following in Table 4.33. External Switching Characteristics (VCC = 1.0 V):
for Automotive • Added footnote for tSKEW_PRI and tSKEW_EDGE.
• Updated fDATA_GDDRX4_MP in Soft D-PHY DDRX4 group to add packages.

Revision 1.5, September 2022

Section Change Summary
All Minor changes in formatting, including removing product name from heading, figure, and
table names.
General Description • Updated the following in Table 1.1. CrossLink-NX Commercial/Industrial Family Selection
Guide:
• Changed Distributed RAM for LIFCL-17 and LIFCL-40 to 108 kb and 252 kb,
respectively.
• Changed HP GPIO for LIFCL-40 in 256 caBGA, 289 csBGA, and 400 caBGA packages
from 74 to 148.
• Corrected typo from WLSCP to WLCSP.
• Updated table note 3 to specify available speed grade for Commercial/Industrial.
• Updated table note 3 to specify available speed grade for Automotive in Table 1.2.
CrossLink-NX Automotive Family Selection Guide.
Architecture • Updated Analog Interface section content to specify the speed grades the feature is
available.
• Updated the following in SGMII Tx/Rx section:
• Changed section name from SGMII Clock Data Recovery to SGMII Tx/Rx.
• Updated content to specify that the device utilizes different components/resources
for the SGMII transmit and receive paths.
• Updated sysMEM Memory Block section content to specify the speed grades the ECC
engine is available.

166 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Section Change Summary

DC and Switching Characteristics • Added Table 3.17. VIN Maximum Overshoot/Undershoot Allowance – Wide Range and
for Commercial and Industrial Table 3.18. VIN Maximum Overshoot/Undershoot Allowance – High Performance.
• Updated the following in Table 3.29. Maximum I/O Buffer Speed:
• Changed max data rate (for both Maximum sysI/O Input and Output Frequency) of
caBGA256, csBGA289, and caBGA400 to 1500.
• Updated footnote reference in the Differential groups.
• Updated DSP functions in Table 3.31. Register-to-Register Performance.
• Updated the following in Table 3.34. sysCLOCK PLL Timing (VCC = 1.0 V) –
Commercial/Industrial:
• Raised minimum input clock frequency from 10 to 18 MHz.
• Raised minimum phase detector input frequency from 10 to 18 MHz; removed table
note and table note reference.
• Corrected tPH footnote.
• Removed and Added conditions for the tOPJIT parameter to accurately reflect PLL
jitter performance.
• Updated table note 1 in Table 3.37. ADC Specifications to specify available speed grade
for ADC.
• Updated table note 2 in Table 3.39. DTR Specifications to specify available speed grade
for DTR.
• Updated the following in SGMII Characteristics section:
• Updated header and sub section names.
• Updated table name to Table 3.47 SGMII and added table note 2 to specify SGMII is
not supported on 72-pin packages.
DC and Switching Characteristics • Added Table 4.17. VIN Maximum Overshoot/Undershoot Allowance – Wide Range and
for Automotive Table 4.18. VIN Maximum Overshoot/Undershoot Allowance – High Performance.
• Updated Table 4.29. Maximum I/O Buffer Speed:
• Changed max data rate (for both Maximum sysI/O Input and Output Frequency) of
caBGA256, csBGA289, and caBGA400 to 1500.
• Updated footnote reference in the Differential groups.
• Updated DSP functions in Table 4.31. Register-to-Register Performance.
• Updated Table 4.33. External Switching Characteristics (VCC = 1.0 V) to remove -8 Auto
speed grade.
• Updated the following in Table 4.34. sysCLOCK PLL Timing (VCC = 1.0 V) – Automotive:
• Raised minimum input clock frequency from 10 to 18 MHz.
• Raised minimum phase detector input frequency from 10 to 18 MHz; removed table
note and table note reference.
• Corrected tPH footnote.
• Removed and Added conditions for the tOPJIT parameter to accurately reflect PLL
jitter performance.
• Added table note 3 in Table 4.37. ADC Specifications to specify available speed grade for
ADC.
• Updated table note 2 in Table 4.39. DTR Specifications to specify available speed grade
for DTR.
• Added SGMII Characteristics section.
Pinout Information • Updated table note 2 in Signal Descriptions to specify available speed grade for ADC.
• Updated the following in Pin Information Summary:
• Updated Bank 5 values for 72QFN and 121csfBGA (LIFCL-17 and LIFCL-40), 72WLCSP
and 256caBGA (LIFCL-17).
• Updated table note 1 to specify available speed grade for ADC.

FPGA-DS-02049-2.1 167
CrossLink-NX Family
Data Sheet

Revision 1.4, June 2022

Section Change Summary
DC and Switching Characteristics Updated max value of ZOS in Table 3.22. SLVS Output DC Characteristics.
for Commercial and Industrial
DC and Switching Characteristics • Updated LVDS and subLVDS VCCIO (Input) value in Table 4.13. sysI/O Recommended
for Automotive Operating Conditions.
• Updated max value of ZOS in Table 4.22. SLVS Output DC Characteristics.
Pinout Information • Added table note 3 and table note reference to VCCADC18 in 72WLCSP and 121csfBGA
(LIFLCL-17 and LIFCL-40); Added table note and reference to table note for Dedicated
ADCI/O Pins; Adjustment in formatting to remove superscripts for Shared Configuration
Pins, Shared User GPIO Pins, and Shared CLOCK Pins in Signal Descriptions.
• Added table note 3 and table note reference to VCCADC18; Updated 256caBGA, 289csBGA,
and 400caBGA values for Dedicated ADC channels, Dedicated ADC reference, and Total
Dedicated Pins; Updated 256caBGA and 289csBGA values for Bank 3 Shared Comparator
Channels and add table note 2 in Pin Information Summary.

Revision 1.3, March 2022

Section Change Summary
All Adjustments in formatting and wording across the document, including changing the
reference document names from Usage Guide to User Guide and changing table footnote
with asterisk (*) to one (1).
General Description • Updated content, including rewording some bullet points in the Features section.
• Added note for ECC in Flexible Memory Resources bullet point and Dual ADC bullet
point.
• Updated Table 1.1. CrossLink-NX Commercial/Industrial Family Selection Guide and
Table 1.2. CrossLink-NX Automotive Family Selection Guide to add table note 3 for ADC
block.
Architecture • Updated content, including rewording some information in the following sections:
• Overview
• PFU Blocks
• Routing
• Programmable I/O (PIO)
• Programmable I/O Cell (PIC)
• Tri-state Register Block
• DDR Memory Support
• sysI/O Buffer
• Analog Interface
• Device Configuration
• Single Event Upset (SEU) Handling
• On-Chip Oscillator
• User I²C IP
• MIPI D-PHY Blocks
• Peripheral Component Interconnect Express (PCIe)
• Added information on select speed grades in sysMEM Memory Block and Analog
Interface.
• Updated note reference in Table 2.2. Slice Signal Descriptions.
• Updated TD[1:0] parameter name to T[1:0] in Table 2.8. Tri-state Block Port
Description.
• Updated Figure 2.6. General Purpose PLL Diagram to correct shading in CLKOS4 and
CLKOS5.
• Updated DELAY CODE to DELAYCODE_I and DELAYCODE_O in Figure 2.26. DQS Control
and Delay Block (DQSBUF).

168 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Section Change Summary

DC and Switching Characteristics • Removed “Over Recommended Operating Conditions” info across the section.
for Commercial and Industrial • Added this info in the section: All specifications in this Chapter are characterized within
recommended operating conditions unless otherwise specified.
• Added Commercial and Industrial grade information in ESD Performance.
• Updated TA max value in Table 3.1. Absolute Maximum Ratings.
• Updated table note 2 in Table 3.2. Recommended Operating Conditions.
• Updated table note 2 in Table 3.6. Hot Socketing Specifications for GPIO.
• Updated unit in Table 3.9. Capacitors – Wide Range, Table 3.10. Capacitors – High
Performance, Table 3.30. LMMI FMAX Summary, and Table 3.33. Internal Oscillators
(VCC = 1.0 V).
• Updated LVDS and subLVDS VCCIO (Input) value in Table 3.13. sysI/O Recommended
Operating Conditions.
• Updated VIH, VIL, IOL, IOH values and table notes in Table 3.14. sysI/O DC Electrical
Characteristics – Wide Range I/O and Table 3.15. sysI/O DC Electrical Characteristics –
High Performance I/O.
• Updated information for VCCAUX in LVDS.
• Changed VINN to VINM in table note 2 and added table note 3 in Table 3.17. LVDS DC
Electrical Characteristics1.
• Added table note for VICM in SubLVDS (Input Only).
• Updated min and max value of ZOS in Table 3.24. Soft D-PHY Output Timing and Levels.
• Updated max value of HSTL15 in Table 3.27. CrossLink-NX Maximum I/O Buffer Speed.
• Added reference to table note 2 for 32 k x 32 k True-Dual Port RAM in Table 3.29.
Register-to-Register Performance.
• Updated Generic DDRX1 group to add WRIO and HPIO in Table 3.31. CrossLink-NX
External Switching Characteristics (VCC = 1.0 V).
• Updated Min and Max values, added reference for table note 2 in cycles unit, and
added table notes for ADC in Table 3.35. ADC Specifications.
• Added table note for Comparator in Table 3.36. Comparator Specifications1.
• Added table note for ADC in Table 3.37. DTR Specifications.
• Updated VTERM-EN description, min value of VIDTH (1.5 Gbps), and max value of VIDTL
• (1.5 Gbps) in Table 3.38. Hardened D-PHY Input Timing and Levels.
• Updated VTX-DE-RATIO-3.5dB description and ZRX-HIGH-IMP-DC min value in Table 3.43. PCIe (2.5
Gbps).
• Updated VTX-DE-RATIO-3.5dB and VTX-DE-RATIO-6dB description in Table 3.44. PCIe (5 Gbps).
• Updated row name to Slave SPI/I2C/I3C POR, description of tMSPI_INM and tFIO_EN, max
value for tFIO_EN; Changed tDONE_HIGH to tWAKEUP_DONE_HIGH in Wake-Up Timing row, added
references table notes, and added table note 2 and 3 in Table 3.46. CrossLink-NX
sysCONFIG Port Timing Specifications.
• Updated Figure 3.2. LVDS25E Output Termination Example, Figure 3.19. Slave SPI
Configuration Timing, Figure 3.20. I2C /I3C Configuration Timing, Figure 3.21. Controller
SPI Wake-Up Timing, and Figure 3.22. Slave SPI/I2C/I3C Wake-Up Timing.

FPGA-DS-02049-2.1 169
CrossLink-NX Family
Data Sheet

Section Change Summary

DC and Switching Characteristics • Removed “Over Recommended Operating Conditions” info across the section.
for Automotive • Added this info in the section: All specifications in this Chapter are characterized within
recommended operating conditions unless otherwise specified.
• Added Automotive grade information in ESD Performance.
• Updated TA max value in Table 4.1. Absolute Maximum Ratings.
• Updated table note 2 in Table 4.6. Hot Socketing Specifications for GPIO.
• Updated unit in Table 4.9. Capacitors – Wide Range, Table 4.10. Capacitors – High
Performance, Table 4.30. LMMI FMAX Summary, and Table 4.33. Internal Oscillators
(VCC = 1.0 V).
• Updated VIH, VIL, IOL, IOH values and table notes in Table 4.14. sysI/O DC Electrical
Characteristics – Wide Range I/O and Table 4.15. sysI/O DC Electrical Characteristics –
High Performance I/O3.
• Updated min and max value of ZOS and min value of VOH in Table 4.24. Soft D-PHY
Output Timing and Levels.
• Updated Generic DDRX1 group to add WRIO and HPIO in Table 4.31. CrossLink-NX
External Switching Characteristics (VCC = 1.0 V).
• Updated Min and Max values, added reference for table note 2 in cycles unit, and
added table notes for ADC in Table 4.35. ADC Specifications.
• Added table notes in Table 4.37. DTR Specifications1.
• Updated VTERM-EN description, min value of VIDTH (1.5 Gbps), and max value of VIDTL
(1.5 Gbps) in Table 4.38. Hardened D-PHY Input Timing and Levels.
• Updated VTX-DE-RATIO-3.5dB description and ZRX-HIGH-IMP-DC min value in Table 4.43. PCIe (2.5
Gbps).
• Updated VTX-DE-RATIO-3.5dB and VTX-DE-RATIO-6dB description in Table 4.44. PCIe (5 Gbps).
• Updated row name to Slave SPI/I2C/I3C POR, description of tMSPI_INM and tFIO_EN,
max value for tFIO_EN; Changed tDONE_HIGH to tWAKEUP_DONE_HIGH in Wake-Up Timing row,
added references table notes, and added table note 2 and 3 in Table 4.45. CrossLink-NX
sysCONFIG Port Timing Specifications.
• Updated Figure 4.2. LVDS25E Output Termination Example, Figure 4.3. SubLVDS Input
Interface, Figure 4.4. SubLVDS Output Interface, Figure 4.5. SLVS Interface, Figure 4.21.
Controller SPI Wake-Up Timing, and Figure 4.22. Slave SPI/I2C/I3C Wake-Up Timing.
Pinout Information • Updated description for ADC_REF and ADC_DP/N in Signal Descriptions.
• Added table note and reference for Dedicated ADC Channels and Reference in
CrossLink-NX Family.
Ordering Information Added footnote for speed in LIFCL-40 and LIFCL-17 diagrams.

Revision 1.2, September 2021

Section Change Summary
All Changed 17 k and 39 k to 17k and 39k across the document.
Architecture • Changed Successive Approximation Resistor/Capacitor reference to Successive
Approximation Register in Analog to Digital Converters section.
• Updated SGMII Clock Data Recovery (CDR) section to add information that SGMII CDR is
only available on commercial and industrial grade devices.
DC and Switching Characteristics • Updated Figure 3.3 to move resistor to the on-chip side.
for Commercial and Industrial • Updated Figure 3.14 and Figure 3.15 to move location of power rail and tICFG parameter.
• Updated SubLVDSE/SubLVDSEH (Output Only) section content to change Bank 5 and
Bank 6 to Bank 6 and Bank 7.
• Removed table note 8 reference in Table 3.27.
• Updated Min and Max value of fCLKHF in Table 3.33.
• Updated DTRRANGE max value, change values, and added note for external voltage
reference in DTRACCURACY in Table 3.37.
• Updated table note and test conditions of JTOL_Dj and JTOL_Tj in Table 3.45.

170 FPGA-DS-02049-2.1
CrossLink-NX Family
Data Sheet

Section Change Summary

• Added new row for tICFG_POR and updated max and unit for tICFG, unit of tVMC, typ of
fMCLK_DEF, max value of tDONE_LOW, and data in the I2C/I3C section in Table 3.46.
• Updated table note and data for tBTRF in Table 3.47.Table 3.39
DC and Switching Characteristics • Added Power Supply Ramp Rates (section 4.3) to Switching Test Conditions (section
for Automotive 4.29) to complete the CrossLink-NX Automotive data for production release.
• Updated Table 4.2 to change tAUTO to tJAUTO.

Revision 1.1, July 2021

Section Change Summary
All • Corrected units and measurements across the document.
• Minor formatting across the document.
• Changed 17K and 39K to 17 k and 39 k across the document.
Architecture • Updated Programmable I/O (PIO) content to remove reference to CrossLink-NX
regarding PIC.
• Updated Programmable I/O Cell (PIC) to provide additional information on PIC.
• Updated Figure 2.17 and Figure 2.18.
• Added Trace ID section.
• Updated Cryptographic Engine content.
Introduction Minor formatting in Features section.
DC and Switching Characteristics • Updated note in Table 3.6 and Table 3.27.
for Commercial and Industrial • Added note 3 in Table 3.14 and Table 3.15.
• Added three rows for fSSC in Table 3.32.
• Changed EBR Output Registers to Output Registers for 32k × 32 True-Dual Large
Memory Functions in Table 3.29.
• Updated max value for tOPJIT Output Clock Phase Jitter and added rows for fSSC_MOD
in Table 3.32.
• Updated Table 3.35 to fill up empty cells.
Pinout Summary • Updated table in Signal Descriptions to add PLLCK in PBxxx/LRC_GPLL, PBxxx/LLC_GPLL,
and PBxxx/ULC_GPLL.
• Updated table in CrossLink-NX Family to re-arrange pinout package from lowest to
highest.
References Added reference documents.

Revision 1.0, April 2021

Section Change Summary
All Production release

FPGA-DS-02049-2.1 171
www.latticesemi.com

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