Department of Computer Science

Panjab University, Chandigarh

Subject: Computer Organisation (Dr R.K. Singla)

· These notes have 8 pages, including this cover sheet.

· There are 4 questions.

 Name: _____________________

Question 1
Multiple Choice and Short Answer

For each multiple choice question, circle your answer. For the short answer problems, please
justify your answers. Responses of ‘yes’ or ‘no’ without an explanation will be worth 0
points.

i. In binary arithmetic, if a given binary number is a multiple of 4, dividing the

number by 4 is equivalent to sliding all of the bits:

a. to the left by two bits

b. to the left by four bits
c. to the right by two bits
d. to the right by four bits

ii. You are given the 8-bit binary number 1101 0011. Which of the following
matches the proper binary formats to the corresponding decimal translation?

Unsigned Signed magnitude Signed 1’s complement Signed 2’s complement

a. 211 -83 -44 -45
b. 211 -211 -83 -84
c. 211 -83 -45 -44
d. 211 -83 44 45

iii. When reducing Boolean expressions, we have used both Boolean algebra and
Karnaugh Maps.

A) Describe an advantage of using K-maps instead of Boolean algebra.

Solution: K-maps are simpler and easier to use than Boolean algrebra, they often require
less time, and they are less prone to errors.

B) Describe an advantage of using Boolean algebra instead of K-maps.

Solution: It is difficult to find some gates (like XOR) in K-maps. Boolean algebra can
find a different form of solution (minimum literals instead of MSP). Boolean algebra
scales more easily for > 4 variables.

2
 Name: _____________________

iv. Look at the following groupings of the same function with don’t cares:

y y
0 0 0 0 0 0 0 0
X X 1 1 X X 1 1
x x
0 X X X 0 X X X
w w
0 1 1 0 0 1 1 0
z z
i. ii.

A) Derive the two MSP equations based on the groupings in i. and ii.

Solution:
i. w’x + wz
ii. xy + wz

B) Are the two equations from A) logically equivalent? Justify your answer.

Solution: The equations x’w + wz and xy + wz are NOT logically equivalent. The
easiest way to show this is to look at the input (w,x,y,z) = 0100. In i., this gives 11 + 00
= 1. In ii., it gives 10 + 00 = 0. Since the equations give different outputs for the same
input, they are not logically equivalent.

You can also show this by constructing truth tables for each equation.

3
 Name: _____________________

Question 2
Circuit Analysis

Consider the following circuit:

d
g
e

a. Derive the truth table for the function H(A,B,C). You may opt to use the
intermediate steps (d,e,f,g), but doing so is not required.

Solution: Using DeMorgan’s law, we can derive the following equations:

d = A’B, e = ABC’, f = B + C, g = d’e’, and H = g’ + f’

Inputs Intermediate Steps Output

A B C d e f g H(A,B,C)
0 0 0 0 0 0 1 1
0 0 1 0 0 1 1 0
0 1 0 1 0 1 0 1
0 1 1 1 0 1 0 1
1 0 0 0 0 0 1 1
1 0 1 0 0 1 1 0
1 1 0 0 1 1 0 1
1 1 1 0 0 1 1 0

b. Express H(A,B,C) as a sum of minterms, based on your truth table from a).

Solution: H(A,B,C) = Sm(0,2,3,4,6)

4
 Name: _____________________

Question 2 (Cont’d.)

c. Use a K-map to derive the minimum sum-of-products form of H(A,B,C).

Then, draw the resulting circuit.

Solution:

B
1 0 1 1
A 1 0 0 1
C

H(A,B,C) = A’B + C’

5
 Name: _____________________

Question 3
Signed 2’s Complement and Subtraction

a. Assume that the 3-bit numbers listed below are in signed magnitude
format. Translate them to signed two’s complement form.

Signed Signed 2’s

Magnitude Complement
000 000
001 001
010 010
011 011
100 000 or –
101 111
110 110
111 101

b. For 3-bit binary numbers, what value can be represented in signed two’s
complement form that can’t be represented in signed magnitude form? Explain the
reason for this briefly.

Solution: (-4) can be represented in signed two’s complement, but it can’t be represented
in signed magnitude form. Here are some of the acceptable explanations:
· The range of 3-bit signed two’s complement numbers is –4 to 3, while the
range for signed magnitude is –3 to 3.
· Signed magnitude has two forms for 0, 000 (0) and 100 (-0). Because of this,
it can’t represent the value represented by 100 in signed 2’s complement,
which equals -4.
· In 3-bit signed magnitude, the first bit is used only for the sign, while the
remaining two bits determine the value. Three bits are needed to represent the
magnitude of –4, which is 4. This is why –4 can’t be represented in 3-bit
signed magnitude.

6
 Name: _____________________

Below is an attempt to make a circuit that will perform one of two

operations on a 4-bit, signed two’s complement number X. When S is 0, then
X should be incremented by one. When S is 1, X should be decremented by
one. The result is passed through the adder and outputted as G.

This implementation is incorrect, however. For both possible values of S, state what
value G is, in terms of an arithmetic operation on X, assuming that there is no
overflow.

Solution: When S = 0, A = 0001, so G=X+1

When S = 1, A = 1110 = -2, so G=X-2

c. There are two ways that this circuit could be fixed by only changing one of the
adder inputs. Briefly state what inputs should be changed, and to what. (6 points
for one solution, 4 points for the second)

Solution:
· A0 could be changed to permanently be 1. So when S = 0, A = 0001,
while when S = 1, A = 1111 = -1, which produces the effect we want.
· CI could be changed to S. When S = 0, G = X + 0001 + 0 = X + 1. When
S = 1, G = X + 1110 (-2) + 1 = X + 1111 (-1) = X – 1.

7
 Name: _____________________

Question 4
Demultiplexer

A demultiplexer is a circuit that performs the inverse function of a multiplexer. In other

words, a 1-to-2n demultiplexer receives data from one line, and transmits it to one of 2n
possible output lines. n selection lines are used to choose which output line receives the data.
All other output lines receive a zero.

Your task is to design a 1-to-8 demultiplexer from scratch. You are permitted to use any
gates that we have used and any larger parts we have studied, such as decoders and
multiplexers. You can use block symbols for decoders or multiplexers, but make sure inputs
and outputs are clearly labeled. Output lines on the demultiplexer should be labeled D0-D7,
and selection inputs should be labeled S0-S2. The data input should be labeled as X.

Show all your work, and explain why your circuit implements a demultiplexer.

Solution: The two key parts to solving this were, first, to see that the demultiplexer functions
in a similar fashion to a decoder, which only transmits a 1 to the selected output and 0 to
every other output, and second, to make it so that the input X was transmitted to the
appropriate output instead of a 1. Two possible solutions are shown below.