Microprocessor
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A microcontroller at-least should consist of:
a) RAM, ROM, I/O ports and timers
b) CPU, RAM, I/O ports and timers
c) CPU, RAM, ROM, I/O ports and timers
d) CPU, ROM, I/O ports and timers
Answer: c
Explanation: A microcontroller at-least consists of a processor as its CPU with RAM, ROM, I/O ports and timers. It
may contain some additional peripherals like ADC, PWM, etc.
2. Unlike microprocessors, microcontrollers make use of batteries because they have:
a) high power dissipation
b) low power consumption
c) low voltage consumption
d) low current consumption
Answer: b
Explanation: Micro Controllers are made by using the concept of VLSI technology. So here, CMOS based logic gate
s are coupled together by this technique that consumes low power.
3. What is the order decided by a processor or the CPU of a controller to execute an instruction?
a) decode,fetch,execute
b) execute,fetch,decode
c) fetch,execute,decode
d) fetch,decode,execute
Answer: d
Explanation: First instruction is fetched from Program Memory. After fetching, instruction is decoded to generate co
ntrol signals to perform the intended task. After decoding, instruction is executed and the complete intended task of t
hat particular instruction.
4. If we say microcontroller is 8-bit then here 8-bit denotes size of:
a) Data Bus
b) ALU
c) Control Bus
d) Address Bus
Answer: b
Explanation: If we say a microcontroller is 8-bit it means that it is capable of processing 8-bit data at a time. Data pr
ocessing is the task of ALU and if ALU is able to process 8-bit data then the data bus should be 8-bit wide. In most
books it tells that size of data bus but to be precise it is the size of ALU because in Harvard Architecture there are tw
o sets of data bus which can be of same size but it is not mandatory.
5. How are the performance and the computer capability affected by increasing its internal bus width?
a) it increases and turns better
b) it decreases
c) remains the same
d) internal bus width doesn’t affect the performance in any way
Answer: a
Explanation: As the bus width increases, the number of bits carried by bus at a time increases as a result of which th
e total performance and computer capability increases.
6. Abbreviate CISC and RISC.
a) Complete Instruction Set Computer, Reduced Instruction Set Computer
b) Complex Instruction Set Computer, Reduced Instruction Set Computer
c) Complex Instruction Set Computer, Reliable Instruction Set Computer
d) Complete Instruction Set Computer, Reliable Instruction Set Computer
Answer: b
Explanation: CISC means Complete Instruction Set Computer because in this a microcontroller has an instruction se
t that supports many addressing modes for the arithmetic and logical instructions, data transfer and memory accesses
instructions. RISC means Reduced Instruction Set Computer because here a microcontroller has an instruction set t
hat supports fewer addressing modes for the arithmetic and logical instructions and for data transfer instructions.
7. Give the names of the buses present in a controller for transferring data from one place to another?
a) data bus, address bus
b) data bus
c) data bus, address bus, control bus
d) address bus
Answer: c
Explanation: There are 3 buses present in a microcontroller they are data bus (for carrying data from one place to an
other), address bus (for carrying the address to which the data will flow) and the control bus (which tells the controll
er to execute which type of work at that address may be it read or write operation).
8. What is the file extension that is loaded in a microcontroller for executing any instruction?
a) .doc
b) .c
c) .txt
d) .hex
Answer: d
Explanation: Microcontrollers are loaded with .hex extension as they understand the language of 0’s and 1’s only.
9. What is the most appropriate criterion for choosing the right microcontroller of our choice?
a) speed
b) availability
c) ease with the product
d) all of the mentioned
Answer: d
Explanation: For choosing the right microcontroller for our product we must consider its speed so that the instructio
ns may be executed in the least possible time. It also depends on the availability so that the particular product may b
e available in our neighboring regions or market in our need. It also depends on the compatibility with the product s
o that the best results may be obtained.
10. Why microcontrollers are not called general purpose computers?
a) because they have built in RAM and ROM
b) because they design to perform dedicated task
c) because they are cheap
d) because they consume low power
Answer: b
Explanation: Microcontrollers are designed to perform dedicated tasks. While designing general purpose computers
end use is not known to designers.
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1. How many types of architectures are available, for designing a device that is able to work on its own?
a) 3
b) 2
c) 1
d) 4
Answer: b
Explanation: There are basically two main types of architectures present, they are Von Neumann and Harvard archit
ectures.
2. Which architecture is followed by general purpose microprocessors?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: b
Explanation: General purpose microprocessors make use of Von Neumann architecture as here a simpler design is of
fered.
3. Which architecture involves both the volatile and the non volatile memory?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a
Explanation: In Harvard architecture, both the volatile and the non volatile memories are involved. This is done to in
crease its efficiency as both the memories are being used over here.
4. Which architecture provides separate buses for program and data memory?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a
Explanation: Harvard Architecture provides separated buses for data and program memory to fetch program and dat
a simultaneously. By doing this access time is reduced and hence performance is increased.
5. Which microcontroller doesn’t match with its architecture below?
a) Microchip PIC- Harvard
b) MSP430- Harvard
c) ARM7- Von Neumann
d) ARM9- Harvard
Answer: b
Explanation: MSP430 supports Von Neumann architecture.
6. Harvard architecture has _____________
a) dedicated buses for data and program memory
b) pipeline technique
c) complex architecture
d) all of the mentioned
Answer: d
Explanation: Harvard Architecture has dedicated buses for data and program memory and pipeline technique becaus
e of this architecture is complex.
7. Which out of the following supports Harvard architecture?
a) ARM7
b) Pentium
c) SHARC
d) All of the mentioned
Answer: c
Explanation: SHARC supports harvard architecture for signal processing in DSP.
8. Why most of the DSPs use Harvard architecture?
a) they provide greater bandwidth
b) they provide more predictable bandwidth
c) they provide greater bandwidth & also more predictable bandwidth
d) none of the mentioned
Answer: c
Explanation: Most of the DSPs use harvard architecture because they provide a wider predictable bandwidth.
9. Which of the following supports CISC as well as Harvard architecture?
a) ARM7
b) ARM9
c) SHARC
d) None of the mentioned
Answer: c
Explanation: SHARC supports both the CISC and the Harvard architecture.
10. Which of the two architecture saves memory?
a) Harvard
b) Von Neumann
c) Harvard & Von Neumann
d) None of the mentioned
Answer: b
Explanation: As only one memory is present in the Von Neumann architecture so it saves a lot of memory.
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1. 8051 microcontrollers are manufactured by which of the following companies?
a) Atmel
b) Philips
c) Intel
d) All of the mentioned
Answer: d
Explanation: 8051 microcontrollers are manufactured by Intel, Atmel, Philips/Signetics, Infineon, Dallas Semi/Maxi
m.
2. AT89C2051 has RAM of:
a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
Answer: a
Explanation: It has 128 bytes of RAM in it.
3. 8051 series has how many 16 bit registers?
a) 2
b) 3
c) 1
d) 0
Answer: a
Explanation: It has two 16 bit registers DPTR and PC.
4. When 8051 wakes up then 0x00 is loaded to which register?
a) PSW
b) SP
c) PC
d) None of the mentioned
Answer: c
Explanation: When 8051 wakes up, Program Counter (P
c) loaded with 0000H. Because of this in 8051 first opcode is stored in ROM address at 0000H.
5. When the microcontroller executes some arithmetic operations, then the flag bits of which register are affected?
a) PSW
b) SP
c) DPTR
d) PC
Answer: a
Explanation: It stands for program status word. It consists of carry, auxiliary carry, overflow, parity, register bank se
lect bits etc which are affected during such operations.
6. How are the status of the carry, auxiliary carry and parity flag affected if the write instruction
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
Answer: b
Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so CY and AC are set to 1. In t
he result, the number of 1’s present are even so parity flag is set to zero.
7. How are the bits of the register PSW affected if we select Bank2 of 8051?
a) PSW.5=0 and PSW.4=1
b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
Answer: d
Explanation: Bits of PSW register are CY, AC, F0, RS1, RS0, OV, -, P so for selecting bank2 RS1=1 and RS0=0 wh
ich are fourth and third bit of the register respectively.
8. If we push data onto the stack then the stack pointer
a) increases with every push
b) decreases with every push
c) increases & decreases with every push
d) none of the mentioned
Answer: a
Explanation: If we push elements onto the stack then the stack pointer increases with every push of element.
9. On power up, the 8051 uses which RAM locations for register R0- R7
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
Answer: b
Explanation: On power up register bank 0 is selected which has memory address from 00H-07H.
10. How many bytes of bit addressable memory is present in 8051 based microcontrollers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
Answer: c
Explanation: 8051 microcontrollers have 16 bytes of bit addressable memory.
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1. “DJNZ R0, label” is ________ byte instruction.
a) 2
b) 3
c) 1
d) Can’t be determined
Answer: a
Explanation: DJNZ is 2-byte instruction. This means jump can be of -128 to +127 locations with respect to PC. Here
-128 means upward or backward jump and +127 means downward or forward jump.
2. JZ, JNZ, instructions checked content of _______ register.
a) DPTR
b) B
c) A
d) PSW
Answer: c
Explanation: JZ and JNZ instructions checked the content of A register and if condition was satisfied or true then ju
mp to target address.
3. Calculate the jump code for again and here if code starts at 0000H
a) F3,02
b) F9,01
c) E9,01
d) E3,02
Answer: c
Explanation: Loop address is calculated by subtracting destination address and the address next to the source address
.
4. When the call instruction is executed the topmost element of stack comes out to be
a) the address where stack pointer starts
b) the address next to the call instruction
c) address of the call instruction
d) next address of the stack pointer
Answer: b
Explanation: The topmost element of the stack is the address of the instruction next to the call instruction so that wh
en RET is executed then PC is filled with that address and so the pointer moves to the main program and continue w
ith its routine task.
5. LCALL instruction takes
a) 2 bytes
b) 4 bytes
c) 3 bytes
d) 1 byte
Answer: c
Explanation: LCALL instruction moves the pointer to a 16 bit address so it is a 3 byte instruction.
6. Are PUSH and POP instructions are a type of CALL instructions?
a) yes
b) no
c) none of the mentioned
d) cant be determined
Answer: b
Explanation: PUSH and POP instructions are not CALL instructions because in POP and PUSH instructions the poi
nter does not move to any location specified by its address which is the fundamental of CALL instruction, so it is no
t a type of CALL instruction.
7. What is the time taken by one machine cycle if crystal frequency is 20MHz?
a) 1.085 micro seconds
b) 0.60 micro seconds
c) 0.75 micro seconds
d) 1 micro seconds
Answer: b
Explanation: Time taken by one machine cycle is calculated by the inverse of a (crystal frequency) /12
8. Find the number of times the following loop will be executed
a) 100
b) 200
c) 20000
d) 2000
Answer: c
Explanation: It will be executed 200*100 times.
9. What is the meaning of the instruction MOV A,05H?
a) data 05H is stored in the accumulator
b) fifth bit of accumulator is set to one
c) address 05H is stored in the accumulator
d) none of the mentioned
Answer: c
Explanation: If we need to store the address in the accumulator, then directly the address is moved to it unlikely of u
sing # used for storing data in any register.
10. Do the two instructions mean the same?
a) yes
b) no
c) cant be determined
d) yes and the second one is preferred
Answer: b
Explanation: In the first statement, when the decrements approach zero then the jump moves back and in the second
statement, when the result after decrements is not zero, then it jumps back.
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1. To initialize any port as an output port what value is to be given to it?
a) 0xFF
b) 0x00
c) 0x01
d) A port is by default an output port
Answer: d
Explanation: In 8051, a port is initialized by default in its output mode no need to pass any value to it.
2. Which out of the four ports of 8051 needs a pull-up resistor for using it is as an input or an output port?
a) PORT 0
b) PORT 1
c) PORT 2
d) PORT 3
Answer: a
Explanation: These pins are the open drain pins of the controller which means it needs a pull-up resistor for using it
as an input or an output ports.
3. Which of the ports act as the 16 bit address lines for transferring data through it?
a) PORT 0 and PORT 1
b) PORT 1 and PORT 2
c) PORT 0 and PORT 2
d) PORT 1 and PORT 3
Answer: c
Explanation: PORT 0 and PORT 2 are used as the 16 bit address lines where PORT0 act as lower bit address lines a
nd PORT 2 as higher bit address lines.
4. Which of the following registers are not bit addressable?
a) SCON
b) PCON
c) A
d) PSW
Answer: b
Explanation: PCON register is not a bit addressable register.
5. Which instruction is used to check the status of a single bit?
a) MOV A,P0
b) ADD A,#05H
c) JNB PO.0, label
d) CLR P0.05H
Answer: b
Explanation: JNB which stands for Jump if no bit checks the status of the bit P0.0 and jumps if the bit is 0.
6. Which addressing mode is used in pushing or popping any element on or from the stack?
a) immediate
b) direct
c) indirect
d) register
Answer: c
Explanation: If we want to push or pop any element on or from the stack then direct addressing mode has to be used
in it, as the other way is not accepted.
7. Which operator is the most important while assigning any instruction as register indirect instruction?
a) $
b) #
c) @
d) &
Answer: b
Explanation: In register, indirect mode data is copied at that location where R0 or R1 are present, so @ operator is u
sed ex. MOV @R0,A
8. What is the advantage of register indirect addressing mode?
a) it makes use of registers R0 and R1
b) it uses the data dynamically
c) it makes use of operator @
d) it is easy
Answer: b
Explanation: Register indirect addressing mode is useful if a series of data is to be assigned to that address, with the
help of this quality the number of instructions decreases as a result of which performance increases.
9. Which of the following comes under the indexed addressing mode?
a) MOVX A, @DPTR
b) MOVC @A+DPTR,A
c) MOV A,R0
d) MOV @R0,A
Answer: b
Explanation: Indexed addressing mode stands for that instruction where the bits of the accumulator is also indexed w
ith the 16 bit registers.
PSST! You better watch out, something's buggy above.
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1. When we add two numbers the destination address must always be.
a) some immediate data
b) any register
c) accumulator
d) memory
Answer: c
Explanation: For addition purposes, the destination address must always be an accumulator. Example- ADD A,R0;
ADD A, @R1; ADD A,@ DPTR
2. DAA command adds 6 to the nibble if:
a) CY and AC are necessarily 1
b) either CY or AC is 1
c) no relation with CY or AC
d) CY is 1
Answer: b
Explanation: DAA command adds 6 to the nibble if any of the nibbles becomes greater than 9.
3. If SUBB A,R4 is executed, then actually what operation is being applied?
a) R4+A
b) R4-A
c) A-R4
d) R4+A
Answer: c
Explanation: SUBB command subtracts with borrow the contents of an accumulator with that of the register or some
immediate value. So A-R4 is being executed.
4. A valid division instruction always makes:
a) CY=0,AC=1
b) CY=1,AC=1
c) CY=0,AC=0
d) no relation with AC and CY
Answer: c
Explanation: When we divide two numbers then AC and CY become zero.
5. In 8 bit signed number operations, OV flag is set to 1 if:
a) a carry is generated from D7 bit
b) a carry is generated from D3 bit
c) a carry is generated from D7 or D3 bit
d) a carry is generated from D7 or D6 bit
Answer: d
Explanation: In 8 bit operations, if a carry is generated from D6 or D7 bit, then OV flag is set to 1.
6. In unsigned number addition, the status of which bit is important?
a) OV
b) CY
c) AC
d) PSW
Answer: b
Explanation: If unsigned numbers operations are involved, then the status of CY flag is important and in signed num
ber operation the status of OV flag is important.
7. Which instructions have no effect on the flags of PSW?
a) ANL
b) ORL
c) XRL
d) All of the mentioned
Answer: d
Explanation: These instructions are the arithmetic operations and the flags are affected by the data copy instructions,
so all these instructions don’t affect the bits of the flag.
8. ANL instruction is used _______
a) to AND the contents of the two registers
b) to mask the status of the bits
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: ANL instruction is used to AND the contents of the two registers and is also used to mask the status of
the bits of the register.
9. CJNE instruction makes _______
a) the pointer to jump if the values of the destination and the source address are equal
b) sets CY=1, if the contents of the destination register are greater then that of the source register
c) sets CY=0, if the contents of the destination register are smaller then that of the source register
d) none of the mentioned
Answer: d
Explanation: In CJNE command, the pointer jumps if the values of the two registers are not equal and it resets CY if
the destination address is larger then the source address and sets CY if the destination address is smaller then the so
urce address.
10. XRL, ORL, ANL commands have _______
a) accumulator as the destination address and any register, memory or any immediate data as the source address
b) accumulator as the destination address and any immediate data as the source address
c) any register as the destination address and accumulator, memory or any immediate data as the source address
d) any register as the destination address and any immediate data as the source address
Answer: a
Explanation: These commands have accumulator as the destination address and any register, memory or any immedi
ate data as the source address.
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1. What is the clock source for the timers?
a) some external crystal applied to the micro-controller for executing the timer
b) from the crystal applied to the micro-controller
c) through the software
d) through programming
Answer: b
Explanation: Timer’s clock source is the crystal that is applied to the controller.
2. What is the frequency of the clock that is being used as the clock source for the timer?
a) some externally applied frequency f’
b) controller’s crystal frequency f
c) controller’s crystal frequency /12
d) externally applied frequency/12
Answer: c
Explanation: The frequency of the clock source for the timer is equal to f/12(where f is the frequency of the crystal).
3. What is the function of the TMOD register?
a) TMOD register is used to set various operation modes of timer/counter
b) TMOD register is used to load the count of the timer
c) Is the destination or the final register where the result is obtained after the operation of the timer
d) Is used to interrupt the timer
Answer: a
Explanation: TMOD is used to set various operation modes of timer/counter by the programmer.
4. What is the maximum delay that can be generated with the crystal frequency of 22MHz?
a) 2978.9 sec
b) 0.011 msec
c) 11.63 sec
d) 2.97 msec
Answer: d
Explanation: For generating the maximum delay we have to multiply the maximum number of counts with the time
period required to execute one machine cycle( 65536*1/22MHz).
5. Auto reload mode is allowed in which mode of the timer?
a) Mode 0
b) Mode 1
c) Mode 2
d) Mode 3
Answer: c
Explanation: Auto reload is allowed in the Mode 2 of the timer because here in this mode, we don’t need to load the
count again and again in the register.
6. Find out the roll over value for the timer in Mode 0, Mode 1 and Mode 2?
a) 00FFH,0FFFH,FFFFH
b) 1FFFH,0FFFH,FFFFH
c) 1FFFH,FFFFH,00FFH
d) 1FFFH,00FFH,FFFFH
Answer: c
Explanation: For Mode 0 13 bit value is used so 1FFFH is chosen to be the roll over value. Similarly for Mode 1 FF
FFH and for Mode 2 FFH is the roll over value for the timers and counter.
7. What steps are followed when we need to turn on any timer?
a) load the count, start the timer, keep monitoring it, stop the timer
b) load the TMOD register, load the count, start the timer, keep monitoring it, stop the timer
c) load the TMOD register, start the timer, load the count, keep monitoring it, stop the timer
d) none of the mentioned
Answer: b
Explanation: When any timer is to turn on, then firstly we have to load the TMOD register and the count. Then the ti
mer is to get started. After then, we need to monitor the timer properly and then when the roll over condition arises t
hen the timer is to be stopped.
8. If Timer 0 is to be used as a counter, then at what particular pin clock pulse need to be applied?
a) P3.3
b) P3.4
c) P3.5
d) P3.6
Answer: b
Explanation: If Timer 0 is to be used as a counter, then a pulse has to be applied at P3.4 and if it is for Timer 1 then t
he clock pulse has to be applied at the pin P3.5.
9. In the instruction “MOV TH1,#-3”, what is the value that is being loaded in the TH1 register?
a) 0xFCH
b) 0xFBH
c) 0xFDH
d) 0xFEH
Answer: c
Explanation: Negative value is loaded in 2’s complement form. -3 represented in 2’s complement form as FDH.
10. TF1, TR1, TF0, TR0 bits are of which register?
a) TMOD
b) SCON
c) TCON
d) SMOD
Answer: c
Explanation: All of these bits are part of TCON (Timer Control) register. TF0 and TF1 are used to check overflow o
f timer 0 and timer 1 respectively. TR0 and TR1 are timer control bits used to start and stop of timer 0 and timer 1 re
spectively.
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1. Which devices are specifically being used for converting serial to parallel and from parallel to serial respectively?
a) timers
b) counters
c) registers
d) serial communication
Answer: c
Explanation: Some registers like the parallel in serial out and serial in parallel out are used to convert serial data into
parallel and vice versa respectively.
2. What is the difference between UART and USART communication?
a) they are the names of the same particular thing, just the difference of A and S is there in it
b) one uses asynchronous means of communication and the other uses synchronous means of communication
c) one uses asynchronous means of communication and the other uses asynchronous and synchronous means of com
munication
d) one uses angular means of the communication and the other uses linear means of communication
Answer: c
Explanation: UART stands for Universal Asynchronous receiver-transmitter and USART stands for Universal Sync
hronous and Asynchronous receiver-transmitter.
3. Which of the following best describes the use of framing in asynchronous means of communication?
a) it binds the data properly
b) it tells us about the start and stops of the data to be transmitted or received
c) it is used for error checking
d) it is used for flow control
Answer: b
Explanation: In data framing in asynchronous means of communication, the data is packed between the start and the
stop bit. This is done so as to tell the other computer about the start and the end of the data.
4. Which of the following signal control the flow of data?
a) RTS
b) DTR
c) RTS & DTR
d) None of the mentioned
Answer: a
Explanation: RTS is a request to send control signal which is a control for the flow of data. On the other hand DTR i
s a Data Terminal Ready control signal which tells about the current status of the DTE.
5. Which of the following is the logic level understood by the micro-controller/micro-processor?
a) TTL logic level
b) RS232 logic level
c) None of the mentioned
d) TTL & RS232 logic level
Answer: a
Explanation: TTL logic or the transistor logic level is the logic that is understood by the micro-controllers/microproc
essors.
6. What is a null modem connection?
a) no data transmission
b) no MAX232
c) the RxD of one is the TxD for the other
d) no serial communication
Answer: c
Explanation: In null modem connection the RxD of one is the TxD for the other.
7. Which of the following best states the reason that why baud rate is mentioned in serial communication?
a) to know about the no of bits being transmitted per second
b) to make the two devices compatible with each other, so that the transmission becomes easy and error free
c) to use Timer 1
d) for wasting memory
Answer: b
Explanation: To make two devices compatible with each other baud rate is mentioned in the serial communication s
o that the transmission becomes easy and error free.
8. With what frequency UART operates( where f denoted the crystal frequency )?
a) f/12
b) f/32
c) f/144
d) f/384
Answer: d
Explanation: UART frequency is the crystal frequency f/12 divided by 32, that comes out to be f/384.
9. What is the function of the SCON register?
a) to control SBUF and SMOD registers
b) to program the start bit, stop bit, and data bits of framing
c) to control SMOD registers
d) none of the mentioned
Answer: b
Explanation: SCON register is mainly used for programming the start bits, stop bits and data bits of framing. As it c
onsists of bits like RB8, TB8, SM0, SM1, SM2 etc.
10. What should be done if we want to double the baud rate?
a) change a bit of the TMOD register
b) change a bit of the PCON register
c) change a bit of the SCON register
d) change a bit of the SBUF register
Answer: b
Explanation: PCON register consists of SMOD bit as its D7 bit, so if we set this bit then the baud rate gets doubled.
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1. When an interrupt is enabled, then where does the pointer moves immediately after this interrupt has occurred?
a) to the next instruction which is to be executed
b) to the first instruction of ISR
c) to a fixed location in memory called interrupt vector table
d) to the end of the program
Answer: c
Explanation: When an interrupt occurs, then it jumps to a fixed memory location in memory called the interrupt vect
or table that holds the address of the Interrupt Service Routine.
2. What are the contents of the IE register, when the interrupt of the memory location 0x00 is caused?
a) 0xFFH
b) 0x00H
c) 0x10H
d) 0xF0H
Answer: b
Explanation: When interrupt of 0x00 is caused (the reset interrupt) then all the other interrupts will be disabled or th
e contents of the IE register becomes null.
3. After RETI instruction is executed then the pointer will move to which location in the program?
a) next interrupt of the interrupt vector table
b) immediate next instruction where interrupt is occurred
c) next instruction after the RETI in the memory
d) none of the mentioned
Answer: b
Explanation: When the RETI instruction is executed, PC will fetch 2-bytes (address) from top of stack which is store
d when interrupt is occurred. This will return to the place where interrupt is occurred and starts executing instruction
s.
4. Which pin of the external hardware is said to exhibit INT0 interrupt?
a) pin no 10
b) pin no 11
c) pin no 12
d) pin no 13
Answer: c
Explanation: INT0 interrupt is caused when pin no 12 in the hardware of the 8051 controller is enabled with a low le
veled pulse.
5. Which bit of the IE register is used to enable TxD/RxD interrupt?
a) IE.D5
b) IE.D2
c) IE.D3
d) IE.D4
Answer: d
Explanation: IE.D4 is used to enable RS interrupt or the serial communication interrupt.
6. Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register (assu
ming initially all bits of the IE register are zero)?
a) EX0=1
b) EA=1
c) any of the mentioned
d) EX0=1 & EA=1
Answer: d
Explanation: For executing the EX0 interrupt, the EX0 and EA bits of the IE register should be set. EA is set to enab
le all the interrupts and EX0 is set to enable the external hardware interrupt 0 interrupt and mask the other enabled in
terrupts.
7. Why normally LJMP instructions are the topmost lines of the ISR?
a) so as to jump to some other location where there is a wider space of memory available to write the codes
b) so as to avoid overwriting of other interrupt instructions
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: There is a small space of memory present in the vector table between two different interrupts so in orde
r to avoid overwriting of other interrupts we normally jump to other locations where a wide range of space is availab
le.
8. Which register is used to make the interrupt level or an edge triggered pulse?
a) TCON
b) IE
c) IPR
d) SCON
Answer: a
Explanation: TCON register is used to make any interrupt level or edge triggered.
9. What is the disadvantage of a level triggered pulse?
a) a constant pulse is to be maintained for a greater span of time
b) another interrupt may be generated if the low-level signal is not removed before the ISR is finished
c) it is difficult to produce
d) another interrupt may be caused if the signal is still low before the completion of the last instruction
Answer: d
Explanation: In a level triggered interrupt, if the low signal at interrupt pin must be removed before the execution of
last instruction of the ISR i.e. RETI. If low signal at interrupt pin is not removed before completing the ISR then it w
ill be generating another interrupt.
10. What is the correct order of priority that is set after a controller gets reset?
a) RI/TI > TF1 > TF0 > INT1 > INT0
b) RI/TI < TF1 < TF0 < INT1 < INT0
c) INT0 > TF0 > INT1 > TF1 > RI/TI
d) INT0 < TF0 < INT1 < TF1 < RI/TI
Answer: c
Explanation: On reset Interrupt Priorities are as INT0 > TF0 > INT1 > TF1 > RI/TI, where ‘>’ is used to denote high
est priority.
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1. How many rows and columns are present in a 16*2 alphanumeric LCD?
a) rows=2, columns=32
b) rows=16, columns=2
c) rows=16, columns=16
d) rows=2, columns=16
Answer: d
Explanation: 16*2 alphanumeric LCD has 2 rows and 16 columns.
2. How many data lines are there in a 16*2 alphanumeric LCD?
a) 16
b) 8
c) 1
d) 0
Answer: b
Explanation: There are eight data lines from pin no 7 to pin no 14 in an LCD.
3. Which pin of the LCD is used for adjusting its contrast?
a) pin no 1
b) pin no 2
c) pin no 3
d) pin no 4
Answer: c
Explanation: Pin no 3 is used for controlling the contrast of the LCD.
4. For writing commands on an LCD, RS bit is
a) set
b) reset
c) set & reset
d) none of the mentioned
Answer: b
Explanation: For writing commands on an LCD, RS pin is reset.
5. Which command of an LCD is used to shift the entire display to the right?
a) 0x1C
b) 0x18
c) 0x05
d) 0x07
Answer: a
Explanation: 0x1C is used to shift the entire display to the right.
6. Which command is used to select the 2 lines and 5*7 matrix of an LCD?
a) 0x01
b) 0x06
c) 0x0e
d) 0x38
Answer: d
Explanation: 0x38 is used to select the 2 lines and 5*7 matrix of an LCD.
7. Which of the following step/s is/are correct for sending data to an LCD?
a) set the R/W bit
b) set the E bit
c) set the RS bit
d) all of the mentioned
Answer: d
Explanation: To send data to an LCD, RS pin should be set so that LCD will come to know that it will receive data
which has to display on the screen. R/W pin should be reset as data has to be displayed (i.e. write to the LCD). High
to low pulse must be applied to the E pin when data is supplied to data pins of the LCD.
8. Which of the following step/s is/are correct to perform reading operation from an LCD?
a) low to high pulse at E pin
b) R/W pin is set high
c) low to high pulse at E pin & R/W pin is set high
d) none of the mentioned
Answer: c
Explanation: For reading operations, R/W pin should be made high and added to it, a low to high pulse is also gener
ated at the E pin.
9. Which instruction is used to select the first row first column of an LCD?
a) 0x08
b) 0x0c
c) 0x80
d) 0xc0
Answer: c
Explanation: 0x80 is used to select the first row first column of an LCD.
10. The RS pin is _________ for an LCD.
a) input
b) output
c) input & output
d) none of the mentioned
Answer: a
Explanation: The RS pin is an input pin for an LCD.
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1. Which of the following steps detects the key in a 4*4 keyboard matrix about the key that is being pressed?
a) masking of bits
b) ensuring that initially, all keys are open
c) checking that whether the key is actually pressed or not
d) all of the mentioned
Answer: d
Explanation: For detecting that whether the key is actually pressed or not, firstly this must be ensured that initially al
l the keys are closed. Then we need to mask the bits individually to detect that which key is pressed. Then we need t
o check that is the key actually pressed or not, by checking that whether the key pressed for a time more than 20 mic
ro seconds.
2. What is described by this command: CJNE A,#00001111b, ROW1
a) it masks the bit and then jumps to the label where ROW1 is written
b) it makes the value of the accumulator 0FH and then jumps at the address where ROW1 label is written
c) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if the val
ue becomes equal
d) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if the val
ue is not equal
Answer: d
Explanation: This particular command CJNE A,#00001111b, ROW1 compares the value of the accumulator with O
FH and jumps to ROW1 address if the value is not equal.
3. To detect that in which column, the key is placed?
a) we can mask the bits and then check it
b) we can rotate the bits and then check that particular bit which is set or reset(according to the particular condition)
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: We can mask or we can even rotate the bits to check that particularly in which column is the key place
d.
4. In reading the columns of a matrix, if no key is pressed we should get all in binary notation
a) 0
b) 1
c) F
d) 7
Answer: b
Explanation: If no key is pressed, then all the keys show 1 as they are all connected to power supply.
5. If we need to operate a key of a keyboard in an interrupt mode, then it will generate what kind of interrupt?
a) ES
b) EX0/EX1
c) T0/T1
d) RESET
Answer: b
Explanation: If a key is to operate in an interrupt mode then it will generate an external hardware interrupt.
6. To identify that which key is being pressed, we need to:
a) ground all the pins of the port at a time
b) ground pins of the port one at a time
c) connect all the pins of the port to the main supply at a time
d) none of the mentioned
Answer: b
Explanation: To detect that which key is being pressed, we need to ground the pins one by one.
7. Key press detection and Key identification are:
a) the same processes
b) two different works are done in Keyboard Interfacing
c) none of the mentioned
d) any of the mentioned
Answer: b
Explanation: They are two different works that are involved in Keyboard Interfacing. One is used for checking that
which key is being actually pressed and the other is used to check that is the key actually pressed or not.
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1. Why two pins for ground are available in ADC0804?
a) for controlling the ADCON0 and ADCON1 register of the controller
b) for controlling the analog and the digital pins of the controller
c) for both parts of the chip respectively
d) for isolate analog and digital signal
Answer: d
Explanation: Two grounds are available in ADC0804 to isolate analog signal from digital signal. This isolation prov
ides accuracy in digital output.
2. What is the function of the WR pin?
a) its active high input used to inform ADC0804 to the end of conversion
b) its active low input used to inform ADC0804 to the end of conversion
c) its active low input used to inform ADC0804 to the start of conversion
d) its active high input used to inform ADC0804 to the start of conversion
Answer: c
Explanation: WR is active low input used to inform the ADC0804 to start the conversion process.
3. State which of the following statements are false?
a) CLK IN pin used for External Clock Input or Internal Clock with external RC element
b) INTR pin tells about the end of the conversion
c) ADC0804 IC is an 8 bit parallel ADC in the family of the ADC0800 series
d) None of the mentioned
Answer: d
Explanation: CLK IN pin is used to tell about the conversion time, INTR pin tells about the end of the conversion an
d ADC0804 has a resolution of 8 bits only so all three statements are true.
4. While programming the ADC0808/0809 IC what steps are followed?
a) select the analog channel, start the conversion, monitor the conversion, display the digital results
b) select the analog channel, activate the ALE signal (L to H pulse), start the conversion, monitor the conversion, rea
d the digital results
c) select the analog channel, activate the ALE signal (H to L pulse), start the conversion, monitor the conversion, rea
d the digital results
d) select the channel, start the conversion, end the conversion
Answer: b
Explanation: While programming the ADC0808/0809 IC firstly we need to select the channel from the A, B, C pins.
Then we need to activate the ALE signal, this is needed to latch the address. Then we start the conversion from the
WR pin. After monitoring the INTR pin we get to know about the end of the conversion. Then we activate the OE e
nable to read out data out of the ADC chip.
5. In ADC0808/0809 IC which pin is used to select Step Size?
a) Vref
b) Vin
c) Vref/2 & Vin
d) None of the mentioned
Answer: a
Explanation: Step Size is calculated by formula Vref/(2n). As ADC0808/0809 8-bit ADC value of n=8. Therefore fo
rmula becomes Vref/(28) = Vref/256. If Vref = 5V then Step Size will be 5/256 i.e. 19.53mV.
6. What is the difference between ADC0804 and MAX1112?
a) ADC0804 has 8 bits and MAX1112 has 1 bit for data output
b) ADC0804 is used for adc and dac conversions whereas MAX1112 is used for serial data transmissions
c) ADC0804 has 32 bits and MAX1112 has 3 bit for data output
d) None of the mentioned
Answer: a
Explanation: ADC0804 is used for parallel ADC and MAX1112 is used for serial ADC.
7. Which of the following statements are true about DAC0808?
a) parallel digital data to analog data conversion
b) it has current as an output
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: DAC0804 is used for parallel data to analog data conversion.
8. 8 input DAC has ________
a) 8 discrete voltage levels
b) 64 discrete voltage levels
c) 124 discrete voltage levels
d) 256 discrete voltage levels
Answer: d
Explanation: For n input DAC has 2^n discrete voltage levels.
9. INTR, WR signal is an input/output signal pin?
a) both are output
b) both are input
c) one is input and the other is output
d) none of the mentioned
Answer: c
Explanation: INTR pin tells about the end of the conversion (output) and WR pin tells us to start the conversion (inp
ut).
10. What is the function of the SCLK pin in MAX1112?
a) It is used to bring data in
b) It is used to bring data out and send in the control byte, one at a time
c) It is used to get output clock
d) It is used to get serial output
Answer: b
Explanation: SCLK is used to bring data out and send in the control byte.
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1. A thermistor is a __________
a) sensor
b) adc
c) transducer
d) micro controller
Answer: c
Explanation: A thermistor is a device which is used to convert the temperature into electrical signals, so it acts as a tr
ansducer.
2. What is the difference between LM 34 and LM 35 sensors?
a) one is a sensor and the other is a transducer
b) one’s output voltage corresponds to the Fahrenheit temperature and the other corresponds to the Celsius temperat
ure
c) one is of low precision and the other is of higher precision
d) one requires external calibration and the other doesn’t require it
Answer: b
Explanation: LM 34’s output voltage corresponds to the Fahrenheit temperature and LM 35 corresponds to the Celsi
us temperature.
3. An electronic device which converts physical quantity or energy from one form to another is called ______
a) Sensor
b) Transistor
c) Transducer
d) Thyristor
Answer: c
Explanation: An electronic device that converts physical quantity or energy from one form to another is called Trans
ducer. Examples: Sensor, Speaker, Microphone, etc.
4. What is signal conditioning?
a) to analyse any signal
b) conversion or modification is referred to as conditioning
c) conversion from analog to digital is signal conditioning
d) conversion from digital to analog is signal conditioning
Answer: b
Explanation: Signal Conditioning is referred to as the conversion of a signal from one form to other, now this may b
e from analog to digital conditioning or digital to analog conditioning.
5. What steps have to be followed for interfacing a sensor to a microcontroller 8051?
a) make the appropriate connections with the controller, ADC conversion, analyse the results
b) interface sensor with ADC and ADC with 8051
c) interface sensor with the MAX232, send now to microcontroller, analyse the results
d) none of the mentioned
Answer: b
Explanation: For interfacing a sensor with an 8051 microcontroller, we need ADC in between because output of sen
sor is analog and microcontroller works on digital signals only. So whatever signal generated by the sensor is conver
ted into its digital equivalent using ADC and equivalent digital signal is given to the microcontroller for processing.
6. LM35 has how many pins?
a) 2
b) 1
c) 3
d) 4
Answer: c
Explanation: LM35 has 3 pins.
7. Why Vref is set of ADC0848 to 2.56 V if analog input is connected to the LM35?
a) to set the step size of the sampled input
b) to set the ground for the chip
c) to provide supply to the chip
d) all of the mentioned
Answer: a
Explanation: Vref is used to set the step size of the ADC conversion, if it is selected to 2.56 then the step size will be
selected to 10mV, so for every step increase of the analog voltage an increase of 10 mV will be there.
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1. The 8255 is a ______ chip.
a) Input/Output
b) Analog to Digital
c) Digital to analog
d) None of the mentioned
Answer: a
Explanation: The 8255 is Input/Output (I/O) chip. It has three separate accessible ports. The 8255 chip is used to exp
and the I/O ports of microcontrollers.
2. Which pins of a microcontroller are directly connected with 8255?
a) RD
b) WR
c) D0-D7
d) All of the mentioned
Answer: d
Explanation: RD, WR, D0-D7 all are directly connected to the 8051 for telling the chip about the control signals and
also for transferring the data.
3. Find the control word for PA = out, PB = in, PCL = out, PCH = out (Mode0)?
a) 0x02H
b) 0x82H
c) 0x83H
d) 0x03H
Answer: b
Explanation: The value that is being loaded in the control word is 10000010b for PB as an input port and all others a
s the output ports being operated in mode0. The hex equivalent of 10000010b → 0x82H.
4. Which pins are used to select the ports and the control register?
a) CS
b) A1
c) A0
d) All of the mentioned
Answer: d
Explanation: CS pin is an active low input pin for 8255 and it is used for selecting a chip. A0 and A1 pins are used f
or select ports and the control register.
5. What is the value of the control register when RESET button is set to zero?
a) 0x00H
b) 0xFFH
c) 0x11H
d) value remains the same
Answer: d
Explanation: RESET is active-high signal input into the 8255 used to clear the control register. When RESET is acti
vated (i.e. set to high), all ports are initialized as input mode. Hence the value of the control register remains the sam
e as it is even when the RESET button is set to zero.
6. Why MOVX instruction is being used to access the ports of the 8255?
a) because 8255 is connecting a microcontroller in memory mapped I/O configuration
b) because 8255 is used to access the external communication
c) because 8255 is used to access the data transfer
d) because 8255 is used to access the interfacing of LCD, motor etc
Answer: a
Explanation: As 8255 is connecting a microcontroller in memory mapped I/O configuration. This means that memor
y space used to access 8255 (i.e. 8255 is treated as external memory). MOVX instruction is used to access external
memory locations.
7. What is correct about the BSR mode from below?
a) In BSR mode, only the individual bits of PORT A can be programmed
b) In BSR mode, only the individual bits of PORT B can be programmed
c) In BSR mode, only the individual bits of PORT C can be programmed
d) none of the mentioned
Answer: c
Explanation: BSR (Bit Set/Rest) mode is used to program individual bits of PORT C only.
8. How many pins of the 8255 can be used as the I/O ports?
a) 8
b) 16
c) 24
d) 32
Answer: c
Explanation: There are 3 ports available in the 8255 so 24 pins are available for the I/O ports pins.
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1. DS12887 is a ____________
a) Timer IC
b) Serial communication IC
c) RTC IC
d) Motor
Answer: c
Explanation: DS12887 is a real time clock that is widely used to provide accurate time and date for many application
s.
2. DS12887 has _____ amount of RAM.
a) 14 bytes
b) 114 bytes
c) 128 bytes
d) 64 bytes
Answer: c
Explanation: DS12887 has 128 bytes of non-volatile RAM.
3. DS12887 has _____ amount of RAM for general purpose applications.
a) 9 bytes
b) 114 bytes
c) 128 bytes
d) 14 bytes
Answer: b
Explanation: DS12887 has 128 bytes of non-volatile RAM. Out of 128 bytes, 14 bytes of RAM for clock/calendar a
nd control registers, and another 114 bytes of RAM for general purpose data storage.
4. In DS12887, which bits of the Register A are used to turn on the oscillator?
a) D4
b) D5
c) D6
d) All of the mentioned
Answer: d
Explanation: In DS12887, D4-D6 bits of register A are used to turn on the oscillator. A specific value of 010 of D4-
D6 is desirable for turning on the oscillator.
5. In DS12887, which out of the following is correct about the SQW pin?
a) it is an output pin
b) it can provide up to 15 different square waves
c) the frequency of the square wave is set by the register A
d) all of the mentioned are correct
Answer: d
Explanation: In DS12887, SQW pin stands for SQuare Wave. It is an output pin that can provide us with 15 differen
t square waves. The frequency of the square wave is selected by programming register A.
6. In DS12887, what is correct about the UIP bit of the register A?
a) it is a read only bit
b) it is used to know about the result
c) it is used to select the DS12887 datasheet
d) all of the mentioned
Answer: a
Explanation: In DS12887, UIP bit of register A stands for Update In Progress. The update-in-progress (UIP) bit is a
status flag i.e. read-only bit.
7. In DS12887, what is the range of RAM addresses which are used to store the values of time, calendar and alarm d
ata?
a) 00-7FH
b) 00-09H
c) 0EH-7FH
d) 0A-0DH
Answer: b
Explanation: In DS12887, the first ten locations i.e. 00-09H are used to store the values of time, calendar and alarm
data.
8. Is DS12887 has non-volatile RAM?
a) Yes
b) No
c) Can’t be determined
d) None of the mentioned
Answer: a
Explanation: Yes, DS12887 has non-volatile RAM.
9. Name the read only registers are present in the DS12887?
a) register A, register B
b) register B, register C
c) register C, register D
d) register D, register A
Answer: c
Explanation: Register C and D are the read only registers in the DS12887 found at memory locations 0C-0DH.
10. In DS12887, when the external source is turned-off, how does DS12887 get power to retain its data?
a) Internal Lithium Battery
b) Internal Lead Battery
c) Additional external Alkaline Battery
d) Additional external Lithium Battery
Answer: a
Explanation: When Vcc falls below 3V or external voltage source is switched-off, internal lithium battery provides p
ower to DS12887. And this will prevent loss of data.
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1. What is the principle on which electromagnetic relays operate?
a) electromagnetic induction
b) motor control
c) switching
d) none of the mentioned
Answer: a
Explanation: Electromagnetic relays work on the principle of electromagnetic induction. It is used as a switch in ind
ustrial controls, automobile and appliances. It allows the isolation of the sections of a system with two different volt
age sources.
2. What are DPDT relays?
a) Single pole, single throw
b) Single pole, double throw
c) Double pole, double throw
d) None of the mentioned
Answer: c
Explanation: In DPDT relay, there are two poles and two throws (i.e.contacts). For each pole there are two contacts i
.e. normally open (NO) and normally closed (NC). The contacts can be NO or NC. Generally, contact is NC when th
e coil is not energized. When the coil is energized both poles become NC.
3. Why do we need a ULN2803 in driving a relay?
a) for switching a motor
b) for increasing the current
c) for increasing the power
d) for switching the voltage
Answer: b
Explanation: We need a ULN2803 for driving a relay because the relay coil requires 10mA or more current to be en
ergized. If microcontroller pins are not able to provide sufficient current to drive relays then we need ULN2803 for
driving relays.
4. Why are solid-state relays advantageous over electromechanical relays?
a) they need zero voltage circuit
b) they need less current to be energised
c) they need less voltage to be energised
d) none of the mentioned
Answer: b
Explanation: Solid-state relays are advantageous over electromechanical relays because their switching response tim
e is much faster than electromechanical relays as solid-state relays are made-up of semiconductor materials. Also, so
lid-state relays required low input current for operation and small packaging make them ideal for microcontrollers.
5. What are optoisolators?
a) it is a driver
b) it is a thing isolated from the entire world
c) it is a device that can be used as an electromagnetic relay without a driver
d) none of the mentioned
Answer: c
Explanation: Optoisolators are devices that can be used as an electromagnetic relay without a driver. It usually consi
sts of a led (transmitter) and a photoresistive receiver.
6. How can we control the speed of a stepper motor?
a) by controlling its switching rate
b) by controlling its torque
c) by controlling its wave drive 4 step sequence
d) cant be controlled
Answer: a
Explanation: Speed of a stepper motor can be controlled by changing its switching speed or by changing the length o
f the time delay loop.
7. Which of the following can be a unit for torque?
a) kg/m2
b) ounce-inch
c) kg-m3
d) g/m
Answer: b
Explanation: Torque is equal to the force applied at a particular distance. So its unit can be ounce-inch.
8. The RPM rating given for the DC motor is for?
a) no-loaded
b) loaded
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: RPM rating given for a DC motor is for a no-loaded condition.
9. How can we change the speed of a DC motor using PWM?
a) By changing amplitude of PWM
b) By keeping fixed duty cycle
c) By changing duty cycle of PWM
d) By increasing power of PWM
Answer: c
Explanation: We can change the speed of a DC motor using PWM by changing the duty cycle of PWM. Changing d
uty cycle means changing ON and OFF timing of PWM. Even if amplitude of PWM is fixed by increasing the ON ti
me of PWM increases the speed of the DC motor.
10. How can the direction of the DC motor be changed?
a) by changing the torque
b) by changing the switching speed
c) by changing the polarity of voltages connected to the leads
d) by changing the RPM rating
Answer: c
Explanation: The direction of the DC motor can be changed by changing the polarity of the voltages connected to its
leads.
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1. Is the following instruction correct LDI R3,50?
a) Yes
b) No
c) Cant be said
d) None of the mentioned
Answer: b
Explanation: If LDI Rd,k is written then the range of Rd varies from R16-R31, as R3 is less than R16 so this instruct
ion will generate an error.
2. Registers R0-R31 are used for what type of works?
a) they are used for arithmetic and logic instructions
b) they are used for data copy
c) they are used for calculations
d) none of the mentioned
Answer: a
Explanation: GPRs are used for implementing arithmetic and logic instructions in the controller. They do the same
work as the accumulator does in the other microcontrollers and microprocessors.
3. The largest value that can be loaded in an 8 bit register is?
a) 11111111H
b) FH
c) FFH
d) 00H
Answer: c
Explanation: The largest value that can be loaded in an 8 bit register is 11111111b or FFH.
4. The total space for the data memory available in the AVR based microcontroller is?
a) FFH
b) FFFH
c) FFFFH
d) FFFFFH
Answer: c
Explanation: The maximum value that can be loaded in the code memory of an AVR based microcontroller is FFFF
H.
5. Which of the following instructions affect the flags of the status register?
a) AND
b) INC
c) OR
d) All of the mentioned
Answer: d
Explanation: AND, INC, OR could affect status register flags. All arithmetic and logical instructions affect status re
gister flags except SER Rd instruction. SER Rd is used to SEt Register i.e. after the execution of this instruction Rd l
oaded with FFH value and no flag is affected.
6. What is the difference between the two given instructions?
a) One copies the hexadecimal value to R16 and the other copies the decimal value to the R16 register
b) One is for command, other is for data
c) One is for assignment, other is for operations
d) Both the commands are the same
Answer: d
Explanation: Both the above commands are the same. They both are used for assigning the hexadecimal values to th
e registers.
7. Which out of the following is not a directive?
a) .EQU
b) .DEVICE
c) .ORG
d) .LDI
Answer: d
Explanation: .EQU, .DEVICE, .ORG all are the directives to the assembler whereas LDI is a command.
8. Is an assembly language a high level language?
a) Yes
b) No
c) Can’t be said
d) None of the mentioned
Answer: b
Explanation: Assembly language is not high level language rather it is low level language because it deals directly w
ith the internal structure of CPU. To program in assembly, the internal structure of the CPU must be known. Wherea
s in high level programming languages programmers don’t bother about the internal structure of the CPU because th
is is done by the compiler.
9. A 14-bit program counter can access __________ bytes of memory locations.
a) 4K
b) 8K
c) 16K
d) 64K
Answer: c
Explanation: A 14-bit program counter can access 214 bytes of memory locations i.e. 16k bytes.
214 = 24 x 210
a) 00H
b) 000H
c) 0000H
d) 00000H
Answer: d
Explanation: When an AVR wakes up, then the PC starts at the memory location 00000H.
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1. Which of the following is correct about BRNE instruction in avr microcontrollers?
a) it is used to compare two registers
b) it is used to compare two values
c) it is used to check the zero flag
d) it is used to jump to the given mentioned label when the zero flag accounts to 0
Answer: d
Explanation: BRNE label instruction is used to jump to that particular address denoted by label if condition (Z=0) is
true or satisfied. If the condition is not satisfied then it will execute the next immediate instruction.
2. How many times is this loop going to get executed?
a) 10
b) 70
c) 700
d) none of the mentioned
Answer: b
Explanation: As the R21 register is loaded with 70, so to make it zero it needs to be decremented 70 times then only
the OUT instruction will be executed so this loop repeats 70 times.
3. Which of the below mentioned are not the conditional jumps?
a) BRLO
b) BRMI
c) BRVC
d) None of the mentioned
Answer: d
Explanation: BRLO is used to branch if C=1, BRMI is used when N=1 and BRVC are used when V=0, so all are the
conditional jumps.
4. What is the relation between the target and the relative address?
a) target address= PC address + relative address
b) target address= relation address*2
c) relative address= PC address + target address
d) none of the mentioned
Answer: a
Explanation: Target address can be calculated by calculating the sum of the address of the program counter and the r
elative address.
5. In the JMP instruction, how many bits are there for determining the target address?
a) 16
b) 32
c) 22
d) 10
Answer: c
Explanation: In the JMP instruction of 4 bytes space, 22 bits are there for determining the target address and the othe
r 10 are for the op code verification.
6. Which of the following statements are correct?
a) relative address of RJMP instruction varies from 000-fffH
b) target address of JMP instruction varies from 000000-3fffffH
c) IJMP instruction jumps to that address that points to by the Z register
d) all of the mentioned
Answer: d
Explanation: The relative address of the RJMP instruction varies from 000-fffH. The target address of the JMP instr
uction varies from 000000-3fffffH. IJMP instruction is used to jump at that particular address pointed to by the Z reg
ister. So all are the correct statements.
7. Which of the following is used to represent the last RAM address?
a) MEM
b) LASTRAM
c) RAMEND
d) None of the mentioned
Answer: c
Explanation: RAMEND is a micro used to represent the last RAM address. In AVR, Stack Pointer is initialized on t
op of the stack i.e. last address of RAM.
8. Which of the following statements are correct about the RCALL instruction?
a) it is a 2 byte instruction
b) it is a 4 byte instruction
c) it is a 16 byte instruction
d) none of the mentioned
Answer: a
Explanation: RCALL instruction is used to go to the target address in the memory from -2048 to 2047.
9. On power on SP points to the address?
a) ffffH
b) fffH
c) 00h
d) all of the mentioned
Answer: c
Explanation: On power on SP register points to the 00H address.
10. Which of the following statements is true?
a) CALL instruction is used to transfer control anywhere in the 4M memory space
b) PUSH instruction is used to take out the value from the stack into some register
c) POP instruction is used to jump to any location
d) RCALL is a 4 byte instruction
Answer: a
Explanation: CALL instruction is used to transfer control anywhere in the 4M memory space available in the AVR.
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1. In AVR, which registers are there for the I/O programming of ports?
a) PORT
b) PIN
c) DDR
d) All of the mentioned
Answer: d
Explanation: For I/O programming of the ports in AVR microcontrollers, there are basically three main registers. Th
ey are PORT, PIN, DDR, so all of the mentioned is the right option.
2. The data will not go from the port registers to the pin unless:
a) DDR register of that port is set to 0
b) PORT register of that port is set to 1
c) DDR register of that port is set to 1
d) PORT register of that port is set to 0
Answer: c
Explanation: The data will not go from the port registers to the pin unless the DDR register of that port is set to 1 be
cause by doing this we make that port an output port after which data can be taken from the PORT registers to the pi
n.
3. On reset DDR registers of all ports are set to:
a) 0
b) 1
c) None of the mentioned
d) 0 & 1
Answer: a
Explanation: On reset, the DDR registers of all the ports are set to 0 which means that the by default all ports are set
as input ports.
4. Which of the following statements are correct?
a) PIN register of a port is used to bring data into CPU from pins
b) PORT register is used to send data out to pins
c) DDR register is used to control the direction of a port
d) All of the mentioned
Answer: d
Explanation: There are three registers that are related to a port. They are PIN, PORT, DDR. PIN register is used to b
ring data into CPU from pins, PORT register is used to send data to pins and DDR register is used to control the dire
ction of the data transfer. So all are the right options.
5. In the AVR family, all I/O ports have 8 pins?
a) true
b) false
c) none of the mentioned
d) can’t be determined
Answer: b
Explanation: In the AVR family, all I/O ports don’t have 8 pins. Number of I/O pins depends on the total number of
pins of the controller. Eg. ATtinyxx is an 8 pin controller and it has 6 I/O pins.
6. Which of the following is not a single bit instruction in AVR?
a) SBI
b) PORT
c) CBI
d) All of the mentioned
Answer: b
Explanation: PORT is not an instruction. It is the name of a register in AVR.
7. Which of the following is correct about the SBIS instruction?
a) it is used to monitor status of bit in I/O register
b) it is a byte oriented instruction
c) It is a 4 byte instruction
d) all of the mentioned
Answer: a
Explanation: SBIS (Skip if Bit in I/O register Set) is used to check status of bit in I/O register. If the bit mentioned in
the instruction is SET or HIGH then the controller will skip the immediate next instruction.
8. Instruction CBI PORTB,1 means
a) clearing the PORTB register
b) clearing the first bit of the PORTB register
c) setting the PORTB register
d) setting the first bit of the PORTB register
Answer: b
Explanation: CBI PORTB, 1 means to clear the first bit of the PORTB register. It is a bit oriented instruction.
9. Which of the following instruction can be used to toggle a bit of the PORT?
a) SBI
b) CBI
c) SBI & CBI
d) None of the mentioned
Answer: c
Explanation: If SBI and CBI are used together, then they can be used to toggle a bit of a port successfully.
10. What is the main function of the SBIC instruction?
a) it is used to clear a particular bit of a port
b) it is used to jump unconditionally
c) it is used to skip the instruction if a particular bit of a port is zero
d) none of the mentioned
Answer: c
Explanation: SBIC (Skip if Bit in I/O register Clear) is used to check status of bit in I/O register. If the bit mentioned
in the instruction is CLEAR or LOW then the controller will skip the immediate next instruction.
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1. In AVR microcontrollers, ADD instruction affects the status of which of the following bits of a status register?
a) Z
b) C
c) N
d) All of the mentioned
Answer: d
Explanation: ADD instruction affects the status of Z, C, N, V, H and S bits of a status register.
2. ADC instruction is used for?
a) addition of two 16 bit numbers
b) analog to digital conversion
c) automatic digital control
d) none of the mentioned
Answer: a
Explanation: ADC instruction can be used for addition of two 16 bit numbers as here two 8 bit numbers are added si
multaneously along with the carry coming from the previous 8 bits. So it can be used for the addition of two 16 bit n
umbers.
3. AVR supports which of the following mentioned subtraction instructions?
a) SUB
b) SBC
c) SUBI
d) All of the mentioned
Answer: d
Explanation: AVR supports five types of subtraction instructions. They are SUB, SBC, SUBI, SBCI, SBIW.
4. What steps are involved when we subtract two numbers present at two different locations?
a) take the two’s complement of the subtrahend
b) add it to the minuend
c) invert the carry
d) all of the mentioned
Answer: d
Explanation: When we need to subtract two numbers present at two different locations then firstly we need to take th
e 2’s complement of the subtrahend, then we add it with the minuend and then when we invert the carry then the co
mplete procedure of the subtraction is completed.
5. In executing subtraction based instructions, state the role of the C flag?
a) if C=1, the result is negative
b) if C=1, the result is positive
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: If the C flag comes out to be 1, then the result is assumed to be negative and vice versa.
6. Which of the following is correct about the MUL instruction?
a) it is a byte-by-byte multiplication instruction
b) the product is stored in two registers R1 and R0
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: MUL instruction is a byte-by-byte multiplication instruction whose result is stored in two registers R1
and R0.
7. In AVR, when is the V flag set?
a) there is a carry from D7 bit
b) there is a carry from D6 to D7 bit
c) when carry is generated only from D6 to D7 or carry is generated only from D7
d) none of the mentioned
Answer: c
Explanation: In AVR, V i.e. Overflow flag is set when carry is generated only from D6 to D7 or carry is generated o
nly from D7. Overflow flag is used to detect errors in signed arithmetic operations.
8. To set the bits of a register R1 to 1, we must OR the contents of the register with?
a) 00H
b) 11H
c) FFH
d) 0FH
Answer: c
Explanation: To make the contents of the register R1 to 1 we must OR the contents of that register with FFH becaus
e according to Or algorithm 0+1=1 and 1+0=1.
9. CP instruction alters the value of the register?
a) true
b) false
c) none of the mentioned
d) can’t be said
Answer: b
Explanation: CP command is used to compare the contents of the two registers. It doesn’t actually alter the value of t
he register.
10. What is right about the ROR instruction?
a) it rotates the contents of the register left to right
b) it rotates the contents of the register from right to left
c) it rotates the contents of the register from left to right through carry
d) it rotates the contents of the register from right to left through carry
Answer: c
Explanation: ROR instruction is used to rotate the contents of the register from left to right through carry.
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1. In AVR, which of the following registers are not used for programming timers?
a) TCNT
b) TCON
c) TIFR
d) None of the mentioned
Answer: b
Explanation: In the timer programming of an AVR microcontroller, mainly used registers are TCNTn that stores the
values of the count. TCCRn that is used to assign the mode of operation of a timer and TIFR that stores the status of
various flags of the timers. Two more registers are used they are OCRn and OCFn. They are used for comparison wi
th the count register.
2. What is the use of the prescalar in the operation of the timer?
a) for fast calculations
b) for increasing the time delay given by the timer by decreasing its frequency of operation
c) for removing the concept the reloading of count
d) for easy counter operations
Answer: b
Explanation: Prescalars are used in the operation of the timers because they generally increase the time delay generat
ion by decreasing the frequency of its operation.
3. What modes are generally used in the operation of the timer0?
a) Normal mode
b) CTC mode
c) PWM mode
d) All of the mentioned
Answer: d
Explanation: Modes of a timer are decided by the WGM00 and WGM01 bit of the TCCR0 register and for timer0 th
ese modes are normal mode, CTC mode, pwm mode and the fast pwm mode.
4. Timer 0 can act as a counter ____________
a) if the CS02-CS00 are 110 or 111
b) if the FOC0 bit is set to 110
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: Timer0 can act as a counter if the CS02-CS00 bits are from 110-111.
5. Which of the timer can operate in the 16 bit condition?
a) timer0
b) timer1
c) timer2
d) all of the mentioned
Answer: b
Explanation: Timer0 and Timer2 can operate in the 8 bit condition while only Timer 1 operates in the 16 bit conditio
n.
6. Which of the following will generate the maximum time delay?
a) f/2
b) f/4
c) f/16
d) f/32
Answer: d
Explanation: f/32 has the lowest frequency as it is divided by the maximum value of the constant, so as time and fre
quency are inversely related to each other so this will generate the maximum amount of machine cycle which will as
a result generate the greatest delay.
7. What is the difference in the operation of a normal and a CTC mode of a timer?
a) in CTC mode PWM is used
b) here serial timer is monitored
c) in CTC mode, timer counts up until contents of TCNT register becomes equal to the contents of OCR
d) none of the mentioned
Answer: c
Explanation: In CTC mode, timer counts up until the contents of TCNT register becomes equal to the contents of O
CR; then the timer will be cleared and the OCF0 flag will be set when the next clock occurs. In Normal mode, timer
counts until max i.e. 0xFFH. When it rolls over from 0xFFH to 0x00H, it sets TOV(Timer Overflow).
8. We can count the pulses on the positive or the negative edge triggered pulse of the clock?
a) true
b) false
c) can’t be determined
d) depends on the circumstances
Answer: a
Explanation: A counter can count pulses on the positive or the negative edge of the clock.
9. Which pin is used for the input clock of the counter0?
a) PORTB.0
b) PORTB.1
c) PORTB.2
d) PORTB.3
Answer: a
Explanation: In ATmega32/16, T0 is the alternative function of PORTB.0. T0 is Timer/Counter 0 External Clock In
put.
10. Which resource provides the clock pulse to AVR timers if CS02-00=6?
a) internal clock of the AVR
b) external clock of the AVR
c) none of the mentioned
d) all of the mentioned
Answer: b
Explanation: The External clock is used for providing the pulse to the AVR timers if CS02-00=6.
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1. On reset, what are the contents of the SREG register?
a) 00h
b) ffh
c) 1fh
d) 11h
Answer: a
Explanation: On reset, all the interrupts are masked and so the contents of the SREG register is also set to zero as it s
hows the status of the flags.
2. TIMSK register is used for?
a) knowing the status of the timer count
b) used for masking the interrupts flags of the Timer0, Timer1 and Timer2
c) it is used for enabling all the timer interrupts
d) it is used for resetting the value of the interrupts
Answer: b
Explanation: TIMSK is used for masking the interrupt flags of the timers. They mask the bits of the timer flags if the
D7 bit of the SREG register is set to 1 or when firstly all interrupts are enabled.
3. Why RETI instruction be the last instruction of ISR?
a) because it returns with carry
b) because it returns to the main program with all the flags of the SREG raised
c) because it returns to the main program where interrupt is generated and set the global interrupt enable bit in SRE
G
d) none of the mentioned
Answer: c
Explanation: When an interrupt occurs, the global interrupt enable bit is cleared. If global interrupt enable is cleared
it means interrupts are disabled. RETI instruction must last instruction of ISR because it returns to the main program
where interrupt is generated and sets the global interrupt enable bit in SREG.
4. In AVR what is the ISR address for an external hardware interrupt?
a) 0002h
b) 0004h
c) 0006h
d) all of the mentioned
Answer: d
Explanation: The ISR addresses for the external hardware interrupts are 0002h, 0004h, 0006h.
5. What is the address in the interrupt service routine assigned for the timer0 overflow flag?
a) 0012h
b) 000Ah
c) 0016h
d) all of the mentioned
Answer: c
Explanation: 0016h is the address in the interrupt service routine assigned for the timer0 overflow flag.
6. Is the same address is assigned for the timer0 and timer1 overflow flag in the interrupt vector table of the interrupt
s?
a) true
b) false
c) can’t be determined
d) depends on the situation
Answer: b
Explanation: Different addresses are assigned for Timer0 and Timer1 overflow flags in the interrupt vector table. Th
ey are 0016h and 0012h for timer0 and timer1 respectively.
7. External hardware interrupts are assigned to which pins of the atmega32?
a) PORTD.2
b) PORTD.3
c) PORTB.2
d) All of the mentioned
Answer: d
Explanation: There are three external hardware interrupts in the atmega32 microcontrollers. They are assigned to bit
s PORTD.2, PORTD.3 and PORTB.2.
8. Which register is responsible for handling all the external hardware interrupts?
a) TIMSK
b) GICR
c) MCUCR
d) IVCE
Answer: b
Explanation: GICR register is responsible for all the external hardware interrupts in the AVR.
9. By default, INT0-INT2 interrupts are?
a) edge triggered
b) level triggered
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: By default, INT0-INT2 are the level triggered pulses. The low level of the pulse generates the interrupt
.
10. What will happen in that condition, if an interrupt occurs while the microcontroller is serving any other interrupt
?
a) both the interrupts will be handled simultaneously
b) the interrupt which is being done first will be served first
c) the interrupt that is more priority in the interrupt vector table will be served first
d) the interrupt having low priority in the interrupt vector table will be served first
Answer: c
Explanation: If two or more interrupts occur simultaneously then the interrupt that is having more priority in the inte
rrupt vector table will be served first.
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1. What actually are the DB9, DB25 ports available in our computers?
a) they are connectors used to transfer data either serially or parallelly
b) they are the RS232 connectors used to connect two incompatible devices
c) they are the TTL logic connector pins used for communication
d) they are just data transfer pins used to transfer the data
Answer: b
Explanation: DB9 and the DB25 ports are the ports that are based on the RS232 logic that is basically used for com
municating two incompatible devices.
2. What does RI handshaking signal refer to according to the RS232 logic?
a) if this logic is high then a receive interrupt is generated
b) this pin is high during transmission
c) this pin is high during a reception in order to tell that the device is busy at this particular time
d) none of the mentioned
Answer: c
Explanation: RI pin of the RS232 logic tells us about the ring indicator i.e it sends a busy signal if the device is curre
ntly receiving any data.
3. What is the major difference between a MAX232 and a MAX233 device?
a) one has one serial port other has two
b) one has inbuilt UART other doesn’t have that
c) one needs some additional circuitry to operate while the other doesn’t have that
d) one is used just for transmission while the other is used for both transmission as well as reception
Answer: c
Explanation: MAX232 needs some extra capacitors at pins like 1,2 and 3,4 while on the other hand MAX233 has th
at inbuilt capacitors built inside it only.
4. Which of the following is correct about the baud rate during serial transmission?
a) it tells us about the speed at which the transmission is going to place
b) it tells us about the number of bits transferred during a second
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: Baud Rate tells us about the speed in which the transmission is being done and this speed is measured i
n terms of bits per second.
5. With fosc=8 MHz, what will the count that has to filled in the UBRR register to account for the 9600 baud rate?
a) 67H
b) CEH
c) 33H
d) 34H
Answer: c
Explanation: The count that had to be filled in the UBRR register is calculated as (fosc/16(desired baud rate))-1.
6. The USART in AVR based microcontrollers operate at which of the following modes?
a) double speed asynchronous mode
b) master synchronous
c) slave synchronous
d) all of the mentioned
Answer: d
Explanation: The USART in AVR consists of the following modes. They are the normal asynchronous mode, doubl
e speed asynchronous mode, slave synchronous and the master synchronous mode.
7. Which bit of the UCSRA is used for doubling the baud rate of the transmission?
a) DOR
b) PE
c) U2X
d) MPCM
Answer: c
Explanation: U2X bit of the UCSRA is used for doubling the baud rate of the transmission.
8. What is the use of the PE and the FE bits of the UCSRA register?
a) they are used for keeping a check at the speed of transmission and reception
b) they are used for keeping a check at the data bits to be transferred
c) they are used to keep the transmission error free
d) they are used as extra redundant bits with no use
Answer: c
Explanation: PE and the FE bits of the UCSRA register are used for error checking in the transmission.
9. Which of the following bits are used for setting the data frame size?
a) UCSZ0
b) U2X
c) DOR
d) MPCM
Answer: a
Explanation: UCSZ0 and UCSZ1 bits of the UCSRB register and the UCSZ2 bit of the UCSRC register are used for
setting the data frame size in AVR based microcontrollers.
10. Which of the following parameters should the transmitter and the receiver agree upon before starting a serial tran
smission?
a) baud rate
b) frame size
c) stop bit
d) all of the mentioned
Answer: d
Explanation: Before starting the serial transmission, the following parameters should be taken care of. They are the b
aud rate, frame size, stop bit and the parity bit.
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1. In AVR, the LCD operates in two main modes, it can be in 8 bit or 4 bit data.
a) true
b) false
c) depends on the situation
d) can’t be said
Answer: a
Explanation: In AVR, the LCD operates in two main modes, they are in the 8 bit data transfer mode and the 4 bit dat
a transfer mode.
2. What can be the sequence of commands that may be used for initializing an LCD?
a) 0x06, 0x0e, 0x01
b) 0x0e, 0x01, 0x80
c) 0x38, 0x0e, 0x01
d) all of the mentioned
Answer: c
Explanation: For initializing an LCD, we can use commands like 0x38 for selecting the 5*7 matrix, 0x0e for display
on and the cursor blinking and 0x01 for clearing the screen.
3. When the LCD operates in the 4 bit mode, then what more commands are added to it?
a) 33
b) 32
c) 28
d) all of the mentioned
Answer: d
Explanation: When an LCD operates in the 4 bit mode than 33, 32, 28 in hex are sent to it. They represent 3, 3, 3, 2
nibbles which tell the LCD to do into the 4 bit mode for saving the i/o pins of the port.
4. What is the main function of the LPM instruction used in LCD?
a) for initializing the LCD in the read mode
b) for initializing the LCD in the write mode
c) for sending a long string of characters to the LCD
d) all of the mentioned
Answer: c
Explanation: LPM instruction is used for sending a long string of characters to the LCD.
5. The RS pin acts as an
a) input pin
b) output pin
c) any of the mentioned depending on the conditions
d) none of the mentioned
Answer: a
Explanation: The RS pin of the LCD is used for selecting a particular register used for sending a command or the dat
a to the LCD.
6. To latch in information at the data pins of the LCD, we send
a) H-L pulse at the E pin
b) L-H pulse at the E pin
c) A constant H pulse at the E pin
d) A constant L pulse at the E pin
Answer: a
Explanation: For latching in information at the data pins of the LCD, we send a H-L pulse at the LCD.
7. What is the function of the 0x06 command?
a) to clear the LCD
b) to blink the cursor
c) to shift the cursor to the right
d) for selecting the matrix
Answer: c
Explanation: 0x06 command is used for shifting the cursor to the right after every data send to it.
8. What is the address of the second column and the second row of the 2*20 LCD?
a) 0x80
b) 0x81
c) 0xc0
d) 0xc1
Answer: d
Explanation: 0xc0 acts as the address for selecting the second row and the first column of the LCD, so according to i
t if we need to select the second row and the second column of the LCD, then the address should be 0xc1.
9. Which of the following commands takes more than 100 microseconds to run?
a) shift cursor left
b) shift cursor right
c) set address location of the DDRAM
d) clear screen
Answer: d
Explanation: Clear screen is a command that takes more than 100 microseconds to run.
10. For selecting the data pins in an LCD, RS pin should be
a) 1
b) 0
c) F
d) 10
Answer: a
Explanation: For selecting the data pins of the LCD, the RS pin of the LCD should be set to 1.
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1. In reading the columns of a keyboard matrix, when no key is pressed then all the pins show?
a) 0
b) 1
c) F
d) 7
Answer: b
Explanation: When no key is pressed, in a keyboard then all the pins will read 1 as they all are connected to the main
power supply.
2. To see if any key is pressed, all rows are grounded.
a) true
b) false
c) can’t be said
d) depends on the conditions
Answer: a
Explanation: To see that whether any key is pressed or not then all the rows are grounded so that columns can be rea
d to deliver the better results.
3. Identify the row and the column for the following case when for the row D3-D0= 1110 and for the column D3-D0
= 1101
a) first row and second column
b) first row and third column
c) second row and first column
d) second row and second column
Answer: a
Explanation: To identify the key that is pressed from this particular combination, we obtain that the key belongs to t
he first row and the second column as the D0 bit of the row port and the D1 bit of the column port are zero.
4. What are the actual steps that are followed in identifying any key that is being pressed?
a) wait for the debounce time
b) identify the key that is pressed
c) initially no key should be pressed
d) all of the mentioned
Answer: d
Explanation: In order to identify that which key is actually pressed form a particular format of a 3*3 matrix keyboar
d, we firstly ensure all initially all the keys are open, then we press a key and check that whether the key is actually
pressed or not by waiting for a time span of 20mseconds, after this we identify the key that is pressed by masking th
e bits of the port. In this particular format, we can identify the key that is actually pressed.
5. To identify that the key is present in which row and the column
a) we ground the bits of the row one by one
b) we ground the bits of the column one by one
c) we connect the bits of the row to the logic level 1 one by one
d) we can connect the columns to the logic level 1 one by one
Answer: a
Explanation: To determine that the pressed key is in which row and column, we ground the rows one by one to deter
mine the column by masking the bits separately.
6. The key detection and the key identification are two different procedures?
a) true
b) false
c) depends on the circumstances
d) difficult to tell
Answer: a
Explanation: The key detection and the key identification are the two different procedures, one is used to detect that
whether any key is pressed or not and the other technique is used to find that the pressed key is located in which row
and column.
7. What is described by the following command?
a) load KCODE0 with 0
b) rotate the contents of the KCODE0 register to the right
c) rotate the contents of the KCODE0 register to the left
d) none of the mentioned
Answer: b
Explanation: KCODE0<<1 means to rotate the contents of the KCODE0 register to the left after every loop.
8. If the pins of the keyboard are used as an interrupt, then these pins will cause an interrupt of what type?
a) External hardware interrupt
b) Timer interrupt
c) TI/RI interrupt
d) None of the mentioned
Answer: a
Explanation: The pins of the keyboard act as an external hardware interrupt as some external pulse is helping in gene
rating this interrupt.
9. What will happen if the two keys of the keyboard are pressed at a time?
a) both the keys will be displayed on the screen
b) the key which is being actually pressed(for more then 20microseconds) will be displayed
c) the key that is pressed first will be displayed
d) none of the mentioned
Answer: b
Explanation: If two or more keys are pressed at a time, then the key that will be pressed for more then 20 microseco
nds will be displayed on the screen.
10. Why initially all keys are considered open before detecting the key pressed?
a) to make the task easy
b) to remove the errors caused by other pressing keys during detection
c) to remove the flow problems
d) none of the mentioned
Answer: b
Explanation: Initially all keys are considered open in order to ensure the accuracy while identification of the pressed
key.
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1. Which of the following is correct about the word resolution in ADC DAC converters in AVR’s?
a) it is the smallest change that can be described by an ADC
b) it is equal to Vref/2n (where n represents the number of bits)
c) it is 0.076mV or 76uV for n=16 and Vref=5V
d) all of the mentioned
Answer: d
Explanation: Resolution is defined as the smallest change in the step size that is described by an ADC, it is equal to
Vref/2n.
2. In an ADC, we can calculate the output voltage from the formula
a) Step size / Vin
b) Step size * Vin
c) Vin / step size
d) Vref / step size
Answer: c
Explanation: The output voltage can be calculated by using the formula Vin / step size.
3. ADC0848 is a ____________ bit converter?
a) 16
b) 4
c) 8
d) 48
Answer: c
Explanation: ADC0848 is a 8 bit converter.
4. Which of the following factors can affect the step size calculation?
a) number of bits
b) input current
c) output current
d) all of the mentioned
Answer: a
Explanation: There are mainly two factors that can affect the step size calculation of an ADC converter, they are the
number of bits and the Vref voltage.
5. MAX1112 is a _________ type of ADC converter?
a) parallel
b) 12 bit
c) serial
d) all of the mentioned
Answer: c
Explanation: MAX1112 is a serial ADC converter, as it has only one pin for the data output.
6. Why do we connect a capacitor between the Vref and the Gnd pin?
a) to remove the leakage
b) to ensure more current at that place
c) to make more Vref
d) to make Vref stable and also to increase the precision of the ADC
Answer: d
Explanation: A capacitor is connected between the Vref and the Gnd pin in order to stabilize the Vref value and also
to increase the precision of the ADc converter.
7. Which of the following are the registers that are used for controlling the ADC conversion in the AVR?
a) ADCSRA
b) ADMUX
c) SPIOR
d) All of the mentioned
Answer: d
Explanation: For programming the ADC conversion in an AVR, we require the following registers. They are ADCS
RA, ADMUX, SPIOR. There are two more registers used for handling the output data, they are ADCH and ADCL r
egisters.
8. What is the internal Vref of an Atmega32 series?
a) 5V
b) 3.3V
c) 2.56V
d) all of the mentioned
Answer: c
Explanation: 2.56V is the internal Vref selected for an Atmega32 series based microcontrollers.
9. The output of a DAC0808 is in the form of ____________
a) electrical pulse
b) current
c) voltage
d) all of the mentioned
Answer: b
Explanation: The output of a DAC0808 is in the form of a current.
10. In a DAC the input is ______ and the output is ______
a) analog, digital
b) current, voltage
c) digital, analog
d) analog, current
Answer: c
Explanation: In a DAC, the input is digital and the output is analog in nature.
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1. Which of the following is correct about the word sensors?
a) that senses something
b) it is a type of a transducer that converts one form of energy to another
c) it can produce output in the form of electrical pulses, current or voltage
d) all of the mentioned
Answer: d
Explanation: Sensors are the devices that are used to sense a particular thing by converting one form of energy into a
nother, this converted form can be in the form of some analog output, or in the form of current or the voltage as the c
ase may be.
2. Why do we need to apply the concept of signal conditioning to a sensor?
a) in order to convert it into a desirable form of energy
b) for testing
c) for sensing something
d) all of the mentioned
Answer: a
Explanation: Signal Conditioning is the concept that is used for data acquisition of the signal. For measuring and ana
lyzing this value at a practical stage, by converting it into a desirable form of energy.
3. Which of the following is correct about LM35 based sensors?
a) its output voltage is directly proportional to the Celsius scale
b) its output voltage is directly proportional to the Fahrenheit scale
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: LM35 based sensors are those sensors whose output voltage is directly proportional to the Celsius scale
.
4. What is the difference between the LM34 and the LM35 based sensors?
a) one requires external calibration while other does not
b) one has output voltage proportional to the Celsius scale while others have to the Fahrenheit scale
c) one is fast other is slow
d) all of the mentioned
Answer: b
Explanation: LM35 has the output voltage proportional to the Celsius scale while the LM35 based sensors have outp
ut voltage proportional to the Fahrenheit scale.
5. Every transducer must be connected with the signal conditioning circuit?
a) true
b) false
c) can’t say
d) depends on the conditions
Answer: a
Explanation: For analyzing purposes, every transducer must be connected to a signal conditioning circuit in order to
measure its value as a practical platform.
6. LM35 provides _______ V for each degree count?
a) 1
b) 0.1
c) 0.001
d) 10
Answer: c
Explanation: LM35 provides 10mV for every degree change of the Celsius scale.
7. Why for the 8 bit analog input we select Vref as the 2.56V?
a) to obtain each degree count as the 2.56V
b) to get 2.56V at the output
c) to obtain each degree count as the 10mV
d) to get 10mV as the output
Answer: c
Explanation: For an 8 bit analog input, each degree count is calculated as the Vref/256, so if Vref is selected as 2.56
V then we can obtain 10mV for each degree count of the scale.
8. What is the temperature for LM35 sensor if the analog output is 0011 1001?
a) 3
b) 9
c) 57
d) 41
Answer: c
Explanation: The binary for the above output is 57, so in case of LM35 sensors we obtain the output as 57 C.
9. In an external hardware, there are how many pins available for the LM35 and the LM34 based sensors?
a) 2
b) 3
c) 10
d) 1
Answer: b
Explanation: LM35 consists of mainly 3 pins, they are Vcc, Gnd, analog output.
10. Do LM34 and LM35 based sensors have linear output?
a) yes
b) no
c) depends on the conditions
d) can’t say
Answer: a
Explanation: LM34 and the LM35 based sensors are linearly proportional to their corresponding Fahrenheit and the
Celsius scale, so they are linear by nature.
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1. The 8255 is a ______ chip.
a) Input/Output
b) Analog to Digital
c) Digital to analog
d) None of the mentioned
Answer: a
Explanation: The 8255 is Input/Output (I/O) chip. It has three separate accessible ports. The 8255 chip is used to exp
and the I/O ports of microcontrollers.
2. Which pins of a microcontroller are directly connected with 8255?
a) RD
b) WR
c) D0-D7
d) All of the mentioned
Answer: d
Explanation: RD, WR, D0-D7 all are directly connected to the 8051 for telling the chip about the control signals and
also for transferring the data.
3. Find the control word for PA= out, PB= in, PCL=out, PCH=out (Mode0)?
a) 0x02H
b) 0x82H
c) 0x83H
d) 0x03H
Answer: b
Explanation: The value that is being loaded in the control word is 10000010b for PB as an input port and all others a
s the output ports being operated in mode0. The hex equivalent of 10000010b → 0x82H.
4. Which pins are used to select the ports and the control register?
a) CS
b) A1
c) A0
d) All of the mentioned
Answer: d
Explanation: CS pin is an active low input pin for 8255 and it is used for selecting a chip. A0 and A1 pins are used f
or select ports and the control register.
5. What is the value of the control register when RESET button is set to zero?
a) 0x00H
b) 0xFFH
c) 0x11H
d) value remains the same
Answer: d
Explanation: RESET is active-high signal input into the 8255 used to clear the control register. When RESET is acti
vated (i.e. set to high), all ports are initialized as input mode. Hence the value of the control register remains the sam
e as it is even when the RESET button is set to zero.
6. Why MOVX instruction is being used to access the ports of the 8255?
a) because 8255 is connecting a microcontroller in memory mapped I/O configuration
b) because 8255 is used to access the external communication
c) because 8255 is used to access the data transfer
d) because 8255 is used to access the interfacing of LCD, motor etc
Answer: a
Explanation: As 8255 is connecting a microcontroller in memory mapped I/O configuration. This means that memor
y space used to access 8255 (i.e. 8255 is treated as external memory). MOVX instruction is used to access external
memory locations.
7. What is correct about the BSR mode from below?
a) In BSR mode, only the individual bits of PORT A can be programmed
b) In BSR mode, only the individual bits of PORT B can be programmed
c) In BSR mode, only the individual bits of PORT C can be programmed
d) none of the mentioned
Answer: c
Explanation: BSR (Bit Set/Rest) mode is used to program individual bits of PORT C only.
8. How many pins of the 8255 can be used as the I/O ports?
a) 8
b) 16
c) 24
d) 32
Answer: c
Explanation: They are 3 ports available in the 8255 so 24 pins are available for the I/O ports pins.
9. 8255 is a ____ pin IC.
a) 16
b) 8
c) 40
d) 60
Answer: c
Explanation: 8255 is a 40 pin IC.
10. 8255 has handshaking capability?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: 8255 is a device that with the help of its handshaking property gets interfaced with any microcontroller
.
11. The 8255 can be programmed in any of the __________
a) 2 modes
b) 3 modes
c) 4 modes
d) 5 modes
Answer: c
Explanation: 8255 can be programmed in any of the 4 modes.
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1. RTC is used for __________
a) conversion
b) communication
c) real time and clock measurement
d) memory management
Answer: c
Explanation: RTC is a device that is basically used for all the real time clock related issues.
2. RTC chips use ______ to compute time, date when the power is off.
a) ac supply
b) generators
c) rectifiers
d) battery
Answer: d
Explanation: RTC chips require batteries in order to calculate the time and date when the power of the device is off.
3. DS12887 is known for as a ________
a) Communication device
b) Good battery device
c) RTC chip
d) All of the mentioned
Answer: c
Explanation: DS12887 is known as an RTC chip.
4. DS1307 is a parallel RTC with I2C bus.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: DS1307 is a serial RTC with I2C bus.
5. DS1307 is a _______ pin IC and operates on _______ clock frequency.
a) 16, 8Mhz
b) 8, 16Mhz
c) 16, 32Mhz
d) 8, 32Khz
Answer: d
Explanation: DS1307 is a 8 pin IC and operates on a 32KHz clock frequency.
6. Vbat requires a positive signal of
a) 3V
b) 5V
c) 9V
d) 12V
Answer: a
Explanation: Vbat requires a positive signal of 3V which can be obtained through a battery.
7. In DS1307, which out of the following is correct about the SQW pin?
a) input pin
b) output pin
c) i/o pin
d) none of the mentioned
Answer: b
Explanation: In DS1307, SQW pin is an output pin. It provides a clock of frequency 1khz, 4khz, 8khz, 32khz if the p
in is enabled.
8. DS1307 has a total of _______ bytes of RAM space.
a) 32
b) 64
c) 128
d) 256
Answer: c
Explanation: DS1307 has a total of 64 bytes(00-3F) of RAM space.
9. DS1307 control register has an address of _________
a) 00H
b) 03H
c) 07H
d) 10H
Answer: b
Explanation: DS1307 control register has an address of 07H.
PSST! You better watch out, something's buggy above.
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1. Why are relays used for driving the motors?
a) they can be used as switch as well as they provide isolation
b) they increase the current capability required by the motors
c) they are used to reduce the back emf from the motors
d) all of the mentioned
Answer: a
Explanation: Relay is the electrically controlled switch and it allows isolation of two separate sections of the system.
It has three main components: the coil, the common pole and the contacts. When an electric field is applied to the c
oil; it gets energized and generates a magnetic field which will force the common pole to change contact from Norm
ally Closed to Normally Open.
2. Why are ULN2803 normally used between the microcontrollers and the relays?
a) for switching purposes
b) for increasing the current capability required by a relay
c) for increasing the voltage capability required by a relay
d) all of the mentioned
Answer: b
Explanation: More current is desired for driving a motor with the help of a relay, so a ULN2803 is used for increasin
g the current as per the requirement of the relay.
3. Why are opto isolators normally used between the microcontrollers and the ULN2803?
a) to optimize the current
b) to reduce the back emf
c) to increase the current
d) to increase the voltage
Answer: b
Explanation: Opto isolators are used between the microcontrollers and the ULN2803 chips in order to decrease the b
ack emf from the ULN2803 and to save the microcontrollers for a long time.
4. Which of the following is a type of an electromagnetic relay?
a) SPST
b) SPDT
c) DPDT
d) All of the mentioned
Answer: d
Explanation: There are normally three kinds of electromagnetic relays. They are SPST(single pole single throw), SP
DT(single pole double throw) and the DPDT(double pole double throw) relays.
5. Reed switches show connectivity whenever they are in the presence of an electrical field?
a) true
b) false
c) can’t say
d) depends on the conditions
Answer: b
Explanation: Reed switches are the devices that show connectivity whenever they are in the presence of some magne
tic field.
6. Which of the following is an application of stepper motors?
a) in printers
b) in robots
c) in vehicles
d) all of the mentioned
Answer: d
Explanation: Stepper motors are used wherever there is a need of a movement at an angle, maybe it in printers, in m
otors or in vehicles stepper motors are used everywhere.
7. What are normal 4 step sequence of a stepper motor if we start to move in clockwise direction with 0110 value?
a) 1100,1001,0011,0110
b) 0011,1001,1100,0110
c) 1001,1100,0110,0011
d) 0101,1010,0101,1010
Answer: b
Explanation: For a normal 4 step sequence of a stepper motor, if we start to move in a clockwise direction then we r
otate towards right direction with every rotation.
8. What is the meaning of a step angle?
a) angle which a stepper motor has
b) angle between the two windings of the stator in a stepper motor
c) minimum degree of rotation associated with a single step
d) angle between the stator and the rotor
Answer: c
Explanation: Step angle is the minimum degree of rotation associated with a single step.
9. For a normal 4 step sequence, what are the number of teeth required to accomplish a 2 degree step angle?
a) 180
b) 90
c) 360
d) 45
Answer: d
Explanation: For a 2 degree step angle there will be 180 step per rotation, so the total number of rotor teeth are (180/
4=45).
10. Ounch-inch is a unit of a torque.
a) true
b) false
c) can’t say
d) depends on the situation
Answer: a
Explanation: Torque is a quantity which is obtained by multiplying the amount of force that is applied at a particular
angle. It is measured in terms of ounch-inch.
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1. Why do we make the connection of the SCLK for communicating serially between two devices?
a) to get a clock output from the device
b) to synchronize the two devices
c) to obtain an analog output
d) all of the mentioned
Answer: d
Explanation: We need an SCLK in order for the two devices to communicate with each other properly. It acts as a p
ulse according to which one device sends a message and the other receives it.
2. What is the function of the CE pin in SPI?
a) it is used for synchronization
b) it is used as a transmitting pin
c) it is used as a receiving pin
d) it is used to initiate and terminate the data transfer
Answer: c
Explanation: CE pin is used to initiate and terminate the data transfer in the controller via SPI interface.
3. Which of the following is correct?
a) MOSI has the same meaning as the SDO
b) SCLK is used to initiate and terminate the data transfer
c) In 3 wire SPI, there is only one pin for transmission and reception
d) In 3 wire SPI, there are three pins MOSI, MISO and SCLK
Answer: b
Explanation: In 3 wire SPI, there is only one pin for transmission and reception and the other two pins SCLK and C
E are used for synchronization of data and for initialization and termination of data.
4. If CPHA= 0 and CPOL=1, then which of the following is true?
a) read on rising edge, changed on a falling edge
b) read on falling edge, changed on a rising edge
c) write on rising edge, changed on a falling edge
d) write on rising edge, changed on a falling edge
Answer: b
Explanation: If CPOL= 1 and CPHA= 0, then reading operation is performed on the rising edge and the change occu
rs at every falling edge.
5. In SPI write, LSB goes first?
a) true
b) false
c) can’t be said
d) depends on the cases
Answer: d
Explanation: In SPI write, MSB goes first.
6. In AVR, which of the following registers are used for SPI?
a) SPSR
b) SPCR
c) SPDR
d) All of the mentioned
Answer: b
Explanation: In AVR, SPSR(SPI Status Register), SPCR(SPI Control Register) and SPDR(SPI Data Register) are us
ed for programming the SPI module.
7. How do we set the SPI, to operate in the master mode 1?
a) We set the MSTR bit, and make the CPOL= 1 and CPHA=0
b) We set the MSTR bit, and make the CPOL= 0 and CPHA=1
c) We reset the MSTR bit, and make the CPOL= 1 and CPHA=0
d) We reset the MSTR bit, and make the CPOL= 0 and CPHA=1
Answer: b
Explanation: In SPI, to make it work in the master mode, we make the MSTR bit is equal to 1 and for operating it in
the mode 1 we make the CPOL=0 and CPHA=1.
8. SPI can act as a half duplex transmission?
a) true
b) false
c) depends on the conditions
d) can’t be said
Answer: d
Explanation: No, SPI can’t work in the half duplex transmission mode.
9. Which frequency is not recommended for SPI clock?
a) fosc/4
b) fosc/64
c) fosc/16
d) fosc/2
Answer: a
Explanation: fosc/2 is not recommended frequency for SPI transfer in AVR.
PSST! You better watch out, something's buggy above.
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1. Which of the following is correct?
a) I2C is a technique by which data is transmitted with the help of only eight pins
b) SDA is used to synchronize data transfer between two chips
c) TWI is another name for I2C
d) All of the mentioned
Answer: c
Explanation: I2C is a technique by which data is transmitted between two devices by the help of only 2 pins so it is a
lso called Two wire Serial Interface.
2. Which of the following is true about the I2C protocols?
a) the data line cannot change when the clock line is high
b) the data line can change when the clock line is high
c) the clock line cannot change when the data line is high
d) the clock line can change when the data line is high
Answer: a
Explanation: According to I2C protocols, the data line(SD
a) changes only if the clock line(SCL) is at its active low level.
3. I2C is a connection oriented communication protocol.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: I2C is a connection oriented protocol i.e each transmission is initiated by a START condition and is ter
minated by a STOP condition.
4. The STOP condition is generated by a
a) high to low change in the SDA line when the SCL is low
b) high to low change in the SDA line when the SCL is high
c) low to high change in the SDA line when the SCL is low
d) low to high change in the SDA line when the SCL is high
Answer: c
Explanation: The STOP condition is generated when there is a low to high change in the SDA line when the SCL is l
ow.
5. For receiving the acknowledgment
a) SDA from the transmitter should be high
b) SDA from the transmitter should be low
c) SDA from receiver should be high
d) SDA from receiver should be low
Answer: d
Explanation: The packet format in I2C consists of 9 bits, out of which first 8 are the data bits while the ninth bit is th
e acknowledgment bit. For obtaining the acknowledgment, the SDA line of the receiver should be pushed to low.
6. What steps are followed to complete the data transfer?
a) START condition, STOP condition
b) Address packet
c) One or more data packet
d) All of the mentioned
Answer: d
Explanation: For having the complete data transfer, the steps that are actually being followed are START condition,
address packet, one or more data packet, STOP condition.
7. I2C is ideal for short distances?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: I2C is that module of the AVR, which is used for short distances.
8. Which of the following is a register used for programming AVR’s I2C module?
a) TWBR
b) TWCR
c) TWSR
d) All of the mentioned
Answer: d
Explanation: TWBR( TWI Bit rate register), TWCR( TWI Control Register), TWSR(TWI Status Register), TWAR(
TWI Address Register), TWDR( TWI Data Register) are used for programming an AVR’s I2C module.
9. Which bit is polled to know that whether the TWI is ready or not?
a) TWWC
b) TWINT
c) TWEA
d) All of the mentioned
Answer: b
Explanation: TWINT is the bit that is polled to know that whether the TWI is ready or not.
PSST! You better watch out, something's buggy above.
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1. In MSP430, the size of the status register is ________
a) 1 byte
b) 2 bytes
c) 1 bit
d) 2 bit
Answer: b
Explanation: In MSP430, the size of the status register is 2 bytes. The bits of the status register consists of the C flag
, Z flag, N flag, GIE flag, CPU off, OSC off, SCG0, SCG1, V flag and 7 reserved bits.
2. Which of the following bit/s of the status register that allows the microcontroller to operate in its low power mode
?
a) Z
b) Reserved
c) CPU off
d) N
Answer: d
Explanation: The CPU off bit, OSC off bit, SCG0 bit, SCG1 bit of the status register are used to allow the microcont
roller to operate in its low power mode.
3. What is actually done to improve the efficiency of a RISC processor?
a) instructions are reduced
b) they have two or more processors inbuilt connected between
c) they have many instructions that are interrelated to each other
d) they have one or more registers hard wired to the commonly used values
Answer: d
Explanation: To improve the efficiency of the RISC processor, the registers that are hard wired to commonly used v
alues are used instead of other ones.
4. To improve the efficiency of an MSP430 based microcontroller, for one register
a) there is only one value for all addressing modes
b) there are two values for each addressing mode
c) there are 2 values for four addressing modes
d) there are 4 values for four addressing modes
Answer: d
Explanation: In MSP430, there are namely 4 addressing modes. So the main advantage of this controller( which basi
cally increases its efficiency )is that for one register their exists 4 different values for 4 different addressing modes o
f the controller.
5. Their are_______________ number of emulated instructions found in the MSP430?
a) 4
b) 8
c) 16
d) 24
Answer: c
Explanation: The constants CG1 and CG2 are combined together to give 27 native instructions. These instructions ar
e further converted into 24 emulated instructions. So, there are 24 emulated instructions found in an MSP430 based
controller.
6. .w form is used for operations
a) that uses bytes
b) that uses words
c) that uses both
d) that uses none
Answer: b
Explanation: .w form is used for operations, that uses both bytes and words for operations.
7. Pre increment addressing is available in MSP430?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: MSP430 supports only post increment addressing. For performing pre increment addressing, we requir
e some special functions that accomplish that work.
8. Which out of the following is a correct emulated instruction?
a) ADC(.
b) dst
b) ADD(.
b) src,dst
c) ADDC(.
b) src,dst
d) AND(.
b) src,dst
Answer: a
Explanation: “ADC(.
b) dst” this is emulated to “ADDC.B #0,dst” hence this is an emulated instruction. The emulated instructions use cor
e instructions combined with the architecture and implementation of the CPU for higher code efficiency and faster e
xecution.
9. dadd instruction can act as _____________
a) valid BCD addition
b) valid adder with carry
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: Dadd instruction can act as a valid BCD addition instruction if the numbers are initially in BCD state(0
-9).
PSST! You better watch out, something's buggy above.
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1. There are _____ number of addressing modes found for the source and _____ number of modes for the destinatio
n part.
a) 4,4
b) 2,4
c) 7,4
d) 2,2
Answer: c
Explanation: In MSP430, Seven addressing modes for the source operand and four addressing modes for the destinat
ion operand can address the complete address space with no exceptions.
2. MSP430 describes reti instruction as ___________
a) Format1 addressing
b) Format2 addressing
c) Jump addressing
d) None of the mentioned
Answer: b
Explanation: MSP430 describes reti instruction as that type of addressing which consists of only single operand, so i
t comes under Format2 addressing.
3. mov.w R3, R4 takes _________
a) one cycle
b) two cycles
c) four cycles
d) eight cycles
Answer: a
Explanation: mov.w R3, R4 takes only one cycle to transfer the data from register R3 to R4. This type of mode of ad
dressing is called the register mode of addressing.
4. Indexed addressing can be used for _________
a) source
b) destination
c) source & destination
d) none of the mentioned
Answer: c
Explanation: Indexed addressing is used for both the source and the destination addresses.
5. What do you understand form this instruction mov.w X(PC), R6
a) R6 = X+PC
b) R6 = PC-X
c) R6 = -X-PC
d) R6 = -X+PC
Answer: a
Explanation: This instruction mov.w X(PC), R6 means that the contents of X+PC address are copied to the R6 regist
er.
6. Absolute mode uses which of the following operators?
a) %
b) /
c) $
d) &
Answer: d
Explanation: Absolute mode uses the & operator to transfer a constant to a register.
7. Indirect register mode is used by _________
a) source register
b) destination register
c) source & destination register
d) none of the mentioned
Answer: a
Explanation: Indirect addressing mode is used only by the source register.
8. Indirect mode and the indirect auto increment mode have which common operator in them
a) +
b) –
c) @
d) &
Answer: c
Explanation: Both the indirect and the indirect auto increment mode use the @ operator for the source register to tra
nsfer the data from one memory location to a register.
9. Are the following two instructions similar?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: MOV @R10,0(R11) → Move the contents of the source address (contents of R10) to the destination ad
dress (contents of R11).
10. MOV @R10,0(R11) is a type of ________
a) Register Mode
b) Indirect Register Mode
c) Immediate Mode
d) Indirect Autoincrement Mode
Answer: b
Explanation: The type of given instruction is Indirect Register Mode.
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1. Which instruction is used to call functions?
a) MOV
b) GO
c) CALL
d) All of the mentioned
Answer: c
Explanation: CALL instruction is used for going to a particular address in MSP430. It actually causes the pointer to j
ump at a particular address and push the current address of the PC to the stack.
2. ret instruction is used for _________
a) determining the end of the program
b) for returning back from the subroutine to the main program
c) for transferring data from one place to another
d) none of the mentioned
Answer: b
Explanation: Ret instruction is basically used for returning back from a subroutine. It actually pops the top address fr
om the stack and moves that address to its PC, so that it now returns to the main program and continue the execution
normally.
3. According to conventions being followed, R12 to R15 are used for _________
a) parameter passing
b) preserved for call
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: According to the conventions, R12 to R15 are used for parameter passing and hence are not preserved f
or the call.
4. We can store the temporary results across a call instruction with the help of which of the following registers
a) R1-R4
b) R4-R11
c) R12-R15
d) All of the mentioned
Answer: b
Explanation: Temporary results are stored by the registers R4-R11.
5. Can we allocate variables on the stack?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, we can allocate the variables on the stack, it is a very effective way of storing the variables.
6. Which registers are reserved for passing the parameters to a subroutine and then returning the final result?
a) R1-R4
b) R4-R11
c) R12-R15
d) All of the mentioned
Answer: c
Explanation: Originally, R12-R15 registers are reserved for passing the parameters to a subroutine and then returnin
g the final result.
7. What actually is the order of stack frame for a parameter to pass to a subroutine?
a) parameter passed to a subroutine
b) return address
c) saved copies of registers(R4-R11)
d) all of the mentioned
Answer: d
Explanation: All the steps i.e. parameter passed to a subroutine, return address, saved copies of registers(R4-R11), lo
cal variables in subroutines are required for passing a parameter to a subroutine.
8. When any subroutine is called, then the first value of stack will be
a) value of PC
b) the return address
c) none of the mentioned
d) both are one and the same things
Answer: d
Explanation: When any subroutine is called then the first place of the stack will be filled with the return address, or t
he address of the PC so that the pointer may return back to its appropriate place after the return instruction of the sub
routine.
9. Which of the following instruction/s is/are used to return back to the main program after the subroutine is complet
ed?
a) ret
b) reti
c) ret and reti
d) none of the mentioned
Answer: c
Explanation: For returning back from the subroutine, both ret and reti can be used, the main difference between the t
wo is that reti just resets the interrupt flag before the return, so that the interrupt can occur again.
10. Is the approach of making subroutines effective or not?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The approach of making subroutine is indeed very effective, as with its help we don’t need to retrace/w
rite a particular set of codes again and again. It makes our approach modular.
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1. MSP430 uses vectored interrupts?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: MSP430 has vectored interrupts i.e. the address of each ISR is stored in a vector table, that’s why it has
vectored interrupts.
2. Which of the following is true?
a) interrupts are required to wake a CPU from sleep
b) same vector address associated with multiple flags
c) most interrupts are maskable
d) all of the mentioned
Answer: d
Explanation: All of the above mentioned statements are true i.e. interrupts are required to wake a CPU from sleep, sa
me vector address associated with multiple flags and most of the interrupts are maskable.
3. After the interrupt has occurred, the stack is filled with ______________
a) return address
b) status register
c) return address & status register
d) none of the mentioned
Answer: c
Explanation: When an interrupt had occurred, the top place of the stack is filled with the return address, so that imm
ediately after the reti instruction the pointer moves to the main program, the stack is also filled with the bits of the st
atus register so that all the temporary values get stored in it.
4. What is the purpose of __interrupt() function?
a) it is used to enable the interrupt
b) it is used to disable the interrupt
c) it denotes that the routine is an ISR
d) all of the mentioned
Answer: c
Explanation: The purpose of __interrupt() function is to denote that the routine is an ISR.
5. What is the purpose of .intvec assembler directive?
a) it creates an interrupt vector entry that points to an interrupt routine name
b) one is used for storage, other for display
c) one stores locally other stores globally
d) the two are the same
Answer: a
Explanation: The .intvec directive creates an interrupt vector entry that points to an interrupt routine name.
6. For enabling any interrupt, firstly _____________
a) GIE=0
b) GIE=1
c) None of the mentioned
d) GIE=0 & 1
Answer: b
Explanation: If GIE is set to 1, then only other hardware interrupts are enabled.
7. Nonmaskable vectors are stored at different vector locations?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Nonmaskable interrupts are stored in the same vector location, it may be of higher or the lower priority
.
8. Which of the following can generate a nonmaskable interrupt?
a) access violation to flash memory, ACCVIFG
b) timer_A interrupt
c) compare / capture interrupt
d) all of the mentioned
Answer: a
Explanation: A nonmaskable interrupt is generated by an access violation to flash memory, ACCVIFG.
9. External RST/NMI pin is a nonmaskable interrupt?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, external RST/NMI pin is a nonmaskable interrupt( The function of the RST/NMI pin is configure
d in the control register for the watchdog timer module, WDTCTL).
10. How many cycles are used by MSP430, when reti instruction is executed?
a) 3
b) 4
c) 5
d) depends on the conditions
Answer: c
Explanation: When reti instruction is executed, five cycles are used because it firstly pops the stack register complet
ely and then takes the top of the stack into the PC to return to the next address of the main program.
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1. There are how many MSP430’s low power modes available in the chip?
a) two
b) three
c) four
d) five
Answer: d
Explanation: There are five low power modes available in the MSP430, out of which two are rarely employed in the
current devices.
2. Which of the following are the low power modes?
a) LPM0
b) LPM3
c) LPM4
d) All of the mentioned
Answer: d
Explanation: LPM0, LPM3, LPM4 all are the low power modes that are available in the MSP430.
3. Which of the following modes is also known as the RAM retention mode?
a) LPM0
b) LPM3
c) LPM4
d) All of the mentioned
Answer: c
Explanation: LPM4 is known as the RAM retention mode. Here, the CPU and all clocks are disabled, I ≈ 0.1A. The
device can be woken only by an external signal.
4. Waking a device simply means that switching that device’s operation from a low power mode to an active mode.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: When a device is operating in a low power mode, it can also be assumed that the device is sleeping, so
waking a device simply means to turn that device’s operation from a low power mode to an active mode.
5. When an interrupt is accepted, the contents of the status register are ___________
a) set
b) reset
c) remains the same
d) cant be said
Answer: d
Explanation: When an interrupt is accepted, the contents of the status register are cleared, it actually puts the process
or in the active mode.
6. Which of the following basic clock modules supplies clock signals to the MSP430?
a) ACLK
b) MCLK
c) SMCLK
d) All of the mentioned
Answer: a
Explanation: All of the mentioned options are correct. The basic clock module supplies the MSP430 with three cloc
k signals as follows:
7. _ _low_ power_mode_0() states the processor to __________
a) enable the interrupt
b) disable the interrupt
c) nothing
d) to go in an active mode
Answer: b
Explanation: _ _low_ power_mode_0() puts the processor in the LPM0 mode.
8. More power can be saved by using low_power mode 0 than low_power mode 3.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: More power is saved in low_ power mode 3.
9. _BIC_SR_IRQ() is used to _______________
a) set the particular bits of the SR
b) reset the particular bits of the SR
c) any of the above mentioned depending on the conditions
d) none of the mentioned
Answer: b
Explanation: _BIC_SR_IRQ() is used to clear the bits of the SR.
PSST! You better watch out, something's buggy above.
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1. Which of the following registers are related to port P1?
a) P1SEL
b) P1DIR
c) P1IES
d) All of the mentioned
Answer: d
Explanation: All of the mentioned registers are related to Port1.
2. A pull-up or pull-down resistor ___________
a) removes the full output drive on the output pin
b) gives only a feeble current through the pull-up to resistor
c) removes the full output drive on the output pin & gives only a feeble current through the pull-up to resistor
d) none of the mentioned
Answer: c
Explanation: A pull-up or pull-down resistor is used to remove the full output drive on the output pin. It also gives a
feeble current through the pull-up to a resistor.
3. P1.3 is the ___________
a) input CCI1A to Timer_A
b) is connected to the voltage reference VREF of SD16_A
c) is output TA0 from Timer_A
d) are digital inputs with pull-up resistors
Answer: b
Explanation: P1.3 is connected to the voltage reference VREF of SD16_A.
4. What actually is SD16_A?
a) it is an interrupt
b) it is a timer
c) it is an analog to Digital Converter
d) it is a serial communication module
Answer: c
Explanation: SD16_A is an analog to the digital module.
5. P1IE and P1IES are registers that are used to ___________
a) control the Port1 digital i/o ports
b) control the Port1 interrupts
c) control the Port1 serial communication interfaces
d) all of the mentioned
Answer: b
Explanation: P1IE and P1IES both registers are used to control the Port1 interrupts.
6. Unused pins must never be left unconnected in their default state as inputs.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Unused pins must never be left unconnected in their default state as inputs. This follows a general rule
that inputs to CMOS must never be left unconnected or “floating”.
7. Which of the following is an effect of a Schmidt trigger?
a) it turns slowly varying inputs, which might cause problems while they pass slowly through the undefined range of
input voltages, into abrupt, clean logical transitions
b) It eliminates the effect of noise on the input, provided that it is not large enough to span the gap between the upwa
rd and downward thresholds
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: Schmidt trigger has two of the above mentioned effects in it.
8. To ensure that a negative fluctuation does not trigger an unwanted downward transition by pulling the input down
through VIT−, we must choose
a) minimum hysteresis
b) maximum hysteresis
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: To ensure that a negative fluctuation does not trigger an unwanted downward transition by pulling the i
nput down through VIT−, we must choose a minimum hysteresis of 0.3V.
9. The SPDT switch can be used as a ___________
a) detecting circuit
b) debouncing circuit
c) devaluing circuit
d) degenerating circuit
Answer: b
Explanation: The SPDT(single pole, double pole) switch can be used as a debouncing circuit of a switch.
10. Debouncing can be carried out at a hardware as well as the software end?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Debouncing can be carried out at both the fronts both at the software as well as the hardware front, to c
arry out the process appropriately.
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1. What are the basic functions of a timer?
a) it provided a time delay
b) it can act as a counter
c) it can control the compare, capture mode
d) all of the mentioned
Answer: d
Explanation: Timers are used to provide a time delay, they can even act as a counter and control the compare capture
mode of a microcontroller.
2. Most of the MSP430’s devices have __________ number of timers in it.
a) three
b) four
c) five
d) seven
Answer: c
Explanation: MSP430 has mainly five types of timers in it. They are Watchdog Timer, Basic Timer1, Real clock Ti
me, Timer_A, Timer_B.
3. A Watchdog Timer can act as an interval timer?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: A Watchdog Timer can act as an interval timer if the protection is not needed for it.
4. Which out of the following is the main function of a Watchdog timer?
a) control the compare mode
b) control the capture mode
c) protection from failures to the system
d) all of the mentioned
Answer: c
Explanation: Its main function is to protect the system against malfunctions.
5. Basic Timer1 can provide __________
a) clock for the LCD
b) an internal timer
c) clock to the LCD and can & also used as an interval timer
d) none of the mentioned
Answer: c
Explanation: Basic Timer1 device is used to provide the clock to the LCD and can also be used as an interval timer.
6. LCD_A controllers make use of the Basic Timer1 timer for providing a clock to the LCD?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Basic Timer1 is not used in LCD_A controllers, because these provide an internal clock of its own to al
l of its devices.
7. Real time clock is an extension of Basic Timer1?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Real time clock is an extension of Basic Timer1 and is present in almost all devices for controlling its r
eal time clock.
8. Timer_A can be used to _________
a) generate interrupts
b) handle external inputs
c) drive outputs
d) all of the mentioned
Answer: d
Explanation: Timer_A can be used to generate the interrupts, handle the external inputs or for driving the outputs.
9. Time stamp inputs can be measured by a Timer_A?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, time stamp inputs can be measured by a Timer_A.
10. Timer_B includes _________
a) sampling inputs
b) driving outputs
c) sampling inputs & driving outputs
d) none of the mentioned
Answer: b
Explanation: Timer_B is used for driving the outputs as with Timer_A but it lacks the property of Timer_A of sampl
ing inputs.
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1. The watchdog counts up and resets the MSP430 when it reaches the limit?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The watchdog timer is used for the protection of the device. It keeps a track at the counter so that the c
ode doesn’t reach an infinite unending loop. So it actually resets the counter before this particular condition.
2. Which of the following is correct about WDTCTL?
a) it is a 16 bit register
b) it is guided against accidental writes that require a password
c) a reset will occur if a value with an incorrect password is written to WDTCTL
d) all of the mentioned
Answer: d
Explanation: WDTCTL is a 16 bit register that is used for protecting the microcontroller. It actually resets the value
when an incorrect password is written to WDTCTL.
3. WDTNMI is found in the _________
a) higher byte of WDTCTL
b) lower byte of WDTCTL
c) its first four bits
d) its last four bits
Answer: b
Explanation: WDTNMI is the fifth bit of the WDTCTL register.
4. Which of the following bits reads 0 under normal conditions but goes 1 when it wants to initiate some action?
a) WDTNMI
b) WDTHOLD
c) WDTTMSEL
d) WDTCNTCL
Answer: d
Explanation: WDTCNTCL is the bit that reads 0 under normal conditions but goes 1 when it wants to initiate some a
ction like resetting the counter.
5. WDTISx bits control the _________
a) period of the clock
b) act as “Nonmaskable Interrupts”
c) stop the watchdog timer
d) start the watchdog timer
Answer: a
Explanation: WDTISx bits of the WDTCTL register is responsible for controlling the period of the clock.
6. The process of setting the WDTCNTCL bit in WDTCTL is through
a) petting
b) feeding
c) kicking
d) all of the mentioned
Answer: d
Explanation: the process of setting the WDTCNTCL bit in the WDTCTL register is by the processes like petting, fee
ding and kicking.
7. What is the function of this instruction “WDTCTL = WDTPW | WDTCONFIG”, where **#define WDTCONFIG
(WDTCNTCL|WDTSSEL)**
a) it sets the watchdog timer
b) it configures and clears the watchdog timer
c) it stops the watchdog timer
d) it configures and sets the watchdog timer
Answer: b
Explanation: WDTCTL = WDTPW | WDTCONFIG instruction is used to clear and configure the watchdog timer of
a microcontroller.
8. Is this instruction correct?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: No WDTCTL_bit.WDTCNTCL = 1; is an incorrect way of setting the bits of the WDTCTL register be
cause it violates the password protection.
9. Setting the WDTTMSEL bit of the WDTCTL register makes the watchdog timer act as
a) interrupt
b) communication device
c) converter
d) interval timer
Answer: d
Explanation: The WDTTMSEL bit of the WDTCTL register makes the watchdog timer act as the interval timer.
10. WDTIFG flag gets cleared if
a) if is interrupt had occurred
b) if the interrupt is serviced
c) if there can be no interrupt
d) all of the mentioned
Answer: b
Explanation: WDTIFG flag gets cleared if the interrupt is serviced so that again the interrupt can occur.
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1. Which of the following is true about the FRFQx bits of the BTCTL register?
a) these bits are used for clock input
b) these bits are used for setting a particular frequency fLCD
c) these bits start the timer
d) these bits stop the timer
Answer: b
Explanation: FRFQx bits of the BTCTL register are used for selecting a particular frequency fLCD varying from fA
CLK/256 to fACLK/32.
2. Timer1 is responsible for ________
a) providing a clock to the LCD module
b) cause an interrupt
c) a pulse for the RTC
d) all of the mentioned
Answer: d
Explanation: Timer1 is responsible for providing a clock for the LCD module. It can also cause an interrupt if the B
TIE bit is high. It also provides the clock to the RTC.
3. For fACLK = 32 KHz, what would be the desirable range of fLCD?
a) 2hz-256hz
b) 12hz-512hz
c) 128hz-1khz
d) 1khz-10khz
Answer: c
Explanation: For fACLK = 32khz, the desirable range of the fLCD is the fACLK/256 to fACLK/32. This value com
es out to be in the range of 128hz-1khz.
4. Normally BTCNT1 only function is to provide a prescalar for the BNTCNT2?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: LCD’s controllers nowadays don’t require a clock pulse, so the only main function of the BTCNT1 is t
o provide a prescalar for the BNTCNT2.
5. BTCNT2 provides 2 output signals?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: BNTCNT2 has no outputs. Instead, it raises the BTIFG flag at a frequency determined by the BTIPx bi
ts.
6. RTCSEC, RTCMIN, RTCDOW etc. are the bytes of a set of registers that are used to store
a) seconds
b) minutes
c) days of a week
d) all of the mentioned
Answer: d
Explanation: The current time and date are held in a set of registers that contain the following bytes like RTCSEC, R
TCMIN, RTCHOUR, RTCDOW etc.
7. The RTC module is configured in the calendar mode if __________
a) RTCMODE bit is reset
b) RTCMODE is set
c) RTCRDY is reset
d) RTCRDY is set
Answer: d
Explanation: Calendar mode is selected when RTCMODE is set.
8. The RTC module makes use of the Basic Timer1 because of _________
a) its bytes are controlled in the Basic Timer1 register
b) it is started by timer1
c) it is ended by basic timer1
d) it needs a clock pulse of 1hz that is provided by basic timer1
Answer: c
Explanation: The RTC module requires a clock of worth 1hz that is provided by basic timer1 so that why it makes u
se of basic timer1.
9. IF RTCIE interrupt is generated then _________
a) BTIFG flag is set
b) RTCFG flag is set
c) Both flags are set
d) None of the flag is set
Answer: c
Explanation: When RTCIE interrupt is generated then both BTIFG and RTCFG flags are set simultaneously.
PSST! You better watch out, something's buggy above.
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1. All channels within Timer_A share the same timer block?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: There is only one TAR in Timer_A so all of its channels share the same timer block.
2. Timer_A has _________
a) RTC module in it
b) Compare/ capture channel
c) Communication channel
d) Converter channel
Answer: b
Explanation: Timer_A has compared/ capture channel inbuilt inside it.
3. TACLK and INCLK are _________
a) internally generated clock pulses
b) externally fed clock pulses
c) of no use in Timer_A
d) very slow
Answer: b
Explanation: TACLK and INCLK clock pulses are the externally fed pulses that are required by the Timer_A.
4. In continuous mode of the counter _________
a) counter moves from 0000-ffff
b) counter moves from ffff-0000-ffff
c) counter moves from 0000-ffff and then again returns to 0
d) all of the mentioned
Answer: c
Explanation: In a continuous mode of the counter, the counter firstly increases from 0000-ffff, then after this value t
he roll over condition comes and it again gets started from 0000. This particular mode is very useful for capturing in
puts.
5. TACLR bit in TACTL _________
a) clear the interrupt flag
b) clear the status flags
c) clear the count in TAR
d) all of the mentioned
Answer: c
Explanation: TACLR bit in TACTL clears the count in the TAR.
6. TAxCCTLn is a _________
a) set of 2 bits used for selecting the mode of operation of the timer
b) a register of 8 bits used for giving the count to the timer
c) a register of 16 bits used to select the compare/capture channel of the Timer_Ax
d) a register of 16 bits used to cause the timer interrupt
Answer: c
Explanation: TAxCCTLn is a register of 16 bits used to select the compare/capture channel of the Timer_Ax.
7. CCI1B comes from _________
a) ACLK
b) CAOUT
c) SCLK
d) TACLK
Answer: b
Explanation: CCI1B comes from CAOUT.
8. Which of the following parameters are given by the TAxCCRn?
a) Capture/compare input. The selected input signal can be read by this bit
b) Synchronized capture/compare input. The selected CCI input signal is latched with the EQUx signal and can be re
ad from this bit
c) Holds the data for the comparison to the timer value in the Timer_A Register, TAR
d) None of the mentioned
Answer: c
Explanation: Compare mode: TAxCCRn holds the data for the comparison to the timer value in the Timer_A Regist
er, TAR.
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1. Why Timer_B is not considered as most suitable one for receiving asynchronous signals?
a) because of the absence of the TBOUTH input pin
b) because of the presence of the TBOUTH input pin
c) because of the absence of the SCCI bit
d) because of the presence of the SCCI bit
Answer: c
Explanation: The SCCI bit is absent in the Timer_B which means that the sampling mode is absent in it that’s why it
is considered as unsuitable for receiving asynchronous signals.
2. There is double buffering in the immediate mode?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Immediate mode offers no double buffering condition. As here, values are copied to TBCLn as soon as
they are written to TBCCRn.
3. Double buffering protects channel 0.
a) as it acts as the limit in the Up and up/down modes
b) it doesn’t actually protect it
c) as it does not accept the inputs
d) none of the mentioned
Answer: a
Explanation: Double buffering protects channel 0 as it acts as the limit in the Up and Up/Down modes.
4. Timer_B has _________
a) three serial communication ports
b) seven LCD driver
c) seven compare/capture channels
d) three LED driver ports
Answer: c
Explanation: Timer_B has seven compare/capture channels.
5. The capture/compare registers TBCCRn are double-buffered when used for compare events?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The capture/compare registers TBCCRn are double-buffered when used for compare events.
6. The length of TBR can be programmed to be _________
a) 8 bits
b) 12 bits
c) 16 bits
d) all of the mentioned
Answer: d
Explanation: The length of TBR can be programmed to be 8, 12, 16 or 10 bits long.
7. TBOUTH can pin can be used to _________
a) values are moved from one place to another
b) the length of the number of bits is selected by this register
c) it can be used to put all the outputs of the Timer_B register in the high impedance state
d) it can be used for outputting the input values of the timers
Answer: c
Explanation: TBOUTH pin is used to put all the outputs of the Timer_B register in the high impedance state by a hig
h external signal applied to this pin.
8. TBCLn provided in each channel is actually _________
a) a comparator
b) compare latch
c) controller
d) control logic
Answer: b
Explanation: TBCLn is actually a compare latch that is provided in its every channel.
9. When TBR counts to zero?
a) TBCLn is updated from TBCCRn
b) CLLDx is updated to TBCCTLn
c) CLLDx is updated to TBCCRn
d) TBCLn is updated to CLLDx
Answer: a
Explanation: When TBR counts to zero, TBCLn is updated from TBCCRn.
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1. Which of the following is the analog to digital converter that is present in the MSP430 based processors?
a) comparator
b) successive approximation ADC
c) sigma delta ADC
d) all of the mentioned
Answer: d
Explanation: A comparator module, a successive approximation ADC module and a sigma delta ADC converters are
found in the MSP based processors.
2. Higher resolution along with the slow speed is given by which ADC module?
a) comparator
b) successive approximation ADC
c) sigma delta ADC
d) all of the mentioned
Answer: c
Explanation: Higher resolution along with the slow speed is given by the sigma delta ADC module.
3. The technical terms that help us in differentiating between converters are:
a) resolution
b) accuracy
c) precision
d) all of the mentioned
Answer: d
Explanation: While selecting the converter, necessary for our work we had to take care of the factors like resolution,
accuracy and precision in it.
4. The number of repeated closeness to the true value is accounted by
a) resolution
b) accuracy
c) precision
d) all of the mentioned
Answer: c
Explanation: The degree of closeness of the measured value to the actual true value is its accuracy, while on the othe
r hand the measure of the repeated accuracy is termed as the precision.
5. Resolution is _________
a) change in measured value from the true value
b) the amount of change in the input value for the corresponding change of 1 unit in the output value
c) as the measure of the repeated accuracy
d) all of the mentioned
Answer: b
Explanation: Resolution is defined as the amount of change in the input value for the corresponding change of 1 unit
in the output value.
6. The process of reduction of a continuous input to a discrete output is
a) levelling
b) signalling
c) quantization
d) converting
Answer: c
Explanation: The process of reduction of a continuous input to a discrete output is called as quantization.
7. Which of the following functions can be used for converting the nearest integer to its argument?
a) int
b) mint
c) uint
d) nint
Answer: d
Explanation: nint is the function that is priorly used for converting the nearest integer to its argument.
8. Integral nonlinearity is termed as
a) process of reduction of a continuous input to a discrete output
b) change in measured value from the true value
c) maximum deviation between this corrected staircase and the actual transfer characteristic
d) the function used in the quantization
Answer: c
Explanation: Integral nonlinearity is termed as the maximum deviation between this corrected staircase and the actua
l transfer characteristic.
9. The SNR_______ with the increase of the number of bits.
a) remains constant
b) goes up
c) goes down
d) goes asymmetrically
Answer: b
Explanation: The SNR goes up with the number of bits.
10. The intervals between the samples are obtained from _________
a) Fs
b) Ts
c) Us
d) Ks
Answer: b
Explanation: The intervals between the samples is obtained by Ts that is equal to 1/fs.
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1. Comparator_A+ is controlled by which of the following peripheral registers?
a) CACTL1
b) CACTL2
c) CACTL1 & CACTL2
d) None of the mentioned
Answer: c
Explanation: Comparator_A+ is controlled by the CACTL1 and the CACTL2 registers.
2. CAON bit is used to ___________
a) start a timer
b) start an A/D conversion
c) switch on the comparator module
d) switch on the bit transmission
Answer: c
Explanation: CAON bit is used to switch on the comparator module namely, Comparator_A+.
3. P2CA4-P2CA0 bits are used for _______
a) giving the power supply to the comparator module
b) for selecting the mode of operation of the comparator
c) for connecting the non inverting inputs to the CA0-CA2 pins
d) all of the mentioned
Answer: c
Explanation: P2CA4-P2CA0 bits are used for connecting the non inverting inputs to the CA0-CA2 pins.
4. CAREFx bits are used for _______
a) inputting a positive reference voltage
b) inputting a negative reference voltage
c) selecting the internal reference voltage
d) all of the mentioned
Answer: c
Explanation: CAREFx bits are used for selecting the appropriate reference voltage for the comparator.
5. Which of the following bits are not actually associated with the comparator module?
a) CAREFx
b) CLLDx
c) CAON
d) CAIFG
Answer: b
Explanation: CLLDx bit is related to the Timer_2 module. All others are related to the comparator module.
6. Flag CAIFG is raised,
a) at a low level triggered pulse
b) at a high level triggered pulse
c) at the falling and rising edge of the pulse
d) at the falling or rising edge of the pulse
Answer: d
Explanation: Flag CAIFG is raised, at the falling or rising edge of the pulse that is selected by the CAIES bit.
7. Setting a bit in the Port Disable register CAPD causes the circuits for the usual digital input and output buffers to
be disconnected from the appropriate pin.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Setting a bit in the Port Disable register CAPD causes the circuits for the usual digital input and output
buffers to be disconnected from the appropriate pin.
8. Which bit is used for exchanging the two inputs of the comparator and invert its output to compensate?
a) CAIFG
b) CASHORT
c) CAPD
d) CAEX
Answer: d
Explanation: CAEX is used for exchanging the two inputs of the comparator and invert its output to compensate.
9. Changes in Vcc changes the value of V+?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: When some variation is made in the value of Vcc, in the same manner, itself the value of the V+ chang
es because, the voltage from the potential divider is proportional to Vcc. This changing effect can be reduced if the s
imilar change takes place in the value of V- itself.
10. The relaxation oscillator circuit helps in _______
a) calculating the duration single RC transient
b) setting the reference voltage
c) setting the clock frequency
d) calculating the conversion speed
Answer: a
Explanation: The relaxation oscillator is a circuit that with the help of charging and discharging of an oscillator, help
us in calculating the duration of the single RC transient.
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1. The successive approximation converters have a resolution of _________
a) 8-10 bits
b) 10-12 bits
c) 12-16 bits
d) 16-32 bits
Answer: b
Explanation: The successive approximation converters have a resolution of about 10-12 bits in it.
2. In SAR based conversions, each bit typically requires one clock cycle (sometimes two) to make a comparison and
set up the new voltage.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: In SAR based conversions, each bit typically requires one clock cycle (sometimes two) to make a com
parison and set up the new voltage.
3. The main operations that are basically performed in a SAR ADC are?
a) logic to control the operation
b) some way of generating the voltages, for comparison
c) logic to control the operation and finding some way of generating the voltages for comparison
d) none of the mentioned
Answer: c
Explanation: The main operations that are basically performed in a SAR ADC are the logic to control the operation a
nd finding some way of generating the voltages, for comparison.
4. Usually, a capacitor is inserted between an analog input and the ground because
a) it blocks the analog voltage
b) it suppresses the noise
c) it increases the gain
d) none of the mentioned
Answer: b
Explanation: A capacitor is inserted between the analog input and the ground because it suppresses the noise.
5. ADC10 and ADC12 are _________
a) The converters
b) SAR modules available in the MSP430
c) Sigma delta modules available in the MSP430
d) Comparator modules available in the MSP430
Answer: b
Explanation: ADC10 and ADC12 are the SAR modules available in the MSP430.
6. ADC10 needs external capacitors on its voltage reference.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: ADC12 needs external capacitors on its voltage reference as compared to the ADC10 module.
7. ADC10CTL0 and ADC10CTL1 are registers
a) for controlling SAR module
b) for controlling the sigma delta module
c) for controlling the comparator module
d) all of the mentioned
Answer: a
Explanation: ADC10CTL0 and ADC10CTL1 are the registers that are used for controlling the SAR module in the
MSP430.
8. While conversion is in progress, which of the flag is affected.
a) ADC10ON
b) ADC10MEM
c) ADC10BUSY
d) ADC10DF
Answer: c
Explanation: While conversion is in progress, then ADC10BUSY flag is set.
9. ADC10SHTx bits allow_________cycles of the ADC10CLK.
a) 4
b) 8
c) 16
d) all of the mentioned
Answer: d
Explanation: ADC10SHTx bits allow 4,8,16 and 64 cycles of the ADC10CLK.
10. The input to the ADC10 is selected from_______bits of the ADC10CTL1 register?
a) INCHx
b) ADC10SC
c) ADC10ON
d) ENC
Answer: a
Explanation: The input to the ADC10 is selected from the INCHx bits of the ADC10CTL1 register.
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1. The basic idea behind the sigma delta converter is that
a) to carry out the conversion
b) to carry out communication
c) to reduce the circuit to its simplest way possible and then carry out the conversion
d) all of the mentioned
Answer: c
Explanation: The main idea behind the sigma delta converter is that to reduce the circuit to its simplest way possible
and then carry out the conversion.
2. Sigma delta converter is a __________
a) 1 bit converter
b) 2 bit converter
c) 3 bit converter
d) 4 bit converter
Answer: a
Explanation: Sigma delta converter is a 1 bit converter.
3. Sigma delta converter is having good resolution.
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Sigma delta converter is having poor resolution quality.
3. Oversampling ratio is defined as the _________
a) final frequency
b) oversampling frequency
c) oversampling frequency/final frequency
d) final frequency/oversampling frequency
Answer: c
Explanation: Oversampling ratio is defined as the ration of the oversampling frequency fm to the final frequency fs.
4. Here the word sigma represents _________
a) subtraction
b) differentiation
c) integration
d) none of the mentioned
Answer: c
Explanation: In a sigma delta converter, sigma word represents that the output obtained from the delta function is get
ting integrated.
5. SD16_A features are controlled by _________
a) memory mapped registers
b) register mapped registers
c) data mapped registers
d) none of the mentioned
Answer: a
Explanation: SD16_A features are controlled by the memory mapped registers.
6. The second part of the ADC handles purely digital signals.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The second part of the ADC handles purely digital signals.
7. The second part of the ADC’s output is in the form of _________
a) the fast stream of single bits
b) the fast stream of multiple bits
c) the slow stream of single bits
d) the slow stream of multiple bits
Answer: d
Explanation: The second part of the ADC take in fast stream of single bit and give out a slow stream of multiple bit
values.
8. The filtered digital signal is then decimated to
a) reduce the rate of samples from fm to fs
b) reduce the rate of samples from fs to fm
c) increase the rate of samples from fm to fs
d) increase the rate of samples from fs to fm
Answer: a
Explanation: The filtered digital output is then decimated in order to reduce the rate of samples from fm to fs.
9. Decimated means _________
a) multipled by 10
b) multiplied by 100
c) divided by 10
d) divided by 100
Answer: c
Explanation: Decimated means to divide the result by 10.
10. The SD16 has a second-order modulator with a _________
a) sinc filter
b) sinc2 filter
c) sinc3 fiter
d) rect filter
Answer: c
Explanation: The SD16 has a second-order modulator with a sinc3 filter.
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1. What actually is a bit bagging?
a) it actually refers to the technique of assigning the bits with their inputs
b) a technique by which an MSP430 can communicate through hardware
c) a technique by which MSP430 can communicate through software
d) a technique through which conversion becomes possible
Answer: c
Explanation: Bit bagging is the technique through which a processor can communicate to its associate partners when
an appropriate hardware is not available for its purpose. This communication is made possible through the software.
2. SPI, I2C, Asynchronous serial communication are the means of communicating a processor with its associate part
ners?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: SPI, I2C, Asynchronous serial communication are the means for the processor by which communicatio
n is made possible.
3. All digital communications don’t require any clock.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Clock is the prior need for any communication to occur. This is because synchronization is maintained
with the help of a clock.
4. SPI needs______ wires than I2C?
a) less
b) same
c) more
d) depends on the conditions
Answer: c
Explanation: In SPI, there is no control of transmission in software—no addresses or acknowledgment, that’s why it
requires more amount of wires.
5. USI handles _________
a) SPI
b) I2C
c) SPI & I2C
d) None of the mentioned
Answer: c
Explanation: USI(Universal Serial Interface) supports both the types of synchronous communication i.e. SPI and I2
C.
6. USCI consists of _________
a) one channel
b) two channels
c) three channels
d) four channels
Answer: b
Explanation: USCI consists of mainly two channels, A and B. These are largely independent but share a few register
s and interrupt vectors.
7. LIN is enabled in which of the following channels?
a) A
b) B
c) C
d) D
Answer: a
Explanation: Channel A is the asynchronous receiver/ transmitter channel. It can detect the baud rate of an incoming
signal, which enables its use on a local interconnect network (LIN).
8. Can one device have more than one USC interfaces?
a) yes
b) no
c) depends on the conditions
d) cant be said
Answer: a
Explanation: Yes, one device can have more than one USC interfaces. There is a small difference because the interru
pt flags and enable bits for the “0” modules are in a special function registers IFG2 and IE2, while those for the “1”
modules are in their own registers, UC1IFG and UC1IE.
9. Which of the following conditions is more difficult to attain?
a) synchronous masters
b) synchronous slaves
c) asynchronous masters
d) asynchronous slaves
Answer: d
Explanation: Synchronous slaves are the most difficult to attain because the problem is that the slave must react quic
kly when a clock transition arrives from the master.
10. Timer_A is used in _________
a) SPI
b) I2C
c) Asynchronous Serial Communication
d) All of the mentioned
Answer: c
Explanation: Timer_A is used in the Asynchronous Serial Communication.
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1. Is SPI a full duplex technique?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, SPI is a technique where a data can be transmitted/ received in both the directions.
2. The concept of SPI is based on __________
a) two counters
b) four flip flops
c) two shift registers
d) four steady state machines
Answer: c
Explanation: The concept of the SPI is based on the two shift registers, one for the transmitter and the other is there f
or the receiver terminal.
3. Writing on the trailing edge of the clock pulse and reading on the leading edge of the clock pulse is done when
a) CPHA is set
b) CPHA is reset
c) CPOL is set
d) CPOL is reset
Answer: b
Explanation: When CPHA is reset to zero, then writing on the trailing edge of the clock pulse and reading on the lea
ding edge of the clock pulse.
4. When CPOL=1 then,
a) clock idles high between transfers
b) clock idles low between transfers
c) bit idles high between transfers
d) bit ideals low between transfers
Answer: a
Explanation: When CPOL=1, clock idles high between transfers.
5. Is CPKH and CPOL the same.
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: CPKL=CPOL and CPKH=(not CPHA).
6. SPI with the USI can be selected by ________
a) setting the USII2C bit in the register USICTL1
b) clearing the USII2C bit in the register USICTL1
c) setting the USIPE5–7 bits in USICTL0
d) clearing the USIPE5–7 bits in USICTL0
Answer: b
Explanation: SPI with the USi can be selected by clearing the USII2C bit in the register USICTL1.
7. SCLK, SDO, and SDI are found ___________ on F20x3.
a) P1.0-2
b) P1.2-4
c) P1.4-6
d) P1.5-7
Answer: d
Explanation: SCLK, SDO, and SDI are found at P1.5-7 on F20x3.
8. Transmission and reception are made at a time in SPI?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Transmission and reception occur at a time in SPI. This means that a value is received only if the trans
mitter is active.
9. When the buffer is ________ the low power mode is__________
a) empty, reset
b) having one byte, reset
c) full, reset
d) empty, two
Answer: c
Explanation: When the buffer is full, the low power mode is cleared.
10. Falling edge of the SS pin denotes ________
a) end of the transfer
b) starts a new transfer
c) selects a new master
d) none of the mentioned
Answer: b
Explanation: Falling edge of the SS pin denotes the start of a new transfer over SPI.
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1. The I2C bus uses which of the following lines?
a) CLK
b) MISO
c) SDA
d) All of the mentioned
Answer: c
Explanation: The I2C bus uses only two lines. They are SDA and SCL.
2. I2C is a faster means of data transfer than SPI?
a) yes
b) no
c) depends on the conditions
d) cant be said
Answer: b
Explanation: I2C is a slower means of transfer than SPI because here only one line is there for the two way commun
ication to occur.
3. Each slave has its unique address.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, in I2C protocol each slave has its own unique address, in order to differentiate it from others.
4. Pull-up resistors Rp keep the lines at VCC when _____________
a) all the drivers are active
b) none of the drivers are active
c) some the drivers are at sleep
d) none of the drivers is at sleep
Answer: b
Explanation: Pull-up resistors Rp keep the lines at VCC when all of the drivers are active.
5. Rising edge on SDA while SCL is high denotes __________
a) start condition (S)
b) stop condition (P)
c) transfer in progress
d) none of the mentioned
Answer: b
Explanation: Rising edge on SDA while SCL is high denotes the stop condition of the transfer.
6. Which of the following is an issue while programming I2C using the software?
a) open-collector output
b) open-drain output
c) totem pole output
d) all of the mentioned
Answer: b
Explanation: There are two main issues while programming I2C using software, they are the open-drain output and t
he detection of start and stop conditions.
7. Which of the following is the slave to be addressed when a device acts as a master?
a) UCB0I2COA
b) UCB0I2CSA
c) UCB0I2CIE
d) All of the mentioned
Answer: b
Explanation: UCB0I2CSA is the slave to be addressed when a device acts as a master.
8. Is baud rate selected in I2C?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, baud rate is also selected in the I2C module, as is the case with the SPI module.
9. How is I2C with USI different from I2C with USI_B?
a) there is only one common pin between the two devices
b) here in this case no synchronization is important
c) the outputs of SDA and SCL are open drain
d) none of the mentioned
Answer: c
Explanation: I2C is different in USI than that of USI_B module because here in this module, the output pins SDA an
d the SCL are open drains in nature.
10. UCB0RXIFG is set when ________
a) complete byte is acknowledged
b) complete byte is transmitted
c) complete byte is received
d) none of the mentioned
Answer: c
Explanation: UCB0RXIFG is set when the complete byte sent via I2C is received.
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1. Asynchronous serial communication usually requires two wires for each direction plus a common ground.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Asynchronous serial communication usually requires only a single wire for each direction plus a comm
on ground.
2. In an asynchronous mode of transmission, usually the data is sent along with the
a) the start bit
b) the stop bit
c) the start & stopbit
d) none of the mentioned
Answer: c
Explanation: In an asynchronous mode of transmission, both the start and the stop bits are present that are basically
used for intimating the other terminal that whether the data had received correctly the other destination or not.
3. The _____ rate gives the frequency at which the bits are transmitted on the line.
a) bit rate
b) packet rate
c) baud rate
d) data rate
Answer: c
Explanation: Baud rate is the rate which determines us the frequency at which the bits are transmitted on the line.
4. Baud rate is the reverse of the ________
a) baud time
b) baud period
c) bit time
d) bit period
Answer: b
Explanation: Baud rate is the reverse of the baud period.
5. Clock is transmitted in the asynchronous communication?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: No clock is transmitted in the asynchronous communication, so the transmitter and the receiver are allo
wed to work independently at their own terminals.
6. A framing error occurs is the bit is ________
a) high
b) low
c) same
d) changed
Answer: b
Explanation: Framing error occurs if the bit is low.
7. What is the non return to zero format?
a) the bits are either high or low and have no gaps between them
b) the bits are either high or low and have gaps between them
c) the bits are high and have gaps between them
d) the bits are low and have no gaps between them
Answer: a
Explanation: Non-return to zero format represents a format in which the bits are either high or low and have no gaps
between them.
8. LSB is sent first in case of the non return to zero format.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: In non-return to zero format, normally LSB is sent first.
9. There are _______ clocks in the USCI_A.
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: they are 3 clocks in the USCI_A. They are BRCLK, BITCLK and BITCLK16.
10. BITCLK16 is the ________
a) sampling clock in the undersampling mode
b) sampling clock in the oversampling mode
c) quantising clock in the undersampling mode
d) quantising clock in the oversampling mode
Answer: b
Explanation: BITCLK16 is the sampling clock in the oversampling mode.
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Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Date-16/06/2021
Subject Name-KCS-403-Microprocessor_CSE-Semester 4
UNIT-1
1. In 8085 microprocessor, the RST6 instruction transfer programme execution
to following location
a. 0030H
b. 0024H
c. 0048H
d. 0060H
Answer: (a).0030H
2. HLT opcode means
a. load data to accumulator
b. store result in memory
c. load accumulator with contents of register
d. end of program
Answer: (d).end of program
3. What is SIM?
a. Select interrupt mask
b. Sorting interrupt mask
c. Set interrupt mask
d. None of these
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Answer: (c).Set interrupt mask
4. The ROM programmed during manufacturing process itself is called
a. MROM
b. PROM
c. EPROM
d. EEPROM
Answer: (a).MROM
5. A field programmable ROM is called
a. MROM
b. PROM
c. FROM
d. FPROM
Answer: (b).PROM
6. The operations executed by two or more control units are referred as
a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer: (b).Macro-operations
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
7. Program counter in a digital computer
a. Counts the numbers of programs run in the machine.
b. Counts the number of times a subroutine is called.
c. Counts the number of times the loops are executed.
d. Points the memory address of the next instruction to be fetched.
Answer: (d).Points the memory address of the next instruction to be fetched.
8. At the beginning of a fetch cycle, the contents of the program
counter are
a. incremented by one.
b. transferred to address bus.
c. transferred to memory address register.
d. transferred to memory data register.
Answer: (c).transferred to memory address register.
9. Which components are NOT found on chip in a microprocessor but may be
found on chip in a micro-controller?
a. SRAM & USART
b. EPROM & PORTS
c. EPROM, USART & PORTS
d. SRAM, EPROM & PORTS
Answer: (c).EPROM, USART & PORTS
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
10. For the purpose of data processing an efficient assembly language
programmer makes use of the general purpose registers rather than
memory. The reason is
a. the set of instructions for data processing with memory is limited
b. data processing becomes easier when register are used
c. more memory related instructions are required
d. data processing with registers takes fewer cycles than that with memory
Answer: (d).data processing with registers takes fewer cycles than that with memory
11. The first machine cycle of an instruction is always
a. A memory read cycle
b. A fetch cycle
c. An I/O read cycle
d. A memory write cycle
Answer: (b).A fetch cycle
12. The output data lines of microprocessor and memories are usually tristated
because
a. More than one device can transmit information over the data bus by enabling
only one device at a time
b. More than one device can transmit over the data bus at the same time
c. The data line can be multiplexed for both input and output
d. It increases the speed of data transfer over the data bus
Answer: (a).More than one device can transmit information over the data bus by
enabling only one device at a time
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13. The correct sequence of steps in the instruction cycle of a basic computer is
a. Fetch, Execute, Decode and Read effective address.
b. Read effective address,Decode,Fetch and Execute.
c. Fetch, Decode, Read effective address and ,Execute.
d. Fetch, Read effective address, Decode and Execute.
Answer: (c).Fetch, Decode, Read effective address and ,Execute.
14. The register which holds the information about the nature of results of
arithmetic and logic operations is called as
a. Accumulator
b. Condition code register
c. Flag register
d. Process status register
Answer: (c).Flag register
15. Consider the following statements:
Arithmetic Logic Unit (ALU)
1.Performs arithmetic operations
2.Performs comparisons.
3.Communicates with I/O devices
4.Keeps watch on the system
Which of these statements are correct?
a. 1, 2, 3 and 4
b. 1, 2 and 3
c. 1 and 2 only
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d. 3 and 4 only
Answer: (c).1 and 2 only
16. Ready pin of microprocessor is used
a. to indicate that microprocessor is ready to receive inputs
b. to indicate that microprocessor is ready to receive outputs
c. to introduce wait state
d. to provide direct memory access
Answer: (c).to introduce wait state
17. Both the ALU and control section of CPU employ which special purpose
storage location?
a. Buffers
b. Decoders
c. Accumulators
d. Registers
Answer: (c).Accumulators
18. A high on RESET OUT signifies that
a. all the registers of the CPU are being reset
b. all the registers and counters are being reset
c. all the registers and counters are being reset and this signal can be used to
reset external support chip
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d. processing can begin when this signal goes high
Answer: (c).all the registers and counters are being reset and this signal can be
used to reset external support chip
19. In a vector interrupt
a. the branch address is assigned to a fixed location in memory
b. the interrupting source supplies the branch information to the processor
through an interrupt vector
c. the branch address is obtained from a register in the processor
d. none of the above
Answer: (a).the branch address is assigned to a fixed location in memory
20. The content of the A15-A8 (higher order address lines) while executing “IN
8-bit port address” instruction are
a. same as the content of A7-A0
b. irrelevant
c. all bits reset (i.e. 00H)
d. all bits set (i.e. FFH)
Answer: (a).same as the content of A7-A0
21. Which one of the following interrupt is only level triggering?
a. TRAP
b. RST 7.5
c. RST 6.5 and RST 5.5
d. RST 6.5
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Answer: (c).RST 6.5 and RST 5.5
22. Which one of the following instruction may be used to clear the
accumulator content irrespective of its initial value?
a. CLR A
b. ORA A
c. SUB A
d. MOV A, 00H
Answer: (c).SUB A
23. ___________ signal prevent the microprocessor from reading the same data
more than one.
a. pipelining
b. handshaking
c. controlling
d. signaling
Answer: (b).handshaking
24. Data transfer between the microprocessor for peripheral takes place
through __________.
a. I/O port
b. input port
c. output port
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d. multi port
Answer: (a).I/O port
25. 8255A operates with ________ power supply.
a. +5V
b. -5V
c. -10V
d. +10V
Answer: (a).+5V
26. The _______ allow data transfer between memory and peripherals.
a. DMA technique
b. Microprocessor
c. Register
d. Decoder
Answer: (a).DMA technique
27. Expansion of SPGA is _________.
a. Staggered Pin Grid-Array package
b. Staggered Point Grid-Array package
c. Staggered Plus Grid-Array package
d. Staggered per grid-Array package
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Answer: (a).Staggered Pin Grid-Array package
28. Pentium-pro processor design implements________ micro architecture.
a. P2
b. P4
c. P6
d. P8
Answer: (c).P6
29. The number of hardware chips needed for multiple digit display can be
minimized by using the technique called ______.
a. interfacing
b. multiplexing
c. demultiplexing
d. multiprocessing
Answer: (b).multiplexing
30. An RS-232 interface is ____________.
a. a parallel interface
b. a serial interface
c. printer interface
d. a modem interface
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Answer: (b).a serial interface
31. Expansion for DTE is ______.
a. data terminal equipment
b. data trap equipment
c. data text equipment
d. data terminal extension
Answer: (a).data terminal equipment
32. Compared with RS-232, USB is faster and uses___________.
a. medium voltage
b. higher voltage
c. lower voltage
d. None of the above
Answer: (c).lower voltage
33. Expansion for HMOS technology is _______.
a. high level mode oxygen semiconductor
b. high level metal oxygen semiconductor
c. high performance medium oxide semiconductor
d. high performance metal oxide semiconductor
Answer: (d).high performance metal oxide semiconductor
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34. RIM is used to check whether, the ___________.
a. write operation is done or not
b. interrupt is Masked or not
c. interrupt is Masked
d. interrupt is not Masked
Answer: (b).interrupt is Masked or not
35. What does microprocessor speed depends on?
a. clock
b. data bus width
c. address bus width
d. signal bus
Answer: (c).address bus width
36. The advantage of memory mapped I/O over I/O mapped I/O is _________
a. faster operation
b. many instructions supporting memory mapped I/O
c. require a bigger address decoder
d. all the above
Answer: (d).all the above
37. In 8279 Status Word, data is read when ________ pins are low, and write to
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the display RAM with ____________ are low.
a. A0, CS, RD & A0, WR, CS
b. CS, WR, A0 & A0, CS, RD
c. A0, RD & WR, CS
d. CS, RD & A0, CS
Answer: (a).A0, CS, RD & A0, WR, CS
38. In 8279, the keyboard entries are de bounced and stored in an _________,
that is further accessed by the CPU to read the key codes.
a. 8-bit FIFO
b. 8-byte FIFO
c. 16 byte FIFO
d. 16 bit FIFO
Answer: (b).8-byte FIFO
39. For the most Static RAM the write pulse width should be at least
a. 10 ns
b. 60 ns
c. 300 ns
d. 350 ns
Answer: (b).60 ns
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40. Pentium-I, Pentium-II, Pentium-III and Pentium-IV are recently
introduced microprocessor by__________.
a. Motorala
b. Intel
c. Stephen Mors
d. HCL
Answer: (b).Intel
41. The address bus flow in __________.
a. bidirection
b. unidirection
c. mulidirection
d. circular
Answer: (b).unidirection
42. The 8085 microprocessor is based in a ________ pin DIP.
a. 40
b. 45
c. 20
d. 35
Answer: (a).40
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43. The 8085 Microprocessor uses__________ power supply.
a. +5V
b. -5V
c. +12V
d. -12V
Answer: (a).+5V
44. Which is used to store critical pieces of data during subroutines and
interrupts ?
a. Stack
b. Queue
c. Accumulator
d. Data register
Answer: (a).Stack
45. The data in the stack is called
a. Pushing data
b. Pushed
c. Pulling
d. None of these
Answer: (a).Pushing data
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46. The external system bus architecture is created using from ______
architecture.
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
Answer: (d).Von Neumann
47. Secondary memory can store____.
a. Program store code
b. Compiler
c. Operating system
d. All of these
Answer: (d).All of these
48. Secondary memory is also called____.
a. Auxiliary
b. Backup store
c. Both A and B
d. None of these
Answer: (c).Both A and B
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49. The lower red curvy arrow show that CPU places the address extracted
from the memory location on the_____.
a. Address bus
b. System bus
c. Control bus
d. Data bus
Answer: (a).Address bus
50. The CPU sends out a ____ signal to indicate that valid data is available on
the data bus.
a. Read
b. Write
c. Both a and b
d. None of these
Answer: (b).Write
UNIT-2
1. In 8085 microprocessor, how many interrupts are maskable.
a. Two
b. Three
c. Four
d. Five
Answer. c
2. Which stack is used in 8085 microprocessors?
a. FIFO
b. FILO
c. LIFO
d. LILO
Answer. c
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3. In the instruction of the 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
4. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
5. Which one of the following register of 8085 microprocessor is not a part of the
programming model?
a. Instruction register
b. Memory address register
c. Status register
d. Temporary data register
Answer. c
6. The program counter in 8085 microprocessor is a 16-bit register, because
a. It counts 16 bits at a time
b. There are 16 address times
c. It facilitates the users storing 16-bit data temporarily
d. It has to fetch two 8-bit data at a time.
Answer. b
7. A direct memory access (DMA) transfer replies
a. Direct transfer of data between memory and accumulator
b. Direct transfer of data between memory and I/O devices without the use of
microprocessor
c. Transfer of data exclusively within microprocessor registers
d. A fast transfer of data between microprocessor and I/O devices
Answer. b
8. Handshaking mode of data transfer is
a. Synchronous data transfer
b. asynchronous data transfer
c. interrupt driven data transfer
d. level Mode of DMA data transfer
Answer. a
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9. In a Microprocessor, the address of the new next instruction to be executed is
stored in
a. Stack pointer
b. address latch
c. Program counter
d. General purpose register
Answer. c
10. In how many different modes a universal shift register operates?
a. 2
b. 3
c. 4
d. 5
Answer. c
11. The insruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
12. Which one of the following statements is correct regarding the instruction
CMP A ?
a. compare accumulator with register A
b. compare accumulator with memory
c. compare accumulator with register H
d. This instruction does not exist
Answer. a
13. The instruction JNC 16-bit refers to jump to 16-bit address if ?
a. sign flag is set
b. carry flag is reset
c. zero flag is set
d. parity flag is reset
Answer. b
14. Among the given instructions, the one which affects the maximum number of
flags is ?
a. RAL
b. POP PSW
c. XRA A
d. DCR A
Answer. c
15. XCHG instruction of 8085 exchanges the content of ?
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a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
16. Direction flag is used with
a. string instructions
b. stack instructions
c. arithmetic instructions
d. branch instructions
Answer. a
17. The number of output pins of a 8085 microprocessor are
a. 40
b. 27
c. 21
d. 19
Answer. b
18. Following is a 16-bit register for 8085 microprocessor
a. Stack pointer
b. Accumulator
c. Register B
d. Register C
Answer. a
19. The register which holds the information about the nature of results of
arithmetic of logic operations is called as
a. Accumulator
b. Condition code register
c. Flag register
d. Process status registers
Answer. c
20. When referring to instruction words, a mnemonic is
a. a short abbreviation for the operand address.
b. a short abbreviation for the operation to be performed.
c. a short abbreviation for the data word stored at the operand address.
d. Shorthand for machine language.
Answer. b
21. While using a frequency counter for measuring frequency, two modes of
measurement are possible.
1. Period mode
2. Frequency mode
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There is a ‘cross-over frequency’ below which the period mode is preferred.
Assuming the crystal oscillator frequency to be 4 MHz the crossover frequency is
given by
a. 8 MHz
b. 2 MHz
c. 2 kHz
d. 1 kHz
Answer. b
22. In a 8085 microprocessor system with memory-mapped I/O, which of the
following is true?
a. Devices have 8-bit‘address line
b. Devices are accessed using IN and OUT instructions
c. There can be maximum of 256 input devices and 256 output devices
d. Arithmetic and logic operations can be directly performed with the I/O data
Answer. d
23. Consider the following statements:
Arithmetic Logic Unit (ALU)
1 . Performs arithmetic operations.
2. Performs comparisons.
3. Communicates with I/O devices.
4. Keeps watch on the system.
Which of these statements are correct?
a. 1, 2, 3 and 4
b. 1,2 and 3 only
c. 1 and 2 only
d. 3 and 4 only
Answer. c
24. Ready pin 0f microprocessor is used
a. to indicate that the microprocessor is ready to receive inputs
b. to indicate that the microprocessor is ready to receive outputs
c. to introduce wait state
d. to provide direct memory access
Answer. c
25. A bus connected between the CPU and the main memory that permits transfer
of information between main memory and the CPU is known as
a. DMA bus
b. Memory bus
c. Address bus
d. Control bus
Answer. b
26. The operations executed by two or more control units are referred as
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a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer. c
27. Consider the following registers:
1. Accumulator and flag register
2. B and C registers
3. D and E registers
4. H and L registers
Which of these 8-bit registers of 8085 μP can be paired together to make a 16-bit
register?
a. (a) 1, 3 and 4
b. 2, 3 and 4
c. 1, 2 and 3
d. 1, 2 and 4
Answer. b
28. The first microprocessor to include virtual memory in the Intel
microprocessor family is
a. 80286
b. 80386
c. 80486
d. Pentium
Answer. a
29. Program counter in a digital computer
a. counts the numbers of programs run in the machine ,
b. counts the number of times a subroutine is called
c. counts the number of times the loops are executed
d. points the memory address of the current or the next instruction to be
executed
Answer
Answer. d
30. Assuming LSB is at position 0 and MSB at position 7, which bit positions are
not used (undefined) in Flag Register of an 8085 microprocessor?
a. 1, 3, 5
b. 2, 3, 5
c. 1, 2, 5
d. 1, 3, 4
Answer. a
31. At the beginning of a fetch cycle, the contents of the program counter are
a. incremented by one
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b. transferred to address bus
c. transferred to memory address register
d. transferred to memory data register
Answer. c
32. Each instruction in an assembly language program has the following fields
1. Label field
2. Mnemonic field
3. Operand field
4. Comment field
What is the correct sequence of these fields?
a. 1, 2, 3 and 4
b. 2, 1, 4 and 3
c. 1,3, 2 and 4
d. 2, 4, 1 and 3
Answer. a
33. The relation among IC (lnstruction Cycle), FC (Fetch Cycle) and EC (Execute
Cycle) is
a. IC = FC − EC
b. IC = FC+ EC
c. IC= FC + 2EC
d. EC = IC+FC
Answer. b
34. When a peripheral is connected to the microprocessor in input/output mode,
the data transfer takes place between
a. any register and I/O device
b. memory and I/O device
c. accumulator and I/O device
d. HL registerand I/O device.
Answer. c
35. While execution of I/O instruction takes place, the 8-bit address of the port is
placed on
a. lower address bus
b. higher address bus
c. data bus
d. lower as well as higher-order address bus
Answer. d
36. The length of a bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and
an indeterminate number of wait state clock cycles denoted by TW. The wait
states are always inserted between
a. T1 and T2
b. T2 and T3
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c. T3 and T4
d. T4 and T1
Answer. c
37. Which one of the following circuits transmits two messages simultaneously in
one direction?
a. Duplex
b. Diplex
c. Simplex
d. Quadruplex
Answer. b
38. A microprocessor is ALU
a. and control unit on a single chip
b. and memory on a single chip
c. register unit and I/O device on a single chip
d. register unit and control unit on a single chip
Answer. d
39. In Intel 8085 microprocessor, ALE signal is made high to
a. Enable the data bus to be used as low order address bus
b. To latch data D0— D7 from the data bus
c. To disable data bus
d. To achieve all the functions listed above
Answer. a
40. Output of the assembler in machine codes is referred to as
a. Object program
b. Source program
c. Macro instruction
d. Symbolic addressing
Answer. a
41. Which one of the following statements for Intel 8085 is correct?
a. Program counter (PC) specifies the address of the instruction last executed
b. PC specifies the address of the instruction being executed
c. PC specifies the address of the instruction be executed
d. PC specifies the number of instruction executed so far
Answer. c
42. The instruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
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43. Which one of the following statements is correct regarding the instruction
CMP A?
a. Compare accumulator with register A
b. Compare accumulator with memory
c. Compare accumulator with register H
d. This instruction does not exist
Answer. a
44. The instruction JNC 16-bit refers to jump to 16-bit address if
a. Sign flag is set
b. Carry flag is reset
c. Zero flag is set
d. Parity flag is reset
Answer. b
45. Consider the following interrupts for 8085 microprocessor:
1. INTR
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. TRAP
If the interrupt is to be vectored to any memory location then which of the above
interrupt is/are correct?
a. 1 and 2 only
b. 1, 2, 3 and 4
c. 5 only
d. 1 only
Answer. d
46. Consider the following statements:
1. Auxiliary carry flag is used only by the DAA and DAS instruction.
2. Zero flag is set to 1 if the two operands compared are equal.
3. All conditional jumps are long type jumps.
Which of the above statements are correct?
a. 1, 2 and 3 only
b. 1 and 2 only
c. 1 and 3 only
d. 2 and 3 only
Answer. b
47. Among the given instructions, the one which affects maximum number of
flags is
a. RAL
b. POP PSW
c. XRA A
d. DCR A
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Answer. c
48. XCHG instruction of 8085 exchanges the content of
a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
49. Direction flag is used with
a. String instructions
b. Stack instructions
c. Arithmetic instructions
d. Branch instructions
Answer. a
50. What will be the contents of DE and HL register pairs respectively after the
execution of the following instructions?
LXIH, 2500 H
LXID, 0200 H
DAD D
XCHG
a. 0200 H, 2500 H
b. 0200 H, 2700 H
c. 2500 H, 0200 H
d. 2700 H, 0200 H
Answer. d
UNIT-3
51. In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
52. A ‘DAD H” instruction is the same as shifting each bit by one position to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
53. When a program is being executed in an 8085 microprocessor, its program
counter contains
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a.
the memory address as the instruction that is to be executed next.
b.
the memory address of the instruction that is being currently matched.
c.
the total number of instructions in the program being executed.
d.
the number of instructions in the current program that have already been
executed.
Answer. a
54. Which of the following data transfer is not possible in microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
55. LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
d. loads English like command and generates the binary code
Answer. b
56. Which of the following instructions is closest match to the instruction POP
PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
57. How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
58. Which of the following 8085 instruction will require maximum T-states for
execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
59. In 8085 microprocessor, which mode of addressing does the instruction CMP
M use?
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a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
60. With reference to 8085 microprocessor, which of the following statements
are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
61. Assume that the accumulator and the register C of 8085 microprocessor
contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution of
instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
62. It is desired to multiply the numbers 0A H by OB H and store the result in the
accumulator. The numbers are available in registers B and C respectively. A part
of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C
b. ADD B; JNZ LOOP; DCR C
c. DCR C; JNZ LOOP; ADD B
d. ADD B; DCR C; JNZ LOOP
Answer. d
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63. Find the content of the accumulator after the execution of the following
program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
64. The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
65. The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
66. The content of accumulator are 70 H. Initially all flags are zero. What will be
values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
67. A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
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How many times DCR instruction will be executed?
a. 255
b. 510
c. 65025
d. 65279
Answer. d
68. What is content of accumulator of 8085 microprocessor after the execution of
XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
69. The 8085 programming manual says that it takes seven T states to fetch and
execute the MOV instruction. If the system clock has a frequency of 2.5 MHz, how
long is an instruction Cycle?
a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
70. The instruction PCHL, in 8085 is used for
a. Load PC with contents of HL.
b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
71. The following instruction copies a byte of data from the accumulator into the
memory address given in the instruction
a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
72. The instruction that exchanges top of stack with HL pair is
a. XTHL
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b. SPHL
c. PUSH H
d. POP H
Answer. a
73. In 8085 microprocessor, during PUSH PSW Operation, Stack pointer is
a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
74. While a program is being executed in an Intel 8085 microprocessor, the
program counter of the microprocessor contains:
a. The memory address of the instruction that is being currently executed.
b. The memory address of the instruction that is to be executed next.
c. The number of instructions that have already been executed.
d. The total number of instructions in the current program still to be
executed.
Answer. b
75. The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
76. If the status of the control lines SI and SO is LOW, then 8085 microprocessor
is performing
a. Reset operation
b. HOLD operation
c. Halt operation
d. Interrupt acknowledge
Answer. c
77. LXI SP, 7FFF H
MVI A, 25 H
XRI 02 H
PUSH PSW
POP H
MOV A,L
ORI 10 H
HLT
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What are the contents of A, H, L, SP and PSW registers after executing the above
set of instructions? Assume undefined flags always remain clear.
a. 10H, 25H, 00H, 7FFFH, 00H respectively
b. 14H, 27H, 04H, 7FFFH, 04H respectively
c. 14H, 25H, 00H. 7FFFH, 04H respectively
d. 10H, 27H, 04H, 7FFFH, 00H respectively
Answer. b
78. The content of the programme counter of an 8085 microprocessor is
a. the total number of instructions in the program already executed.
b. the total number of times a subroutine is called.
c. the memory address of the instruction that is being currently executed.
d. the memory address of the instruction that is to be executed next.
Answer. d
79. The opcode for the instruction “Add Immediately to Accumulator with carry”
in 8085 microprocessor is
a. ADI
b. ACI
c. ADC
d. ADD
Answer. b
80. MVI A, AA H
ORI FFH
RRC
RRC
CMC
INR A
What are the contents of A and PSW registers after executing the above set of
instructions in sequence?
a. AAH and 00H
b. FFH and 66H
c. 00H and 54H
d. 00H and 00H
Answer. c
81. For which one of the following, the instruction XRA A in 8085 microprocessor
can be used?
a. Set the carry flag
b. Set the zero flag
c. Reset the carry flag and clear the accumulator
d. Transfer FFH to the accumulator
Answer. b
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82. An 8085 microprocessor is executing the programme as follows:
MVI A, 20H
MVI B, 10H
BACK: NOP
ADD B
RLC
JNC BACK
HLT
How many times the instruction NOP will be executed?
a. 4
b. 3
c. 2
d. 1
Answer. b
83. The stack pointer of an 8085 microprocessor is ABCD H. At the end of
execution of the sequence of instructions, what will be the content of the stack
pointer?
PUSH PSW
XTHL
PUSH D
JMP FC70 H
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
84. What is the correct 8085 assembly language instruction that stores the
contents of H and L registers into the memory locations 1080 H and 1081 H
respectively?
a. SPHL 1080 H
b. SHLD 1080 H
c. STAX 1080 H
d. SPHL 1081 H
Answer. b
85. When the operand requires for instruction is stored inside the processor, then
What this addressing mode is called?
a. Direct
b. Register
c. Implicit
d. Immediate
Answer. b
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86. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
87. In an instruction of 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
88. Which one is the indirect addressing mode in the following instructions?
a. LXI H 2050 H
b. MOV A, B
c. LDAX B
d. LDA 2050 H
Answer. c
89. The addressing mode used in the instruction JMP F347 H in case of an Intel
8085A microprocessor is which one of the following?
a. Direct
b. Register—indirect
c. Implicit
d. Immediate
Answer. d
90. Carry flag is not affected after the execution of
a. ADD B
b. SBB B
c. INR B
d. ORA B
Answer. c
91. The contents of the Program Counter (PC), when the microprocessor is
reading from 2FFF H memory location, will be
a. 2FFE H
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b. 2FFF H
c. 3000 H
d. 3001 H
Answer. c
92. If the HLT instruction of an Intel 8085A microprocessor is executed
a. the microprocessor is disconnected from the system bus till the RESET is
pressed.
b. the microprocessor halts the execution of the program and returns to the
monitor.
c. the microprocessor enters into a HALT state and the buses are tri-stated.
d. the microprocessor reloads the program counter from the locations 0024 H
and 0025 H.
Answer. c
93. The stack pointer of an 8085 A microprocessor contains ABCD H.
PUSH PSW
XTHL
PUSH D
JMP EC75 H
At the end of the execution of the above instructions, what would be the content
of the stack pointer?
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
94. In an Intel 8085 A, what is the content of the Instruction Register (IR)?
a. Op-code for the instruction being executed
b. Operand for the instruction being executed
c. Op-code for the instruction to be executed next
d. Operand for the instruction to be executed next
Answer. a
95. The content of the Program Counter of an intel 8085A microprocessor
specifies which one of the following?
a. The address of the instruction being executed
b. The address of the instruction executed earlier
c. The address of the next instruction to be executed
d. The number of instructions executed so far
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Answer. c
96. Which one of the following statement does not describe
property/characteristic of a stack pointer register in 8085 microprocessor?
a. It points to the top of the stack.
b. It is UP/DOWN counter
c. It is automatically initialized to 0000 H on power-on
d. It is a 16-bit register
Answer. c
97. Which one of the following instructions is a 3-byte instruction?
a. MVI A
b. LDAX B
c. JMP 2050 H
d. MOV A,M
Answer. c
98. In 8085, the DAA instruction is used for
a. Direct Address Accumulator
b. Double Add Accumulator
c. Decimal Adjust Accumulator
d. Direct Access Accumulator
Answer. c
99. When an 8086 executes an INT type instruction, it?
a. Resets both IF and TF flags
b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
100. When an 8086 executes an INT type instruction, it?
a. Resets both IF and TF flags
b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
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UNIT-4
ASSEMBLY LANGUAGE PROGRAMMING Multiple Choice Questions :-
1) Assembly language programs are written using
A) Hex code
B) Mnenonics
C) ASCII code
D) None of these View
ANS: B
2) For execution of an interrupt applied at INTR, number of states required by
8085 Microprocessor are
A) 4
B) 6
C) 12
D) 18
ANS: C
3) In 8085 which is/are the 16 bit registers?
A) Program Counter
B) Stack Pointer
C) Both A) & B)
D) None of the above
ANS: C
4) How many memory locations are required to store the instruction LXIH,
0800H in an 8085 assembly language program?
A) 1
B) 2
C) 3
D) 4
ANS: B
5) The instruction DEC N inform the assembler to....
A) Decrement the content of N
B) Decrement the data addressed by N
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C) Convert signed decimal number to binary
D) None of the above
ANS: A
6) In 8085 microprocessor, the value of the most significant bit of the result
following the execution of any arithmetic or Boolean instruction is stored in
the
A) carry status flag
B) auxiliary carry status flag
C) sign status flag
D) zero status flag
ANS: C
7) Instructions performing actions in assembly language are called
A) imperative statements
B) declarative statements
C) directive statements
D) none of the above
ANS: A
8) What is the content of Stack Pointer ?
A) Address of the current instruction
B) Address of the next instruction
C) Address of the top element of the stack
D) None of the above
ANS: C
9) Which of the following interrupt has highest Priority?
A) INTR
B) TRAP
C) RST 7.5
D) RST 6.5
ANS: B
10) Number of machine cycles required for RET instruction in 8085
microprocessor is
A) 1
B) 2
C) 3
D) 5
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ANS: C
11) __________ converts the programs written in assembly language into
machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
Answer: c
Clarification: An assembler is a software used to convert the programs into
machine instructions.
12) The instructions like MOV or ADD are called as ______
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned
Answer: a
Clarification: This OP – codes tell the system what operation to perform on the
operands.
13) The alternate way of writing the instruction, ADD #5,R1 is ______
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way
Answer: b
Clarification: The ADDI instruction, means the addition is in immediate
addressing mode.
14) Instructions which won’t appear in the object program are called as
_____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
Answer: d
Clarification: The directives help the program in getting compiled and hence
won’t be there in the object code.
15) The assembler directive EQU, when used in the instruction: Sum EQU
200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
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c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
Answer: b
Clarification: This basically is used to replace the variable with a constant value.
16) The purpose of the ORIGIN directive is __________
a) To indicate the starting position in memory, where the program block is
to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used
Answer: a
Clarification: This does the function similar to the main statement.
17) The directive used to perform initialization before the execution of
the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU
Answer: c
Clarification: None.
18) _____ directive is used to specify and assign the memory required for
the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve
Answer: d
Clarification: This instruction is used to allocate a block of memory and to store
the object code of the program there.
19) _____ directive specifies the end of execution of a program.
a) End
b) Return
c) Stop
d) Terminate
Answer: b
Clarification: This instruction directive is used to terminate the program
execution.
20) The last statement of the source program should be _______
a) Stop
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b) Return
c) OP
d) End
Answer: d
Clarification: This enables the processor to load some other process.
21) When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive
Answer: c
Clarification: When the assembler comes across the branch code, it immediately
finds the branch offset and replaces it with it.
22) The assembler stores all the names and their corresponding values in
______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned
Answer: b
Clarification: The table where the assembler stores the variable names along with
their corresponding memory locations and values.
23) The assembler stores the object code in ______
a) Main memory
b) Cache
c) RAM
d) Magnetic disk
Answer: d
Clarification: After compiling the object code, the assembler stores it in the
magnetic disk and waits for further execution.
24) The utility program used to bring the object code into memory for
execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker
Answer: a
Clarification: The program is used to load the program into memory.
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25) To overcome the problems of the assembler in dealing with
branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
Answer: d
Clarification: This creates entries into the symbol table first and then creates the
object code.
26) In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
27) A ‘DAD H” instruction is the same as shifting each bit by one position
to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
28) When a program is being executed in an 8085 microprocessor, its
program counter contains
a. the memory address as the instruction that is to be executed next.
b. the memory address of the instruction that is being currently matched.
c. the total number of instructions in the program being executed.
d. the number of instructions in the current program that have already been
executed.
Answer. a
29) Which of the following data transfer is not possible in
microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
30) LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
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d. loads English like command and generates the binary code
Answer. b
31) Which of the following instructions is closest match to the
instruction POP PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
32) How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
33) Which of the following 8085 instruction will require maximum T-
states for execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
34) In 8085 microprocessor, which mode of addressing does the
instruction CMP M use?
a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
35) With reference to 8085 microprocessor, which of the following
statements are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
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36) Assume that the accumulator and the register C of 8085
microprocessor contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution
of instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
37) It is desired to multiply the numbers 0A H by OB H and store the
result in the accumulator. The numbers are available in registers B and C
respectively. A part of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C
b. ADD B; JNZ LOOP; DCR C
c. DCR C; JNZ LOOP; ADD B
d. ADD B; DCR C; JNZ LOOP
Answer. d
38) Find the content of the accumulator after the execution of the
following program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
39) The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
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a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
40) The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
41) The content of accumulator are 70 H. Initially all flags are zero. What
will be values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
42) A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR instruction will be executed?
a. 255
b. 510
c. 65025
d. 65279
Answer. d
43) What is content of accumulator of 8085 microprocessor after the
execution of XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
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44) The 8085 programming manual says that it takes seven T states to
fetch and execute the MOV instruction. If the system clock has a frequency
of 2.5 MHz, how long is an instruction Cycle?
a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
45) The instruction PCHL, in 8085 is used for
a. Load PC with contents of HL.
b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
46) The following instruction copies a byte of data from the accumulator
into the memory address given in the instruction
a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
47) The instruction that exchanges top of stack with HL pair is
a. XTHL
b. SPHL
c. PUSH H
d. POP H
Answer. a
48) In 8085 microprocessor, during PUSH PSW Operation, Stack pointer
is
a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
49) While a program is being executed in an Intel 8085 microprocessor,
the program counter of the microprocessor contains:
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a.The memory address of the instruction that is being currently executed.
b.The memory address of the instruction that is to be executed next.
c.The number of instructions that have already been executed.
d.The total number of instructions in the current program still to be
executed.
Answer. b
50) The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
UNIT-5
Microprocessors Questions and Answers – Programmable DMA Interface
8237 (Part-1)
1. The block of 8237 that decodes the various commands given to the 8237 by the
CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: b
Explanation: The program control block decodes various commands given to the
8237 by the CPU before servicing a DMA request.
2. The priority between the DMA channels requesting the services can be
resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: c
Explanation: The priority encoder block resolves the priority between the DMA
channels requesting the services.
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3. The register that holds the current memory address is
a) current word register
b) current address register
c) base address register
d) command register
Answer: b
Explanation: The current address register holds the current memory address. The
current address register is accessed during the DMA transfer.
4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register
Answer: a
Explanation: The current word register is a 16-bit register that holds the data
transfers. The word count is decremented after each transfer, and the new value
is stored again in the register.
5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated
Answer: c
Explanation: When the count becomes zero, the EOP signal is generated. This can
be written in successive bytes by the CPU, in program mode.
6. The current address register is programmed by the CPU as
a) bit-wise
b) byte-wise
c) bit-wise and byte-wise
d) none of the mentioned
View Answer
Explanation: The current address register is byte-wise programmed by the CPU,
i.e. lower byte first and the higher byte later.
7. Which of these register’s contents is used for auto-initialization (internally)?
a) current word register
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b) current address register
c) base address register
d) command register
Answer: c
Explanation: The contents of base address register cannot be read by the CPU.
These contents are used internally for auto-initialization.
8. The register that maintains an original copy of the respective initial current
address register and current word register is
a) mode register
b) base address register
c) command register
d) mask register
Answer: b
Explanation: The base address register maintains an original copy of the current
address register and current word register, before incrementing or
decrementing.
9. The register that can be automatically incremented or decremented, after each
DMA transfer is
a) mask register
b) mode register
c) command register
d) current address register
Answer: d
Explanation: The address is automatically incremented or decremented after
each DMA transfer, and the resulting address value is again stored in the current
address register.
10. Which of the following is a type of DMA transfer?
a) memory read
b) memory write
c) verify transfer
d) all of the mentioned
Answer: d
Explanation: Memory read, memory write and verify transfer are the three types
of DMA transfer.
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Microprocessors Questions and Answers – 8255 programmable peripheral
interface-(Part-2)
Question 1: How many pins does the 8255 PPI IC contains?
a. 24
b. 20
c. 32
d. 40
Answer: d. 40
Question 2: In which mode do all the Ports of the 8255 PPI work as Input-Output
units for data transfer?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: b. Mode 0 of I/O mode
Question 3: Which of the following pins are responsible for handling the on the
Read Write control logic unit of the 8255 PPI?
a. CS'
b. RD'
c. WR'
d. ALL of the above
Answer: d. All of the above
Question 4: In which of the following modes is the 8255 PPI capable of
transferring data while handshaking with the interfaced device?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: c. Mode 1 of I/O mode
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Question 5: How many bits of data can be transferred between the 8255 PPI and
the interfaced device at a time? or What is the size of internal bus of the 8255
PPI?
a. 16 bits
b. 12 bits
c. 8 bits
d. None of the above
Answer: c. 8 bits
Question 6: Which port of the 8255 PPI is capable of performing the handshaking
function with the interfaced devices?
a. Port A
b. Port B
c. Port C
d. All of the above
Answer: c. Port C
Question 7: In which of the following modes of the 8255 PPI, only port C is taken
into consideration?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: a. BSR mode
Question 8: In mode 2 of I/O mode, which of the following ports are capable of
transferring the data in both the directions?
a. Port A
b. Port B
c. Port C
d. All of the above
Answer: a. Port A
Question 9: In which of the following modes we do not consider the D6, D5 and
D4 bits of the control word?
a. BSR mode
b. Mode 0 of I/O mode
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c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: a. BSR mode
Question 10: How many data lines in total are there in the 8255 PPI IC?
a. 8 data lines
b. 32 data lines
c. 24 data lines
d. None of the above
Answer: c. 24 data lines
Microprocessors Questions and Answers – 8253/8254programmable
timer/counter-(Part-3)
1. The number of counters that are present in the programmable timer device
8254 is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: There are three counters that can be used as either counters or
delay generators.
2. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
Answer: b
Explanation: The control word register can only be written and cannot be read.
3. The mode that is used to interrupt the processor by setting a suitable terminal
count is
a) mode 0
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b) mode 1
c) mode 2
d) mode 3
Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.
4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output
becomes low for
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If
the count N is reloaded and again the output becomes high and remains so for (N-
1) clock pulses.
5. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Answer: c
Explanation: When the count N loaded is even, then for half of the count, the
output remains high and for the remaining half it remains low. If the count loaded
is odd, the first clock pulse decrements it by 1 resulting in an even count value.
6. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
Answer: b
Explanation: SC denotes select counter.
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Rooma, Kanpur – 208 008
7. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.
8. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is
BCD count.
9. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.
10. The control word register contents are used for
a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.
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Microprocessors Questions and Answers – 8259 programmable interrupt
controller-(Part-4)
1. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7
View Answer
Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these
five, four pins were alloted fixed vector addresses but the pin INTR was not
alloted by vector address, rather an external device was supposed to hand over
the type of the interrupt to the microprocessor.
2. The register that stores all the interrupt requests in it in order to serve them
one by one on a priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request
Register internally.
3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request
Register) at the direction of the Priority Resolver.
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Rooma, Kanpur – 208 008
4. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
Answer: d
Explanation: The interrupt control logic performs all the operations that are
involved within the interrupts like accepting and managing interrupt
acknowledge signals, interrupts.
5. In a cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64
vectored interrupts can be provided.
6. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode,
then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a
buffer enable to control buffer transreceivers. If it is not used in buffered mode,
then the pin is used as input to designate whether the chip is used as a master or
a slave.
7. Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
Answer: d
Explanation: The initialization procedure involves
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i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.
8. When non-specific EOI command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will
automatically reset the highest ISR.
9. In the application where all the interrupting devices are of equal priority, the
mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
Answer: a
Explanation: The automatic rotation is used in the applications where all the
interrupting devices are of equal priority.
Microprocessors Questions and Answers – 8251 USART and
RS232C- (Part-5)
1. Which of the following is not a mode of data transmission?
a) simplex
b) duplex
c) semi duplex
d) half duplex
Answer: c
Explanation: Basically, there are three modes of data transmission. simplex,
duplex and half duplex.
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2. If the data is transmitted only in one direction over a single communication
channel, then it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: a
Explanation: In simplex mode, the data transmission is unidirectional. For
example, a CPU may transmit data for a CRT display unit in this mode.
3. If the data transmission takes place in either direction, but at a time data may
be transmitted only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: d
Explanation: In half duplex mode, data transmission is bidirectional but not at a
time. For example, Walkie-Talkie.
4. In 8251A, the pin that controls the rate at which the character is to be
transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)
Answer: a
Explanation: Transmitter Clock Input (TXC(active low)) is a pin that controls the
rate at which the character is to be transmitted.
5. TXD(Transmitted Data Output) pin carries serial stream of the transmitted
data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned
Answer: d
Explanation: Transmitted Data Output pin carries a serial stream of the
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transmitted data bits along with other information like start bits, stop bits and
parity bits etc.
6. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY(Transmitter ready)
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)
Answer: b
Explanation: RXRDY(Receiver ready output) may be used either to interrupt the
CPU or polled by the CPU.
7. The disadvantage of RS-232C is
a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned
Answer: d
Explanation: RS232C has been used for long and has a few disadvantages like
limited speed of communication, high-voltage level signaling and big-size
communication adapters.
8. The USB supports the signaling rate of
a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned
Answer: d
Explanation: The USB standards support the signaling rates. Also, USB signaling is
implemented in a differential in low- and full-speed options.
9. The bit packet that commands the device either to receive data or transmit
data in transmission of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
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Answer: b
Explanation: The token packet is the second type of packet which commands the
device either to receive data or transmit data.
10. High speed USB devices neglect
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
Answer: c
Explanation: PRE packets are only of importance to low-speed USB devices.
→Telegram Channel
→Telegram Group
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IMPORTANT MCQ- MICROPROCESSORS
1. The minimum number of transistors required to implement a two input AND gate is
A. 2
B. 4
C. 6
D. 8
Answer: C
2. Using DeMorgan’s Theorem we can convert any AND-OR structure into
A. NAND-NAND
B. OR-NAND
C. NAND-NOR
D. NOR-NAND
Answer: A
3. For a memory with a 16-bit address space, the addressability is
A. 16 bits
B. 8 bits
C. 2^16 bits
D. Cannot be determined
Answer: D
4. Because we wish to allow each ASCII code to occupy one location in memory, most memories are
_____ addressable.
A. BYTE
B. NIBBLE
C. WORD (16 bits)
D. DOUBLEWORD (32 bits)
Answer: A
5. Circuit A is a 1-bit adder; circuit B is a 1 bit multiplier.
A. Circuit A has more gates than circuit B
B. Circuit B has more gates than circuit A
C. Circuit A has the same number of gates as circuit B
(Hint: Construct the truth table for the adder and the multiplier)
Answer: A
6. When the write enable input is not asserted, the gated D latch ______ its output.
A. can not change
B. clears
C. sets
D. complements
Answer: A
7. A structure that stores a number of bits taken “together as a unit” is a
A. gate
B. mux
C. decoder
D. register
Answer: D
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8. We say that a set of gates is logically complete if we can build any circuit without using any other
kind of gates. Which of the following sets are logically complete
A. set of {AND,OR}
B. set of {EXOR, NOT}
C. set of {AND,OR,NOT}
D. None of the above
Answer: C
9. Of the following circuits, the one which involves storage is
A. RS Latch
B. mux
C. nand
D. decoder
Answer: A
10. If the number of address bits in a memory is reduced by 2 and the
addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory)
A. doubles
B. remains unchanged
C. halves
D. increases by 2^(address bits)/addressability
Answer : C
12. If m is a power of 2, the number of select lines required for an m-input mux is:
A. m
B. 2^m
C. log2 (m)
D. 2*m
Answer: C
13. For the number A[15:0] = 0110110010001111, A[14:13] is ______ A[3:2].
A. less than
B. greater than
C. the same as
d . cannot be determined
Answer: C
14. Which of the following conditions is not allowed in an RS latch?
A. R is asserted, S is asserted
B. R is asserted, S is negated
C. R is negated, S is asserted
D. R is negated, S is negated
Answer: A
15. Which of the following pair of gates can form a latch?
A. a pair of cross coupled OR
B. a pair of cross copled AND
C. a pair of cross coupled NAND
D. a cross coupled NAND/OR
Answer: C
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16. ‘Burst refresh’ in DRAM is also called
A. Concentrated refresh
B. Distributed refresh
C. Hidden refresh
D. None of the above
Answer: A
17. The number of interrupt lines in 8085 is
A. 2
B. 3
C. 4
D. 5
Answer: D
18. A real number consists of
A. integer part
B. integer part and fraction part
C. integer part, fraction part along with positive or negative sign
D. none of the above
Answer: C
19. Assertion (A): Negative values of incremental operator in DO loop are allowed in Fortran 77 but
not in earlier versions of Fortran.
Reason (R): Fortran 77 has better array facilities than earlier versions of Fortran.
A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is correct R is wrong
D. A is wrong R is correct
Answer: B
20. Which of the following is not treated as hexadecimal constant by assembler in 8085?
A. 45 H
B. 6 AFH
C. 234
D. 64 H
Answer: C
21. IC 7485 cannot be cascadeD.
A. True
B. False
Answer: B
22. An I/O processor controls the flow of information between
A. cache memory and I/O devices
B. main memory and I/O devices
C. two I/O devices
D. cache and main memory
Answer: B
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23. MS Access is a DBMS software.
A. True B. False
Answer: A
24. When .9432 E – 4 is subtracted from .5452 E – 3 in normalized floating point mode
A. none of the numbers is changed
B. .9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed
C. .5452 E – 3 is changed to 5.452 E – 4 but .9432 E – 4 is not changed
D. both Ihe numbers are changed and their exponents are, made equal to -5
Answer: B
25. DS directive in 8085
A. forces the assembler to reserve one byte of memory
B. forces the assembler to reserve a specified number of bytes in the memory
C. forces the assembler to reserve a specified number of consecutive bytes in the memory
D. none of the above
Answer: C
26. Which of the following is a valid integer constant?
A. 127
B. 127.0
C. 127
D. 125 + 3
Answer: A
27. The five flags in 8085 are designated as
A. Z, CY, S, P and AC
B. D, Z, S, P, AC
C. Z, C, S, P, AC
D. Z, CY, S, D, AC
Answer: A
28. In 8085 which addressing mode is also called inherent addressing?
A. Direct
B. Register
C. Implicit
D. Immediate
Answer: C
29. It is possible to copy a file in the same directory.
A. True
B. False
Answer: A
30. In a computer the data transfer between hard disk and CPU is nearly the same as that between
diskette and CPU.
A. True
B. False
Answer: B
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31. The timing difference between a slow memory and fast processor can be resolved if
A. processor is capable of waiting
B. external buffer is used
C. either (a) or (b)
D. neither (a) nor (b)
Answer: C
32. In 8086 the number of bytes which can be addressed directly is about
A. 1000
B. 10000
C. 100000
D. one million
Answer: D
33. In Fortran 77 a variable name can contain special characters.
A. True
B. False
Answer: B
34. Which of the following is not a general purpose peripheral?
A. I/O port
B. Programmable interrupt controller
C. Programmable CRT controller
D. Programmable interval timer
Answer: C
35. Each instruction in assembly language program has the following fields:
Lable field
Mnemonic field
Operand field
Comment field
The correct sequence of these fields is?
A. 1, 2, 3, 4
B. 1, 2, 4, 3
C. 2, 1, 3, 4
D. 2, 1, 4, 3
Answer: A
36. In one’s complement 8 bit representation 11111111 represents
A. +0
B. -0
C. +1
D. -1
Answer: B
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37. The operating modes of 8255 A are called
A. mode 0 and mode 1
B. mode 0, mode 1 and mode 2
C. mode 0 and mode 2
D. mode 0, mode 2 and mode 3
Answer: B
38. Which of the following is type declaration statement in C?
A. int bar
B. s = s + 1
C. king = horse + 1
D. prin = prin * prin
Answer: A
39. Internet is a worldwide network of computers where most of the information is freely available.
A. True
B. False
Answer: A
40. A 37 bit mantissa has an accuracy of
A. 6 decimal places
B. 8 decimal places
C. 10 decimal places
D. 11 decimal places
Answer: D
41. In a C expression using assignment operators, relational operators and arithmetic operators, the
hierarchy of operations (in the absence of parenthesis) is
A. assignment, relational, arithmetic
B. relational, assignment, arithmetic
C. arithmetic, assignment, relational
D. arithmetic, relational, assignment
Answer: D
42. In 8085, the pins for SID and SOD are
A. 4 and 5 respectively
B. 5 and 4 respectively
C. 3 and 4 respectively
D. 4 and 3 respectively
Answer: B
43. Assertion (A): Each memory chip has its own address latch.
Reason (R): ALE signal comes out of microprocessor 8085 and goes to memory chip.
A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is correct R is wrong
D. A is wrong R is correct
Answer: D
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44. An e-mail message can be sent to many recipients.
A. True
B. False
Answer: A
45. In C the keywords are also called
A. special words
B. reserved words
C. class words
D. character words
Answer: B
46. The character set of Fortran 77 includes lower case alphabets a to z.
A. True
B. False
Answer: B
47. Which memory has read operation, byte erase, byte write and chip erase?
A. RAM
B. UVEPROM
C. EEPROM
D. both (b) and (c)
Answer: C
48. The forms of IF statements in FORTRAN 77 are called
A. logical IF and Block IF
B. logical IF, block IF and arithmetic IF
C. logic IF, block IF, arithmetic IF and negate IF
D. logical IF and arithmetic IF
Answer: B
49. In 8085
A. P flag is set when the result has even parity
B. P flag is set when the result has odd parity
C. P flag is reset when the result has odd parity
D. P flag is reset when the result has even parity
Answer: A
50. If the sign bit of mantissa is 0 and the exponent is increased from a positive to a more negative
number the result is
A. a larger floating point number
B. a smaller floating point number
C. either (a) or (b) depending on the actual number
D. a negative floating point number
Answer: A
Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors
1. Which interrupt has the highest priority?
a) INTR b) TRAP c) RST6.5
2. In 8085 name the 16 bit registers?
a) Stack pointer b) Program counter c) a & b
3. Which of the following is hardware interrupts?
a) RST5.5, RST6.5, RST7.5 b) INTR, TRAP c) a & b
4. What is the RST for the TRAP?
a) RST5.5 b) RST4.5 c) RST4
5. What are level Triggering interrupts?
a) INTR&TRAP b)RST6.5&RST5.5 c)RST7.5&RST6.5
6. Which interrupt is not level sensitive in 8085?
a) RST6.5 is a raising edge-trigging interrupt.
b) RST7.5 is a raising edge-trigging interrupt.
c) a & b.
7. What are software interrupts?
a) RST 0 - 7 b) RST 5.5 - 7.5 c) INTR, TRAP
8. Which stack is used in 8085?
a) FIFO b) LIFO c) FILO
9. Why 8085 processor is called an 8 bit processor?
a) Because 8085 processor has 8 bit ALU.
b) Because 8085 processor has 8 bit data bus.
c) a & b.
10. What is SIM?
a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask.
11. RIM is used to check whether, ______
a) The write operation is done or not
b) The interrupt is Masked or not
c) a & b
12. What is meant by Maskable interrupts?
a) An interrupt which can never be turned off.
b) An interrupt that can be turned off by the programmer.
c) none
13. In 8086, Example for Non maskable interrupts are
a) Trap b) RST6.5 c) INTR
14. What does microprocessor speed depends on?
a) Clock b) Data bus width c) Address bus width
15. Can ROM be used as stack?
a) Yes b) No c) sometimes yes, sometimes no
16. Which processor structure is pipelined?
a) all x80 processors b) all x85 processors c) all x86 processors
17. Address line for RST3 is?
a) 0020H b) 0028H c) 0018H
18. In 8086 the overflow flag is set when
a) The sum is more than 16 bits
b) Signed numbers go out of their range after an arithmetic operation
c) Carry and sign flags are set
M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/1
Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors
d) During subtraction
19. The advantage of memory mapped I/O over I/O mapped I/O is,
a) Faster
b) Many instructions supporting memory mapped I/O
c) Require a bigger address decoder
d) All the above
20. BHE of 8086 microprocessor signal is used to interface the
a) Even bank memory
b) Odd bank memory
c) I/O
d) DMA
21. In 8086 microprocessor the following has the highest priority among all type
interrupts.
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW
22. In 8086 microprocessor one of the following statements is not true.
a) Coprocessor is interfaced in MAX mode
b) Coprocessor is interfaced in MIN mode
c) I/O can be interfaced in MAX / MIN mode
d) Supports pipelining
23. 8088 microprocessor differs with 8086 microprocessor in
a) Data width on the output
b) Address capability
c) Support of coprocessor
d) Support of MAX / MIN mode
24. Address line for TRAP is?
a) 0023H b) 0024H c) 0033H
M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/2
Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors
Key:
1.1 C 1.2 C 1.3 C 1.4 B 1.5 B 1.6 B
1.7 A 1.8 B 1.9 A 1.10 C 1.11 B 1.12 B
1.13 A 1.14 C 1.15 B 1.16 C 1.17 C 1.18 B
1.19 D 1.20 B 1.21 A 1.22 B 1.23 A 1.24 B
M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/3
Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors
1. Which interrupt has the highest priority?
a) INTR b) TRAP c) RST6.5
2. In 8085 name the 16 bit registers?
a) Stack pointer b) Program counter c) a & b
3. Which of the following is hardware interrupts?
a) RST5.5, RST6.5, RST7.5 b) INTR, TRAP c) a & b
4. What is the RST for the TRAP?
a) RST5.5 b) RST4.5 c) RST4
5. What are level Triggering interrupts?
a) INTR&TRAP b)RST6.5&RST5.5 c)RST7.5&RST6.5
6. Which interrupt is not level sensitive in 8085?
a) RST6.5 is a raising edge-trigging interrupt.
b) RST7.5 is a raising edge-trigging interrupt.
c) a & b.
7. What are software interrupts?
a) RST 0 - 7 b) RST 5.5 - 7.5 c) INTR, TRAP
8. Which stack is used in 8085?
a) FIFO b) LIFO c) FILO
9. Why 8085 processor is called an 8 bit processor?
a) Because 8085 processor has 8 bit ALU.
b) Because 8085 processor has 8 bit data bus.
c) a & b.
10. What is SIM?
a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask.
11. RIM is used to check whether, ______
a) The write operation is done or not
b) The interrupt is Masked or not
c) a & b
12. What is meant by Maskable interrupts?
a) An interrupt which can never be turned off.
b) An interrupt that can be turned off by the programmer.
c) none
13. In 8086, Example for Non maskable interrupts are
a) Trap b) RST6.5 c) INTR
14. What does microprocessor speed depends on?
a) Clock b) Data bus width c) Address bus width
15. Can ROM be used as stack?
a) Yes b) No c) sometimes yes, sometimes no
16. Which processor structure is pipelined?
a) all x80 processors b) all x85 processors c) all x86 processors
17. Address line for RST3 is?
a) 0020H b) 0028H c) 0018H
18. In 8086 the overflow flag is set when
a) The sum is more than 16 bits
b) Signed numbers go out of their range after an arithmetic operation
c) Carry and sign flags are set
M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/1
Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors
d) During subtraction
19. The advantage of memory mapped I/O over I/O mapped I/O is,
a) Faster
b) Many instructions supporting memory mapped I/O
c) Require a bigger address decoder
d) All the above
20. BHE of 8086 microprocessor signal is used to interface the
a) Even bank memory
b) Odd bank memory
c) I/O
d) DMA
21. In 8086 microprocessor the following has the highest priority among all type
interrupts.
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW
22. In 8086 microprocessor one of the following statements is not true.
a) Coprocessor is interfaced in MAX mode
b) Coprocessor is interfaced in MIN mode
c) I/O can be interfaced in MAX / MIN mode
d) Supports pipelining
23. 8088 microprocessor differs with 8086 microprocessor in
a) Data width on the output
b) Address capability
c) Support of coprocessor
d) Support of MAX / MIN mode
24. Address line for TRAP is?
a) 0023H b) 0024H c) 0033H
M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/2
Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors
Key:
1.1 C 1.2 C 1.3 C 1.4 B 1.5 B 1.6 B
1.7 A 1.8 B 1.9 A 1.10 C 1.11 B 1.12 B
1.13 A 1.14 C 1.15 B 1.16 C 1.17 C 1.18 B
1.19 D 1.20 B 1.21 A 1.22 B 1.23 A 1.24 B
M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/3
MICROPROCESSOR 49 IMPORTANT MCQ
Q.1 If the crystal oscillator is operating at 15 MHz, the PCLK output of 8284 is
(A) 2.5 MHz. (B) 5 MHz.
(C) 7.5 MHz. (D) 10 MHz.
Ans: (A)
Q.2 In which T-state does the CPU sends the address to memory or I/O and the ALE signal
for demultiplexing
(A) T1. (B) T2.
(C) T3. (D) T4.
Ans, During the first clocking period in a bus cycle, which is called T1, the address of
the memory or I/O location is sent out and the control signals ALE, DT/R’ and IO/M’
are also output. Hence answer is (A).
Q.3 If a 1M ×1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no
more than _ of time must pass before another row is refreshed.
(A) 64 ms. (B) 4 ns.
(C) 0.5 ns. (D) 15.625 µs .
Ans Answer is (B)
Q.4 In a DMA write operation the data is transferred
(A) from I/O to memory. (B) from memory to I/O.
(C) from memory to memory. (D) from I/O to I/O.
Ans A DMA writes operation transfers data from an I/O device to memory. Hence
answer is (A).
Q.5 Which type of JMP instruction assembles if the distance is 0020 h bytes
(A) near. (B) far.
(C) short. (D) none of the above.
Ans The three byte near jump allows a branch or jump within ± 32K bytes. Hence
answer is (A).
Q.6 A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following
modes this SRAM is operating
(A) Read (B) Write
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(C) Stand by (D) None of the above
Ans For CS’=WE’=0, write operation. Hence answer is (B).
Q.7 Which of the following is true with respect to EEPROM?
(A) contents can be erased byte wise only.
(B) contents of full memory can be erased together.
(C) contents can be erased using ultra violet rays
(D) contents can not be erased
Ans Answer is (C).
Q.8 Pseudo instructions are basically
(A) false instructions.
(B) instructions that are ignored by the microprocessor.
(C) assembler directives.
(D) instructions that are treated like comments.
Ans Pseudo-instructions are commands to the assembler. All pseudo-operations start
with a period. Pseudo-instructions are composed of a pseudo-operation which may be
followed by one or more expressions. Hence answer is (C).
Q.9 Number of the times the instruction sequence below will loop before coming out of
loop is
MOV AL, 00h
A1: INC AL
JNZ A1
(A) 00 (B) 01
(C) 255 (D) 256
Ans Answer is (D)
Q.10 What will be the contents of register AL after the following has been executed
MOV BL, 8C
MOV AL, 7E
ADD AL, BL
(A) 0A and carry flag is set (B) 0A and carry flag is reset
(C) 6A and carry flag is set (D) 6A and carry flag is reset
Ans, Result is 1,0A. Hence answer is (A).
Q.11 Direction flag is used with
(A) String instructions. (B) Stack instructions.
(C) Arithmetic instructions. (D) Branch instructions.
Ans The direction flag is used only with the string instructions. Hence answer is (A).
Q.12 Ready pin of a microprocessor is used
(A) to indicate that the microprocessor is ready to receive inputs.
(B) to indicate that the microprocessor is ready to receive outputs.
(C) to introduce wait states.
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(D) to provide direct memory access.
Ans This input is controlled to insert wait states into the timing of the microprocessor.
Hence answer is (C).
Q.13 These are two ways in which a microprocessor can come out of Halt state.
(A) When hold line is a logical 1.
(B) When interrupt occurs and the interrupt system has been enabled.
(C) When both (A) and (B) are true.
(D) When either (A) or (B) are true.
Ans Answer is (A)
Q.14 In the instruction FADD, F stands for
(A) Far. (B) Floppy.
(C) Floating. (D) File.
Ans Adds two floating point numbers. Hence answer is (C).
Q.15 SD RAM refers to
(A) Synchronous DRAM (B) Static DRAM
(C) Semi DRAM (D) Second DRAM
Ans, Answer is (A)
Q.16 In case of DVD, the speed is referred in terms of n X (for example 32 X). Here, X
refers to
(A) 150 KB/s (B) 300 KB/s
(C) 1.38 MB/s (D) 2.4 MB/s
Ans Answer is (C).
Q.17 Itanium processor of Intel is a
(A) 32 bit microprocessor. (B) 64 bit microprocessor.
(C) 128 bit microprocessor. (D) 256 bit microprocessor.
Ans The Itanium is a 64-bit architecture microprocessor. Hence answer is (B).
Q.18 LOCK prefix is used most often
(A) during normal execution. (B) during DMA accesses
(C) during interrupt servicing. (D) during memory accesses.
Ans LOCK is a prefix which is used to make an instruction of 8086 non-interruptable.
Hence answer is (C).
Q.19 The Pentium microprocessor has execution units.
(A) 1 (B) 2
(C) 3 (D) 4
Ans The Pentium microprocessor is organized with three execution units. One
executes floating-point instructions, and the other two (U-pipe and V-pipe) execute
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integer instructions. Hence answer is (C).
Q.20 EPROM is generally erased by using
(A) Ultraviolet rays (B) infrared rays
(C) 12 V electrical pulse (D) 24 V electrical pulse
Ans The EPROM is erasable if exposed to high-intensity ultraviolet light for about 20
minutes or less. Hence answer is (A)
Q.21 Signal voltage ranges for a logic high and for a logic low in RS-232C standard are
(A) Low = 0 volt to 1.8 volt, high = 2.0 volt to 5 volt
(B) Low =-15 volt to –3 vol, high = +3 volt to +15 volt
(D) Low = +3 volt to +15 volt, high = -3 volt to -15 volt
(E) Low = 2 volt to 5.0 volt, high = 0 volt to 1.8 volt
Ans Answer is (B)
Q.22 The PCI bus is the important bus found in all the new Pentium systems because
(A) It has plug and play characteristics
(B) It has ability to function with a 64 bit data bus
(C) Any Microprocessor can be interfaced to it with PCI controller or bridge
(D) All of the above
Ans, Answer is (D).
Q.23 Which of the following statement is true?
(A) The group of machine cycle is called a state.
(B) A machine cycle consists of one or more instruction cycle.
(C) An instruction cycle is made up of machine cycles and a machine cycle is
made up of number of states.
(D) None of the above
Ans An instruction cycle consists of several machine cycles. Hence Answer is (B).
Q.24 8251 is a
(A) UART
(B) USART
(C) Programmable Interrupt controller
(D) Programmable interval timer/counter
Ans The Intel 8251 is a programmable communication interface. It is USART.
Q.25 8088 microprocessor has
(A) 16 bit data bus (B) 4 byte pre-fetch queue
(C) 6 byte pre-fetch queue (D) 16 bit address bus
Ans The 8088 is a 16-bit microprocessor with an 8-bit data bus. The 16-bit address
bus. Hence answer is (D).
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Q.26 By what factor does the 8284A clock generator divide the crystal oscillator’s output
frequency?
(A) One (B) Two
(C) Three (D) Four
Ans When F/C’ is at logic 0; The oscillator output is steered through to the divide- by-
3 counter. Hence answer is (c).
Q.27 The memory data bus width in Pentium is
(A) 16 bit (B) 32 bit
(C) 64 bit (D) None of these
Ans The Data bus width is 64 bits. Hence answer is (C).
Q.28 When the 82C55 is reset, its I/O ports are all initializes as
(A) output port using mode 0 (B) Input port using mode 1
(C) output port using mode 1 (D) Input port using mode 0
Ans A RESET input to the 82C55 causes all ports to be set up as simple input ports
using mode 0 operations. Hence answer is (D).
Q.29 Which microprocessor pins are used to request and acknowledge a DMA transfer?
(A) reset and ready (B) ready and wait
(C) HOLD and HLDA (D) None o these
Ans, The HOLD pin is an input that is used request a DMA action and the HLDA
pin is an output that that acknowledges the DMA action. Hence answer is (C).
Q.30 Which of the following statement is false?
(A) RTOS performs tasks in predictable amount of time
(B) Windows 98 is RTOS
(C) Interrupts are used to develop RTOS
(D) Kernel is the one of component of any OS
Ans Operating systems, like Windows, defer many tasks and do not guarantee their
execution in predictable time. Hence answer is (B).
Q.31 The VESA local bus operates at
(A) 8 MHz (B) 33 MHz
(C) 16 MHz (D) None of these
Ans The VESA local bus operates at 33 MHz. Hence answer is (B).
Q.32 The first modern computer was called .
(A) FLOW-MATIC (B) UNIVAC-I
(C) ENIAC (D) INTEL
Ans, ENIAC (Electronic Numerical Integrator And Computer) was the first general-
purpose electronic computer. It was a Turing-complete, digital computer capable of
being reprogrammed to solve a full range of computing problems. ENIAC was
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designed to calculate artillery firing tables for the U.S. Army's Ballistic Research
Laboratory. Hence answer is (c).
Q.33 Software command CLEAR MASK REGISTER in DMA
(A) Disables all channels.
(B) Enables all channels.
(C) None.
(D) Clears first/last flip-flop within 8237.
Ans Enables all four DMA channels. Hence answer is (B).
Q.34 The first task of DOS operating system after loading into the memory is to use the file
called .
(A) HIMEM.SYS (B) CONFIG.SYS
(C) AUTOEXEC.BAT (D) SYSTEM.INI
Ans, The first task of the DOS operating system, after loading into memory, is to
use a file called the CONFIG.SYS file. This file specifies various drivers that load
into the memory, setting up or configuring the machine for operation under DOS.
Q.35 If the programmable counter timer 8254 is set in mode 1 and is to be used to count
six events, the output will remain at logic 0 for number of counts
(A) 5 (B) 6
(C) 0 (D) All of the above
Ans. OUT continues for the total length of the count. Hence answer is (B).
Q.36 The flash memory is programmed in the system by 12 V programming pulse.
(A) TRUE (B) FALSE
Ans The flash memory device requires a 12V programming voltage to erase and write
new data. Hence answer is (A).
Q.37 A plug and play (PnP) interface is one that contains a memory that holds
configuration information of the system.
(A) TRUE (B) FALSE
Ans Answer is (A)
Q.38 The accelerated graphics port (AGP) allows virtually any microprocessor to be
interfaced with PCI bus via the use of bridge interface.
(A) TRUE (B) FALSE
Ans, this port probably will never be used for any devices other than the video card.
Hence answer is (B).
Q.39 A Bus cycle is equal to how many clocking periods
(A) Two (B) Three
(C) Four (D) Six
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Ans Typically, the bus-cycle of the 8086 and 8088 processors consist of four clock
cycles or pulses. Thus, duration of a bus-cycle is = ‘4*T’. Hence Answer is (C).
Q.40 The time required to refresh a typical DRAM is
(A) 2 – 4 us (B) 2 – 4 ns
(C) 2 – 4 ms (D) 2 – 4 ps
Ans The capacitor Cs discharges through the internal resistance of the NMOS transistor
T1. Typically Cs = 0.2 pF and the internal resistance Rin = 1010 ohms, so:
Cs x Rin = 0.2 x 10-12 x 1010 x 103 ms = 2 ms
So the typical refresh time interval is 2 ms. Hence Answer is (C).
Q.41 The no. of address lines required to address a memory of size 32 K is
(A) 15 lines (B) 16 lines
(C) 18 lines (D) 14 lines
5 10 15
Ans 32K = 32 X 1024 bits = 2 X 2 =2 Hence answer is ( A).
Q.42 The no. of wait states required to interface 8279 to 8086 with 8MHz clock are
(A) Two (B) Three
(C) One (D) None
Ans Two wait states used so that device can function with an 8 MHz. Hence answers is
( A).
Q.43 NMI input is
(A) Edge sensitive (B) Level sensitive
(C) Both edge and level triggered (D) edge triggered and level sensitive
Ans Non-maskable interrupt (NMI) is an edge –triggered input that requests an
interrupt on the positive edge (0 to 1 transition).
Q.44 Data rate available for use on USB is
(A) 12 Mbits per second (B) 1.5 Mbits per second
(C) Both (A) and (B) (D) No restriction
Ans Data transfer speeds are 12 Mbps for full speed operation and 1.5 Mbps for slow
speed operation. Hence answer is (c).
Q.45 In 80186, the timer which connects to the system clock is
(A) timer 0 (B) timer 1
(C) timer 2 (D) Any one can be connected
Ans. Timer 2 is internal and clocked by the master clock. Hence answer is (c).
Q.46 Conversion of the +1000 decimal number into signed binary word results
(A) 0000 0011 1110 1000 (B) 1111 1100 0001 1000
(C) 1000 0011 1110 1000 (D) 0111 1100 0001 1000
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Ans
1000 /2 =>500 €0
500/2=>250€0
250/2=>125€0
125/2=>62€1
62/2=>31€0
31/2=>15€1
15/2=>7€1
7/2=>3€1
3/2=>1€1
16 bit signed number is 1000,0011,1110,1000
Hence Answer is (C).
Q.47 What do the symbols [ ] indicate?
(A) Direct addressing (B) Register Addressing
(C) Indirect addressing (D) None of the above
Ans Answer is (C).
Q.48 SDRAM refers to
(A) static DRAM (B) synchronous DRAM
(C) sequential DRAM (D) semi DRAM
Ans, Answer is (B)
Q.49 Which pins are general purpose I/O pins during mode-2 operation of the 82C55?
(A) PA0 – PA7 (B) PB0-PB7
(C) PC3-PC7 (D) PC0-PC2
Ans In mode 2 Port-A can be programmed to operate as bidirectional port. The mode-2
operation is only for Port-A. Hence Answer is (A)
8
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Date-16/06/2021
Subject Name-KCS-403-Microprocessor_CSE-Semester 4
UNIT-1
1. In 8085 microprocessor, the RST6 instruction transfer programme execution
to following location
a. 0030H
b. 0024H
c. 0048H
d. 0060H
Answer: (a).0030H
2. HLT opcode means
a. load data to accumulator
b. store result in memory
c. load accumulator with contents of register
d. end of program
Answer: (d).end of program
3. What is SIM?
a. Select interrupt mask
b. Sorting interrupt mask
c. Set interrupt mask
d. None of these
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Answer: (c).Set interrupt mask
4. The ROM programmed during manufacturing process itself is called
a. MROM
b. PROM
c. EPROM
d. EEPROM
Answer: (a).MROM
5. A field programmable ROM is called
a. MROM
b. PROM
c. FROM
d. FPROM
Answer: (b).PROM
6. The operations executed by two or more control units are referred as
a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer: (b).Macro-operations
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
7. Program counter in a digital computer
a. Counts the numbers of programs run in the machine.
b. Counts the number of times a subroutine is called.
c. Counts the number of times the loops are executed.
d. Points the memory address of the next instruction to be fetched.
Answer: (d).Points the memory address of the next instruction to be fetched.
8. At the beginning of a fetch cycle, the contents of the program
counter are
a. incremented by one.
b. transferred to address bus.
c. transferred to memory address register.
d. transferred to memory data register.
Answer: (c).transferred to memory address register.
9. Which components are NOT found on chip in a microprocessor but may be
found on chip in a micro-controller?
a. SRAM & USART
b. EPROM & PORTS
c. EPROM, USART & PORTS
d. SRAM, EPROM & PORTS
Answer: (c).EPROM, USART & PORTS
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
10. For the purpose of data processing an efficient assembly language
programmer makes use of the general purpose registers rather than
memory. The reason is
a. the set of instructions for data processing with memory is limited
b. data processing becomes easier when register are used
c. more memory related instructions are required
d. data processing with registers takes fewer cycles than that with memory
Answer: (d).data processing with registers takes fewer cycles than that with memory
11. The first machine cycle of an instruction is always
a. A memory read cycle
b. A fetch cycle
c. An I/O read cycle
d. A memory write cycle
Answer: (b).A fetch cycle
12. The output data lines of microprocessor and memories are usually tristated
because
a. More than one device can transmit information over the data bus by enabling
only one device at a time
b. More than one device can transmit over the data bus at the same time
c. The data line can be multiplexed for both input and output
d. It increases the speed of data transfer over the data bus
Answer: (a).More than one device can transmit information over the data bus by
enabling only one device at a time
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
13. The correct sequence of steps in the instruction cycle of a basic computer is
a. Fetch, Execute, Decode and Read effective address.
b. Read effective address,Decode,Fetch and Execute.
c. Fetch, Decode, Read effective address and ,Execute.
d. Fetch, Read effective address, Decode and Execute.
Answer: (c).Fetch, Decode, Read effective address and ,Execute.
14. The register which holds the information about the nature of results of
arithmetic and logic operations is called as
a. Accumulator
b. Condition code register
c. Flag register
d. Process status register
Answer: (c).Flag register
15. Consider the following statements:
Arithmetic Logic Unit (ALU)
1.Performs arithmetic operations
2.Performs comparisons.
3.Communicates with I/O devices
4.Keeps watch on the system
Which of these statements are correct?
a. 1, 2, 3 and 4
b. 1, 2 and 3
c. 1 and 2 only
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
d. 3 and 4 only
Answer: (c).1 and 2 only
16. Ready pin of microprocessor is used
a. to indicate that microprocessor is ready to receive inputs
b. to indicate that microprocessor is ready to receive outputs
c. to introduce wait state
d. to provide direct memory access
Answer: (c).to introduce wait state
17. Both the ALU and control section of CPU employ which special purpose
storage location?
a. Buffers
b. Decoders
c. Accumulators
d. Registers
Answer: (c).Accumulators
18. A high on RESET OUT signifies that
a. all the registers of the CPU are being reset
b. all the registers and counters are being reset
c. all the registers and counters are being reset and this signal can be used to
reset external support chip
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
d. processing can begin when this signal goes high
Answer: (c).all the registers and counters are being reset and this signal can be
used to reset external support chip
19. In a vector interrupt
a. the branch address is assigned to a fixed location in memory
b. the interrupting source supplies the branch information to the processor
through an interrupt vector
c. the branch address is obtained from a register in the processor
d. none of the above
Answer: (a).the branch address is assigned to a fixed location in memory
20. The content of the A15-A8 (higher order address lines) while executing “IN
8-bit port address” instruction are
a. same as the content of A7-A0
b. irrelevant
c. all bits reset (i.e. 00H)
d. all bits set (i.e. FFH)
Answer: (a).same as the content of A7-A0
21. Which one of the following interrupt is only level triggering?
a. TRAP
b. RST 7.5
c. RST 6.5 and RST 5.5
d. RST 6.5
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Answer: (c).RST 6.5 and RST 5.5
22. Which one of the following instruction may be used to clear the
accumulator content irrespective of its initial value?
a. CLR A
b. ORA A
c. SUB A
d. MOV A, 00H
Answer: (c).SUB A
23. ___________ signal prevent the microprocessor from reading the same data
more than one.
a. pipelining
b. handshaking
c. controlling
d. signaling
Answer: (b).handshaking
24. Data transfer between the microprocessor for peripheral takes place
through __________.
a. I/O port
b. input port
c. output port
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
d. multi port
Answer: (a).I/O port
25. 8255A operates with ________ power supply.
a. +5V
b. -5V
c. -10V
d. +10V
Answer: (a).+5V
26. The _______ allow data transfer between memory and peripherals.
a. DMA technique
b. Microprocessor
c. Register
d. Decoder
Answer: (a).DMA technique
27. Expansion of SPGA is _________.
a. Staggered Pin Grid-Array package
b. Staggered Point Grid-Array package
c. Staggered Plus Grid-Array package
d. Staggered per grid-Array package
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Answer: (a).Staggered Pin Grid-Array package
28. Pentium-pro processor design implements________ micro architecture.
a. P2
b. P4
c. P6
d. P8
Answer: (c).P6
29. The number of hardware chips needed for multiple digit display can be
minimized by using the technique called ______.
a. interfacing
b. multiplexing
c. demultiplexing
d. multiprocessing
Answer: (b).multiplexing
30. An RS-232 interface is ____________.
a. a parallel interface
b. a serial interface
c. printer interface
d. a modem interface
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Answer: (b).a serial interface
31. Expansion for DTE is ______.
a. data terminal equipment
b. data trap equipment
c. data text equipment
d. data terminal extension
Answer: (a).data terminal equipment
32. Compared with RS-232, USB is faster and uses___________.
a. medium voltage
b. higher voltage
c. lower voltage
d. None of the above
Answer: (c).lower voltage
33. Expansion for HMOS technology is _______.
a. high level mode oxygen semiconductor
b. high level metal oxygen semiconductor
c. high performance medium oxide semiconductor
d. high performance metal oxide semiconductor
Answer: (d).high performance metal oxide semiconductor
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
34. RIM is used to check whether, the ___________.
a. write operation is done or not
b. interrupt is Masked or not
c. interrupt is Masked
d. interrupt is not Masked
Answer: (b).interrupt is Masked or not
35. What does microprocessor speed depends on?
a. clock
b. data bus width
c. address bus width
d. signal bus
Answer: (c).address bus width
36. The advantage of memory mapped I/O over I/O mapped I/O is _________
a. faster operation
b. many instructions supporting memory mapped I/O
c. require a bigger address decoder
d. all the above
Answer: (d).all the above
37. In 8279 Status Word, data is read when ________ pins are low, and write to
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
the display RAM with ____________ are low.
a. A0, CS, RD & A0, WR, CS
b. CS, WR, A0 & A0, CS, RD
c. A0, RD & WR, CS
d. CS, RD & A0, CS
Answer: (a).A0, CS, RD & A0, WR, CS
38. In 8279, the keyboard entries are de bounced and stored in an _________,
that is further accessed by the CPU to read the key codes.
a. 8-bit FIFO
b. 8-byte FIFO
c. 16 byte FIFO
d. 16 bit FIFO
Answer: (b).8-byte FIFO
39. For the most Static RAM the write pulse width should be at least
a. 10 ns
b. 60 ns
c. 300 ns
d. 350 ns
Answer: (b).60 ns
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
40. Pentium-I, Pentium-II, Pentium-III and Pentium-IV are recently
introduced microprocessor by__________.
a. Motorala
b. Intel
c. Stephen Mors
d. HCL
Answer: (b).Intel
41. The address bus flow in __________.
a. bidirection
b. unidirection
c. mulidirection
d. circular
Answer: (b).unidirection
42. The 8085 microprocessor is based in a ________ pin DIP.
a. 40
b. 45
c. 20
d. 35
Answer: (a).40
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
43. The 8085 Microprocessor uses__________ power supply.
a. +5V
b. -5V
c. +12V
d. -12V
Answer: (a).+5V
44. Which is used to store critical pieces of data during subroutines and
interrupts ?
a. Stack
b. Queue
c. Accumulator
d. Data register
Answer: (a).Stack
45. The data in the stack is called
a. Pushing data
b. Pushed
c. Pulling
d. None of these
Answer: (a).Pushing data
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
46. The external system bus architecture is created using from ______
architecture.
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
Answer: (d).Von Neumann
47. Secondary memory can store____.
a. Program store code
b. Compiler
c. Operating system
d. All of these
Answer: (d).All of these
48. Secondary memory is also called____.
a. Auxiliary
b. Backup store
c. Both A and B
d. None of these
Answer: (c).Both A and B
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
49. The lower red curvy arrow show that CPU places the address extracted
from the memory location on the_____.
a. Address bus
b. System bus
c. Control bus
d. Data bus
Answer: (a).Address bus
50. The CPU sends out a ____ signal to indicate that valid data is available on
the data bus.
a. Read
b. Write
c. Both a and b
d. None of these
Answer: (b).Write
UNIT-2
1. In 8085 microprocessor, how many interrupts are maskable.
a. Two
b. Three
c. Four
d. Five
Answer. c
2. Which stack is used in 8085 microprocessors?
a. FIFO
b. FILO
c. LIFO
d. LILO
Answer. c
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3. In the instruction of the 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
4. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
5. Which one of the following register of 8085 microprocessor is not a part of the
programming model?
a. Instruction register
b. Memory address register
c. Status register
d. Temporary data register
Answer. c
6. The program counter in 8085 microprocessor is a 16-bit register, because
a. It counts 16 bits at a time
b. There are 16 address times
c. It facilitates the users storing 16-bit data temporarily
d. It has to fetch two 8-bit data at a time.
Answer. b
7. A direct memory access (DMA) transfer replies
a. Direct transfer of data between memory and accumulator
b. Direct transfer of data between memory and I/O devices without the use of
microprocessor
c. Transfer of data exclusively within microprocessor registers
d. A fast transfer of data between microprocessor and I/O devices
Answer. b
8. Handshaking mode of data transfer is
a. Synchronous data transfer
b. asynchronous data transfer
c. interrupt driven data transfer
d. level Mode of DMA data transfer
Answer. a
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9. In a Microprocessor, the address of the new next instruction to be executed is
stored in
a. Stack pointer
b. address latch
c. Program counter
d. General purpose register
Answer. c
10. In how many different modes a universal shift register operates?
a. 2
b. 3
c. 4
d. 5
Answer. c
11. The insruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
12. Which one of the following statements is correct regarding the instruction
CMP A ?
a. compare accumulator with register A
b. compare accumulator with memory
c. compare accumulator with register H
d. This instruction does not exist
Answer. a
13. The instruction JNC 16-bit refers to jump to 16-bit address if ?
a. sign flag is set
b. carry flag is reset
c. zero flag is set
d. parity flag is reset
Answer. b
14. Among the given instructions, the one which affects the maximum number of
flags is ?
a. RAL
b. POP PSW
c. XRA A
d. DCR A
Answer. c
15. XCHG instruction of 8085 exchanges the content of ?
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a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
16. Direction flag is used with
a. string instructions
b. stack instructions
c. arithmetic instructions
d. branch instructions
Answer. a
17. The number of output pins of a 8085 microprocessor are
a. 40
b. 27
c. 21
d. 19
Answer. b
18. Following is a 16-bit register for 8085 microprocessor
a. Stack pointer
b. Accumulator
c. Register B
d. Register C
Answer. a
19. The register which holds the information about the nature of results of
arithmetic of logic operations is called as
a. Accumulator
b. Condition code register
c. Flag register
d. Process status registers
Answer. c
20. When referring to instruction words, a mnemonic is
a. a short abbreviation for the operand address.
b. a short abbreviation for the operation to be performed.
c. a short abbreviation for the data word stored at the operand address.
d. Shorthand for machine language.
Answer. b
21. While using a frequency counter for measuring frequency, two modes of
measurement are possible.
1. Period mode
2. Frequency mode
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There is a ‘cross-over frequency’ below which the period mode is preferred.
Assuming the crystal oscillator frequency to be 4 MHz the crossover frequency is
given by
a. 8 MHz
b. 2 MHz
c. 2 kHz
d. 1 kHz
Answer. b
22. In a 8085 microprocessor system with memory-mapped I/O, which of the
following is true?
a. Devices have 8-bit‘address line
b. Devices are accessed using IN and OUT instructions
c. There can be maximum of 256 input devices and 256 output devices
d. Arithmetic and logic operations can be directly performed with the I/O data
Answer. d
23. Consider the following statements:
Arithmetic Logic Unit (ALU)
1 . Performs arithmetic operations.
2. Performs comparisons.
3. Communicates with I/O devices.
4. Keeps watch on the system.
Which of these statements are correct?
a. 1, 2, 3 and 4
b. 1,2 and 3 only
c. 1 and 2 only
d. 3 and 4 only
Answer. c
24. Ready pin 0f microprocessor is used
a. to indicate that the microprocessor is ready to receive inputs
b. to indicate that the microprocessor is ready to receive outputs
c. to introduce wait state
d. to provide direct memory access
Answer. c
25. A bus connected between the CPU and the main memory that permits transfer
of information between main memory and the CPU is known as
a. DMA bus
b. Memory bus
c. Address bus
d. Control bus
Answer. b
26. The operations executed by two or more control units are referred as
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a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer. c
27. Consider the following registers:
1. Accumulator and flag register
2. B and C registers
3. D and E registers
4. H and L registers
Which of these 8-bit registers of 8085 μP can be paired together to make a 16-bit
register?
a. (a) 1, 3 and 4
b. 2, 3 and 4
c. 1, 2 and 3
d. 1, 2 and 4
Answer. b
28. The first microprocessor to include virtual memory in the Intel
microprocessor family is
a. 80286
b. 80386
c. 80486
d. Pentium
Answer. a
29. Program counter in a digital computer
a. counts the numbers of programs run in the machine ,
b. counts the number of times a subroutine is called
c. counts the number of times the loops are executed
d. points the memory address of the current or the next instruction to be
executed
Answer
Answer. d
30. Assuming LSB is at position 0 and MSB at position 7, which bit positions are
not used (undefined) in Flag Register of an 8085 microprocessor?
a. 1, 3, 5
b. 2, 3, 5
c. 1, 2, 5
d. 1, 3, 4
Answer. a
31. At the beginning of a fetch cycle, the contents of the program counter are
a. incremented by one
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b. transferred to address bus
c. transferred to memory address register
d. transferred to memory data register
Answer. c
32. Each instruction in an assembly language program has the following fields
1. Label field
2. Mnemonic field
3. Operand field
4. Comment field
What is the correct sequence of these fields?
a. 1, 2, 3 and 4
b. 2, 1, 4 and 3
c. 1,3, 2 and 4
d. 2, 4, 1 and 3
Answer. a
33. The relation among IC (lnstruction Cycle), FC (Fetch Cycle) and EC (Execute
Cycle) is
a. IC = FC − EC
b. IC = FC+ EC
c. IC= FC + 2EC
d. EC = IC+FC
Answer. b
34. When a peripheral is connected to the microprocessor in input/output mode,
the data transfer takes place between
a. any register and I/O device
b. memory and I/O device
c. accumulator and I/O device
d. HL registerand I/O device.
Answer. c
35. While execution of I/O instruction takes place, the 8-bit address of the port is
placed on
a. lower address bus
b. higher address bus
c. data bus
d. lower as well as higher-order address bus
Answer. d
36. The length of a bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and
an indeterminate number of wait state clock cycles denoted by TW. The wait
states are always inserted between
a. T1 and T2
b. T2 and T3
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c. T3 and T4
d. T4 and T1
Answer. c
37. Which one of the following circuits transmits two messages simultaneously in
one direction?
a. Duplex
b. Diplex
c. Simplex
d. Quadruplex
Answer. b
38. A microprocessor is ALU
a. and control unit on a single chip
b. and memory on a single chip
c. register unit and I/O device on a single chip
d. register unit and control unit on a single chip
Answer. d
39. In Intel 8085 microprocessor, ALE signal is made high to
a. Enable the data bus to be used as low order address bus
b. To latch data D0— D7 from the data bus
c. To disable data bus
d. To achieve all the functions listed above
Answer. a
40. Output of the assembler in machine codes is referred to as
a. Object program
b. Source program
c. Macro instruction
d. Symbolic addressing
Answer. a
41. Which one of the following statements for Intel 8085 is correct?
a. Program counter (PC) specifies the address of the instruction last executed
b. PC specifies the address of the instruction being executed
c. PC specifies the address of the instruction be executed
d. PC specifies the number of instruction executed so far
Answer. c
42. The instruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
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43. Which one of the following statements is correct regarding the instruction
CMP A?
a. Compare accumulator with register A
b. Compare accumulator with memory
c. Compare accumulator with register H
d. This instruction does not exist
Answer. a
44. The instruction JNC 16-bit refers to jump to 16-bit address if
a. Sign flag is set
b. Carry flag is reset
c. Zero flag is set
d. Parity flag is reset
Answer. b
45. Consider the following interrupts for 8085 microprocessor:
1. INTR
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. TRAP
If the interrupt is to be vectored to any memory location then which of the above
interrupt is/are correct?
a. 1 and 2 only
b. 1, 2, 3 and 4
c. 5 only
d. 1 only
Answer. d
46. Consider the following statements:
1. Auxiliary carry flag is used only by the DAA and DAS instruction.
2. Zero flag is set to 1 if the two operands compared are equal.
3. All conditional jumps are long type jumps.
Which of the above statements are correct?
a. 1, 2 and 3 only
b. 1 and 2 only
c. 1 and 3 only
d. 2 and 3 only
Answer. b
47. Among the given instructions, the one which affects maximum number of
flags is
a. RAL
b. POP PSW
c. XRA A
d. DCR A
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Answer. c
48. XCHG instruction of 8085 exchanges the content of
a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
49. Direction flag is used with
a. String instructions
b. Stack instructions
c. Arithmetic instructions
d. Branch instructions
Answer. a
50. What will be the contents of DE and HL register pairs respectively after the
execution of the following instructions?
LXIH, 2500 H
LXID, 0200 H
DAD D
XCHG
a. 0200 H, 2500 H
b. 0200 H, 2700 H
c. 2500 H, 0200 H
d. 2700 H, 0200 H
Answer. d
UNIT-3
51. In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
52. A ‘DAD H” instruction is the same as shifting each bit by one position to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
53. When a program is being executed in an 8085 microprocessor, its program
counter contains
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a.
the memory address as the instruction that is to be executed next.
b.
the memory address of the instruction that is being currently matched.
c.
the total number of instructions in the program being executed.
d.
the number of instructions in the current program that have already been
executed.
Answer. a
54. Which of the following data transfer is not possible in microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
55. LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
d. loads English like command and generates the binary code
Answer. b
56. Which of the following instructions is closest match to the instruction POP
PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
57. How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
58. Which of the following 8085 instruction will require maximum T-states for
execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
59. In 8085 microprocessor, which mode of addressing does the instruction CMP
M use?
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a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
60. With reference to 8085 microprocessor, which of the following statements
are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
61. Assume that the accumulator and the register C of 8085 microprocessor
contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution of
instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
62. It is desired to multiply the numbers 0A H by OB H and store the result in the
accumulator. The numbers are available in registers B and C respectively. A part
of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C
b. ADD B; JNZ LOOP; DCR C
c. DCR C; JNZ LOOP; ADD B
d. ADD B; DCR C; JNZ LOOP
Answer. d
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63. Find the content of the accumulator after the execution of the following
program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
64. The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
65. The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
66. The content of accumulator are 70 H. Initially all flags are zero. What will be
values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
67. A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
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How many times DCR instruction will be executed?
a. 255
b. 510
c. 65025
d. 65279
Answer. d
68. What is content of accumulator of 8085 microprocessor after the execution of
XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
69. The 8085 programming manual says that it takes seven T states to fetch and
execute the MOV instruction. If the system clock has a frequency of 2.5 MHz, how
long is an instruction Cycle?
a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
70. The instruction PCHL, in 8085 is used for
a. Load PC with contents of HL.
b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
71. The following instruction copies a byte of data from the accumulator into the
memory address given in the instruction
a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
72. The instruction that exchanges top of stack with HL pair is
a. XTHL
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b. SPHL
c. PUSH H
d. POP H
Answer. a
73. In 8085 microprocessor, during PUSH PSW Operation, Stack pointer is
a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
74. While a program is being executed in an Intel 8085 microprocessor, the
program counter of the microprocessor contains:
a. The memory address of the instruction that is being currently executed.
b. The memory address of the instruction that is to be executed next.
c. The number of instructions that have already been executed.
d. The total number of instructions in the current program still to be
executed.
Answer. b
75. The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
76. If the status of the control lines SI and SO is LOW, then 8085 microprocessor
is performing
a. Reset operation
b. HOLD operation
c. Halt operation
d. Interrupt acknowledge
Answer. c
77. LXI SP, 7FFF H
MVI A, 25 H
XRI 02 H
PUSH PSW
POP H
MOV A,L
ORI 10 H
HLT
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What are the contents of A, H, L, SP and PSW registers after executing the above
set of instructions? Assume undefined flags always remain clear.
a. 10H, 25H, 00H, 7FFFH, 00H respectively
b. 14H, 27H, 04H, 7FFFH, 04H respectively
c. 14H, 25H, 00H. 7FFFH, 04H respectively
d. 10H, 27H, 04H, 7FFFH, 00H respectively
Answer. b
78. The content of the programme counter of an 8085 microprocessor is
a. the total number of instructions in the program already executed.
b. the total number of times a subroutine is called.
c. the memory address of the instruction that is being currently executed.
d. the memory address of the instruction that is to be executed next.
Answer. d
79. The opcode for the instruction “Add Immediately to Accumulator with carry”
in 8085 microprocessor is
a. ADI
b. ACI
c. ADC
d. ADD
Answer. b
80. MVI A, AA H
ORI FFH
RRC
RRC
CMC
INR A
What are the contents of A and PSW registers after executing the above set of
instructions in sequence?
a. AAH and 00H
b. FFH and 66H
c. 00H and 54H
d. 00H and 00H
Answer. c
81. For which one of the following, the instruction XRA A in 8085 microprocessor
can be used?
a. Set the carry flag
b. Set the zero flag
c. Reset the carry flag and clear the accumulator
d. Transfer FFH to the accumulator
Answer. b
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82. An 8085 microprocessor is executing the programme as follows:
MVI A, 20H
MVI B, 10H
BACK: NOP
ADD B
RLC
JNC BACK
HLT
How many times the instruction NOP will be executed?
a. 4
b. 3
c. 2
d. 1
Answer. b
83. The stack pointer of an 8085 microprocessor is ABCD H. At the end of
execution of the sequence of instructions, what will be the content of the stack
pointer?
PUSH PSW
XTHL
PUSH D
JMP FC70 H
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
84. What is the correct 8085 assembly language instruction that stores the
contents of H and L registers into the memory locations 1080 H and 1081 H
respectively?
a. SPHL 1080 H
b. SHLD 1080 H
c. STAX 1080 H
d. SPHL 1081 H
Answer. b
85. When the operand requires for instruction is stored inside the processor, then
What this addressing mode is called?
a. Direct
b. Register
c. Implicit
d. Immediate
Answer. b
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86. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
87. In an instruction of 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
88. Which one is the indirect addressing mode in the following instructions?
a. LXI H 2050 H
b. MOV A, B
c. LDAX B
d. LDA 2050 H
Answer. c
89. The addressing mode used in the instruction JMP F347 H in case of an Intel
8085A microprocessor is which one of the following?
a. Direct
b. Register—indirect
c. Implicit
d. Immediate
Answer. d
90. Carry flag is not affected after the execution of
a. ADD B
b. SBB B
c. INR B
d. ORA B
Answer. c
91. The contents of the Program Counter (PC), when the microprocessor is
reading from 2FFF H memory location, will be
a. 2FFE H
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b. 2FFF H
c. 3000 H
d. 3001 H
Answer. c
92. If the HLT instruction of an Intel 8085A microprocessor is executed
a. the microprocessor is disconnected from the system bus till the RESET is
pressed.
b. the microprocessor halts the execution of the program and returns to the
monitor.
c. the microprocessor enters into a HALT state and the buses are tri-stated.
d. the microprocessor reloads the program counter from the locations 0024 H
and 0025 H.
Answer. c
93. The stack pointer of an 8085 A microprocessor contains ABCD H.
PUSH PSW
XTHL
PUSH D
JMP EC75 H
At the end of the execution of the above instructions, what would be the content
of the stack pointer?
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
94. In an Intel 8085 A, what is the content of the Instruction Register (IR)?
a. Op-code for the instruction being executed
b. Operand for the instruction being executed
c. Op-code for the instruction to be executed next
d. Operand for the instruction to be executed next
Answer. a
95. The content of the Program Counter of an intel 8085A microprocessor
specifies which one of the following?
a. The address of the instruction being executed
b. The address of the instruction executed earlier
c. The address of the next instruction to be executed
d. The number of instructions executed so far
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Answer. c
96. Which one of the following statement does not describe
property/characteristic of a stack pointer register in 8085 microprocessor?
a. It points to the top of the stack.
b. It is UP/DOWN counter
c. It is automatically initialized to 0000 H on power-on
d. It is a 16-bit register
Answer. c
97. Which one of the following instructions is a 3-byte instruction?
a. MVI A
b. LDAX B
c. JMP 2050 H
d. MOV A,M
Answer. c
98. In 8085, the DAA instruction is used for
a. Direct Address Accumulator
b. Double Add Accumulator
c. Decimal Adjust Accumulator
d. Direct Access Accumulator
Answer. c
99. When an 8086 executes an INT type instruction, it?
a. Resets both IF and TF flags
b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
100. When an 8086 executes an INT type instruction, it?
a. Resets both IF and TF flags
b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
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UNIT-4
ASSEMBLY LANGUAGE PROGRAMMING Multiple Choice Questions :-
1) Assembly language programs are written using
A) Hex code
B) Mnenonics
C) ASCII code
D) None of these View
ANS: B
2) For execution of an interrupt applied at INTR, number of states required by
8085 Microprocessor are
A) 4
B) 6
C) 12
D) 18
ANS: C
3) In 8085 which is/are the 16 bit registers?
A) Program Counter
B) Stack Pointer
C) Both A) & B)
D) None of the above
ANS: C
4) How many memory locations are required to store the instruction LXIH,
0800H in an 8085 assembly language program?
A) 1
B) 2
C) 3
D) 4
ANS: B
5) The instruction DEC N inform the assembler to....
A) Decrement the content of N
B) Decrement the data addressed by N
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C) Convert signed decimal number to binary
D) None of the above
ANS: A
6) In 8085 microprocessor, the value of the most significant bit of the result
following the execution of any arithmetic or Boolean instruction is stored in
the
A) carry status flag
B) auxiliary carry status flag
C) sign status flag
D) zero status flag
ANS: C
7) Instructions performing actions in assembly language are called
A) imperative statements
B) declarative statements
C) directive statements
D) none of the above
ANS: A
8) What is the content of Stack Pointer ?
A) Address of the current instruction
B) Address of the next instruction
C) Address of the top element of the stack
D) None of the above
ANS: C
9) Which of the following interrupt has highest Priority?
A) INTR
B) TRAP
C) RST 7.5
D) RST 6.5
ANS: B
10) Number of machine cycles required for RET instruction in 8085
microprocessor is
A) 1
B) 2
C) 3
D) 5
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ANS: C
11) __________ converts the programs written in assembly language into
machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
Answer: c
Clarification: An assembler is a software used to convert the programs into
machine instructions.
12) The instructions like MOV or ADD are called as ______
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned
Answer: a
Clarification: This OP – codes tell the system what operation to perform on the
operands.
13) The alternate way of writing the instruction, ADD #5,R1 is ______
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way
Answer: b
Clarification: The ADDI instruction, means the addition is in immediate
addressing mode.
14) Instructions which won’t appear in the object program are called as
_____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
Answer: d
Clarification: The directives help the program in getting compiled and hence
won’t be there in the object code.
15) The assembler directive EQU, when used in the instruction: Sum EQU
200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
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c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
Answer: b
Clarification: This basically is used to replace the variable with a constant value.
16) The purpose of the ORIGIN directive is __________
a) To indicate the starting position in memory, where the program block is
to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used
Answer: a
Clarification: This does the function similar to the main statement.
17) The directive used to perform initialization before the execution of
the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU
Answer: c
Clarification: None.
18) _____ directive is used to specify and assign the memory required for
the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve
Answer: d
Clarification: This instruction is used to allocate a block of memory and to store
the object code of the program there.
19) _____ directive specifies the end of execution of a program.
a) End
b) Return
c) Stop
d) Terminate
Answer: b
Clarification: This instruction directive is used to terminate the program
execution.
20) The last statement of the source program should be _______
a) Stop
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b) Return
c) OP
d) End
Answer: d
Clarification: This enables the processor to load some other process.
21) When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive
Answer: c
Clarification: When the assembler comes across the branch code, it immediately
finds the branch offset and replaces it with it.
22) The assembler stores all the names and their corresponding values in
______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned
Answer: b
Clarification: The table where the assembler stores the variable names along with
their corresponding memory locations and values.
23) The assembler stores the object code in ______
a) Main memory
b) Cache
c) RAM
d) Magnetic disk
Answer: d
Clarification: After compiling the object code, the assembler stores it in the
magnetic disk and waits for further execution.
24) The utility program used to bring the object code into memory for
execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker
Answer: a
Clarification: The program is used to load the program into memory.
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25) To overcome the problems of the assembler in dealing with
branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
Answer: d
Clarification: This creates entries into the symbol table first and then creates the
object code.
26) In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
27) A ‘DAD H” instruction is the same as shifting each bit by one position
to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
28) When a program is being executed in an 8085 microprocessor, its
program counter contains
a. the memory address as the instruction that is to be executed next.
b. the memory address of the instruction that is being currently matched.
c. the total number of instructions in the program being executed.
d. the number of instructions in the current program that have already been
executed.
Answer. a
29) Which of the following data transfer is not possible in
microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
30) LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
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d. loads English like command and generates the binary code
Answer. b
31) Which of the following instructions is closest match to the
instruction POP PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
32) How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
33) Which of the following 8085 instruction will require maximum T-
states for execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
34) In 8085 microprocessor, which mode of addressing does the
instruction CMP M use?
a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
35) With reference to 8085 microprocessor, which of the following
statements are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
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36) Assume that the accumulator and the register C of 8085
microprocessor contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution
of instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
37) It is desired to multiply the numbers 0A H by OB H and store the
result in the accumulator. The numbers are available in registers B and C
respectively. A part of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C
b. ADD B; JNZ LOOP; DCR C
c. DCR C; JNZ LOOP; ADD B
d. ADD B; DCR C; JNZ LOOP
Answer. d
38) Find the content of the accumulator after the execution of the
following program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
39) The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
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a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
40) The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
41) The content of accumulator are 70 H. Initially all flags are zero. What
will be values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
42) A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR instruction will be executed?
a. 255
b. 510
c. 65025
d. 65279
Answer. d
43) What is content of accumulator of 8085 microprocessor after the
execution of XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
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44) The 8085 programming manual says that it takes seven T states to
fetch and execute the MOV instruction. If the system clock has a frequency
of 2.5 MHz, how long is an instruction Cycle?
a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
45) The instruction PCHL, in 8085 is used for
a. Load PC with contents of HL.
b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
46) The following instruction copies a byte of data from the accumulator
into the memory address given in the instruction
a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
47) The instruction that exchanges top of stack with HL pair is
a. XTHL
b. SPHL
c. PUSH H
d. POP H
Answer. a
48) In 8085 microprocessor, during PUSH PSW Operation, Stack pointer
is
a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
49) While a program is being executed in an Intel 8085 microprocessor,
the program counter of the microprocessor contains:
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a.The memory address of the instruction that is being currently executed.
b.The memory address of the instruction that is to be executed next.
c.The number of instructions that have already been executed.
d.The total number of instructions in the current program still to be
executed.
Answer. b
50) The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
UNIT-5
Microprocessors Questions and Answers – Programmable DMA Interface
8237 (Part-1)
1. The block of 8237 that decodes the various commands given to the 8237 by the
CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: b
Explanation: The program control block decodes various commands given to the
8237 by the CPU before servicing a DMA request.
2. The priority between the DMA channels requesting the services can be
resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: c
Explanation: The priority encoder block resolves the priority between the DMA
channels requesting the services.
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3. The register that holds the current memory address is
a) current word register
b) current address register
c) base address register
d) command register
Answer: b
Explanation: The current address register holds the current memory address. The
current address register is accessed during the DMA transfer.
4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register
Answer: a
Explanation: The current word register is a 16-bit register that holds the data
transfers. The word count is decremented after each transfer, and the new value
is stored again in the register.
5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated
Answer: c
Explanation: When the count becomes zero, the EOP signal is generated. This can
be written in successive bytes by the CPU, in program mode.
6. The current address register is programmed by the CPU as
a) bit-wise
b) byte-wise
c) bit-wise and byte-wise
d) none of the mentioned
View Answer
Explanation: The current address register is byte-wise programmed by the CPU,
i.e. lower byte first and the higher byte later.
7. Which of these register’s contents is used for auto-initialization (internally)?
a) current word register
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b) current address register
c) base address register
d) command register
Answer: c
Explanation: The contents of base address register cannot be read by the CPU.
These contents are used internally for auto-initialization.
8. The register that maintains an original copy of the respective initial current
address register and current word register is
a) mode register
b) base address register
c) command register
d) mask register
Answer: b
Explanation: The base address register maintains an original copy of the current
address register and current word register, before incrementing or
decrementing.
9. The register that can be automatically incremented or decremented, after each
DMA transfer is
a) mask register
b) mode register
c) command register
d) current address register
Answer: d
Explanation: The address is automatically incremented or decremented after
each DMA transfer, and the resulting address value is again stored in the current
address register.
10. Which of the following is a type of DMA transfer?
a) memory read
b) memory write
c) verify transfer
d) all of the mentioned
Answer: d
Explanation: Memory read, memory write and verify transfer are the three types
of DMA transfer.
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Microprocessors Questions and Answers – 8255 programmable peripheral
interface-(Part-2)
Question 1: How many pins does the 8255 PPI IC contains?
a. 24
b. 20
c. 32
d. 40
Answer: d. 40
Question 2: In which mode do all the Ports of the 8255 PPI work as Input-Output
units for data transfer?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: b. Mode 0 of I/O mode
Question 3: Which of the following pins are responsible for handling the on the
Read Write control logic unit of the 8255 PPI?
a. CS'
b. RD'
c. WR'
d. ALL of the above
Answer: d. All of the above
Question 4: In which of the following modes is the 8255 PPI capable of
transferring data while handshaking with the interfaced device?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: c. Mode 1 of I/O mode
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Question 5: How many bits of data can be transferred between the 8255 PPI and
the interfaced device at a time? or What is the size of internal bus of the 8255
PPI?
a. 16 bits
b. 12 bits
c. 8 bits
d. None of the above
Answer: c. 8 bits
Question 6: Which port of the 8255 PPI is capable of performing the handshaking
function with the interfaced devices?
a. Port A
b. Port B
c. Port C
d. All of the above
Answer: c. Port C
Question 7: In which of the following modes of the 8255 PPI, only port C is taken
into consideration?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: a. BSR mode
Question 8: In mode 2 of I/O mode, which of the following ports are capable of
transferring the data in both the directions?
a. Port A
b. Port B
c. Port C
d. All of the above
Answer: a. Port A
Question 9: In which of the following modes we do not consider the D6, D5 and
D4 bits of the control word?
a. BSR mode
b. Mode 0 of I/O mode
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c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: a. BSR mode
Question 10: How many data lines in total are there in the 8255 PPI IC?
a. 8 data lines
b. 32 data lines
c. 24 data lines
d. None of the above
Answer: c. 24 data lines
Microprocessors Questions and Answers – 8253/8254programmable
timer/counter-(Part-3)
1. The number of counters that are present in the programmable timer device
8254 is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: There are three counters that can be used as either counters or
delay generators.
2. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
Answer: b
Explanation: The control word register can only be written and cannot be read.
3. The mode that is used to interrupt the processor by setting a suitable terminal
count is
a) mode 0
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b) mode 1
c) mode 2
d) mode 3
Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.
4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output
becomes low for
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If
the count N is reloaded and again the output becomes high and remains so for (N-
1) clock pulses.
5. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Answer: c
Explanation: When the count N loaded is even, then for half of the count, the
output remains high and for the remaining half it remains low. If the count loaded
is odd, the first clock pulse decrements it by 1 resulting in an even count value.
6. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
Answer: b
Explanation: SC denotes select counter.
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7. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.
8. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is
BCD count.
9. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.
10. The control word register contents are used for
a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.
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Microprocessors Questions and Answers – 8259 programmable interrupt
controller-(Part-4)
1. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7
View Answer
Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these
five, four pins were alloted fixed vector addresses but the pin INTR was not
alloted by vector address, rather an external device was supposed to hand over
the type of the interrupt to the microprocessor.
2. The register that stores all the interrupt requests in it in order to serve them
one by one on a priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request
Register internally.
3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request
Register) at the direction of the Priority Resolver.
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4. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
Answer: d
Explanation: The interrupt control logic performs all the operations that are
involved within the interrupts like accepting and managing interrupt
acknowledge signals, interrupts.
5. In a cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64
vectored interrupts can be provided.
6. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode,
then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a
buffer enable to control buffer transreceivers. If it is not used in buffered mode,
then the pin is used as input to designate whether the chip is used as a master or
a slave.
7. Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
Answer: d
Explanation: The initialization procedure involves
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i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.
8. When non-specific EOI command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will
automatically reset the highest ISR.
9. In the application where all the interrupting devices are of equal priority, the
mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
Answer: a
Explanation: The automatic rotation is used in the applications where all the
interrupting devices are of equal priority.
Microprocessors Questions and Answers – 8251 USART and
RS232C- (Part-5)
1. Which of the following is not a mode of data transmission?
a) simplex
b) duplex
c) semi duplex
d) half duplex
Answer: c
Explanation: Basically, there are three modes of data transmission. simplex,
duplex and half duplex.
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2. If the data is transmitted only in one direction over a single communication
channel, then it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: a
Explanation: In simplex mode, the data transmission is unidirectional. For
example, a CPU may transmit data for a CRT display unit in this mode.
3. If the data transmission takes place in either direction, but at a time data may
be transmitted only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: d
Explanation: In half duplex mode, data transmission is bidirectional but not at a
time. For example, Walkie-Talkie.
4. In 8251A, the pin that controls the rate at which the character is to be
transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)
Answer: a
Explanation: Transmitter Clock Input (TXC(active low)) is a pin that controls the
rate at which the character is to be transmitted.
5. TXD(Transmitted Data Output) pin carries serial stream of the transmitted
data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned
Answer: d
Explanation: Transmitted Data Output pin carries a serial stream of the
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transmitted data bits along with other information like start bits, stop bits and
parity bits etc.
6. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY(Transmitter ready)
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)
Answer: b
Explanation: RXRDY(Receiver ready output) may be used either to interrupt the
CPU or polled by the CPU.
7. The disadvantage of RS-232C is
a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned
Answer: d
Explanation: RS232C has been used for long and has a few disadvantages like
limited speed of communication, high-voltage level signaling and big-size
communication adapters.
8. The USB supports the signaling rate of
a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned
Answer: d
Explanation: The USB standards support the signaling rates. Also, USB signaling is
implemented in a differential in low- and full-speed options.
9. The bit packet that commands the device either to receive data or transmit
data in transmission of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
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Answer: b
Explanation: The token packet is the second type of packet which commands the
device either to receive data or transmit data.
10. High speed USB devices neglect
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
Answer: c
Explanation: PRE packets are only of importance to low-speed USB devices.
Microprocessor Interview
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Microprocessor Interview Questions And Answers
G
Microprocessor Job Interview Preparation Guide.
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Question # 1
What is a Microprocessor?
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Answer:-
Microprocessor is a program-controlled device, which fetches the instructions from memory, decodes and executes the instructions. Most Micro Processor are single-
chip devices.
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Question # 2
What are the flags in 8086?
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Answer:-
In 8086 Carry flag, Parity flag, Auxiliary carry flag, Zero flag, Overflow flag, Trace flag, Interrupt flag, Direction flag, and Sign flag.
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Question # 3
Why crystal is a preferred clock source?
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Answer:-
Because of high stability, large Q (Quality Factor) & the frequency that doesn't drift with aging. Crystal is used as a clock source most of the times.
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Question # 4
In 8085 which is called as High order / Low order Register?
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Answer:-
Flag is called as Low order register & Accumulator is called as High order Register.
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Question # 5
What is Tri-state logic?
Answer:-
Three Logic Levels are used and they are High, Low, High impedance state. The high and low are normal logic levels & high impedance state is electrical open
circuit conditions. Tri-state logic has a third line called enable line.
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Question # 6
What happens when HLT instruction is executed in processor?
Answer:-
The Micro Processor enters into Halt-State and the buses are tri-stated.
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Question # 7
Which Stack is used in 8085?
Answer:-
LIFO (Last In First Out) stack is used in 8085.In this type of Stack the last stored information can be retrieved first
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Microprocessor Interview Questions And Answers
Question # 8
What is Program counter?
Answer:-
Program counter holds the address of either the first byte of the next instruction to be fetched for execution or the address of the next byte of a multi byte instruction,
which has not been completely fetched. In both the cases it gets incremented automatically one by one as the instruction bytes get fetched. Also Program register
keeps the address of the next instruction
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Question # 9
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What are the various registers in 8085?
Answer:-
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Accumulator register, Temporary register, Instruction register, Stack Pointer, Program Counter are the various registers in 8085
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Question # 10
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What is 1st / 2nd / 3rd / 4th generation processor?
Answer:-
The processor made of PMOS / NMOS / HMOS / HCMOS technology is called 1st / 2nd / 3rd / 4th generation processor, and it is made up of 4 / 8 / 16 / 32 bits.
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Question # 11
Name the processor lines of two major manufacturer?
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Answer:-
High-end: Intel - Pentium (II, III, 4), AMD - Athlon. Low-end: Intel - Celeron, AMD - Duron. 64-bit: Intel - Itanium 2, AMD - Opteron.
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Question # 12
What's the speed and device maximum specs for Firewire?
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Answer:-
IEEE 1394 (Firewire) supports the maximum of 63 connected devices with speeds up to 400 Mbps. Where's MBR located on the disk? Main Boot Record is located
in sector 0, track 0, head 0, cylinder 0 of the primary active partition.
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Question # 13
Where does the CPU Enhanced mode originate from?
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Answer:-
Intel's 80386 was the first 32-bit processor, and since the company had to backward-support the 8086. All the modern Intel-based processors run in the Enhanced
mode, capable of switching between Real mode (just like the real 8086) and Protected mode, which is the current mode of operation.
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Question # 14
How many bit combinations are there in a byte?
Answer:-
Byte contains 8 combinations of bits.
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Question # 15
Have you studied buses? What types?
Answer:-
There are three types of buses.
Address bus: This is used to carry the Address to the memory to fetch either Instruction or Data.
Data bus : This is used to carry the Data from the memory.
Control bus : This is used to carry the Control signals like RD/WR, Select etc.
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Question # 16
What is the Maximum clock frequency in 8086?
Answer:-
5 Mhz is the Maximum clock frequency in 8086.
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Question # 17
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Microprocessor Interview Questions And Answers
What is meant by Maskable interrupts?
Answer:-
An interrupt that can be turned off by the programmer is known as Maskable interrupt.
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Question # 18
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What is Non-Maskable interrupts?
Answer:-
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An interrupt which can be never be turned off (ie. disabled) is known as Non-Maskable interrupt
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Question # 19
What are the different functional units in 8086?
Answer:-
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Bus Interface Unit and Execution unit, are the two different functional units in 8086.
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Question # 20
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What are the various segment registers in 8086?
Answer:-
Code, Data, Stack, Extra Segment registers in 8086.
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Question # 21
What does the EU do?
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Answer:-
Execution Unit receives program instruction codes and data from BIU, executes these instructions and store the result in general registers.
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Question # 22
Which Stack is used in 8086? k is used in 8086?
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Answer:-
FIFO (First In First Out) stack is used in 8086.In this type of Stack the first stored information is retrieved first.
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Question # 23
What are the major flags in 8086?
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Answer:-
In 8086 Carry flag, Parity flag, Auxiliary carry flag, Zero flag, Overflow flag, Trace flag, Interrupt flag, Direction flag, and Sign flag.
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Question # 24
What is SIM and RIM instructions?
Answer:-
SIM is Set Interrupt Mask. Used to mask the hardware interrupts.
RIM is Read Interrupt Mask. Used to check whether the interrupt is Masked or not.
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Computer Hardware Most Popular Interview Topics.
1 : Basic Computer Frequently Asked Interview Questions and Answers Guide.
2 : A + (Plus) Hardware Frequently Asked Interview Questions and Answers Guide.
3 : Computer Architecture Frequently Asked Interview Questions and Answers Guide.
4 : Electronics Frequently Asked Interview Questions and Answers Guide.
5 : Embedded System Frequently Asked Interview Questions and Answers Guide.
6 : Motherboard Frequently Asked Interview Questions and Answers Guide.
7 : 8085 Frequently Asked Interview Questions and Answers Guide.
8 : Basic Input Output System Frequently Asked Interview Questions and Answers Guide.
9 : Random Access Memory Frequently Asked Interview Questions and Answers Guide.
10 : 8086 Frequently Asked Interview Questions and Answers Guide.
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1. A Process Control Block(PCB) does not contain which of the following?
a) Code
b) Stack
c) Bootstrap program
d) Data
Answer: d
Explanation: Process Control Block (PC
b) contains information related to a process such as Process State, Program Counter, CPU Register, etc. Process Con
trol Block is also known as Task Control Block. Bootstrap program is a program which runs initially when the syste
m or computer is booted or rebooted.
2. The number of processes completed per unit time is known as __________
a) Output
b) Throughput
c) Efficiency
d) Capacity
Answer: a
Explanation: The number of processes completed per unit time is known as Throughput. Suppose there are 4 process
es A, B, C & D they are taking 1, 3, 4 & 7 units of time respectively for their executions. For 10 units of time, throu
ghput is high if process A, B & C are running first as 3 processes can execute. If process C runs first then throughput
is low as maximum only 2 processes can execute. Throughput is low for processes which take a long time for execu
tion. Throughput is high for processes which take a short time for execution.
3. The state of a process is defined by __________
a) the final activity of the process
b) the activity just executed by the process
c) the activity to next be executed by the process
d) the current activity of the process
Answer: c
Explanation: The state of a process is defined by the current activity of the process. A process state changes when th
e process executes. The process states are as New, Ready, Running, Wait, Terminated.
1. Which of the following do not belong to queues for processes?
a) Job Queue
b) PCB queue
c) Device Queue
d) Ready Queue
Answer: c
Explanation: PCB queue does not belong to queues for processes. PCB is a process control block which contains inf
ormation related to process. Each process is represented by PCB.
2. When the process issues an I/O request __________
a) It is placed in an I/O queue
b) It is placed in a waiting queue
c) It is placed in the ready queue
d) It is placed in the Job queue
Answer: c
Explanation: When the process issues an I/O request it is placed in an I/O queue. I/O is a resource and it should be u
sed effectively and every process should get access to it. There might be multiple processes which requested for I/O.
Depending on scheduling algorithm I/O is allocated to any particular process and after completing I/O operation, I/
O access is returned to the OS.
3. What will happen when a process terminates?
a) It is removed from all queues
b) It is removed from all, but the job queue
c) Its process control block is de-allocated
d) Its process control block is never de-allocated
Answer: a
Explanation: When a process terminates, it removes from all queues. All allocated resources to that particular proces
s are deallocated and all those resources are returned back to OS.
4. What is a long-term scheduler?
a) It selects processes which have to be brought into the ready queue
b) It selects processes which have to be executed next and allocates CPU
c) It selects processes which heave to remove from memory by swapping
d) None of the mentioned
Answer: b
Explanation: A long-term scheduler selects processes which have to be brought into the ready queue. When processe
s enter the system, they are put in the job queue. Long-term scheduler selects processes from the job queue and puts
them in the ready queue. It is also known as Job Scheduler.
5. If all processes I/O bound, the ready queue will almost always be ______ and the Short term Scheduler will have
a ______ to do.
a) full, little
b) full, lot
c) empty, little
d) empty, lot
Answer: c
Explanation: If all processes are I/O bound, the ready queue will almost empty and the short-term scheduler will hav
e a little to do. I/O bound processes spend more time doing I/O than computation.
6. What is a medium-term scheduler?
a) It selects which process has to be brought into the ready queue
b) It selects which process has to be executed next and allocates CPU
c) It selects which process to remove from memory by swapping
d) None of the mentioned
Answer: b
Explanation: A medium-term scheduler selects which process to remove from memory by swapping. The medium-te
rm scheduler swapped out the process and later swapped in. Swapping helps to free up memory.
7. What is a short-term scheduler?
a) It selects which process has to be brought into the ready queue
b) It selects which process has to be executed next and allocates CPU
c) It selects which process to remove from memory by swapping
d) None of the mentioned
Answer: d
Explanation: A short-term scheduler selects a process which has to be executed next and allocates CPU. Short-term
scheduler selects a process from the ready queue. It selects processes frequently.
8. The primary distinction between the short term scheduler and the long term scheduler is __________
a) The length of their queues
b) The type of processes they schedule
c) The frequency of their execution
d) None of the mentioned
Answer: b
Explanation: The primary distinction between the short-term scheduler and the long-term scheduler is the frequency
of their execution. The short-term scheduler executes frequently while the long-term scheduler executes much less fr
equently.
9. The only state transition that is initiated by the user process itself is __________
a) block
b) wakeup
c) dispatch
d) none of the mentioned
Answer: c
Explanation: The only state transition that is initiated by the user process itself is block. Whenever a user process ini
tiates an I/O request it goes into block state unless and until the I/O request is not completed.
1. Restricting the child process to a subset of the parent’s resources prevents any process from __________
a) overloading the system by using a lot of secondary storage
b) under-loading the system by very less CPU utilization
c) overloading the system by creating a lot of sub-processes
d) crashing the system by utilizing multiple resources
Answer: c
Explanation: Restricting the child process to a subset of the parent’s resources prevents any process from overloadin
g the system by creating a lot of sub-processes. A process creates a child process, child process requires certain reso
urces to complete its task. A child process can demand required resources directly from the system, but by doing this
system will be overloaded. So to avoid overloading of the system, the parent process shares its resources among chi
ldren.
2. A parent process calling _____ system call will be suspended until children processes terminate.
a) wait
b) fork
c) exit
d) exec
Answer: a
Explanation: A parent process calling wait system call will be suspended until children processes terminate. A para
meter is passed to wait system call which will obtain exit status of child as well as wait system call returns PID of ter
minated process.
3. Cascading termination refers to termination of all child processes if the parent process terminates ______
a) Normally
b) Abnormally
c) Normally or abnormally
d) None of the mentioned
Answer: c
Explanation: Cascading termination refers to termination of all child processes if the parent process terminates Norm
ally or Abnormally. Some systems don’t allow child processes to exist if the parent process has terminated. Cascadin
g termination is normally initiated by the operating system.
4. With _____________ only one process can execute at a time; meanwhile all other process are waiting for the proc
essor. With ______________ more than one process can be running simultaneously each on a different processor.
a) Multiprocessing, Multiprogramming
b) Multiprogramming, Uniprocessing
c) Multiprogramming, Multiprocessing
d) Uniprogramming, Multiprocessing
Answer: d
Explanation: With Uniprogramming only one process can execute at a time; meanwhile all other processes are waiti
ng for the processor. With Multiprocessing more than one process can run simultaneously each on different processo
rs. The Uniprogramming system has only one program inside the core while the Multiprocessing system has multipl
e processes inside multiple cores. The core is one which executes instructions and stores data locally into registers.
5. In UNIX, each process is identified by its __________
a) Process Control Block
b) Device Queue
c) Process Identifier
d) None of the mentioned
Answer: c
Explanation: In Unix, each process is identified by its Process Identifier or PID. The PID provides unique value to e
ach process in the system so that each process can be identified uniquely.
6. In UNIX, the return value for the fork system call is _____ for the child process and _____ for the parent process.
a) A Negative integer, Zero
b) Zero, A Negative integer
c) Zero, A nonzero integer
d) A nonzero integer, Zero
Answer: c
Explanation: In Unix, the return value of the fork system call is Zero for the child process and Non-zero value for pa
rent process. A fork system call returns the PID of a newly created (chil
d) process to the parent and returns Zero to that newly created (chil
d) process.
7. The child process can __________
a) be a duplicate of the parent process
b) never be a duplicate of the parent process
c) cannot have another program loaded into it
d) never have another program loaded into it
Answer: a
Explanation: The child process can be a duplicate of the parent process. The child process created by fork consists of
a copy of the address space of the parent process.
8. The child process completes execution, but the parent keeps executing, then the child process is known as ______
____
a) Orphan
b) Zombie
c) Body
d) Dead
Answer: b
Explanation: The child process completes execution, but the parent keeps executing, then the child process is known
as Zombie. When a child process terminates, its resources get deallocated but its entry in the Process Control Block
(PC
b) remains there until its parent calls wait system call.
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1. What is Interprocess communication?
a) allows processes to communicate and synchronize their actions when using the same address space
b) allows processes to communicate and synchronize their actions
c) allows the processes to only synchronize their actions without communication
d) none of the mentioned
Answer: b
Explanation: Interprocess Communication allows processes to communicate and synchronize their actions. Interproc
ess Communication (IP
c) mechanism is used by cooperating processes to exchange data and information.
2. Message passing system allows processes to __________
a) communicate with each other without sharing the same address space
b) communicate with one another by resorting to shared data
c) share data
d) name the recipient or sender of the message
Answer: a
Explanation: Message Passing system allows processes to communicate with each other without sharing the same ad
dress space.
3. Which of the following two operations are provided by the IPC facility?
a) write & delete message
b) delete & receive message
c) send & delete message
d) receive & send message
Answer: d
Explanation: Two operations provided by the IPC facility are receive and send messages. Exchange of data takes pla
ce in cooperating processes.
4. Messages sent by a process __________
a) have to be of a fixed size
b) have to be a variable size
c) can be fixed or variable sized
d) none of the mentioned
Answer: c
Explanation: Messages sent by a process can be fixed or variable size. If the message size of the process is fixed the
n system level implementation is straightforward but it makes the task of programming more difficult. If the messag
e size of the process is variable then system level implementation is more complex but it makes the task of program
ming simpler.
5. The link between two processes P and Q to send and receive messages is called __________
a) communication link
b) message-passing link
c) synchronization link
d) all of the mentioned
Answer: a
Explanation: The link between two processes P and Q to send and receive messages is called communication link. T
wo processes P and Q want to communicate with each other; there should be a communication link that must exist b
etween these two processes so that both processes can able to send and receive messages using that link.
6. Which of the following are TRUE for direct communication?
a) A communication link can be associated with N number of process(N = max. number of processes supported by s
ystem)
b) A communication link is associated with exactly two processes
c) Exactly N/2 links exist between each pair of processes(N = max. number of processes supported by system)
d) Exactly two link exists between each pair of processes
Answer: b
Explanation: For direct communication, a communication link is associated with exactly two processes. One commu
nication link must exist between a pair of processes.
7. In indirect communication between processes P and Q __________
a) there is another process R to handle and pass on the messages between P and Q
b) there is another machine between the two processes to help communication
c) there is a mailbox to help communication between P and Q
d) none of the mentioned
Answer: c
Explanation: In indirect communication between processes P and Q there is a mailbox to help communication betwe
en P and Q. A mailbox can be viewed abstractly as an object into which messages can be placed by processes and fr
om which messages can be removed.
8. In the non blocking send __________
a) the sending process keeps sending until the message is received
b) the sending process sends the message and resumes operation
c) the sending process keeps sending until it receives a message
d) none of the mentioned
Answer: b
Explanation: In the non blocking send, the sending process sends the message and resumes operation. Sending proce
ss doesn’t care about reception. It is also known as asynchronous send.
9. In the Zero capacity queue __________
a) the queue can store at least one message
b) the sender blocks until the receiver receives the message
c) the sender keeps sending and the messages don’t wait in the queue
d) none of the mentioned
Answer: b
Explanation: In the Zero capacity queue the sender blocks until the receiver receives the message. Zero capacity que
ue has maximum capacity of Zero; thus message queue does not have any waiting message in it.
10. The Zero Capacity queue __________
a) is referred to as a message system with buffering
b) is referred to as a message system with no buffering
c) is referred to as a link
d) none of the mentioned
Answer: b
Explanation: The Zero capacity queue is referred to as a message system with no buffering. Zero capacity queue has
maximum capacity of Zero; thus message queue does not have any waiting message in it.
11. Bounded capacity and Unbounded capacity queues are referred to as __________
a) Programmed buffering
b) Automatic buffering
c) User defined buffering
d) No buffering
Answer: b
Explanation: Bounded capacity and Unbounded capacity queues are referred to as Automatic buffering. Buffer capa
city of the Bounded capacity queue is finite length and buffer capacity of the Unbounded queue is infinite.
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1. Remote Procedure Calls are used ____________
a) for communication between two processes remotely different from each other on the same system
b) for communication between two processes on the same system
c) for communication between two processes on separate systems
d) none of the mentioned
Answer: c
Explanation: None.
2. To differentiate the many network services a system supports ______ are used.
a) Variables
b) Sockets
c) Ports
d) Service names
Answer: c
Explanation: None.
3. RPC provides a(an) _____ on the client-side, a separate one for each remote procedure.
a) stub
b) identifier
c) name
d) process identifier
Answer: a
Explanation: None.
4. What is stub?
a) transmits the message to the server where the server side stub receives the message and invokes procedure on the
server side
b) packs the parameters into a form transmittable over the network
c) locates the port on the server
d) all of the mentioned
Answer: d
Explanation: None.
5. To resolve the problem of data representation on different systems RPCs define _____________
a) machine dependent representation of data
b) machine representation of data
c) machine-independent representation of data
d) none of the mentioned
Answer: c
Explanation: None.
6. What is the full form of RMI?
a) Remote Memory Installation
b) Remote Memory Invocation
c) Remote Method Installation
d) Remote Method Invocation
Answer: d
Explanation: None.
7. The remote method invocation __________
a) allows a process to invoke memory on a remote object
b) allows a thread to invoke a method on a remote object
c) allows a thread to invoke memory on a remote object
d) allows a process to invoke a method on a remote object
Answer: b
Explanation: None.
8. A process that is based on IPC mechanism which executes on different systems and can communicate with other
processes using message based communication, is called ________
a) Local Procedure Call
b) Inter Process Communication
c) Remote Procedure Call
d) Remote Machine Invocation
Answer: c
Explanation: None.
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1. The initial program that is run when the computer is powered up is called __________
a) boot program
b) bootloader
c) initializer
d) bootstrap program
Answer: d
Explanation: None.
2. How does the software trigger an interrupt?
a) Sending signals to CPU through bus
b) Executing a special operation called system call
c) Executing a special program called system program
d) Executing a special program called interrupt trigger program
Answer: b
Explanation: None.
3. What is a trap/exception?
a) hardware generated interrupt caused by an error
b) software generated interrupt caused by an error
c) user generated interrupt caused by an error
d) none of the mentioned
Answer: b
Explanation: None.
4. What is an ISR?
a) Information Service Request
b) Interrupt Service Request
c) Interrupt Service Routine
d) Information Service Routine
Answer: c
Explanation: None.
5. What is an interrupt vector?
a) It is an address that is indexed to an interrupt handler
b) It is a unique device number that is indexed by an address
c) It is a unique identity given to an interrupt
d) None of the mentioned
Answer: a
Explanation: None.
6. DMA is used for __________
a) High speed devices(disks and communications network)
b) Low speed devices
c) Utilizing CPU cycles
d) All of the mentioned
Answer: a
Explanation: None.
7. In a memory mapped input/output __________
a) the CPU uses polling to watch the control bit constantly, looping to see if a device is ready
b) the CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available
c) the CPU receives an interrupt when the device is ready for the next byte
d) the CPU runs a user written code and does accordingly
Answer: b
Explanation: None.
8. In a programmed input/output(PIO) __________
a) the CPU uses polling to watch the control bit constantly, looping to see if a device is ready
b) the CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available
c) the CPU receives an interrupt when the device is ready for the next byte
d) the CPU runs a user written code and does accordingly
Answer: a
Explanation: None.
9. In an interrupt driven input/output __________
a) the CPU uses polling to watch the control bit constantly, looping to see if a device is ready
b) the CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available
c) the CPU receives an interrupt when the device is ready for the next byte
d) the CPU runs a user written code and does accordingly
Answer: c
Explanation: None.
10. In the layered approach of Operating Systems __________
a) Bottom Layer(0) is the User interface
b) Highest Layer(N) is the User interface
c) Bottom Layer(N) is the hardware
d) Highest Layer(N) is the hardware
Answer: b
Explanation: None.
11. How does the Hardware trigger an interrupt?
a) Sending signals to CPU through a system bus
b) Executing a special program called interrupt program
c) Executing a special program called system program
d) Executing a special operation called system call
Answer: a
Explanation: None.
12. Which operation is performed by an interrupt handler?
a) Saving the current state of the system
b) Loading the interrupt handling code and executing it
c) Once done handling, bringing back the system to the original state it was before the interrupt occurred
d) All of the mentioned
Answer: d
Explanation: None.
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1. CPU scheduling is the basis of ___________
a) multiprocessor systems
b) multiprogramming operating systems
c) larger memory sized systems
d) none of the mentioned
Answer: b
Explanation: None.
2. With multiprogramming ______ is used productively.
a) time
b) space
c) money
d) all of the mentioned
Answer: a
Explanation: None.
3. What are the two steps of a process execution?
a) I/O & OS Burst
b) CPU & I/O Burst
c) Memory & I/O Burst
d) OS & Memory Burst
Answer: b
Explanation: None.
4. An I/O bound program will typically have ____________
a) a few very short CPU bursts
b) many very short I/O bursts
c) many very short CPU bursts
d) a few very short I/O bursts
Answer: c
Explanation: None.
5. A process is selected from the ______ queue by the ________ scheduler, to be executed.
a) blocked, short term
b) wait, long term
c) ready, short term
d) ready, long term
Answer: c
Explanation: None.
6. In the following cases non – preemptive scheduling occurs?
a) When a process switches from the running state to the ready state
b) When a process goes from the running state to the waiting state
c) When a process switches from the waiting state to the ready state
d) All of the mentioned
Answer: b
Explanation: There is no other choice.
7. The switching of the CPU from one process or thread to another is called ____________
a) process switch
b) task switch
c) context switch
d) all of the mentioned
Answer: d
Explanation: None.
8. What is Dispatch latency?
a) the speed of dispatching a process from running to the ready state
b) the time of dispatching a process from running to ready state and keeping the CPU idle
c) the time to stop one process and start running another one
d) none of the mentioned
Answer: c
Explanation: None.
9. Scheduling is done so as to ____________
a) increase CPU utilization
b) decrease CPU utilization
c) keep the CPU more idle
d) none of the mentioned
Answer: a
Explanation: None.
10. Scheduling is done so as to ____________
a) increase the throughput
b) decrease the throughput
c) increase the duration of a specific amount of work
d) none of the mentioned
Answer: a
Explanation: None.
11. What is Turnaround time?
a) the total waiting time for a process to finish execution
b) the total time spent in the ready queue
c) the total time spent in the running queue
d) the total time from the completion till the submission of a process
Answer: d
Explanation: None.
12. Scheduling is done so as to ____________
a) increase the turnaround time
b) decrease the turnaround time
c) keep the turnaround time same
d) there is no relation between scheduling and turnaround time
Answer: b
Explanation: None.
13. What is Waiting time?
a) the total time in the blocked and waiting queues
b) the total time spent in the ready queue
c) the total time spent in the running queue
d) the total time from the completion till the submission of a process
Answer: b
Explanation: None.
14. Scheduling is done so as to ____________
a) increase the waiting time
b) keep the waiting time the same
c) decrease the waiting time
d) none of the mentioned
Answer: c
Explanation: None.
15. What is Response time?
a) the total time taken from the submission time till the completion time
b) the total time taken from the submission time till the first response is produced
c) the total time taken from submission time till the response is output
d) none of the mentioned
Answer: b
Explanation: None.
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1. Round robin scheduling falls under the category of ____________
a) Non-preemptive scheduling
b) Preemptive scheduling
c) All of the mentioned
d) None of the mentioned
Answer: b
Explanation: None.
2. With round robin scheduling algorithm in a time shared system ____________
a) using very large time slices converts it into First come First served scheduling algorithm
b) using very small time slices converts it into First come First served scheduling algorithm
c) using extremely small time slices increases performance
d) using very small time slices converts it into Shortest Job First algorithm
Answer: a
Explanation: All the processes will be able to get completed.
3. The portion of the process scheduler in an operating system that dispatches processes is concerned with ________
____
a) assigning ready processes to CPU
b) assigning ready processes to waiting queue
c) assigning running processes to blocked queue
d) all of the mentioned
Answer: a
Explanation: None.
4. Complex scheduling algorithms ____________
a) are very appropriate for very large computers
b) use minimal resources
c) use many resources
d) all of the mentioned
Answer: a
Explanation: Large computers are overloaded with a greater number of processes.
5. What is FIFO algorithm?
a) first executes the job that came in last in the queue
b) first executes the job that came in first in the queue
c) first executes the job that needs minimal processor
d) first executes the job that has maximum processor needs
Answer: b
Explanation: None.
6. The strategy of making processes that are logically runnable to be temporarily suspended is called ____________
a) Non preemptive scheduling
b) Preemptive scheduling
c) Shortest job first
d) First come First served
Answer: b
Explanation: None.
7. What is Scheduling?
a) allowing a job to use the processor
b) making proper use of processor
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: None.
8. There are 10 different processes running on a workstation. Idle processes are waiting for an input event in the inp
ut queue. Busy processes are scheduled with the Round-Robin time sharing method. Which out of the following qua
ntum times is the best value for small response times, if the processes have a short runtime, e.g. less than 10ms?
a) tQ = 15ms
b) tQ = 40ms
c) tQ = 45ms
d) tQ = 50ms
Answer: a
Explanation: None.
9. Orders are processed in the sequence they arrive if _______ rule sequences the jobs.
a) earliest due date
b) slack time remaining
c) first come, first served
d) critical ratio
Answer: c
Explanation: None.
10. Which of the following algorithms tends to minimize the process flow time?
a) First come First served
b) Shortest Job First
c) Earliest Deadline First
d) Longest Job First
Answer: b
Explanation: None.
11. Under multiprogramming, turnaround time for short jobs is usually ________ and that for long jobs is slightly _
__________
a) Lengthened; Shortened
b) Shortened; Lengthened
c) Shortened; Shortened
d) Shortened; Unchanged
Answer: b
Explanation: None.
12. Which of the following statements are true? (GATE 2010)
a) I only
b) I and III only
c) II and III only
d) I, II and III
Answer: d
Explanation: I) Shortest remaining time first scheduling is a preemptive version of shortest job scheduling. It may ca
use starvation as shorter processes may keep coming and a long CPU burst process never gets CPU.
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1. Which is the most optimal scheduling algorithm?
a) FCFS – First come First served
b) SJF – Shortest Job First
c) RR – Round Robin
d) None of the mentioned
Answer: b
Explanation: None.
2. The real difficulty with SJF in short term scheduling is ____________
a) it is too good an algorithm
b) knowing the length of the next CPU request
c) it is too complex to understand
d) none of the mentioned
Answer: b
Explanation: None.
3. The FCFS algorithm is particularly troublesome for ____________
a) time sharing systems
b) multiprogramming systems
c) multiprocessor systems
d) operating systems
Answer: b
Explanation: In a time sharing system, each user needs to get a share of the CPU at regular intervals.
4. Consider the following set of processes, the length of the CPU burst time given in milliseconds.
a) The waiting time for process P1 is 3ms
b) The waiting time for process P1 is 0ms
c) The waiting time for process P1 is 16ms
d) The waiting time for process P1 is 9ms
Answer: a
Explanation: None.
5. Preemptive Shortest Job First scheduling is sometimes called ____________
a) Fast SJF scheduling
b) EDF scheduling – Earliest Deadline First
c) HRRN scheduling – Highest Response Ratio Next
d) SRTN scheduling – Shortest Remaining Time Next
Answer: d
Explanation: None.
6. An SJF algorithm is simply a priority algorithm where the priority is ____________
a) the predicted next CPU burst
b) the inverse of the predicted next CPU burst
c) the current CPU burst
d) anything the user wants
Answer: a
Explanation: The larger the CPU burst, the lower the priority.
7. Choose one of the disadvantages of the priority scheduling algorithm?
a) it schedules in a very complex manner
b) its scheduling takes up a lot of time
c) it can lead to some low priority process waiting indefinitely for the CPU
d) none of the mentioned
Answer: c
Explanation: None.
8. What is ‘Aging’?
a) keeping track of cache contents
b) keeping track of what pages are currently residing in memory
c) keeping track of how many times a given page is referenced
d) increasing the priority of jobs to ensure termination in a finite time
Answer: d
Explanation: None.
9. A solution to the problem of indefinite blockage of low – priority processes is ____________
a) Starvation
b) Wait queue
c) Ready queue
d) Aging i) Shortest remaining time first scheduling may cause starvation
Answer: d
Explanation: None.
10. Which of the following statements are true? (GATE 2010)
a) i only
b) i and iii only
c) ii and iii only
d) i, ii and iii
Answer: d
Explanation: None.
11. Which of the following scheduling algorithms gives minimum average waiting time?
a) FCFS
b) SJF
c) Round – robin
d) Priority
Answer: b
Explanation: None.
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1. Concurrent access to shared data may result in ____________
a) data consistency
b) data insecurity
c) data inconsistency
d) none of the mentioned
Answer: c
Explanation: None.
2. A situation where several processes access and manipulate the same data concurrently and the outcome of the exe
cution depends on the particular order in which access takes place is called ____________
a) data consistency
b) race condition
c) aging
d) starvation
Answer: b
Explanation: None.
3. The segment of code in which the process may change common variables, update tables, write into files is known
as ____________
a) program
b) critical section
c) non – critical section
d) synchronizing
Answer: b
Explanation: None.
4. Which of the following conditions must be satisfied to solve the critical section problem?
a) Mutual Exclusion
b) Progress
c) Bounded Waiting
d) All of the mentioned
Answer: d
Explanation: None.
5. Mutual exclusion implies that ____________
a) if a process is executing in its critical section, then no other process must be executing in their critical sections
b) if a process is executing in its critical section, then other processes must be executing in their critical sections
c) if a process is executing in its critical section, then all the resources of the system must be blocked until it finishes
execution
d) none of the mentioned
Answer: a
Explanation: None.
6. Bounded waiting implies that there exists a bound on the number of times a process is allowed to enter its critical
section ____________
a) after a process has made a request to enter its critical section and before the request is granted
b) when another process is in its critical section
c) before a process has made a request to enter its critical section
d) none of the mentioned
Answer: a
Explanation: None.
7. A minimum of _____ variable(s) is/are required to be shared between processes to solve the critical section proble
m.
a) one
b) two
c) three
d) four
Answer: b
Explanation: None.
8. In the bakery algorithm to solve the critical section problem ____________
a) each process is put into a queue and picked up in an ordered manner
b) each process receives a number (may or may not be unique) and the one with the lowest number is served next
c) each process gets a unique number and the one with the highest number is served next
d) each process gets a unique number and the one with the lowest number is served next
Answer: b
Explanation: None.
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1. An un-interruptible unit is known as ____________
a) single
b) atomic
c) static
d) none of the mentioned
Answer: b
Explanation: None.
2. TestAndSet instruction is executed ____________
a) after a particular process
b) periodically
c) atomically
d) none of the mentioned
Answer: c
Explanation: None.
3. Semaphore is a/an _______ to solve the critical section problem.
a) hardware for a system
b) special program for a system
c) integer variable
d) none of the mentioned
Answer: c
Explanation: None.
4. What are the two atomic operations permissible on semaphores?
a) wait
b) stop
c) hold
d) none of the mentioned
Answer: a
Explanation: None.
5. What are Spinlocks?
a) CPU cycles wasting locks over critical sections of programs
b) Locks that avoid time wastage in context switches
c) Locks that work better on multiprocessor systems
d) All of the mentioned
Answer: d
Explanation: None.
6. What is the main disadvantage of spinlocks?
a) they are not sufficient for many process
b) they require busy waiting
c) they are unreliable sometimes
d) they are too complex for programmers
Answer: b
Explanation: None.
7. The wait operation of the semaphore basically works on the basic _______ system call.
a) stop()
b) block()
c) hold()
d) wait()
Answer: b
Explanation: None.
8. The signal operation of the semaphore basically works on the basic _______ system call.
a) continue()
b) wakeup()
c) getup()
d) start()
Answer: b
Explanation: None.
9. If the semaphore value is negative ____________
a) its magnitude is the number of processes waiting on that semaphore
b) it is invalid
c) no operation can be further performed on it until the signal operation is performed on it
d) none of the mentioned
Answer: a
Explanation: None.
10. The code that changes the value of the semaphore is ____________
a) remainder section code
b) non – critical section code
c) critical section code
d) none of the mentioned
Answer: c
Explanation: None.
11. The following program consists of 3 concurrent processes and 3 binary semaphores. The semaphores are initializ
ed as S0 = 1, S1 = 0, S2 = 0.
a) At least twice
b) Exactly twice
c) Exactly thrice
d) Exactly once
Answer: a
Explanation: None.
12. Each process Pi, i = 0,1,2,3,……,9 is coded as follows.
a) 1
b) 2
c) 3
d) None of the mentioned
Answer: c
Explanation: Any one of the 9 processes can get into critical section after executing P(mutex) which decrements the
mutex value to 0. At this time P10 can enter critical section by incrementing the value to 1. Now any of the 9 proces
ses can enter the critical section by again decrementing the mutex value to 0. None of the remaining processes can g
et into their critical sections.
13. Two processes, P1 and P2, need to access a critical section of code. Consider the following synchronization cons
truct used by the processes.
a) It does not ensure mutual exclusion
b) It does not ensure bounded waiting
c) It requires that processes enter the critical section in strict alternation
d) It does not prevent deadlocks but ensures mutual exclusion
Answer: d
Explanation: None.
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1. What will happen if a non-recursive mutex is locked more than once?
a) Starvation
b) Deadlock
c) Aging
d) Signaling
Answer: b
Explanation: If a thread which had already locked a mutex, tries to lock the mutex again, it will enter into the waitin
g list of that mutex, which results in a deadlock. It is because no other thread can unlock the mutex.
2. What is a semaphore?
a) is a binary mutex
b) must be accessed from only one process
c) can be accessed from multiple processes
d) none of the mentioned
Answer: c
Explanation: None.
3. What are the two kinds of semaphores?
a) mutex & counting
b) binary & counting
c) counting & decimal
d) decimal & binary
Answer: b
Explanation: None.
4. What is a mutex?
a) is a binary mutex
b) must be accessed from only one process
c) can be accessed from multiple processes
d) none of the mentioned
Answer: b
Explanation: None.
5. At a particular time of computation the value of a counting semaphore is 7.Then 20 P operations and 15 V operati
ons were completed on this semaphore. The resulting value of the semaphore is? (GATE 1987)
a) 42
b) 2
c) 7
d) 12
Answer: b
Explanation: P represents Wait and V represents Signal. P operation will decrease the value by 1 every time and V
operation will increase the value by 1 every time.
6. A binary semaphore is a semaphore with integer values ____________
a) 1
b) -1
c) 0.8
d) 0.5
Answer: a
Explanation: None.
7. The following pair of processes share a common variable X.
a) two
b) three
c) four
d) eight
Answer: c
Explanation: Here are the possible ways in which statements from A and B can be interleaved.
8. The program follows to use a shared binary semaphore T.
a) one
b) two
c) three
d) four
Answer: a
Explanation: The semaphore T ensures that all the statements from A finish execution before B begins. So now there
is only one way in which statements from A and B can be interleaved:
9. Semaphores are mostly used to implement ____________
a) System calls
b) IPC mechanisms
c) System protection
d) None of the mentioned
Answer: b
Explanation: None.
10. Spinlocks are intended to provide __________ only.
a) Mutual Exclusion
b) Bounded Waiting
c) Aging
d) Progress
Answer: b
Explanation: None.
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1. The bounded buffer problem is also known as ____________
a) Readers – Writers problem
b) Dining – Philosophers problem
c) Producer – Consumer problem
d) None of the mentioned
Answer: c
Explanation: None.
2. In the bounded buffer problem, there are the empty and full semaphores that ____________
a) count the number of empty and full buffers
b) count the number of empty and full memory spaces
c) count the number of empty and full queues
d) none of the mentioned
Answer: a
Explanation: None.
3. In the bounded buffer problem ____________
a) there is only one buffer
b) there are n buffers ( n being greater than one but finite)
c) there are infinite buffers
d) the buffer size is bounded
Answer: b
Explanation: None.
4. To ensure difficulties do not arise in the readers – writers problem _______ are given exclusive access to the shar
ed object.
a) readers
b) writers
c) readers and writers
d) none of the mentioned
Answer: b
Explanation: None.
5. The dining – philosophers problem will occur in case of ____________
a) 5 philosophers and 5 chopsticks
b) 4 philosophers and 5 chopsticks
c) 3 philosophers and 5 chopsticks
d) 6 philosophers and 5 chopsticks
Answer: a
Explanation: None.
6. A deadlock free solution to the dining philosophers problem ____________
a) necessarily eliminates the possibility of starvation
b) does not necessarily eliminate the possibility of starvation
c) eliminates any possibility of any kind of problem further
d) none of the mentioned
Answer: b
Explanation: None.
7. All processes share a semaphore variable mutex, initialized to 1. Each process must execute wait(mutex) before e
ntering the critical section and signal(mutex) afterward.
a) a deadlock will occur
b) processes will starve to enter critical section
c) several processes maybe executing in their critical section
d) all of the mentioned
Answer: c
Explanation: None.
8. All processes share a semaphore variable mutex, initialized to 1. Each process must execute wait(mutex) before e
ntering the critical section and signal(mutex) afterward.
a) a deadlock will occur
b) processes will starve to enter critical section
c) several processes maybe executing in their critical section
d) all of the mentioned
Answer: a
Explanation: None.
9. Consider the methods used by processes P1 and P2 for accessing their critical sections whenever needed, as given
below. The initial values of shared boolean variables S1 and S2 are randomly assigned. (GATE 2010)
a) Mutual exclusion but not progress
b) Progress but not mutual exclusion
c) Neither mutual exclusion nor progress
d) Both mutual exclusion and progress
Answer: d
Explanation: None.
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1. A monitor is a type of ____________
a) semaphore
b) low level synchronization construct
c) high level synchronization construct
d) none of the mentioned
Answer: c
Explanation: None.
2. A monitor is characterized by ____________
a) a set of programmer defined operators
b) an identifier
c) the number of variables in it
d) all of the mentioned
Answer: a
Explanation: None.
3. A procedure defined within a ________ can access only those variables declared locally within the _______ and i
ts formal parameters.
a) process, semaphore
b) process, monitor
c) semaphore, semaphore
d) monitor, monitor
Answer: d
Explanation: None.
4. The monitor construct ensures that ____________
a) only one process can be active at a time within the monitor
b) n number of processes can be active at a time within the monitor (n being greater than 1)
c) the queue has only one process in it at a time
d) all of the mentioned
Answer: a
Explanation: None.
5. What are the operations that can be invoked on a condition variable?
a) wait & signal
b) hold & wait
c) signal & hold
d) continue & signal
Answer: a
Explanation: None.
6. Which is the process of invoking the wait operation?
a) suspended until another process invokes the signal operation
b) waiting for another process to complete before it can itself call the signal operation
c) stopped until the next process in the queue finishes execution
d) none of the mentioned
Answer: a
Explanation: None.
7. If no process is suspended, the signal operation ____________
a) puts the system into a deadlock state
b) suspends some default process execution
c) nothing happens
d) the output is unpredictable
Answer: c
Explanation: None.
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1. A collection of instructions that performs a single logical function is called ____________
a) transaction
b) operation
c) function
d) all of the mentioned
Answer: a
Explanation: None.
2. A terminated transaction that has completed its execution successfully is ____________ otherwise it is ________
__
a) committed, destroyed
b) aborted, destroyed
c) committed, aborted
d) none of the mentioned
Answer: c
Explanation: None.
3. The state of the data accessed by an aborted transaction must be restored to what it was just before the transaction
started executing. This restoration is known as ________ of transaction.
a) safety
b) protection
c) roll – back
d) revert – back
Answer: c
Explanation: None.
4. Write ahead logging is a way ____________
a) to ensure atomicity
b) to keep data consistent
c) that records data on stable storage
d) all of the mentioned
Answer: d
Explanation: None.
5. In the write ahead logging a _____________ is maintained.
a) a memory
b) a system
c) a disk
d) a log record
Answer: d
Explanation: None.
6. An actual update is not allowed to a data item ____________
a) before the corresponding log record is written out to stable storage
b) after the corresponding log record is written out to stable storage
c) until the whole log record has been checked for inconsistencies
d) all of the mentioned
Answer: a
Explanation: None.
7. The undo and redo operations must be _________ to guarantee correct behaviour, even if a failure occurs during r
ecovery process.
a) idempotent
b) easy
c) protected
d) all of the mentioned
Answer: a
Explanation: Idempotent – Multiple executions of an operation have the same result as does one execution.
8. The system periodically performs checkpoints that consists of the following operation(s) ____________
a) Putting all the log records currently in main memory onto stable storage
b) putting all modified data residing in main memory onto stable storage
c) putting a log record onto stable storage
d) all of the mentioned
Answer: d
Explanation: None.
9. Consider a transaction T1 that committed prior to checkpoint. The <T1 commits> record appears in the log before
the <checkpoint> record. Any modifications made by T1 must have been written to the stable storage either with th
e checkpoint or prior to it. Thus at recovery time ____________
a) There is a need to perform an undo operation on T1
b) There is a need to perform a redo operation on T1
c) There is no need to perform an undo and redo operation on T1
d) All of the mentioned
Answer: c
Explanation: None.
10. Serializable schedules are ones where ____________
a) concurrent execution of transactions is equivalent to the transactions executed serially
b) the transactions can be carried out one after the other
c) a valid result occurs after execution transactions
d) none of the mentioned
Answer: a
Explanation: None.
11. A locking protocol is one that ____________
a) governs how locks are acquired
b) governs how locks are released
c) governs how locks are acquired and released
d) none of the mentioned
Answer: c
Explanation: None.
12. The two phase locking protocol consists of ____________
a) growing & shrinking phase
b) shrinking & creation phase
c) creation & growing phase
d) destruction & creation phase
Answer: a
Explanation: None.
13. The growing phase is a phase in which?
a) A transaction may obtain locks, but does not release any
b) A transaction may obtain locks, and releases a few or all of them
c) A transaction may release locks, but does not obtain any new locks
d) A transaction may release locks, and does obtain new locks
Answer: a
Explanation: None.
14. The shrinking phase is a phase in which?
a) A transaction may obtain locks, but does not release any
b) A transaction may obtain locks, and releases a few or all of them
c) A transaction may release locks, but does not obtain any new locks
d) A transaction may release locks, and does obtain new locks
Answer: c
Explanation: None.
15. Which of the following concurrency control protocols ensure both conflict serializability and freedom from dead
lock?
a) I only
b) II only
c) Both I and II
d) Neither I nor II
Answer: b
Explanation: None.
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1. The number of resources requested by a process ____________
a) must always be less than the total number of resources available in the system
b) must always be equal to the total number of resources available in the system
c) must not exceed the total number of resources available in the system
d) must exceed the total number of resources available in the system
Answer: c
Explanation: None.
2. The request and release of resources are ___________
a) command line statements
b) interrupts
c) system calls
d) special programs
Answer: c
Explanation: None.
3. What are Multithreaded programs?
a) lesser prone to deadlocks
b) more prone to deadlocks
c) not at all prone to deadlocks
d) none of the mentioned
Answer: b
Explanation: Multiple threads can compete for shared resources.
4. For a deadlock to arise, which of the following conditions must hold simultaneously?
a) Mutual exclusion
b) No preemption
c) Hold and wait
d) All of the mentioned
Answer: d
Explanation: None.
5. For Mutual exclusion to prevail in the system ____________
a) at least one resource must be held in a non sharable mode
b) the processor must be a uniprocessor rather than a multiprocessor
c) there must be at least one resource in a sharable mode
d) all of the mentioned
Answer: a
Explanation: If another process requests that resource (non – shareable resource), the requesting process must be del
ayed until the resource has been released.
6. For a Hold and wait condition to prevail ____________
a) A process must be not be holding a resource, but waiting for one to be freed, and then request to acquire it
b) A process must be holding at least one resource and waiting to acquire additional resources that are being held by
other processes
c) A process must hold at least one resource and not be waiting to acquire additional resources
d) None of the mentioned
Answer: b
Explanation: None.
7. Deadlock prevention is a set of methods ____________
a) to ensure that at least one of the necessary conditions cannot hold
b) to ensure that all of the necessary conditions do not hold
c) to decide if the requested resources for a process have to be given or not
d) to recover from a deadlock
Answer: a
Explanation: None.
8. For non sharable resources like a printer, mutual exclusion ____________
a) must exist
b) must not exist
c) may exist
d) none of the mentioned
Answer: a
Explanation: A printer cannot be simultaneously shared by several processes.
9. For sharable resources, mutual exclusion ____________
a) is required
b) is not required
c) may be or may not be required
d) none of the mentioned
Answer: b
Explanation: They do not require mutually exclusive access, and hence cannot be involved in a deadlock.
10. To ensure that the hold and wait condition never occurs in the system, it must be ensured that ____________
a) whenever a resource is requested by a process, it is not holding any other resources
b) each process must request and be allocated all its resources before it begins its execution
c) a process can request resources only when it has none
d) all of the mentioned
Answer: d
Explanation: c – A process may request some resources and use them. Before it can can request any additional resou
rces, however it must release all the resources that it is currently allocated.
11. The disadvantage of a process being allocated all its resources before beginning its execution is ____________
a) Low CPU utilization
b) Low resource utilization
c) Very high resource utilization
d) None of the mentioned
Answer: b
Explanation: None.
12. To ensure no preemption, if a process is holding some resources and requests another resource that cannot be im
mediately allocated to it ____________
a) then the process waits for the resources be allocated to it
b) the process keeps sending requests until the resource is allocated to it
c) the process resumes execution without the resource being allocated to it
d) then all resources currently being held are preempted
Answer: d
Explanation: None.
13. One way to ensure that the circular wait condition never holds is to ____________
a) impose a total ordering of all resource types and to determine whether one precedes another in the ordering
b) to never let a process acquire resources that are held by other processes
c) to let a process wait for only one resource at a time
d) all of the mentioned
Answer: a
Explanation: None.
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1. Each request requires that the system consider the _____________ to decide whether the current request can be sa
tisfied or must wait to avoid a future possible deadlock.
a) resources currently available
b) processes that have previously been in the system
c) resources currently allocated to each process
d) future requests and releases of each process
Answer: a
Explanation: None.
2. Given a priori information about the ________ number of resources of each type that maybe requested for each pr
ocess, it is possible to construct an algorithm that ensures that the system will never enter a deadlock state.
a) minimum
b) average
c) maximum
d) approximate
Answer: c
Explanation: None.
3. A deadlock avoidance algorithm dynamically examines the __________ to ensure that a circular wait condition ca
n never exist.
a) resource allocation state
b) system storage state
c) operating system
d) resources
Answer: a
Explanation: Resource allocation states are used to maintain the availability of the already and current available reso
urces.
4. A state is safe, if ____________
a) the system does not crash due to deadlock occurrence
b) the system can allocate resources to each process in some order and still avoid a deadlock
c) the state keeps the system protected and safe
d) all of the mentioned
Answer: b
Explanation: None.
5. A system is in a safe state only if there exists a ____________
a) safe allocation
b) safe resource
c) safe sequence
d) all of the mentioned
Answer: c
Explanation: None.
6. All unsafe states are ____________
a) deadlocks
b) not deadlocks
c) fatal
d) none of the mentioned
Answer: b
Explanation: None.
7. A system has 12 magnetic tape drives and 3 processes : P0, P1, and P2. Process P0 requires 10 tape drives, P1 req
uires 4 and P2 requires 9 tape drives.
a) P0, P1, P2
b) P1, P2, P0
c) P2, P0, P1
d) P1, P0, P2
Answer: d
Explanation: None.
10
a) then the system will not be in a safe state
b) then the system will be in a safe state
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: None.
a) with multiple instances of each resource type
b) with a single instance of each resource type
c) single & multiple instances of each resource type
d) none of the mentioned
Answer: a
Explanation: None.
8. If no cycle exists in the resource allocation graph ____________
a) less efficient
b) more efficient
c) equal
d) none of the mentioned
Answer: a
Explanation: None.
9. The resource allocation graph is not applicable to a resource allocation system ____________
a) Available
b) Need
c) Allocation
d) All of the mentioned
Answer: d
Explanation: None.
10. The Banker’s algorithm is _____________ than the resource allocation graph algorithm.
a) Allocation – Available
b) Max – Available
c) Max – Allocation
d) Allocation – Max
Answer: c
Explanation: None.
11. The data structures available in the Banker’s algorithm are ____________
a) an unsafe state
b) a safe state
c) a protected state
d) a deadlock
Answer: b
Explanation: None.
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1. The wait-for graph is a deadlock detection algorithm that is applicable when ____________
a) all resources have a single instance
b) all resources have multiple instances
c) all resources have a single 7 multiple instances
d) all of the mentioned
Answer: a
Explanation: None.
2. An edge from process Pi to Pj in a wait for graph indicates that ____________
a) Pi is waiting for Pj to release a resource that Pi needs
b) Pj is waiting for Pi to release a resource that Pj needs
c) Pi is waiting for Pj to leave the system
d) Pj is waiting for Pi to leave the system
Answer: a
Explanation: None.
3. If the wait for graph contains a cycle ____________
a) then a deadlock does not exist
b) then a deadlock exists
c) then the system is in a safe state
d) either deadlock exists or system is in a safe state
Answer: b
Explanation: None.
4. If deadlocks occur frequently, the detection algorithm must be invoked ________
a) rarely
b) frequently
c) rarely & frequently
d) none of the mentioned
Answer: b
Explanation: None.
5. What is the disadvantage of invoking the detection algorithm for every request?
a) overhead of the detection algorithm due to consumption of memory
b) excessive time consumed in the request to be allocated memory
c) considerable overhead in computation time
d) all of the mentioned
Answer: c
Explanation: None.
6. A deadlock eventually cripples system throughput and will cause the CPU utilization to ______
a) increase
b) drop
c) stay still
d) none of the mentioned
Answer: b
Explanation: None.
7. Every time a request for allocation cannot be granted immediately, the detection algorithm is invoked. This will h
elp identify ____________
a) the set of processes that have been deadlocked
b) the set of processes in the deadlock queue
c) the specific process that caused the deadlock
d) all of the mentioned
Answer: a
Explanation: None.
8. A computer system has 6 tape drives, with ‘n’ processes competing for them. Each process may need 3 tape drive
s. The maximum value of ‘n’ for which the system is guaranteed to be deadlock free is?
a) 2
b) 3
c) 4
d) 1
Answer: a
Explanation: None.
9. A system has 3 processes sharing 4 resources. If each process needs a maximum of 2 units then, deadlock ______
______
a) can never occur
b) may occur
c) has to occur
d) none of the mentioned
Answer: a
Explanation: None.
10. ‘m’ processes share ‘n’ resources of the same type. The maximum need of each process doesn’t exceed ‘n’ and t
he sum of all their maximum needs is always less than m+n. In this setup, deadlock ____________
a) can never occur
b) may occur
c) has to occur
d) none of the mentioned
Answer: a
Explanation: None.
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1. A deadlock can be broken by ____________
a) abort one or more processes to break the circular wait
b) abort all the process in the system
c) preempt all resources from all processes
d) none of the mentioned
Answer: a
Explanation: None.
2. The two ways of aborting processes and eliminating deadlocks are ____________
a) Abort all deadlocked processes
b) Abort all processes
c) Abort one process at a time until the deadlock cycle is eliminated
d) All of the mentioned
Answer: c
Explanation: None.
3. Those processes should be aborted on occurrence of a deadlock, the termination of which?
a) is more time consuming
b) incurs minimum cost
c) safety is not hampered
d) all of the mentioned
Answer: b
Explanation: None.
4. The process to be aborted is chosen on the basis of the following factors?
a) priority of the process
b) process is interactive or batch
c) how long the process has computed
d) all of the mentioned
Answer: d
Explanation: None.
5. Cost factors for process termination include ____________
a) Number of resources the deadlock process is not holding
b) CPU utilization at the time of deadlock
c) Amount of time a deadlocked process has thus far consumed during its execution
d) All of the mentioned
Answer: c
Explanation: None.
6. If we preempt a resource from a process, the process cannot continue with its normal execution and it must be ___
_________
a) aborted
b) rolled back
c) terminated
d) queued
Answer: b
Explanation: None.
7. To _______ to a safe state, the system needs to keep more information about the states of processes.
a) abort the process
b) roll back the process
c) queue the process
d) none of the mentioned
Answer: b
Explanation: None.
8. If the resources are always preempted from the same process __________ can occur.
a) deadlock
b) system crash
c) aging
d) starvation
Answer: d
Explanation: None.
9. What is the solution to starvation?
a) the number of rollbacks must be included in the cost factor
b) the number of resources must be included in resource preemption
c) resource preemption be done instead
d) all of the mentioned
Answer: a
Explanation: None.
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1. What is Address Binding?
a) going to an address in memory
b) locating an address with the help of another address
c) binding two addresses together to form a new address in a different memory space
d) a mapping from one address space to another
Answer: d
Explanation: None.
2. Binding of instructions and data to memory addresses can be done at ____________
a) Compile time
b) Load time
c) Execution time
d) All of the mentioned
Answer: d
Explanation: None.
3. If the process can be moved during its execution from one memory segment to another, then binding must be ___
_________
a) delayed until run time
b) preponed to compile time
c) preponed to load time
d) none of the mentioned
Answer: a
Explanation: None.
4. What is Dynamic loading?
a) loading multiple routines dynamically
b) loading a routine only when it is called
c) loading multiple routines randomly
d) none of the mentioned
Answer: b
Explanation: None.
5. What is the advantage of dynamic loading?
a) A used routine is used multiple times
b) An unused routine is never loaded
c) CPU utilization increases
d) All of the mentioned
Answer: b
Explanation: None.
6. The idea of overlays is to ____________
a) data that are needed at any given time
b) enable a process to be larger than the amount of memory allocated to it
c) keep in memory only those instructions
d) all of the mentioned
Answer: d
Explanation: None.
7. The ___________ must design and program the overlay structure.
a) programmer
b) system architect
c) system designer
d) none of the mentioned
Answer: a
Explanation: None.
8. The ___________ swaps processes in and out of the memory.
a) Memory manager
b) CPU
c) CPU manager
d) User
Answer: a
Explanation: None.
9. If a higher priority process arrives and wants service, the memory manager can swap out the lower priority proces
s to execute the higher priority process. When the higher priority process finishes, the lower priority process is swap
ped back in and continues execution. This variant of swapping is sometimes called?
a) priority swapping
b) pull out, push in
c) roll out, roll in
d) none of the mentioned
Answer: c
Explanation: None.
10. If binding is done at assembly or load time, then the process _____ be moved to different locations after being s
wapped out and in again.
a) can
b) must
c) can never
d) may
Answer: c
Explanation: None.
11. In a system that does not support swapping ____________
a) the compiler normally binds symbolic addresses (variables) to relocatable addresses
b) the compiler normally binds symbolic addresses to physical addresses
c) the loader binds relocatable addresses to physical addresses
d) binding of symbolic addresses to physical addresses normally takes place during execution
Answer: a
Explanation: None.
12. Which of the following is TRUE?
a) Overlays are used to increase the size of physical memory
b) Overlays are used to increase the logical address space
c) When overlays are used, the size of a process is not limited to the size of the physical memory
d) Overlays are used whenever the physical address space is smaller than the logical address space
Answer: c
Explanation: None.
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1. The address generated by the CPU is referred to as ____________
a) Physical address
b) Logical address
c) Neither physical nor logical
d) None of the mentioned
Answer: b
Explanation: None.
2. The address loaded into the memory address register of the memory is referred to as ____________
a) Physical address
b) Logical address
c) Neither physical nor logical
d) None of the mentioned
Answer: a
Explanation: None.
3. The run time mapping from virtual to physical addresses is done by a hardware device called the ____________
a) Virtual to physical mapper
b) Memory management unit
c) Memory mapping unit
d) None of the mentioned
Answer: b
Explanation: None.
4. The base register is also known as the ____________
a) basic register
b) regular register
c) relocation register
d) delocation register
Answer: c
Explanation: None.
5. The size of a process is limited to the size of ____________
a) physical memory
b) external storage
c) secondary storage
d) none of the mentioned
Answer: a
Explanation: None.
6. If execution time binding is being used, then a process ______ be swapped to a different memory space.
a) has to be
b) can never
c) must
d) may
Answer: d
Explanation: None.
7. Swapping requires a _________
a) motherboard
b) keyboard
c) monitor
d) backing store
Answer: d
Explanation: None.
8. The backing store is generally a ____________
a) fast disk
b) disk large enough to accommodate copies of all memory images for all users
c) disk to provide direct access to the memory images
d) all of the mentioned
Answer: d
Explanation: None.
9. The ________ consists of all processes whose memory images are in the backing store or in memory and are read
y to run.
a) wait queue
b) ready queue
c) cpu
d) secondary storage
Answer: b
Explanation: None.
10. The _________ time in a swap out of a running process and swap in of a new process into the memory is very hi
gh.
a) context – switch
b) waiting
c) execution
d) all of the mentioned
Answer: a
Explanation: None.
11. The major part of swap time is _______ time.
a) waiting
b) transfer
c) execution
d) none of the mentioned
Answer: b
Explanation: None.
12. Swapping _______ be done when a process has pending I/O, or has to execute I/O operations only into operating
system buffers.
a) must
b) can
c) must never
d) maybe
Answer: c
Explanation: None.
13. Swap space is allocated ____________
a) as a chunk of disk
b) separate from a file system
c) into a file system
d) all of the mentioned
Answer: a
Explanation: None.
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1. The main memory accommodates ____________
a) operating system
b) cpu
c) user processes
d) all of the mentioned
Answer: a
Explanation: None.
2. What is the operating system?
a) in the low memory
b) in the high memory
c) either low or high memory (depending on the location of interrupt vector)
d) none of the mentioned
Answer: c
Explanation: None.
3. In contiguous memory allocation ____________
a) each process is contained in a single contiguous section of memory
b) all processes are contained in a single contiguous section of memory
c) the memory space is contiguous
d) none of the mentioned
Answer: a
Explanation: None.
4. The relocation register helps in ____________
a) providing more address space to processes
b) a different address space to processes
c) to protect the address spaces of processes
d) none of the mentioned
Answer: c
Explanation: None.
5. With relocation and limit registers, each logical address must be _______ the limit register.
a) less than
b) equal to
c) greater than
d) none of the mentioned
Answer: a
Explanation: None.
6. The operating system and the other processes are protected from being modified by an already running process be
cause ____________
a) they are in different memory spaces
b) they are in different logical addresses
c) they have a protection algorithm
d) every address generated by the CPU is being checked against the relocation and limit registers
Answer: d
Explanation: None.
7. Transient operating system code is code that ____________
a) is not easily accessible
b) comes and goes as needed
c) stays in the memory always
d) never enters the memory space
Answer: b
Explanation: None.
8. Using transient code, _______ the size of the operating system during program execution.
a) increases
b) decreases
c) changes
d) maintains
Answer: c
Explanation: None.
9. When memory is divided into several fixed sized partitions, each partition may contain ________
a) exactly one process
b) at least one process
c) multiple processes at once
d) none of the mentioned
Answer: a
Explanation: None.
10. In fixed size partition, the degree of multiprogramming is bounded by ___________
a) the number of partitions
b) the CPU utilization
c) the memory size
d) all of the mentioned
Answer: a
Explanation: None
11. The first fit, best fit and worst fit are strategies to select a ______
a) process from a queue to put in memory
b) processor to run the next process
c) free hole from a set of available holes
d) all of the mentioned
Answer: c
Explanation: None.
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1. In internal fragmentation, memory is internal to a partition and ____________
a) is being used
b) is not being used
c) is always used
d) none of the mentioned
Answer: b
Explanation: None.
2. A solution to the problem of external fragmentation is ____________
a) compaction
b) larger memory space
c) smaller memory space
d) none of the mentioned
Answer: a
Explanation: None.
3. Another solution to the problem of external fragmentation problem is to ____________
a) permit the logical address space of a process to be noncontiguous
b) permit smaller processes to be allocated memory at last
c) permit larger processes to be allocated memory at last
d) all of the mentioned
Answer: a
Explanation: None.
4. If relocation is static and is done at assembly or load time, compaction _________
a) cannot be done
b) must be done
c) must not be done
d) can be done
Answer: a
Explanation: None.
5. The disadvantage of moving all process to one end of memory and all holes to the other direction, producing one l
arge hole of available memory is ____________
a) the cost incurred
b) the memory used
c) the CPU used
d) all of the mentioned
Answer: a
Explanation: None.
6. __________ is generally faster than _________ and _________
a) first fit, best fit, worst fit
b) best fit, first fit, worst fit
c) worst fit, best fit, first fit
d) none of the mentioned
Answer: a
Explanation: None.
7. External fragmentation exists when?
a) enough total memory exists to satisfy a request but it is not contiguous
b) the total memory is insufficient to satisfy a request
c) a request cannot be satisfied even when the total memory is free
d) none of the mentioned
Answer: a
Explanation: None.
8. External fragmentation will not occur when?
a) first fit is used
b) best fit is used
c) worst fit is used
d) no matter which algorithm is used, it will always occur
Answer: d
Explanation: None.
9. Sometimes the overhead of keeping track of a hole might be ____________
a) larger than the memory
b) larger than the hole itself
c) very small
d) all of the mentioned
Answer: b
Explanation: None.
10. When the memory allocated to a process is slightly larger than the process, then ____________
a) internal fragmentation occurs
b) external fragmentation occurs
c) both internal and external fragmentation occurs
d) neither internal nor external fragmentation occurs
Answer: a
Explanation: None.
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1. Physical memory is broken into fixed-sized blocks called ________
a) frames
b) pages
c) backing store
d) none of the mentioned
Answer: a
Explanation: None.
2. Logical memory is broken into blocks of the same size called _________
a) frames
b) pages
c) backing store
d) none of the mentioned
Answer: b
Explanation: None.
3. Every address generated by the CPU is divided into two parts. They are ____________
a) frame bit & page number
b) page number & page offset
c) page offset & frame bit
d) frame offset & page offset
Answer: b
Explanation: None.
4. The __________ is used as an index into the page table.
a) frame bit
b) page number
c) page offset
d) frame offset
Answer: b
Explanation: None.
5. The _____ table contains the base address of each page in physical memory.
a) process
b) memory
c) page
d) frame
Answer: c
Explanation: None.
6. The size of a page is typically ____________
a) varied
b) power of 2
c) power of 4
d) none of the mentioned
Answer: b
Explanation: None.
7. If the size of logical address space is 2 to the power of m, and a page size is 2 to the power of n addressing units, t
hen the high order _____ bits of a logical address designate the page number, and the ____ low order bits designate t
he page offset.
a) m, n
b) n, m
c) m – n, m
d) m – n, n
Answer: d
Explanation: None.
8. With paging there is no ________ fragmentation.
a) internal
b) external
c) either type of
d) none of the mentioned
Answer: b
Explanation: None.
9. The operating system maintains a ______ table that keeps track of how many frames have been allocated, how ma
ny are there, and how many are available.
a) page
b) mapping
c) frame
d) memory
Answer: c
Explanation: None.
10. Paging increases the ______ time.
a) waiting
b) execution
c) context – switch
d) all of the mentioned
Answer: c
Explanation: None.
11. Smaller page tables are implemented as a set of _______
a) queues
b) stacks
c) counters
d) registers
Answer: d
Explanation: None.
12. The page table registers should be built with _______
a) very low speed logic
b) very high speed logic
c) a large memory space
d) none of the mentioned
Answer: b
Explanation: None.
13. For larger page tables, they are kept in main memory and a __________ points to the page table.
a) page table base register
b) page table base pointer
c) page table register pointer
d) page table base
Answer: a
Explanation: None.
14. For every process there is a __________
a) page table
b) copy of page table
c) pointer to page table
d) all of the mentioned
Answer: a
Explanation: None.
15. Time taken in memory access through PTBR is ____________
a) extended by a factor of 3
b) extended by a factor of 2
c) slowed by a factor of 3
d) slowed by a factor of 2
Answer: d
Explanation: None.
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1. Each entry in a translation lookaside buffer (TL
b) consists of ____________
a) key
b) value
c) bit value
d) constant
Answer: a
Explanation: None.
2. If a page number is not found in the TLB, then it is known as a ____________
a) TLB miss
b) Buffer miss
c) TLB hit
d) All of the mentioned
Answer: a
Explanation: None.
3. An ______ uniquely identifies processes and is used to provide address space protection for that process.
a) address space locator
b) address space identifier
c) address process identifier
d) none of the mentioned
Answer: b
Explanation: None.
4. The percentage of times a page number is found in the TLB is known as ____________
a) miss ratio
b) hit ratio
c) miss percent
d) none of the mentioned
Answer: b
Explanation: None.
5. Memory protection in a paged environment is accomplished by ____________
a) protection algorithm with each page
b) restricted access rights to users
c) restriction on page visibility
d) protection bit with each page
Answer: d
Explanation: None.
6. When the valid – invalid bit is set to valid, it means that the associated page ____________
a) is in the TLB
b) has data in it
c) is in the process’s logical address space
d) is the system’s physical address space
Answer: c
Explanation: None.
7. Illegal addresses are trapped using the _____ bit.
a) error
b) protection
c) valid – invalid
d) access
Answer: c
Explanation: None.
8. When there is a large logical address space, the best way of paging would be ____________
a) not to page
b) a two level paging algorithm
c) the page table itself
d) all of the mentioned
Answer: b
Explanation: None.
9. In a paged memory, the page hit ratio is 0.35. The required to access a page in secondary memory is equal to 100
ns. The time required to access a page in primary memory is 10 ns. The average time required to access a page is?
a) 3.0 ns
b) 68.0 ns
c) 68.5 ns
d) 78.5 ns
Answer: c
Explanation: None.
10. To obtain better memory utilization, dynamic loading is used. With dynamic loading, a routine is not loaded unti
l it is called. For implementing dynamic loading ____________
a) special support from hardware is required
b) special support from operating system is essential
c) special support from both hardware and operating system is essential
d) user programs can implement dynamic loading without any special support from hardware or operating system
Answer: d
Explanation: None.
11. In paged memory systems, if the page size is increased, then the internal fragmentation generally ____________
a) becomes less
b) becomes more
c) remains constant
d) none of the mentioned
Answer: b
Explanation: None.
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1. In segmentation, each address is specified by ____________
a) a segment number & offset
b) an offset & value
c) a value & segment number
d) a key & value
Answer: a
Explanation: None.
2. In paging the user provides only ________ which is partitioned by the hardware into ________ and ______
a) one address, page number, offset
b) one offset, page number, address
c) page number, offset, address
d) none of the mentioned
Answer: a
Explanation: None.
3. Each entry in a segment table has a ____________
a) segment base
b) segment peak
c) segment value
d) none of the mentioned
Answer: a
Explanation: None.
4. The segment base contains the ____________
a) starting logical address of the process
b) starting physical address of the segment in memory
c) segment length
d) none of the mentioned
Answer: b
Explanation: None.
5. The segment limit contains the ____________
a) starting logical address of the process
b) starting physical address of the segment in memory
c) segment length
d) none of the mentioned
Answer: c
Explanation: None.
6. The offset ‘d’ of the logical address must be ____________
a) greater than segment limit
b) between 0 and segment limit
c) between 0 and the segment number
d) greater than the segment number
Answer: b
Explanation: None.
7. If the offset is legal ____________
a) it is used as a physical memory address itself
b) it is subtracted from the segment base to produce the physical memory address
c) it is added to the segment base to produce the physical memory address
d) none of the mentioned
Answer: a
Explanation: None.
8. When the entries in the segment tables of two different processes point to the same physical location __________
__
a) the segments are invalid
b) the processes get blocked
c) segments are shared
d) all of the mentioned
Answer: c
Explanation: None.
9. The protection bit is 0/1 based on ____________
a) write only
b) read only
c) read – write
d) none of the mentioned
Answer: c
Explanation: None.
10. If there are 32 segments, each of size 1Kb, then the logical address should have ____________
a) 13 bits
b) 14 bits
c) 15 bits
d) 16 bits
Answer: a
Explanation: To specify a particular segment, 5 bits are required. To select a particular byte after selecting a page, 1
0 more bits are required. Hence 15 bits are required.
11. Consider a computer with 8 Mbytes of main memory and a 128K cache. The cache block size is 4 K. It uses a di
rect mapping scheme for cache management. How many different main memory blocks can map onto a given physic
al cache block?
a) 2048
b) 256
c) 64
d) 8
Answer: c
Explanation: None.
12. A multilevel page table is preferred in comparison to a single level page table for translating virtual address to ph
ysical address because ____________
a) it reduces the memory access time to read or write a memory location
b) it helps to reduce the size of page table needed to implement the virtual address space of a process
c) it is required by the translation lookaside buffer
d) it helps to reduce the number of page faults in page replacement algorithms
Answer: b
Explanation: None.
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1. If one or more devices use a common set of wires to communicate with the computer system, the connection is cal
led ______
a) CPU
b) Monitor
c) Wirefull
d) Bus
Answer: d
Explanation: None.
2. A ____ a set of wires and a rigidly defined protocol that specifies a set of messages that can be sent on the wires.
a) port
b) node
c) bus
d) none of the mentioned
Answer: c
Explanation: None.
3. When device A has a cable that plugs into device B, and device B has a cable that plugs into device C and device
C plugs into a port on the computer, this arrangement is called a _________
a) port
b) daisy chain
c) bus
d) cable
Answer: b
Explanation: None.
4. The _________ present a uniform device-access interface to the I/O subsystem, much as system calls provide a st
andard interface between the application and the operating system.
a) Devices
b) Buses
c) Device drivers
d) I/O systems
Answer: c
Explanation: None.
5. A ________ is a collection of electronics that can operate a port, a bus, or a device.
a) controller
b) driver
c) host
d) bus
Answer: a
Explanation: None.
6. An I/O port typically consists of four registers status, control, ________ and ________ registers.
a) system in, system out
b) data in, data out
c) flow in, flow out
d) input, output
Answer: b
Explanation: None.
7. The ______ register is read by the host to get input.
a) flow in
b) flow out
c) data in
d) data out
Answer: c
Explanation: None.
8. The ______ register is written by the host to send output.
a) status
b) control
c) data in
d) data out
Answer: d
Explanation: None.
9. The hardware mechanism that allows a device to notify the CPU is called _______
a) polling
b) interrupt
c) driver
d) controlling
Answer: b
Explanation: None.
10. The CPU hardware has a wire called __________ that the CPU senses after executing every instruction.
a) interrupt request line
b) interrupt bus
c) interrupt receive line
d) interrupt sense line
Answer: a
Explanation: None.
11. The _________ determines the cause of the interrupt, performs the necessary processing and executes a return fr
om the interrupt instruction to return the CPU to the execution state prior to the interrupt.
a) interrupt request line
b) device driver
c) interrupt handler
d) all of the mentioned
Answer: c
Explanation: None.
12. In general the two interrupt request lines are ____________
a) maskable & non maskable interrupts
b) blocked & non maskable interrupts
c) maskable & blocked interrupts
d) none of the mentioned
Answer: a
Explanation: None.
13. The _________ are reserved for events such as unrecoverable memory errors.
a) non maskable interrupts
b) blocked interrupts
c) maskable interrupts
d) none of the mentioned
Answer: a
Explanation: None.
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1. The ________ can be turned off by the CPU before the execution of critical instruction sequences that must not b
e interrupted.
a) nonmaskable interrupt
b) blocked interrupt
c) maskable interrupt
d) none of the mentioned
Answer: c
Explanation: None.
2. The __________ is used by device controllers to request service.
a) nonmaskable interrupt
b) blocked interrupt
c) maskable interrupt
d) none of the mentioned
Answer: c
Explanation: None.
3. The interrupt vector contains ____________
a) the interrupts
b) the memory addresses of specialized interrupt handlers
c) the identifiers of interrupts
d) the device addresses
Answer: b
Explanation: None.
4. Division by zero, accessing a protected or non existent memory address, or attempting to execute a privileged inst
ruction from user mode are all categorized as ________
a) errors
b) exceptions
c) interrupt handlers
d) all of the mentioned
Answer: b
Explanation: None.
5. For large data transfers, _________ is used.
a) dma
b) programmed I/O
c) controller register
d) none of the mentioned
Answer: a
Explanation: None.
6. A character stream device transfers ____________
a) bytes one by one
b) block of bytes as a unit
c) with unpredictable response times
d) none of the mentioned
Answer: a
Explanation: None.
7. A block device transfers ____________
a) bytes one by one
b) block of bytes as a unit
c) with unpredictable response times
d) none of the mentioned
Answer: b
Explanation: None.
8. What is a dedicated device?
a) opposite to a sharable device
b) same as a sharable device
c) can be used concurrently by several processes
d) none of the mentioned
Answer: a
Explanation: None.
9. A keyboard is an example of a device that is accessed through a __________ interface.
a) block stream
b) set of blocks
c) character stream
d) none of the mentioned
Answer: c
Explanation: None.
10. In polling ____________
a) busy – wait cycles wait for I/O from device
b) interrupt handler receives interrupts
c) interrupt-request line is triggered by I/O device
d) all of the mentioned
Answer: a
Explanation: None.
11. A non blocking system call _________________
a) halts the execution of the application for an extended time
b) does not halt the execution of the application
c) does not block the interrupts
d) none of the mentioned
Answer: b
Explanation: None.
12. An asynchronous call ____________
a) returns immediately, without waiting for the I/O to complete
b) does not return immediately and waits for the I/O to complete
c) consumes a lot of time
d) is too slow
Answer: a
Explanation: None.
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1. Buffering is done to ____________
a) cope with device speed mismatch
b) cope with device transfer size mismatch
c) maintain copy semantics
d) all of the mentioned
Answer: d
Explanation: None.
2. Caching is ________ spooling.
a) same as
b) not the same as
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: None.
3. Caching ____________
a) holds a copy of the data
b) is fast memory
c) holds the only copy of the data
d) holds output for a device
Answer: a
Explanation: None.
4. Spooling ____________
a) holds a copy of the data
b) is fast memory
c) holds the only copy of the data
d) holds output for a device
Answer: c
Explanation: None.
5. The ________ keeps state information about the use of I/O components.
a) CPU
b) OS
c) kernel
d) shell
Answer: c
Explanation: None.
6. The kernel data structures include ____________
a) process table
b) open file table
c) close file table
d) all of the mentioned
Answer: b
Explanation: None.
7. Windows NT uses a __________ implementation for I/O.
a) message – passing
b) draft – passing
c) secondary memory
d) cache
Answer: a
Explanation: None.
8. A ________ is a full duplex connection between a device driver and a user level process.
a) Bus
b) I/O operation
c) Stream
d) Flow
Answer: c
Explanation: None.
9. I/O is a _________ in system performance.
a) major factor
b) minor factor
c) does not matter
d) none of the mentioned
Answer: a
Explanation: None.
10. If the number of cycles spent busy – waiting is not excessive, then ____________
a) interrupt driven I/O is more efficient than programmed I/O
b) programmed I/O is more efficient than interrupt driven I/O
c) both programmed and interrupt driven I/O are equally efficient
d) none of the mentioned
Answer: b
Explanation: None.
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1. What is the disadvantage of real addressing mode?
a) there is a lot of cost involved
b) time consumption overhead
c) absence of memory protection between processes
d) restricted access to memory locations by processes
Answer: c
Explanation: None.
2. Preemptive, priority based scheduling guarantees ____________
a) hard real time functionality
b) soft real time functionality
c) protection of memory
d) none of the mentioned
Answer: b
Explanation: None.
3. Real time systems must have ____________
a) preemptive kernels
b) non preemptive kernels
c) preemptive kernels or non preemptive kernels
d) neither preemptive nor non preemptive kernels
Answer: a
Explanation: None.
4. What is Event latency?
a) the amount of time an event takes to occur from when the system started
b) the amount of time from the event occurrence till the system stops
c) the amount of time from event occurrence till the event crashes
d) the amount of time that elapses from when an event occurs to when it is serviced.
Answer: d
Explanation: None.
5. Interrupt latency refers to the period of time ____________
a) from the occurrence of an event to the arrival of an interrupt
b) from the occurrence of an event to the servicing of an interrupt
c) from arrival of an interrupt to the start of the interrupt service routine
d) none of the mentioned
Answer: c
Explanation: None.
6. Real time systems need to __________ the interrupt latency.
a) minimize
b) maximize
c) not bother about
d) none of the mentioned
Answer: a
Explanation: None.
7. The amount of time required for the scheduling dispatcher to stop one process and start another is known as ____
__________
a) event latency
b) interrupt latency
c) dispatch latency
d) context switch
Answer: c
Explanation: None.
8. The most effective technique to keep dispatch latency low is to ____________
a) provide non preemptive kernels
b) provide preemptive kernels
c) make it user programmed
d) run less number of processes at a time
Answer: b
Explanation: None.
9. Priority inversion is solved by use of _____________
a) priority inheritance protocol
b) two phase lock protocol
c) time protocol
d) all of the mentioned
Answer: a
Explanation: None.
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1. In a real time system the computer results ____________
a) must be produced within a specific deadline period
b) may be produced at any time
c) may be correct
d) all of the mentioned
Answer: a
Explanation: None.
2. In a safety critical system, incorrect operation ____________
a) does not affect much
b) causes minor problems
c) causes major and serious problems
d) none of the mentioned
Answer: c
Explanation: None.
3. Antilock brake systems, flight management systems, pacemakers are examples of ____________
a) safety critical system
b) hard real time system
c) soft real time system
d) safety critical system and hard real time system
Answer: d
Explanation: None.
4. In a ______ real time system, it is guaranteed that critical real time tasks will be completed within their deadlines.
a) soft
b) hard
c) critical
d) none of the mentioned
Answer: b
Explanation: None.
5. Some of the properties of real time systems include ____________
a) single purpose
b) inexpensively mass produced
c) small size
d) all of the mentioned
Answer: d
Explanation: None.
6. The amount of memory in a real time system is generally ____________
a) less compared to PCs
b) high compared to PCs
c) same as in PCs
d) they do not have any memory
Answer: a
Explanation: None.
7. What is the priority of a real time task?
a) must degrade over time
b) must not degrade over time
c) may degrade over time
d) none of the mentioned
Answer: b
Explanation: None.
8. Memory management units ____________
a) increase the cost of the system
b) increase the power consumption of the system
c) increase the time required to complete an operation
d) all of the mentioned
Answer: d
Explanation: None.
9. The technique in which the CPU generates physical addresses directly is known as ____________
a) relocation register method
b) real addressing
c) virtual addressing
d) none of the mentioned
Answer: b
Explanation: None.
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1. Earliest deadline first algorithm assigns priorities according to ____________
a) periods
b) deadlines
c) burst times
d) none of the mentioned
Answer: b
Explanation: None.
2. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35. The tota
l CPU utilization is ____________
a) 0.90
b) 0.74
c) 0.94
d) 0.80
Answer: c
Explanation: None.
3. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35., the prio
rities of P1 and P2 are?
a) remain the same throughout
b) keep varying from time to time
c) may or may not be change
d) none of the mentioned
Answer: b
Explanation: None.
4. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35., can the
two processes be scheduled using the EDF algorithm without missing their respective deadlines?
a) Yes
b) No
c) Maybe
d) None of the mentioned
Answer: a
Explanation: None.
5. Using EDF algorithm practically, it is impossible to achieve 100 percent utilization due to __________
a) the cost of context switching
b) interrupt handling
c) power consumption
d) all of the mentioned
Answer: a
Explanation: None.
6. T shares of time are allocated among all processes out of N shares in __________ scheduling algorithm.
a) rate monotonic
b) proportional share
c) earliest deadline first
d) none of the mentioned
Answer: b
Explanation: None.
7. If there are a total of T = 100 shares to be divided among three processes, A, B and C. A is assigned 50 shares, B i
s assigned 15 shares and C is assigned 20 shares.
a) 20
b) 15
c) 50
d) none of the mentioned
Answer: c
Explanation: None.
8. If there are a total of T = 100 shares to be divided among three processes, A, B and C. A is assigned 50 shares, B
is assigned 15 shares and C is assigned 20 shares.
a) 20
b) 15
c) 50
d) none of the mentioned
Answer: b
Explanation: None.
9. If there are a total of T = 100 shares to be divided among three processes, A, B and C. A is assigned 50 shares, B
is assigned 15 shares and C is assigned 20 shares.
a) 20
b) 15
c) 50
d) none of the mentioned
Answer: a
Explanation: None.
10. If there are a total of T = 100 shares to be divided among three processes, A, B and C. A is assigned 50 shares,
B is assigned 15 shares and C is assigned 20 shares.
a) allocate 30 shares to it
b) deny entry to D in the system
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: None.
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1. To schedule the processes, they are considered _________
a) infinitely long
b) periodic
c) heavy weight
d) light weight
Answer: b
Explanation: None.
2. If the period of a process is ‘p’, then what is the rate of the task?
a) p2
b) 2*p
c) 1/p
d) p
Answer: c
Explanation: None.
3. The scheduler admits a process using __________
a) two phase locking protocol
b) admission control algorithm
c) busy wait polling
d) none of the mentioned
Answer: c
Explanation: None.
4. The ____________ scheduling algorithm schedules periodic tasks using a static priority policy with preemption.
a) earliest deadline first
b) rate monotonic
c) first cum first served
d) priority
Answer: b
Explanation: None.
5. Rate monotonic scheduling assumes that the __________
a) processing time of a periodic process is same for each CPU burst
b) processing time of a periodic process is different for each CPU burst
c) periods of all processes is the same
d) none of the mentioned
Answer: a
Explanation: None.
6. In rate monotonic scheduling, a process with a shorter period is assigned __________
a) a higher priority
b) a lower priority
c) higher & lower priority
d) none of the mentioned
Answer: a
Explanation: None.
7. There are two processes P1 and P2, whose periods are 50 and 100 respectively. P1 is assigned higher priority than
P2. The processing times are t1 = 20 for P1 and t2 = 35 for P2. Is it possible to schedule these tasks so that each me
ets its deadline using Rate monotonic scheduling?
a) yes
b) no
c) maybe
d) none of the mentioned
Answer: a
Explanation: None.
8. If a set of processes cannot be scheduled by rate monotonic scheduling algorithm, then __________
a) they can be scheduled by EDF algorithm
b) they cannot be scheduled by EDF algorithm
c) they cannot be scheduled by any other algorithm
d) none of the mentioned
Answer: c
Explanation: None.
9. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35. The tota
l CPU utilization is?
a) 0.90
b) 0.74
c) 0.94
d) 0.80
Answer: c
Explanation: None.
10. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35. Can th
e processes be scheduled without missing the deadlines?
a) Yes
b) No
c) Maybe
d) None of the mentioned
Answer: b
Explanation: None.
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1. The major difference between a multimedia file and a regular file is ___________
a) the size
b) the attributes
c) the ownership
d) the rate at which the file must be accessed
Answer: d
Explanation: Multimedia files must be accessed at a specific rate whereas accessing regular files requires no special
timings.
2. Video is represented as a series of images formally known as ___________
a) pics
b) shots
c) frames
d) snaps
Answer: c
Explanation: None.
3. The faster the frames are displayed, ___________
a) the rougher the video appears
b) the smoother the video appears
c) it gets blurry
d) none of the mentioned
Answer: b
Explanation: None.
4. The characteristic of the eye to retain the image for a short time after it has been presented is known as ________
___
a) persistence of vision
b) learning power
c) memory mapped input
d) none of the mentioned
Answer: a
Explanation: None.
5. When will Local playback be used?
a) the multimedia data are delivered from a local file system
b) a computer next to you is playing something
c) a multimedia file is being played on a system in the local network
d) none of the mentioned
Answer: a
Explanation: None.
6. Multimedia files stored on a remote server are delivered to a client across the network using a technique known as
___________
a) download
b) streaming
c) flowing
d) leaking
Answer: b
Explanation: None.
7. What are the two types of streaming techniques?
a) progressive download & real time streaming
b) regular download & real time streaming
c) real time & virtual time streaming
d) virtual time streaming
Answer: a
Explanation: None.
8. A media file containing audio or video is downloaded and stored on the client’s local file system in ___________
a) progressive download
b) regular download
c) real time streaming
d) virtual time streaming
Answer: a
Explanation: As the file is being downloaded, the client is able to play back the media file without having to wait for
the file to be downloaded in its entirety.
9. Progressive download is most useful for ___________
a) short video clips
b) long video clips
c) extremely long and high quality videos
d) none of the mentioned
Answer: a
Explanation: None.
10. The media file is streamed to the client but is only played and not stored by the client in ___________
a) progressive download
b) regular download
c) real time streaming
d) virtual time streaming
Answer: c
Explanation: None.
11. Real time streaming is most useful for ___________
a) short video clips
b) long video clips
c) extremely short and low quality videos
d) none of the mentioned
Answer: b
Explanation: None.
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1. The ability to move around within a media stream is known as ___________
a) buffering
b) random access
c) access
d) sequential access
Answer: b
Explanation: None.
2. What are the two types of real time streaming?
a) live & on demand streaming
b) dead & static streaming
c) static & on demand streaming
d) on demand streaming
Answer: a
Explanation: None.
3. Random access is not allowed in ___________
a) live streaming
b) dead streaming
c) static streaming
d) on demand streaming
Answer: a
Explanation: None.
4. The streaming that takes place as the event is occurring is ___________
a) live streaming
b) dead streaming
c) static streaming
d) on demand streaming
Answer: d
Explanation: None.
5. For a computer to deliver continuous media it must guarantee the specific rate and timing requirements, also kno
wn as ___________
a) deadline
b) quality of service
c) period
d) burst time
Answer: b
Explanation: None.
6. For QOS to be implemented properly ___________
a) file systems must be efficient to meet the rate requirements of continuous media
b) network protocols must support bandwidth requirements while minimizing delay and jitter
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: None.
7. What will happen once a file is compressed?
a) it has a better quality
b) it takes up less space for storage
c) it cannot be delivered to the client more quickly
d) none of the mentioned
Answer: b
Explanation: None.
8. Compression ratio is the ratio of ___________
a) the original file size to the size of the compressed file
b) the number of pixels in a frame of the original size to those in a frame of the compressed file
c) compressed file size to the original file size
d) none of the mentioned
Answer: a
Explanation: None.
9. Lossy and lossless are classifications of ___________
a) multimedia storage systems
b) files
c) compression algorithms
d) all of the mentioned
Answer: c
Explanation: None.
10. Lossy techniques provide ___________ when compared to lossless techniques.
a) lower compression ratios
b) much higher compression ratios
c) similar compression ratios
d) none of the mentioned
Answer: b
Explanation: None.
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1. What is the full form of MPEG?
a) Motion Pictures Engineering Group
b) Motion Picture Engineers Group
c) Motion Picture Experts Group
d) None of the mentioned
Answer: c
Explanation: None.
2. What is MPEG compression?
a) stores the compression values of each frame
b) stores the differences between successive frames
c) stores multiple frames’ values together
d) none of the mentioned
Answer: b
Explanation: None.
3. What are the levels in QoS?
a) Best effort service
b) Soft QoS
c) Hard QoS
d) All of the mentioned
Answer: d
Explanation: None.
4. The level that treats different types of traffics in different ways, giving certain traffic streams higher priority than
other streams and with best efforts, but no guarantees are made ___________
a) Best effort service
b) Soft QoS
c) Worst effort service
d) Hard QoS
Answer: b
Explanation: None.
5. The quality of service requirements are guaranteed in ___________
a) Best effort service
b) Soft QoS
c) Worst effort service
d) Hard QoS
Answer: d
Explanation: None.
6. What are the factors that define QoS?
a) Throughput
b) Jitter
c) Delay
d) All of the mentioned
Answer: d
Explanation: None.
7. Delay and Jitter ___________
a) mean the same thing
b) are two completely different things
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: None.
8. What is the Delay?
a) the time from when a request is first submitted to when the desired result is produced
b) the delay that occurs during playback of the stream
c) how the errors are handled during the transmission and processing of continuous media
d) none of the mentioned
Answer: a
Explanation: None.
9. What is Admission control?
a) the delay that occurs during playback of the stream
b) the practice of admitting a request for service only if the server has sufficient resources to satisfy the request
c) how the errors are handled during the transmission and processing of continuous media
d) none of the mentioned
Answer: b
Explanation: None.
10. An admission control scheme assigns a __________ to each type of resource.
a) processor
b) memory location
c) resource manager
d) all of the mentioned
Answer: c
Explanation: None.
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1. A scheduling algorithm can use either ___________ priority or ________ priority.
a) static, still
b) static, dynamic
c) live, dead
d) none of the mentioned
Answer: b
Explanation: None.
2. The priority of a process will ______________ if the scheduler assigns it a static priority.
a) change
b) remain unchanged
c) depends on the operating system
d) none of the mentioned
Answer: b
Explanation: None.
3. As disks have relatively low transfer rates and relatively high latency rates, disk schedulers must reduce latency ti
mes to ___________
a) ensure high bandwidth
b) ensure low bandwidth
c) make sure data is transferred
d) reduce data transfer speeds
Answer: a
Explanation: None.
4. Servicing requests strictly according to deadline using EDF may result in ___________
a) lower seek times
b) lower bandwidth
c) higher seek time
d) higher bandwidth
Answer: c
Explanation: None.
5. The hybrid algorithm that combines EDF with SCAN algorithm is known as ___________
a) EDS
b) SDF
c) SCAN-EDF
d) None of the mentioned
Answer: c
Explanation: None.
6. If several requests have different deadlines that are relatively close together, then using the SCAN – EDF algorith
m ___________
a) the SCAN ordering will service the requests in that batch
b) the EDF ordering will service the requests in that batch
c) the FCFS ordering will service the requests in that batch
d) none of the mentioned
Answer: a
Explanation: None.
7. Multimedia systems require _________ scheduling to ensure critical tasks will be serviced within timing deadline
s.
a) soft real time
b) hard real time
c) normal
d) none of the mentioned
Answer: b
Explanation: None.
8. The EDF scheduler uses ________ to order requests according to their deadlines.
a) stack
b) disks
c) queue
d) none of the mentioned
Answer: c
Explanation: None.
9. In SCAN – EDF, requests with the same deadlines are ordered according to ___________
a) SCAN policy
b) EDF policy
c) FCFS policy
d) FIFO policy
Answer: a
Explanation: None.
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1. The three general methods for delivering content from a server to a client across a network are ___________
a) unicasting
b) multicasting
c) broadcasting
d) all of the mentioned
Answer: d
Explanation: None.
2. Unicasting delivers the content to ___________
a) a single client
b) all clients, regardless whether they want the content or not
c) a group of receivers who indicate they wish to receive the content
d) none of the mentioned
Answer: a
Explanation: None.
3. Broadcasting delivers the content to ___________
a) a single client
b) all clients, regardless whether they want the content or not
c) a group of receivers who indicate they wish to receive the content
d) none of the mentioned
Answer: b
Explanation: None.
4. Multicasting delivers the content to ___________
a) a single client
b) all clients, regardless whether they want the content or not
c) a group of receivers who indicate they wish to receive the content
d) none of the mentioned
Answer: c
Explanation: None.
5. RTSP stands for ___________
a) Real Time Streaming Policy
b) Real Time Streaming Protocol
c) Real Time Systems Protocol
d) Read Time Streaming Policy
Answer: b
Explanation: None.
6. HTTP is __________
a) a stateful protocol
b) a stateless protocol
c) a protocol that maintains the status of its connection with the client
d) a stateless protocol that does not maintain the status of its connection with the client
Answer: d
Explanation: None.
7. RTSP includes which of the following states?
a) SETUP
b) PLAY
c) PAUSE
d) All of the mentioned
Answer: d
Explanation: None.
8. In the SETUP state ___________
a) the server is setup
b) the client is setup
c) the server allocates resources for the client session
d) the client sends requests to the server
Answer: c
Explanation: None.
9. In the TEARDOWN state ___________
a) the server breaks down the connection and releases the resources allocated for the session
b) the client breaks down the connection and releases the resources allocated for the session
c) the system crashes
d) none of the mentioned
Answer: a
Explanation: None.
10. RTP stands for ___________
a) real time protocol
b) real time transmission control protocol
c) real time transmission protocol
d) real time transport protocol
Answer: d
Explanation: None.
11. The problem with unicast delivery is that the ___________
a) memory allocation is difficult
b) server must establish a separate unicast session for each client
c) the routers must support unicasting
d) the clients must be close to the server
Answer: b
Explanation: None.
12. The difficulty with multicasting from a practical point of view is ___________
a) memory allocation is difficult
b) server must establish a separate unicast session for each client
c) the routers must support multicasting
d) none of the mentioned
Answer: c
Explanation: None.
13. To let a client have random access to a media stream with ___________
a) the protocol used must not be stateless
b) the server must support download
c) the stream should give access rights to the client
d) all of the mentioned
Answer: a
Explanation: None.
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1. Which of the following are forms of malicious attack?
a) Theft of information
b) Modification of data
c) Wiping of information
d) All of the mentioned
Answer: d
Explanation: None.
2. What are the common security threats?
a) File Shredding
b) File sharing and permission
c) File corrupting
d) File integrity
Answer: b
Explanation: Sharing and associated permissions are usual exploits which can compromise the system.
3. From the following, which is not a common file permission?
a) Write
b) Execute
c) Stop
d) Read
Answer: c
Explanation: None.
4. Which of the following is a good practice?
a) Give full permission for remote transferring
b) Grant read only permission
c) Grant limited permission to specified account
d) Give both read and write permission but not execute
Answer: c
Explanation: Limited access is a key method to circumvent unauthorized access and exploits.
5. What is not a good practice for user administration?
a) Isolating a system after a compromise
b) Perform random auditing procedures
c) Granting privileges on a per host basis
d) Using telnet and FTP for remote access
Answer: d
Explanation: Telnet and FTP are not encrypted and can be compromised.
6. Which of the following is the least secure method of authentication?
a) Key card
b) fingerprint
c) retina pattern
d) Password
Answer: d
Explanation: Passwords can be compromised more easily than to replicate a physical thing like key card, fingerprint
or retina.
7. Which of the following is a strong password?
a) 19thAugust88
b) Delhi88
c) P@assw0rd
d) !augustdelhi
Answer: c
Explanation: It has a combination of Alphabet both capital and small along with number and special character. Thus
always use complex password with a combination of all these.
8. Why is one time password safe?
a) It is easy to generated
b) It cannot be shared
c) It is different for every access
d) It is a complex encrypted password
Answer: c
Explanation: One time password is safe since it is generated per access and thus cannot be brute forced or deduced.
9. What does Light Directory Access Protocol (LDAP) doesn’t store?
a) Users
b) Address
c) Passwords
d) Security Keys
Answer: b
Explanation: None.
10. What is characteristic of RADIUS system?
a) It is essential for centralized encryption and authentication
b) It works on Network layer to deny access to unauthorized people
c) It provides centralized authentication mechanism via network devices
d) It’s a strong File access system
Answer: c
Explanation: None.
11. Which happens first authorization or authentication?
a) Authorization
b) Authentication
c) Authorization & Authentication are same
d) None of the mentioned
Answer: a
Explanation: None.
12. What are the characteristics of Authorization?
a) RADIUS and RSA
b) 3 way handshaking with syn and fin
c) Multilayered protection for securing resources
d) Deals with privileges and rights
Answer: d
Explanation: None.
13. What forces the user to change password at first login?
a) Default behavior of OS
b) Part of AES encryption practice
c) Devices being accessed forces the user
d) Account administrator
Answer: d
Explanation: Its administrator’s job to ensure that password of the user remains private and is known only to user. B
ut while making a new user account he assigns a random general password to give it to user. Thus even administrato
r cannot access a particular users account.
14. What is not a best practice for password policy?
a) Deciding maximum age of password
b) Restriction on password reuse and history
c) Password encryption
d) Having change password every 2 years
Answer: d
Explanation: Old passwords are more vulnerable to being misplaced or compromised. Passwords should be changed
periodically to enhance security.
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1. What is the breach of integrity?
a) This type of violation involves unauthorized reading of data
b) This violation involves unauthorized modification of data
c) This violation involves unauthorized destruction of data
d) This violation involves unauthorized use of resources
Answer: b
Explanation: None.
2. What is breach of confidentiality?
a) This type of violation involves unauthorized reading of data
b) This violation involves unauthorized modification of data
c) This violation involves unauthorized destruction of data
d) This violation involves unauthorized use of resources
Answer: a
Explanation: None.
3. What is theft of service?
a) This type of violation involves unauthorized reading of data
b) This violation involves unauthorized modification of data
c) This violation involves unauthorized destruction of data
d) This violation involves unauthorized use of resources
Answer: d
Explanation: None.
4. What is breach of availability?
a) This type of violation involves unauthorized reading of data
b) This violation involves unauthorized modification of data
c) This violation involves unauthorized destruction of data
d) This violation involves unauthorized use of resources
Answer: c
Explanation: None.
5. What is Trojan horse?
a) It is a useful way to encrypt password
b) It is a user which steals valuable information
c) It is a rogue program which tricks users
d) It’s a brute force attack algorithm
Answer: c
Explanation: None.
6. What is trap door?
a) IT is trap door in WarGames
b) It is a hole in software left by designer
c) It is a Trojan horse
d) It is a virus which traps and locks user terminal
Answer: b
Explanation: None.
7. Which mechanism is used by worm process?
a) Trap door
b) Fake process
c) Spawn Process
d) VAX process
Answer: c
Explanation: None.
8. Which of the following is not a characteristic of a virus?
a) Virus destroy and modify user data
b) Virus is a standalone program
c) Virus is a code embedded in a legitimate program
d) Virus cannot be detected
Answer: d
Explanation: Virus can be detected by having an antivirus program.
9. What is known as masquerading?
a) When one participant in communication pretends to be someone else
b) When attacker modifies data in communication
c) When attack is of fraudulent repeat of a valid data
d) When attack gains access to remote systems
Answer: a
Explanation: None.
10. Who unleashed famous worm attack in 1988 which effected UNIX systems and caused losses in millions?
a) Robert Morris
b) Bob Milano
c) Mark zuckerberg
d) Bill Gates
Answer: a
Explanation: None.
11. What is port scanning?
a) It is a software used to scan system for attack
b) It is a software application designed to probe a server or host for open ports
c) It is software used to scan system for introducing attacks by brute force
d) None of the mentioned
Answer: b
Explanation: None.
12. Which is not a port scan type?
a) TCP scanning
b) SYN scanning
c) UDP scanning
d) SYSTEM Scanning
Answer: d
Explanation: None.
13. Which is not a valid port scan type?
a) ACK scanning
b) Window scanning
c) IGMP scan
d) FIN scanning
Answer: c
Explanation: None.
14. What are zombie systems?
a) Are specific system which are designed to attack by manufacturer
b) They are network of known hacking group
c) These systems are previously compromised independent systems
d) None of the mentioned
Answer: c
Explanation: None.
15. What is known as a DOS attack?
a) It is attacked to block traffic of network
b) It is attacked to harm contents stored in HDD by worm spawn processes
c) It is an attempt to make a machine or network resource unavailable
d) None of the mentioned
Answer: c
Explanation: None.
16. With regard to DOS attack what is not true from below options?
a) We can stop DOS attack completely
b) By upgrading OS vulnerability we can stop DOS attack to some extent
c) DOS attack has to be stopped at network level
d) Such attack can last for hours
Answer: a
Explanation: None.
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1. What is not an important part of security protection?
a) Large amount of RAM to support antivirus
b) Strong passwords
c) Audit log periodically
d) Scan for unauthorized programs in system directories
Answer: a
Explanation: RAM has no effect on security of a system. System’s protection remains unchanged in increasing or de
creasing amount of RAM.
2. What is used to protect network from outside internet access?
a) A trusted antivirus
b) 24 hours scanning for virus
c) Firewall to separate trusted and untrusted network
d) Deny users access to websites which can potentially cause security leak
Answer: c
Explanation: Firewall create a protective barrier to secure internal network. An antivirus can only detect harmful vir
uses but cannot stop illegal access by remote attacker.
3. What is the best practice in the firewall domain environment?
a) Create two domain trusted and untrusted domain
b) Create strong policy in firewall to support different types of users
c) Create a Demilitarized zone
d) Create two DMZ zones with one untrusted domain
Answer: c
Explanation: All live servers or workstations are kept in a separate zone than inside and outside to enhance protectio
n.
4. Which direction access cannot happen using DMZ zone by default?
a) Company computer to DMZ
b) Internet to DMZ
c) Internet to company computer
d) Company computer to internet
Answer: c
Explanation: Connection from internet is never allowed to directly access internal PCs but is routed through DMZ z
one to prevent attacks.
5. What are the two features of a tripwire file system?
a) It is a tool to monitor file systems
b) It is used to automatically take corrective action
c) It is used to secure UNIX system
d) None of the mentioned
Answer: a
Explanation: None.
6. How do viruses avoid basic pattern match of antivirus?
a) They are encrypted
b) They act with special permissions
c) They modify themselves
d) None of the mentioned
Answer: c
Explanation: None.
7. How does an antivirus of today identify viruses?
a) Previously known patterns
b) It can detect unknown patterns
c) It can take high priority to increase scanning speed
d) None of the mentioned
Answer: a
Explanation: None.
8. What is known as a sandbox?
a) It is a program which can be molded to do the desired task
b) It is a program that is controlled or emulated section of OS
c) It is a special mode of antivirus
d) None of the mentioned
Answer: b
Explanation: None.
9. What is are two safe computing practices?
a) Not to open software from unknown vendors
b) Open and execute programs in admin level/root
c) Open and execute programs in presence of antivirus
d) None of the mentioned
Answer: a
Explanation: Disgruntled employees have in past infected the master copies of software programs to do economic ha
rm to the company.
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1. What are the different ways to intrude?
a) Buffer overflows
b) Unexpected combinations and unhandled input
c) Race conditions
d) All of the mentioned
Answer: d
Explanation: None.
2. What are the major components of the intrusion detection system?
a) Analysis Engine
b) Event provider
c) Alert Database
d) All of the mentioned
Answer: d
Explanation: None.
3. What are the different ways to classify an IDS?
a) anomaly detection
b) signature based misuse
c) stack based
d) all of the mentioned
Answer: d
Explanation: None.
4. What are the different ways to classify an IDS?
a) Zone based
b) Host & Network based
c) Network & Zone based
d) Level based
Answer: b
Explanation: None.
5. What are the characteristics of anomaly based IDS?
a) It models the normal usage of network as a noise characterization
b) It doesn’t detect novel attacks
c) Anything distinct from the noise is not assumed to be intrusion activity
d) It detects based on signature
Answer: a
Explanation: None.
6. What is the major drawback of anomaly detection IDS?
a) These are very slow at detection
b) It generates many false alarms
c) It doesn’t detect novel attacks
d) None of the mentioned
Answer: b
Explanation: None.
7. What are the characteristics of signature based IDS?
a) Most are based on simple pattern matching algorithms
b) It is programmed to interpret a certain series of packets
c) It models the normal usage of network as a noise characterization
d) Anything distinct from the noise is assumed to be intrusion activity
Answer: a
Explanation: None.
8. What are the drawbacks of signature based IDS?
a) They are unable to detect novel attacks
b) They suffer from false alarms
c) They have to be programmed again for every new pattern to be detected
d) All of the mentioned
Answer: d
Explanation: None.
9. What are the characteristics of Host based IDS?
a) The host operating system logs in the audit information
b) Logs includes logins,file opens and program executions
c) Logs are analysed to detect tails of intrusion
d) All of the mentioned
Answer: d
Explanation: None.
10. What are the drawbacks of the host based IDS?
a) Unselective logging of messages may increase the audit burdens
b) Selective logging runs the risk of missed attacks
c) They are very fast to detect
d) They have to be programmed for new patterns
Answer: a
Explanation: None.
11. What are the strengths of the host based IDS?
a) Attack verification
b) System specific activity
c) No additional hardware required
d) All of the mentioned
Answer: d
Explanation: None.
12. What are characteristics of stack based IDS?
a) They are integrated closely with the TCP/IP stack and watch packets
b) The host operating system logs in the audit information
c) It is programmed to interpret a certain series of packets
d) It models the normal usage of network as a noise characterization
Answer: a
Explanation: None.
13. What are characteristics of Network based IDS?
a) They look for attack signatures in network traffic
b) Filter decides which traffic will not be discarded or passed
c) It is programmed to interpret a certain series of packet
d) It models the normal usage of network as a noise characterization
Answer: a
Explanation: None.
14. What are strengths of Network based IDS?
a) Cost of ownership reduced
b) Malicious intent detection
c) Real time detection and response
d) All of the mentioned
Answer: d
Explanation: None.
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1. What is the preferred way of encryption?
a) pre shared secret key
b) using key distribution center (KD
c)
c) public key-encryption
d) symmetric key
Answer: c
Explanation: Pre Shared key can be compromised and either party can be suspected. Likewise KDC or symmetric ke
y can have breach which are undesirable. Public and private key encryption is a known industry standard.
2. What is not a role of encryption?
a) It is used to protect data from unauthorized access during transmission
b) It is used to ensure user authentication
c) It is used to ensure data integrity
d) It is used to ensure data corruption doesn’t happens
Answer: d
Explanation: Encryption doesn’t have error correction or detection facility thus cannot be used to safeguard from dat
a corruption.
3. What is cipher-block chaining?
a) Data is logically ‘ANDed’ with previous block
b) Data is logically ‘ORed’ with previous block
c) Data is logically ‘XORed’ with previous block
d) None of the mentioned
Answer: c
Explanation: None.
4. What is not an encryption standard?
a) AES
b) TES
c) Triple DES
d) DES
Answer: b
Explanation: None.
5. Which of the following is not a stream cipher?
a) Two fish
b) RC5
c) RC4
d) TBONE
Answer: d
Explanation: None.
6. What is a Hash Function?
a) It creates a small flexible block of data
b) It creates a small,fixed block of data
c) It creates a encrypted block of data
d) None of the mentioned
Answer: b
Explanation: None.
7. MD5 produces __________ bits hash data.
a) 128
b) 150
c) 160
d) 112
Answer: a
Explanation: None.
8. SHA-1 produces __________ bit of hash.
a) 128
b) 160
c) 150
d) 112
Answer: b
Explanation: None.
9. Which two of the following are authentication algorithms?
a) MAC
b) AES
c) DAS
d) Digital-signature
Answer: a
Explanation: None.
10. What is the role of Key Distribution Center?
a) It is used to distribute keys to everyone in world
b) It intended to reduce the risks inherent in exchanging keys
c) All of the mentioned
d) None of the mentioned
Answer: b
Explanation: None.
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1. A thread is also called ___________
a) Light Weight Process(LWP)
b) Heavy Weight Process(HWP)
c) Process
d) None of the mentioned
Answer: a
Explanation: None.
2. A thread shares its resources(like data section, code section, open files, signals) with ___________
a) other process similar to the one that the thread belongs to
b) other threads that belong to similar processes
c) other threads that belong to the same process
d) all of the mentioned
Answer: c
Explanation: None.
3. A heavy weight process ___________
a) has multiple threads of execution
b) has a single thread of execution
c) can have multiple or a single thread for execution
d) none of the mentioned
Answer: b
Explanation: None.
4. A process having multiple threads of control implies ___________
a) it can do more than one task at a time
b) it can do only one task at a time, but much faster
c) it has to use only one thread per process
d) none of the mentioned
Answer: a
Explanation: None.
5. Multithreading an interactive program will increase responsiveness to the user by ___________
a) continuing to run even if a part of it is blocked
b) waiting for one part to finish before the other begins
c) asking the user to decide the order of multithreading
d) none of the mentioned
Answer: a
Explanation: None.
6. Resource sharing helps ___________
a) share the memory and resources of the process to which the threads belong
b) an application have several different threads of activity all within the same address space
c) reduce the address space that a process could potentially use
d) all of the mentioned
Answer: d
Explanation: None.
7. Multithreading on a multi – CPU machine ___________
a) decreases concurrency
b) increases concurrency
c) doesn’t affect the concurrency
d) can increase or decrease the concurrency
Answer: b
Explanation: None.
8. The kernel is _______ of user threads.
a) a part of
b) the creator of
c) unaware of
d) aware of
Answer: c
Explanation: None.
9. If the kernel is single threaded, then any user level thread performing a blocking system call will ___________
a) cause the entire process to run along with the other threads
b) cause the thread to block with the other threads running
c) cause the entire process to block even if the other threads are available to run
d) none of the mentioned
Answer: c
Explanation: None.
10. Because the kernel thread management is done by the Operating System itself ___________
a) kernel threads are faster to create than user threads
b) kernel threads are slower to create than user threads
c) kernel threads are easier to manage as well as create then user threads
d) none of the mentioned
Answer: b
Explanation: None.
11. If a kernel thread performs a blocking system call, ____________
a) the kernel can schedule another thread in the application for execution
b) the kernel cannot schedule another thread in the same application for execution
c) the kernel must schedule another thread of a different application for execution
d) the kernel must schedule another thread of the same application on a different processor
Answer: a
Explanation: None.
12. Which of the following is FALSE?
a) Context switch time is longer for kernel level threads than for user level threads
b) User level threads do not need any hardware support
c) Related kernel level threads can be scheduled on different processors in a multiprocessor system
d) Blocking one kernel level thread blocks all other related threads
Answer: d
Explanation: None.
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1. The model in which one kernel thread is mapped to many user-level threads is called ___________
a) Many to One model
b) One to Many model
c) Many to Many model
d) One to One model
Answer: a
Explanation: None.
2. The model in which one user-level thread is mapped to many kernel level threads is called ___________
a) Many to One model
b) One to Many model
c) Many to Many model
d) One to One model
Answer: b
Explanation: None.
3. In the Many to One model, if a thread makes a blocking system call ___________
a) the entire process will be blocked
b) a part of the process will stay blocked, with the rest running
c) the entire process will run
d) none of the mentioned
Answer: a
Explanation: None.
4. In the Many to One model, multiple threads are unable to run in parallel on multiprocessors because of ________
___
a) only one thread can access the kernel at a time
b) many user threads have access to just one kernel thread
c) there is only one kernel thread
d) none of the mentioned
Answer: a
Explanation: None.
5. The One to One model allows ___________
a) increased concurrency
b) decreased concurrency
c) increased or decreased concurrency
d) concurrency equivalent to other models
Answer: a
Explanation: None.
6. In the One to One model when a thread makes a blocking system call ___________
a) other threads are strictly prohibited from running
b) other threads are allowed to run
c) other threads only from other processes are allowed to run
d) none of the mentioned
Answer: b
Explanation: None.
7. Which of the following is the drawback of the One to One Model?
a) increased concurrency provided by this model
b) decreased concurrency provided by this model
c) creating so many threads at once can crash the system
d) creating a user thread requires creating the corresponding kernel thread
Answer: d
Explanation: None.
8. When is the Many to One model at an advantage?
a) When the program does not need multithreading
b) When the program has to be multi-threaded
c) When there is a single processor
d) None of the mentioned
Answer: a
Explanation: None.
9. In the Many to Many model true concurrency cannot be gained because ___________
a) the kernel can schedule only one thread at a time
b) there are too many threads to handle
c) it is hard to map threads with each other
d) none of the mentioned
Answer: a
Explanation: None.
10. In the Many to Many models when a thread performs a blocking system call ___________
a) other threads are strictly prohibited from running
b) other threads are allowed to run
c) other threads only from other processes are allowed to run
d) none of the mentioned
Answer: b
Explanation: None.
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1. Signals that occur at the same time, are presented to the process ____________
a) one at a time, in a particular order
b) one at a time, in no particular order
c) all at a time
d) none of the mentioned
Answer: b
Explanation: None.
2. Which of the following is not TRUE?
a) Processes may send each other signals
b) Kernel may send signals internally
c) A field is updated in the signal table when the signal is sent
d) Each signal is maintained by a single bit
Answer: c
Explanation: A field is updated in the process table when the signal is sent.
1. Virtual memory allows ____________
a) execution of a process that may not be completely in memory
b) a program to be smaller than the physical memory
c) a program to be larger than the secondary storage
d) execution of a process without being in physical memory
Answer: a
Explanation: None.
2. The instruction being executed, must be in ____________
a) physical memory
b) logical memory
c) physical & logical memory
d) none of the mentioned
Answer: a
Explanation: None.
3. Error handler codes, to handle unusual errors are ____________
a) almost never executed
b) executed very often
c) executed periodically
d) none of the mentioned
Answer: a
Explanation: None.
4. The ability to execute a program that is only partially in memory has benefits like ____________
a) The amount of physical memory cannot put a constraint on the program
b) Programs for an extremely large virtual space can be created
c) Throughput increases
d) All of the mentioned
Answer: d
Explanation: None.
5. In virtual memory. the programmer __________ of overlays.
a) has to take care
b) does not have to take care
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: None.
6. Virtual memory is normally implemented by ________
a) demand paging
b) buses
c) virtualization
d) all of the mentioned
Answer: a
Explanation: None.
7. Segment replacement algorithms are more complex than page replacement algorithms because ____________
a) Segments are better than pages
b) Pages are better than segments
c) Segments have variable sizes
d) Segments have fixed sizes
Answer: c
Explanation: None.
8. A swapper manipulates ___________ whereas the pager is concerned with individual _______ of a process.
a) the entire process, parts
b) all the pages of a process, segments
c) the entire process, pages
d) none of the mentioned
Answer: c
Explanation: None.
9. Using a pager ____________
a) increases the swap time
b) decreases the swap time
c) decreases the swap time & amount of physical memory needed
d) increases the amount of physical memory needed
Answer: c
Explanation: None.
10. The valid – invalid bit, in this case, when valid indicates?
a) the page is not legal
b) the page is illegal
c) the page is in memory
d) the page is not in memory
Answer: c
Explanation: None.
11. A page fault occurs when?
a) a page gives inconsistent data
b) a page cannot be accessed due to its absence from memory
c) a page is invisible
d) all of the mentioned
Answer: b
Explanation: None.
12. When a page fault occurs, the state of the interrupted process is ____________
a) disrupted
b) invalid
c) saved
d) none of the mentioned
Answer: c
Explanation: None.
13. When a process begins execution with no pages in memory?
a) process execution becomes impossible
b) a page fault occurs for every page brought into memory
c) process causes system crash
d) none of the mentioned
Answer: b
Explanation: None.
14. If the memory access time is denoted by ‘ma’ and ‘p’ is the probability of a page fault (0 <= p <= 1). Then the ef
fective access time for a demand paged memory is ____________
a) p x ma + (1-p) x page fault time
b) ma + page fault time
c) (1-p) x ma + p x page fault time
d) none of the mentioned
Answer: c
Explanation: None.
15. When the page fault rate is low ____________
a) the turnaround time increases
b) the effective access time increases
c) the effective access time decreases
d) turnaround time & effective access time increases
Answer: c
Explanation: None.
16. Locality of reference implies that the page reference being made by a process ____________
a) will always be to the page used in the previous page reference
b) is likely to be one of the pages used in the last few page references
c) will always be one of the pages existing in memory
d) will always lead to page faults
Answer: b
Explanation: None.
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1. Which of the following page replacement algorithms suffers from Belady’s Anomaly?
a) Optimal replacement
b) LRU
c) FIFO
d) Both optimal replacement and FIFO
Answer: c
Explanation: None.
2. A process refers to 5 pages, A, B, C, D, E in the order : A, B, C, D, A, B, E, A, B, C, D, E. If the page replacemen
t algorithm is FIFO, the number of page transfers with an empty internal store of 3 frames is?
a) 8
b) 10
c) 9
d) 7
Answer: c
Explanation: None.
3. In question 2, if the number of page frames is increased to 4, then the number of page transfers ____________
a) decreases
b) increases
c) remains the same
d) none of the mentioned
Answer: b
Explanation: None.
4. A memory page containing a heavily used variable that was initialized very early and is in constant use is remove
d, then the page replacement algorithm used is ____________
a) LRU
b) LFU
c) FIFO
d) None of the mentioned
Answer: c
Explanation: None.
5. A virtual memory system uses First In First Out (FIFO) page replacement policy and allocates a fixed number of f
rames to a process. Consider the following statements.
a) Both P and Q are true, and Q is the reason for P
b) Both P and Q are true, but Q is not the reason for P
c) P is false but Q is true
d) Both P and Q are false
Answer: c
Explanation: None.
6. Users _______ that their processes are running on a paged system.
a) are aware
b) are unaware
c) may unaware
d) none of the mentioned
Answer: b
Explanation: None.
7. If no frames are free, _____ page transfer(s) is/are required.
a) one
b) two
c) three
d) four
Answer: b
Explanation: None.
8. When a page is selected for replacement, and its modify bit is set ____________
a) the page is clean
b) the page has been modified since it was read in from the disk
c) the page is dirty
d) the page has been modified since it was read in from the disk & page is dirty
Answer: d
Explanation: None.
9. The aim of creating page replacement algorithms is to ____________
a) replace pages faster
b) increase the page fault rate
c) decrease the page fault rate
d) to allocate multiple pages to processes
Answer: c
Explanation: None.
10. A FIFO replacement algorithm associates with each page the _______
a) time it was brought into memory
b) size of the page in memory
c) page after and before it
d) all of the mentioned
Answer: a
Explanation: None.
11. What is the Optimal page – replacement algorithm?
a) Replace the page that has not been used for a long time
b) Replace the page that has been used for a long time
c) Replace the page that will not be used for a long time
d) None of the mentioned
Answer: c
Explanation: None.
12. Optimal page – replacement algorithm is difficult to implement, because ____________
a) it requires a lot of information
b) it requires future knowledge of the reference string
c) it is too complex
d) it is extremely expensive
Answer: b
Explanation: None.
13. LRU page – replacement algorithm associates with each page the ______
a) time it was brought into memory
b) the time of that page’s last use
c) page after and before it
d) all of the mentioned
Answer: b
Explanation: None.
14. For 3 page frames, the following is the reference string:
a) 10
b) 15
c) 11
d) 12
Answer: d
Explanation: None.
15. What are the two methods of the LRU page replacement policy that can be implemented in hardware?
a) Counters
b) RAM & Registers
c) Stack & Counters
d) Registers
Answer: c
Explanation: None.
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1. When using counters to implement LRU, we replace the page with the ____________
a) smallest time value
b) largest time value
c) greatest size
d) none of the mentioned
Answer: a
Explanation: Whenever a reference to a page is made, the contents of the clock register are copied into the time-of-u
se field in the page-table entry for that page. In this way, we always have the time of the last reference to each page.
2. In the stack implementation of the LRU algorithm, a stack can be maintained in a manner ____________
a) whenever a page is used, it is removed from the stack and put on bottom
b) the bottom of the stack is the LRU page
c) the top of the stack contains the LRU page and all new pages are added to the top
d) none of the mentioned
Answer: b
Explanation: None.
3. There is a set of page replacement algorithms that can never exhibit Belady’s Anomaly, called ____________
a) queue algorithms
b) stack algorithms
c) string algorithms
d) none of the mentioned
Answer: b
Explanation: None.
4. Applying the LRU page replacement to the following reference string.
a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: None.
5. Increasing the RAM of a computer typically improves performance because ____________
a) Virtual memory increases
b) Larger RAMs are faster
c) Fewer page faults occur
d) None of the mentioned
Answer: c
Explanation: None.
6. The essential content(s) in each entry of a page table is/are ____________
a) Virtual page number
b) Page frame number
c) Both virtual page number and page frame number
d) Access right information
Answer: b
Explanation: None.
7. The minimum number of page frames that must be allocated to a running process in a virtual memory environmen
t is determined by ____________
a) the instruction set architecture
b) page size
c) physical memory size
d) number of processes in memory
Answer: a
Explanation: None.
8. What is the reason for using the LFU page replacement algorithm?
a) an actively used page should have a large reference count
b) a less used page has more chances to be used again
c) it is extremely efficient and optimal
d) all of the mentioned
Answer: a
Explanation: None.
9. What is the reason for using the MFU page replacement algorithm?
a) an actively used page should have a large reference count
b) a less used page has more chances to be used again
c) it is extremely efficient and optimal
d) all of the mentioned
Answer: b
Explanation: None.
10. The implementation of the LFU and the MFU algorithm is very uncommon because ____________
a) they are too complicated
b) they are optimal
c) they are expensive
d) all of the mentioned
Answer: c
Explanation: None.
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1. The minimum number of frames to be allocated to a process is decided by the ____________
a) the amount of available physical memory
b) operating System
c) instruction set architecture
d) none of the mentioned
Answer: c
Explanation: None.
2. When a page fault occurs before an executing instruction is complete if ____________
a) the instruction must be restarted
b) the instruction must be ignored
c) the instruction must be completed ignoring the page fault
d) none of the mentioned
Answer: a
Explanation: None.
3. Consider a machine in which all memory reference instructions have only one memory address, for them we need
at least _____ frame(s).
a) one
b) two
c) three
d) none of the mentioned
Answer: b
Explanation: At least one frame for the instruction and one for the memory reference.
4. The maximum number of frames per process is defined by ____________
a) the amount of available physical memory
b) operating System
c) instruction set architecture
d) none of the mentioned
Answer: a
Explanation: None.
5. The algorithm in which we split m frames among n processes, to give everyone an equal share, m/n frames is kno
wn as ____________
a) proportional allocation algorithm
b) equal allocation algorithm
c) split allocation algorithm
d) none of the mentioned
Answer: b
Explanation: None.
6. The algorithm in which we allocate memory to each process according to its size is known as ____________
a) proportional allocation algorithm
b) equal allocation algorithm
c) split allocation algorithm
d) none of the mentioned
Answer: a
Explanation: None.
7. With either equal or proportional algorithm, a high priority process is treated ___________ a low priority process.
a) greater than
b) same as
c) lesser than
d) none of the mentioned
Answer: b
Explanation: None.
8. _________ replacement allows a process to select a replacement frame from the set of all frames, even if the fram
e is currently allocated to some other process.
a) Local
b) Universal
c) Global
d) Public
Answer: c
Explanation: None.
9. _________ replacement allows each process to only select from its own set of allocated frames.
a) Local
b) Universal
c) Global
d) Public
Answer: a
Explanation: None.
10. One problem with the global replacement algorithm is that ____________
a) it is very expensive
b) many frames can be allocated to a process
c) only a few frames can be allocated to a process
d) a process cannot control its own page – fault rate
Answer: d
Explanation: None.
11. ________ replacement generally results in greater system throughput.
a) Local
b) Global
c) Universal
d) Public
Answer: b
Explanation: None.
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1. A process is thrashing if ____________
a) it spends a lot of time executing, rather than paging
b) it spends a lot of time paging than executing
c) it has no memory allocated to it
d) none of the mentioned
Answer: b
Explanation: None.
2. Thrashing _______ the CPU utilization.
a) increases
b) keeps constant
c) decreases
d) none of the mentioned
Answer: c
Explanation: None.
3. What is a locality?
a) a set of pages that are actively used together
b) a space in memory
c) an area near a set of processes
d) none of the mentioned
Answer: a
Explanation: None.
4. When a subroutine is called ____________
a) it defines a new locality
b) it is in the same locality from where it was called
c) it does not define a new locality
d) none of the mentioned
Answer: a
Explanation: None.
5. A program is generally composed of several different localities, which _____ overlap.
a) may
b) must
c) do not
d) must not
Answer: a
Explanation: None.
6. In the working set model, for:
a) {1, 2, 4, 5, 6}
b) {2, 1, 6, 7, 3}
c) {1, 6, 5, 7, 2}
d) {1, 2, 3, 4, 5}
Answer: c
Explanation: None.
7. The accuracy of the working set depends on the selection of ____________
a) working set model
b) working set size
c) memory size
d) number of pages in memory
Answer: b
Explanation: None.
8. If working set window is too small ____________
a) it will not encompass entire locality
b) it may overlap several localities
c) it will cause memory problems
d) none of the mentioned
Answer: a
Explanation: None.
9. If working set window is too large ____________
a) it will not encompass entire locality
b) it may overlap several localities
c) it will cause memory problems
d) none of the mentioned
Answer: b
Explanation: None.
10. If the sum of the working – set sizes increases, exceeding the total number of available frames ____________
a) then the process crashes
b) the memory overflows
c) the system crashes
d) the operating system selects a process to suspend
Answer: d
Explanation: None.
11. Consider the following page reference string.
a) 10
b) 14
c) 8
d) 11
Answer: a
Explanation: None.
12. Consider the following page reference string.
a) 10
b) 14
c) 8
d) 11
Answer: c
Explanation: None.
13. Consider the following page reference string.
a) 16
b) 15
c) 14
d) 11
Answer: a
Explanation: None.
14. Consider the following page reference string.
a) 16
b) 15
c) 14
d) 11
Answer: c
Explanation: None.
15. Consider the following page reference string.
a) 16
b) 15
c) 14
d) 11
Answer: d
Explanation: None.
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1. Data cannot be written to secondary storage unless written within a ______
a) file
b) swap space
c) directory
d) text format
Answer: a
Explanation: None.
2. File attributes consist of ____________
a) name
b) type
c) identifier
d) all of the mentioned
Answer: d
Explanation: None.
3. The information about all files is kept in ____________
a) swap space
b) operating system
c) seperate directory structure
d) none of the mentioned
Answer: c
Explanation: None.
4. A file is a/an _______ data type.
a) abstract
b) primitive
c) public
d) private
Answer: a
Explanation: None.
5. The operating system keeps a small table containing information about all open files called ____________
a) system table
b) open-file table
c) file table
d) directory table
Answer: b
Explanation: None.
6. In UNIX, what will the open system call return?
a) pointer to the entry in the open file table
b) pointer to the entry in the system wide table
c) a file to the process calling it
d) none of the mentioned
Answer: a
Explanation: None.
7. System wide table in UNIX contains process independent information such as ____________
a) location of file on disk
b) access dates
c) file size
d) all of the mentioned
Answer: d
Explanation: None.
8. The open file table has a/an _______ associated with each file.
a) file content
b) file permission
c) open count
d) close count
Answer: c
Explanation: open count indicates the number of processes that have the file open.
9. Which of the following are the two parts of the file name?
a) name & identifier
b) identifier & type
c) extension & name
d) type & extension
Answer: c
Explanation: None.
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1. The UNIX sytem uses a/an ________ stored at the beginning of a some files to indicate roughly the type of file.
a) identifier
b) extension
c) virtual number
d) magic number
Answer: d
Explanation: None.
2. The larger the block size, the ______ the internal fragmentation.
a) greater
b) lesser
c) same
d) none of the mentioned
Answer: a
Explanation: None.
3. In the sequential access method, information in the file is processed ____________
a) one disk after the other, record access doesnt matter
b) one record after the other
c) one text document after the other
d) none of the mentioned
Answer: b
Explanation: None.
4. Sequential access method ______ on random access devices.
a) works well
b) doesnt work well
c) maybe works well and doesnt work well
d) none of the mentioned
Answer: a
Explanation: None.
5. The direct access method is based on a ______ model of a file, as _____ allow random access to any file block.
a) magnetic tape, magnetic tapes
b) tape, tapes
c) disk, disks
d) all of the mentioned
Answer: c
Explanation: None.
6. For a direct access file ____________
a) there are restrictions on the order of reading and writing
b) there are no restrictions on the order of reading and writing
c) access is restricted permission wise
d) access is not restricted permission wise
Answer: b
Explanation: None.
7. A relative block number is an index relative to ____________
a) the beginning of the file
b) the end of the file
c) the last written position in file
d) none of the mentioned
Answer: a
Explanation: None.
8. The index contains ____________
a) names of all contents of file
b) pointers to each page
c) pointers to the various blocks
d) all of the mentioned
Answer: c
Explanation: None.
9. For large files, when the index itself becomes too large to be kept in memory?
a) index is called
b) an index is created for the index file
c) secondary index files are created
d) all of the mentioned
Answer: b
Explanation: None.
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1. To organise file systems on disk _______________
a) they are split into one or more partitions
b) information about files is added to each partition
c) they are made on different storage spaces
d) all of the mentioned
Answer: b
Explanation: None.
2. The directory can be viewed as a _________ that translates file names into their directory entries.
a) symbol table
b) partition
c) swap space
d) cache
Answer: a
Explanation: None.
3. What will happen in the single level directory?
a) All files are contained in different directories all at the same level
b) All files are contained in the same directory
c) Depends on the operating system
d) None of the mentioned
Answer: b
Explanation: None.
4. What will happen in the single level directory?
a) all directories must have unique names
b) all files must have unique names
c) all files must have unique owners
d) all of the mentioned
Answer: b
Explanation: None.
5. What will happen in the two level directory structure?
a) each user has his/her own user file directory
b) the system doesn’t its own master file directory
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: None.
6. When a user job starts in a two level directory system, or a user logs in _____________
a) the users user file directory is searched
b) the system’s master file directory is not searched
c) the master file directory is indexed by user name or account number, and each entry points to the UFD for that use
r
d) all of the mentioned
Answer: c
Explanation: None.
7. When a user refers to a particular file?
a) system MFD is searched
b) his own UFD is not searched
c) both MFD and UFD are searched
d) every directory is searched
Answer: c
Explanation: None.
8. What is the disadvantage of the two level directory structure?
a) it does not solve the name collision problem
b) it solves the name collision problem
c) it does not isolate users from one another
d) it isolates users from one another
Answer: d
Explanation: None.
9. In the tree structured directories _____________
a) the tree has the stem directory
b) the tree has the leaf directory
c) the tree has the root directory
d) all of the mentioned
Answer: c
Explanation: None.
10. The current directory contains, most of the files that are _____________
a) of current interest to the user
b) stored currently in the system
c) not used in the system
d) not of current interest to the system
Answer: a
Explanation: None.
11. Which of the following are the types of Path names?
a) absolute & relative
b) local & global
c) global & relative
d) relative & local
Answer: a
Explanation: None.
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1. An absolute path name begins at the _____________
a) leaf
b) stem
c) current directory
d) root
Answer: d
Explanation: None.
2. A relative path name begins at the _____________
a) leaf
b) stem
c) current directory
d) root
Answer: c
Explanation: None.
3. In a tree structure, when deleting a directory that is not empty?
a) The contents of the directory are safe
b) The contents of the directory are also deleted
c) contents of the directory are not deleted
d) none of the mentioned
Answer: b
Explanation: None.
4. When two users keep a subdirectory in their own directories, the structure being referred to is _____________
a) tree structure
b) cyclic graph directory structure
c) two level directory structure
d) acyclic graph directory
Answer: d
Explanation: None.
5. A tree structure ______ the sharing of files and directories.
a) allows
b) may restrict
c) restricts
d) none of the mentioned
Answer: c
Explanation: None.
6. With a shared file _____________
a) actual file exists
b) there are two copies of the file
c) the changes made by one person are not reflected to the other
d) the changes made by one person are reflected to the other
Answer: d
Explanation: None.
7. In UNIX, what is a link?
a) a directory entry
b) a pointer to another file or subdirectory
c) implemented as an absolute or relative path name
d) all of the mentioned
Answer: d
Explanation: None.
8. The operating system _______ the links when traversing directory trees, to preserve the acyclic structure of the sy
stem.
a) considers
b) ignores
c) deletes
d) none of the mentioned
Answer: b
Explanation: None.
9. The deletion of a link ________ the original file.
a) deletes
b) affects
c) does not affect
d) none of the mentioned
Answer: c
Explanation: None.
10. When keeping a list of all the links/references to a file, and the list is empty, implies that _____________
a) the file has no copies
b) the file is deleted
c) the file is hidden
d) none of the mentioned
Answer: b
Explanation: None.
11. When a cycle exists, the reference count maybe non zero, even when it is no longer possible to refer to a director
y or file, due to _______
a) the possibility of one hidden reference
b) the possibility of two hidden references
c) the possibility of self referencing
d) none of the mentioned
Answer: c
Explanation: None.
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1. What is the mount point?
a) an empty directory at which the mounted file system will be attached
b) a location where every time file systems are mounted
c) is the time when the mounting is done
d) none of the mentioned
Answer: a
Explanation: None.
2. When a file system is mounted over a directory that is not empty then _____________
a) the system may not allow the mount
b) the system must allow the mount
c) the system may allow the mount and the directory’s existing files will then be made obscure
d) all of the mentioned
Answer: c
Explanation: None.
3. In UNIX, exactly which operations can be executed by group members and other users is definable by _________
____
a) the group’s head
b) the file’s owner
c) the file’s permissions
d) all of the mentioned
Answer: b
Explanation: None.
4. A process _____ lower the priority of another process if both are owned by the same owner.
a) must
b) can
c) cannot
d) none of the mentioned
Answer: b
Explanation: None.
5. In distributed file system ________________ directories are visible from the local machine.
a) protected
b) local
c) private
d) remote
Answer: d
Explanation: None.
6. In the world wide web, a ____ is needed to gain access to the remote files, and separate operations are used to tran
sfer files.
a) laptop
b) plugin
c) browser
d) player
Answer: c
Explanation: None.
7. Anonymous access allows a user to transfer files _____________
a) without having an account on the remote system
b) only if he accesses the system with a guest account
c) only if he has an account on the remote system
d) none of the mentioned
Answer: a
Explanation: The world wide web uses anonymous file exchange almost exclusively.
8. The machine containing the files is the _______ and the machine wanting to access the files is the ______
a) master, slave
b) memory, user
c) server, client
d) none of the mentioned
Answer: c
Explanation: None.
9. Distributed naming services/Distributed information systems have been devised to _____________
a) provide information about all the systems
b) provide unified access to the information needed for remote computing
c) provide unique names to all systems in a network
d) all of the mentioned
Answer: b
Explanation: None.
10. Domain name system provides _____________
a) host-name-to-network-address translations for the entire internet
b) network-address-to-host-name translations for the entire internet
c) binary to hex translations for the entire internet
d) all of the mentioned
Answer: a
Explanation: None.
11. To recover from failures in the network operations _____________ information may be maintained.
a) ip address
b) state
c) stateless
d) operating system
Answer: b
Explanation: None.
12. The series of accesses between the open and close operations is a _____________
a) transaction
b) procedure
c) program
d) file session
Answer: d
Explanation: None.
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1. Reliability of files can be increased by _____________
a) keeping the files safely in the memory
b) making a different partition for the files
c) by keeping them in external storage
d) by keeping duplicate copies of the file
Answer: d
Explanation: None.
2. Protection is only provided at the _____ level.
a) lower
b) central
c) higher
d) none of the mentioned
Answer: a
Explanation: None.
3. What is the main problem with access control lists?
a) their maintenance
b) their length
c) their permissions
d) all of the mentioned
Answer: b
Explanation: None.
4. Many systems recognize three classifications of users in connection with each file (to condense the access control
list).
a) Owner
b) Group
c) Universe
d) All of the mentioned
Answer: d
Explanation: None.
5. All users in a group get _______ access to a file.
a) different
b) similar
c) same
d) none of the mentioned
Answer: b
Explanation: None.
6. Universe consists of _____________
a) all users that aren’t included in the group or owners
b) all users that are not owners
c) all users in the system
d) none of the mentioned
Answer: c
Explanation: None.
7. In UNIX, groups can be created and modified by?
a) superuser
b) any user
c) a programmer only
d) the people in the group only
Answer: a
Explanation: None.
8. To control access the three bits used in UNIX are represented by _____________
a) r
b) w
c) x
d) all of the mentioned
Answer: d
Explanation: None.
9. If each access to a file is controlled by a password, then what is the disadvantage?
a) user will need to remember a lot of passwords
b) it is not reliable
c) it is not efficient
d) all of the mentioned
Answer: a
Explanation: None.
10. What will happen in a multi level directory structure?
a) the same previous techniques will be used as in the other structures
b) a mechanism for directory protection will have to applied
c) the subdirectories do not need protection once the directory is protected
d) none of the mentioned
Answer: b
Explanation: None.
11. In UNIX, the directory protection is handled _________ to the file protection.
a) different
b) similar
c) it is not handled at all
d) none of the mentioned
Answer: b
Explanation: None.
12. Disks are segmented into one or more partitions, each containing a file system or ______
a) left ‘raw’
b) made into swap space
c) made into backup space
d) left ‘ripe’
Answer: a
Explanation: None.
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1. The three major methods of allocating disk space that are in wide use are _____________
a) contiguous
b) linked
c) indexed
d) all of the mentioned
Answer: d
Explanation: None.
2. In contiguous allocation _____________
a) each file must occupy a set of contiguous blocks on the disk
b) each file is a linked list of disk blocks
c) all the pointers to scattered blocks are placed together in one location
d) none of the mentioned
Answer: a
Explanation: None.
3. In linked allocation _____________
a) each file must occupy a set of contiguous blocks on the disk
b) each file is a linked list of disk blocks
c) all the pointers to scattered blocks are placed together in one location
d) none of the mentioned
Answer: b
Explanation: None.
4. In indexed allocation _____________
a) each file must occupy a set of contiguous blocks on the disk
b) each file is a linked list of disk blocks
c) all the pointers to scattered blocks are placed together in one location
d) none of the mentioned
Answer: c
Explanation: None.
5. On systems where there are multiple operating system, the decision to load a particular one is done by _________
____
a) boot loader
b) bootstrap
c) process control block
d) file control block
Answer: a
Explanation: None.
6. The VFS (virtual file system) activates file system specific operations to handle local requests according to their _
______
a) size
b) commands
c) timings
d) file system types
Answer: d
Explanation: None.
7. What is the real disadvantage of a linear list of directory entries?
a) size of the linear list in memory
b) linear search to find a file
c) it is not reliable
d) all of the mentioned
Answer: b
Explanation: None.
8. Contiguous allocation of a file is defined by _____________
a) disk address of the first block & length
b) length & size of the block
c) size of the block
d) total size of the file
Answer: a
Explanation: None.
9. One difficulty of contiguous allocation is _____________
a) finding space for a new file
b) inefficient
c) costly
d) time taking
Answer: a
Explanation: None.
10. _______ and ________ are the most common strategies used to select a free hole from the set of available holes.
a) First fit, Best fit
b) Worst fit, First fit
c) Best fit, Worst fit
d) None of the mentioned
Answer: a
Explanation: None.
11. The first fit and best fit algorithms suffer from _____________
a) internal fragmentation
b) external fragmentation
c) starvation
d) all of the mentioned
Answer: b
Explanation: None.
12. To solve the problem of external fragmentation ________ needs to be done periodically.
a) compaction
b) check
c) formatting
d) replacing memory
Answer: a
Explanation: None.
13. If too little space is allocated to a file _____________
a) the file will not work
b) there will not be any space for the data, as the FCB takes it all
c) the file cannot be extended
d) the file cannot be opened
Answer: c
Explanation: None.
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1. A device driver can be thought of like a translator. Its input consists of _____ commands and output consists of _
______ instructions.
a) high level, low level
b) low level, high level
c) complex, simple
d) low level, complex
Answer: a
Explanation: None.
2. The file organization module knows about _____________
a) files
b) logical blocks of files
c) physical blocks of files
d) all of the mentioned
Answer: d
Explanation: None.
3. Metadata includes _____________
a) all of the file system structure
b) contents of files
c) both file system structure and contents of files
d) none of the mentioned
Answer: c
Explanation: None.
4. For each file there exists a ___________ that contains information about the file, including ownership, permission
s and location of the file contents.
a) metadata
b) file control block
c) process control block
d) all of the mentioned
Answer: b
Explanation: None.
5. For processes to request access to file contents, they need _____________
a) to run a seperate program
b) special interrupts
c) to implement the open and close system calls
d) none of the mentioned
Answer: c
Explanation: None.
6. During compaction time, other normal system operations _______ be permitted.
a) can
b) cannot
c) is
d) none of the mentioned
Answer: b
Explanation: None.
7. When in contiguous allocation the space cannot be extended easily?
a) the contents of the file have to be copied to a new space, a larger hole
b) the file gets destroyed
c) the file will get formatted and lost all its data
d) none of the mentioned
Answer: a
Explanation: None.
8. In the linked allocation, the directory contains a pointer to which block?
a) I only
b) II only
c) Both I and II
d) Neither I nor II
Answer: c
Explanation: None.
9. There is no __________ with linked allocation.
a) internal fragmentation
b) external fragmentation
c) starvation
d) all of the mentioned
Answer: b
Explanation: None.
10. What is the major disadvantage with a linked allocation?
a) internal fragmentation
b) external fragmentation
c) there is no sequential access
d) there is only sequential access
Answer: d
Explanation: None.
11. What if a pointer is lost or damaged in a linked allocation?
a) the entire file could get damaged
b) only a part of the file would be affected
c) there would not be any problems
d) none of the mentioned
Answer: a
Explanation: None.
12. FAT stands for _____________
a) File Attribute Transport
b) File Allocation Table
c) Fork At Time
d) None of the mentioned
Answer: b
Explanation: None.
13. By using FAT, random access time is __________
a) the same
b) increased
c) decreased
d) not affected
Answer: c
Explanation: None.
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1. A better way of contiguous allocation to extend the file size is _____________
a) adding an extent (another chunk of contiguous space)
b) adding an index table to the first contiguous block
c) adding pointers into the first contiguous block
d) none of the mentioned
Answer: a
Explanation: None.
2. If the extents are too large, then what is the problem that comes in?
a) internal fragmentation
b) external fragmentation
c) starvation
d) all of the mentioned
Answer: a
Explanation: None.
3. The FAT is used much as a _________
a) stack
b) linked list
c) data
d) pointer
Answer: b
Explanation: None.
4. A section of disk at the beginning of each partition is set aside to contain the table in _____________
a) fat
b) linked allocation
c) hashed allocation
d) indexed allocation
Answer: a
Explanation: None.
5. Contiguous allocation has two problems _________ and _________ that linked allocation solves.
a) external – fragmentation & size – declaration
b) internal – fragmentation & external – fragmentation
c) size – declaration & internal – fragmentation
d) memory – allocation & size – declaration
Answer: a
Explanation: None.
6. Each _______ has its own index block.
a) partition
b) address
c) file
d) all of the mentioned
Answer: c
Explanation: None.
7. Indexed allocation _________ direct access.
a) supports
b) does not support
c) is not related to
d) none of the mentioned
Answer: a
Explanation: None.
8. The pointer overhead of indexed allocation is generally _________ the pointer overhead of linked allocation.
a) less than
b) equal to
c) greater than
d) keeps varying with
Answer: c
Explanation: None.
9. For any type of access, contiguous allocation requires ______ access to get a disk block.
a) only one
b) at least two
c) exactly two
d) none of the mentioned
Answer: a
Explanation: We can easily keep the initial address of the file in memory and calculate immediately the disk address
of the ith block and read it directly.
10. Consider a disk where blocks 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 17, 18, 25, 26 and 27 are free and the rest of the bloc
ks are allocated. Then the free space bitmap would be _____________
a) 10000110000001110011111100011111…
b) 110000110000001110011111100011111…
c) 01111001111110001100000011100000…
d) 001111001111110001100000011100000…
Answer: d
Explanation: None.
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1. _______ tend to represent a major bottleneck in system performance.
a) CPUs
b) Disks
c) Programs
d) I/O
Answer: b
Explanation: None.
2. In UNIX, even an ’empty’ disk has a percentage of its space lost to ______
a) programs
b) inodes
c) virtual memory
d) stacks
Answer: b
Explanation: None.
3. By preallocating the inodes and spreading them across the volume, we ___________ the system performance.
a) improve
b) decrease
c) maintain
d) do not affect
Answer: a
Explanation: None.
4. ____________ writes occur in the order in which the disk subsystem receives them, and the writes are not buffere
d.
a) Asynchronous
b) Regular
c) Synchronous
d) Irregular
Answer: c
Explanation: None.
5. In ___________ writes, the data is stored in the cache.
a) Asynchronous
b) Regular
c) Synchronous
d) Irregular
Answer: a
Explanation: None.
6. A file being read or written sequentially should not have its pages replaced in LRU order, because ____________
_
a) it is very costly
b) the most recently used page will be used last
c) it is not efficient
d) all of the mentioned
Answer: b
Explanation: None.
7. In the optimized technique for sequential access ___________ removes a page from the buffer as soon as the next
page is requested.
a) write ahead
b) read ahead
c) free-behind
d) add-front
Answer: c
Explanation: None.
8. With _______ a requested page and several subsequent pages are read and cached.
a) write ahead
b) read ahead
c) free-behind
d) add-front
Answer: b
Explanation: None.
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1. Some directory information is kept in main memory or cache to ___________
a) fill up the cache
b) increase free space in secondary storage
c) decrease free space in secondary storage
d) speed up access
Answer: d
Explanation: None.
2. A systems program such as fsck in ______ is a consistency checker.
a) UNIX
b) Windows
c) Macintosh
d) Solaris
Answer: a
Explanation: None.
3. A consistency checker __________________ and tries to fix any inconsistencies it finds.
a) compares the data in the secondary storage with the data in the cache
b) compares the data in the directory structure with the data blocks on disk
c) compares the system generated output and user required output
d) all of the mentioned
Answer: b
Explanation: None.
4. Each set of operations for performing a specific task is a _________
a) program
b) code
c) transaction
d) all of the mentioned
Answer: c
Explanation: None.
5. Once the changes are written to the log, they are considered to be ________
a) committed
b) aborted
c) completed
d) none of the mentioned
Answer: a
Explanation: None.
6. When an entire committed transaction is completed, ___________
a) it is stored in the memory
b) it is removed from the log file
c) it is redone
d) none of the mentioned
Answer: b
Explanation: None.
7. What is a circular buffer?
a) writes to the end of its space and then continues at the beginning
b) overwrites older values as it goes
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: None.
8. All the changes that were done from a transaction that did not commit before the system crashed, have to be ____
_____
a) saved
b) saved and the transaction redone
c) undone
d) none of the mentioned
Answer: c
Explanation: None.
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1. A machine in Network file system (NFS) can be ________
a) client
b) server
c) both client and server
d) neither client nor server
Answer: c
Explanation: None.
2. A _________ directory is mounted over a directory of a _______ file system.
a) local, remote
b) remote, local
c) local, local
d) none of the mentioned
Answer: d
Explanation: None.
3. The _________ becomes the name of the root of the newly mounted directory.
a) root of the previous directory
b) local directory
c) remote directory itself
d) none of the mentioned
Answer: b
Explanation: None.
4. ___________ mounts, is when a file system can be mounted over another file system, that is remotely mounted, n
ot local.
a) recursive
b) cascading
c) trivial
d) none of the mentioned
Answer: b
Explanation: None.
5. The mount mechanism ________ a transitive property.
a) exhibits
b) does not exhibit
c) may exhibit
d) none of the mentioned
Answer: b
Explanation: Mounting a remote file system does not give the client access to other file systems that were, by chance
, mounted over the former file system.
6. A mount operation includes the _____________
a) name of the network
b) name of the remote directory to be mounted
c) name of the server machine storing it
d) all of the mentioned
Answer: b
Explanation: None.
7. The mount request is mapped to the corresponding __________ and is forwarded to the mount server running on t
he specific server machine.
a) IPC
b) System
c) CPU
d) RPC
Answer: b
Explanation: None.
8. The server maintains a/an ________ that specifies local file systems that it exports for mounting, along with name
s of machines that are permitted to mount them.
a) export list
b) import list
c) sending list
d) receiving list
Answer: a
Explanation: None.
9. In UNIX, the file handle consists of a __________ and __________
a) file-system identifier & an inode number
b) an inode number & FAT
c) a FAT & an inode number
d) a file pointer & FAT
Answer: a
Explanation: None.
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1. The NFS servers ____________
a) are stateless
b) save the current state of the request
c) maybe stateless
d) none of the mentioned
Answer: a
Explanation: None.
2. Every NFS request has a _________ allowing the server to determine if a request is duplicated or if any are missi
ng.
a) name
b) transaction
c) sequence number
d) all of the mentioned
Answer: c
Explanation: None.
3. A server crash and recovery will __________ to a client.
a) be visible
b) affect
c) be invisible
d) harm
Answer: c
Explanation: All blocks that the server is managing for the client will be intact.
4. The server must write all NFS data ___________
a) synchronously
b) asynchronously
c) index-wise
d) none of the mentioned
Answer: a
Explanation: None.
5. A single NFS write procedure ____________
a) can be atomic
b) is atomic
c) is non atomic
d) none of the mentioned
Answer: b
Explanation: None.
6. The NFS protocol __________ concurrency control mechanisms.
a) provides
b) does not provide
c) may provide
d) none of the mentioned
Answer: b
Explanation: None.
7. _______________ in NFS involves the parsing of a path name into separate directory entries – or components.
a) Path parse
b) Path name parse
c) Path name translation
d) Path name parsing
Answer: c
Explanation: None.
8. For every pair of component and directory vnode after path name translation ____________
a) a single NFS lookup call is used sequentially
b) a single NFS lookup call is used beginning from the last component
c) at least two NFS lookup calls per component are performed
d) a separate NFS lookup call is performed
Answer: d
Explanation: None.
9. When a client has a cascading mount _______ server(s) is/are involved in a path name traversal.
a) at least one
b) more than one
c) more than two
d) more than three
Answer: b
Explanation: None.
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1. In _______ information is recorded magnetically on platters.
a) magnetic disks
b) electrical disks
c) assemblies
d) cylinders
Answer: a
Explanation: None.
2. The heads of the magnetic disk are attached to a _____ that moves all the heads as a unit.
a) spindle
b) disk arm
c) track
d) none of the mentioned
Answer: b
Explanation: None.
3. The set of tracks that are at one arm position make up a ___________
a) magnetic disks
b) electrical disks
c) assemblies
d) cylinders
Answer: d
Explanation: None.
4. The time taken to move the disk arm to the desired cylinder is called the ____________
a) positioning time
b) random access time
c) seek time
d) rotational latency
Answer: c
Explanation: None.
5. The time taken for the desired sector to rotate to the disk head is called ____________
a) positioning time
b) random access time
c) seek time
d) rotational latency
Answer: d
Explanation: None.
6. When the head damages the magnetic surface, it is known as _________
a) disk crash
b) head crash
c) magnetic damage
d) all of the mentioned
Answer: b
Explanation: None.
7. A floppy disk is designed to rotate ___________ as compared to a hard disk drive.
a) faster
b) slower
c) at the same speed
d) none of the mentioned
Answer: b
Explanation: None.
8. What is the host controller?
a) controller built at the end of each disk
b) controller at the computer end of the bus
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: None.
9. ______ controller sends the command placed into it, via messages to the _____ controller.
a) host, host
b) disk, disk
c) host, disk
d) disk, host
Answer: c
Explanation: None.
10. What is the disk bandwidth?
a) the total number of bytes transferred
b) total time between the first request for service and the completion on the last transfer
c) the total number of bytes transferred divided by the total time between the first request for service and the comple
tion on the last transfer
d) none of the mentioned
Answer: c
Explanation: None.
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1. Whenever a process needs I/O to or from a disk it issues a ______________
a) system call to the CPU
b) system call to the operating system
c) a special procedure
d) all of the mentioned
Answer: b
Explanation: None.
2. If a process needs I/O to or from a disk, and if the drive or controller is busy then ____________
a) the request will be placed in the queue of pending requests for that drive
b) the request will not be processed and will be ignored completely
c) the request will be not be placed
d) none of the mentioned
Answer: a
Explanation: None.
3. Consider a disk queue with requests for I/O to blocks on cylinders.
a) 600
b) 620
c) 630
d) 640
Answer: d
Explanation: None.
4. Consider a disk queue with requests for I/O to blocks on cylinders.
a) 224
b) 236
c) 245
d) 240
Answer: b
Explanation: None.
5. Random access in magnetic tapes is _________ compared to magnetic disks.
a) fast
b) very fast
c) slow
d) very slow
Answer: d
Explanation: None.
6. Magnetic tape drives can write data at a speed ________ disk drives.
a) much lesser than
b) comparable to
c) much faster than
d) none of the mentioned
Answer: b
Explanation: None.
7. On media that use constant linear velocity (CLV), the _____________ is uniform.
a) density of bits on the disk
b) density of bits per sector
c) the density of bits per track
d) none of the mentioned
Answer: c
Explanation: The farther a track is from the center of the disk.
8. SSTF algorithm, like SJF __________ of some requests.
a) may cause starvation
b) will cause starvation
c) does not cause starvation
d) causes aging
Answer: a
Explanation: None.
9. In the ______ algorithm, the disk arm starts at one end of the disk and moves toward the other end, servicing requ
ests till the other end of the disk. At the other end, the direction is reversed and servicing continues.
a) LOOK
b) SCAN
c) C-SCAN
d) C-LOOK
Answer: b
Explanation: None.
10. In the _______ algorithm, the disk head moves from one end to the other, servicing requests along the way. Whe
n the head reaches the other end, it immediately returns to the beginning of the disk without servicing any requests o
n the return trip.
a) LOOK
b) SCAN
c) C-SCAN
d) C-LOOK
Answer: c
Explanation: None.
11. In the ______ algorithm, the disk arm goes as far as the final request in each direction, then reverses direction im
mediately without going to the end of the disk.
a) LOOK
b) SCAN
c) C-SCAN
d) C-LOOK
Answer: a
Explanation: None.
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1. The process of dividing a disk into sectors that the disk controller can read and write, before a disk can store data i
s known as ____________
a) partitioning
b) swap space creation
c) low-level formatting
d) none of the mentioned
Answer: c
Explanation: None.
2. The data structure for a sector typically contains ____________
a) header
b) data area
c) trailer
d) all of the mentioned
Answer: d
Explanation: None.
3. The header and trailer of a sector contain information used by the disk controller such as _________ and _______
__
a) main section & disk identifier
b) error correcting codes (EC
c) & sector number
c) sector number & main section
d) disk identifier & sector number
Answer: b
Explanation: None.
4. The two steps the operating system takes to use a disk to hold its files are _______ and ________
a) partitioning & logical formatting
b) swap space creation & caching
c) caching & logical formatting
d) logical formatting & swap space creation
Answer: a
Explanation: None.
5. The _______ program initializes all aspects of the system, from CPU registers to device controllers and the conte
nts of main memory, and then starts the operating system.
a) main
b) bootloader
c) bootstrap
d) rom
Answer: c
Explanation: None.
6. For most computers, the bootstrap is stored in ________
a) RAM
b) ROM
c) Cache
d) Tertiary storage
Answer: b
Explanation: None.
7. A disk that has a boot partition is called a _________
a) start disk
b) end disk
c) boot disk
d) all of the mentioned
Answer: c
Explanation: None.
8. Defective sectors on disks are often known as __________
a) good blocks
b) destroyed blocks
c) bad blocks
d) none of the mentioned
Answer: c
Explanation: None.
9. In SCSI disks used in high end PCs, the controller maintains a list of _________ on the disk. The disk is initialize
d during ________ formatting which sets aside spare sectors not visible to the operating system.
a) destroyed blocks, high level formatting
b) bad blocks, partitioning
c) bad blocks, low level formatting
d) destroyed blocks, partitioning
Answer: c
Explanation: None.
10. The scheme used in the above question is known as _______ or ________
a) sector sparing & forwarding
b) forwarding & sector utilization
c) backwarding & forwarding
d) sector utilization & backwarding
Answer: a
Explanation: None.
11. An unrecoverable error is known as _________
a) hard error
b) tough error
c) soft error
d) none of the mentioned
Answer: a
Explanation: None.
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1. Virtual memory uses disk space as an extension of _________
a) secondary storage
b) main memory
c) tertiary storage
d) none of the mentioned
Answer: b
Explanation: None.
2. Using swap space significantly _________ system performance.
a) increases
b) decreases
c) maintains
d) does not affect
Answer: b
Explanation: Disk access is much slower than memory access.
3. Linux __________ the use of multiple swap spaces.
a) allows
b) does not allow
c) may allow
d) none of the mentioned
Answer: a
Explanation: Putting these swap spaces on separate disks reduces the load places on the I/O system.
4. A single swap space ______ reside in two places.
a) can
b) cannot
c) must not
d) none of the mentioned
Answer: a
Explanation: None.
5. If the swap space is simply a large file, within the file system, ____________ used to create it, name it and allocat
e its space.
a) special routines must be
b) normal file system routines can be
c) normal file system routines cannot be
d) swap space storage manager is
Answer: b
Explanation: None.
6. For swap space created in a separate disk partition where no file system or directory structure is placed, ________
_____ used to allocate and deallocate the blocks.
a) special routines must be
b) normal file system routines can be
c) normal file system routines cannot be
d) swap space storage manager is
Answer: d
Explanation: None.
7. When a fixed amount of swap space is created during disk partitioning, more swap space can be added only by?
a) only I
b) only II
c) both I and II
d) neither I nor II
Answer: c
Explanation: None.
8. In UNIX, two per process ________ are used by the kernel to track swap space use.
a) process tables
b) swap maps
c) memory maps
d) partition maps
Answer: b
Explanation: None.
9. It is __________ to reread a page from the file system than to write it to swap space and then to reread it from the
re.
a) useless
b) less efficient
c) more efficient
d) none of the mentioned
Answer: c
Explanation: None.
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1. A microcontroller at-least should consist of:
a) RAM, ROM, I/O ports and timers
b) CPU, RAM, I/O ports and timers
c) CPU, RAM, ROM, I/O ports and timers
d) CPU, ROM, I/O ports and timers
Answer: c
Explanation: A microcontroller at-least consists of a processor as its CPU with RAM, ROM, I/O ports and timers. It
may contain some additional peripherals like ADC, PWM, etc.
2. Unlike microprocessors, microcontrollers make use of batteries because they have:
a) high power dissipation
b) low power consumption
c) low voltage consumption
d) low current consumption
Answer: b
Explanation: Micro Controllers are made by using the concept of VLSI technology. So here, CMOS based logic gate
s are coupled together by this technique that consumes low power.
3. What is the order decided by a processor or the CPU of a controller to execute an instruction?
a) decode,fetch,execute
b) execute,fetch,decode
c) fetch,execute,decode
d) fetch,decode,execute
Answer: d
Explanation: First instruction is fetched from Program Memory. After fetching, instruction is decoded to generate co
ntrol signals to perform the intended task. After decoding, instruction is executed and the complete intended task of t
hat particular instruction.
4. If we say microcontroller is 8-bit then here 8-bit denotes size of:
a) Data Bus
b) ALU
c) Control Bus
d) Address Bus
Answer: b
Explanation: If we say a microcontroller is 8-bit it means that it is capable of processing 8-bit data at a time. Data pr
ocessing is the task of ALU and if ALU is able to process 8-bit data then the data bus should be 8-bit wide. In most
books it tells that size of data bus but to be precise it is the size of ALU because in Harvard Architecture there are tw
o sets of data bus which can be of same size but it is not mandatory.
5. How are the performance and the computer capability affected by increasing its internal bus width?
a) it increases and turns better
b) it decreases
c) remains the same
d) internal bus width doesn’t affect the performance in any way
Answer: a
Explanation: As the bus width increases, the number of bits carried by bus at a time increases as a result of which th
e total performance and computer capability increases.
6. Abbreviate CISC and RISC.
a) Complete Instruction Set Computer, Reduced Instruction Set Computer
b) Complex Instruction Set Computer, Reduced Instruction Set Computer
c) Complex Instruction Set Computer, Reliable Instruction Set Computer
d) Complete Instruction Set Computer, Reliable Instruction Set Computer
Answer: b
Explanation: CISC means Complete Instruction Set Computer because in this a microcontroller has an instruction se
t that supports many addressing modes for the arithmetic and logical instructions, data transfer and memory accesses
instructions. RISC means Reduced Instruction Set Computer because here a microcontroller has an instruction set t
hat supports fewer addressing modes for the arithmetic and logical instructions and for data transfer instructions.
7. Give the names of the buses present in a controller for transferring data from one place to another?
a) data bus, address bus
b) data bus
c) data bus, address bus, control bus
d) address bus
Answer: c
Explanation: There are 3 buses present in a microcontroller they are data bus (for carrying data from one place to an
other), address bus (for carrying the address to which the data will flow) and the control bus (which tells the controll
er to execute which type of work at that address may be it read or write operation).
8. What is the file extension that is loaded in a microcontroller for executing any instruction?
a) .doc
b) .c
c) .txt
d) .hex
Answer: d
Explanation: Microcontrollers are loaded with .hex extension as they understand the language of 0’s and 1’s only.
9. What is the most appropriate criterion for choosing the right microcontroller of our choice?
a) speed
b) availability
c) ease with the product
d) all of the mentioned
Answer: d
Explanation: For choosing the right microcontroller for our product we must consider its speed so that the instructio
ns may be executed in the least possible time. It also depends on the availability so that the particular product may b
e available in our neighboring regions or market in our need. It also depends on the compatibility with the product s
o that the best results may be obtained.
10. Why microcontrollers are not called general purpose computers?
a) because they have built in RAM and ROM
b) because they design to perform dedicated task
c) because they are cheap
d) because they consume low power
Answer: b
Explanation: Microcontrollers are designed to perform dedicated tasks. While designing general purpose computers
end use is not known to designers.
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1. How many types of architectures are available, for designing a device that is able to work on its own?
a) 3
b) 2
c) 1
d) 4
Answer: b
Explanation: There are basically two main types of architectures present, they are Von Neumann and Harvard archit
ectures.
2. Which architecture is followed by general purpose microprocessors?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: b
Explanation: General purpose microprocessors make use of Von Neumann architecture as here a simpler design is of
fered.
3. Which architecture involves both the volatile and the non volatile memory?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a
Explanation: In Harvard architecture, both the volatile and the non volatile memories are involved. This is done to in
crease its efficiency as both the memories are being used over here.
4. Which architecture provides separate buses for program and data memory?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a
Explanation: Harvard Architecture provides separated buses for data and program memory to fetch program and dat
a simultaneously. By doing this access time is reduced and hence performance is increased.
5. Which microcontroller doesn’t match with its architecture below?
a) Microchip PIC- Harvard
b) MSP430- Harvard
c) ARM7- Von Neumann
d) ARM9- Harvard
Answer: b
Explanation: MSP430 supports Von Neumann architecture.
6. Harvard architecture has _____________
a) dedicated buses for data and program memory
b) pipeline technique
c) complex architecture
d) all of the mentioned
Answer: d
Explanation: Harvard Architecture has dedicated buses for data and program memory and pipeline technique becaus
e of this architecture is complex.
7. Which out of the following supports Harvard architecture?
a) ARM7
b) Pentium
c) SHARC
d) All of the mentioned
Answer: c
Explanation: SHARC supports harvard architecture for signal processing in DSP.
8. Why most of the DSPs use Harvard architecture?
a) they provide greater bandwidth
b) they provide more predictable bandwidth
c) they provide greater bandwidth & also more predictable bandwidth
d) none of the mentioned
Answer: c
Explanation: Most of the DSPs use harvard architecture because they provide a wider predictable bandwidth.
9. Which of the following supports CISC as well as Harvard architecture?
a) ARM7
b) ARM9
c) SHARC
d) None of the mentioned
Answer: c
Explanation: SHARC supports both the CISC and the Harvard architecture.
10. Which of the two architecture saves memory?
a) Harvard
b) Von Neumann
c) Harvard & Von Neumann
d) None of the mentioned
Answer: b
Explanation: As only one memory is present in the Von Neumann architecture so it saves a lot of memory.
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1. 8051 microcontrollers are manufactured by which of the following companies?
a) Atmel
b) Philips
c) Intel
d) All of the mentioned
Answer: d
Explanation: 8051 microcontrollers are manufactured by Intel, Atmel, Philips/Signetics, Infineon, Dallas Semi/Maxi
m.
2. AT89C2051 has RAM of:
a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
Answer: a
Explanation: It has 128 bytes of RAM in it.
3. 8051 series has how many 16 bit registers?
a) 2
b) 3
c) 1
d) 0
Answer: a
Explanation: It has two 16 bit registers DPTR and PC.
4. When 8051 wakes up then 0x00 is loaded to which register?
a) PSW
b) SP
c) PC
d) None of the mentioned
Answer: c
Explanation: When 8051 wakes up, Program Counter (P
c) loaded with 0000H. Because of this in 8051 first opcode is stored in ROM address at 0000H.
5. When the microcontroller executes some arithmetic operations, then the flag bits of which register are affected?
a) PSW
b) SP
c) DPTR
d) PC
Answer: a
Explanation: It stands for program status word. It consists of carry, auxiliary carry, overflow, parity, register bank se
lect bits etc which are affected during such operations.
6. How are the status of the carry, auxiliary carry and parity flag affected if the write instruction
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
Answer: b
Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so CY and AC are set to 1. In t
he result, the number of 1’s present are even so parity flag is set to zero.
7. How are the bits of the register PSW affected if we select Bank2 of 8051?
a) PSW.5=0 and PSW.4=1
b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
Answer: d
Explanation: Bits of PSW register are CY, AC, F0, RS1, RS0, OV, -, P so for selecting bank2 RS1=1 and RS0=0 wh
ich are fourth and third bit of the register respectively.
8. If we push data onto the stack then the stack pointer
a) increases with every push
b) decreases with every push
c) increases & decreases with every push
d) none of the mentioned
Answer: a
Explanation: If we push elements onto the stack then the stack pointer increases with every push of element.
9. On power up, the 8051 uses which RAM locations for register R0- R7
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
Answer: b
Explanation: On power up register bank 0 is selected which has memory address from 00H-07H.
10. How many bytes of bit addressable memory is present in 8051 based microcontrollers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
Answer: c
Explanation: 8051 microcontrollers have 16 bytes of bit addressable memory.
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1. “DJNZ R0, label” is ________ byte instruction.
a) 2
b) 3
c) 1
d) Can’t be determined
Answer: a
Explanation: DJNZ is 2-byte instruction. This means jump can be of -128 to +127 locations with respect to PC. Here
-128 means upward or backward jump and +127 means downward or forward jump.
2. JZ, JNZ, instructions checked content of _______ register.
a) DPTR
b) B
c) A
d) PSW
Answer: c
Explanation: JZ and JNZ instructions checked the content of A register and if condition was satisfied or true then ju
mp to target address.
3. Calculate the jump code for again and here if code starts at 0000H
a) F3,02
b) F9,01
c) E9,01
d) E3,02
Answer: c
Explanation: Loop address is calculated by subtracting destination address and the address next to the source address
.
4. When the call instruction is executed the topmost element of stack comes out to be
a) the address where stack pointer starts
b) the address next to the call instruction
c) address of the call instruction
d) next address of the stack pointer
Answer: b
Explanation: The topmost element of the stack is the address of the instruction next to the call instruction so that wh
en RET is executed then PC is filled with that address and so the pointer moves to the main program and continue w
ith its routine task.
5. LCALL instruction takes
a) 2 bytes
b) 4 bytes
c) 3 bytes
d) 1 byte
Answer: c
Explanation: LCALL instruction moves the pointer to a 16 bit address so it is a 3 byte instruction.
6. Are PUSH and POP instructions are a type of CALL instructions?
a) yes
b) no
c) none of the mentioned
d) cant be determined
Answer: b
Explanation: PUSH and POP instructions are not CALL instructions because in POP and PUSH instructions the poi
nter does not move to any location specified by its address which is the fundamental of CALL instruction, so it is no
t a type of CALL instruction.
7. What is the time taken by one machine cycle if crystal frequency is 20MHz?
a) 1.085 micro seconds
b) 0.60 micro seconds
c) 0.75 micro seconds
d) 1 micro seconds
Answer: b
Explanation: Time taken by one machine cycle is calculated by the inverse of a (crystal frequency) /12
8. Find the number of times the following loop will be executed
a) 100
b) 200
c) 20000
d) 2000
Answer: c
Explanation: It will be executed 200*100 times.
9. What is the meaning of the instruction MOV A,05H?
a) data 05H is stored in the accumulator
b) fifth bit of accumulator is set to one
c) address 05H is stored in the accumulator
d) none of the mentioned
Answer: c
Explanation: If we need to store the address in the accumulator, then directly the address is moved to it unlikely of u
sing # used for storing data in any register.
10. Do the two instructions mean the same?
a) yes
b) no
c) cant be determined
d) yes and the second one is preferred
Answer: b
Explanation: In the first statement, when the decrements approach zero then the jump moves back and in the second
statement, when the result after decrements is not zero, then it jumps back.
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1. To initialize any port as an output port what value is to be given to it?
a) 0xFF
b) 0x00
c) 0x01
d) A port is by default an output port
Answer: d
Explanation: In 8051, a port is initialized by default in its output mode no need to pass any value to it.
2. Which out of the four ports of 8051 needs a pull-up resistor for using it is as an input or an output port?
a) PORT 0
b) PORT 1
c) PORT 2
d) PORT 3
Answer: a
Explanation: These pins are the open drain pins of the controller which means it needs a pull-up resistor for using it
as an input or an output ports.
3. Which of the ports act as the 16 bit address lines for transferring data through it?
a) PORT 0 and PORT 1
b) PORT 1 and PORT 2
c) PORT 0 and PORT 2
d) PORT 1 and PORT 3
Answer: c
Explanation: PORT 0 and PORT 2 are used as the 16 bit address lines where PORT0 act as lower bit address lines a
nd PORT 2 as higher bit address lines.
4. Which of the following registers are not bit addressable?
a) SCON
b) PCON
c) A
d) PSW
Answer: b
Explanation: PCON register is not a bit addressable register.
5. Which instruction is used to check the status of a single bit?
a) MOV A,P0
b) ADD A,#05H
c) JNB PO.0, label
d) CLR P0.05H
Answer: b
Explanation: JNB which stands for Jump if no bit checks the status of the bit P0.0 and jumps if the bit is 0.
6. Which addressing mode is used in pushing or popping any element on or from the stack?
a) immediate
b) direct
c) indirect
d) register
Answer: c
Explanation: If we want to push or pop any element on or from the stack then direct addressing mode has to be used
in it, as the other way is not accepted.
7. Which operator is the most important while assigning any instruction as register indirect instruction?
a) $
b) #
c) @
d) &
Answer: b
Explanation: In register, indirect mode data is copied at that location where R0 or R1 are present, so @ operator is u
sed ex. MOV @R0,A
8. What is the advantage of register indirect addressing mode?
a) it makes use of registers R0 and R1
b) it uses the data dynamically
c) it makes use of operator @
d) it is easy
Answer: b
Explanation: Register indirect addressing mode is useful if a series of data is to be assigned to that address, with the
help of this quality the number of instructions decreases as a result of which performance increases.
9. Which of the following comes under the indexed addressing mode?
a) MOVX A, @DPTR
b) MOVC @A+DPTR,A
c) MOV A,R0
d) MOV @R0,A
Answer: b
Explanation: Indexed addressing mode stands for that instruction where the bits of the accumulator is also indexed w
ith the 16 bit registers.
PSST! You better watch out, something's buggy above.
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1. When we add two numbers the destination address must always be.
a) some immediate data
b) any register
c) accumulator
d) memory
Answer: c
Explanation: For addition purposes, the destination address must always be an accumulator. Example- ADD A,R0;
ADD A, @R1; ADD A,@ DPTR
2. DAA command adds 6 to the nibble if:
a) CY and AC are necessarily 1
b) either CY or AC is 1
c) no relation with CY or AC
d) CY is 1
Answer: b
Explanation: DAA command adds 6 to the nibble if any of the nibbles becomes greater than 9.
3. If SUBB A,R4 is executed, then actually what operation is being applied?
a) R4+A
b) R4-A
c) A-R4
d) R4+A
Answer: c
Explanation: SUBB command subtracts with borrow the contents of an accumulator with that of the register or some
immediate value. So A-R4 is being executed.
4. A valid division instruction always makes:
a) CY=0,AC=1
b) CY=1,AC=1
c) CY=0,AC=0
d) no relation with AC and CY
Answer: c
Explanation: When we divide two numbers then AC and CY become zero.
5. In 8 bit signed number operations, OV flag is set to 1 if:
a) a carry is generated from D7 bit
b) a carry is generated from D3 bit
c) a carry is generated from D7 or D3 bit
d) a carry is generated from D7 or D6 bit
Answer: d
Explanation: In 8 bit operations, if a carry is generated from D6 or D7 bit, then OV flag is set to 1.
6. In unsigned number addition, the status of which bit is important?
a) OV
b) CY
c) AC
d) PSW
Answer: b
Explanation: If unsigned numbers operations are involved, then the status of CY flag is important and in signed num
ber operation the status of OV flag is important.
7. Which instructions have no effect on the flags of PSW?
a) ANL
b) ORL
c) XRL
d) All of the mentioned
Answer: d
Explanation: These instructions are the arithmetic operations and the flags are affected by the data copy instructions,
so all these instructions don’t affect the bits of the flag.
8. ANL instruction is used _______
a) to AND the contents of the two registers
b) to mask the status of the bits
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: ANL instruction is used to AND the contents of the two registers and is also used to mask the status of
the bits of the register.
9. CJNE instruction makes _______
a) the pointer to jump if the values of the destination and the source address are equal
b) sets CY=1, if the contents of the destination register are greater then that of the source register
c) sets CY=0, if the contents of the destination register are smaller then that of the source register
d) none of the mentioned
Answer: d
Explanation: In CJNE command, the pointer jumps if the values of the two registers are not equal and it resets CY if
the destination address is larger then the source address and sets CY if the destination address is smaller then the so
urce address.
10. XRL, ORL, ANL commands have _______
a) accumulator as the destination address and any register, memory or any immediate data as the source address
b) accumulator as the destination address and any immediate data as the source address
c) any register as the destination address and accumulator, memory or any immediate data as the source address
d) any register as the destination address and any immediate data as the source address
Answer: a
Explanation: These commands have accumulator as the destination address and any register, memory or any immedi
ate data as the source address.
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1. What is the clock source for the timers?
a) some external crystal applied to the micro-controller for executing the timer
b) from the crystal applied to the micro-controller
c) through the software
d) through programming
Answer: b
Explanation: Timer’s clock source is the crystal that is applied to the controller.
2. What is the frequency of the clock that is being used as the clock source for the timer?
a) some externally applied frequency f’
b) controller’s crystal frequency f
c) controller’s crystal frequency /12
d) externally applied frequency/12
Answer: c
Explanation: The frequency of the clock source for the timer is equal to f/12(where f is the frequency of the crystal).
3. What is the function of the TMOD register?
a) TMOD register is used to set various operation modes of timer/counter
b) TMOD register is used to load the count of the timer
c) Is the destination or the final register where the result is obtained after the operation of the timer
d) Is used to interrupt the timer
Answer: a
Explanation: TMOD is used to set various operation modes of timer/counter by the programmer.
4. What is the maximum delay that can be generated with the crystal frequency of 22MHz?
a) 2978.9 sec
b) 0.011 msec
c) 11.63 sec
d) 2.97 msec
Answer: d
Explanation: For generating the maximum delay we have to multiply the maximum number of counts with the time
period required to execute one machine cycle( 65536*1/22MHz).
5. Auto reload mode is allowed in which mode of the timer?
a) Mode 0
b) Mode 1
c) Mode 2
d) Mode 3
Answer: c
Explanation: Auto reload is allowed in the Mode 2 of the timer because here in this mode, we don’t need to load the
count again and again in the register.
6. Find out the roll over value for the timer in Mode 0, Mode 1 and Mode 2?
a) 00FFH,0FFFH,FFFFH
b) 1FFFH,0FFFH,FFFFH
c) 1FFFH,FFFFH,00FFH
d) 1FFFH,00FFH,FFFFH
Answer: c
Explanation: For Mode 0 13 bit value is used so 1FFFH is chosen to be the roll over value. Similarly for Mode 1 FF
FFH and for Mode 2 FFH is the roll over value for the timers and counter.
7. What steps are followed when we need to turn on any timer?
a) load the count, start the timer, keep monitoring it, stop the timer
b) load the TMOD register, load the count, start the timer, keep monitoring it, stop the timer
c) load the TMOD register, start the timer, load the count, keep monitoring it, stop the timer
d) none of the mentioned
Answer: b
Explanation: When any timer is to turn on, then firstly we have to load the TMOD register and the count. Then the ti
mer is to get started. After then, we need to monitor the timer properly and then when the roll over condition arises t
hen the timer is to be stopped.
8. If Timer 0 is to be used as a counter, then at what particular pin clock pulse need to be applied?
a) P3.3
b) P3.4
c) P3.5
d) P3.6
Answer: b
Explanation: If Timer 0 is to be used as a counter, then a pulse has to be applied at P3.4 and if it is for Timer 1 then t
he clock pulse has to be applied at the pin P3.5.
9. In the instruction “MOV TH1,#-3”, what is the value that is being loaded in the TH1 register?
a) 0xFCH
b) 0xFBH
c) 0xFDH
d) 0xFEH
Answer: c
Explanation: Negative value is loaded in 2’s complement form. -3 represented in 2’s complement form as FDH.
10. TF1, TR1, TF0, TR0 bits are of which register?
a) TMOD
b) SCON
c) TCON
d) SMOD
Answer: c
Explanation: All of these bits are part of TCON (Timer Control) register. TF0 and TF1 are used to check overflow o
f timer 0 and timer 1 respectively. TR0 and TR1 are timer control bits used to start and stop of timer 0 and timer 1 re
spectively.
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1. Which devices are specifically being used for converting serial to parallel and from parallel to serial respectively?
a) timers
b) counters
c) registers
d) serial communication
Answer: c
Explanation: Some registers like the parallel in serial out and serial in parallel out are used to convert serial data into
parallel and vice versa respectively.
2. What is the difference between UART and USART communication?
a) they are the names of the same particular thing, just the difference of A and S is there in it
b) one uses asynchronous means of communication and the other uses synchronous means of communication
c) one uses asynchronous means of communication and the other uses asynchronous and synchronous means of com
munication
d) one uses angular means of the communication and the other uses linear means of communication
Answer: c
Explanation: UART stands for Universal Asynchronous receiver-transmitter and USART stands for Universal Sync
hronous and Asynchronous receiver-transmitter.
3. Which of the following best describes the use of framing in asynchronous means of communication?
a) it binds the data properly
b) it tells us about the start and stops of the data to be transmitted or received
c) it is used for error checking
d) it is used for flow control
Answer: b
Explanation: In data framing in asynchronous means of communication, the data is packed between the start and the
stop bit. This is done so as to tell the other computer about the start and the end of the data.
4. Which of the following signal control the flow of data?
a) RTS
b) DTR
c) RTS & DTR
d) None of the mentioned
Answer: a
Explanation: RTS is a request to send control signal which is a control for the flow of data. On the other hand DTR i
s a Data Terminal Ready control signal which tells about the current status of the DTE.
5. Which of the following is the logic level understood by the micro-controller/micro-processor?
a) TTL logic level
b) RS232 logic level
c) None of the mentioned
d) TTL & RS232 logic level
Answer: a
Explanation: TTL logic or the transistor logic level is the logic that is understood by the micro-controllers/microproc
essors.
6. What is a null modem connection?
a) no data transmission
b) no MAX232
c) the RxD of one is the TxD for the other
d) no serial communication
Answer: c
Explanation: In null modem connection the RxD of one is the TxD for the other.
7. Which of the following best states the reason that why baud rate is mentioned in serial communication?
a) to know about the no of bits being transmitted per second
b) to make the two devices compatible with each other, so that the transmission becomes easy and error free
c) to use Timer 1
d) for wasting memory
Answer: b
Explanation: To make two devices compatible with each other baud rate is mentioned in the serial communication s
o that the transmission becomes easy and error free.
8. With what frequency UART operates( where f denoted the crystal frequency )?
a) f/12
b) f/32
c) f/144
d) f/384
Answer: d
Explanation: UART frequency is the crystal frequency f/12 divided by 32, that comes out to be f/384.
9. What is the function of the SCON register?
a) to control SBUF and SMOD registers
b) to program the start bit, stop bit, and data bits of framing
c) to control SMOD registers
d) none of the mentioned
Answer: b
Explanation: SCON register is mainly used for programming the start bits, stop bits and data bits of framing. As it c
onsists of bits like RB8, TB8, SM0, SM1, SM2 etc.
10. What should be done if we want to double the baud rate?
a) change a bit of the TMOD register
b) change a bit of the PCON register
c) change a bit of the SCON register
d) change a bit of the SBUF register
Answer: b
Explanation: PCON register consists of SMOD bit as its D7 bit, so if we set this bit then the baud rate gets doubled.
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1. When an interrupt is enabled, then where does the pointer moves immediately after this interrupt has occurred?
a) to the next instruction which is to be executed
b) to the first instruction of ISR
c) to a fixed location in memory called interrupt vector table
d) to the end of the program
Answer: c
Explanation: When an interrupt occurs, then it jumps to a fixed memory location in memory called the interrupt vect
or table that holds the address of the Interrupt Service Routine.
2. What are the contents of the IE register, when the interrupt of the memory location 0x00 is caused?
a) 0xFFH
b) 0x00H
c) 0x10H
d) 0xF0H
Answer: b
Explanation: When interrupt of 0x00 is caused (the reset interrupt) then all the other interrupts will be disabled or th
e contents of the IE register becomes null.
3. After RETI instruction is executed then the pointer will move to which location in the program?
a) next interrupt of the interrupt vector table
b) immediate next instruction where interrupt is occurred
c) next instruction after the RETI in the memory
d) none of the mentioned
Answer: b
Explanation: When the RETI instruction is executed, PC will fetch 2-bytes (address) from top of stack which is store
d when interrupt is occurred. This will return to the place where interrupt is occurred and starts executing instruction
s.
4. Which pin of the external hardware is said to exhibit INT0 interrupt?
a) pin no 10
b) pin no 11
c) pin no 12
d) pin no 13
Answer: c
Explanation: INT0 interrupt is caused when pin no 12 in the hardware of the 8051 controller is enabled with a low le
veled pulse.
5. Which bit of the IE register is used to enable TxD/RxD interrupt?
a) IE.D5
b) IE.D2
c) IE.D3
d) IE.D4
Answer: d
Explanation: IE.D4 is used to enable RS interrupt or the serial communication interrupt.
6. Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register (assu
ming initially all bits of the IE register are zero)?
a) EX0=1
b) EA=1
c) any of the mentioned
d) EX0=1 & EA=1
Answer: d
Explanation: For executing the EX0 interrupt, the EX0 and EA bits of the IE register should be set. EA is set to enab
le all the interrupts and EX0 is set to enable the external hardware interrupt 0 interrupt and mask the other enabled in
terrupts.
7. Why normally LJMP instructions are the topmost lines of the ISR?
a) so as to jump to some other location where there is a wider space of memory available to write the codes
b) so as to avoid overwriting of other interrupt instructions
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: There is a small space of memory present in the vector table between two different interrupts so in orde
r to avoid overwriting of other interrupts we normally jump to other locations where a wide range of space is availab
le.
8. Which register is used to make the interrupt level or an edge triggered pulse?
a) TCON
b) IE
c) IPR
d) SCON
Answer: a
Explanation: TCON register is used to make any interrupt level or edge triggered.
9. What is the disadvantage of a level triggered pulse?
a) a constant pulse is to be maintained for a greater span of time
b) another interrupt may be generated if the low-level signal is not removed before the ISR is finished
c) it is difficult to produce
d) another interrupt may be caused if the signal is still low before the completion of the last instruction
Answer: d
Explanation: In a level triggered interrupt, if the low signal at interrupt pin must be removed before the execution of
last instruction of the ISR i.e. RETI. If low signal at interrupt pin is not removed before completing the ISR then it w
ill be generating another interrupt.
10. What is the correct order of priority that is set after a controller gets reset?
a) RI/TI > TF1 > TF0 > INT1 > INT0
b) RI/TI < TF1 < TF0 < INT1 < INT0
c) INT0 > TF0 > INT1 > TF1 > RI/TI
d) INT0 < TF0 < INT1 < TF1 < RI/TI
Answer: c
Explanation: On reset Interrupt Priorities are as INT0 > TF0 > INT1 > TF1 > RI/TI, where ‘>’ is used to denote high
est priority.
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1. How many rows and columns are present in a 16*2 alphanumeric LCD?
a) rows=2, columns=32
b) rows=16, columns=2
c) rows=16, columns=16
d) rows=2, columns=16
Answer: d
Explanation: 16*2 alphanumeric LCD has 2 rows and 16 columns.
2. How many data lines are there in a 16*2 alphanumeric LCD?
a) 16
b) 8
c) 1
d) 0
Answer: b
Explanation: There are eight data lines from pin no 7 to pin no 14 in an LCD.
3. Which pin of the LCD is used for adjusting its contrast?
a) pin no 1
b) pin no 2
c) pin no 3
d) pin no 4
Answer: c
Explanation: Pin no 3 is used for controlling the contrast of the LCD.
4. For writing commands on an LCD, RS bit is
a) set
b) reset
c) set & reset
d) none of the mentioned
Answer: b
Explanation: For writing commands on an LCD, RS pin is reset.
5. Which command of an LCD is used to shift the entire display to the right?
a) 0x1C
b) 0x18
c) 0x05
d) 0x07
Answer: a
Explanation: 0x1C is used to shift the entire display to the right.
6. Which command is used to select the 2 lines and 5*7 matrix of an LCD?
a) 0x01
b) 0x06
c) 0x0e
d) 0x38
Answer: d
Explanation: 0x38 is used to select the 2 lines and 5*7 matrix of an LCD.
7. Which of the following step/s is/are correct for sending data to an LCD?
a) set the R/W bit
b) set the E bit
c) set the RS bit
d) all of the mentioned
Answer: d
Explanation: To send data to an LCD, RS pin should be set so that LCD will come to know that it will receive data
which has to display on the screen. R/W pin should be reset as data has to be displayed (i.e. write to the LCD). High
to low pulse must be applied to the E pin when data is supplied to data pins of the LCD.
8. Which of the following step/s is/are correct to perform reading operation from an LCD?
a) low to high pulse at E pin
b) R/W pin is set high
c) low to high pulse at E pin & R/W pin is set high
d) none of the mentioned
Answer: c
Explanation: For reading operations, R/W pin should be made high and added to it, a low to high pulse is also gener
ated at the E pin.
9. Which instruction is used to select the first row first column of an LCD?
a) 0x08
b) 0x0c
c) 0x80
d) 0xc0
Answer: c
Explanation: 0x80 is used to select the first row first column of an LCD.
10. The RS pin is _________ for an LCD.
a) input
b) output
c) input & output
d) none of the mentioned
Answer: a
Explanation: The RS pin is an input pin for an LCD.
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1. Which of the following steps detects the key in a 4*4 keyboard matrix about the key that is being pressed?
a) masking of bits
b) ensuring that initially, all keys are open
c) checking that whether the key is actually pressed or not
d) all of the mentioned
Answer: d
Explanation: For detecting that whether the key is actually pressed or not, firstly this must be ensured that initially al
l the keys are closed. Then we need to mask the bits individually to detect that which key is pressed. Then we need t
o check that is the key actually pressed or not, by checking that whether the key pressed for a time more than 20 mic
ro seconds.
2. What is described by this command: CJNE A,#00001111b, ROW1
a) it masks the bit and then jumps to the label where ROW1 is written
b) it makes the value of the accumulator 0FH and then jumps at the address where ROW1 label is written
c) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if the val
ue becomes equal
d) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if the val
ue is not equal
Answer: d
Explanation: This particular command CJNE A,#00001111b, ROW1 compares the value of the accumulator with O
FH and jumps to ROW1 address if the value is not equal.
3. To detect that in which column, the key is placed?
a) we can mask the bits and then check it
b) we can rotate the bits and then check that particular bit which is set or reset(according to the particular condition)
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: We can mask or we can even rotate the bits to check that particularly in which column is the key place
d.
4. In reading the columns of a matrix, if no key is pressed we should get all in binary notation
a) 0
b) 1
c) F
d) 7
Answer: b
Explanation: If no key is pressed, then all the keys show 1 as they are all connected to power supply.
5. If we need to operate a key of a keyboard in an interrupt mode, then it will generate what kind of interrupt?
a) ES
b) EX0/EX1
c) T0/T1
d) RESET
Answer: b
Explanation: If a key is to operate in an interrupt mode then it will generate an external hardware interrupt.
6. To identify that which key is being pressed, we need to:
a) ground all the pins of the port at a time
b) ground pins of the port one at a time
c) connect all the pins of the port to the main supply at a time
d) none of the mentioned
Answer: b
Explanation: To detect that which key is being pressed, we need to ground the pins one by one.
7. Key press detection and Key identification are:
a) the same processes
b) two different works are done in Keyboard Interfacing
c) none of the mentioned
d) any of the mentioned
Answer: b
Explanation: They are two different works that are involved in Keyboard Interfacing. One is used for checking that
which key is being actually pressed and the other is used to check that is the key actually pressed or not.
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1. Why two pins for ground are available in ADC0804?
a) for controlling the ADCON0 and ADCON1 register of the controller
b) for controlling the analog and the digital pins of the controller
c) for both parts of the chip respectively
d) for isolate analog and digital signal
Answer: d
Explanation: Two grounds are available in ADC0804 to isolate analog signal from digital signal. This isolation prov
ides accuracy in digital output.
2. What is the function of the WR pin?
a) its active high input used to inform ADC0804 to the end of conversion
b) its active low input used to inform ADC0804 to the end of conversion
c) its active low input used to inform ADC0804 to the start of conversion
d) its active high input used to inform ADC0804 to the start of conversion
Answer: c
Explanation: WR is active low input used to inform the ADC0804 to start the conversion process.
3. State which of the following statements are false?
a) CLK IN pin used for External Clock Input or Internal Clock with external RC element
b) INTR pin tells about the end of the conversion
c) ADC0804 IC is an 8 bit parallel ADC in the family of the ADC0800 series
d) None of the mentioned
Answer: d
Explanation: CLK IN pin is used to tell about the conversion time, INTR pin tells about the end of the conversion an
d ADC0804 has a resolution of 8 bits only so all three statements are true.
4. While programming the ADC0808/0809 IC what steps are followed?
a) select the analog channel, start the conversion, monitor the conversion, display the digital results
b) select the analog channel, activate the ALE signal (L to H pulse), start the conversion, monitor the conversion, rea
d the digital results
c) select the analog channel, activate the ALE signal (H to L pulse), start the conversion, monitor the conversion, rea
d the digital results
d) select the channel, start the conversion, end the conversion
Answer: b
Explanation: While programming the ADC0808/0809 IC firstly we need to select the channel from the A, B, C pins.
Then we need to activate the ALE signal, this is needed to latch the address. Then we start the conversion from the
WR pin. After monitoring the INTR pin we get to know about the end of the conversion. Then we activate the OE e
nable to read out data out of the ADC chip.
5. In ADC0808/0809 IC which pin is used to select Step Size?
a) Vref
b) Vin
c) Vref/2 & Vin
d) None of the mentioned
Answer: a
Explanation: Step Size is calculated by formula Vref/(2n). As ADC0808/0809 8-bit ADC value of n=8. Therefore fo
rmula becomes Vref/(28) = Vref/256. If Vref = 5V then Step Size will be 5/256 i.e. 19.53mV.
6. What is the difference between ADC0804 and MAX1112?
a) ADC0804 has 8 bits and MAX1112 has 1 bit for data output
b) ADC0804 is used for adc and dac conversions whereas MAX1112 is used for serial data transmissions
c) ADC0804 has 32 bits and MAX1112 has 3 bit for data output
d) None of the mentioned
Answer: a
Explanation: ADC0804 is used for parallel ADC and MAX1112 is used for serial ADC.
7. Which of the following statements are true about DAC0808?
a) parallel digital data to analog data conversion
b) it has current as an output
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: DAC0804 is used for parallel data to analog data conversion.
8. 8 input DAC has ________
a) 8 discrete voltage levels
b) 64 discrete voltage levels
c) 124 discrete voltage levels
d) 256 discrete voltage levels
Answer: d
Explanation: For n input DAC has 2^n discrete voltage levels.
9. INTR, WR signal is an input/output signal pin?
a) both are output
b) both are input
c) one is input and the other is output
d) none of the mentioned
Answer: c
Explanation: INTR pin tells about the end of the conversion (output) and WR pin tells us to start the conversion (inp
ut).
10. What is the function of the SCLK pin in MAX1112?
a) It is used to bring data in
b) It is used to bring data out and send in the control byte, one at a time
c) It is used to get output clock
d) It is used to get serial output
Answer: b
Explanation: SCLK is used to bring data out and send in the control byte.
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1. A thermistor is a __________
a) sensor
b) adc
c) transducer
d) micro controller
Answer: c
Explanation: A thermistor is a device which is used to convert the temperature into electrical signals, so it acts as a tr
ansducer.
2. What is the difference between LM 34 and LM 35 sensors?
a) one is a sensor and the other is a transducer
b) one’s output voltage corresponds to the Fahrenheit temperature and the other corresponds to the Celsius temperat
ure
c) one is of low precision and the other is of higher precision
d) one requires external calibration and the other doesn’t require it
Answer: b
Explanation: LM 34’s output voltage corresponds to the Fahrenheit temperature and LM 35 corresponds to the Celsi
us temperature.
3. An electronic device which converts physical quantity or energy from one form to another is called ______
a) Sensor
b) Transistor
c) Transducer
d) Thyristor
Answer: c
Explanation: An electronic device that converts physical quantity or energy from one form to another is called Trans
ducer. Examples: Sensor, Speaker, Microphone, etc.
4. What is signal conditioning?
a) to analyse any signal
b) conversion or modification is referred to as conditioning
c) conversion from analog to digital is signal conditioning
d) conversion from digital to analog is signal conditioning
Answer: b
Explanation: Signal Conditioning is referred to as the conversion of a signal from one form to other, now this may b
e from analog to digital conditioning or digital to analog conditioning.
5. What steps have to be followed for interfacing a sensor to a microcontroller 8051?
a) make the appropriate connections with the controller, ADC conversion, analyse the results
b) interface sensor with ADC and ADC with 8051
c) interface sensor with the MAX232, send now to microcontroller, analyse the results
d) none of the mentioned
Answer: b
Explanation: For interfacing a sensor with an 8051 microcontroller, we need ADC in between because output of sen
sor is analog and microcontroller works on digital signals only. So whatever signal generated by the sensor is conver
ted into its digital equivalent using ADC and equivalent digital signal is given to the microcontroller for processing.
6. LM35 has how many pins?
a) 2
b) 1
c) 3
d) 4
Answer: c
Explanation: LM35 has 3 pins.
7. Why Vref is set of ADC0848 to 2.56 V if analog input is connected to the LM35?
a) to set the step size of the sampled input
b) to set the ground for the chip
c) to provide supply to the chip
d) all of the mentioned
Answer: a
Explanation: Vref is used to set the step size of the ADC conversion, if it is selected to 2.56 then the step size will be
selected to 10mV, so for every step increase of the analog voltage an increase of 10 mV will be there.
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1. The 8255 is a ______ chip.
a) Input/Output
b) Analog to Digital
c) Digital to analog
d) None of the mentioned
Answer: a
Explanation: The 8255 is Input/Output (I/O) chip. It has three separate accessible ports. The 8255 chip is used to exp
and the I/O ports of microcontrollers.
2. Which pins of a microcontroller are directly connected with 8255?
a) RD
b) WR
c) D0-D7
d) All of the mentioned
Answer: d
Explanation: RD, WR, D0-D7 all are directly connected to the 8051 for telling the chip about the control signals and
also for transferring the data.
3. Find the control word for PA = out, PB = in, PCL = out, PCH = out (Mode0)?
a) 0x02H
b) 0x82H
c) 0x83H
d) 0x03H
Answer: b
Explanation: The value that is being loaded in the control word is 10000010b for PB as an input port and all others a
s the output ports being operated in mode0. The hex equivalent of 10000010b → 0x82H.
4. Which pins are used to select the ports and the control register?
a) CS
b) A1
c) A0
d) All of the mentioned
Answer: d
Explanation: CS pin is an active low input pin for 8255 and it is used for selecting a chip. A0 and A1 pins are used f
or select ports and the control register.
5. What is the value of the control register when RESET button is set to zero?
a) 0x00H
b) 0xFFH
c) 0x11H
d) value remains the same
Answer: d
Explanation: RESET is active-high signal input into the 8255 used to clear the control register. When RESET is acti
vated (i.e. set to high), all ports are initialized as input mode. Hence the value of the control register remains the sam
e as it is even when the RESET button is set to zero.
6. Why MOVX instruction is being used to access the ports of the 8255?
a) because 8255 is connecting a microcontroller in memory mapped I/O configuration
b) because 8255 is used to access the external communication
c) because 8255 is used to access the data transfer
d) because 8255 is used to access the interfacing of LCD, motor etc
Answer: a
Explanation: As 8255 is connecting a microcontroller in memory mapped I/O configuration. This means that memor
y space used to access 8255 (i.e. 8255 is treated as external memory). MOVX instruction is used to access external
memory locations.
7. What is correct about the BSR mode from below?
a) In BSR mode, only the individual bits of PORT A can be programmed
b) In BSR mode, only the individual bits of PORT B can be programmed
c) In BSR mode, only the individual bits of PORT C can be programmed
d) none of the mentioned
Answer: c
Explanation: BSR (Bit Set/Rest) mode is used to program individual bits of PORT C only.
8. How many pins of the 8255 can be used as the I/O ports?
a) 8
b) 16
c) 24
d) 32
Answer: c
Explanation: There are 3 ports available in the 8255 so 24 pins are available for the I/O ports pins.
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1. DS12887 is a ____________
a) Timer IC
b) Serial communication IC
c) RTC IC
d) Motor
Answer: c
Explanation: DS12887 is a real time clock that is widely used to provide accurate time and date for many application
s.
2. DS12887 has _____ amount of RAM.
a) 14 bytes
b) 114 bytes
c) 128 bytes
d) 64 bytes
Answer: c
Explanation: DS12887 has 128 bytes of non-volatile RAM.
3. DS12887 has _____ amount of RAM for general purpose applications.
a) 9 bytes
b) 114 bytes
c) 128 bytes
d) 14 bytes
Answer: b
Explanation: DS12887 has 128 bytes of non-volatile RAM. Out of 128 bytes, 14 bytes of RAM for clock/calendar a
nd control registers, and another 114 bytes of RAM for general purpose data storage.
4. In DS12887, which bits of the Register A are used to turn on the oscillator?
a) D4
b) D5
c) D6
d) All of the mentioned
Answer: d
Explanation: In DS12887, D4-D6 bits of register A are used to turn on the oscillator. A specific value of 010 of D4-
D6 is desirable for turning on the oscillator.
5. In DS12887, which out of the following is correct about the SQW pin?
a) it is an output pin
b) it can provide up to 15 different square waves
c) the frequency of the square wave is set by the register A
d) all of the mentioned are correct
Answer: d
Explanation: In DS12887, SQW pin stands for SQuare Wave. It is an output pin that can provide us with 15 differen
t square waves. The frequency of the square wave is selected by programming register A.
6. In DS12887, what is correct about the UIP bit of the register A?
a) it is a read only bit
b) it is used to know about the result
c) it is used to select the DS12887 datasheet
d) all of the mentioned
Answer: a
Explanation: In DS12887, UIP bit of register A stands for Update In Progress. The update-in-progress (UIP) bit is a
status flag i.e. read-only bit.
7. In DS12887, what is the range of RAM addresses which are used to store the values of time, calendar and alarm d
ata?
a) 00-7FH
b) 00-09H
c) 0EH-7FH
d) 0A-0DH
Answer: b
Explanation: In DS12887, the first ten locations i.e. 00-09H are used to store the values of time, calendar and alarm
data.
8. Is DS12887 has non-volatile RAM?
a) Yes
b) No
c) Can’t be determined
d) None of the mentioned
Answer: a
Explanation: Yes, DS12887 has non-volatile RAM.
9. Name the read only registers are present in the DS12887?
a) register A, register B
b) register B, register C
c) register C, register D
d) register D, register A
Answer: c
Explanation: Register C and D are the read only registers in the DS12887 found at memory locations 0C-0DH.
10. In DS12887, when the external source is turned-off, how does DS12887 get power to retain its data?
a) Internal Lithium Battery
b) Internal Lead Battery
c) Additional external Alkaline Battery
d) Additional external Lithium Battery
Answer: a
Explanation: When Vcc falls below 3V or external voltage source is switched-off, internal lithium battery provides p
ower to DS12887. And this will prevent loss of data.
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1. What is the principle on which electromagnetic relays operate?
a) electromagnetic induction
b) motor control
c) switching
d) none of the mentioned
Answer: a
Explanation: Electromagnetic relays work on the principle of electromagnetic induction. It is used as a switch in ind
ustrial controls, automobile and appliances. It allows the isolation of the sections of a system with two different volt
age sources.
2. What are DPDT relays?
a) Single pole, single throw
b) Single pole, double throw
c) Double pole, double throw
d) None of the mentioned
Answer: c
Explanation: In DPDT relay, there are two poles and two throws (i.e.contacts). For each pole there are two contacts i
.e. normally open (NO) and normally closed (NC). The contacts can be NO or NC. Generally, contact is NC when th
e coil is not energized. When the coil is energized both poles become NC.
3. Why do we need a ULN2803 in driving a relay?
a) for switching a motor
b) for increasing the current
c) for increasing the power
d) for switching the voltage
Answer: b
Explanation: We need a ULN2803 for driving a relay because the relay coil requires 10mA or more current to be en
ergized. If microcontroller pins are not able to provide sufficient current to drive relays then we need ULN2803 for
driving relays.
4. Why are solid-state relays advantageous over electromechanical relays?
a) they need zero voltage circuit
b) they need less current to be energised
c) they need less voltage to be energised
d) none of the mentioned
Answer: b
Explanation: Solid-state relays are advantageous over electromechanical relays because their switching response tim
e is much faster than electromechanical relays as solid-state relays are made-up of semiconductor materials. Also, so
lid-state relays required low input current for operation and small packaging make them ideal for microcontrollers.
5. What are optoisolators?
a) it is a driver
b) it is a thing isolated from the entire world
c) it is a device that can be used as an electromagnetic relay without a driver
d) none of the mentioned
Answer: c
Explanation: Optoisolators are devices that can be used as an electromagnetic relay without a driver. It usually consi
sts of a led (transmitter) and a photoresistive receiver.
6. How can we control the speed of a stepper motor?
a) by controlling its switching rate
b) by controlling its torque
c) by controlling its wave drive 4 step sequence
d) cant be controlled
Answer: a
Explanation: Speed of a stepper motor can be controlled by changing its switching speed or by changing the length o
f the time delay loop.
7. Which of the following can be a unit for torque?
a) kg/m2
b) ounce-inch
c) kg-m3
d) g/m
Answer: b
Explanation: Torque is equal to the force applied at a particular distance. So its unit can be ounce-inch.
8. The RPM rating given for the DC motor is for?
a) no-loaded
b) loaded
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: RPM rating given for a DC motor is for a no-loaded condition.
9. How can we change the speed of a DC motor using PWM?
a) By changing amplitude of PWM
b) By keeping fixed duty cycle
c) By changing duty cycle of PWM
d) By increasing power of PWM
Answer: c
Explanation: We can change the speed of a DC motor using PWM by changing the duty cycle of PWM. Changing d
uty cycle means changing ON and OFF timing of PWM. Even if amplitude of PWM is fixed by increasing the ON ti
me of PWM increases the speed of the DC motor.
10. How can the direction of the DC motor be changed?
a) by changing the torque
b) by changing the switching speed
c) by changing the polarity of voltages connected to the leads
d) by changing the RPM rating
Answer: c
Explanation: The direction of the DC motor can be changed by changing the polarity of the voltages connected to its
leads.
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1. Is the following instruction correct LDI R3,50?
a) Yes
b) No
c) Cant be said
d) None of the mentioned
Answer: b
Explanation: If LDI Rd,k is written then the range of Rd varies from R16-R31, as R3 is less than R16 so this instruct
ion will generate an error.
2. Registers R0-R31 are used for what type of works?
a) they are used for arithmetic and logic instructions
b) they are used for data copy
c) they are used for calculations
d) none of the mentioned
Answer: a
Explanation: GPRs are used for implementing arithmetic and logic instructions in the controller. They do the same
work as the accumulator does in the other microcontrollers and microprocessors.
3. The largest value that can be loaded in an 8 bit register is?
a) 11111111H
b) FH
c) FFH
d) 00H
Answer: c
Explanation: The largest value that can be loaded in an 8 bit register is 11111111b or FFH.
4. The total space for the data memory available in the AVR based microcontroller is?
a) FFH
b) FFFH
c) FFFFH
d) FFFFFH
Answer: c
Explanation: The maximum value that can be loaded in the code memory of an AVR based microcontroller is FFFF
H.
5. Which of the following instructions affect the flags of the status register?
a) AND
b) INC
c) OR
d) All of the mentioned
Answer: d
Explanation: AND, INC, OR could affect status register flags. All arithmetic and logical instructions affect status re
gister flags except SER Rd instruction. SER Rd is used to SEt Register i.e. after the execution of this instruction Rd l
oaded with FFH value and no flag is affected.
6. What is the difference between the two given instructions?
a) One copies the hexadecimal value to R16 and the other copies the decimal value to the R16 register
b) One is for command, other is for data
c) One is for assignment, other is for operations
d) Both the commands are the same
Answer: d
Explanation: Both the above commands are the same. They both are used for assigning the hexadecimal values to th
e registers.
7. Which out of the following is not a directive?
a) .EQU
b) .DEVICE
c) .ORG
d) .LDI
Answer: d
Explanation: .EQU, .DEVICE, .ORG all are the directives to the assembler whereas LDI is a command.
8. Is an assembly language a high level language?
a) Yes
b) No
c) Can’t be said
d) None of the mentioned
Answer: b
Explanation: Assembly language is not high level language rather it is low level language because it deals directly w
ith the internal structure of CPU. To program in assembly, the internal structure of the CPU must be known. Wherea
s in high level programming languages programmers don’t bother about the internal structure of the CPU because th
is is done by the compiler.
9. A 14-bit program counter can access __________ bytes of memory locations.
a) 4K
b) 8K
c) 16K
d) 64K
Answer: c
Explanation: A 14-bit program counter can access 214 bytes of memory locations i.e. 16k bytes.
214 = 24 x 210
a) 00H
b) 000H
c) 0000H
d) 00000H
Answer: d
Explanation: When an AVR wakes up, then the PC starts at the memory location 00000H.
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1. Which of the following is correct about BRNE instruction in avr microcontrollers?
a) it is used to compare two registers
b) it is used to compare two values
c) it is used to check the zero flag
d) it is used to jump to the given mentioned label when the zero flag accounts to 0
Answer: d
Explanation: BRNE label instruction is used to jump to that particular address denoted by label if condition (Z=0) is
true or satisfied. If the condition is not satisfied then it will execute the next immediate instruction.
2. How many times is this loop going to get executed?
a) 10
b) 70
c) 700
d) none of the mentioned
Answer: b
Explanation: As the R21 register is loaded with 70, so to make it zero it needs to be decremented 70 times then only
the OUT instruction will be executed so this loop repeats 70 times.
3. Which of the below mentioned are not the conditional jumps?
a) BRLO
b) BRMI
c) BRVC
d) None of the mentioned
Answer: d
Explanation: BRLO is used to branch if C=1, BRMI is used when N=1 and BRVC are used when V=0, so all are the
conditional jumps.
4. What is the relation between the target and the relative address?
a) target address= PC address + relative address
b) target address= relation address*2
c) relative address= PC address + target address
d) none of the mentioned
Answer: a
Explanation: Target address can be calculated by calculating the sum of the address of the program counter and the r
elative address.
5. In the JMP instruction, how many bits are there for determining the target address?
a) 16
b) 32
c) 22
d) 10
Answer: c
Explanation: In the JMP instruction of 4 bytes space, 22 bits are there for determining the target address and the othe
r 10 are for the op code verification.
6. Which of the following statements are correct?
a) relative address of RJMP instruction varies from 000-fffH
b) target address of JMP instruction varies from 000000-3fffffH
c) IJMP instruction jumps to that address that points to by the Z register
d) all of the mentioned
Answer: d
Explanation: The relative address of the RJMP instruction varies from 000-fffH. The target address of the JMP instr
uction varies from 000000-3fffffH. IJMP instruction is used to jump at that particular address pointed to by the Z reg
ister. So all are the correct statements.
7. Which of the following is used to represent the last RAM address?
a) MEM
b) LASTRAM
c) RAMEND
d) None of the mentioned
Answer: c
Explanation: RAMEND is a micro used to represent the last RAM address. In AVR, Stack Pointer is initialized on t
op of the stack i.e. last address of RAM.
8. Which of the following statements are correct about the RCALL instruction?
a) it is a 2 byte instruction
b) it is a 4 byte instruction
c) it is a 16 byte instruction
d) none of the mentioned
Answer: a
Explanation: RCALL instruction is used to go to the target address in the memory from -2048 to 2047.
9. On power on SP points to the address?
a) ffffH
b) fffH
c) 00h
d) all of the mentioned
Answer: c
Explanation: On power on SP register points to the 00H address.
10. Which of the following statements is true?
a) CALL instruction is used to transfer control anywhere in the 4M memory space
b) PUSH instruction is used to take out the value from the stack into some register
c) POP instruction is used to jump to any location
d) RCALL is a 4 byte instruction
Answer: a
Explanation: CALL instruction is used to transfer control anywhere in the 4M memory space available in the AVR.
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1. In AVR, which registers are there for the I/O programming of ports?
a) PORT
b) PIN
c) DDR
d) All of the mentioned
Answer: d
Explanation: For I/O programming of the ports in AVR microcontrollers, there are basically three main registers. Th
ey are PORT, PIN, DDR, so all of the mentioned is the right option.
2. The data will not go from the port registers to the pin unless:
a) DDR register of that port is set to 0
b) PORT register of that port is set to 1
c) DDR register of that port is set to 1
d) PORT register of that port is set to 0
Answer: c
Explanation: The data will not go from the port registers to the pin unless the DDR register of that port is set to 1 be
cause by doing this we make that port an output port after which data can be taken from the PORT registers to the pi
n.
3. On reset DDR registers of all ports are set to:
a) 0
b) 1
c) None of the mentioned
d) 0 & 1
Answer: a
Explanation: On reset, the DDR registers of all the ports are set to 0 which means that the by default all ports are set
as input ports.
4. Which of the following statements are correct?
a) PIN register of a port is used to bring data into CPU from pins
b) PORT register is used to send data out to pins
c) DDR register is used to control the direction of a port
d) All of the mentioned
Answer: d
Explanation: There are three registers that are related to a port. They are PIN, PORT, DDR. PIN register is used to b
ring data into CPU from pins, PORT register is used to send data to pins and DDR register is used to control the dire
ction of the data transfer. So all are the right options.
5. In the AVR family, all I/O ports have 8 pins?
a) true
b) false
c) none of the mentioned
d) can’t be determined
Answer: b
Explanation: In the AVR family, all I/O ports don’t have 8 pins. Number of I/O pins depends on the total number of
pins of the controller. Eg. ATtinyxx is an 8 pin controller and it has 6 I/O pins.
6. Which of the following is not a single bit instruction in AVR?
a) SBI
b) PORT
c) CBI
d) All of the mentioned
Answer: b
Explanation: PORT is not an instruction. It is the name of a register in AVR.
7. Which of the following is correct about the SBIS instruction?
a) it is used to monitor status of bit in I/O register
b) it is a byte oriented instruction
c) It is a 4 byte instruction
d) all of the mentioned
Answer: a
Explanation: SBIS (Skip if Bit in I/O register Set) is used to check status of bit in I/O register. If the bit mentioned in
the instruction is SET or HIGH then the controller will skip the immediate next instruction.
8. Instruction CBI PORTB,1 means
a) clearing the PORTB register
b) clearing the first bit of the PORTB register
c) setting the PORTB register
d) setting the first bit of the PORTB register
Answer: b
Explanation: CBI PORTB, 1 means to clear the first bit of the PORTB register. It is a bit oriented instruction.
9. Which of the following instruction can be used to toggle a bit of the PORT?
a) SBI
b) CBI
c) SBI & CBI
d) None of the mentioned
Answer: c
Explanation: If SBI and CBI are used together, then they can be used to toggle a bit of a port successfully.
10. What is the main function of the SBIC instruction?
a) it is used to clear a particular bit of a port
b) it is used to jump unconditionally
c) it is used to skip the instruction if a particular bit of a port is zero
d) none of the mentioned
Answer: c
Explanation: SBIC (Skip if Bit in I/O register Clear) is used to check status of bit in I/O register. If the bit mentioned
in the instruction is CLEAR or LOW then the controller will skip the immediate next instruction.
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1. In AVR microcontrollers, ADD instruction affects the status of which of the following bits of a status register?
a) Z
b) C
c) N
d) All of the mentioned
Answer: d
Explanation: ADD instruction affects the status of Z, C, N, V, H and S bits of a status register.
2. ADC instruction is used for?
a) addition of two 16 bit numbers
b) analog to digital conversion
c) automatic digital control
d) none of the mentioned
Answer: a
Explanation: ADC instruction can be used for addition of two 16 bit numbers as here two 8 bit numbers are added si
multaneously along with the carry coming from the previous 8 bits. So it can be used for the addition of two 16 bit n
umbers.
3. AVR supports which of the following mentioned subtraction instructions?
a) SUB
b) SBC
c) SUBI
d) All of the mentioned
Answer: d
Explanation: AVR supports five types of subtraction instructions. They are SUB, SBC, SUBI, SBCI, SBIW.
4. What steps are involved when we subtract two numbers present at two different locations?
a) take the two’s complement of the subtrahend
b) add it to the minuend
c) invert the carry
d) all of the mentioned
Answer: d
Explanation: When we need to subtract two numbers present at two different locations then firstly we need to take th
e 2’s complement of the subtrahend, then we add it with the minuend and then when we invert the carry then the co
mplete procedure of the subtraction is completed.
5. In executing subtraction based instructions, state the role of the C flag?
a) if C=1, the result is negative
b) if C=1, the result is positive
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: If the C flag comes out to be 1, then the result is assumed to be negative and vice versa.
6. Which of the following is correct about the MUL instruction?
a) it is a byte-by-byte multiplication instruction
b) the product is stored in two registers R1 and R0
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: MUL instruction is a byte-by-byte multiplication instruction whose result is stored in two registers R1
and R0.
7. In AVR, when is the V flag set?
a) there is a carry from D7 bit
b) there is a carry from D6 to D7 bit
c) when carry is generated only from D6 to D7 or carry is generated only from D7
d) none of the mentioned
Answer: c
Explanation: In AVR, V i.e. Overflow flag is set when carry is generated only from D6 to D7 or carry is generated o
nly from D7. Overflow flag is used to detect errors in signed arithmetic operations.
8. To set the bits of a register R1 to 1, we must OR the contents of the register with?
a) 00H
b) 11H
c) FFH
d) 0FH
Answer: c
Explanation: To make the contents of the register R1 to 1 we must OR the contents of that register with FFH becaus
e according to Or algorithm 0+1=1 and 1+0=1.
9. CP instruction alters the value of the register?
a) true
b) false
c) none of the mentioned
d) can’t be said
Answer: b
Explanation: CP command is used to compare the contents of the two registers. It doesn’t actually alter the value of t
he register.
10. What is right about the ROR instruction?
a) it rotates the contents of the register left to right
b) it rotates the contents of the register from right to left
c) it rotates the contents of the register from left to right through carry
d) it rotates the contents of the register from right to left through carry
Answer: c
Explanation: ROR instruction is used to rotate the contents of the register from left to right through carry.
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1. In AVR, which of the following registers are not used for programming timers?
a) TCNT
b) TCON
c) TIFR
d) None of the mentioned
Answer: b
Explanation: In the timer programming of an AVR microcontroller, mainly used registers are TCNTn that stores the
values of the count. TCCRn that is used to assign the mode of operation of a timer and TIFR that stores the status of
various flags of the timers. Two more registers are used they are OCRn and OCFn. They are used for comparison wi
th the count register.
2. What is the use of the prescalar in the operation of the timer?
a) for fast calculations
b) for increasing the time delay given by the timer by decreasing its frequency of operation
c) for removing the concept the reloading of count
d) for easy counter operations
Answer: b
Explanation: Prescalars are used in the operation of the timers because they generally increase the time delay generat
ion by decreasing the frequency of its operation.
3. What modes are generally used in the operation of the timer0?
a) Normal mode
b) CTC mode
c) PWM mode
d) All of the mentioned
Answer: d
Explanation: Modes of a timer are decided by the WGM00 and WGM01 bit of the TCCR0 register and for timer0 th
ese modes are normal mode, CTC mode, pwm mode and the fast pwm mode.
4. Timer 0 can act as a counter ____________
a) if the CS02-CS00 are 110 or 111
b) if the FOC0 bit is set to 110
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: Timer0 can act as a counter if the CS02-CS00 bits are from 110-111.
5. Which of the timer can operate in the 16 bit condition?
a) timer0
b) timer1
c) timer2
d) all of the mentioned
Answer: b
Explanation: Timer0 and Timer2 can operate in the 8 bit condition while only Timer 1 operates in the 16 bit conditio
n.
6. Which of the following will generate the maximum time delay?
a) f/2
b) f/4
c) f/16
d) f/32
Answer: d
Explanation: f/32 has the lowest frequency as it is divided by the maximum value of the constant, so as time and fre
quency are inversely related to each other so this will generate the maximum amount of machine cycle which will as
a result generate the greatest delay.
7. What is the difference in the operation of a normal and a CTC mode of a timer?
a) in CTC mode PWM is used
b) here serial timer is monitored
c) in CTC mode, timer counts up until contents of TCNT register becomes equal to the contents of OCR
d) none of the mentioned
Answer: c
Explanation: In CTC mode, timer counts up until the contents of TCNT register becomes equal to the contents of O
CR; then the timer will be cleared and the OCF0 flag will be set when the next clock occurs. In Normal mode, timer
counts until max i.e. 0xFFH. When it rolls over from 0xFFH to 0x00H, it sets TOV(Timer Overflow).
8. We can count the pulses on the positive or the negative edge triggered pulse of the clock?
a) true
b) false
c) can’t be determined
d) depends on the circumstances
Answer: a
Explanation: A counter can count pulses on the positive or the negative edge of the clock.
9. Which pin is used for the input clock of the counter0?
a) PORTB.0
b) PORTB.1
c) PORTB.2
d) PORTB.3
Answer: a
Explanation: In ATmega32/16, T0 is the alternative function of PORTB.0. T0 is Timer/Counter 0 External Clock In
put.
10. Which resource provides the clock pulse to AVR timers if CS02-00=6?
a) internal clock of the AVR
b) external clock of the AVR
c) none of the mentioned
d) all of the mentioned
Answer: b
Explanation: The External clock is used for providing the pulse to the AVR timers if CS02-00=6.
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1. On reset, what are the contents of the SREG register?
a) 00h
b) ffh
c) 1fh
d) 11h
Answer: a
Explanation: On reset, all the interrupts are masked and so the contents of the SREG register is also set to zero as it s
hows the status of the flags.
2. TIMSK register is used for?
a) knowing the status of the timer count
b) used for masking the interrupts flags of the Timer0, Timer1 and Timer2
c) it is used for enabling all the timer interrupts
d) it is used for resetting the value of the interrupts
Answer: b
Explanation: TIMSK is used for masking the interrupt flags of the timers. They mask the bits of the timer flags if the
D7 bit of the SREG register is set to 1 or when firstly all interrupts are enabled.
3. Why RETI instruction be the last instruction of ISR?
a) because it returns with carry
b) because it returns to the main program with all the flags of the SREG raised
c) because it returns to the main program where interrupt is generated and set the global interrupt enable bit in SRE
G
d) none of the mentioned
Answer: c
Explanation: When an interrupt occurs, the global interrupt enable bit is cleared. If global interrupt enable is cleared
it means interrupts are disabled. RETI instruction must last instruction of ISR because it returns to the main program
where interrupt is generated and sets the global interrupt enable bit in SREG.
4. In AVR what is the ISR address for an external hardware interrupt?
a) 0002h
b) 0004h
c) 0006h
d) all of the mentioned
Answer: d
Explanation: The ISR addresses for the external hardware interrupts are 0002h, 0004h, 0006h.
5. What is the address in the interrupt service routine assigned for the timer0 overflow flag?
a) 0012h
b) 000Ah
c) 0016h
d) all of the mentioned
Answer: c
Explanation: 0016h is the address in the interrupt service routine assigned for the timer0 overflow flag.
6. Is the same address is assigned for the timer0 and timer1 overflow flag in the interrupt vector table of the interrupt
s?
a) true
b) false
c) can’t be determined
d) depends on the situation
Answer: b
Explanation: Different addresses are assigned for Timer0 and Timer1 overflow flags in the interrupt vector table. Th
ey are 0016h and 0012h for timer0 and timer1 respectively.
7. External hardware interrupts are assigned to which pins of the atmega32?
a) PORTD.2
b) PORTD.3
c) PORTB.2
d) All of the mentioned
Answer: d
Explanation: There are three external hardware interrupts in the atmega32 microcontrollers. They are assigned to bit
s PORTD.2, PORTD.3 and PORTB.2.
8. Which register is responsible for handling all the external hardware interrupts?
a) TIMSK
b) GICR
c) MCUCR
d) IVCE
Answer: b
Explanation: GICR register is responsible for all the external hardware interrupts in the AVR.
9. By default, INT0-INT2 interrupts are?
a) edge triggered
b) level triggered
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: By default, INT0-INT2 are the level triggered pulses. The low level of the pulse generates the interrupt
.
10. What will happen in that condition, if an interrupt occurs while the microcontroller is serving any other interrupt
?
a) both the interrupts will be handled simultaneously
b) the interrupt which is being done first will be served first
c) the interrupt that is more priority in the interrupt vector table will be served first
d) the interrupt having low priority in the interrupt vector table will be served first
Answer: c
Explanation: If two or more interrupts occur simultaneously then the interrupt that is having more priority in the inte
rrupt vector table will be served first.
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1. What actually are the DB9, DB25 ports available in our computers?
a) they are connectors used to transfer data either serially or parallelly
b) they are the RS232 connectors used to connect two incompatible devices
c) they are the TTL logic connector pins used for communication
d) they are just data transfer pins used to transfer the data
Answer: b
Explanation: DB9 and the DB25 ports are the ports that are based on the RS232 logic that is basically used for com
municating two incompatible devices.
2. What does RI handshaking signal refer to according to the RS232 logic?
a) if this logic is high then a receive interrupt is generated
b) this pin is high during transmission
c) this pin is high during a reception in order to tell that the device is busy at this particular time
d) none of the mentioned
Answer: c
Explanation: RI pin of the RS232 logic tells us about the ring indicator i.e it sends a busy signal if the device is curre
ntly receiving any data.
3. What is the major difference between a MAX232 and a MAX233 device?
a) one has one serial port other has two
b) one has inbuilt UART other doesn’t have that
c) one needs some additional circuitry to operate while the other doesn’t have that
d) one is used just for transmission while the other is used for both transmission as well as reception
Answer: c
Explanation: MAX232 needs some extra capacitors at pins like 1,2 and 3,4 while on the other hand MAX233 has th
at inbuilt capacitors built inside it only.
4. Which of the following is correct about the baud rate during serial transmission?
a) it tells us about the speed at which the transmission is going to place
b) it tells us about the number of bits transferred during a second
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: Baud Rate tells us about the speed in which the transmission is being done and this speed is measured i
n terms of bits per second.
5. With fosc=8 MHz, what will the count that has to filled in the UBRR register to account for the 9600 baud rate?
a) 67H
b) CEH
c) 33H
d) 34H
Answer: c
Explanation: The count that had to be filled in the UBRR register is calculated as (fosc/16(desired baud rate))-1.
6. The USART in AVR based microcontrollers operate at which of the following modes?
a) double speed asynchronous mode
b) master synchronous
c) slave synchronous
d) all of the mentioned
Answer: d
Explanation: The USART in AVR consists of the following modes. They are the normal asynchronous mode, doubl
e speed asynchronous mode, slave synchronous and the master synchronous mode.
7. Which bit of the UCSRA is used for doubling the baud rate of the transmission?
a) DOR
b) PE
c) U2X
d) MPCM
Answer: c
Explanation: U2X bit of the UCSRA is used for doubling the baud rate of the transmission.
8. What is the use of the PE and the FE bits of the UCSRA register?
a) they are used for keeping a check at the speed of transmission and reception
b) they are used for keeping a check at the data bits to be transferred
c) they are used to keep the transmission error free
d) they are used as extra redundant bits with no use
Answer: c
Explanation: PE and the FE bits of the UCSRA register are used for error checking in the transmission.
9. Which of the following bits are used for setting the data frame size?
a) UCSZ0
b) U2X
c) DOR
d) MPCM
Answer: a
Explanation: UCSZ0 and UCSZ1 bits of the UCSRB register and the UCSZ2 bit of the UCSRC register are used for
setting the data frame size in AVR based microcontrollers.
10. Which of the following parameters should the transmitter and the receiver agree upon before starting a serial tran
smission?
a) baud rate
b) frame size
c) stop bit
d) all of the mentioned
Answer: d
Explanation: Before starting the serial transmission, the following parameters should be taken care of. They are the b
aud rate, frame size, stop bit and the parity bit.
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1. In AVR, the LCD operates in two main modes, it can be in 8 bit or 4 bit data.
a) true
b) false
c) depends on the situation
d) can’t be said
Answer: a
Explanation: In AVR, the LCD operates in two main modes, they are in the 8 bit data transfer mode and the 4 bit dat
a transfer mode.
2. What can be the sequence of commands that may be used for initializing an LCD?
a) 0x06, 0x0e, 0x01
b) 0x0e, 0x01, 0x80
c) 0x38, 0x0e, 0x01
d) all of the mentioned
Answer: c
Explanation: For initializing an LCD, we can use commands like 0x38 for selecting the 5*7 matrix, 0x0e for display
on and the cursor blinking and 0x01 for clearing the screen.
3. When the LCD operates in the 4 bit mode, then what more commands are added to it?
a) 33
b) 32
c) 28
d) all of the mentioned
Answer: d
Explanation: When an LCD operates in the 4 bit mode than 33, 32, 28 in hex are sent to it. They represent 3, 3, 3, 2
nibbles which tell the LCD to do into the 4 bit mode for saving the i/o pins of the port.
4. What is the main function of the LPM instruction used in LCD?
a) for initializing the LCD in the read mode
b) for initializing the LCD in the write mode
c) for sending a long string of characters to the LCD
d) all of the mentioned
Answer: c
Explanation: LPM instruction is used for sending a long string of characters to the LCD.
5. The RS pin acts as an
a) input pin
b) output pin
c) any of the mentioned depending on the conditions
d) none of the mentioned
Answer: a
Explanation: The RS pin of the LCD is used for selecting a particular register used for sending a command or the dat
a to the LCD.
6. To latch in information at the data pins of the LCD, we send
a) H-L pulse at the E pin
b) L-H pulse at the E pin
c) A constant H pulse at the E pin
d) A constant L pulse at the E pin
Answer: a
Explanation: For latching in information at the data pins of the LCD, we send a H-L pulse at the LCD.
7. What is the function of the 0x06 command?
a) to clear the LCD
b) to blink the cursor
c) to shift the cursor to the right
d) for selecting the matrix
Answer: c
Explanation: 0x06 command is used for shifting the cursor to the right after every data send to it.
8. What is the address of the second column and the second row of the 2*20 LCD?
a) 0x80
b) 0x81
c) 0xc0
d) 0xc1
Answer: d
Explanation: 0xc0 acts as the address for selecting the second row and the first column of the LCD, so according to i
t if we need to select the second row and the second column of the LCD, then the address should be 0xc1.
9. Which of the following commands takes more than 100 microseconds to run?
a) shift cursor left
b) shift cursor right
c) set address location of the DDRAM
d) clear screen
Answer: d
Explanation: Clear screen is a command that takes more than 100 microseconds to run.
10. For selecting the data pins in an LCD, RS pin should be
a) 1
b) 0
c) F
d) 10
Answer: a
Explanation: For selecting the data pins of the LCD, the RS pin of the LCD should be set to 1.
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1. In reading the columns of a keyboard matrix, when no key is pressed then all the pins show?
a) 0
b) 1
c) F
d) 7
Answer: b
Explanation: When no key is pressed, in a keyboard then all the pins will read 1 as they all are connected to the main
power supply.
2. To see if any key is pressed, all rows are grounded.
a) true
b) false
c) can’t be said
d) depends on the conditions
Answer: a
Explanation: To see that whether any key is pressed or not then all the rows are grounded so that columns can be rea
d to deliver the better results.
3. Identify the row and the column for the following case when for the row D3-D0= 1110 and for the column D3-D0
= 1101
a) first row and second column
b) first row and third column
c) second row and first column
d) second row and second column
Answer: a
Explanation: To identify the key that is pressed from this particular combination, we obtain that the key belongs to t
he first row and the second column as the D0 bit of the row port and the D1 bit of the column port are zero.
4. What are the actual steps that are followed in identifying any key that is being pressed?
a) wait for the debounce time
b) identify the key that is pressed
c) initially no key should be pressed
d) all of the mentioned
Answer: d
Explanation: In order to identify that which key is actually pressed form a particular format of a 3*3 matrix keyboar
d, we firstly ensure all initially all the keys are open, then we press a key and check that whether the key is actually
pressed or not by waiting for a time span of 20mseconds, after this we identify the key that is pressed by masking th
e bits of the port. In this particular format, we can identify the key that is actually pressed.
5. To identify that the key is present in which row and the column
a) we ground the bits of the row one by one
b) we ground the bits of the column one by one
c) we connect the bits of the row to the logic level 1 one by one
d) we can connect the columns to the logic level 1 one by one
Answer: a
Explanation: To determine that the pressed key is in which row and column, we ground the rows one by one to deter
mine the column by masking the bits separately.
6. The key detection and the key identification are two different procedures?
a) true
b) false
c) depends on the circumstances
d) difficult to tell
Answer: a
Explanation: The key detection and the key identification are the two different procedures, one is used to detect that
whether any key is pressed or not and the other technique is used to find that the pressed key is located in which row
and column.
7. What is described by the following command?
a) load KCODE0 with 0
b) rotate the contents of the KCODE0 register to the right
c) rotate the contents of the KCODE0 register to the left
d) none of the mentioned
Answer: b
Explanation: KCODE0<<1 means to rotate the contents of the KCODE0 register to the left after every loop.
8. If the pins of the keyboard are used as an interrupt, then these pins will cause an interrupt of what type?
a) External hardware interrupt
b) Timer interrupt
c) TI/RI interrupt
d) None of the mentioned
Answer: a
Explanation: The pins of the keyboard act as an external hardware interrupt as some external pulse is helping in gene
rating this interrupt.
9. What will happen if the two keys of the keyboard are pressed at a time?
a) both the keys will be displayed on the screen
b) the key which is being actually pressed(for more then 20microseconds) will be displayed
c) the key that is pressed first will be displayed
d) none of the mentioned
Answer: b
Explanation: If two or more keys are pressed at a time, then the key that will be pressed for more then 20 microseco
nds will be displayed on the screen.
10. Why initially all keys are considered open before detecting the key pressed?
a) to make the task easy
b) to remove the errors caused by other pressing keys during detection
c) to remove the flow problems
d) none of the mentioned
Answer: b
Explanation: Initially all keys are considered open in order to ensure the accuracy while identification of the pressed
key.
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1. Which of the following is correct about the word resolution in ADC DAC converters in AVR’s?
a) it is the smallest change that can be described by an ADC
b) it is equal to Vref/2n (where n represents the number of bits)
c) it is 0.076mV or 76uV for n=16 and Vref=5V
d) all of the mentioned
Answer: d
Explanation: Resolution is defined as the smallest change in the step size that is described by an ADC, it is equal to
Vref/2n.
2. In an ADC, we can calculate the output voltage from the formula
a) Step size / Vin
b) Step size * Vin
c) Vin / step size
d) Vref / step size
Answer: c
Explanation: The output voltage can be calculated by using the formula Vin / step size.
3. ADC0848 is a ____________ bit converter?
a) 16
b) 4
c) 8
d) 48
Answer: c
Explanation: ADC0848 is a 8 bit converter.
4. Which of the following factors can affect the step size calculation?
a) number of bits
b) input current
c) output current
d) all of the mentioned
Answer: a
Explanation: There are mainly two factors that can affect the step size calculation of an ADC converter, they are the
number of bits and the Vref voltage.
5. MAX1112 is a _________ type of ADC converter?
a) parallel
b) 12 bit
c) serial
d) all of the mentioned
Answer: c
Explanation: MAX1112 is a serial ADC converter, as it has only one pin for the data output.
6. Why do we connect a capacitor between the Vref and the Gnd pin?
a) to remove the leakage
b) to ensure more current at that place
c) to make more Vref
d) to make Vref stable and also to increase the precision of the ADC
Answer: d
Explanation: A capacitor is connected between the Vref and the Gnd pin in order to stabilize the Vref value and also
to increase the precision of the ADc converter.
7. Which of the following are the registers that are used for controlling the ADC conversion in the AVR?
a) ADCSRA
b) ADMUX
c) SPIOR
d) All of the mentioned
Answer: d
Explanation: For programming the ADC conversion in an AVR, we require the following registers. They are ADCS
RA, ADMUX, SPIOR. There are two more registers used for handling the output data, they are ADCH and ADCL r
egisters.
8. What is the internal Vref of an Atmega32 series?
a) 5V
b) 3.3V
c) 2.56V
d) all of the mentioned
Answer: c
Explanation: 2.56V is the internal Vref selected for an Atmega32 series based microcontrollers.
9. The output of a DAC0808 is in the form of ____________
a) electrical pulse
b) current
c) voltage
d) all of the mentioned
Answer: b
Explanation: The output of a DAC0808 is in the form of a current.
10. In a DAC the input is ______ and the output is ______
a) analog, digital
b) current, voltage
c) digital, analog
d) analog, current
Answer: c
Explanation: In a DAC, the input is digital and the output is analog in nature.
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1. Which of the following is correct about the word sensors?
a) that senses something
b) it is a type of a transducer that converts one form of energy to another
c) it can produce output in the form of electrical pulses, current or voltage
d) all of the mentioned
Answer: d
Explanation: Sensors are the devices that are used to sense a particular thing by converting one form of energy into a
nother, this converted form can be in the form of some analog output, or in the form of current or the voltage as the c
ase may be.
2. Why do we need to apply the concept of signal conditioning to a sensor?
a) in order to convert it into a desirable form of energy
b) for testing
c) for sensing something
d) all of the mentioned
Answer: a
Explanation: Signal Conditioning is the concept that is used for data acquisition of the signal. For measuring and ana
lyzing this value at a practical stage, by converting it into a desirable form of energy.
3. Which of the following is correct about LM35 based sensors?
a) its output voltage is directly proportional to the Celsius scale
b) its output voltage is directly proportional to the Fahrenheit scale
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: LM35 based sensors are those sensors whose output voltage is directly proportional to the Celsius scale
.
4. What is the difference between the LM34 and the LM35 based sensors?
a) one requires external calibration while other does not
b) one has output voltage proportional to the Celsius scale while others have to the Fahrenheit scale
c) one is fast other is slow
d) all of the mentioned
Answer: b
Explanation: LM35 has the output voltage proportional to the Celsius scale while the LM35 based sensors have outp
ut voltage proportional to the Fahrenheit scale.
5. Every transducer must be connected with the signal conditioning circuit?
a) true
b) false
c) can’t say
d) depends on the conditions
Answer: a
Explanation: For analyzing purposes, every transducer must be connected to a signal conditioning circuit in order to
measure its value as a practical platform.
6. LM35 provides _______ V for each degree count?
a) 1
b) 0.1
c) 0.001
d) 10
Answer: c
Explanation: LM35 provides 10mV for every degree change of the Celsius scale.
7. Why for the 8 bit analog input we select Vref as the 2.56V?
a) to obtain each degree count as the 2.56V
b) to get 2.56V at the output
c) to obtain each degree count as the 10mV
d) to get 10mV as the output
Answer: c
Explanation: For an 8 bit analog input, each degree count is calculated as the Vref/256, so if Vref is selected as 2.56
V then we can obtain 10mV for each degree count of the scale.
8. What is the temperature for LM35 sensor if the analog output is 0011 1001?
a) 3
b) 9
c) 57
d) 41
Answer: c
Explanation: The binary for the above output is 57, so in case of LM35 sensors we obtain the output as 57 C.
9. In an external hardware, there are how many pins available for the LM35 and the LM34 based sensors?
a) 2
b) 3
c) 10
d) 1
Answer: b
Explanation: LM35 consists of mainly 3 pins, they are Vcc, Gnd, analog output.
10. Do LM34 and LM35 based sensors have linear output?
a) yes
b) no
c) depends on the conditions
d) can’t say
Answer: a
Explanation: LM34 and the LM35 based sensors are linearly proportional to their corresponding Fahrenheit and the
Celsius scale, so they are linear by nature.
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1. The 8255 is a ______ chip.
a) Input/Output
b) Analog to Digital
c) Digital to analog
d) None of the mentioned
Answer: a
Explanation: The 8255 is Input/Output (I/O) chip. It has three separate accessible ports. The 8255 chip is used to exp
and the I/O ports of microcontrollers.
2. Which pins of a microcontroller are directly connected with 8255?
a) RD
b) WR
c) D0-D7
d) All of the mentioned
Answer: d
Explanation: RD, WR, D0-D7 all are directly connected to the 8051 for telling the chip about the control signals and
also for transferring the data.
3. Find the control word for PA= out, PB= in, PCL=out, PCH=out (Mode0)?
a) 0x02H
b) 0x82H
c) 0x83H
d) 0x03H
Answer: b
Explanation: The value that is being loaded in the control word is 10000010b for PB as an input port and all others a
s the output ports being operated in mode0. The hex equivalent of 10000010b → 0x82H.
4. Which pins are used to select the ports and the control register?
a) CS
b) A1
c) A0
d) All of the mentioned
Answer: d
Explanation: CS pin is an active low input pin for 8255 and it is used for selecting a chip. A0 and A1 pins are used f
or select ports and the control register.
5. What is the value of the control register when RESET button is set to zero?
a) 0x00H
b) 0xFFH
c) 0x11H
d) value remains the same
Answer: d
Explanation: RESET is active-high signal input into the 8255 used to clear the control register. When RESET is acti
vated (i.e. set to high), all ports are initialized as input mode. Hence the value of the control register remains the sam
e as it is even when the RESET button is set to zero.
6. Why MOVX instruction is being used to access the ports of the 8255?
a) because 8255 is connecting a microcontroller in memory mapped I/O configuration
b) because 8255 is used to access the external communication
c) because 8255 is used to access the data transfer
d) because 8255 is used to access the interfacing of LCD, motor etc
Answer: a
Explanation: As 8255 is connecting a microcontroller in memory mapped I/O configuration. This means that memor
y space used to access 8255 (i.e. 8255 is treated as external memory). MOVX instruction is used to access external
memory locations.
7. What is correct about the BSR mode from below?
a) In BSR mode, only the individual bits of PORT A can be programmed
b) In BSR mode, only the individual bits of PORT B can be programmed
c) In BSR mode, only the individual bits of PORT C can be programmed
d) none of the mentioned
Answer: c
Explanation: BSR (Bit Set/Rest) mode is used to program individual bits of PORT C only.
8. How many pins of the 8255 can be used as the I/O ports?
a) 8
b) 16
c) 24
d) 32
Answer: c
Explanation: They are 3 ports available in the 8255 so 24 pins are available for the I/O ports pins.
9. 8255 is a ____ pin IC.
a) 16
b) 8
c) 40
d) 60
Answer: c
Explanation: 8255 is a 40 pin IC.
10. 8255 has handshaking capability?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: 8255 is a device that with the help of its handshaking property gets interfaced with any microcontroller
.
11. The 8255 can be programmed in any of the __________
a) 2 modes
b) 3 modes
c) 4 modes
d) 5 modes
Answer: c
Explanation: 8255 can be programmed in any of the 4 modes.
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1. RTC is used for __________
a) conversion
b) communication
c) real time and clock measurement
d) memory management
Answer: c
Explanation: RTC is a device that is basically used for all the real time clock related issues.
2. RTC chips use ______ to compute time, date when the power is off.
a) ac supply
b) generators
c) rectifiers
d) battery
Answer: d
Explanation: RTC chips require batteries in order to calculate the time and date when the power of the device is off.
3. DS12887 is known for as a ________
a) Communication device
b) Good battery device
c) RTC chip
d) All of the mentioned
Answer: c
Explanation: DS12887 is known as an RTC chip.
4. DS1307 is a parallel RTC with I2C bus.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: DS1307 is a serial RTC with I2C bus.
5. DS1307 is a _______ pin IC and operates on _______ clock frequency.
a) 16, 8Mhz
b) 8, 16Mhz
c) 16, 32Mhz
d) 8, 32Khz
Answer: d
Explanation: DS1307 is a 8 pin IC and operates on a 32KHz clock frequency.
6. Vbat requires a positive signal of
a) 3V
b) 5V
c) 9V
d) 12V
Answer: a
Explanation: Vbat requires a positive signal of 3V which can be obtained through a battery.
7. In DS1307, which out of the following is correct about the SQW pin?
a) input pin
b) output pin
c) i/o pin
d) none of the mentioned
Answer: b
Explanation: In DS1307, SQW pin is an output pin. It provides a clock of frequency 1khz, 4khz, 8khz, 32khz if the p
in is enabled.
8. DS1307 has a total of _______ bytes of RAM space.
a) 32
b) 64
c) 128
d) 256
Answer: c
Explanation: DS1307 has a total of 64 bytes(00-3F) of RAM space.
9. DS1307 control register has an address of _________
a) 00H
b) 03H
c) 07H
d) 10H
Answer: b
Explanation: DS1307 control register has an address of 07H.
PSST! You better watch out, something's buggy above.
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1. Why are relays used for driving the motors?
a) they can be used as switch as well as they provide isolation
b) they increase the current capability required by the motors
c) they are used to reduce the back emf from the motors
d) all of the mentioned
Answer: a
Explanation: Relay is the electrically controlled switch and it allows isolation of two separate sections of the system.
It has three main components: the coil, the common pole and the contacts. When an electric field is applied to the c
oil; it gets energized and generates a magnetic field which will force the common pole to change contact from Norm
ally Closed to Normally Open.
2. Why are ULN2803 normally used between the microcontrollers and the relays?
a) for switching purposes
b) for increasing the current capability required by a relay
c) for increasing the voltage capability required by a relay
d) all of the mentioned
Answer: b
Explanation: More current is desired for driving a motor with the help of a relay, so a ULN2803 is used for increasin
g the current as per the requirement of the relay.
3. Why are opto isolators normally used between the microcontrollers and the ULN2803?
a) to optimize the current
b) to reduce the back emf
c) to increase the current
d) to increase the voltage
Answer: b
Explanation: Opto isolators are used between the microcontrollers and the ULN2803 chips in order to decrease the b
ack emf from the ULN2803 and to save the microcontrollers for a long time.
4. Which of the following is a type of an electromagnetic relay?
a) SPST
b) SPDT
c) DPDT
d) All of the mentioned
Answer: d
Explanation: There are normally three kinds of electromagnetic relays. They are SPST(single pole single throw), SP
DT(single pole double throw) and the DPDT(double pole double throw) relays.
5. Reed switches show connectivity whenever they are in the presence of an electrical field?
a) true
b) false
c) can’t say
d) depends on the conditions
Answer: b
Explanation: Reed switches are the devices that show connectivity whenever they are in the presence of some magne
tic field.
6. Which of the following is an application of stepper motors?
a) in printers
b) in robots
c) in vehicles
d) all of the mentioned
Answer: d
Explanation: Stepper motors are used wherever there is a need of a movement at an angle, maybe it in printers, in m
otors or in vehicles stepper motors are used everywhere.
7. What are normal 4 step sequence of a stepper motor if we start to move in clockwise direction with 0110 value?
a) 1100,1001,0011,0110
b) 0011,1001,1100,0110
c) 1001,1100,0110,0011
d) 0101,1010,0101,1010
Answer: b
Explanation: For a normal 4 step sequence of a stepper motor, if we start to move in a clockwise direction then we r
otate towards right direction with every rotation.
8. What is the meaning of a step angle?
a) angle which a stepper motor has
b) angle between the two windings of the stator in a stepper motor
c) minimum degree of rotation associated with a single step
d) angle between the stator and the rotor
Answer: c
Explanation: Step angle is the minimum degree of rotation associated with a single step.
9. For a normal 4 step sequence, what are the number of teeth required to accomplish a 2 degree step angle?
a) 180
b) 90
c) 360
d) 45
Answer: d
Explanation: For a 2 degree step angle there will be 180 step per rotation, so the total number of rotor teeth are (180/
4=45).
10. Ounch-inch is a unit of a torque.
a) true
b) false
c) can’t say
d) depends on the situation
Answer: a
Explanation: Torque is a quantity which is obtained by multiplying the amount of force that is applied at a particular
angle. It is measured in terms of ounch-inch.
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1. Why do we make the connection of the SCLK for communicating serially between two devices?
a) to get a clock output from the device
b) to synchronize the two devices
c) to obtain an analog output
d) all of the mentioned
Answer: d
Explanation: We need an SCLK in order for the two devices to communicate with each other properly. It acts as a p
ulse according to which one device sends a message and the other receives it.
2. What is the function of the CE pin in SPI?
a) it is used for synchronization
b) it is used as a transmitting pin
c) it is used as a receiving pin
d) it is used to initiate and terminate the data transfer
Answer: c
Explanation: CE pin is used to initiate and terminate the data transfer in the controller via SPI interface.
3. Which of the following is correct?
a) MOSI has the same meaning as the SDO
b) SCLK is used to initiate and terminate the data transfer
c) In 3 wire SPI, there is only one pin for transmission and reception
d) In 3 wire SPI, there are three pins MOSI, MISO and SCLK
Answer: b
Explanation: In 3 wire SPI, there is only one pin for transmission and reception and the other two pins SCLK and C
E are used for synchronization of data and for initialization and termination of data.
4. If CPHA= 0 and CPOL=1, then which of the following is true?
a) read on rising edge, changed on a falling edge
b) read on falling edge, changed on a rising edge
c) write on rising edge, changed on a falling edge
d) write on rising edge, changed on a falling edge
Answer: b
Explanation: If CPOL= 1 and CPHA= 0, then reading operation is performed on the rising edge and the change occu
rs at every falling edge.
5. In SPI write, LSB goes first?
a) true
b) false
c) can’t be said
d) depends on the cases
Answer: d
Explanation: In SPI write, MSB goes first.
6. In AVR, which of the following registers are used for SPI?
a) SPSR
b) SPCR
c) SPDR
d) All of the mentioned
Answer: b
Explanation: In AVR, SPSR(SPI Status Register), SPCR(SPI Control Register) and SPDR(SPI Data Register) are us
ed for programming the SPI module.
7. How do we set the SPI, to operate in the master mode 1?
a) We set the MSTR bit, and make the CPOL= 1 and CPHA=0
b) We set the MSTR bit, and make the CPOL= 0 and CPHA=1
c) We reset the MSTR bit, and make the CPOL= 1 and CPHA=0
d) We reset the MSTR bit, and make the CPOL= 0 and CPHA=1
Answer: b
Explanation: In SPI, to make it work in the master mode, we make the MSTR bit is equal to 1 and for operating it in
the mode 1 we make the CPOL=0 and CPHA=1.
8. SPI can act as a half duplex transmission?
a) true
b) false
c) depends on the conditions
d) can’t be said
Answer: d
Explanation: No, SPI can’t work in the half duplex transmission mode.
9. Which frequency is not recommended for SPI clock?
a) fosc/4
b) fosc/64
c) fosc/16
d) fosc/2
Answer: a
Explanation: fosc/2 is not recommended frequency for SPI transfer in AVR.
PSST! You better watch out, something's buggy above.
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1. Which of the following is correct?
a) I2C is a technique by which data is transmitted with the help of only eight pins
b) SDA is used to synchronize data transfer between two chips
c) TWI is another name for I2C
d) All of the mentioned
Answer: c
Explanation: I2C is a technique by which data is transmitted between two devices by the help of only 2 pins so it is a
lso called Two wire Serial Interface.
2. Which of the following is true about the I2C protocols?
a) the data line cannot change when the clock line is high
b) the data line can change when the clock line is high
c) the clock line cannot change when the data line is high
d) the clock line can change when the data line is high
Answer: a
Explanation: According to I2C protocols, the data line(SD
a) changes only if the clock line(SCL) is at its active low level.
3. I2C is a connection oriented communication protocol.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: I2C is a connection oriented protocol i.e each transmission is initiated by a START condition and is ter
minated by a STOP condition.
4. The STOP condition is generated by a
a) high to low change in the SDA line when the SCL is low
b) high to low change in the SDA line when the SCL is high
c) low to high change in the SDA line when the SCL is low
d) low to high change in the SDA line when the SCL is high
Answer: c
Explanation: The STOP condition is generated when there is a low to high change in the SDA line when the SCL is l
ow.
5. For receiving the acknowledgment
a) SDA from the transmitter should be high
b) SDA from the transmitter should be low
c) SDA from receiver should be high
d) SDA from receiver should be low
Answer: d
Explanation: The packet format in I2C consists of 9 bits, out of which first 8 are the data bits while the ninth bit is th
e acknowledgment bit. For obtaining the acknowledgment, the SDA line of the receiver should be pushed to low.
6. What steps are followed to complete the data transfer?
a) START condition, STOP condition
b) Address packet
c) One or more data packet
d) All of the mentioned
Answer: d
Explanation: For having the complete data transfer, the steps that are actually being followed are START condition,
address packet, one or more data packet, STOP condition.
7. I2C is ideal for short distances?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: I2C is that module of the AVR, which is used for short distances.
8. Which of the following is a register used for programming AVR’s I2C module?
a) TWBR
b) TWCR
c) TWSR
d) All of the mentioned
Answer: d
Explanation: TWBR( TWI Bit rate register), TWCR( TWI Control Register), TWSR(TWI Status Register), TWAR(
TWI Address Register), TWDR( TWI Data Register) are used for programming an AVR’s I2C module.
9. Which bit is polled to know that whether the TWI is ready or not?
a) TWWC
b) TWINT
c) TWEA
d) All of the mentioned
Answer: b
Explanation: TWINT is the bit that is polled to know that whether the TWI is ready or not.
PSST! You better watch out, something's buggy above.
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1. In MSP430, the size of the status register is ________
a) 1 byte
b) 2 bytes
c) 1 bit
d) 2 bit
Answer: b
Explanation: In MSP430, the size of the status register is 2 bytes. The bits of the status register consists of the C flag
, Z flag, N flag, GIE flag, CPU off, OSC off, SCG0, SCG1, V flag and 7 reserved bits.
2. Which of the following bit/s of the status register that allows the microcontroller to operate in its low power mode
?
a) Z
b) Reserved
c) CPU off
d) N
Answer: d
Explanation: The CPU off bit, OSC off bit, SCG0 bit, SCG1 bit of the status register are used to allow the microcont
roller to operate in its low power mode.
3. What is actually done to improve the efficiency of a RISC processor?
a) instructions are reduced
b) they have two or more processors inbuilt connected between
c) they have many instructions that are interrelated to each other
d) they have one or more registers hard wired to the commonly used values
Answer: d
Explanation: To improve the efficiency of the RISC processor, the registers that are hard wired to commonly used v
alues are used instead of other ones.
4. To improve the efficiency of an MSP430 based microcontroller, for one register
a) there is only one value for all addressing modes
b) there are two values for each addressing mode
c) there are 2 values for four addressing modes
d) there are 4 values for four addressing modes
Answer: d
Explanation: In MSP430, there are namely 4 addressing modes. So the main advantage of this controller( which basi
cally increases its efficiency )is that for one register their exists 4 different values for 4 different addressing modes o
f the controller.
5. Their are_______________ number of emulated instructions found in the MSP430?
a) 4
b) 8
c) 16
d) 24
Answer: c
Explanation: The constants CG1 and CG2 are combined together to give 27 native instructions. These instructions ar
e further converted into 24 emulated instructions. So, there are 24 emulated instructions found in an MSP430 based
controller.
6. .w form is used for operations
a) that uses bytes
b) that uses words
c) that uses both
d) that uses none
Answer: b
Explanation: .w form is used for operations, that uses both bytes and words for operations.
7. Pre increment addressing is available in MSP430?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: MSP430 supports only post increment addressing. For performing pre increment addressing, we requir
e some special functions that accomplish that work.
8. Which out of the following is a correct emulated instruction?
a) ADC(.
b) dst
b) ADD(.
b) src,dst
c) ADDC(.
b) src,dst
d) AND(.
b) src,dst
Answer: a
Explanation: “ADC(.
b) dst” this is emulated to “ADDC.B #0,dst” hence this is an emulated instruction. The emulated instructions use cor
e instructions combined with the architecture and implementation of the CPU for higher code efficiency and faster e
xecution.
9. dadd instruction can act as _____________
a) valid BCD addition
b) valid adder with carry
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: Dadd instruction can act as a valid BCD addition instruction if the numbers are initially in BCD state(0
-9).
PSST! You better watch out, something's buggy above.
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1. There are _____ number of addressing modes found for the source and _____ number of modes for the destinatio
n part.
a) 4,4
b) 2,4
c) 7,4
d) 2,2
Answer: c
Explanation: In MSP430, Seven addressing modes for the source operand and four addressing modes for the destinat
ion operand can address the complete address space with no exceptions.
2. MSP430 describes reti instruction as ___________
a) Format1 addressing
b) Format2 addressing
c) Jump addressing
d) None of the mentioned
Answer: b
Explanation: MSP430 describes reti instruction as that type of addressing which consists of only single operand, so i
t comes under Format2 addressing.
3. mov.w R3, R4 takes _________
a) one cycle
b) two cycles
c) four cycles
d) eight cycles
Answer: a
Explanation: mov.w R3, R4 takes only one cycle to transfer the data from register R3 to R4. This type of mode of ad
dressing is called the register mode of addressing.
4. Indexed addressing can be used for _________
a) source
b) destination
c) source & destination
d) none of the mentioned
Answer: c
Explanation: Indexed addressing is used for both the source and the destination addresses.
5. What do you understand form this instruction mov.w X(PC), R6
a) R6 = X+PC
b) R6 = PC-X
c) R6 = -X-PC
d) R6 = -X+PC
Answer: a
Explanation: This instruction mov.w X(PC), R6 means that the contents of X+PC address are copied to the R6 regist
er.
6. Absolute mode uses which of the following operators?
a) %
b) /
c) $
d) &
Answer: d
Explanation: Absolute mode uses the & operator to transfer a constant to a register.
7. Indirect register mode is used by _________
a) source register
b) destination register
c) source & destination register
d) none of the mentioned
Answer: a
Explanation: Indirect addressing mode is used only by the source register.
8. Indirect mode and the indirect auto increment mode have which common operator in them
a) +
b) –
c) @
d) &
Answer: c
Explanation: Both the indirect and the indirect auto increment mode use the @ operator for the source register to tra
nsfer the data from one memory location to a register.
9. Are the following two instructions similar?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: MOV @R10,0(R11) → Move the contents of the source address (contents of R10) to the destination ad
dress (contents of R11).
10. MOV @R10,0(R11) is a type of ________
a) Register Mode
b) Indirect Register Mode
c) Immediate Mode
d) Indirect Autoincrement Mode
Answer: b
Explanation: The type of given instruction is Indirect Register Mode.
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1. Which instruction is used to call functions?
a) MOV
b) GO
c) CALL
d) All of the mentioned
Answer: c
Explanation: CALL instruction is used for going to a particular address in MSP430. It actually causes the pointer to j
ump at a particular address and push the current address of the PC to the stack.
2. ret instruction is used for _________
a) determining the end of the program
b) for returning back from the subroutine to the main program
c) for transferring data from one place to another
d) none of the mentioned
Answer: b
Explanation: Ret instruction is basically used for returning back from a subroutine. It actually pops the top address fr
om the stack and moves that address to its PC, so that it now returns to the main program and continue the execution
normally.
3. According to conventions being followed, R12 to R15 are used for _________
a) parameter passing
b) preserved for call
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: According to the conventions, R12 to R15 are used for parameter passing and hence are not preserved f
or the call.
4. We can store the temporary results across a call instruction with the help of which of the following registers
a) R1-R4
b) R4-R11
c) R12-R15
d) All of the mentioned
Answer: b
Explanation: Temporary results are stored by the registers R4-R11.
5. Can we allocate variables on the stack?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, we can allocate the variables on the stack, it is a very effective way of storing the variables.
6. Which registers are reserved for passing the parameters to a subroutine and then returning the final result?
a) R1-R4
b) R4-R11
c) R12-R15
d) All of the mentioned
Answer: c
Explanation: Originally, R12-R15 registers are reserved for passing the parameters to a subroutine and then returnin
g the final result.
7. What actually is the order of stack frame for a parameter to pass to a subroutine?
a) parameter passed to a subroutine
b) return address
c) saved copies of registers(R4-R11)
d) all of the mentioned
Answer: d
Explanation: All the steps i.e. parameter passed to a subroutine, return address, saved copies of registers(R4-R11), lo
cal variables in subroutines are required for passing a parameter to a subroutine.
8. When any subroutine is called, then the first value of stack will be
a) value of PC
b) the return address
c) none of the mentioned
d) both are one and the same things
Answer: d
Explanation: When any subroutine is called then the first place of the stack will be filled with the return address, or t
he address of the PC so that the pointer may return back to its appropriate place after the return instruction of the sub
routine.
9. Which of the following instruction/s is/are used to return back to the main program after the subroutine is complet
ed?
a) ret
b) reti
c) ret and reti
d) none of the mentioned
Answer: c
Explanation: For returning back from the subroutine, both ret and reti can be used, the main difference between the t
wo is that reti just resets the interrupt flag before the return, so that the interrupt can occur again.
10. Is the approach of making subroutines effective or not?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The approach of making subroutine is indeed very effective, as with its help we don’t need to retrace/w
rite a particular set of codes again and again. It makes our approach modular.
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1. MSP430 uses vectored interrupts?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: MSP430 has vectored interrupts i.e. the address of each ISR is stored in a vector table, that’s why it has
vectored interrupts.
2. Which of the following is true?
a) interrupts are required to wake a CPU from sleep
b) same vector address associated with multiple flags
c) most interrupts are maskable
d) all of the mentioned
Answer: d
Explanation: All of the above mentioned statements are true i.e. interrupts are required to wake a CPU from sleep, sa
me vector address associated with multiple flags and most of the interrupts are maskable.
3. After the interrupt has occurred, the stack is filled with ______________
a) return address
b) status register
c) return address & status register
d) none of the mentioned
Answer: c
Explanation: When an interrupt had occurred, the top place of the stack is filled with the return address, so that imm
ediately after the reti instruction the pointer moves to the main program, the stack is also filled with the bits of the st
atus register so that all the temporary values get stored in it.
4. What is the purpose of __interrupt() function?
a) it is used to enable the interrupt
b) it is used to disable the interrupt
c) it denotes that the routine is an ISR
d) all of the mentioned
Answer: c
Explanation: The purpose of __interrupt() function is to denote that the routine is an ISR.
5. What is the purpose of .intvec assembler directive?
a) it creates an interrupt vector entry that points to an interrupt routine name
b) one is used for storage, other for display
c) one stores locally other stores globally
d) the two are the same
Answer: a
Explanation: The .intvec directive creates an interrupt vector entry that points to an interrupt routine name.
6. For enabling any interrupt, firstly _____________
a) GIE=0
b) GIE=1
c) None of the mentioned
d) GIE=0 & 1
Answer: b
Explanation: If GIE is set to 1, then only other hardware interrupts are enabled.
7. Nonmaskable vectors are stored at different vector locations?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Nonmaskable interrupts are stored in the same vector location, it may be of higher or the lower priority
.
8. Which of the following can generate a nonmaskable interrupt?
a) access violation to flash memory, ACCVIFG
b) timer_A interrupt
c) compare / capture interrupt
d) all of the mentioned
Answer: a
Explanation: A nonmaskable interrupt is generated by an access violation to flash memory, ACCVIFG.
9. External RST/NMI pin is a nonmaskable interrupt?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, external RST/NMI pin is a nonmaskable interrupt( The function of the RST/NMI pin is configure
d in the control register for the watchdog timer module, WDTCTL).
10. How many cycles are used by MSP430, when reti instruction is executed?
a) 3
b) 4
c) 5
d) depends on the conditions
Answer: c
Explanation: When reti instruction is executed, five cycles are used because it firstly pops the stack register complet
ely and then takes the top of the stack into the PC to return to the next address of the main program.
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1. There are how many MSP430’s low power modes available in the chip?
a) two
b) three
c) four
d) five
Answer: d
Explanation: There are five low power modes available in the MSP430, out of which two are rarely employed in the
current devices.
2. Which of the following are the low power modes?
a) LPM0
b) LPM3
c) LPM4
d) All of the mentioned
Answer: d
Explanation: LPM0, LPM3, LPM4 all are the low power modes that are available in the MSP430.
3. Which of the following modes is also known as the RAM retention mode?
a) LPM0
b) LPM3
c) LPM4
d) All of the mentioned
Answer: c
Explanation: LPM4 is known as the RAM retention mode. Here, the CPU and all clocks are disabled, I ≈ 0.1A. The
device can be woken only by an external signal.
4. Waking a device simply means that switching that device’s operation from a low power mode to an active mode.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: When a device is operating in a low power mode, it can also be assumed that the device is sleeping, so
waking a device simply means to turn that device’s operation from a low power mode to an active mode.
5. When an interrupt is accepted, the contents of the status register are ___________
a) set
b) reset
c) remains the same
d) cant be said
Answer: d
Explanation: When an interrupt is accepted, the contents of the status register are cleared, it actually puts the process
or in the active mode.
6. Which of the following basic clock modules supplies clock signals to the MSP430?
a) ACLK
b) MCLK
c) SMCLK
d) All of the mentioned
Answer: a
Explanation: All of the mentioned options are correct. The basic clock module supplies the MSP430 with three cloc
k signals as follows:
7. _ _low_ power_mode_0() states the processor to __________
a) enable the interrupt
b) disable the interrupt
c) nothing
d) to go in an active mode
Answer: b
Explanation: _ _low_ power_mode_0() puts the processor in the LPM0 mode.
8. More power can be saved by using low_power mode 0 than low_power mode 3.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: More power is saved in low_ power mode 3.
9. _BIC_SR_IRQ() is used to _______________
a) set the particular bits of the SR
b) reset the particular bits of the SR
c) any of the above mentioned depending on the conditions
d) none of the mentioned
Answer: b
Explanation: _BIC_SR_IRQ() is used to clear the bits of the SR.
PSST! You better watch out, something's buggy above.
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1. Which of the following registers are related to port P1?
a) P1SEL
b) P1DIR
c) P1IES
d) All of the mentioned
Answer: d
Explanation: All of the mentioned registers are related to Port1.
2. A pull-up or pull-down resistor ___________
a) removes the full output drive on the output pin
b) gives only a feeble current through the pull-up to resistor
c) removes the full output drive on the output pin & gives only a feeble current through the pull-up to resistor
d) none of the mentioned
Answer: c
Explanation: A pull-up or pull-down resistor is used to remove the full output drive on the output pin. It also gives a
feeble current through the pull-up to a resistor.
3. P1.3 is the ___________
a) input CCI1A to Timer_A
b) is connected to the voltage reference VREF of SD16_A
c) is output TA0 from Timer_A
d) are digital inputs with pull-up resistors
Answer: b
Explanation: P1.3 is connected to the voltage reference VREF of SD16_A.
4. What actually is SD16_A?
a) it is an interrupt
b) it is a timer
c) it is an analog to Digital Converter
d) it is a serial communication module
Answer: c
Explanation: SD16_A is an analog to the digital module.
5. P1IE and P1IES are registers that are used to ___________
a) control the Port1 digital i/o ports
b) control the Port1 interrupts
c) control the Port1 serial communication interfaces
d) all of the mentioned
Answer: b
Explanation: P1IE and P1IES both registers are used to control the Port1 interrupts.
6. Unused pins must never be left unconnected in their default state as inputs.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Unused pins must never be left unconnected in their default state as inputs. This follows a general rule
that inputs to CMOS must never be left unconnected or “floating”.
7. Which of the following is an effect of a Schmidt trigger?
a) it turns slowly varying inputs, which might cause problems while they pass slowly through the undefined range of
input voltages, into abrupt, clean logical transitions
b) It eliminates the effect of noise on the input, provided that it is not large enough to span the gap between the upwa
rd and downward thresholds
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: Schmidt trigger has two of the above mentioned effects in it.
8. To ensure that a negative fluctuation does not trigger an unwanted downward transition by pulling the input down
through VIT−, we must choose
a) minimum hysteresis
b) maximum hysteresis
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: To ensure that a negative fluctuation does not trigger an unwanted downward transition by pulling the i
nput down through VIT−, we must choose a minimum hysteresis of 0.3V.
9. The SPDT switch can be used as a ___________
a) detecting circuit
b) debouncing circuit
c) devaluing circuit
d) degenerating circuit
Answer: b
Explanation: The SPDT(single pole, double pole) switch can be used as a debouncing circuit of a switch.
10. Debouncing can be carried out at a hardware as well as the software end?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Debouncing can be carried out at both the fronts both at the software as well as the hardware front, to c
arry out the process appropriately.
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1. What are the basic functions of a timer?
a) it provided a time delay
b) it can act as a counter
c) it can control the compare, capture mode
d) all of the mentioned
Answer: d
Explanation: Timers are used to provide a time delay, they can even act as a counter and control the compare capture
mode of a microcontroller.
2. Most of the MSP430’s devices have __________ number of timers in it.
a) three
b) four
c) five
d) seven
Answer: c
Explanation: MSP430 has mainly five types of timers in it. They are Watchdog Timer, Basic Timer1, Real clock Ti
me, Timer_A, Timer_B.
3. A Watchdog Timer can act as an interval timer?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: A Watchdog Timer can act as an interval timer if the protection is not needed for it.
4. Which out of the following is the main function of a Watchdog timer?
a) control the compare mode
b) control the capture mode
c) protection from failures to the system
d) all of the mentioned
Answer: c
Explanation: Its main function is to protect the system against malfunctions.
5. Basic Timer1 can provide __________
a) clock for the LCD
b) an internal timer
c) clock to the LCD and can & also used as an interval timer
d) none of the mentioned
Answer: c
Explanation: Basic Timer1 device is used to provide the clock to the LCD and can also be used as an interval timer.
6. LCD_A controllers make use of the Basic Timer1 timer for providing a clock to the LCD?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Basic Timer1 is not used in LCD_A controllers, because these provide an internal clock of its own to al
l of its devices.
7. Real time clock is an extension of Basic Timer1?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Real time clock is an extension of Basic Timer1 and is present in almost all devices for controlling its r
eal time clock.
8. Timer_A can be used to _________
a) generate interrupts
b) handle external inputs
c) drive outputs
d) all of the mentioned
Answer: d
Explanation: Timer_A can be used to generate the interrupts, handle the external inputs or for driving the outputs.
9. Time stamp inputs can be measured by a Timer_A?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, time stamp inputs can be measured by a Timer_A.
10. Timer_B includes _________
a) sampling inputs
b) driving outputs
c) sampling inputs & driving outputs
d) none of the mentioned
Answer: b
Explanation: Timer_B is used for driving the outputs as with Timer_A but it lacks the property of Timer_A of sampl
ing inputs.
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1. The watchdog counts up and resets the MSP430 when it reaches the limit?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The watchdog timer is used for the protection of the device. It keeps a track at the counter so that the c
ode doesn’t reach an infinite unending loop. So it actually resets the counter before this particular condition.
2. Which of the following is correct about WDTCTL?
a) it is a 16 bit register
b) it is guided against accidental writes that require a password
c) a reset will occur if a value with an incorrect password is written to WDTCTL
d) all of the mentioned
Answer: d
Explanation: WDTCTL is a 16 bit register that is used for protecting the microcontroller. It actually resets the value
when an incorrect password is written to WDTCTL.
3. WDTNMI is found in the _________
a) higher byte of WDTCTL
b) lower byte of WDTCTL
c) its first four bits
d) its last four bits
Answer: b
Explanation: WDTNMI is the fifth bit of the WDTCTL register.
4. Which of the following bits reads 0 under normal conditions but goes 1 when it wants to initiate some action?
a) WDTNMI
b) WDTHOLD
c) WDTTMSEL
d) WDTCNTCL
Answer: d
Explanation: WDTCNTCL is the bit that reads 0 under normal conditions but goes 1 when it wants to initiate some a
ction like resetting the counter.
5. WDTISx bits control the _________
a) period of the clock
b) act as “Nonmaskable Interrupts”
c) stop the watchdog timer
d) start the watchdog timer
Answer: a
Explanation: WDTISx bits of the WDTCTL register is responsible for controlling the period of the clock.
6. The process of setting the WDTCNTCL bit in WDTCTL is through
a) petting
b) feeding
c) kicking
d) all of the mentioned
Answer: d
Explanation: the process of setting the WDTCNTCL bit in the WDTCTL register is by the processes like petting, fee
ding and kicking.
7. What is the function of this instruction “WDTCTL = WDTPW | WDTCONFIG”, where **#define WDTCONFIG
(WDTCNTCL|WDTSSEL)**
a) it sets the watchdog timer
b) it configures and clears the watchdog timer
c) it stops the watchdog timer
d) it configures and sets the watchdog timer
Answer: b
Explanation: WDTCTL = WDTPW | WDTCONFIG instruction is used to clear and configure the watchdog timer of
a microcontroller.
8. Is this instruction correct?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: No WDTCTL_bit.WDTCNTCL = 1; is an incorrect way of setting the bits of the WDTCTL register be
cause it violates the password protection.
9. Setting the WDTTMSEL bit of the WDTCTL register makes the watchdog timer act as
a) interrupt
b) communication device
c) converter
d) interval timer
Answer: d
Explanation: The WDTTMSEL bit of the WDTCTL register makes the watchdog timer act as the interval timer.
10. WDTIFG flag gets cleared if
a) if is interrupt had occurred
b) if the interrupt is serviced
c) if there can be no interrupt
d) all of the mentioned
Answer: b
Explanation: WDTIFG flag gets cleared if the interrupt is serviced so that again the interrupt can occur.
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1. Which of the following is true about the FRFQx bits of the BTCTL register?
a) these bits are used for clock input
b) these bits are used for setting a particular frequency fLCD
c) these bits start the timer
d) these bits stop the timer
Answer: b
Explanation: FRFQx bits of the BTCTL register are used for selecting a particular frequency fLCD varying from fA
CLK/256 to fACLK/32.
2. Timer1 is responsible for ________
a) providing a clock to the LCD module
b) cause an interrupt
c) a pulse for the RTC
d) all of the mentioned
Answer: d
Explanation: Timer1 is responsible for providing a clock for the LCD module. It can also cause an interrupt if the B
TIE bit is high. It also provides the clock to the RTC.
3. For fACLK = 32 KHz, what would be the desirable range of fLCD?
a) 2hz-256hz
b) 12hz-512hz
c) 128hz-1khz
d) 1khz-10khz
Answer: c
Explanation: For fACLK = 32khz, the desirable range of the fLCD is the fACLK/256 to fACLK/32. This value com
es out to be in the range of 128hz-1khz.
4. Normally BTCNT1 only function is to provide a prescalar for the BNTCNT2?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: LCD’s controllers nowadays don’t require a clock pulse, so the only main function of the BTCNT1 is t
o provide a prescalar for the BNTCNT2.
5. BTCNT2 provides 2 output signals?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: BNTCNT2 has no outputs. Instead, it raises the BTIFG flag at a frequency determined by the BTIPx bi
ts.
6. RTCSEC, RTCMIN, RTCDOW etc. are the bytes of a set of registers that are used to store
a) seconds
b) minutes
c) days of a week
d) all of the mentioned
Answer: d
Explanation: The current time and date are held in a set of registers that contain the following bytes like RTCSEC, R
TCMIN, RTCHOUR, RTCDOW etc.
7. The RTC module is configured in the calendar mode if __________
a) RTCMODE bit is reset
b) RTCMODE is set
c) RTCRDY is reset
d) RTCRDY is set
Answer: d
Explanation: Calendar mode is selected when RTCMODE is set.
8. The RTC module makes use of the Basic Timer1 because of _________
a) its bytes are controlled in the Basic Timer1 register
b) it is started by timer1
c) it is ended by basic timer1
d) it needs a clock pulse of 1hz that is provided by basic timer1
Answer: c
Explanation: The RTC module requires a clock of worth 1hz that is provided by basic timer1 so that why it makes u
se of basic timer1.
9. IF RTCIE interrupt is generated then _________
a) BTIFG flag is set
b) RTCFG flag is set
c) Both flags are set
d) None of the flag is set
Answer: c
Explanation: When RTCIE interrupt is generated then both BTIFG and RTCFG flags are set simultaneously.
PSST! You better watch out, something's buggy above.
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1. All channels within Timer_A share the same timer block?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: There is only one TAR in Timer_A so all of its channels share the same timer block.
2. Timer_A has _________
a) RTC module in it
b) Compare/ capture channel
c) Communication channel
d) Converter channel
Answer: b
Explanation: Timer_A has compared/ capture channel inbuilt inside it.
3. TACLK and INCLK are _________
a) internally generated clock pulses
b) externally fed clock pulses
c) of no use in Timer_A
d) very slow
Answer: b
Explanation: TACLK and INCLK clock pulses are the externally fed pulses that are required by the Timer_A.
4. In continuous mode of the counter _________
a) counter moves from 0000-ffff
b) counter moves from ffff-0000-ffff
c) counter moves from 0000-ffff and then again returns to 0
d) all of the mentioned
Answer: c
Explanation: In a continuous mode of the counter, the counter firstly increases from 0000-ffff, then after this value t
he roll over condition comes and it again gets started from 0000. This particular mode is very useful for capturing in
puts.
5. TACLR bit in TACTL _________
a) clear the interrupt flag
b) clear the status flags
c) clear the count in TAR
d) all of the mentioned
Answer: c
Explanation: TACLR bit in TACTL clears the count in the TAR.
6. TAxCCTLn is a _________
a) set of 2 bits used for selecting the mode of operation of the timer
b) a register of 8 bits used for giving the count to the timer
c) a register of 16 bits used to select the compare/capture channel of the Timer_Ax
d) a register of 16 bits used to cause the timer interrupt
Answer: c
Explanation: TAxCCTLn is a register of 16 bits used to select the compare/capture channel of the Timer_Ax.
7. CCI1B comes from _________
a) ACLK
b) CAOUT
c) SCLK
d) TACLK
Answer: b
Explanation: CCI1B comes from CAOUT.
8. Which of the following parameters are given by the TAxCCRn?
a) Capture/compare input. The selected input signal can be read by this bit
b) Synchronized capture/compare input. The selected CCI input signal is latched with the EQUx signal and can be re
ad from this bit
c) Holds the data for the comparison to the timer value in the Timer_A Register, TAR
d) None of the mentioned
Answer: c
Explanation: Compare mode: TAxCCRn holds the data for the comparison to the timer value in the Timer_A Regist
er, TAR.
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1. Why Timer_B is not considered as most suitable one for receiving asynchronous signals?
a) because of the absence of the TBOUTH input pin
b) because of the presence of the TBOUTH input pin
c) because of the absence of the SCCI bit
d) because of the presence of the SCCI bit
Answer: c
Explanation: The SCCI bit is absent in the Timer_B which means that the sampling mode is absent in it that’s why it
is considered as unsuitable for receiving asynchronous signals.
2. There is double buffering in the immediate mode?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Immediate mode offers no double buffering condition. As here, values are copied to TBCLn as soon as
they are written to TBCCRn.
3. Double buffering protects channel 0.
a) as it acts as the limit in the Up and up/down modes
b) it doesn’t actually protect it
c) as it does not accept the inputs
d) none of the mentioned
Answer: a
Explanation: Double buffering protects channel 0 as it acts as the limit in the Up and Up/Down modes.
4. Timer_B has _________
a) three serial communication ports
b) seven LCD driver
c) seven compare/capture channels
d) three LED driver ports
Answer: c
Explanation: Timer_B has seven compare/capture channels.
5. The capture/compare registers TBCCRn are double-buffered when used for compare events?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The capture/compare registers TBCCRn are double-buffered when used for compare events.
6. The length of TBR can be programmed to be _________
a) 8 bits
b) 12 bits
c) 16 bits
d) all of the mentioned
Answer: d
Explanation: The length of TBR can be programmed to be 8, 12, 16 or 10 bits long.
7. TBOUTH can pin can be used to _________
a) values are moved from one place to another
b) the length of the number of bits is selected by this register
c) it can be used to put all the outputs of the Timer_B register in the high impedance state
d) it can be used for outputting the input values of the timers
Answer: c
Explanation: TBOUTH pin is used to put all the outputs of the Timer_B register in the high impedance state by a hig
h external signal applied to this pin.
8. TBCLn provided in each channel is actually _________
a) a comparator
b) compare latch
c) controller
d) control logic
Answer: b
Explanation: TBCLn is actually a compare latch that is provided in its every channel.
9. When TBR counts to zero?
a) TBCLn is updated from TBCCRn
b) CLLDx is updated to TBCCTLn
c) CLLDx is updated to TBCCRn
d) TBCLn is updated to CLLDx
Answer: a
Explanation: When TBR counts to zero, TBCLn is updated from TBCCRn.
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1. Which of the following is the analog to digital converter that is present in the MSP430 based processors?
a) comparator
b) successive approximation ADC
c) sigma delta ADC
d) all of the mentioned
Answer: d
Explanation: A comparator module, a successive approximation ADC module and a sigma delta ADC converters are
found in the MSP based processors.
2. Higher resolution along with the slow speed is given by which ADC module?
a) comparator
b) successive approximation ADC
c) sigma delta ADC
d) all of the mentioned
Answer: c
Explanation: Higher resolution along with the slow speed is given by the sigma delta ADC module.
3. The technical terms that help us in differentiating between converters are:
a) resolution
b) accuracy
c) precision
d) all of the mentioned
Answer: d
Explanation: While selecting the converter, necessary for our work we had to take care of the factors like resolution,
accuracy and precision in it.
4. The number of repeated closeness to the true value is accounted by
a) resolution
b) accuracy
c) precision
d) all of the mentioned
Answer: c
Explanation: The degree of closeness of the measured value to the actual true value is its accuracy, while on the othe
r hand the measure of the repeated accuracy is termed as the precision.
5. Resolution is _________
a) change in measured value from the true value
b) the amount of change in the input value for the corresponding change of 1 unit in the output value
c) as the measure of the repeated accuracy
d) all of the mentioned
Answer: b
Explanation: Resolution is defined as the amount of change in the input value for the corresponding change of 1 unit
in the output value.
6. The process of reduction of a continuous input to a discrete output is
a) levelling
b) signalling
c) quantization
d) converting
Answer: c
Explanation: The process of reduction of a continuous input to a discrete output is called as quantization.
7. Which of the following functions can be used for converting the nearest integer to its argument?
a) int
b) mint
c) uint
d) nint
Answer: d
Explanation: nint is the function that is priorly used for converting the nearest integer to its argument.
8. Integral nonlinearity is termed as
a) process of reduction of a continuous input to a discrete output
b) change in measured value from the true value
c) maximum deviation between this corrected staircase and the actual transfer characteristic
d) the function used in the quantization
Answer: c
Explanation: Integral nonlinearity is termed as the maximum deviation between this corrected staircase and the actua
l transfer characteristic.
9. The SNR_______ with the increase of the number of bits.
a) remains constant
b) goes up
c) goes down
d) goes asymmetrically
Answer: b
Explanation: The SNR goes up with the number of bits.
10. The intervals between the samples are obtained from _________
a) Fs
b) Ts
c) Us
d) Ks
Answer: b
Explanation: The intervals between the samples is obtained by Ts that is equal to 1/fs.
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1. Comparator_A+ is controlled by which of the following peripheral registers?
a) CACTL1
b) CACTL2
c) CACTL1 & CACTL2
d) None of the mentioned
Answer: c
Explanation: Comparator_A+ is controlled by the CACTL1 and the CACTL2 registers.
2. CAON bit is used to ___________
a) start a timer
b) start an A/D conversion
c) switch on the comparator module
d) switch on the bit transmission
Answer: c
Explanation: CAON bit is used to switch on the comparator module namely, Comparator_A+.
3. P2CA4-P2CA0 bits are used for _______
a) giving the power supply to the comparator module
b) for selecting the mode of operation of the comparator
c) for connecting the non inverting inputs to the CA0-CA2 pins
d) all of the mentioned
Answer: c
Explanation: P2CA4-P2CA0 bits are used for connecting the non inverting inputs to the CA0-CA2 pins.
4. CAREFx bits are used for _______
a) inputting a positive reference voltage
b) inputting a negative reference voltage
c) selecting the internal reference voltage
d) all of the mentioned
Answer: c
Explanation: CAREFx bits are used for selecting the appropriate reference voltage for the comparator.
5. Which of the following bits are not actually associated with the comparator module?
a) CAREFx
b) CLLDx
c) CAON
d) CAIFG
Answer: b
Explanation: CLLDx bit is related to the Timer_2 module. All others are related to the comparator module.
6. Flag CAIFG is raised,
a) at a low level triggered pulse
b) at a high level triggered pulse
c) at the falling and rising edge of the pulse
d) at the falling or rising edge of the pulse
Answer: d
Explanation: Flag CAIFG is raised, at the falling or rising edge of the pulse that is selected by the CAIES bit.
7. Setting a bit in the Port Disable register CAPD causes the circuits for the usual digital input and output buffers to
be disconnected from the appropriate pin.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Setting a bit in the Port Disable register CAPD causes the circuits for the usual digital input and output
buffers to be disconnected from the appropriate pin.
8. Which bit is used for exchanging the two inputs of the comparator and invert its output to compensate?
a) CAIFG
b) CASHORT
c) CAPD
d) CAEX
Answer: d
Explanation: CAEX is used for exchanging the two inputs of the comparator and invert its output to compensate.
9. Changes in Vcc changes the value of V+?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: When some variation is made in the value of Vcc, in the same manner, itself the value of the V+ chang
es because, the voltage from the potential divider is proportional to Vcc. This changing effect can be reduced if the s
imilar change takes place in the value of V- itself.
10. The relaxation oscillator circuit helps in _______
a) calculating the duration single RC transient
b) setting the reference voltage
c) setting the clock frequency
d) calculating the conversion speed
Answer: a
Explanation: The relaxation oscillator is a circuit that with the help of charging and discharging of an oscillator, help
us in calculating the duration of the single RC transient.
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1. The successive approximation converters have a resolution of _________
a) 8-10 bits
b) 10-12 bits
c) 12-16 bits
d) 16-32 bits
Answer: b
Explanation: The successive approximation converters have a resolution of about 10-12 bits in it.
2. In SAR based conversions, each bit typically requires one clock cycle (sometimes two) to make a comparison and
set up the new voltage.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: In SAR based conversions, each bit typically requires one clock cycle (sometimes two) to make a com
parison and set up the new voltage.
3. The main operations that are basically performed in a SAR ADC are?
a) logic to control the operation
b) some way of generating the voltages, for comparison
c) logic to control the operation and finding some way of generating the voltages for comparison
d) none of the mentioned
Answer: c
Explanation: The main operations that are basically performed in a SAR ADC are the logic to control the operation a
nd finding some way of generating the voltages, for comparison.
4. Usually, a capacitor is inserted between an analog input and the ground because
a) it blocks the analog voltage
b) it suppresses the noise
c) it increases the gain
d) none of the mentioned
Answer: b
Explanation: A capacitor is inserted between the analog input and the ground because it suppresses the noise.
5. ADC10 and ADC12 are _________
a) The converters
b) SAR modules available in the MSP430
c) Sigma delta modules available in the MSP430
d) Comparator modules available in the MSP430
Answer: b
Explanation: ADC10 and ADC12 are the SAR modules available in the MSP430.
6. ADC10 needs external capacitors on its voltage reference.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: ADC12 needs external capacitors on its voltage reference as compared to the ADC10 module.
7. ADC10CTL0 and ADC10CTL1 are registers
a) for controlling SAR module
b) for controlling the sigma delta module
c) for controlling the comparator module
d) all of the mentioned
Answer: a
Explanation: ADC10CTL0 and ADC10CTL1 are the registers that are used for controlling the SAR module in the
MSP430.
8. While conversion is in progress, which of the flag is affected.
a) ADC10ON
b) ADC10MEM
c) ADC10BUSY
d) ADC10DF
Answer: c
Explanation: While conversion is in progress, then ADC10BUSY flag is set.
9. ADC10SHTx bits allow_________cycles of the ADC10CLK.
a) 4
b) 8
c) 16
d) all of the mentioned
Answer: d
Explanation: ADC10SHTx bits allow 4,8,16 and 64 cycles of the ADC10CLK.
10. The input to the ADC10 is selected from_______bits of the ADC10CTL1 register?
a) INCHx
b) ADC10SC
c) ADC10ON
d) ENC
Answer: a
Explanation: The input to the ADC10 is selected from the INCHx bits of the ADC10CTL1 register.
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1. The basic idea behind the sigma delta converter is that
a) to carry out the conversion
b) to carry out communication
c) to reduce the circuit to its simplest way possible and then carry out the conversion
d) all of the mentioned
Answer: c
Explanation: The main idea behind the sigma delta converter is that to reduce the circuit to its simplest way possible
and then carry out the conversion.
2. Sigma delta converter is a __________
a) 1 bit converter
b) 2 bit converter
c) 3 bit converter
d) 4 bit converter
Answer: a
Explanation: Sigma delta converter is a 1 bit converter.
3. Sigma delta converter is having good resolution.
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Sigma delta converter is having poor resolution quality.
3. Oversampling ratio is defined as the _________
a) final frequency
b) oversampling frequency
c) oversampling frequency/final frequency
d) final frequency/oversampling frequency
Answer: c
Explanation: Oversampling ratio is defined as the ration of the oversampling frequency fm to the final frequency fs.
4. Here the word sigma represents _________
a) subtraction
b) differentiation
c) integration
d) none of the mentioned
Answer: c
Explanation: In a sigma delta converter, sigma word represents that the output obtained from the delta function is get
ting integrated.
5. SD16_A features are controlled by _________
a) memory mapped registers
b) register mapped registers
c) data mapped registers
d) none of the mentioned
Answer: a
Explanation: SD16_A features are controlled by the memory mapped registers.
6. The second part of the ADC handles purely digital signals.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The second part of the ADC handles purely digital signals.
7. The second part of the ADC’s output is in the form of _________
a) the fast stream of single bits
b) the fast stream of multiple bits
c) the slow stream of single bits
d) the slow stream of multiple bits
Answer: d
Explanation: The second part of the ADC take in fast stream of single bit and give out a slow stream of multiple bit
values.
8. The filtered digital signal is then decimated to
a) reduce the rate of samples from fm to fs
b) reduce the rate of samples from fs to fm
c) increase the rate of samples from fm to fs
d) increase the rate of samples from fs to fm
Answer: a
Explanation: The filtered digital output is then decimated in order to reduce the rate of samples from fm to fs.
9. Decimated means _________
a) multipled by 10
b) multiplied by 100
c) divided by 10
d) divided by 100
Answer: c
Explanation: Decimated means to divide the result by 10.
10. The SD16 has a second-order modulator with a _________
a) sinc filter
b) sinc2 filter
c) sinc3 fiter
d) rect filter
Answer: c
Explanation: The SD16 has a second-order modulator with a sinc3 filter.
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1. What actually is a bit bagging?
a) it actually refers to the technique of assigning the bits with their inputs
b) a technique by which an MSP430 can communicate through hardware
c) a technique by which MSP430 can communicate through software
d) a technique through which conversion becomes possible
Answer: c
Explanation: Bit bagging is the technique through which a processor can communicate to its associate partners when
an appropriate hardware is not available for its purpose. This communication is made possible through the software.
2. SPI, I2C, Asynchronous serial communication are the means of communicating a processor with its associate part
ners?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: SPI, I2C, Asynchronous serial communication are the means for the processor by which communicatio
n is made possible.
3. All digital communications don’t require any clock.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Clock is the prior need for any communication to occur. This is because synchronization is maintained
with the help of a clock.
4. SPI needs______ wires than I2C?
a) less
b) same
c) more
d) depends on the conditions
Answer: c
Explanation: In SPI, there is no control of transmission in software—no addresses or acknowledgment, that’s why it
requires more amount of wires.
5. USI handles _________
a) SPI
b) I2C
c) SPI & I2C
d) None of the mentioned
Answer: c
Explanation: USI(Universal Serial Interface) supports both the types of synchronous communication i.e. SPI and I2
C.
6. USCI consists of _________
a) one channel
b) two channels
c) three channels
d) four channels
Answer: b
Explanation: USCI consists of mainly two channels, A and B. These are largely independent but share a few register
s and interrupt vectors.
7. LIN is enabled in which of the following channels?
a) A
b) B
c) C
d) D
Answer: a
Explanation: Channel A is the asynchronous receiver/ transmitter channel. It can detect the baud rate of an incoming
signal, which enables its use on a local interconnect network (LIN).
8. Can one device have more than one USC interfaces?
a) yes
b) no
c) depends on the conditions
d) cant be said
Answer: a
Explanation: Yes, one device can have more than one USC interfaces. There is a small difference because the interru
pt flags and enable bits for the “0” modules are in a special function registers IFG2 and IE2, while those for the “1”
modules are in their own registers, UC1IFG and UC1IE.
9. Which of the following conditions is more difficult to attain?
a) synchronous masters
b) synchronous slaves
c) asynchronous masters
d) asynchronous slaves
Answer: d
Explanation: Synchronous slaves are the most difficult to attain because the problem is that the slave must react quic
kly when a clock transition arrives from the master.
10. Timer_A is used in _________
a) SPI
b) I2C
c) Asynchronous Serial Communication
d) All of the mentioned
Answer: c
Explanation: Timer_A is used in the Asynchronous Serial Communication.
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1. Is SPI a full duplex technique?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, SPI is a technique where a data can be transmitted/ received in both the directions.
2. The concept of SPI is based on __________
a) two counters
b) four flip flops
c) two shift registers
d) four steady state machines
Answer: c
Explanation: The concept of the SPI is based on the two shift registers, one for the transmitter and the other is there f
or the receiver terminal.
3. Writing on the trailing edge of the clock pulse and reading on the leading edge of the clock pulse is done when
a) CPHA is set
b) CPHA is reset
c) CPOL is set
d) CPOL is reset
Answer: b
Explanation: When CPHA is reset to zero, then writing on the trailing edge of the clock pulse and reading on the lea
ding edge of the clock pulse.
4. When CPOL=1 then,
a) clock idles high between transfers
b) clock idles low between transfers
c) bit idles high between transfers
d) bit ideals low between transfers
Answer: a
Explanation: When CPOL=1, clock idles high between transfers.
5. Is CPKH and CPOL the same.
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: CPKL=CPOL and CPKH=(not CPHA).
6. SPI with the USI can be selected by ________
a) setting the USII2C bit in the register USICTL1
b) clearing the USII2C bit in the register USICTL1
c) setting the USIPE5–7 bits in USICTL0
d) clearing the USIPE5–7 bits in USICTL0
Answer: b
Explanation: SPI with the USi can be selected by clearing the USII2C bit in the register USICTL1.
7. SCLK, SDO, and SDI are found ___________ on F20x3.
a) P1.0-2
b) P1.2-4
c) P1.4-6
d) P1.5-7
Answer: d
Explanation: SCLK, SDO, and SDI are found at P1.5-7 on F20x3.
8. Transmission and reception are made at a time in SPI?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Transmission and reception occur at a time in SPI. This means that a value is received only if the trans
mitter is active.
9. When the buffer is ________ the low power mode is__________
a) empty, reset
b) having one byte, reset
c) full, reset
d) empty, two
Answer: c
Explanation: When the buffer is full, the low power mode is cleared.
10. Falling edge of the SS pin denotes ________
a) end of the transfer
b) starts a new transfer
c) selects a new master
d) none of the mentioned
Answer: b
Explanation: Falling edge of the SS pin denotes the start of a new transfer over SPI.
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1. The I2C bus uses which of the following lines?
a) CLK
b) MISO
c) SDA
d) All of the mentioned
Answer: c
Explanation: The I2C bus uses only two lines. They are SDA and SCL.
2. I2C is a faster means of data transfer than SPI?
a) yes
b) no
c) depends on the conditions
d) cant be said
Answer: b
Explanation: I2C is a slower means of transfer than SPI because here only one line is there for the two way commun
ication to occur.
3. Each slave has its unique address.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, in I2C protocol each slave has its own unique address, in order to differentiate it from others.
4. Pull-up resistors Rp keep the lines at VCC when _____________
a) all the drivers are active
b) none of the drivers are active
c) some the drivers are at sleep
d) none of the drivers is at sleep
Answer: b
Explanation: Pull-up resistors Rp keep the lines at VCC when all of the drivers are active.
5. Rising edge on SDA while SCL is high denotes __________
a) start condition (S)
b) stop condition (P)
c) transfer in progress
d) none of the mentioned
Answer: b
Explanation: Rising edge on SDA while SCL is high denotes the stop condition of the transfer.
6. Which of the following is an issue while programming I2C using the software?
a) open-collector output
b) open-drain output
c) totem pole output
d) all of the mentioned
Answer: b
Explanation: There are two main issues while programming I2C using software, they are the open-drain output and t
he detection of start and stop conditions.
7. Which of the following is the slave to be addressed when a device acts as a master?
a) UCB0I2COA
b) UCB0I2CSA
c) UCB0I2CIE
d) All of the mentioned
Answer: b
Explanation: UCB0I2CSA is the slave to be addressed when a device acts as a master.
8. Is baud rate selected in I2C?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, baud rate is also selected in the I2C module, as is the case with the SPI module.
9. How is I2C with USI different from I2C with USI_B?
a) there is only one common pin between the two devices
b) here in this case no synchronization is important
c) the outputs of SDA and SCL are open drain
d) none of the mentioned
Answer: c
Explanation: I2C is different in USI than that of USI_B module because here in this module, the output pins SDA an
d the SCL are open drains in nature.
10. UCB0RXIFG is set when ________
a) complete byte is acknowledged
b) complete byte is transmitted
c) complete byte is received
d) none of the mentioned
Answer: c
Explanation: UCB0RXIFG is set when the complete byte sent via I2C is received.
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1. Asynchronous serial communication usually requires two wires for each direction plus a common ground.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Asynchronous serial communication usually requires only a single wire for each direction plus a comm
on ground.
2. In an asynchronous mode of transmission, usually the data is sent along with the
a) the start bit
b) the stop bit
c) the start & stopbit
d) none of the mentioned
Answer: c
Explanation: In an asynchronous mode of transmission, both the start and the stop bits are present that are basically
used for intimating the other terminal that whether the data had received correctly the other destination or not.
3. The _____ rate gives the frequency at which the bits are transmitted on the line.
a) bit rate
b) packet rate
c) baud rate
d) data rate
Answer: c
Explanation: Baud rate is the rate which determines us the frequency at which the bits are transmitted on the line.
4. Baud rate is the reverse of the ________
a) baud time
b) baud period
c) bit time
d) bit period
Answer: b
Explanation: Baud rate is the reverse of the baud period.
5. Clock is transmitted in the asynchronous communication?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: No clock is transmitted in the asynchronous communication, so the transmitter and the receiver are allo
wed to work independently at their own terminals.
6. A framing error occurs is the bit is ________
a) high
b) low
c) same
d) changed
Answer: b
Explanation: Framing error occurs if the bit is low.
7. What is the non return to zero format?
a) the bits are either high or low and have no gaps between them
b) the bits are either high or low and have gaps between them
c) the bits are high and have gaps between them
d) the bits are low and have no gaps between them
Answer: a
Explanation: Non-return to zero format represents a format in which the bits are either high or low and have no gaps
between them.
8. LSB is sent first in case of the non return to zero format.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: In non-return to zero format, normally LSB is sent first.
9. There are _______ clocks in the USCI_A.
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: they are 3 clocks in the USCI_A. They are BRCLK, BITCLK and BITCLK16.
10. BITCLK16 is the ________
a) sampling clock in the undersampling mode
b) sampling clock in the oversampling mode
c) quantising clock in the undersampling mode
d) quantising clock in the oversampling mode
Answer: b
Explanation: BITCLK16 is the sampling clock in the oversampling mode.
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ABES Engineering College, Ghaziabad
Department of Computer Science
MCQ Quiz 4
(Even Semester, 2020-21)
Estd. 2000
Programme: B.Tech Semester: 4th Section:
Course Code: KCS-403 Course Title: Microprocessor
1. Addressing Range of 8086 Microprocessor is
a. 20000H-FFFFFH
b. 21000H-FFFFFH
c. 00000H-FFFFFH
d. None of the above
2. Microprocessor Control Bus and Data bus is
a. Unidirectional, Bidirectional
b. Bi-Directional, Unidirectional
c. a and b both
d. None of the above
3. ALE, IO/M signals are
a. Address signals
b. Data Signals
c. Control Signals
d. None of the Above
4. If ALE = 0 then AD0-AD7 carries
a. Address
b. Data
c. a and b both
d. none of the mentioned
5. INTA stands for
a. Interrupt Address
b. Interrupt Acknowledgement
c. a and b both
d. None of the above
6. word and Double Word represented as
a. 8 bits and 16 bits
b. 16 bits and 32 bits
c. 8 bits and 32 bits
d. 16 bits and 8 bits
7. In AD0-AD7 in 8085 is the
a. Higher order Address bus
b. Lower order address bus
c. Lower Order Address-data bus
d. None of the above
8. A 20 bit address bus addressable
memory
a. 64K
b. 32K
c. 1MB
d. None of the above
9. AX and BX registers of 8086
a. 8 bit wide
b. 16 bit wide
c. 20 bit wide
d. none of the above
10. The first machine cycle of SBI 20H
instruction is
a. Memory Read
b. Memory Write
c. Opcode Fetch
d. None of the above
11. Flag Register of 8086 MP contains how
many conditional flags
a. 6
b. 3
c. 4
d. 5
12. Which is the maskable Interrupt of 8085
a. INTR
b. TRAP
c. RST 7.5
d. a and c both
13. SOD stands for
a. Serial Output Data
b. Series Output Data
c. Series Open data
d. None of the above
14. For Peripheral which IC is used
a. 8255
b. 8359
c. 8254
d. None of the Above
15. The number of memory cycles required to
execute the following 8085 instructions
IN 20H and MVI M, 12H
a. 10, 7
b. 10, 10
c. 13, 7
d. None of the Above
16. For the 8085 ALP given below, the content of
accumulator after the execution till RAR
instruction of the program is
MVI A, 45H
MOV B, A
STC
CMC
RAR
XRA B
a. 22H
b. 45H
c. 67H
d. E7H
17. For the 8085 microprocessor the following
program is executed.
MVI A, 05H
MVI B, 05H
PTR: ADD B
DCR B
JNZ PTR
ADI 03H
HLT
At the end of the program, A contains and loop
executes how many times
a. 17H, 5
b. 23H, 5
c. 20H, 4
d. 05H, 5
18. The Number of Machine cycles for the
instructions SUB H, ORA H
a. 1, 2
b. 2, 1
c. 1, 1
d. 2, 2
19.The pin that disables all the DMA
channels by clearing the mode registers
is
a) MARK
b) CLEAR
c) RESET
d) READY
20. The pin that requests the access of the
system bus is
a) HLDA
b) HRQ
c) ADSTB
d) None of the mentioned
21. SBI 45H belongs to which addressing
mode
a. Direct AM
b. Indirect AM
c. Immediate AM
d. Register AM
22. JP 2000H Belongs to which addressing
Mode
a. Direct AM
b. Indirect AM
c. Implicit AM
d. Register AM
23. RST 6.5 address line is
a. 002CH
b. 0024H
c. 0034H
d. 0033H
24. STAX instruction belongs to
a. Indirect AM
b. Direct AM
c. Implicit AM
d. None of the Above
25. JPE instruction is
a) Jump if Positive Odd
b) Jump if Parity Even
c) Jump if Parity Odd
d) Jump if Positive
ABES Engineering College, Ghaziabad
Department of Computer Science
MCQ Quiz 3
(Even Semester, 2020-21)
Estd. 2000
Programme: B.Tech Semester: 4th Section:
Course Code: KCS-403 Course Title: Microprocessor
1. Addressing Range of 8085 Microprocessor is
e. 2000H-FFFFH
f. 2100H-FFFFH
g. 0000H-FFFFH
h. None of the above
2. Microprocessor Address bus and Data bus
is
e. Unidirectional, Bidirectional
f. Bi-Directional, Unidirectional
g. a and b both
h. None of the above
3. RD, WR signals are
e. Address signals
f. Data Signals
g. Control Signals
h. None of the Above
4. If ALE = 1 then AD0-AD7 carries
e. Address
f. Data
g. a and b both
h. none of the mentioned
5. ALE stands for
e. Address lag Enable
f. Address Latch Enable
g. a and b both
h. None of the above
6. Nibble and Double Word represented as
e. 8 bits and 4 bits
f. 4 bits and 32 bits
g. 8 bits and 16 bits
h. 16 bits and 8 bits
7. In A8-A15 in 8085 is the
e. Higher order Address bus
f. Lower order address bus
g. Address-data bus
h. None of the above
8. A 16 bit address bus addressable
memory
e. 64K
f. 32K
g. 128K
h. None of the above
9. In assembly language programming is
done in alphanumeric codes which is
known as
e. machine
f. mnemonics
g. nomics
h. none of the above
10. The first machine cycle of every
instruction is
e. Memory Read
f. Memory Write
g. Opcode Fetch
h. None of the above
11. Flag Register of 8086 MP contains how
many control flags
e. 4
f. 3
g. 2
h. 5
12. Which is the non-maskable Interrupt of
8085
e. INTR
f. TRAP
g. RST 7.5
h. None of the above
13. SID stands for
e. Serial Input Data
f. Series Input Data
g. Series Insert data
h. None of the above
14. For generating Hardware delay which IC
is used
e. 8255
f. 8359
g. 8254
h. None of the Above
15. The number of memory cycles required
to execute the following 8085
instructions
STA 2050H and MVI M, 12H
e. 10, 7
f. 13, 10
g. 13, 7
h. None of the Above
16. For the 8085 ALP given below, the content
of accumulator after the execution of the
program is
MVI A, 45H
MOV B, A
STC
CMC
RAR
XRA B
e. 00H
f. 45H
g. 67H
h. E7H
17. For the 8085 microprocessor the following
program is executed.
MVI A, 05H
MVI B, 05H
PTR: ADD B
DCR B
JNZ PTR
ADI 03H
HLT
At the end of the program, A contains
e. 17H
f. 23H
g. 20H
h. 05H
18. The Number of Machine cycles for the
instructions LDA 2000H, IN Port
e. 4,2
f. 4,3
g. 3,4
h. 4,4
19. In BSR mode, only port C can be
used to
a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports
20. The register that stores all
the interrupt requests in it in order to
serve them one by one
on priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
21. ORA B belongs to which addressing
mode
e. Direct AM
f. Indirect AM
g. Implicit AM
h. Register AM
22. XRI 20H Belongs to which addressing
Mode
e. Direct AM
f. Indirect AM
g. Implicit AM
h. Immediate AM
23. RST 5.5 address line is
e. 002CH
f. 0024H
g. 0034H
h. 0033H
24. LDAX instruction belongs to
e. Indirect AM
f. Direct AM
g. Implicit AM
h. None of the Above
25. If the data transmission takes place in
either direction, but at a time data
may be transmitted only in one
direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
ABES Engineering College, Ghaziabad
Department of Computer Science
MCQ Quiz 2
(Even Semester, 2020-21)
Estd. 2000
Programme: B.Tech Semester: 4th Section:
Course Code: KCS-403 Course Title: Microprocessor
1. Address Bus of 8085 Microprocessor is
i. 4 bit wide
j. 16 bit wide
k. 8 bit wide
l. None of the above
2. Microcontroller is a
i. Special Purpose Processor
j. General Purpose Processor
k. a and b both
l. None of the above
3. T state is also known as?
i. Clock Rate.
j. Clock Length.
k. Clock Set.
l. Clock Cycle
4. If the processor is executing the main
program that calls a subroutine, then
after executing the main program up to
the CALL instruction, the control will be
transferred to
i. address of main program
j. subroutine address
k. address of CALL instruction
l. none of the mentioned
5. JPE is for
i. Jump if Parity Even
j. Jump if Parity Odd
k. Jump if Positive
l. None of the Above
6. Nibble and Word represented as
i. 8 bits and 4 bits
j. 4 bits and 8 bits
k. 4 bits and 16 bits
l. 16 bits and 8 bits
7. Queue follows the principle of
i. LIFO
j. FIFO
k. FILO
l. LILO
8. A 20 bit address bus addressing
capability
i. 64 K
j. 128 K
k. 1 MB
l. None of the above
9. A good assembly language programmer
should use general purpose registers
rather than memory in maximum
possible ways for data processing. This
is because:
i. Data Processing with registers is
easier than memory
j. Data Processing with Memory
requires more instructions in the
program than that with registers
k. Of limited set of instructions for data
processing with memory
l. Data processing with registers takes
fewer cycles than that with memory
10. CMP instructions affects
i. CY and S Flag
j. CY and Z Flag
k. All Flags
l. None of the above
11. Instructions related to the subroutine
a. PUSH, POP, LXI SP
b. CALL and RET
c. a and b both
d. None of the above
12. Flag Register of 8085 MP
i. 16 bit wide
j. 8 bit wide
k. 12 bit wide
l. None of the above
13. Which is the non-vectored Interrupt of
8086
i. NMI
j. TRAP
k. RST 7.5
l. None of the above
14. SIM stands for
i. SET Interrupt Mask
j. SET Inter Mask
k. a and b used both
l. None of the above
15. Unconditional Call Instruction Mnemonic
is
i. CC
j. CZ
k. CALL
l. None of the Above
16. The number of memory cycles required
to execute the following 8085
instructions
LDA, 2050H and MOV M, B
i. 13, 7
j. 7, 10
k. 7,7
l. None of the Above
17. Consider the sequence of the 8085
instruction given below:
LXI H, 5892
MOV A, M
CMA
MOV M, A
i. Contents of Locations 9258H are
moved to the A
j. Contents of Locations 5892H are
complemented
k. Contents of Locations 9258H are
complemented
l. None of the above
18. While pushing data from the stack, the
stack pointer is
i. Incremented the stack pointer
content by 2
j. Decremented the Stack pointer
content by 2
k. Incremented the Stack Pointer
content by 1
l. Decremented the Stack Pointer
content by 1
19. An 8085 ALP is
MVI A, B5H
MVI B, 0EH
XRI 69H
ADD B
ANI 9BH
CPI 9FH
STA 3010H
HLT
After the execution of line no 6 of the
program, the content of CY and Z Flag
i. 0, 0
j. 0, 1
k. 1, 0
l. 1, 1
20. HLDA Stands for
a. Hold Acknowledgement
b. Hold Access
c. Hold Addressing
d. None of the Above
21. 8254 have how counters
a. 2
b. 3
c. 5
d. None of the Above
22. DAA belongs to which addressing mode
i. Direct AM
j. Indirect AM
k. Implicit AM
l. Register AM
23. CMP Belongs to which addressing
Mode
i. Direct AM
j. Indirect AM
k. Implicit AM
l. Register AM
24. Address line for RST 5.5 is?
i. 002CH
j. 0024H
k. 0034H
l. 0033H
25. DAD Stands for
i. Data Addition
j. Direct Addition
k. Double Addition
l. None of the above
ABES Engineering College, Ghaziabad
Department of Computer Science
MCQ Quiz
(Even Semester, 2020-21)
Estd. 2000
Programme: B.Tech Semester: 4th Section:
Course Code: KCS-403 Course Title: Microprocessor
1. Data Bus of 8085 Microprocessor is
m. 4 bit wide
n. 16 bit wide
o. 8 bit wide
p. None of the above
2. Microprocessor is a
m. Special Purpose Processor
n. General Purpose Processor
o. a and b both
p. None of the above
3. Clock Speed is also known as?
m. Clock Rate.
n. Clock Length.
o. Clock Set.
p. Clock Type.
4. If the processor is executing the main
program that calls a subroutine, then
after executing the main program up to
the CALL instruction, the control will be
transferred to
m. address of main program
n. subroutine address
o. address of CALL instruction
p. none of the mentioned
5. To obtain 16-bit data bus width, the two
4K*8 chips of RAM and ROM are
arranged in
m. Parallel
n. Serial
o. both serial and parallel
p. neither serial nor parallel
6. Byte and Word represented as
m. 8 bits and 4 bits
n. 4 bits and 8 bits
o. 8 bits and 16 bits
p. 16 bits and 8 bits
7. Stack follows the principle of
m. LIFO
n. FIFO
o. FILO
p. LILO
8. A 16 bit address bus generate
addresses
m. 65535
n. 65536
o. 65534
p. None of the above
9. A good assembly language programmer
should use general purpose registers
rather than memory in maximum
possible ways for data processing. This
is because:
m. Data Processing with registers is
easier than memory
n. Data Processing with Memory
requires more instructions in the
program than that with registers
o. Of limited set of instructions for data
processing with memory
p. Data processing with registers takes
fewer cycles than that with memory
10. The correct sequence of steps in the
instruction cycle of the computer is
m. Fetch, Decode and Execute
n. Fetch, Execute and Decode
o. Decode, Fetch and Execute
p. None of the above
11. Instructions related to the stack
e. PUSH, POP, LXI SP
f. CALL and RET
g. a and b both
h. None of the above
12. Flag Register of 8086 MP
m. 16 bit wide
n. 8 bit wide
o. 12 bit wide
p. None of the above
13. Which is the non-vectored Interrupt of
8085
m. INTR
n. TRAP
o. RST 7.5
p. None of the above
14. RIM stands for
m. Read Interrupt Mask
n. Read Inter Mask
o. a and b used both
p. None of the above
15. The number of instructions actually
executed by the microprocessor
depends on the
m. Stack
n. Loop Count
o. Program Counter
p. None of the Above
16. The number of memory cycles required
to execute the following 8085
instructions
LXI H, 2050H and MOV A, M
m. 10, 7
n. 7, 10
o. 7,7
p. None of the Above
17. Consider the sequence of the 8085
instruction given below:
LXI H, 9258
MOV A, M
CMA
MOV M, A
m. Contents of Locations 9258H are
moved to the A
n. Contents of Locations 5892H are
moved to the A
o. Contents of Locations 9258H are
complemented
p. None of the above
18. While retrieving data from the stack, the
stack pointer is
m. Incremented the stack pointer
content by 2
n. Decremented the Stack pointer
content by 2
o. Incremented the Stack Pointer
content by 1
p. Decremented the Stack Pointer
content by 1
19. An 8085 ALP is
MVI A, B5H
MVI B, 0EH
XRI 69H
ADD B
ANI 9BH
CPI 9FH
STA 3010H
HLT
After the execution of line no 7 of the
program, the content of CY and Z Flag
m. 0, 0
n. 0, 1
o. 1, 0
p. 1, 1
20. DMA Stands for
e. Direct Memory Access
f. Data Memory Access
g. Data Memory Addressing
h. None of the Above
21. 8255 have how many ports
e. 2
f. 3
g. 5
h. None of the Above
22. MOV B, M belongs to which addressing
mode
m. Direct AM
n. Indirect AM
o. Implicit AM
p. Register AM
23. CMA Belongs to which addressing
Mode
m. Direct AM
n. Indirect AM
o. Implicit AM
p. Register AM
24. Address line for TRAP is?
m. 0023H
n. 0024H
o. 0034H
p. 0033H
25. DAA Stands for
m. Decimal Adjust Accumulator
n. Data Adjust Accumulator
o. Digital Adjust Accumulator
p. None of the above
ABES Engineering College, Ghaziabad
Department of Computer Science
MCQ Bank
(Even Semester, 2020-21)
Estd. 2000
Programme: B.Tech Semester: 4th Section: A, B, C
Course Code: KCS-403 Course Title: Microprocessor
S.NO KL, CO Question Marks
SECTION A
An 8-bit microprocessor can process _____ data at a
time.
A. 4-bit
1 CO1 B. 8-bit 1
C. 16-bit
D. All of the above
Clock Speed is also known as?
A. Clock Rate.
2 CO1 B. Clock Length. 1
C. Clock Set.
D. Clock Type.
If the processor is executing the main program that calls a
subroutine, then after executing the main program up to
the CALL instruction, the control will be transferred to
3 CO1
a) address of main program 1
b) subroutine address
c) address of CALL instruction
d) none of the mentioned
If ‘n’ denotes the number of clock cycles and ‘T’ denotes
period of the clock at which the microprocessor is
running, then the duration of execution of loop once can
be denoted by
4 CO1 a) n+T 1
b) n-T
c) n*T
d) n/T
The Stack follows the sequence
a) first-in-first-out
5 CO1
b) first-in-last-out 1
c) last-in-first-out
d) last-in-last-out
To obtain 16-bit data bus width, the two 4K*8 chips of
RAM and ROM are arranged in
a) parallel
6 CO1 b) serial 1
c) both serial and parallel
d) neither serial nor parallel
Nibble and Byte represented in the form of
a) 8 bits and 4 bits
7 CO1 b) 8 bits and 16 bits 1
c) 4 bits and 8 bits
d) 4 bits and 16 bits
A 16 bit address bits generate __________ addresses
a) 65536
8 b) 65534
CO1 1
c) 25652
d) 34564
A good assembly language programmer should use
general purpose registers rather than memory in
maximum possible ways for data processing. This is
because:
a) Data processing with registers is easier than with
memory
9 CO1 1
b) Data processing with memory requires more
instructions in the program than that with registers
c) Of limited set of instructions for data processing
with memory
d) Data processing with registers takes fewer cycles
than that with memory
Assertion(A): Address bus is unidirectional. Reason(R):
Data bus is bidirectional
10 CO1 1
a) Both A & R are true and R is the correct
explanation of A
b) Both A & R are true but R is not the correct
explanation of A
c) A is true but R is false
A is false but R is true
The correct sequence of steps in the instruction cycle of a
basic computer is
a) Fetch, Execute, Decode.
11 CO1 1
b) Decode, Fetch and Execute.
c) Fetch, Decode, Execute.
d) Fetch, Decode and Execute.
HLT opcode means
a) load data to accumulator.
12 CO1 b) Store result in the memory 1
c) End of the program
d) None of the above
Which of the following function relate to stack?
a) Push and pop
b) Call and return
13 CO1 c) Both push pop and call return 1
d) None of the mentioned
To address a memory location out of N memory
locations, the number of address lines required is
a) log N (to the base 2)
14 CO1 b) log N (to the base 10) 1
c) log N (to the base e)
d) log (2N) (to the base e)
Which is Non-vectored interrupt
a) INTR
15 CO1 b) TRAP 1
c) RST 7.5
d) RST 6.5
Flag register of 8085 is
a) 16 bit wide
16 CO1 b) 8 bit wide 1
c) 12 bit wide
d) 4 bit wide
Which is Non- Maskable interrupt of 8085 Mp
a) TRAP
17 CO1 b) RST 7.5 1
c) INTR
d) None of the Above
A machine language instruction format consists of
a) Operation code field
18 CO1 b) Operation code field and operand field 1
c) Operand field
d) None of the above
SIM Stands for
a) Sorting inter mask
19 CO1 b) Set Interrupt mask 1
c) Select Interrupt Mask
d) None of the above
The number of instructions actually executed by the
microprocessor depends on the
a) stack
20 CO1 b) loop count 1
c) program counter
d) time duration
SECTION B
ALU (Arithmetic and Logic Unit ) of 8085 microprocessor
consists of
a) Accumulator, temporary register, arithmetic and logic
circuits
21
CO2 b) Accumulator, arithmetic, logic circuits and five flags 1
c) Accumulator, arithmetic and logic circuits
d) Accumulator, temporary register, arithmetic, logic
circuits and five flags
Consider the following statements: In 8085
microprocessor, data-bus and address bus are
22 CO2 1
multiplexed in order to I)Increase the speed of
microprocessor. II)Reduce the number of pins.
III)Connect more peripheral chips. Which of these
statements is/are correct?
a) (I) only
b) (II) only
c) (II) & (III)
d) (I), (II) & (III)
In an intel 8085, which is the first machine cycle of an
instruction?
a) An op-code fetch cycle
23 CO2 1
b) A memory read cycle
c) A memory write cycle
d) An I/O read cycle
In an intel 8085A microprocessor, why is READY signal
used?
a) To indicate to user that the microprocessor is working
and is ready for use.
b) To provide proper WAIT states when the
24 CO2
microprocessor is communicating with a slow 1
peripheral device.
c) To slow down a fast peripheral device so as to
communicate at the microprocessor’s device.
d) None of the above.
The processor status word of 8085 microprocessor has five
flags namely:
a) S, Z, AC, P, CY
25 CO2 b) S, OV, AC, P, CY 1
c) S, Z, OV, P, CY
d) S, Z, AC, P, OV
Which of the following statements for intel 8085 is correct?
Program Counter (PC) specifies the address of the
instruction last executed
a) PC specifies the address of the instruction being
executed
26 CO2 b) PC specifies the address of the instruction to be 1
executed
c) PC specifies the number of instructions executed so
far
d) None of the above
if ALE=1 then AD0 to AD7 bus carries
a) Address
b) Data
27 CO2 c) Address and Data both 1
d) None of the Above
ALE Stands for
a) Address Lack Enable
b) Address Latch Enable
28 CO2 c) a and b both 1
d) none of the above
In 8085 microprocessor, the RST6 instruction transfer
programme execution to following location
a) 0030H
29 CO2 b) 0020H 1
c) 0024H
d) 0048H
The instruction “CALL” belongs to
a) sequential control flow instructions
b) control transfer instructions
30 CO2 c) branch instructions 1
d) control transfer & branch instructions
In 8085 16 bit registers are
a) Program counter
31 CO2 b) Stack Pointer 1
c) a & b
d) None of the above
Unconditional JUMP instruction mnemonic is
a) JNZ
32 CO2 b) JP 1
c) JPE
d) JMP
Address Bus and Data bus of 8085 MP is
33 CO2 a) 16 bit and 8 bit wide 1
b) 8 bit and 16 bit wide
c) 10 bit and 20 bit wide
d) 20 bit and 16 bit wide
Addressing capability of 8085 Microprocessor is
a) 1 MB
34 CO2 b) 512 KB 1
c) 64 KB
d) 128 KB
DCR and INR instruction affects which flag
a) Sign, Parity, Auxilary Flag and Zero
35 CO2 b) Sign, Carry and Zero 1
c) Carry and Parity
d) None of the above
RAL instruction stands for
a) Rotate Accumulator Left with carry
36 CO2 b) Rotate Accumulator right with carry 1
c) Rotate Accumulator Left without carry
d) Rotate Accumulator right without carry
LXI instruction is of
a) 2 bytes
37 CO2 b) 3 bytes 1
c) 1 byte
d) None of the above
MOV A, M instruction belongs to which addressing mode
a) Immediate AM
38 CO2 b) Register AM 1
c) Register Indirect AM
d) Implied AM
DAA Instruction belongs to which addressing mode
a) Immediate AM
39 CO2 b) Register AM 1
c) Register Indirect AM
d) Implied AM
Which of the flag is not part of 8085 flag register
a) CY Flag
40 CO2 b) Sign Flag 1
c) Overflow Flag
d) Auxiliary Flag
SECTION C
8086 Microprocessor supports _______ modes of
operation.
41 CO3
A. 2 1
B. 3
C. 4
D. 5
Which of the following is not a Features of 8086?
A. It uses two stages of pipelining
B. It is available in 3 versions based on the
42 CO3 frequency of operation 1
C. Fetch stage can prefetch up to 6 bytes of
instructions
D. It has 512 vectored interrupts.
8086 can access up to?
A. 512KB
43 CO3 B. 1Mb 1
C. 2Mb
D. 256KB
8086 has ___ address bus.
A. 16-bit
44 CO3 B. 18-bit 1
C. 20-bit
D. 24-bit
Which flag is set to 1 when the result of arithmetic or
logical operation is zero else it is set to 0?
45 CO3
A. Binary bit 1
B. Zero flag
C. Sign flag
D. Overflow flag
Which flag represents the result when the system
capacity is exceeded?
46 CO3 1
A. Carry flag
B. Auxiliary flag
C. Trap flag
D. Overflow flag
. It is an edge triggered input, which causes an
interrupt request to the microprocessor.
A. NMA
47 CO3 B. INTR 1
C. INTA
D. ALE
It is used to write the data into the memory or the
output device depending on the status of M/IO signal.
48 CO3
A. IR 1
B. HLDA
C. HR
D. WR
Which instruction is Used to load the address of
operand into the provided register?
49 CO3 A. LEA 1
B. LDS
C. LES
D. LAHF
The different ways in which a source operand is
denoted in an instruction is known as
50 CO3 A. Instruction Set 1
B. Interrupts
C. 8086 Configuration
D. Addressing Modes
. The microprocessor can read/write 16 bit data from
or to
A. memory
51 CO3 B. I /O device 1
C. processor
D. register
The 16 bit flag of 8086 microprocessor is responsible
to indicate
A. the condition of result of ALU operation
52 CO3 B. the condition of memory 1
C. the result of addition
D. the result of subtraction
The index register are used to hold
A. memory register
53 CO3 B. offset address 1
C. segment memory
D. offset memory
The CS register stores instruction in code segment
A. stream
54 CO3
B. path 1
C. codes
D. stream line
INC destination increments the content of destination
by
A. 1
55 CO3 B. 2 1
C. 30
D. 41
The JS is called as
A. jump the signed bit
56 CO3
B. jump single bit 1
C. jump simple bit
D. jump signal it
The 8086 fetches instruction one after another from
memory
A. code segment
57 CO3
B. Instruction Pointer 1
C. Extra Segment
D. Stack Segment
In max mode, control bus signal So,S1 and S2 are sent
out in form
58 CO3 A. decoded 1
B. encoded
C. shared
D. unshared
__________ generate interrupt signal to
microprocessor and receive acknowledge
A. priority resolver
59 CO3 B. control logic 1
C. interrupt request register
D. interrupt register
Address line for TRAP is?
A. 0023H
60 CO3
B. 0024H 1
C. 0033H
D. 0099H
SECTION D
An 8085 executes the following instructions
2710 LXI H, 30A0H
2713 DAD H
2714 PCHL
All addresses and constants are in hexadecimal. What are
61 CO4 the content of Program Counter and H-L Register Pair after 1
the execution of PCHL instruction
a) PC=2715H, HL= 30A0H
b) PC=30A0H HL=2715H
c) PC=6140H, HL=6140H
d) PC=6140H, HL= 2715H
For the 8085 ALP given below, the content of accumulator after the
execution of the program is
MVI A, 45H
MOV B, A
STC
CMC
62 CO4 RAR 1
XRA B
a) 00H
b) 45H
c) 67 H
d) E7H
An 8085 ALP is given below. Assume that carry flag is initially unset.
63 CO4 The content of the A after the execution of the program is 1
MVI A, 07H
RLC
MOV B, A
RLC
RLC
ADD B
RRC
a) 8CH
b) 64H
c) 23H
d) 15H
For the 8085 microprocessor the following program is executed.
MVI A, 05H
MVI B, 05H
PTR: ADD B
DCR B
JNZ PTR
ADI 03H
64 CO4 1
HLT
At the end of the program, A contains
a) 17H
b) 23H
c) 20H
d) 05H
An 8085 microprocessor executes STA 1234H with starting addresses
location 1FFEH with starting address location 1FFEH. While the
instruction is fetched and executed, the sequence of values written
at the address pin A15-A8 is
65 CO4 a) 1FH, 1FH, 20H, 12H 1
b) 1FH, 1FH, 12H, 12H
c) 1FH, FEH, 1FH, FFH, 12H
d) 1FH, 1FH, 12H, 20H, 12H
MVI B, 87H
MOV A, B
START: JMP NEXT
66 CO4 1
MVI B, 00H
XRA B
OUT PORT 1
HLT
NEXT: XRA B
JP START
OUT PORT 2
HLT
a) An O/P of 87H at port 1
b) An O/P of 87H at port 2
c) Infinite looping of the program execution with A data
remaining at 00H
d) Infinite looping of program execution with A data alternating
between 00H & 87H
How many buses are connected as a part of 8085
Microprocessor
a) 8
67 CO4 b) 3 1
c) 4
d) 2
The content of A= 3AH and B=49H. after using instruction SUB B,
which of the following is true
a) A= F1H, CY=1, S=1
68 CO4 1
b) A=0FH, CY=1, S=1
c) A=F0H, CY=0, S=0
d) A=1FH, CY=1, S=1
For the instructions given below, how many memory operations
(R/W) are performed during the execution in the 8085 MP.
MVI A, C3H
NOP
ADD B
DCR A
JNZ GO
JMP BACK
69 CO4 1
GO: OUT 47H
BACK: HLT
a) 17 MC
b) 14 MC
c) 10MC
d) 15 MC
The number of memory cycles required to execute the following
8085 instructions
70 CO4 (i) LDA 3000H 1
(ii) LXI D, F0F1H
a) 2 for (i) and 2 for (ii)
b) 4 for (i) and 3 for (ii)
c) 3 for (i) and 3 for (ii)
d) 3 for (i) and 4 for (ii)
Consider the sequence of the 8085 instruction given below:
LXI H, 9258
MOV A, M
CMA
MOV M, A
a) Contents of locations 9258H are moved to the A
71 CO4 b) Contents of locations 9258H are compared with the 1
contents of A
c) Contents of locations 8529H are complemented and stored
in location 8529H
d) Contents of locations 5892H are complemented and stored
in location 5892H
It is desired to multiply the numbers 0AH by 0BH and store the result
in the accumulator. The numbers are available in registers B & C
respectively. A part of the 8085 program for this purpose
MVI A, 00H
LOOP:
72 CO4 1
HLT
a) JNZ LOOP, ADD B, DCR C
b) ADD B, JNZ LOOP, DCR C
c) DCR C, JNZ LOOP, ADD B
d) ADD B, DCR C, JNZ LOOP
The following program starts at location 0100H.
LXI SP, 00FFH
LXI H, 0701H
MVI A, 20H
SUB M
73 CO4 The content of A when the program counter reaches 0109H is. 1
Content of memory location 0701H is 00H.
a) 20H
b) 02H
c) 00H
d) FFH
If the additional code exists in question no. 13 from location 0109H
74 CO4 onwards 1
ORI 40H
ADD M
What will be the result in the A after the last instruction is executed.
a) 20H
b) 02H
c) 60H
d) 06H
An 8085 ALP is
MVI A, B5H
MVI B, 0EH
XRI 69H
ADD B
ANI 9BH
CPI 9FH
STA 3010H
75 CO4 HLT 1
The contents of accumulator just after execution ADD
instruction in line 4 will be
a) C3H
b) EAH
c) DCH
d) 69H
In the question 75, After the execution of line 7 of the program, the
status of CY and Z flag
a) CY=0, Z=0
76 CO4 b) CY=0, Z=1 1
c) CY=1, Z=0
d) CY=1, Z=1
Following is the segment of 8085 ALP
LXI SP, EFFFH
CALL 3000H
77 CO4 1
3000H: LXI H, 3CF4H
PUSH PSW
SPHL
POP PSW
RET
On the completion of the RET instruction, the content of SP is
a) 3CF0H
b) 3CF8H
c) 3FFDH
d) EFFFH
Register pair used to indicate memory
a) B&C
78 CO4 b) H&L 1
c) D&E
d) W&Z
While retrieving data from the stack, the stack pointer is
a) incremented by 1
b) incremented by 2
c) decremented by 1
79 CO4 1
d) decremented by 2
DCX instructions affects which flag
a) CY, Sign and Auxiliary Flag
80 CO4 b) Sign and Parity Flag 1
c) CY and Auxiliary Flag
d) None of the above
SECTION E
The ______ is a general purpose programmable I/O
device designed to transfer the data from I/O to
interrupt I/O.
81 CO5 A. 8285A 1
B. 8241A
C. 8255A
D. 8251A
How many ports 8255A has?
82 CO5 1
A. 2
B. 3
C. 4
D. 5
Which port can be split into two parts?
A. PORT A
83 CO5 B. PORT B 1
C. PORT C
D. PORT D
It is a tri-state, bi-directional, 8-bit buffer, which is
used to interface the 8253/54 to the system data bus.
84 CO5
A. Read/Write Logic 1
B. Data Bus Buffer
C. system data bus
D. System Buffer
The common register(s) for all the four channels of
8257 is
85 CO5 a) DMA address register 1
b) Terminal count register
c) Mode set register and status register
d) None of the mentioned
The pin that disables all the DMA channels by
clearing the mode registers is
86 CO5 a) MARK 1
b) CLEAR
c) RESET
d) READY
The pin that requests the access of the system bus is
a) HLDA
87 CO5 b) HRQ 1
c) ADSTB
d) None of the mentioned
. In a cascaded mode, the number of vectored
interrupts provided by 8259A is
88 CO5 1
a) 4
b) 8
c) 16
d) 64
When non-specific EOI command is issued to 8259A
it will automatically
89 CO5 a) set the ISR 1
b) reset the ISR
c) set the INTR
d) reset the INTR
In the application where all the interrupting devices
are of equal priority, the mode used is
90 CO5
a) Automatic rotation 1
b) Automatic EOI mode
c) Specific rotation
d) EOI
The register that stores all the interrupt requests in it in
order to serve them one by one on priority basis is
91 CO5
a) Interrupt Request Register 1
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
In BSR mode, only port C can be used to
a) set individual ports
b) reset individual ports
92 CO5 c) set and reset individual ports 1
d) programmable I/O ports
If the data transmission takes place in either direction,
but at a time data may be transmitted only in one
direction then, it is of
93 CO5 a) simplex mode 1
b) duplex mode
c) semi duplex mode
d) half duplex mode
In 8251A, the pin that controls the rate at which the
character is to be transmitted is
94 CO5
a) TXC(active low) 1
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)
The signal that may be used either to interrupt the
CPU or polled by the CPU is
95 CO5
a) TXRDY(Transmitter ready) 1
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)
The 8-bit _______ data buffer interfaces internal
circuit of 8253 to microprocessor systems bus.
a) Unidirectional
96 CO5
b) Single 1
c) Bidirectional
d) None of these
The speciality of the 8253 counters is that they can be
easily read on line without disturbing the ________
input to the counter.
97 CO5
a) GATE 1
b) CLK
c) OUT
d) WR
When count is N loaded in ________ , then for half of
the count, the output remains high and for remaining
half it remain low.
98 CO5
a) Odd 1
b) Even
c) Even-even
d) Odd-odd
The “programmable interval timer” is
1. 8253 chip
99 CO5 2. 8251 chip 1
3. 8250 chip
4. 8275 chip
The bit packet that commands the device either to
receive data or transmit data in transmission of USB
asynchronous communication is
100 CO5 a) Handshake packet 1
b) Token packet
c) PRE packet
d) Data packet
CO-Course Outcomes mapped with respective question
KL- Bloom’s Knowledge Level (K1,K2,K3,K4,K5,K6)
K1 – RememberK2 – UnderstandK3 – ApplyK4 – AnalyzeK5 – EvaluateK6– Create
8086 Microprocessor
8086
• 8086 is a 16 bit microprocessor with powerful
instruction set.
• Upward software compatible
8086
• 16 bit processor
• 16 bit ALU
• 16 bit registers
• 16 bit data bus
• Three versions
• 8086—5MHz
• 8086-2—8MHz
• 8086-1—10MHz
• 20 address lines to access memory
• 8086 is pipelined processor
– Uses two stage pipelining
• Fetch stage that pre-fetches upto 6 bytes of instructions
stores them in the queue
• Execute stage that execute these instructions
• Pipelining improves the performance of the processor
• Operate in 2 modes
– Minimum mode
• System with only one processor
– Maximum Mode
• System with 8086 and other processors like 8087,8089 etc.
– Uses memory banks
• Memory is divided into two banks of 512KB each
• Lower Bank or even bank because it stores the data bytes at
even locations i.e. 0,2,4….
• Higher Bank or odd bank because it stores the data bytes at
odd locations i.e. 1,3,5…
• Memory segmentation
– Divided into four segments
• Code Segment
• Stack Segment
• Data Segment
• Extra Segment
• Interrupts: 256 vectored interrupts
• 14, 16 bit registers
• Powerful instruction set that supports
multiply and divide operations also
• 8086 can perform operations on bit, byte,
word or string
8086 internal architecture
• 8086 divided into 2 units
– BIU (Bus Interface Unit)
– EU (Execution Unit)
• These two units are independent of each other
and they share work of the CPU
• Such a work division speeds up the processing
and reduces the processing time. This is called
pipelining.
• The process of fetching the next instruction,
when the present instruction is being executed is
called pipelining
• Pipelining eliminates the waiting time of EU and
speeds up the processing
• Pipelining is possible due to the use of queue
• BIU restarts filling in the queue when at least
two locations of the queue are vacant
• 8086 queue is only 6 byte long.
EU(Execution Unit)
• Main function of EU is decoding and executions of the
instructions
– ALU
– Flag Registers
– General purpose registers
– Control Unit
– Point and index Registers
ALU
• The ALU in the EU is a 16 bit unit i.e. it can
perform 16 bit operation simultaneously
• It is capable of performing a variety of
arithmetic and logical operations such as add,
subtract, AND,OR,NOT etc.
Flag Register
• A flag is a flip flop which indicates some conditions produced by the
execution of an instruction or controls certain operations of the EU .
• In 8086 The EU contains
– 16 bit flag register
– 9 of the 16 are active flags and remaining 7 are undefined.
• 6 flags indicates some conditions- status flags
• 3 flags –control Flags
U U U U OF DF IF TF SF ZF U AF U PF U CF
Sign Auxiliary Carry
Interrupt Trap Zero Parity
Over flow Direction
U - Unused
11
• Conditional Status Flags
• Parity Flag
– If even parity then PF=1 otherwise zero
• Zero Flag
– The flag is set if the result of the operation is zero, else it is reset
• Sign Flag
– If the MSB of the result is 1 then sign flag is set otherwise reset
• Auxiliary Flag
– If the carry from 3rd bit to 4th bit then AF is set otherwise reset
• Carry Flag
• Overflow Flag
– Overflow occurs when signed numbers are added or subtracted. An
overflow indicates the result has exceeded the capacity of the Machine
– (75H + 37H)
– Control Flag
• Trap Flag
• Interrupt Flag
– If user sets IF flag, processor will recognize
external interrupt requests
– Clearing IF disables these interrupts
• Direction Flag
Flag Register
• Six of the flags are status indicators reflecting properties
of the last arithmetic or logical instruction.
• For example, if register AL = 7Fh and the instruction ADD
AL,1 is executed then the following happen
AL = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed
14
General Purpose Registers
16 bits
8 bits 8 bits
AH AL Accumulator
AX
BX
BH BL Base
CX CH CL Count
DX DH DL
Data
SP Stack Pointer
Pointer
BP Base Pointer
SI Source Index
Index
DI Destination Index
15
EXECUTION UNIT – General Purpose Registers
Register Purpose
AX Word multiply, word divide, word I /O
AL Byte multiply, byte divide, byte I/O, decimal arithmetic
AH Byte multiply, byte divide
BX Store address information
CX String operation, loops
CL Variable shift and rotate
DX Word multiply, word divide, indirect I/O
(Used to hold I/O address during I/O instructions. If the result is more than
16-bits, the lower order 16-bits are stored in accumulator and higher order
16-bits are stored in DX register)
16
Pointer And Index Registers
• used to keep offset addresses.
• Used in various forms of memory addressing.
• In the case of SP and BP the default reference to form a
physical address is the Stack Segment (SS-will be discussed
under the BIU)
• The index registers (SI & DI) and the BX generally default to
the Data segment register (DS).
SP: Stack pointer
– Used with SS to access the stack segment
BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments
17
• SI: Source Index register
– is required for some string operations
– When string operations are performed, the SI
register points to memory locations in the data
segment which is addressed by the DS register.
Thus, SI is associated with the DS in string
operations.
• DI: Destination Index register
– is also required for some string operations.
– When string operations are performed, the DI
register points to memory locations in the data
segment which is addressed by the ES register.
Thus, DI is associated with the ES in string
operations.
18
BIU (Bus Interface Unit)
Contains
• 6-byte Instruction Queue (Q)
• The Segment Registers (CS, DS, ES, SS).
• The Instruction Pointer (IP).
• The Address Summing block (Σ)
• Performs all activities related to bus.
– Instruction fetching from primary memory
– Read/write of data operand from/to primary
memory
– I/O of data from/to peripherals ports
– Address generation for memory reference
– Instruction queuing in an instruction queue
Instruction queue
• When the EU unit is busy in decoding and
executing an instruction, the BIU fetches upto
six instruction bytes for next instruction
• These bytes are called as pre fetched bytes
and they are stored in FIFO register set called
queue
Segment Registers
Segmented Memory Physical Memory
00000
▪The memory in an 8086/88 based
system is organized as segmented
memory.
Code segment (64KB)
▪The CPU 8086 is able to address
Data segment (64KB)
1 MB
1Mbyte of memory.
Extra segment (64KB)
▪The Complete physically available
memory may be divided into a Stack segment (64KB)
number of logical segments.
FFFFF
23
• The size of each segment is 64 KB
• A segment may be located any where in the
memory
• Each of these segments can be used for a specific
function.
– Code segment is used for storing the instructions.
– The stack segment is used as a stack and it is used to
store the return addresses.
– The data and extra segments are used for storing data
byte.
* In the assembly language programming, more than
one data/ code/ stack segments can be defined. But
only one segment of each type can be accessed at any
time.
24
• The 4 segments are Code, Data, Extra and Stack
segments.
• A Segment is a 64kbyte block of memory.
• The 16 bit contents of the segment registers in the
BIU actually point to the starting location of a
particular segment.
• Segments may be overlapped or non-overlapped
Advantages of Segmented memory Scheme
• Allows the memory capacity to be 1Mb although the actual addresses to be
handled are of 16 bit size.
• Allows the placing of code, data and stack portions of the same program in different
parts (segments) of the m/y, for data and code protection.
• Permits a program and/or its data to be put into different areas of memory each
time program is executed, i.e. provision for relocation may be done .
• The segment registers are used to allow the instruction, data or stack portion of a
program to be more than 64Kbytes long. The above can be achieved by using more
than one code, data or stack segments.
25
Segment registers
• In 8086/88 the processors have 4 segments registers
• Code Segment register (CS), Data Segment register (DS),
Extra Segment register (ES) and Stack Segment (SS)
register.
• All are 16 bit registers.
• Each of the Segment registers store the upper 16 bit
address of the starting address of the corresponding
segments.
26
27
MEMORY
FFFFFH
BIU
Segment Registers 7FFFFH
CODE (64k)
70000H
CSR 34BA
5FFFFH
DATA (64K)
1 MB
DSR 44EB 50000H
3FFFFH
ESR 54EB EXTRA (64K)
30000H
SSR 695E 2FFFFH
STACK (64K)
20000H
Each segment register store the upper
16 bit of the starting address of the
segments 28
Instruction pointer & summing block
• The instruction pointer register contains a 16-bit offset
address of instruction that is to be executed next.
• The IP always references the Code segment register (CS).
• The value contained in the instruction pointer is called as
an offset because this value must be added to the base
address of the code segment, which is available in the CS
register to find the 20-bit physical address.
• The value of the instruction pointer is incremented after
executing every instruction.
• To form a 20bit address of the next instruction, the 16 bit
address of the IP is added (by the address summing block)
to the address contained in the CS , which has been
shifted four bits to the left.
29
30
• The following examples shows the CS:IP scheme
of address formation:
CS 34BA IP 8AB4 Code segment
34BA0
Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR 8AB4 (offset)
four binary digits left
3D645
34BA0(CS)+
8AB4(IP)
3 D 6 5 4 (next address)
44B9F
31
• Example For Address Calculation (segment:
offset)
• If the data segment starts at location 1000h and
a data reference contains the address 29h where
is the actual data?
Offset 0000 0000 0010 1001
Segment Address
0001 0000 0000 0000 0000
Required Address 0001 0000 0000 0010 1001
32
Segment and Address register
combination
• CS:IP
• SS:SP SS:BP
• DS:BX DS:SI
• DS:DI (for other than string operations)
• ES:DI (for string operations)
33
Summary of Registers & Pipeline of 8086 µP
EU BIU
AX AH AL
IP
BX BH BL
Fetch &
CX CH CL D
store code CS DS ES SS
E
DX DH DL C
bytes in
C
O PIPELINE C
O PIPELINE O IP BX DI SP
D
SP D E (or) D DI BP
E O QUEUE E
BP I SI
R U
SI T N
DI
Default Assignment
Timing
FLAGS ALU control
34
Comparison of 8085 & 8086
8085 8086
• Size: 8 bit microprocessor • 16 bit microprocessor
• Address bus of 16 bits • Address bus of 20 bits
• It can access upto 64Kbytes • It can access upto 1MB of
of memory memory
• It does not have instruction • 6 byte instruction queue
queue • Supports 2 stage pipelined
structure
INTEL 8086 - Pin Diagram
INTEL 8086 - Pin Details
Power Supply
5V 10%
Ground
Reset
Registers, seg
regs, flags
Clock
INTEL 8086 - Pin Details
Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
D0 when ALE is 0. multiplexed
address/data bus
contains address
information.
INTEL 8086 - Pin Details
INTERRUPT
Non - maskable
interrupt
Interrupt
acknowledge
Interrupt request
INTEL 8086 - Pin Details
Direct
Memory
Access
Hold
Hold
acknowledge
INTEL 8086 - Pin Details
Address/Status Bus
Address bits A19 –
A16 & Status bits S6
– S3
INTEL 8086 - Pin Details
BHE#, A0: Bus High Enable/S7
S7: Always 1.
INTEL 8086 - Pin Details
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Minimum Mode Pins
Maximum Mode
Pins
Minimum Mode- Pin Details
Read Signal
Write Signal
Memory or I/0
Data
Transmit/Receive
Data Bus Enable
Maximum Mode - Pin Details
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access Status Signal
101: read memory
110: write memory Inputs to 8288 to
111: none -passive generate eliminated
signals due to max
mode.
Maximum Mode - Pin Details
Lock Output
Used to lock peripherals
off the system
DMA
Activated by using the Request/Grant
LOCK: prefix on any
instruction
Lock Output
Maximum Mode - Pin Details
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode
Queue Status
Used by numeric
coprocessor (8087)
Demultiplexing Technique for the 8086 Microprocessor
PROGRAMMABLE PERIPHERAL
INTERFACE-8255
Features:
It is a programmable , parallel I/O device .
It has 24 I/O programmable pins like PA,PB,PC (3-
8 pins).
It operate in two modes:
BSR Mode
I/O Mode
Pin Diagram
Function of pins:
Data bus(D0-D7):These are 8-bit bi-directional
buses, connected to 8085 data bus for transferring
data.
CS: This is Active Low signal. When it is low, then
data is transfer from 8085.
Read: This is Active Low signal, when it is Low
read operation will be start.
Write: This is Active Low signal, when it is Low
Write operation will be start.
Address (A0-A1):This is used to select the ports. like
this
A1 A0 Select
0 0 PA
0 1 PB
1 0 PC
Control
1 1
reg.
RESET: This is used to reset the device. That
means clear control registers.
PA0-PA7:It is the 8-bit bi-directional I/O pins
used to send the data to peripheral or
or to receive the data from peripheral.
PB0-PB7:Similar to PA
PC0-PC7:This is also 8-bit bidirectional I/O pins.
These lines are divided into two groups.
1. PC0 to PC3(Lower Groups)
2. PC4 to PC7 (Higher groups)
These two groups working in separately using 4
data’s.
Block Diagram
Data Bus buffer:
It is a 8-bit bidirectional Data bus.
Used to interface between 8255 data bus with system
bus.
The internal data bus and Outer pins D0-D7 pins are
connected in internally.
Read/Write Control Logic:
This is getting the input signals from control bus and
Address bus
Control signal are RD and WR.
Address signals are A0,A1,and CS.
8255 operation is enabled or disabled by CS.
Group A and Group B control:
Group A and B get the Control Signal from CPU
and send the command to the individual control blocks.
Group A send the control signal to port A and Port C
(Upper) PC7-PC4.
• Group B send the control signal to port B and Port C (Lower)
PC3-PC0.
• PORT A:
• This is a 8-bit I/O port.
• It can be programmed by mode 0 , mode 1, mode 2 .
PORT B:
This is a 8-bit I/O port
It can be programmed by mode 0 and mode 1.
PORT C:
This is a 8-bit I/O port
It is splitted into two parts.
It can be programmed by bit set/reset operation.
Operation modes:
BIT SET/RESET MODE (BSR):
The PORT C can be Set or Reset by sending OUT
instruction to the CONTROL registers.
I/O MODES:
MODE 0(Simple input / Output):
In this mode , port A, port B and port C is used as
individually (Simply).
Ports do not have Handshake or interrupt capability.
MODE 1 :(Input/output with Hand shake)
In this mode, input or output is transferred by hand
shaking Signals.
Computer DATA BUS Printer
STB
ACK
Handshaking signals is used to transfer data between
whose data transfer is not same.
Example:
The computer send the data to the printer large speed
compared to the printer.
When computer send the data according to the printer
speed at the time only, printer can accept.
If printer is not ready to accept the data then after sending
the data bus , computer uses another handshaking signal
to tell printer that valid data is available on the data bus.
Each port uses three lines from port C as handshake signals
MODE 2:bi-directional I/O data transfer:
This mode allows bidirectional data transfer over a single
8-bit data bus using handshake signals.
This feature is possible only Group A
Port A is working as 8-bit bidirectional.
PC3-PC7 is used for handshaking purpose.
The data is sent by CPU through this port , when the
peripheral request it.
FOR BIT SET/RESET MODE:
This is bit set/reset control word format.
D7 D6 D5 D4 D3 D2 D1 D0
X X X
Don’t care BIT SET/RESET
1=SET
0=RESET
Bit select
0 1 B
21 3 4 5 6 7
0 1 B
02 1 0 1 0 1
0 0 1 1 0 0 1 1
0 0 0 0 1 1 1 1
BIT SET/RESET FLAG
=0 Active
PC0-PC7 is set or reset as per the status of D0.
A BSR word is written for each bit
Example:
PC3 is Set then control register will be 0XXX0111.
PC4 is Reset then control register will be 0XXX01000.
X is a don’t care.
FOR I/O MODE:
The mode format for I/O as shown in figure
D7 D6 D5 D4 D3 D2 D1 D0
Group A Group B
Port C Upper
1=Input Port C Lower
Mode set
flag=1=I/O 0=Output 1=Input
mode Port A 0=Output
1=Input Port B
0=Output 1=Input
Mode selection 0=Output
00=mode 0 Mode selection
01=mode 1 0=mode 0
1x=mode 2 1=mode 1
Bit D7 is used for specifying whether word loaded in to
Bit set/reset mode or I/O Mode .
D7=1= I/O Mode.
D7=0=Bit set/Reset mode.
Introduction:
Direct Memory Access (DMA) is a method of allowing data
to be moved from one location to another in a computer
without intervention from the central processor (CPU).
It is also a fast way of transferring data within (and
sometimes between) computer.
The DMA I/O technique provides direct access to the
memory while the microprocessor is temporarily disabled.
The DMA controller temporarily borrows the address bus,
data bus and control bus from the microprocessor and
transfers the data directly from the external devices to a
series of memory locations (and vice versa).
Basic DMA Operation:
Two control signals are used to request and acknowledge a
direct memory access (DMA) transfer in the microprocessor-
based system.
The HOLD signal as an input(to the processor) is used to
request a DMA action.
The HLDA signal as an output that acknowledges the DMA
action.
When the processor recognizes the hold, it stops its execution and
enters hold cycles.
Cont.,
HOLD input has higher priority than INTR or NMI.
The only microprocessor pin that has a higher priority
than a HOLD is the RESET pin.
HLDA becomes active to indicate that the processor has
placed its buses at high-impedance state.
Basic DMA Definitions:
Direct memory accesses normally occur between an I/O
device and memory without the use of the microprocessor.
A DMA read transfers data from the memory
to the I/O device.
A DMA write transfers data from an I/O device
to memory.
The system contains separate memory and I/O control
signals.
Hence the Memory & the I/O are controlled simultaneously
The DMA controller provides memory with its address, and the
controller signal selects the I/O device during the transfer.
Data transfer speed is determined by speed of the memory device
or a DMA controller.
In many cases, the DMA controller slows the speed of the system
when transfers occur.
The serial PCI (Peripheral Component Interface) Express bus
transfers data at rates exceeding DMA transfers.
This in modern systems has made DMA is less important.
78
The 8237 DMA Controller
The 8237 supplies memory & I/O with control signals and
memory address information during the DMA transfer.
It is actually a special-purpose microprocessor whose job is
high-speed data transfer between memory and I/O
CPU having the control over the bus:
When DMA operates:
8257 DMA Controller
Features
It is a 4-channel DMA.
So 4 I/O devices can be interfaced to DMA
It is designed by Intel
Each channel have 16-bit address and 14 bit counter
It provides chip priority resolver that resolves priority of
channels in fixed or rotating mode.
It provide on chip channel inhibit logic.
It generates a TC signal to indicate the peripheral that the
programmed number of data bytes have been transferred.
The maximum frequency is 3Mhz and minimum frequency is
250 Hz.
Block Diagram
D0-D7:
it is a bidirectional ,tri state ,Buffered ,Multiplexed data (D0-D7)and
(A8-A15).
IOR:
It is active low ,tristate ,buffered ,Bidirectional lines.
IOW:
It is active low ,tristate ,buffered ,Bidirectional control lines.
CLK:
It is the input line ,connected with TTL clock generator
RESET:
Used to clear mode set registers and status registers
A0-A3:
A0-A3 bits of memory address on the lines.
READY:
It is a asynchronous input line.
In master mode,
When ready is high it is received the signal.
HRQ:
It is used to receiving the hold request signal from the output device.
HLDA:
It is acknowledgment signal from microprocessor.
AEN (Address enable):
It is a control output line.
Used it isolate the system address ,data ,and control lines.
ADSTB: (Address Strobe)
It is a control output line.
Used to split data and address line.
TC (Terminal Count):
It is a status of output line.
It is high ,it selected the peripheral.
It is low ,it free and looking for a new peripheral.
MARK:
It is a modulo 128 MARK output line.
DRQ0-DRQ3(DMA Request):
These are the asynchronous peripheral request input signal.
The request signals is generated by external peripheral device.
DACK0-DACK3:
These are the active low DMA acknowledge output lines.
Low level indicate that ,peripheral is selected for giving the
information (DMA cycle).
In master mode it is used for chip select.
Control logic block:
It contains ,
1. Control logic
2. Mode set register and
3. Status Register.
MODE SET REGISTERS:
It is a write only registers.
It is used to set the operating modes.
This registers is programmed after initialization of DMA channel.
D7 D6 D5 D4 D3 D 2 D1 D0
AL TCS EW RP EN3 EN2 EN1 EN0
AL=1=Auto load mode
AL=0=Rotating mode
TCS=1=Stop after TC (Disable Channel)
TCS=0=Start after TC (Enable Channel)
EW=1=Extended write mode
EW=0=normal mode.
RP=1=Rotating priority
RP=0=Fixed priority.
EN3=1=Enable DMA CH-3
EN3=0=Disable DMA CH-3
EN2=1=Enable DMA CH-2
EN2=0=Disable DMA CH-2
EN1=1=Enable DMA CH-1
EN1=0=Disable DMA CH-1
EN0=1=Enable DMA CH-0
EN0=0=Disable DMA CH-0
8259 Programmable Interrupt Controller (PIC)
1. This IC is designed to simplify the implementation of the interrupt interface in the 8088
and 8086 based microcomputer systems.
2. This device is known as a ‘Programmable Interrupt Controller’ or PIC.
3. It is manufactured using the NMOS technology and It is available in 28-pin DIP.
4. The operation of the PIC is programmable under software control (Programmable)and it
can be configured for a wide variety of applications.
5. 8259A is treated as peripheral in a microcomputer system.
6. 8259A PIC adds eight vectored priority encoded interrupts to the microprocessor.
7. This controller can be expanded without additional hardware to accept up to 64
interrupt request inputs. This expansion required a master 8259A and eight 8259A
slaves.
8. Some of its programmable features are:
· The ability to accept level-triggered or edge-triggered inputs.
· The ability to be easily cascaded to expand from 8 to 64 interrupt-inputs.
· Its ability to be configured to implement a wide variety of priority schemes.
ASSINGMENT OF SIGNALS FOR 8259:
1. D7- D0 is connected to microprocessor data bus D7-D0 (AD7-AD0).
2. IR7- IR0, Interrupt Request inputs are used to request an interrupt and to connect to a slave
in a system with multiple 8259As.
3. WR - the write input connects to write strobe signal of microprocessor.
4. RD - the read input connects to the IORC signal.
5. INT - the interrupt output connects to the INTR pin on the microprocessor from the master,
and is connected to a master IR pin on a slave.
6. INTA - the interrupt acknowledge is an input that connects to the INTA signal on the system.
In a system with a master and slaves, only the master INTA signal is connected.
7. A0 - this address input selects different command words within the 8259A.
8. CS - chip select enables the 8259A for programming and control.
9. SP/EN - Slave Program/Enable Buffer is a dual-function pin.
❖ When the 8259A is in buffered mode, this pin is an output that controls the data bus
transceivers in a large microprocessor-based system.
❖ When the 8259A is not in buffered mode, this pin programs the device as a master
(1) or a slave (0).
❖ CAS2-CAS0, the cascade lines are used as outputs from the master to the slaves for
cascading multiple 8259As in a system.
8259A PIC- PIN DIGRAM
8
2
5
9
8259A PIC- BLOCK DIAGRAM
DATA BUS BUFFER
8 bit (D7-D0) Bidirectional data lines
Tri-state Buffer used to Interface the 8259 to the system data bus.
Control words, Status words and vectoring data are all passed
through the data bus buffer.
Interrupt request register (IRR)
IRR stores the current status of the interrupt request inputs
Has one bit for each IR input
The values in the bit positions reflect whether the interrupt
inputs are active or inactive
Priority resolver
The priority resolver identifies which of the active interrupt inputs
has the highest priority
The resolver can be configured to work using a number of different
priority schemes through software
It will signal the control logic that an interrupt is active and in
response, the control logic causes the INT signal to be issued
Interrupt mask register
Interrupt mask register (IMR) can be used to enable or mask out
individually the interrupt request inputs
There are 8 bits and each bit represents one interrupt input
0- enable; 1- mask out (disable)
The register can be read from or written into under software
control (programmed via the microprocessor
Read/Write Control Logic
❖ The function of this block is to accept output commands from the CPU.
❖ It contains the Initialization Command Word (lCW) registers and Operation
Command Word (OCW) registers which store the various control formats for
device operation.
❖ This function block also allows the status of the 8259A to be transferred
onto the Data Bus.
Control Logic
INT (Interrupt)→ Output
→ Connected to Interrupt pin of Microprocessor.
→ When interrupt occurs this pin goes high.
➢ INTA ( Interrupt Acknowledge) → Input from Microprocessor
CASCADE BUFFER/ COMPARATOR
Generates control signals for cascade operation.
Also generates buffer enable signals.
8259 cascaded with other 8259s
→ Interrupt handling capacity to 64 levels
→ Former is called master and latter is slave.
8259 can be set up as master or slave by SP/EN pin in
non-buffered mode or by software if it is to be operated
in the buffered mode of operation.
INTERCONNECTING OF MASTER /SLAVE PICs AND CPU
➢ Each PIC scheme provides to receive only up to 8 IR signals. If
required more than 8 IR signals then used multiple PIC schemes
from which one is master and others are slave. At this case PIC
schemes are used in cascading mode.
➢ In cascading mode INT outs of Slave are connected into nonuse IR
line of Master. When is programmed PIC must be defined each IR
inputs of Master that can be captured by Slave device.
➢ INTR input of CPU can be receives common interrupt request
signal only from INT output of single Master
➢ Number of selected interrupt vector can be transferred from only
Master PIC
Slave 8259A
Interrupt controller
External e device 00
……..… IR0
……..…
INT
External e device 07 IR7
Microprocessor
Master 8259A
Interrupt controller
INTR
…………………
IR0
……..…
INT INT
IR7
Slave 8259A
Interrupt controller
External e device 53
IR0
……..…
……..…
INT
External e device 64 IR7
CONNECTING MULTIPLE (64) INTERRUPTED I/O DEVICES TO
PROCESSOR
Partial Reference Based On
Image
De-Noising Using Dual-Tree
Complex Wavelet Transform
Shrinkage
Fig:- Interface 8259 PIC with 8086 Microprocessor
Programming the 8259A: -
The 82C59A accepts two types of command words generated by the
CPU:
1. Initialization Command Words (ICWs):
Before normal operation can begin, each 82C59A in the
system must be brought to a starting point - by a sequence of 2 to
4 bytes timed by WR pulses.
2. Operational Command Words (OCWs):
These are the command words which command the 82C59A
to operate in various interrupt modes. Among these modes are:
a. Fully nested mode.
b. Rotating priority mode.
c. Special mask mode.
d. Polled mode.
The OCWs can be written into the 82C59A anytime after
initialization.
Initialization Command Words: -
There are four Initialization
Command Words for the 8259A that are
selected with the help of logic level of A0
pin.
When the 8259A is first powered
up, it must be sent ICW1, ICW2 and ICW4.
If the 8259A is programmed in
cascade mode by ICW1, then we also
must program ICW3.
So, if a single 8259A is used in a
system ICW1, ICW2 and ICW4 must be
programmed.
If cascade mode is used in a
system, then all four ICWs must be
programmed.
ICW1:
❖ To program this ICW for 8086 we place a logic 1 in bit IC4.
❖ Bits D7, D6 , D5and D2 are don’t care for microprocessor operation and only
apply to the 8259A when used with an 8-bit 8085 microprocessor.
❖ This ICW selects single or cascade operation by programming the SNGL bit. If
cascade operation is selected, we must also program ICW3.
❖ The LTIM bit determines whether the interrupt request inputs are positive edge
triggered or level-triggered.
ICW2:
❖ Selects the vector number used with the interrupt request inputs.
❖ For example, if we decide to program the 8259A so that it functions at vector
locations 08H-0FH, we place a 08H into this command word.
❖ Likewise, if we decide to program the 8259A for vectors 70H-77H, we place a
70H in this ICW.
ICW3:
❖ Is used only when ICW1 indicates that the system is operated in cascade mode.
❖ This ICW indicates where the slave is connected to the master.
❖ For example, if we connected a slave to IR2, then to program ICW3 for this
connection, in both master and slave, we place a 04H in ICW3.
❖ Suppose we have two slaves connected to a master using IR0 and IR1. The
master is programmed with an ICW3 of 03H; one slave is programmed with an
ICW3 of 01H and the other with an ICW3 of 02H.
ICW4:
❖ Is programmed for use with the 8088/8086. This ICW
is not programmed in a system that functions with the
8085 microprocessors.
❖ The rightmost bit must be logic 1 to select operation
with the 8086 microprocessor, and the remaining bits
are programmed as follows:
SNFM:
Selects the special fully nested mode of operation for the 8259A if logic 1 is
placed in this bit. This allows the highest priority interrupt request from a slave to be
recognized by the master while it is processing another interrupt from a slave. Normally,
only one interrupt request is processed at a time and others are ignored until the process
is completed.
BUF and M/S:
Buffer and master slave are used together to select buffered operation or non-
buffered operation for the 8559A as a master or a slave.
AEOI:
Selects automatic or normal end of interrupt. The EOI commands of OCW2 are
used only if the AEOI mode is not selected by ICW4. If AEOI is selected, the interrupt
automatically resets the interrupt request bit and does not modify priority. This is the
preferred mod of operation for the 8259A and reduces the length of the interrupt service
procedure.
Operation Command Words
OCW1:
❖ Is used to set and read the interrupt mask register.
❖ When a mask bit is set, it will turn off (mask) the corresponding
interrupt input. The mask register is read when OCW1 is read.
❖ Because the state of the mask bits is known when the 8259A is
first initialized, OCW1 must be programmed after programming
the ICW upon initialization.
OCW2:
❖ Is programmed only when the AEOI mod is not selected for the 8259A.
❖ In this case, this OCW selects how the 8259A responds to an interrupt.
❖ The modes are listed as follows in next slide:
❖ Nonspecific End-of-Interrupt:
A command sent by the interrupt service procedure to signal the end of the interrupt.
The 8259A automatically determines which interrupt level was active and resets the
correct bit of the interrupt status register. Resetting the status bit allows the interrupt to
take action again or a lower priority interrupt to take effect.
❖ Specific End-of –Interrupt:
A command that allows a specific interrupt request to be reset. The exact position is
determined with bits L2-L0 of OCW2.
❖ Rotate-on-Nonspecific EOI:
A command that function exactly like the nonspecific end-of-interrupt command except
that it rotates interrupt priorities after resetting the interrupt status register bit. The
level reset by this command becomes the lowest priority interrupt. For example, if IR4
was just serviced by this command, it becomes the lowest priority interrupt and IR5
becomes the highest priority.
❖ Rotate-on-Automatic EOI:
A command that selects automatic EOI with rotating priority. This command must be
sent to the 8259A only once if this mode is desired. If this mode must be turned off, use
the clear command.
❖ Rotate-on-Specific EOI:
Functions as the specific EOI, except that it selects rotating priority.
❖ Set Priority:
Allows the programmer to set the lowest priority interrupt input using the L2-L0 bits.
OCW3:
➢ Selects the register to be read, the operation of the special mask register, and
the poll command.
➢ If polling is selected, the P-bit must be set and then output to the 8259A. The
next read operation would read the poll word. The rightmost three bits of the
poll word indicate the active interrupt request with the highest priority.
➢ The leftmost bit indicates whether there is an interrupt, and must be checked
to determine whether the rightmost three bits contain valid information.
Status Register: -
Three status registers are available in the 8259A:
➢ Interrupt request register (IRR):
an 8-bit register that indicates which interrupt request inputs are active.
➢ In-service register (ISR):
an 8-bit register that contains the level of the interrupt being serviced.
➢ Interrupt mask register (IMR):
An 8-bit register that holds the interrupt mask bits and indicates which
interrupts are masked off.
Both the IRR and ISR are read by programming OCW3 and IMR is read
through OCW1. To read the IMR, A0 = 1, to read IRR or ISR, A0 = 0. Bit positions
D0 and D1 of OCW3 select which register (IRR or ISR) is read when A0 = 0.
Modes of 8259A PIC
❖ Fully Nested mode
❖ Special Fully Nested mode
❖ Nonspecific Rotating
❖ Specific Rotating
❖ Special Mask
❖ Polling
❖ Fixed priority mode
❖ Fully nested mode:
➢ This is a general purpose mode where all IR’s are arranged in highest to
lowest.
➢ IR0 highest and IR7 lowest.
❖ Special Fully Nested Mode:
➢ Used in more complicated systems.
➢ Similar to, normal nested mode.
➢ When an interrupt request from a certain slave is in service, this slave
can further send requests to the master.
➢ The master interrupts the CPU only.
❖ Automatic Rotation Mode:
➢ In this mode a device after being serviced receives the lowest priority.
❖ Specific Rotation Mode:
➢ In this user can select any IR for lowest priority thus fixing all priorities.
❖ Special Mask Mode
➢ When a mask bit is set in OCW, it inhibits further interrupts at that level and
enables interrupt from other levels, which are not mastered.
❖ Poll command
➢ The INT output is neglected, though it functions normally by not connecting INT
output or by masking INT input of the microprocessor.
➢ This mode is entered by setting p=1 in OCW3.
➢ A poll command may give more than 64 priority levels.
Programmable Interval
Timer - 8254
Prepared By:
Ms. Ranjeeta Yadav
Intel’s Programmable
Not Counter/ Timer Device
Possible To (8253/8254) Facilitates
Generate • Accurate Time Delays
Accurate • Minimizes Load On Mp
Time • Real Time Clock
Delays • Event Counter
Using Delay • Digital One Shot
Routines in • Square Wave Generator
8086 • Complex Waveform
Generator
8253 8254-ADVANCED VERSION OF 8253
• 8253 can • 8254 can operate with higher clock
operate at
frequency Frequency Range ( DC To 8 Mhz AND 10
from dc to Mhz FOR 8254-2)
2mhz
• Includes Status Read Back Command That
Latches The Count And Status Of Counters
Features
• Three Independent 16-Bit Counters,
• Clock input upto 10 MHz,
• Status Read-Back Command,
• Six Programmable Counter Modes,
• Binary or BCD Counting,
• Single +5V Supply,
• Superset of PIT-8253.
Pin Diagram
Pin Description
Block Diagram of 8254
Internal Blocks of Counter
• Count Register (CR) to store count (CRL &
CRM),
• Counting elements (CE) are used for counting,
• Output Latch (OLL & OLM) to latch the count
in CE,
• The Control Word Register is not part of the
Counter itself, but its contents determine how
the Counter operates.
• The status register, when latched, contains the
current contents of the Control Word Register
and status of the output and null count flag.
8254 Programming
• Each counter is individually programmed by
writing a control word, followed by the initial
count.
• The control word allows the programmer to
select the counter, mode of operation, binary
or BCD count and type of operation
(read/write).
WRITE Operation
• Control Word to Control register
• Initial count must follow the count format
specified in the Control Word (least
significant byte only, most significant byte
only, or least significant byte and then most
significant byte).
READ Operation
Three Possible Methods to read counters
• Simple Read Operation,
• Counter Latch Command,
• Read Back Command.
Note: Two I/O read operations have to be performed to
get first Lower Byte and then higher byte of count.
Simple Read Operation:
After inhibiting counter using GATE or CLK input
we can read count
Counter Latch Command:
D5 D4 = 0 0 Designates the counter latch command
SC1 SC2 = Specify counter to be latched.
X – Don’t care bits must be 0 to ensure compatibility
with future Intel products.
Read Back Command:
Status Byte
Interleaved Read and Write
Operations:
Valid sequence for read and write of the same
counter set for two byte count:
1. Read least significant byte,
2. Write new least significant byte,
3. Read most significant byte,
4. Write new most significant byte.
Modes of 8254
Six Different Modes
• Mode 0: Interrupt On Terminal Count
• Mode 1: Hardware Retriggerable One-shot
• Mode 2: Rate Generator
• Mode 3: Square Wave Mode
• Mode 4: Software Triggered Strobe
• Mode 5: Hardware Triggered Strobe
(Retriggerable)
MODE 0 – Interrupt on Terminal Count
N : Undefined Count
MODE 1: Hardware Retriggerable One Shot.
MODE 2: Rate Generator
MODE 3: Square Wave Mode
MODE 4: Software Triggered Strobe
MODE 5 : Hardware Triggered Strobe
(Retriggerable)
Applications of 8254
• Real time clock
• Event-counter
• Digital one-shot
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
• Complex waveform generator
• Complex motor controller
References
• Microprocessors and Interfacing by
Douglas V. Hall, TMH Publication.
• Intel 8254 data sheet
(www.datasheetcatalog.com)
→Telegram Channel
→Telegram Group
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Date-16/06/2021
Subject Name-KCS-403-Microprocessor_CSE-Semester 4
UNIT-1
1. In 8085 microprocessor, the RST6 instruction transfer programme execution
to following location
a. 0030H
b. 0024H
c. 0048H
d. 0060H
Answer: (a).0030H
2. HLT opcode means
a. load data to accumulator
b. store result in memory
c. load accumulator with contents of register
d. end of program
Answer: (d).end of program
3. What is SIM?
a. Select interrupt mask
b. Sorting interrupt mask
c. Set interrupt mask
d. None of these
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Answer: (c).Set interrupt mask
4. The ROM programmed during manufacturing process itself is called
a. MROM
b. PROM
c. EPROM
d. EEPROM
Answer: (a).MROM
5. A field programmable ROM is called
a. MROM
b. PROM
c. FROM
d. FPROM
Answer: (b).PROM
6. The operations executed by two or more control units are referred as
a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer: (b).Macro-operations
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
7. Program counter in a digital computer
a. Counts the numbers of programs run in the machine.
b. Counts the number of times a subroutine is called.
c. Counts the number of times the loops are executed.
d. Points the memory address of the next instruction to be fetched.
Answer: (d).Points the memory address of the next instruction to be fetched.
8. At the beginning of a fetch cycle, the contents of the program
counter are
a. incremented by one.
b. transferred to address bus.
c. transferred to memory address register.
d. transferred to memory data register.
Answer: (c).transferred to memory address register.
9. Which components are NOT found on chip in a microprocessor but may be
found on chip in a micro-controller?
a. SRAM & USART
b. EPROM & PORTS
c. EPROM, USART & PORTS
d. SRAM, EPROM & PORTS
Answer: (c).EPROM, USART & PORTS
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
10. For the purpose of data processing an efficient assembly language
programmer makes use of the general purpose registers rather than
memory. The reason is
a. the set of instructions for data processing with memory is limited
b. data processing becomes easier when register are used
c. more memory related instructions are required
d. data processing with registers takes fewer cycles than that with memory
Answer: (d).data processing with registers takes fewer cycles than that with memory
11. The first machine cycle of an instruction is always
a. A memory read cycle
b. A fetch cycle
c. An I/O read cycle
d. A memory write cycle
Answer: (b).A fetch cycle
12. The output data lines of microprocessor and memories are usually tristated
because
a. More than one device can transmit information over the data bus by enabling
only one device at a time
b. More than one device can transmit over the data bus at the same time
c. The data line can be multiplexed for both input and output
d. It increases the speed of data transfer over the data bus
Answer: (a).More than one device can transmit information over the data bus by
enabling only one device at a time
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
13. The correct sequence of steps in the instruction cycle of a basic computer is
a. Fetch, Execute, Decode and Read effective address.
b. Read effective address,Decode,Fetch and Execute.
c. Fetch, Decode, Read effective address and ,Execute.
d. Fetch, Read effective address, Decode and Execute.
Answer: (c).Fetch, Decode, Read effective address and ,Execute.
14. The register which holds the information about the nature of results of
arithmetic and logic operations is called as
a. Accumulator
b. Condition code register
c. Flag register
d. Process status register
Answer: (c).Flag register
15. Consider the following statements:
Arithmetic Logic Unit (ALU)
1.Performs arithmetic operations
2.Performs comparisons.
3.Communicates with I/O devices
4.Keeps watch on the system
Which of these statements are correct?
a. 1, 2, 3 and 4
b. 1, 2 and 3
c. 1 and 2 only
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
d. 3 and 4 only
Answer: (c).1 and 2 only
16. Ready pin of microprocessor is used
a. to indicate that microprocessor is ready to receive inputs
b. to indicate that microprocessor is ready to receive outputs
c. to introduce wait state
d. to provide direct memory access
Answer: (c).to introduce wait state
17. Both the ALU and control section of CPU employ which special purpose
storage location?
a. Buffers
b. Decoders
c. Accumulators
d. Registers
Answer: (c).Accumulators
18. A high on RESET OUT signifies that
a. all the registers of the CPU are being reset
b. all the registers and counters are being reset
c. all the registers and counters are being reset and this signal can be used to
reset external support chip
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
d. processing can begin when this signal goes high
Answer: (c).all the registers and counters are being reset and this signal can be
used to reset external support chip
19. In a vector interrupt
a. the branch address is assigned to a fixed location in memory
b. the interrupting source supplies the branch information to the processor
through an interrupt vector
c. the branch address is obtained from a register in the processor
d. none of the above
Answer: (a).the branch address is assigned to a fixed location in memory
20. The content of the A15-A8 (higher order address lines) while executing “IN
8-bit port address” instruction are
a. same as the content of A7-A0
b. irrelevant
c. all bits reset (i.e. 00H)
d. all bits set (i.e. FFH)
Answer: (a).same as the content of A7-A0
21. Which one of the following interrupt is only level triggering?
a. TRAP
b. RST 7.5
c. RST 6.5 and RST 5.5
d. RST 6.5
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Answer: (c).RST 6.5 and RST 5.5
22. Which one of the following instruction may be used to clear the
accumulator content irrespective of its initial value?
a. CLR A
b. ORA A
c. SUB A
d. MOV A, 00H
Answer: (c).SUB A
23. ___________ signal prevent the microprocessor from reading the same data
more than one.
a. pipelining
b. handshaking
c. controlling
d. signaling
Answer: (b).handshaking
24. Data transfer between the microprocessor for peripheral takes place
through __________.
a. I/O port
b. input port
c. output port
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
d. multi port
Answer: (a).I/O port
25. 8255A operates with ________ power supply.
a. +5V
b. -5V
c. -10V
d. +10V
Answer: (a).+5V
26. The _______ allow data transfer between memory and peripherals.
a. DMA technique
b. Microprocessor
c. Register
d. Decoder
Answer: (a).DMA technique
27. Expansion of SPGA is _________.
a. Staggered Pin Grid-Array package
b. Staggered Point Grid-Array package
c. Staggered Plus Grid-Array package
d. Staggered per grid-Array package
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Answer: (a).Staggered Pin Grid-Array package
28. Pentium-pro processor design implements________ micro architecture.
a. P2
b. P4
c. P6
d. P8
Answer: (c).P6
29. The number of hardware chips needed for multiple digit display can be
minimized by using the technique called ______.
a. interfacing
b. multiplexing
c. demultiplexing
d. multiprocessing
Answer: (b).multiplexing
30. An RS-232 interface is ____________.
a. a parallel interface
b. a serial interface
c. printer interface
d. a modem interface
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Answer: (b).a serial interface
31. Expansion for DTE is ______.
a. data terminal equipment
b. data trap equipment
c. data text equipment
d. data terminal extension
Answer: (a).data terminal equipment
32. Compared with RS-232, USB is faster and uses___________.
a. medium voltage
b. higher voltage
c. lower voltage
d. None of the above
Answer: (c).lower voltage
33. Expansion for HMOS technology is _______.
a. high level mode oxygen semiconductor
b. high level metal oxygen semiconductor
c. high performance medium oxide semiconductor
d. high performance metal oxide semiconductor
Answer: (d).high performance metal oxide semiconductor
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
34. RIM is used to check whether, the ___________.
a. write operation is done or not
b. interrupt is Masked or not
c. interrupt is Masked
d. interrupt is not Masked
Answer: (b).interrupt is Masked or not
35. What does microprocessor speed depends on?
a. clock
b. data bus width
c. address bus width
d. signal bus
Answer: (c).address bus width
36. The advantage of memory mapped I/O over I/O mapped I/O is _________
a. faster operation
b. many instructions supporting memory mapped I/O
c. require a bigger address decoder
d. all the above
Answer: (d).all the above
37. In 8279 Status Word, data is read when ________ pins are low, and write to
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
the display RAM with ____________ are low.
a. A0, CS, RD & A0, WR, CS
b. CS, WR, A0 & A0, CS, RD
c. A0, RD & WR, CS
d. CS, RD & A0, CS
Answer: (a).A0, CS, RD & A0, WR, CS
38. In 8279, the keyboard entries are de bounced and stored in an _________,
that is further accessed by the CPU to read the key codes.
a. 8-bit FIFO
b. 8-byte FIFO
c. 16 byte FIFO
d. 16 bit FIFO
Answer: (b).8-byte FIFO
39. For the most Static RAM the write pulse width should be at least
a. 10 ns
b. 60 ns
c. 300 ns
d. 350 ns
Answer: (b).60 ns
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
40. Pentium-I, Pentium-II, Pentium-III and Pentium-IV are recently
introduced microprocessor by__________.
a. Motorala
b. Intel
c. Stephen Mors
d. HCL
Answer: (b).Intel
41. The address bus flow in __________.
a. bidirection
b. unidirection
c. mulidirection
d. circular
Answer: (b).unidirection
42. The 8085 microprocessor is based in a ________ pin DIP.
a. 40
b. 45
c. 20
d. 35
Answer: (a).40
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43. The 8085 Microprocessor uses__________ power supply.
a. +5V
b. -5V
c. +12V
d. -12V
Answer: (a).+5V
44. Which is used to store critical pieces of data during subroutines and
interrupts ?
a. Stack
b. Queue
c. Accumulator
d. Data register
Answer: (a).Stack
45. The data in the stack is called
a. Pushing data
b. Pushed
c. Pulling
d. None of these
Answer: (a).Pushing data
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46. The external system bus architecture is created using from ______
architecture.
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
Answer: (d).Von Neumann
47. Secondary memory can store____.
a. Program store code
b. Compiler
c. Operating system
d. All of these
Answer: (d).All of these
48. Secondary memory is also called____.
a. Auxiliary
b. Backup store
c. Both A and B
d. None of these
Answer: (c).Both A and B
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49. The lower red curvy arrow show that CPU places the address extracted
from the memory location on the_____.
a. Address bus
b. System bus
c. Control bus
d. Data bus
Answer: (a).Address bus
50. The CPU sends out a ____ signal to indicate that valid data is available on
the data bus.
a. Read
b. Write
c. Both a and b
d. None of these
Answer: (b).Write
UNIT-2
1. In 8085 microprocessor, how many interrupts are maskable.
a. Two
b. Three
c. Four
d. Five
Answer. c
2. Which stack is used in 8085 microprocessors?
a. FIFO
b. FILO
c. LIFO
d. LILO
Answer. c
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3. In the instruction of the 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
4. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
5. Which one of the following register of 8085 microprocessor is not a part of the
programming model?
a. Instruction register
b. Memory address register
c. Status register
d. Temporary data register
Answer. c
6. The program counter in 8085 microprocessor is a 16-bit register, because
a. It counts 16 bits at a time
b. There are 16 address times
c. It facilitates the users storing 16-bit data temporarily
d. It has to fetch two 8-bit data at a time.
Answer. b
7. A direct memory access (DMA) transfer replies
a. Direct transfer of data between memory and accumulator
b. Direct transfer of data between memory and I/O devices without the use of
microprocessor
c. Transfer of data exclusively within microprocessor registers
d. A fast transfer of data between microprocessor and I/O devices
Answer. b
8. Handshaking mode of data transfer is
a. Synchronous data transfer
b. asynchronous data transfer
c. interrupt driven data transfer
d. level Mode of DMA data transfer
Answer. a
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9. In a Microprocessor, the address of the new next instruction to be executed is
stored in
a. Stack pointer
b. address latch
c. Program counter
d. General purpose register
Answer. c
10. In how many different modes a universal shift register operates?
a. 2
b. 3
c. 4
d. 5
Answer. c
11. The insruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
12. Which one of the following statements is correct regarding the instruction
CMP A ?
a. compare accumulator with register A
b. compare accumulator with memory
c. compare accumulator with register H
d. This instruction does not exist
Answer. a
13. The instruction JNC 16-bit refers to jump to 16-bit address if ?
a. sign flag is set
b. carry flag is reset
c. zero flag is set
d. parity flag is reset
Answer. b
14. Among the given instructions, the one which affects the maximum number of
flags is ?
a. RAL
b. POP PSW
c. XRA A
d. DCR A
Answer. c
15. XCHG instruction of 8085 exchanges the content of ?
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a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
16. Direction flag is used with
a. string instructions
b. stack instructions
c. arithmetic instructions
d. branch instructions
Answer. a
17. The number of output pins of a 8085 microprocessor are
a. 40
b. 27
c. 21
d. 19
Answer. b
18. Following is a 16-bit register for 8085 microprocessor
a. Stack pointer
b. Accumulator
c. Register B
d. Register C
Answer. a
19. The register which holds the information about the nature of results of
arithmetic of logic operations is called as
a. Accumulator
b. Condition code register
c. Flag register
d. Process status registers
Answer. c
20. When referring to instruction words, a mnemonic is
a. a short abbreviation for the operand address.
b. a short abbreviation for the operation to be performed.
c. a short abbreviation for the data word stored at the operand address.
d. Shorthand for machine language.
Answer. b
21. While using a frequency counter for measuring frequency, two modes of
measurement are possible.
1. Period mode
2. Frequency mode
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There is a ‘cross-over frequency’ below which the period mode is preferred.
Assuming the crystal oscillator frequency to be 4 MHz the crossover frequency is
given by
a. 8 MHz
b. 2 MHz
c. 2 kHz
d. 1 kHz
Answer. b
22. In a 8085 microprocessor system with memory-mapped I/O, which of the
following is true?
a. Devices have 8-bit‘address line
b. Devices are accessed using IN and OUT instructions
c. There can be maximum of 256 input devices and 256 output devices
d. Arithmetic and logic operations can be directly performed with the I/O data
Answer. d
23. Consider the following statements:
Arithmetic Logic Unit (ALU)
1 . Performs arithmetic operations.
2. Performs comparisons.
3. Communicates with I/O devices.
4. Keeps watch on the system.
Which of these statements are correct?
a. 1, 2, 3 and 4
b. 1,2 and 3 only
c. 1 and 2 only
d. 3 and 4 only
Answer. c
24. Ready pin 0f microprocessor is used
a. to indicate that the microprocessor is ready to receive inputs
b. to indicate that the microprocessor is ready to receive outputs
c. to introduce wait state
d. to provide direct memory access
Answer. c
25. A bus connected between the CPU and the main memory that permits transfer
of information between main memory and the CPU is known as
a. DMA bus
b. Memory bus
c. Address bus
d. Control bus
Answer. b
26. The operations executed by two or more control units are referred as
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a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer. c
27. Consider the following registers:
1. Accumulator and flag register
2. B and C registers
3. D and E registers
4. H and L registers
Which of these 8-bit registers of 8085 μP can be paired together to make a 16-bit
register?
a. (a) 1, 3 and 4
b. 2, 3 and 4
c. 1, 2 and 3
d. 1, 2 and 4
Answer. b
28. The first microprocessor to include virtual memory in the Intel
microprocessor family is
a. 80286
b. 80386
c. 80486
d. Pentium
Answer. a
29. Program counter in a digital computer
a. counts the numbers of programs run in the machine ,
b. counts the number of times a subroutine is called
c. counts the number of times the loops are executed
d. points the memory address of the current or the next instruction to be
executed
Answer
Answer. d
30. Assuming LSB is at position 0 and MSB at position 7, which bit positions are
not used (undefined) in Flag Register of an 8085 microprocessor?
a. 1, 3, 5
b. 2, 3, 5
c. 1, 2, 5
d. 1, 3, 4
Answer. a
31. At the beginning of a fetch cycle, the contents of the program counter are
a. incremented by one
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b. transferred to address bus
c. transferred to memory address register
d. transferred to memory data register
Answer. c
32. Each instruction in an assembly language program has the following fields
1. Label field
2. Mnemonic field
3. Operand field
4. Comment field
What is the correct sequence of these fields?
a. 1, 2, 3 and 4
b. 2, 1, 4 and 3
c. 1,3, 2 and 4
d. 2, 4, 1 and 3
Answer. a
33. The relation among IC (lnstruction Cycle), FC (Fetch Cycle) and EC (Execute
Cycle) is
a. IC = FC − EC
b. IC = FC+ EC
c. IC= FC + 2EC
d. EC = IC+FC
Answer. b
34. When a peripheral is connected to the microprocessor in input/output mode,
the data transfer takes place between
a. any register and I/O device
b. memory and I/O device
c. accumulator and I/O device
d. HL registerand I/O device.
Answer. c
35. While execution of I/O instruction takes place, the 8-bit address of the port is
placed on
a. lower address bus
b. higher address bus
c. data bus
d. lower as well as higher-order address bus
Answer. d
36. The length of a bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and
an indeterminate number of wait state clock cycles denoted by TW. The wait
states are always inserted between
a. T1 and T2
b. T2 and T3
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c. T3 and T4
d. T4 and T1
Answer. c
37. Which one of the following circuits transmits two messages simultaneously in
one direction?
a. Duplex
b. Diplex
c. Simplex
d. Quadruplex
Answer. b
38. A microprocessor is ALU
a. and control unit on a single chip
b. and memory on a single chip
c. register unit and I/O device on a single chip
d. register unit and control unit on a single chip
Answer. d
39. In Intel 8085 microprocessor, ALE signal is made high to
a. Enable the data bus to be used as low order address bus
b. To latch data D0— D7 from the data bus
c. To disable data bus
d. To achieve all the functions listed above
Answer. a
40. Output of the assembler in machine codes is referred to as
a. Object program
b. Source program
c. Macro instruction
d. Symbolic addressing
Answer. a
41. Which one of the following statements for Intel 8085 is correct?
a. Program counter (PC) specifies the address of the instruction last executed
b. PC specifies the address of the instruction being executed
c. PC specifies the address of the instruction be executed
d. PC specifies the number of instruction executed so far
Answer. c
42. The instruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
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43. Which one of the following statements is correct regarding the instruction
CMP A?
a. Compare accumulator with register A
b. Compare accumulator with memory
c. Compare accumulator with register H
d. This instruction does not exist
Answer. a
44. The instruction JNC 16-bit refers to jump to 16-bit address if
a. Sign flag is set
b. Carry flag is reset
c. Zero flag is set
d. Parity flag is reset
Answer. b
45. Consider the following interrupts for 8085 microprocessor:
1. INTR
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. TRAP
If the interrupt is to be vectored to any memory location then which of the above
interrupt is/are correct?
a. 1 and 2 only
b. 1, 2, 3 and 4
c. 5 only
d. 1 only
Answer. d
46. Consider the following statements:
1. Auxiliary carry flag is used only by the DAA and DAS instruction.
2. Zero flag is set to 1 if the two operands compared are equal.
3. All conditional jumps are long type jumps.
Which of the above statements are correct?
a. 1, 2 and 3 only
b. 1 and 2 only
c. 1 and 3 only
d. 2 and 3 only
Answer. b
47. Among the given instructions, the one which affects maximum number of
flags is
a. RAL
b. POP PSW
c. XRA A
d. DCR A
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Answer. c
48. XCHG instruction of 8085 exchanges the content of
a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
49. Direction flag is used with
a. String instructions
b. Stack instructions
c. Arithmetic instructions
d. Branch instructions
Answer. a
50. What will be the contents of DE and HL register pairs respectively after the
execution of the following instructions?
LXIH, 2500 H
LXID, 0200 H
DAD D
XCHG
a. 0200 H, 2500 H
b. 0200 H, 2700 H
c. 2500 H, 0200 H
d. 2700 H, 0200 H
Answer. d
UNIT-3
51. In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
52. A ‘DAD H” instruction is the same as shifting each bit by one position to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
53. When a program is being executed in an 8085 microprocessor, its program
counter contains
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a.
the memory address as the instruction that is to be executed next.
b.
the memory address of the instruction that is being currently matched.
c.
the total number of instructions in the program being executed.
d.
the number of instructions in the current program that have already been
executed.
Answer. a
54. Which of the following data transfer is not possible in microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
55. LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
d. loads English like command and generates the binary code
Answer. b
56. Which of the following instructions is closest match to the instruction POP
PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
57. How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
58. Which of the following 8085 instruction will require maximum T-states for
execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
59. In 8085 microprocessor, which mode of addressing does the instruction CMP
M use?
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a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
60. With reference to 8085 microprocessor, which of the following statements
are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
61. Assume that the accumulator and the register C of 8085 microprocessor
contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution of
instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
62. It is desired to multiply the numbers 0A H by OB H and store the result in the
accumulator. The numbers are available in registers B and C respectively. A part
of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C
b. ADD B; JNZ LOOP; DCR C
c. DCR C; JNZ LOOP; ADD B
d. ADD B; DCR C; JNZ LOOP
Answer. d
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63. Find the content of the accumulator after the execution of the following
program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
64. The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
65. The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
66. The content of accumulator are 70 H. Initially all flags are zero. What will be
values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
67. A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
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How many times DCR instruction will be executed?
a. 255
b. 510
c. 65025
d. 65279
Answer. d
68. What is content of accumulator of 8085 microprocessor after the execution of
XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
69. The 8085 programming manual says that it takes seven T states to fetch and
execute the MOV instruction. If the system clock has a frequency of 2.5 MHz, how
long is an instruction Cycle?
a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
70. The instruction PCHL, in 8085 is used for
a. Load PC with contents of HL.
b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
71. The following instruction copies a byte of data from the accumulator into the
memory address given in the instruction
a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
72. The instruction that exchanges top of stack with HL pair is
a. XTHL
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b. SPHL
c. PUSH H
d. POP H
Answer. a
73. In 8085 microprocessor, during PUSH PSW Operation, Stack pointer is
a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
74. While a program is being executed in an Intel 8085 microprocessor, the
program counter of the microprocessor contains:
a. The memory address of the instruction that is being currently executed.
b. The memory address of the instruction that is to be executed next.
c. The number of instructions that have already been executed.
d. The total number of instructions in the current program still to be
executed.
Answer. b
75. The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
76. If the status of the control lines SI and SO is LOW, then 8085 microprocessor
is performing
a. Reset operation
b. HOLD operation
c. Halt operation
d. Interrupt acknowledge
Answer. c
77. LXI SP, 7FFF H
MVI A, 25 H
XRI 02 H
PUSH PSW
POP H
MOV A,L
ORI 10 H
HLT
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What are the contents of A, H, L, SP and PSW registers after executing the above
set of instructions? Assume undefined flags always remain clear.
a. 10H, 25H, 00H, 7FFFH, 00H respectively
b. 14H, 27H, 04H, 7FFFH, 04H respectively
c. 14H, 25H, 00H. 7FFFH, 04H respectively
d. 10H, 27H, 04H, 7FFFH, 00H respectively
Answer. b
78. The content of the programme counter of an 8085 microprocessor is
a. the total number of instructions in the program already executed.
b. the total number of times a subroutine is called.
c. the memory address of the instruction that is being currently executed.
d. the memory address of the instruction that is to be executed next.
Answer. d
79. The opcode for the instruction “Add Immediately to Accumulator with carry”
in 8085 microprocessor is
a. ADI
b. ACI
c. ADC
d. ADD
Answer. b
80. MVI A, AA H
ORI FFH
RRC
RRC
CMC
INR A
What are the contents of A and PSW registers after executing the above set of
instructions in sequence?
a. AAH and 00H
b. FFH and 66H
c. 00H and 54H
d. 00H and 00H
Answer. c
81. For which one of the following, the instruction XRA A in 8085 microprocessor
can be used?
a. Set the carry flag
b. Set the zero flag
c. Reset the carry flag and clear the accumulator
d. Transfer FFH to the accumulator
Answer. b
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82. An 8085 microprocessor is executing the programme as follows:
MVI A, 20H
MVI B, 10H
BACK: NOP
ADD B
RLC
JNC BACK
HLT
How many times the instruction NOP will be executed?
a. 4
b. 3
c. 2
d. 1
Answer. b
83. The stack pointer of an 8085 microprocessor is ABCD H. At the end of
execution of the sequence of instructions, what will be the content of the stack
pointer?
PUSH PSW
XTHL
PUSH D
JMP FC70 H
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
84. What is the correct 8085 assembly language instruction that stores the
contents of H and L registers into the memory locations 1080 H and 1081 H
respectively?
a. SPHL 1080 H
b. SHLD 1080 H
c. STAX 1080 H
d. SPHL 1081 H
Answer. b
85. When the operand requires for instruction is stored inside the processor, then
What this addressing mode is called?
a. Direct
b. Register
c. Implicit
d. Immediate
Answer. b
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86. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
87. In an instruction of 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
88. Which one is the indirect addressing mode in the following instructions?
a. LXI H 2050 H
b. MOV A, B
c. LDAX B
d. LDA 2050 H
Answer. c
89. The addressing mode used in the instruction JMP F347 H in case of an Intel
8085A microprocessor is which one of the following?
a. Direct
b. Register—indirect
c. Implicit
d. Immediate
Answer. d
90. Carry flag is not affected after the execution of
a. ADD B
b. SBB B
c. INR B
d. ORA B
Answer. c
91. The contents of the Program Counter (PC), when the microprocessor is
reading from 2FFF H memory location, will be
a. 2FFE H
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b. 2FFF H
c. 3000 H
d. 3001 H
Answer. c
92. If the HLT instruction of an Intel 8085A microprocessor is executed
a. the microprocessor is disconnected from the system bus till the RESET is
pressed.
b. the microprocessor halts the execution of the program and returns to the
monitor.
c. the microprocessor enters into a HALT state and the buses are tri-stated.
d. the microprocessor reloads the program counter from the locations 0024 H
and 0025 H.
Answer. c
93. The stack pointer of an 8085 A microprocessor contains ABCD H.
PUSH PSW
XTHL
PUSH D
JMP EC75 H
At the end of the execution of the above instructions, what would be the content
of the stack pointer?
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
94. In an Intel 8085 A, what is the content of the Instruction Register (IR)?
a. Op-code for the instruction being executed
b. Operand for the instruction being executed
c. Op-code for the instruction to be executed next
d. Operand for the instruction to be executed next
Answer. a
95. The content of the Program Counter of an intel 8085A microprocessor
specifies which one of the following?
a. The address of the instruction being executed
b. The address of the instruction executed earlier
c. The address of the next instruction to be executed
d. The number of instructions executed so far
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Answer. c
96. Which one of the following statement does not describe
property/characteristic of a stack pointer register in 8085 microprocessor?
a. It points to the top of the stack.
b. It is UP/DOWN counter
c. It is automatically initialized to 0000 H on power-on
d. It is a 16-bit register
Answer. c
97. Which one of the following instructions is a 3-byte instruction?
a. MVI A
b. LDAX B
c. JMP 2050 H
d. MOV A,M
Answer. c
98. In 8085, the DAA instruction is used for
a. Direct Address Accumulator
b. Double Add Accumulator
c. Decimal Adjust Accumulator
d. Direct Access Accumulator
Answer. c
99. When an 8086 executes an INT type instruction, it?
a. Resets both IF and TF flags
b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
100. When an 8086 executes an INT type instruction, it?
a. Resets both IF and TF flags
b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
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UNIT-4
ASSEMBLY LANGUAGE PROGRAMMING Multiple Choice Questions :-
1) Assembly language programs are written using
A) Hex code
B) Mnenonics
C) ASCII code
D) None of these View
ANS: B
2) For execution of an interrupt applied at INTR, number of states required by
8085 Microprocessor are
A) 4
B) 6
C) 12
D) 18
ANS: C
3) In 8085 which is/are the 16 bit registers?
A) Program Counter
B) Stack Pointer
C) Both A) & B)
D) None of the above
ANS: C
4) How many memory locations are required to store the instruction LXIH,
0800H in an 8085 assembly language program?
A) 1
B) 2
C) 3
D) 4
ANS: B
5) The instruction DEC N inform the assembler to....
A) Decrement the content of N
B) Decrement the data addressed by N
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C) Convert signed decimal number to binary
D) None of the above
ANS: A
6) In 8085 microprocessor, the value of the most significant bit of the result
following the execution of any arithmetic or Boolean instruction is stored in
the
A) carry status flag
B) auxiliary carry status flag
C) sign status flag
D) zero status flag
ANS: C
7) Instructions performing actions in assembly language are called
A) imperative statements
B) declarative statements
C) directive statements
D) none of the above
ANS: A
8) What is the content of Stack Pointer ?
A) Address of the current instruction
B) Address of the next instruction
C) Address of the top element of the stack
D) None of the above
ANS: C
9) Which of the following interrupt has highest Priority?
A) INTR
B) TRAP
C) RST 7.5
D) RST 6.5
ANS: B
10) Number of machine cycles required for RET instruction in 8085
microprocessor is
A) 1
B) 2
C) 3
D) 5
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ANS: C
11) __________ converts the programs written in assembly language into
machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
Answer: c
Clarification: An assembler is a software used to convert the programs into
machine instructions.
12) The instructions like MOV or ADD are called as ______
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned
Answer: a
Clarification: This OP – codes tell the system what operation to perform on the
operands.
13) The alternate way of writing the instruction, ADD #5,R1 is ______
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way
Answer: b
Clarification: The ADDI instruction, means the addition is in immediate
addressing mode.
14) Instructions which won’t appear in the object program are called as
_____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
Answer: d
Clarification: The directives help the program in getting compiled and hence
won’t be there in the object code.
15) The assembler directive EQU, when used in the instruction: Sum EQU
200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
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c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
Answer: b
Clarification: This basically is used to replace the variable with a constant value.
16) The purpose of the ORIGIN directive is __________
a) To indicate the starting position in memory, where the program block is
to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used
Answer: a
Clarification: This does the function similar to the main statement.
17) The directive used to perform initialization before the execution of
the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU
Answer: c
Clarification: None.
18) _____ directive is used to specify and assign the memory required for
the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve
Answer: d
Clarification: This instruction is used to allocate a block of memory and to store
the object code of the program there.
19) _____ directive specifies the end of execution of a program.
a) End
b) Return
c) Stop
d) Terminate
Answer: b
Clarification: This instruction directive is used to terminate the program
execution.
20) The last statement of the source program should be _______
a) Stop
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b) Return
c) OP
d) End
Answer: d
Clarification: This enables the processor to load some other process.
21) When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive
Answer: c
Clarification: When the assembler comes across the branch code, it immediately
finds the branch offset and replaces it with it.
22) The assembler stores all the names and their corresponding values in
______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned
Answer: b
Clarification: The table where the assembler stores the variable names along with
their corresponding memory locations and values.
23) The assembler stores the object code in ______
a) Main memory
b) Cache
c) RAM
d) Magnetic disk
Answer: d
Clarification: After compiling the object code, the assembler stores it in the
magnetic disk and waits for further execution.
24) The utility program used to bring the object code into memory for
execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker
Answer: a
Clarification: The program is used to load the program into memory.
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25) To overcome the problems of the assembler in dealing with
branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
Answer: d
Clarification: This creates entries into the symbol table first and then creates the
object code.
26) In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
27) A ‘DAD H” instruction is the same as shifting each bit by one position
to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
28) When a program is being executed in an 8085 microprocessor, its
program counter contains
a. the memory address as the instruction that is to be executed next.
b. the memory address of the instruction that is being currently matched.
c. the total number of instructions in the program being executed.
d. the number of instructions in the current program that have already been
executed.
Answer. a
29) Which of the following data transfer is not possible in
microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
30) LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
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d. loads English like command and generates the binary code
Answer. b
31) Which of the following instructions is closest match to the
instruction POP PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
32) How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
33) Which of the following 8085 instruction will require maximum T-
states for execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
34) In 8085 microprocessor, which mode of addressing does the
instruction CMP M use?
a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
35) With reference to 8085 microprocessor, which of the following
statements are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
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36) Assume that the accumulator and the register C of 8085
microprocessor contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution
of instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
37) It is desired to multiply the numbers 0A H by OB H and store the
result in the accumulator. The numbers are available in registers B and C
respectively. A part of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C
b. ADD B; JNZ LOOP; DCR C
c. DCR C; JNZ LOOP; ADD B
d. ADD B; DCR C; JNZ LOOP
Answer. d
38) Find the content of the accumulator after the execution of the
following program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
39) The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
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a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
40) The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
41) The content of accumulator are 70 H. Initially all flags are zero. What
will be values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
42) A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR instruction will be executed?
a. 255
b. 510
c. 65025
d. 65279
Answer. d
43) What is content of accumulator of 8085 microprocessor after the
execution of XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
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44) The 8085 programming manual says that it takes seven T states to
fetch and execute the MOV instruction. If the system clock has a frequency
of 2.5 MHz, how long is an instruction Cycle?
a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
45) The instruction PCHL, in 8085 is used for
a. Load PC with contents of HL.
b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
46) The following instruction copies a byte of data from the accumulator
into the memory address given in the instruction
a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
47) The instruction that exchanges top of stack with HL pair is
a. XTHL
b. SPHL
c. PUSH H
d. POP H
Answer. a
48) In 8085 microprocessor, during PUSH PSW Operation, Stack pointer
is
a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
49) While a program is being executed in an Intel 8085 microprocessor,
the program counter of the microprocessor contains:
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a.The memory address of the instruction that is being currently executed.
b.The memory address of the instruction that is to be executed next.
c.The number of instructions that have already been executed.
d.The total number of instructions in the current program still to be
executed.
Answer. b
50) The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
UNIT-5
Microprocessors Questions and Answers – Programmable DMA Interface
8237 (Part-1)
1. The block of 8237 that decodes the various commands given to the 8237 by the
CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: b
Explanation: The program control block decodes various commands given to the
8237 by the CPU before servicing a DMA request.
2. The priority between the DMA channels requesting the services can be
resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: c
Explanation: The priority encoder block resolves the priority between the DMA
channels requesting the services.
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3. The register that holds the current memory address is
a) current word register
b) current address register
c) base address register
d) command register
Answer: b
Explanation: The current address register holds the current memory address. The
current address register is accessed during the DMA transfer.
4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register
Answer: a
Explanation: The current word register is a 16-bit register that holds the data
transfers. The word count is decremented after each transfer, and the new value
is stored again in the register.
5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated
Answer: c
Explanation: When the count becomes zero, the EOP signal is generated. This can
be written in successive bytes by the CPU, in program mode.
6. The current address register is programmed by the CPU as
a) bit-wise
b) byte-wise
c) bit-wise and byte-wise
d) none of the mentioned
View Answer
Explanation: The current address register is byte-wise programmed by the CPU,
i.e. lower byte first and the higher byte later.
7. Which of these register’s contents is used for auto-initialization (internally)?
a) current word register
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b) current address register
c) base address register
d) command register
Answer: c
Explanation: The contents of base address register cannot be read by the CPU.
These contents are used internally for auto-initialization.
8. The register that maintains an original copy of the respective initial current
address register and current word register is
a) mode register
b) base address register
c) command register
d) mask register
Answer: b
Explanation: The base address register maintains an original copy of the current
address register and current word register, before incrementing or
decrementing.
9. The register that can be automatically incremented or decremented, after each
DMA transfer is
a) mask register
b) mode register
c) command register
d) current address register
Answer: d
Explanation: The address is automatically incremented or decremented after
each DMA transfer, and the resulting address value is again stored in the current
address register.
10. Which of the following is a type of DMA transfer?
a) memory read
b) memory write
c) verify transfer
d) all of the mentioned
Answer: d
Explanation: Memory read, memory write and verify transfer are the three types
of DMA transfer.
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Microprocessors Questions and Answers – 8255 programmable peripheral
interface-(Part-2)
Question 1: How many pins does the 8255 PPI IC contains?
a. 24
b. 20
c. 32
d. 40
Answer: d. 40
Question 2: In which mode do all the Ports of the 8255 PPI work as Input-Output
units for data transfer?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: b. Mode 0 of I/O mode
Question 3: Which of the following pins are responsible for handling the on the
Read Write control logic unit of the 8255 PPI?
a. CS'
b. RD'
c. WR'
d. ALL of the above
Answer: d. All of the above
Question 4: In which of the following modes is the 8255 PPI capable of
transferring data while handshaking with the interfaced device?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: c. Mode 1 of I/O mode
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Question 5: How many bits of data can be transferred between the 8255 PPI and
the interfaced device at a time? or What is the size of internal bus of the 8255
PPI?
a. 16 bits
b. 12 bits
c. 8 bits
d. None of the above
Answer: c. 8 bits
Question 6: Which port of the 8255 PPI is capable of performing the handshaking
function with the interfaced devices?
a. Port A
b. Port B
c. Port C
d. All of the above
Answer: c. Port C
Question 7: In which of the following modes of the 8255 PPI, only port C is taken
into consideration?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: a. BSR mode
Question 8: In mode 2 of I/O mode, which of the following ports are capable of
transferring the data in both the directions?
a. Port A
b. Port B
c. Port C
d. All of the above
Answer: a. Port A
Question 9: In which of the following modes we do not consider the D6, D5 and
D4 bits of the control word?
a. BSR mode
b. Mode 0 of I/O mode
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c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: a. BSR mode
Question 10: How many data lines in total are there in the 8255 PPI IC?
a. 8 data lines
b. 32 data lines
c. 24 data lines
d. None of the above
Answer: c. 24 data lines
Microprocessors Questions and Answers – 8253/8254programmable
timer/counter-(Part-3)
1. The number of counters that are present in the programmable timer device
8254 is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: There are three counters that can be used as either counters or
delay generators.
2. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
Answer: b
Explanation: The control word register can only be written and cannot be read.
3. The mode that is used to interrupt the processor by setting a suitable terminal
count is
a) mode 0
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b) mode 1
c) mode 2
d) mode 3
Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.
4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output
becomes low for
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If
the count N is reloaded and again the output becomes high and remains so for (N-
1) clock pulses.
5. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Answer: c
Explanation: When the count N loaded is even, then for half of the count, the
output remains high and for the remaining half it remains low. If the count loaded
is odd, the first clock pulse decrements it by 1 resulting in an even count value.
6. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
Answer: b
Explanation: SC denotes select counter.
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7. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.
8. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is
BCD count.
9. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.
10. The control word register contents are used for
a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.
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Microprocessors Questions and Answers – 8259 programmable interrupt
controller-(Part-4)
1. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7
View Answer
Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these
five, four pins were alloted fixed vector addresses but the pin INTR was not
alloted by vector address, rather an external device was supposed to hand over
the type of the interrupt to the microprocessor.
2. The register that stores all the interrupt requests in it in order to serve them
one by one on a priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request
Register internally.
3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request
Register) at the direction of the Priority Resolver.
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4. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
Answer: d
Explanation: The interrupt control logic performs all the operations that are
involved within the interrupts like accepting and managing interrupt
acknowledge signals, interrupts.
5. In a cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64
vectored interrupts can be provided.
6. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode,
then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a
buffer enable to control buffer transreceivers. If it is not used in buffered mode,
then the pin is used as input to designate whether the chip is used as a master or
a slave.
7. Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
Answer: d
Explanation: The initialization procedure involves
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i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.
8. When non-specific EOI command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will
automatically reset the highest ISR.
9. In the application where all the interrupting devices are of equal priority, the
mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
Answer: a
Explanation: The automatic rotation is used in the applications where all the
interrupting devices are of equal priority.
Microprocessors Questions and Answers – 8251 USART and
RS232C- (Part-5)
1. Which of the following is not a mode of data transmission?
a) simplex
b) duplex
c) semi duplex
d) half duplex
Answer: c
Explanation: Basically, there are three modes of data transmission. simplex,
duplex and half duplex.
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2. If the data is transmitted only in one direction over a single communication
channel, then it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: a
Explanation: In simplex mode, the data transmission is unidirectional. For
example, a CPU may transmit data for a CRT display unit in this mode.
3. If the data transmission takes place in either direction, but at a time data may
be transmitted only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: d
Explanation: In half duplex mode, data transmission is bidirectional but not at a
time. For example, Walkie-Talkie.
4. In 8251A, the pin that controls the rate at which the character is to be
transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)
Answer: a
Explanation: Transmitter Clock Input (TXC(active low)) is a pin that controls the
rate at which the character is to be transmitted.
5. TXD(Transmitted Data Output) pin carries serial stream of the transmitted
data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned
Answer: d
Explanation: Transmitted Data Output pin carries a serial stream of the
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transmitted data bits along with other information like start bits, stop bits and
parity bits etc.
6. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY(Transmitter ready)
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)
Answer: b
Explanation: RXRDY(Receiver ready output) may be used either to interrupt the
CPU or polled by the CPU.
7. The disadvantage of RS-232C is
a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned
Answer: d
Explanation: RS232C has been used for long and has a few disadvantages like
limited speed of communication, high-voltage level signaling and big-size
communication adapters.
8. The USB supports the signaling rate of
a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned
Answer: d
Explanation: The USB standards support the signaling rates. Also, USB signaling is
implemented in a differential in low- and full-speed options.
9. The bit packet that commands the device either to receive data or transmit
data in transmission of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Answer: b
Explanation: The token packet is the second type of packet which commands the
device either to receive data or transmit data.
10. High speed USB devices neglect
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
Answer: c
Explanation: PRE packets are only of importance to low-speed USB devices.
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→Telegram Group
1. A microcontroller at-least should consist of:
a) RAM, ROM, I/O ports and timers
b) CPU, RAM, I/O ports and timers
c) CPU, RAM, ROM, I/O ports and timers
d) CPU, ROM, I/O ports and timers
Answer: c
Explanation: A microcontroller at-least consists of a processor as its CPU with RAM, ROM, I/O ports and timers. It
may contain some additional peripherals like ADC, PWM, etc.
2. Unlike microprocessors, microcontrollers make use of batteries because they have:
a) high power dissipation
b) low power consumption
c) low voltage consumption
d) low current consumption
Answer: b
Explanation: Micro Controllers are made by using the concept of VLSI technology. So here, CMOS based logic gate
s are coupled together by this technique that consumes low power.
3. What is the order decided by a processor or the CPU of a controller to execute an instruction?
a) decode,fetch,execute
b) execute,fetch,decode
c) fetch,execute,decode
d) fetch,decode,execute
Answer: d
Explanation: First instruction is fetched from Program Memory. After fetching, instruction is decoded to generate co
ntrol signals to perform the intended task. After decoding, instruction is executed and the complete intended task of t
hat particular instruction.
4. If we say microcontroller is 8-bit then here 8-bit denotes size of:
a) Data Bus
b) ALU
c) Control Bus
d) Address Bus
Answer: b
Explanation: If we say a microcontroller is 8-bit it means that it is capable of processing 8-bit data at a time. Data pr
ocessing is the task of ALU and if ALU is able to process 8-bit data then the data bus should be 8-bit wide. In most
books it tells that size of data bus but to be precise it is the size of ALU because in Harvard Architecture there are tw
o sets of data bus which can be of same size but it is not mandatory.
5. How are the performance and the computer capability affected by increasing its internal bus width?
a) it increases and turns better
b) it decreases
c) remains the same
d) internal bus width doesn’t affect the performance in any way
Answer: a
Explanation: As the bus width increases, the number of bits carried by bus at a time increases as a result of which th
e total performance and computer capability increases.
6. Abbreviate CISC and RISC.
a) Complete Instruction Set Computer, Reduced Instruction Set Computer
b) Complex Instruction Set Computer, Reduced Instruction Set Computer
c) Complex Instruction Set Computer, Reliable Instruction Set Computer
d) Complete Instruction Set Computer, Reliable Instruction Set Computer
Answer: b
Explanation: CISC means Complete Instruction Set Computer because in this a microcontroller has an instruction se
t that supports many addressing modes for the arithmetic and logical instructions, data transfer and memory accesses
instructions. RISC means Reduced Instruction Set Computer because here a microcontroller has an instruction set t
hat supports fewer addressing modes for the arithmetic and logical instructions and for data transfer instructions.
7. Give the names of the buses present in a controller for transferring data from one place to another?
a) data bus, address bus
b) data bus
c) data bus, address bus, control bus
d) address bus
Answer: c
Explanation: There are 3 buses present in a microcontroller they are data bus (for carrying data from one place to an
other), address bus (for carrying the address to which the data will flow) and the control bus (which tells the controll
er to execute which type of work at that address may be it read or write operation).
8. What is the file extension that is loaded in a microcontroller for executing any instruction?
a) .doc
b) .c
c) .txt
d) .hex
Answer: d
Explanation: Microcontrollers are loaded with .hex extension as they understand the language of 0’s and 1’s only.
9. What is the most appropriate criterion for choosing the right microcontroller of our choice?
a) speed
b) availability
c) ease with the product
d) all of the mentioned
Answer: d
Explanation: For choosing the right microcontroller for our product we must consider its speed so that the instructio
ns may be executed in the least possible time. It also depends on the availability so that the particular product may b
e available in our neighboring regions or market in our need. It also depends on the compatibility with the product s
o that the best results may be obtained.
10. Why microcontrollers are not called general purpose computers?
a) because they have built in RAM and ROM
b) because they design to perform dedicated task
c) because they are cheap
d) because they consume low power
Answer: b
Explanation: Microcontrollers are designed to perform dedicated tasks. While designing general purpose computers
end use is not known to designers.
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1. How many types of architectures are available, for designing a device that is able to work on its own?
a) 3
b) 2
c) 1
d) 4
Answer: b
Explanation: There are basically two main types of architectures present, they are Von Neumann and Harvard archit
ectures.
2. Which architecture is followed by general purpose microprocessors?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: b
Explanation: General purpose microprocessors make use of Von Neumann architecture as here a simpler design is of
fered.
3. Which architecture involves both the volatile and the non volatile memory?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a
Explanation: In Harvard architecture, both the volatile and the non volatile memories are involved. This is done to in
crease its efficiency as both the memories are being used over here.
4. Which architecture provides separate buses for program and data memory?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a
Explanation: Harvard Architecture provides separated buses for data and program memory to fetch program and dat
a simultaneously. By doing this access time is reduced and hence performance is increased.
5. Which microcontroller doesn’t match with its architecture below?
a) Microchip PIC- Harvard
b) MSP430- Harvard
c) ARM7- Von Neumann
d) ARM9- Harvard
Answer: b
Explanation: MSP430 supports Von Neumann architecture.
6. Harvard architecture has _____________
a) dedicated buses for data and program memory
b) pipeline technique
c) complex architecture
d) all of the mentioned
Answer: d
Explanation: Harvard Architecture has dedicated buses for data and program memory and pipeline technique becaus
e of this architecture is complex.
7. Which out of the following supports Harvard architecture?
a) ARM7
b) Pentium
c) SHARC
d) All of the mentioned
Answer: c
Explanation: SHARC supports harvard architecture for signal processing in DSP.
8. Why most of the DSPs use Harvard architecture?
a) they provide greater bandwidth
b) they provide more predictable bandwidth
c) they provide greater bandwidth & also more predictable bandwidth
d) none of the mentioned
Answer: c
Explanation: Most of the DSPs use harvard architecture because they provide a wider predictable bandwidth.
9. Which of the following supports CISC as well as Harvard architecture?
a) ARM7
b) ARM9
c) SHARC
d) None of the mentioned
Answer: c
Explanation: SHARC supports both the CISC and the Harvard architecture.
10. Which of the two architecture saves memory?
a) Harvard
b) Von Neumann
c) Harvard & Von Neumann
d) None of the mentioned
Answer: b
Explanation: As only one memory is present in the Von Neumann architecture so it saves a lot of memory.
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1. 8051 microcontrollers are manufactured by which of the following companies?
a) Atmel
b) Philips
c) Intel
d) All of the mentioned
Answer: d
Explanation: 8051 microcontrollers are manufactured by Intel, Atmel, Philips/Signetics, Infineon, Dallas Semi/Maxi
m.
2. AT89C2051 has RAM of:
a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
Answer: a
Explanation: It has 128 bytes of RAM in it.
3. 8051 series has how many 16 bit registers?
a) 2
b) 3
c) 1
d) 0
Answer: a
Explanation: It has two 16 bit registers DPTR and PC.
4. When 8051 wakes up then 0x00 is loaded to which register?
a) PSW
b) SP
c) PC
d) None of the mentioned
Answer: c
Explanation: When 8051 wakes up, Program Counter (P
c) loaded with 0000H. Because of this in 8051 first opcode is stored in ROM address at 0000H.
5. When the microcontroller executes some arithmetic operations, then the flag bits of which register are affected?
a) PSW
b) SP
c) DPTR
d) PC
Answer: a
Explanation: It stands for program status word. It consists of carry, auxiliary carry, overflow, parity, register bank se
lect bits etc which are affected during such operations.
6. How are the status of the carry, auxiliary carry and parity flag affected if the write instruction
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
Answer: b
Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so CY and AC are set to 1. In t
he result, the number of 1’s present are even so parity flag is set to zero.
7. How are the bits of the register PSW affected if we select Bank2 of 8051?
a) PSW.5=0 and PSW.4=1
b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
Answer: d
Explanation: Bits of PSW register are CY, AC, F0, RS1, RS0, OV, -, P so for selecting bank2 RS1=1 and RS0=0 wh
ich are fourth and third bit of the register respectively.
8. If we push data onto the stack then the stack pointer
a) increases with every push
b) decreases with every push
c) increases & decreases with every push
d) none of the mentioned
Answer: a
Explanation: If we push elements onto the stack then the stack pointer increases with every push of element.
9. On power up, the 8051 uses which RAM locations for register R0- R7
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
Answer: b
Explanation: On power up register bank 0 is selected which has memory address from 00H-07H.
10. How many bytes of bit addressable memory is present in 8051 based microcontrollers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
Answer: c
Explanation: 8051 microcontrollers have 16 bytes of bit addressable memory.
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1. “DJNZ R0, label” is ________ byte instruction.
a) 2
b) 3
c) 1
d) Can’t be determined
Answer: a
Explanation: DJNZ is 2-byte instruction. This means jump can be of -128 to +127 locations with respect to PC. Here
-128 means upward or backward jump and +127 means downward or forward jump.
2. JZ, JNZ, instructions checked content of _______ register.
a) DPTR
b) B
c) A
d) PSW
Answer: c
Explanation: JZ and JNZ instructions checked the content of A register and if condition was satisfied or true then ju
mp to target address.
3. Calculate the jump code for again and here if code starts at 0000H
a) F3,02
b) F9,01
c) E9,01
d) E3,02
Answer: c
Explanation: Loop address is calculated by subtracting destination address and the address next to the source address
.
4. When the call instruction is executed the topmost element of stack comes out to be
a) the address where stack pointer starts
b) the address next to the call instruction
c) address of the call instruction
d) next address of the stack pointer
Answer: b
Explanation: The topmost element of the stack is the address of the instruction next to the call instruction so that wh
en RET is executed then PC is filled with that address and so the pointer moves to the main program and continue w
ith its routine task.
5. LCALL instruction takes
a) 2 bytes
b) 4 bytes
c) 3 bytes
d) 1 byte
Answer: c
Explanation: LCALL instruction moves the pointer to a 16 bit address so it is a 3 byte instruction.
6. Are PUSH and POP instructions are a type of CALL instructions?
a) yes
b) no
c) none of the mentioned
d) cant be determined
Answer: b
Explanation: PUSH and POP instructions are not CALL instructions because in POP and PUSH instructions the poi
nter does not move to any location specified by its address which is the fundamental of CALL instruction, so it is no
t a type of CALL instruction.
7. What is the time taken by one machine cycle if crystal frequency is 20MHz?
a) 1.085 micro seconds
b) 0.60 micro seconds
c) 0.75 micro seconds
d) 1 micro seconds
Answer: b
Explanation: Time taken by one machine cycle is calculated by the inverse of a (crystal frequency) /12
8. Find the number of times the following loop will be executed
a) 100
b) 200
c) 20000
d) 2000
Answer: c
Explanation: It will be executed 200*100 times.
9. What is the meaning of the instruction MOV A,05H?
a) data 05H is stored in the accumulator
b) fifth bit of accumulator is set to one
c) address 05H is stored in the accumulator
d) none of the mentioned
Answer: c
Explanation: If we need to store the address in the accumulator, then directly the address is moved to it unlikely of u
sing # used for storing data in any register.
10. Do the two instructions mean the same?
a) yes
b) no
c) cant be determined
d) yes and the second one is preferred
Answer: b
Explanation: In the first statement, when the decrements approach zero then the jump moves back and in the second
statement, when the result after decrements is not zero, then it jumps back.
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1. To initialize any port as an output port what value is to be given to it?
a) 0xFF
b) 0x00
c) 0x01
d) A port is by default an output port
Answer: d
Explanation: In 8051, a port is initialized by default in its output mode no need to pass any value to it.
2. Which out of the four ports of 8051 needs a pull-up resistor for using it is as an input or an output port?
a) PORT 0
b) PORT 1
c) PORT 2
d) PORT 3
Answer: a
Explanation: These pins are the open drain pins of the controller which means it needs a pull-up resistor for using it
as an input or an output ports.
3. Which of the ports act as the 16 bit address lines for transferring data through it?
a) PORT 0 and PORT 1
b) PORT 1 and PORT 2
c) PORT 0 and PORT 2
d) PORT 1 and PORT 3
Answer: c
Explanation: PORT 0 and PORT 2 are used as the 16 bit address lines where PORT0 act as lower bit address lines a
nd PORT 2 as higher bit address lines.
4. Which of the following registers are not bit addressable?
a) SCON
b) PCON
c) A
d) PSW
Answer: b
Explanation: PCON register is not a bit addressable register.
5. Which instruction is used to check the status of a single bit?
a) MOV A,P0
b) ADD A,#05H
c) JNB PO.0, label
d) CLR P0.05H
Answer: b
Explanation: JNB which stands for Jump if no bit checks the status of the bit P0.0 and jumps if the bit is 0.
6. Which addressing mode is used in pushing or popping any element on or from the stack?
a) immediate
b) direct
c) indirect
d) register
Answer: c
Explanation: If we want to push or pop any element on or from the stack then direct addressing mode has to be used
in it, as the other way is not accepted.
7. Which operator is the most important while assigning any instruction as register indirect instruction?
a) $
b) #
c) @
d) &
Answer: b
Explanation: In register, indirect mode data is copied at that location where R0 or R1 are present, so @ operator is u
sed ex. MOV @R0,A
8. What is the advantage of register indirect addressing mode?
a) it makes use of registers R0 and R1
b) it uses the data dynamically
c) it makes use of operator @
d) it is easy
Answer: b
Explanation: Register indirect addressing mode is useful if a series of data is to be assigned to that address, with the
help of this quality the number of instructions decreases as a result of which performance increases.
9. Which of the following comes under the indexed addressing mode?
a) MOVX A, @DPTR
b) MOVC @A+DPTR,A
c) MOV A,R0
d) MOV @R0,A
Answer: b
Explanation: Indexed addressing mode stands for that instruction where the bits of the accumulator is also indexed w
ith the 16 bit registers.
PSST! You better watch out, something's buggy above.
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1. When we add two numbers the destination address must always be.
a) some immediate data
b) any register
c) accumulator
d) memory
Answer: c
Explanation: For addition purposes, the destination address must always be an accumulator. Example- ADD A,R0;
ADD A, @R1; ADD A,@ DPTR
2. DAA command adds 6 to the nibble if:
a) CY and AC are necessarily 1
b) either CY or AC is 1
c) no relation with CY or AC
d) CY is 1
Answer: b
Explanation: DAA command adds 6 to the nibble if any of the nibbles becomes greater than 9.
3. If SUBB A,R4 is executed, then actually what operation is being applied?
a) R4+A
b) R4-A
c) A-R4
d) R4+A
Answer: c
Explanation: SUBB command subtracts with borrow the contents of an accumulator with that of the register or some
immediate value. So A-R4 is being executed.
4. A valid division instruction always makes:
a) CY=0,AC=1
b) CY=1,AC=1
c) CY=0,AC=0
d) no relation with AC and CY
Answer: c
Explanation: When we divide two numbers then AC and CY become zero.
5. In 8 bit signed number operations, OV flag is set to 1 if:
a) a carry is generated from D7 bit
b) a carry is generated from D3 bit
c) a carry is generated from D7 or D3 bit
d) a carry is generated from D7 or D6 bit
Answer: d
Explanation: In 8 bit operations, if a carry is generated from D6 or D7 bit, then OV flag is set to 1.
6. In unsigned number addition, the status of which bit is important?
a) OV
b) CY
c) AC
d) PSW
Answer: b
Explanation: If unsigned numbers operations are involved, then the status of CY flag is important and in signed num
ber operation the status of OV flag is important.
7. Which instructions have no effect on the flags of PSW?
a) ANL
b) ORL
c) XRL
d) All of the mentioned
Answer: d
Explanation: These instructions are the arithmetic operations and the flags are affected by the data copy instructions,
so all these instructions don’t affect the bits of the flag.
8. ANL instruction is used _______
a) to AND the contents of the two registers
b) to mask the status of the bits
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: ANL instruction is used to AND the contents of the two registers and is also used to mask the status of
the bits of the register.
9. CJNE instruction makes _______
a) the pointer to jump if the values of the destination and the source address are equal
b) sets CY=1, if the contents of the destination register are greater then that of the source register
c) sets CY=0, if the contents of the destination register are smaller then that of the source register
d) none of the mentioned
Answer: d
Explanation: In CJNE command, the pointer jumps if the values of the two registers are not equal and it resets CY if
the destination address is larger then the source address and sets CY if the destination address is smaller then the so
urce address.
10. XRL, ORL, ANL commands have _______
a) accumulator as the destination address and any register, memory or any immediate data as the source address
b) accumulator as the destination address and any immediate data as the source address
c) any register as the destination address and accumulator, memory or any immediate data as the source address
d) any register as the destination address and any immediate data as the source address
Answer: a
Explanation: These commands have accumulator as the destination address and any register, memory or any immedi
ate data as the source address.
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1. What is the clock source for the timers?
a) some external crystal applied to the micro-controller for executing the timer
b) from the crystal applied to the micro-controller
c) through the software
d) through programming
Answer: b
Explanation: Timer’s clock source is the crystal that is applied to the controller.
2. What is the frequency of the clock that is being used as the clock source for the timer?
a) some externally applied frequency f’
b) controller’s crystal frequency f
c) controller’s crystal frequency /12
d) externally applied frequency/12
Answer: c
Explanation: The frequency of the clock source for the timer is equal to f/12(where f is the frequency of the crystal).
3. What is the function of the TMOD register?
a) TMOD register is used to set various operation modes of timer/counter
b) TMOD register is used to load the count of the timer
c) Is the destination or the final register where the result is obtained after the operation of the timer
d) Is used to interrupt the timer
Answer: a
Explanation: TMOD is used to set various operation modes of timer/counter by the programmer.
4. What is the maximum delay that can be generated with the crystal frequency of 22MHz?
a) 2978.9 sec
b) 0.011 msec
c) 11.63 sec
d) 2.97 msec
Answer: d
Explanation: For generating the maximum delay we have to multiply the maximum number of counts with the time
period required to execute one machine cycle( 65536*1/22MHz).
5. Auto reload mode is allowed in which mode of the timer?
a) Mode 0
b) Mode 1
c) Mode 2
d) Mode 3
Answer: c
Explanation: Auto reload is allowed in the Mode 2 of the timer because here in this mode, we don’t need to load the
count again and again in the register.
6. Find out the roll over value for the timer in Mode 0, Mode 1 and Mode 2?
a) 00FFH,0FFFH,FFFFH
b) 1FFFH,0FFFH,FFFFH
c) 1FFFH,FFFFH,00FFH
d) 1FFFH,00FFH,FFFFH
Answer: c
Explanation: For Mode 0 13 bit value is used so 1FFFH is chosen to be the roll over value. Similarly for Mode 1 FF
FFH and for Mode 2 FFH is the roll over value for the timers and counter.
7. What steps are followed when we need to turn on any timer?
a) load the count, start the timer, keep monitoring it, stop the timer
b) load the TMOD register, load the count, start the timer, keep monitoring it, stop the timer
c) load the TMOD register, start the timer, load the count, keep monitoring it, stop the timer
d) none of the mentioned
Answer: b
Explanation: When any timer is to turn on, then firstly we have to load the TMOD register and the count. Then the ti
mer is to get started. After then, we need to monitor the timer properly and then when the roll over condition arises t
hen the timer is to be stopped.
8. If Timer 0 is to be used as a counter, then at what particular pin clock pulse need to be applied?
a) P3.3
b) P3.4
c) P3.5
d) P3.6
Answer: b
Explanation: If Timer 0 is to be used as a counter, then a pulse has to be applied at P3.4 and if it is for Timer 1 then t
he clock pulse has to be applied at the pin P3.5.
9. In the instruction “MOV TH1,#-3”, what is the value that is being loaded in the TH1 register?
a) 0xFCH
b) 0xFBH
c) 0xFDH
d) 0xFEH
Answer: c
Explanation: Negative value is loaded in 2’s complement form. -3 represented in 2’s complement form as FDH.
10. TF1, TR1, TF0, TR0 bits are of which register?
a) TMOD
b) SCON
c) TCON
d) SMOD
Answer: c
Explanation: All of these bits are part of TCON (Timer Control) register. TF0 and TF1 are used to check overflow o
f timer 0 and timer 1 respectively. TR0 and TR1 are timer control bits used to start and stop of timer 0 and timer 1 re
spectively.
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1. Which devices are specifically being used for converting serial to parallel and from parallel to serial respectively?
a) timers
b) counters
c) registers
d) serial communication
Answer: c
Explanation: Some registers like the parallel in serial out and serial in parallel out are used to convert serial data into
parallel and vice versa respectively.
2. What is the difference between UART and USART communication?
a) they are the names of the same particular thing, just the difference of A and S is there in it
b) one uses asynchronous means of communication and the other uses synchronous means of communication
c) one uses asynchronous means of communication and the other uses asynchronous and synchronous means of com
munication
d) one uses angular means of the communication and the other uses linear means of communication
Answer: c
Explanation: UART stands for Universal Asynchronous receiver-transmitter and USART stands for Universal Sync
hronous and Asynchronous receiver-transmitter.
3. Which of the following best describes the use of framing in asynchronous means of communication?
a) it binds the data properly
b) it tells us about the start and stops of the data to be transmitted or received
c) it is used for error checking
d) it is used for flow control
Answer: b
Explanation: In data framing in asynchronous means of communication, the data is packed between the start and the
stop bit. This is done so as to tell the other computer about the start and the end of the data.
4. Which of the following signal control the flow of data?
a) RTS
b) DTR
c) RTS & DTR
d) None of the mentioned
Answer: a
Explanation: RTS is a request to send control signal which is a control for the flow of data. On the other hand DTR i
s a Data Terminal Ready control signal which tells about the current status of the DTE.
5. Which of the following is the logic level understood by the micro-controller/micro-processor?
a) TTL logic level
b) RS232 logic level
c) None of the mentioned
d) TTL & RS232 logic level
Answer: a
Explanation: TTL logic or the transistor logic level is the logic that is understood by the micro-controllers/microproc
essors.
6. What is a null modem connection?
a) no data transmission
b) no MAX232
c) the RxD of one is the TxD for the other
d) no serial communication
Answer: c
Explanation: In null modem connection the RxD of one is the TxD for the other.
7. Which of the following best states the reason that why baud rate is mentioned in serial communication?
a) to know about the no of bits being transmitted per second
b) to make the two devices compatible with each other, so that the transmission becomes easy and error free
c) to use Timer 1
d) for wasting memory
Answer: b
Explanation: To make two devices compatible with each other baud rate is mentioned in the serial communication s
o that the transmission becomes easy and error free.
8. With what frequency UART operates( where f denoted the crystal frequency )?
a) f/12
b) f/32
c) f/144
d) f/384
Answer: d
Explanation: UART frequency is the crystal frequency f/12 divided by 32, that comes out to be f/384.
9. What is the function of the SCON register?
a) to control SBUF and SMOD registers
b) to program the start bit, stop bit, and data bits of framing
c) to control SMOD registers
d) none of the mentioned
Answer: b
Explanation: SCON register is mainly used for programming the start bits, stop bits and data bits of framing. As it c
onsists of bits like RB8, TB8, SM0, SM1, SM2 etc.
10. What should be done if we want to double the baud rate?
a) change a bit of the TMOD register
b) change a bit of the PCON register
c) change a bit of the SCON register
d) change a bit of the SBUF register
Answer: b
Explanation: PCON register consists of SMOD bit as its D7 bit, so if we set this bit then the baud rate gets doubled.
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1. When an interrupt is enabled, then where does the pointer moves immediately after this interrupt has occurred?
a) to the next instruction which is to be executed
b) to the first instruction of ISR
c) to a fixed location in memory called interrupt vector table
d) to the end of the program
Answer: c
Explanation: When an interrupt occurs, then it jumps to a fixed memory location in memory called the interrupt vect
or table that holds the address of the Interrupt Service Routine.
2. What are the contents of the IE register, when the interrupt of the memory location 0x00 is caused?
a) 0xFFH
b) 0x00H
c) 0x10H
d) 0xF0H
Answer: b
Explanation: When interrupt of 0x00 is caused (the reset interrupt) then all the other interrupts will be disabled or th
e contents of the IE register becomes null.
3. After RETI instruction is executed then the pointer will move to which location in the program?
a) next interrupt of the interrupt vector table
b) immediate next instruction where interrupt is occurred
c) next instruction after the RETI in the memory
d) none of the mentioned
Answer: b
Explanation: When the RETI instruction is executed, PC will fetch 2-bytes (address) from top of stack which is store
d when interrupt is occurred. This will return to the place where interrupt is occurred and starts executing instruction
s.
4. Which pin of the external hardware is said to exhibit INT0 interrupt?
a) pin no 10
b) pin no 11
c) pin no 12
d) pin no 13
Answer: c
Explanation: INT0 interrupt is caused when pin no 12 in the hardware of the 8051 controller is enabled with a low le
veled pulse.
5. Which bit of the IE register is used to enable TxD/RxD interrupt?
a) IE.D5
b) IE.D2
c) IE.D3
d) IE.D4
Answer: d
Explanation: IE.D4 is used to enable RS interrupt or the serial communication interrupt.
6. Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register (assu
ming initially all bits of the IE register are zero)?
a) EX0=1
b) EA=1
c) any of the mentioned
d) EX0=1 & EA=1
Answer: d
Explanation: For executing the EX0 interrupt, the EX0 and EA bits of the IE register should be set. EA is set to enab
le all the interrupts and EX0 is set to enable the external hardware interrupt 0 interrupt and mask the other enabled in
terrupts.
7. Why normally LJMP instructions are the topmost lines of the ISR?
a) so as to jump to some other location where there is a wider space of memory available to write the codes
b) so as to avoid overwriting of other interrupt instructions
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: There is a small space of memory present in the vector table between two different interrupts so in orde
r to avoid overwriting of other interrupts we normally jump to other locations where a wide range of space is availab
le.
8. Which register is used to make the interrupt level or an edge triggered pulse?
a) TCON
b) IE
c) IPR
d) SCON
Answer: a
Explanation: TCON register is used to make any interrupt level or edge triggered.
9. What is the disadvantage of a level triggered pulse?
a) a constant pulse is to be maintained for a greater span of time
b) another interrupt may be generated if the low-level signal is not removed before the ISR is finished
c) it is difficult to produce
d) another interrupt may be caused if the signal is still low before the completion of the last instruction
Answer: d
Explanation: In a level triggered interrupt, if the low signal at interrupt pin must be removed before the execution of
last instruction of the ISR i.e. RETI. If low signal at interrupt pin is not removed before completing the ISR then it w
ill be generating another interrupt.
10. What is the correct order of priority that is set after a controller gets reset?
a) RI/TI > TF1 > TF0 > INT1 > INT0
b) RI/TI < TF1 < TF0 < INT1 < INT0
c) INT0 > TF0 > INT1 > TF1 > RI/TI
d) INT0 < TF0 < INT1 < TF1 < RI/TI
Answer: c
Explanation: On reset Interrupt Priorities are as INT0 > TF0 > INT1 > TF1 > RI/TI, where ‘>’ is used to denote high
est priority.
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1. How many rows and columns are present in a 16*2 alphanumeric LCD?
a) rows=2, columns=32
b) rows=16, columns=2
c) rows=16, columns=16
d) rows=2, columns=16
Answer: d
Explanation: 16*2 alphanumeric LCD has 2 rows and 16 columns.
2. How many data lines are there in a 16*2 alphanumeric LCD?
a) 16
b) 8
c) 1
d) 0
Answer: b
Explanation: There are eight data lines from pin no 7 to pin no 14 in an LCD.
3. Which pin of the LCD is used for adjusting its contrast?
a) pin no 1
b) pin no 2
c) pin no 3
d) pin no 4
Answer: c
Explanation: Pin no 3 is used for controlling the contrast of the LCD.
4. For writing commands on an LCD, RS bit is
a) set
b) reset
c) set & reset
d) none of the mentioned
Answer: b
Explanation: For writing commands on an LCD, RS pin is reset.
5. Which command of an LCD is used to shift the entire display to the right?
a) 0x1C
b) 0x18
c) 0x05
d) 0x07
Answer: a
Explanation: 0x1C is used to shift the entire display to the right.
6. Which command is used to select the 2 lines and 5*7 matrix of an LCD?
a) 0x01
b) 0x06
c) 0x0e
d) 0x38
Answer: d
Explanation: 0x38 is used to select the 2 lines and 5*7 matrix of an LCD.
7. Which of the following step/s is/are correct for sending data to an LCD?
a) set the R/W bit
b) set the E bit
c) set the RS bit
d) all of the mentioned
Answer: d
Explanation: To send data to an LCD, RS pin should be set so that LCD will come to know that it will receive data
which has to display on the screen. R/W pin should be reset as data has to be displayed (i.e. write to the LCD). High
to low pulse must be applied to the E pin when data is supplied to data pins of the LCD.
8. Which of the following step/s is/are correct to perform reading operation from an LCD?
a) low to high pulse at E pin
b) R/W pin is set high
c) low to high pulse at E pin & R/W pin is set high
d) none of the mentioned
Answer: c
Explanation: For reading operations, R/W pin should be made high and added to it, a low to high pulse is also gener
ated at the E pin.
9. Which instruction is used to select the first row first column of an LCD?
a) 0x08
b) 0x0c
c) 0x80
d) 0xc0
Answer: c
Explanation: 0x80 is used to select the first row first column of an LCD.
10. The RS pin is _________ for an LCD.
a) input
b) output
c) input & output
d) none of the mentioned
Answer: a
Explanation: The RS pin is an input pin for an LCD.
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1. Which of the following steps detects the key in a 4*4 keyboard matrix about the key that is being pressed?
a) masking of bits
b) ensuring that initially, all keys are open
c) checking that whether the key is actually pressed or not
d) all of the mentioned
Answer: d
Explanation: For detecting that whether the key is actually pressed or not, firstly this must be ensured that initially al
l the keys are closed. Then we need to mask the bits individually to detect that which key is pressed. Then we need t
o check that is the key actually pressed or not, by checking that whether the key pressed for a time more than 20 mic
ro seconds.
2. What is described by this command: CJNE A,#00001111b, ROW1
a) it masks the bit and then jumps to the label where ROW1 is written
b) it makes the value of the accumulator 0FH and then jumps at the address where ROW1 label is written
c) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if the val
ue becomes equal
d) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if the val
ue is not equal
Answer: d
Explanation: This particular command CJNE A,#00001111b, ROW1 compares the value of the accumulator with O
FH and jumps to ROW1 address if the value is not equal.
3. To detect that in which column, the key is placed?
a) we can mask the bits and then check it
b) we can rotate the bits and then check that particular bit which is set or reset(according to the particular condition)
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: We can mask or we can even rotate the bits to check that particularly in which column is the key place
d.
4. In reading the columns of a matrix, if no key is pressed we should get all in binary notation
a) 0
b) 1
c) F
d) 7
Answer: b
Explanation: If no key is pressed, then all the keys show 1 as they are all connected to power supply.
5. If we need to operate a key of a keyboard in an interrupt mode, then it will generate what kind of interrupt?
a) ES
b) EX0/EX1
c) T0/T1
d) RESET
Answer: b
Explanation: If a key is to operate in an interrupt mode then it will generate an external hardware interrupt.
6. To identify that which key is being pressed, we need to:
a) ground all the pins of the port at a time
b) ground pins of the port one at a time
c) connect all the pins of the port to the main supply at a time
d) none of the mentioned
Answer: b
Explanation: To detect that which key is being pressed, we need to ground the pins one by one.
7. Key press detection and Key identification are:
a) the same processes
b) two different works are done in Keyboard Interfacing
c) none of the mentioned
d) any of the mentioned
Answer: b
Explanation: They are two different works that are involved in Keyboard Interfacing. One is used for checking that
which key is being actually pressed and the other is used to check that is the key actually pressed or not.
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1. Why two pins for ground are available in ADC0804?
a) for controlling the ADCON0 and ADCON1 register of the controller
b) for controlling the analog and the digital pins of the controller
c) for both parts of the chip respectively
d) for isolate analog and digital signal
Answer: d
Explanation: Two grounds are available in ADC0804 to isolate analog signal from digital signal. This isolation prov
ides accuracy in digital output.
2. What is the function of the WR pin?
a) its active high input used to inform ADC0804 to the end of conversion
b) its active low input used to inform ADC0804 to the end of conversion
c) its active low input used to inform ADC0804 to the start of conversion
d) its active high input used to inform ADC0804 to the start of conversion
Answer: c
Explanation: WR is active low input used to inform the ADC0804 to start the conversion process.
3. State which of the following statements are false?
a) CLK IN pin used for External Clock Input or Internal Clock with external RC element
b) INTR pin tells about the end of the conversion
c) ADC0804 IC is an 8 bit parallel ADC in the family of the ADC0800 series
d) None of the mentioned
Answer: d
Explanation: CLK IN pin is used to tell about the conversion time, INTR pin tells about the end of the conversion an
d ADC0804 has a resolution of 8 bits only so all three statements are true.
4. While programming the ADC0808/0809 IC what steps are followed?
a) select the analog channel, start the conversion, monitor the conversion, display the digital results
b) select the analog channel, activate the ALE signal (L to H pulse), start the conversion, monitor the conversion, rea
d the digital results
c) select the analog channel, activate the ALE signal (H to L pulse), start the conversion, monitor the conversion, rea
d the digital results
d) select the channel, start the conversion, end the conversion
Answer: b
Explanation: While programming the ADC0808/0809 IC firstly we need to select the channel from the A, B, C pins.
Then we need to activate the ALE signal, this is needed to latch the address. Then we start the conversion from the
WR pin. After monitoring the INTR pin we get to know about the end of the conversion. Then we activate the OE e
nable to read out data out of the ADC chip.
5. In ADC0808/0809 IC which pin is used to select Step Size?
a) Vref
b) Vin
c) Vref/2 & Vin
d) None of the mentioned
Answer: a
Explanation: Step Size is calculated by formula Vref/(2n). As ADC0808/0809 8-bit ADC value of n=8. Therefore fo
rmula becomes Vref/(28) = Vref/256. If Vref = 5V then Step Size will be 5/256 i.e. 19.53mV.
6. What is the difference between ADC0804 and MAX1112?
a) ADC0804 has 8 bits and MAX1112 has 1 bit for data output
b) ADC0804 is used for adc and dac conversions whereas MAX1112 is used for serial data transmissions
c) ADC0804 has 32 bits and MAX1112 has 3 bit for data output
d) None of the mentioned
Answer: a
Explanation: ADC0804 is used for parallel ADC and MAX1112 is used for serial ADC.
7. Which of the following statements are true about DAC0808?
a) parallel digital data to analog data conversion
b) it has current as an output
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: DAC0804 is used for parallel data to analog data conversion.
8. 8 input DAC has ________
a) 8 discrete voltage levels
b) 64 discrete voltage levels
c) 124 discrete voltage levels
d) 256 discrete voltage levels
Answer: d
Explanation: For n input DAC has 2^n discrete voltage levels.
9. INTR, WR signal is an input/output signal pin?
a) both are output
b) both are input
c) one is input and the other is output
d) none of the mentioned
Answer: c
Explanation: INTR pin tells about the end of the conversion (output) and WR pin tells us to start the conversion (inp
ut).
10. What is the function of the SCLK pin in MAX1112?
a) It is used to bring data in
b) It is used to bring data out and send in the control byte, one at a time
c) It is used to get output clock
d) It is used to get serial output
Answer: b
Explanation: SCLK is used to bring data out and send in the control byte.
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1. A thermistor is a __________
a) sensor
b) adc
c) transducer
d) micro controller
Answer: c
Explanation: A thermistor is a device which is used to convert the temperature into electrical signals, so it acts as a tr
ansducer.
2. What is the difference between LM 34 and LM 35 sensors?
a) one is a sensor and the other is a transducer
b) one’s output voltage corresponds to the Fahrenheit temperature and the other corresponds to the Celsius temperat
ure
c) one is of low precision and the other is of higher precision
d) one requires external calibration and the other doesn’t require it
Answer: b
Explanation: LM 34’s output voltage corresponds to the Fahrenheit temperature and LM 35 corresponds to the Celsi
us temperature.
3. An electronic device which converts physical quantity or energy from one form to another is called ______
a) Sensor
b) Transistor
c) Transducer
d) Thyristor
Answer: c
Explanation: An electronic device that converts physical quantity or energy from one form to another is called Trans
ducer. Examples: Sensor, Speaker, Microphone, etc.
4. What is signal conditioning?
a) to analyse any signal
b) conversion or modification is referred to as conditioning
c) conversion from analog to digital is signal conditioning
d) conversion from digital to analog is signal conditioning
Answer: b
Explanation: Signal Conditioning is referred to as the conversion of a signal from one form to other, now this may b
e from analog to digital conditioning or digital to analog conditioning.
5. What steps have to be followed for interfacing a sensor to a microcontroller 8051?
a) make the appropriate connections with the controller, ADC conversion, analyse the results
b) interface sensor with ADC and ADC with 8051
c) interface sensor with the MAX232, send now to microcontroller, analyse the results
d) none of the mentioned
Answer: b
Explanation: For interfacing a sensor with an 8051 microcontroller, we need ADC in between because output of sen
sor is analog and microcontroller works on digital signals only. So whatever signal generated by the sensor is conver
ted into its digital equivalent using ADC and equivalent digital signal is given to the microcontroller for processing.
6. LM35 has how many pins?
a) 2
b) 1
c) 3
d) 4
Answer: c
Explanation: LM35 has 3 pins.
7. Why Vref is set of ADC0848 to 2.56 V if analog input is connected to the LM35?
a) to set the step size of the sampled input
b) to set the ground for the chip
c) to provide supply to the chip
d) all of the mentioned
Answer: a
Explanation: Vref is used to set the step size of the ADC conversion, if it is selected to 2.56 then the step size will be
selected to 10mV, so for every step increase of the analog voltage an increase of 10 mV will be there.
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1. The 8255 is a ______ chip.
a) Input/Output
b) Analog to Digital
c) Digital to analog
d) None of the mentioned
Answer: a
Explanation: The 8255 is Input/Output (I/O) chip. It has three separate accessible ports. The 8255 chip is used to exp
and the I/O ports of microcontrollers.
2. Which pins of a microcontroller are directly connected with 8255?
a) RD
b) WR
c) D0-D7
d) All of the mentioned
Answer: d
Explanation: RD, WR, D0-D7 all are directly connected to the 8051 for telling the chip about the control signals and
also for transferring the data.
3. Find the control word for PA = out, PB = in, PCL = out, PCH = out (Mode0)?
a) 0x02H
b) 0x82H
c) 0x83H
d) 0x03H
Answer: b
Explanation: The value that is being loaded in the control word is 10000010b for PB as an input port and all others a
s the output ports being operated in mode0. The hex equivalent of 10000010b → 0x82H.
4. Which pins are used to select the ports and the control register?
a) CS
b) A1
c) A0
d) All of the mentioned
Answer: d
Explanation: CS pin is an active low input pin for 8255 and it is used for selecting a chip. A0 and A1 pins are used f
or select ports and the control register.
5. What is the value of the control register when RESET button is set to zero?
a) 0x00H
b) 0xFFH
c) 0x11H
d) value remains the same
Answer: d
Explanation: RESET is active-high signal input into the 8255 used to clear the control register. When RESET is acti
vated (i.e. set to high), all ports are initialized as input mode. Hence the value of the control register remains the sam
e as it is even when the RESET button is set to zero.
6. Why MOVX instruction is being used to access the ports of the 8255?
a) because 8255 is connecting a microcontroller in memory mapped I/O configuration
b) because 8255 is used to access the external communication
c) because 8255 is used to access the data transfer
d) because 8255 is used to access the interfacing of LCD, motor etc
Answer: a
Explanation: As 8255 is connecting a microcontroller in memory mapped I/O configuration. This means that memor
y space used to access 8255 (i.e. 8255 is treated as external memory). MOVX instruction is used to access external
memory locations.
7. What is correct about the BSR mode from below?
a) In BSR mode, only the individual bits of PORT A can be programmed
b) In BSR mode, only the individual bits of PORT B can be programmed
c) In BSR mode, only the individual bits of PORT C can be programmed
d) none of the mentioned
Answer: c
Explanation: BSR (Bit Set/Rest) mode is used to program individual bits of PORT C only.
8. How many pins of the 8255 can be used as the I/O ports?
a) 8
b) 16
c) 24
d) 32
Answer: c
Explanation: There are 3 ports available in the 8255 so 24 pins are available for the I/O ports pins.
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1. DS12887 is a ____________
a) Timer IC
b) Serial communication IC
c) RTC IC
d) Motor
Answer: c
Explanation: DS12887 is a real time clock that is widely used to provide accurate time and date for many application
s.
2. DS12887 has _____ amount of RAM.
a) 14 bytes
b) 114 bytes
c) 128 bytes
d) 64 bytes
Answer: c
Explanation: DS12887 has 128 bytes of non-volatile RAM.
3. DS12887 has _____ amount of RAM for general purpose applications.
a) 9 bytes
b) 114 bytes
c) 128 bytes
d) 14 bytes
Answer: b
Explanation: DS12887 has 128 bytes of non-volatile RAM. Out of 128 bytes, 14 bytes of RAM for clock/calendar a
nd control registers, and another 114 bytes of RAM for general purpose data storage.
4. In DS12887, which bits of the Register A are used to turn on the oscillator?
a) D4
b) D5
c) D6
d) All of the mentioned
Answer: d
Explanation: In DS12887, D4-D6 bits of register A are used to turn on the oscillator. A specific value of 010 of D4-
D6 is desirable for turning on the oscillator.
5. In DS12887, which out of the following is correct about the SQW pin?
a) it is an output pin
b) it can provide up to 15 different square waves
c) the frequency of the square wave is set by the register A
d) all of the mentioned are correct
Answer: d
Explanation: In DS12887, SQW pin stands for SQuare Wave. It is an output pin that can provide us with 15 differen
t square waves. The frequency of the square wave is selected by programming register A.
6. In DS12887, what is correct about the UIP bit of the register A?
a) it is a read only bit
b) it is used to know about the result
c) it is used to select the DS12887 datasheet
d) all of the mentioned
Answer: a
Explanation: In DS12887, UIP bit of register A stands for Update In Progress. The update-in-progress (UIP) bit is a
status flag i.e. read-only bit.
7. In DS12887, what is the range of RAM addresses which are used to store the values of time, calendar and alarm d
ata?
a) 00-7FH
b) 00-09H
c) 0EH-7FH
d) 0A-0DH
Answer: b
Explanation: In DS12887, the first ten locations i.e. 00-09H are used to store the values of time, calendar and alarm
data.
8. Is DS12887 has non-volatile RAM?
a) Yes
b) No
c) Can’t be determined
d) None of the mentioned
Answer: a
Explanation: Yes, DS12887 has non-volatile RAM.
9. Name the read only registers are present in the DS12887?
a) register A, register B
b) register B, register C
c) register C, register D
d) register D, register A
Answer: c
Explanation: Register C and D are the read only registers in the DS12887 found at memory locations 0C-0DH.
10. In DS12887, when the external source is turned-off, how does DS12887 get power to retain its data?
a) Internal Lithium Battery
b) Internal Lead Battery
c) Additional external Alkaline Battery
d) Additional external Lithium Battery
Answer: a
Explanation: When Vcc falls below 3V or external voltage source is switched-off, internal lithium battery provides p
ower to DS12887. And this will prevent loss of data.
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1. What is the principle on which electromagnetic relays operate?
a) electromagnetic induction
b) motor control
c) switching
d) none of the mentioned
Answer: a
Explanation: Electromagnetic relays work on the principle of electromagnetic induction. It is used as a switch in ind
ustrial controls, automobile and appliances. It allows the isolation of the sections of a system with two different volt
age sources.
2. What are DPDT relays?
a) Single pole, single throw
b) Single pole, double throw
c) Double pole, double throw
d) None of the mentioned
Answer: c
Explanation: In DPDT relay, there are two poles and two throws (i.e.contacts). For each pole there are two contacts i
.e. normally open (NO) and normally closed (NC). The contacts can be NO or NC. Generally, contact is NC when th
e coil is not energized. When the coil is energized both poles become NC.
3. Why do we need a ULN2803 in driving a relay?
a) for switching a motor
b) for increasing the current
c) for increasing the power
d) for switching the voltage
Answer: b
Explanation: We need a ULN2803 for driving a relay because the relay coil requires 10mA or more current to be en
ergized. If microcontroller pins are not able to provide sufficient current to drive relays then we need ULN2803 for
driving relays.
4. Why are solid-state relays advantageous over electromechanical relays?
a) they need zero voltage circuit
b) they need less current to be energised
c) they need less voltage to be energised
d) none of the mentioned
Answer: b
Explanation: Solid-state relays are advantageous over electromechanical relays because their switching response tim
e is much faster than electromechanical relays as solid-state relays are made-up of semiconductor materials. Also, so
lid-state relays required low input current for operation and small packaging make them ideal for microcontrollers.
5. What are optoisolators?
a) it is a driver
b) it is a thing isolated from the entire world
c) it is a device that can be used as an electromagnetic relay without a driver
d) none of the mentioned
Answer: c
Explanation: Optoisolators are devices that can be used as an electromagnetic relay without a driver. It usually consi
sts of a led (transmitter) and a photoresistive receiver.
6. How can we control the speed of a stepper motor?
a) by controlling its switching rate
b) by controlling its torque
c) by controlling its wave drive 4 step sequence
d) cant be controlled
Answer: a
Explanation: Speed of a stepper motor can be controlled by changing its switching speed or by changing the length o
f the time delay loop.
7. Which of the following can be a unit for torque?
a) kg/m2
b) ounce-inch
c) kg-m3
d) g/m
Answer: b
Explanation: Torque is equal to the force applied at a particular distance. So its unit can be ounce-inch.
8. The RPM rating given for the DC motor is for?
a) no-loaded
b) loaded
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: RPM rating given for a DC motor is for a no-loaded condition.
9. How can we change the speed of a DC motor using PWM?
a) By changing amplitude of PWM
b) By keeping fixed duty cycle
c) By changing duty cycle of PWM
d) By increasing power of PWM
Answer: c
Explanation: We can change the speed of a DC motor using PWM by changing the duty cycle of PWM. Changing d
uty cycle means changing ON and OFF timing of PWM. Even if amplitude of PWM is fixed by increasing the ON ti
me of PWM increases the speed of the DC motor.
10. How can the direction of the DC motor be changed?
a) by changing the torque
b) by changing the switching speed
c) by changing the polarity of voltages connected to the leads
d) by changing the RPM rating
Answer: c
Explanation: The direction of the DC motor can be changed by changing the polarity of the voltages connected to its
leads.
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1. Is the following instruction correct LDI R3,50?
a) Yes
b) No
c) Cant be said
d) None of the mentioned
Answer: b
Explanation: If LDI Rd,k is written then the range of Rd varies from R16-R31, as R3 is less than R16 so this instruct
ion will generate an error.
2. Registers R0-R31 are used for what type of works?
a) they are used for arithmetic and logic instructions
b) they are used for data copy
c) they are used for calculations
d) none of the mentioned
Answer: a
Explanation: GPRs are used for implementing arithmetic and logic instructions in the controller. They do the same
work as the accumulator does in the other microcontrollers and microprocessors.
3. The largest value that can be loaded in an 8 bit register is?
a) 11111111H
b) FH
c) FFH
d) 00H
Answer: c
Explanation: The largest value that can be loaded in an 8 bit register is 11111111b or FFH.
4. The total space for the data memory available in the AVR based microcontroller is?
a) FFH
b) FFFH
c) FFFFH
d) FFFFFH
Answer: c
Explanation: The maximum value that can be loaded in the code memory of an AVR based microcontroller is FFFF
H.
5. Which of the following instructions affect the flags of the status register?
a) AND
b) INC
c) OR
d) All of the mentioned
Answer: d
Explanation: AND, INC, OR could affect status register flags. All arithmetic and logical instructions affect status re
gister flags except SER Rd instruction. SER Rd is used to SEt Register i.e. after the execution of this instruction Rd l
oaded with FFH value and no flag is affected.
6. What is the difference between the two given instructions?
a) One copies the hexadecimal value to R16 and the other copies the decimal value to the R16 register
b) One is for command, other is for data
c) One is for assignment, other is for operations
d) Both the commands are the same
Answer: d
Explanation: Both the above commands are the same. They both are used for assigning the hexadecimal values to th
e registers.
7. Which out of the following is not a directive?
a) .EQU
b) .DEVICE
c) .ORG
d) .LDI
Answer: d
Explanation: .EQU, .DEVICE, .ORG all are the directives to the assembler whereas LDI is a command.
8. Is an assembly language a high level language?
a) Yes
b) No
c) Can’t be said
d) None of the mentioned
Answer: b
Explanation: Assembly language is not high level language rather it is low level language because it deals directly w
ith the internal structure of CPU. To program in assembly, the internal structure of the CPU must be known. Wherea
s in high level programming languages programmers don’t bother about the internal structure of the CPU because th
is is done by the compiler.
9. A 14-bit program counter can access __________ bytes of memory locations.
a) 4K
b) 8K
c) 16K
d) 64K
Answer: c
Explanation: A 14-bit program counter can access 214 bytes of memory locations i.e. 16k bytes.
214 = 24 x 210
a) 00H
b) 000H
c) 0000H
d) 00000H
Answer: d
Explanation: When an AVR wakes up, then the PC starts at the memory location 00000H.
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1. Which of the following is correct about BRNE instruction in avr microcontrollers?
a) it is used to compare two registers
b) it is used to compare two values
c) it is used to check the zero flag
d) it is used to jump to the given mentioned label when the zero flag accounts to 0
Answer: d
Explanation: BRNE label instruction is used to jump to that particular address denoted by label if condition (Z=0) is
true or satisfied. If the condition is not satisfied then it will execute the next immediate instruction.
2. How many times is this loop going to get executed?
a) 10
b) 70
c) 700
d) none of the mentioned
Answer: b
Explanation: As the R21 register is loaded with 70, so to make it zero it needs to be decremented 70 times then only
the OUT instruction will be executed so this loop repeats 70 times.
3. Which of the below mentioned are not the conditional jumps?
a) BRLO
b) BRMI
c) BRVC
d) None of the mentioned
Answer: d
Explanation: BRLO is used to branch if C=1, BRMI is used when N=1 and BRVC are used when V=0, so all are the
conditional jumps.
4. What is the relation between the target and the relative address?
a) target address= PC address + relative address
b) target address= relation address*2
c) relative address= PC address + target address
d) none of the mentioned
Answer: a
Explanation: Target address can be calculated by calculating the sum of the address of the program counter and the r
elative address.
5. In the JMP instruction, how many bits are there for determining the target address?
a) 16
b) 32
c) 22
d) 10
Answer: c
Explanation: In the JMP instruction of 4 bytes space, 22 bits are there for determining the target address and the othe
r 10 are for the op code verification.
6. Which of the following statements are correct?
a) relative address of RJMP instruction varies from 000-fffH
b) target address of JMP instruction varies from 000000-3fffffH
c) IJMP instruction jumps to that address that points to by the Z register
d) all of the mentioned
Answer: d
Explanation: The relative address of the RJMP instruction varies from 000-fffH. The target address of the JMP instr
uction varies from 000000-3fffffH. IJMP instruction is used to jump at that particular address pointed to by the Z reg
ister. So all are the correct statements.
7. Which of the following is used to represent the last RAM address?
a) MEM
b) LASTRAM
c) RAMEND
d) None of the mentioned
Answer: c
Explanation: RAMEND is a micro used to represent the last RAM address. In AVR, Stack Pointer is initialized on t
op of the stack i.e. last address of RAM.
8. Which of the following statements are correct about the RCALL instruction?
a) it is a 2 byte instruction
b) it is a 4 byte instruction
c) it is a 16 byte instruction
d) none of the mentioned
Answer: a
Explanation: RCALL instruction is used to go to the target address in the memory from -2048 to 2047.
9. On power on SP points to the address?
a) ffffH
b) fffH
c) 00h
d) all of the mentioned
Answer: c
Explanation: On power on SP register points to the 00H address.
10. Which of the following statements is true?
a) CALL instruction is used to transfer control anywhere in the 4M memory space
b) PUSH instruction is used to take out the value from the stack into some register
c) POP instruction is used to jump to any location
d) RCALL is a 4 byte instruction
Answer: a
Explanation: CALL instruction is used to transfer control anywhere in the 4M memory space available in the AVR.
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1. In AVR, which registers are there for the I/O programming of ports?
a) PORT
b) PIN
c) DDR
d) All of the mentioned
Answer: d
Explanation: For I/O programming of the ports in AVR microcontrollers, there are basically three main registers. Th
ey are PORT, PIN, DDR, so all of the mentioned is the right option.
2. The data will not go from the port registers to the pin unless:
a) DDR register of that port is set to 0
b) PORT register of that port is set to 1
c) DDR register of that port is set to 1
d) PORT register of that port is set to 0
Answer: c
Explanation: The data will not go from the port registers to the pin unless the DDR register of that port is set to 1 be
cause by doing this we make that port an output port after which data can be taken from the PORT registers to the pi
n.
3. On reset DDR registers of all ports are set to:
a) 0
b) 1
c) None of the mentioned
d) 0 & 1
Answer: a
Explanation: On reset, the DDR registers of all the ports are set to 0 which means that the by default all ports are set
as input ports.
4. Which of the following statements are correct?
a) PIN register of a port is used to bring data into CPU from pins
b) PORT register is used to send data out to pins
c) DDR register is used to control the direction of a port
d) All of the mentioned
Answer: d
Explanation: There are three registers that are related to a port. They are PIN, PORT, DDR. PIN register is used to b
ring data into CPU from pins, PORT register is used to send data to pins and DDR register is used to control the dire
ction of the data transfer. So all are the right options.
5. In the AVR family, all I/O ports have 8 pins?
a) true
b) false
c) none of the mentioned
d) can’t be determined
Answer: b
Explanation: In the AVR family, all I/O ports don’t have 8 pins. Number of I/O pins depends on the total number of
pins of the controller. Eg. ATtinyxx is an 8 pin controller and it has 6 I/O pins.
6. Which of the following is not a single bit instruction in AVR?
a) SBI
b) PORT
c) CBI
d) All of the mentioned
Answer: b
Explanation: PORT is not an instruction. It is the name of a register in AVR.
7. Which of the following is correct about the SBIS instruction?
a) it is used to monitor status of bit in I/O register
b) it is a byte oriented instruction
c) It is a 4 byte instruction
d) all of the mentioned
Answer: a
Explanation: SBIS (Skip if Bit in I/O register Set) is used to check status of bit in I/O register. If the bit mentioned in
the instruction is SET or HIGH then the controller will skip the immediate next instruction.
8. Instruction CBI PORTB,1 means
a) clearing the PORTB register
b) clearing the first bit of the PORTB register
c) setting the PORTB register
d) setting the first bit of the PORTB register
Answer: b
Explanation: CBI PORTB, 1 means to clear the first bit of the PORTB register. It is a bit oriented instruction.
9. Which of the following instruction can be used to toggle a bit of the PORT?
a) SBI
b) CBI
c) SBI & CBI
d) None of the mentioned
Answer: c
Explanation: If SBI and CBI are used together, then they can be used to toggle a bit of a port successfully.
10. What is the main function of the SBIC instruction?
a) it is used to clear a particular bit of a port
b) it is used to jump unconditionally
c) it is used to skip the instruction if a particular bit of a port is zero
d) none of the mentioned
Answer: c
Explanation: SBIC (Skip if Bit in I/O register Clear) is used to check status of bit in I/O register. If the bit mentioned
in the instruction is CLEAR or LOW then the controller will skip the immediate next instruction.
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1. In AVR microcontrollers, ADD instruction affects the status of which of the following bits of a status register?
a) Z
b) C
c) N
d) All of the mentioned
Answer: d
Explanation: ADD instruction affects the status of Z, C, N, V, H and S bits of a status register.
2. ADC instruction is used for?
a) addition of two 16 bit numbers
b) analog to digital conversion
c) automatic digital control
d) none of the mentioned
Answer: a
Explanation: ADC instruction can be used for addition of two 16 bit numbers as here two 8 bit numbers are added si
multaneously along with the carry coming from the previous 8 bits. So it can be used for the addition of two 16 bit n
umbers.
3. AVR supports which of the following mentioned subtraction instructions?
a) SUB
b) SBC
c) SUBI
d) All of the mentioned
Answer: d
Explanation: AVR supports five types of subtraction instructions. They are SUB, SBC, SUBI, SBCI, SBIW.
4. What steps are involved when we subtract two numbers present at two different locations?
a) take the two’s complement of the subtrahend
b) add it to the minuend
c) invert the carry
d) all of the mentioned
Answer: d
Explanation: When we need to subtract two numbers present at two different locations then firstly we need to take th
e 2’s complement of the subtrahend, then we add it with the minuend and then when we invert the carry then the co
mplete procedure of the subtraction is completed.
5. In executing subtraction based instructions, state the role of the C flag?
a) if C=1, the result is negative
b) if C=1, the result is positive
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: If the C flag comes out to be 1, then the result is assumed to be negative and vice versa.
6. Which of the following is correct about the MUL instruction?
a) it is a byte-by-byte multiplication instruction
b) the product is stored in two registers R1 and R0
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: MUL instruction is a byte-by-byte multiplication instruction whose result is stored in two registers R1
and R0.
7. In AVR, when is the V flag set?
a) there is a carry from D7 bit
b) there is a carry from D6 to D7 bit
c) when carry is generated only from D6 to D7 or carry is generated only from D7
d) none of the mentioned
Answer: c
Explanation: In AVR, V i.e. Overflow flag is set when carry is generated only from D6 to D7 or carry is generated o
nly from D7. Overflow flag is used to detect errors in signed arithmetic operations.
8. To set the bits of a register R1 to 1, we must OR the contents of the register with?
a) 00H
b) 11H
c) FFH
d) 0FH
Answer: c
Explanation: To make the contents of the register R1 to 1 we must OR the contents of that register with FFH becaus
e according to Or algorithm 0+1=1 and 1+0=1.
9. CP instruction alters the value of the register?
a) true
b) false
c) none of the mentioned
d) can’t be said
Answer: b
Explanation: CP command is used to compare the contents of the two registers. It doesn’t actually alter the value of t
he register.
10. What is right about the ROR instruction?
a) it rotates the contents of the register left to right
b) it rotates the contents of the register from right to left
c) it rotates the contents of the register from left to right through carry
d) it rotates the contents of the register from right to left through carry
Answer: c
Explanation: ROR instruction is used to rotate the contents of the register from left to right through carry.
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1. In AVR, which of the following registers are not used for programming timers?
a) TCNT
b) TCON
c) TIFR
d) None of the mentioned
Answer: b
Explanation: In the timer programming of an AVR microcontroller, mainly used registers are TCNTn that stores the
values of the count. TCCRn that is used to assign the mode of operation of a timer and TIFR that stores the status of
various flags of the timers. Two more registers are used they are OCRn and OCFn. They are used for comparison wi
th the count register.
2. What is the use of the prescalar in the operation of the timer?
a) for fast calculations
b) for increasing the time delay given by the timer by decreasing its frequency of operation
c) for removing the concept the reloading of count
d) for easy counter operations
Answer: b
Explanation: Prescalars are used in the operation of the timers because they generally increase the time delay generat
ion by decreasing the frequency of its operation.
3. What modes are generally used in the operation of the timer0?
a) Normal mode
b) CTC mode
c) PWM mode
d) All of the mentioned
Answer: d
Explanation: Modes of a timer are decided by the WGM00 and WGM01 bit of the TCCR0 register and for timer0 th
ese modes are normal mode, CTC mode, pwm mode and the fast pwm mode.
4. Timer 0 can act as a counter ____________
a) if the CS02-CS00 are 110 or 111
b) if the FOC0 bit is set to 110
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: Timer0 can act as a counter if the CS02-CS00 bits are from 110-111.
5. Which of the timer can operate in the 16 bit condition?
a) timer0
b) timer1
c) timer2
d) all of the mentioned
Answer: b
Explanation: Timer0 and Timer2 can operate in the 8 bit condition while only Timer 1 operates in the 16 bit conditio
n.
6. Which of the following will generate the maximum time delay?
a) f/2
b) f/4
c) f/16
d) f/32
Answer: d
Explanation: f/32 has the lowest frequency as it is divided by the maximum value of the constant, so as time and fre
quency are inversely related to each other so this will generate the maximum amount of machine cycle which will as
a result generate the greatest delay.
7. What is the difference in the operation of a normal and a CTC mode of a timer?
a) in CTC mode PWM is used
b) here serial timer is monitored
c) in CTC mode, timer counts up until contents of TCNT register becomes equal to the contents of OCR
d) none of the mentioned
Answer: c
Explanation: In CTC mode, timer counts up until the contents of TCNT register becomes equal to the contents of O
CR; then the timer will be cleared and the OCF0 flag will be set when the next clock occurs. In Normal mode, timer
counts until max i.e. 0xFFH. When it rolls over from 0xFFH to 0x00H, it sets TOV(Timer Overflow).
8. We can count the pulses on the positive or the negative edge triggered pulse of the clock?
a) true
b) false
c) can’t be determined
d) depends on the circumstances
Answer: a
Explanation: A counter can count pulses on the positive or the negative edge of the clock.
9. Which pin is used for the input clock of the counter0?
a) PORTB.0
b) PORTB.1
c) PORTB.2
d) PORTB.3
Answer: a
Explanation: In ATmega32/16, T0 is the alternative function of PORTB.0. T0 is Timer/Counter 0 External Clock In
put.
10. Which resource provides the clock pulse to AVR timers if CS02-00=6?
a) internal clock of the AVR
b) external clock of the AVR
c) none of the mentioned
d) all of the mentioned
Answer: b
Explanation: The External clock is used for providing the pulse to the AVR timers if CS02-00=6.
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1. On reset, what are the contents of the SREG register?
a) 00h
b) ffh
c) 1fh
d) 11h
Answer: a
Explanation: On reset, all the interrupts are masked and so the contents of the SREG register is also set to zero as it s
hows the status of the flags.
2. TIMSK register is used for?
a) knowing the status of the timer count
b) used for masking the interrupts flags of the Timer0, Timer1 and Timer2
c) it is used for enabling all the timer interrupts
d) it is used for resetting the value of the interrupts
Answer: b
Explanation: TIMSK is used for masking the interrupt flags of the timers. They mask the bits of the timer flags if the
D7 bit of the SREG register is set to 1 or when firstly all interrupts are enabled.
3. Why RETI instruction be the last instruction of ISR?
a) because it returns with carry
b) because it returns to the main program with all the flags of the SREG raised
c) because it returns to the main program where interrupt is generated and set the global interrupt enable bit in SRE
G
d) none of the mentioned
Answer: c
Explanation: When an interrupt occurs, the global interrupt enable bit is cleared. If global interrupt enable is cleared
it means interrupts are disabled. RETI instruction must last instruction of ISR because it returns to the main program
where interrupt is generated and sets the global interrupt enable bit in SREG.
4. In AVR what is the ISR address for an external hardware interrupt?
a) 0002h
b) 0004h
c) 0006h
d) all of the mentioned
Answer: d
Explanation: The ISR addresses for the external hardware interrupts are 0002h, 0004h, 0006h.
5. What is the address in the interrupt service routine assigned for the timer0 overflow flag?
a) 0012h
b) 000Ah
c) 0016h
d) all of the mentioned
Answer: c
Explanation: 0016h is the address in the interrupt service routine assigned for the timer0 overflow flag.
6. Is the same address is assigned for the timer0 and timer1 overflow flag in the interrupt vector table of the interrupt
s?
a) true
b) false
c) can’t be determined
d) depends on the situation
Answer: b
Explanation: Different addresses are assigned for Timer0 and Timer1 overflow flags in the interrupt vector table. Th
ey are 0016h and 0012h for timer0 and timer1 respectively.
7. External hardware interrupts are assigned to which pins of the atmega32?
a) PORTD.2
b) PORTD.3
c) PORTB.2
d) All of the mentioned
Answer: d
Explanation: There are three external hardware interrupts in the atmega32 microcontrollers. They are assigned to bit
s PORTD.2, PORTD.3 and PORTB.2.
8. Which register is responsible for handling all the external hardware interrupts?
a) TIMSK
b) GICR
c) MCUCR
d) IVCE
Answer: b
Explanation: GICR register is responsible for all the external hardware interrupts in the AVR.
9. By default, INT0-INT2 interrupts are?
a) edge triggered
b) level triggered
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: By default, INT0-INT2 are the level triggered pulses. The low level of the pulse generates the interrupt
.
10. What will happen in that condition, if an interrupt occurs while the microcontroller is serving any other interrupt
?
a) both the interrupts will be handled simultaneously
b) the interrupt which is being done first will be served first
c) the interrupt that is more priority in the interrupt vector table will be served first
d) the interrupt having low priority in the interrupt vector table will be served first
Answer: c
Explanation: If two or more interrupts occur simultaneously then the interrupt that is having more priority in the inte
rrupt vector table will be served first.
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1. What actually are the DB9, DB25 ports available in our computers?
a) they are connectors used to transfer data either serially or parallelly
b) they are the RS232 connectors used to connect two incompatible devices
c) they are the TTL logic connector pins used for communication
d) they are just data transfer pins used to transfer the data
Answer: b
Explanation: DB9 and the DB25 ports are the ports that are based on the RS232 logic that is basically used for com
municating two incompatible devices.
2. What does RI handshaking signal refer to according to the RS232 logic?
a) if this logic is high then a receive interrupt is generated
b) this pin is high during transmission
c) this pin is high during a reception in order to tell that the device is busy at this particular time
d) none of the mentioned
Answer: c
Explanation: RI pin of the RS232 logic tells us about the ring indicator i.e it sends a busy signal if the device is curre
ntly receiving any data.
3. What is the major difference between a MAX232 and a MAX233 device?
a) one has one serial port other has two
b) one has inbuilt UART other doesn’t have that
c) one needs some additional circuitry to operate while the other doesn’t have that
d) one is used just for transmission while the other is used for both transmission as well as reception
Answer: c
Explanation: MAX232 needs some extra capacitors at pins like 1,2 and 3,4 while on the other hand MAX233 has th
at inbuilt capacitors built inside it only.
4. Which of the following is correct about the baud rate during serial transmission?
a) it tells us about the speed at which the transmission is going to place
b) it tells us about the number of bits transferred during a second
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: Baud Rate tells us about the speed in which the transmission is being done and this speed is measured i
n terms of bits per second.
5. With fosc=8 MHz, what will the count that has to filled in the UBRR register to account for the 9600 baud rate?
a) 67H
b) CEH
c) 33H
d) 34H
Answer: c
Explanation: The count that had to be filled in the UBRR register is calculated as (fosc/16(desired baud rate))-1.
6. The USART in AVR based microcontrollers operate at which of the following modes?
a) double speed asynchronous mode
b) master synchronous
c) slave synchronous
d) all of the mentioned
Answer: d
Explanation: The USART in AVR consists of the following modes. They are the normal asynchronous mode, doubl
e speed asynchronous mode, slave synchronous and the master synchronous mode.
7. Which bit of the UCSRA is used for doubling the baud rate of the transmission?
a) DOR
b) PE
c) U2X
d) MPCM
Answer: c
Explanation: U2X bit of the UCSRA is used for doubling the baud rate of the transmission.
8. What is the use of the PE and the FE bits of the UCSRA register?
a) they are used for keeping a check at the speed of transmission and reception
b) they are used for keeping a check at the data bits to be transferred
c) they are used to keep the transmission error free
d) they are used as extra redundant bits with no use
Answer: c
Explanation: PE and the FE bits of the UCSRA register are used for error checking in the transmission.
9. Which of the following bits are used for setting the data frame size?
a) UCSZ0
b) U2X
c) DOR
d) MPCM
Answer: a
Explanation: UCSZ0 and UCSZ1 bits of the UCSRB register and the UCSZ2 bit of the UCSRC register are used for
setting the data frame size in AVR based microcontrollers.
10. Which of the following parameters should the transmitter and the receiver agree upon before starting a serial tran
smission?
a) baud rate
b) frame size
c) stop bit
d) all of the mentioned
Answer: d
Explanation: Before starting the serial transmission, the following parameters should be taken care of. They are the b
aud rate, frame size, stop bit and the parity bit.
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1. In AVR, the LCD operates in two main modes, it can be in 8 bit or 4 bit data.
a) true
b) false
c) depends on the situation
d) can’t be said
Answer: a
Explanation: In AVR, the LCD operates in two main modes, they are in the 8 bit data transfer mode and the 4 bit dat
a transfer mode.
2. What can be the sequence of commands that may be used for initializing an LCD?
a) 0x06, 0x0e, 0x01
b) 0x0e, 0x01, 0x80
c) 0x38, 0x0e, 0x01
d) all of the mentioned
Answer: c
Explanation: For initializing an LCD, we can use commands like 0x38 for selecting the 5*7 matrix, 0x0e for display
on and the cursor blinking and 0x01 for clearing the screen.
3. When the LCD operates in the 4 bit mode, then what more commands are added to it?
a) 33
b) 32
c) 28
d) all of the mentioned
Answer: d
Explanation: When an LCD operates in the 4 bit mode than 33, 32, 28 in hex are sent to it. They represent 3, 3, 3, 2
nibbles which tell the LCD to do into the 4 bit mode for saving the i/o pins of the port.
4. What is the main function of the LPM instruction used in LCD?
a) for initializing the LCD in the read mode
b) for initializing the LCD in the write mode
c) for sending a long string of characters to the LCD
d) all of the mentioned
Answer: c
Explanation: LPM instruction is used for sending a long string of characters to the LCD.
5. The RS pin acts as an
a) input pin
b) output pin
c) any of the mentioned depending on the conditions
d) none of the mentioned
Answer: a
Explanation: The RS pin of the LCD is used for selecting a particular register used for sending a command or the dat
a to the LCD.
6. To latch in information at the data pins of the LCD, we send
a) H-L pulse at the E pin
b) L-H pulse at the E pin
c) A constant H pulse at the E pin
d) A constant L pulse at the E pin
Answer: a
Explanation: For latching in information at the data pins of the LCD, we send a H-L pulse at the LCD.
7. What is the function of the 0x06 command?
a) to clear the LCD
b) to blink the cursor
c) to shift the cursor to the right
d) for selecting the matrix
Answer: c
Explanation: 0x06 command is used for shifting the cursor to the right after every data send to it.
8. What is the address of the second column and the second row of the 2*20 LCD?
a) 0x80
b) 0x81
c) 0xc0
d) 0xc1
Answer: d
Explanation: 0xc0 acts as the address for selecting the second row and the first column of the LCD, so according to i
t if we need to select the second row and the second column of the LCD, then the address should be 0xc1.
9. Which of the following commands takes more than 100 microseconds to run?
a) shift cursor left
b) shift cursor right
c) set address location of the DDRAM
d) clear screen
Answer: d
Explanation: Clear screen is a command that takes more than 100 microseconds to run.
10. For selecting the data pins in an LCD, RS pin should be
a) 1
b) 0
c) F
d) 10
Answer: a
Explanation: For selecting the data pins of the LCD, the RS pin of the LCD should be set to 1.
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1. In reading the columns of a keyboard matrix, when no key is pressed then all the pins show?
a) 0
b) 1
c) F
d) 7
Answer: b
Explanation: When no key is pressed, in a keyboard then all the pins will read 1 as they all are connected to the main
power supply.
2. To see if any key is pressed, all rows are grounded.
a) true
b) false
c) can’t be said
d) depends on the conditions
Answer: a
Explanation: To see that whether any key is pressed or not then all the rows are grounded so that columns can be rea
d to deliver the better results.
3. Identify the row and the column for the following case when for the row D3-D0= 1110 and for the column D3-D0
= 1101
a) first row and second column
b) first row and third column
c) second row and first column
d) second row and second column
Answer: a
Explanation: To identify the key that is pressed from this particular combination, we obtain that the key belongs to t
he first row and the second column as the D0 bit of the row port and the D1 bit of the column port are zero.
4. What are the actual steps that are followed in identifying any key that is being pressed?
a) wait for the debounce time
b) identify the key that is pressed
c) initially no key should be pressed
d) all of the mentioned
Answer: d
Explanation: In order to identify that which key is actually pressed form a particular format of a 3*3 matrix keyboar
d, we firstly ensure all initially all the keys are open, then we press a key and check that whether the key is actually
pressed or not by waiting for a time span of 20mseconds, after this we identify the key that is pressed by masking th
e bits of the port. In this particular format, we can identify the key that is actually pressed.
5. To identify that the key is present in which row and the column
a) we ground the bits of the row one by one
b) we ground the bits of the column one by one
c) we connect the bits of the row to the logic level 1 one by one
d) we can connect the columns to the logic level 1 one by one
Answer: a
Explanation: To determine that the pressed key is in which row and column, we ground the rows one by one to deter
mine the column by masking the bits separately.
6. The key detection and the key identification are two different procedures?
a) true
b) false
c) depends on the circumstances
d) difficult to tell
Answer: a
Explanation: The key detection and the key identification are the two different procedures, one is used to detect that
whether any key is pressed or not and the other technique is used to find that the pressed key is located in which row
and column.
7. What is described by the following command?
a) load KCODE0 with 0
b) rotate the contents of the KCODE0 register to the right
c) rotate the contents of the KCODE0 register to the left
d) none of the mentioned
Answer: b
Explanation: KCODE0<<1 means to rotate the contents of the KCODE0 register to the left after every loop.
8. If the pins of the keyboard are used as an interrupt, then these pins will cause an interrupt of what type?
a) External hardware interrupt
b) Timer interrupt
c) TI/RI interrupt
d) None of the mentioned
Answer: a
Explanation: The pins of the keyboard act as an external hardware interrupt as some external pulse is helping in gene
rating this interrupt.
9. What will happen if the two keys of the keyboard are pressed at a time?
a) both the keys will be displayed on the screen
b) the key which is being actually pressed(for more then 20microseconds) will be displayed
c) the key that is pressed first will be displayed
d) none of the mentioned
Answer: b
Explanation: If two or more keys are pressed at a time, then the key that will be pressed for more then 20 microseco
nds will be displayed on the screen.
10. Why initially all keys are considered open before detecting the key pressed?
a) to make the task easy
b) to remove the errors caused by other pressing keys during detection
c) to remove the flow problems
d) none of the mentioned
Answer: b
Explanation: Initially all keys are considered open in order to ensure the accuracy while identification of the pressed
key.
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1. Which of the following is correct about the word resolution in ADC DAC converters in AVR’s?
a) it is the smallest change that can be described by an ADC
b) it is equal to Vref/2n (where n represents the number of bits)
c) it is 0.076mV or 76uV for n=16 and Vref=5V
d) all of the mentioned
Answer: d
Explanation: Resolution is defined as the smallest change in the step size that is described by an ADC, it is equal to
Vref/2n.
2. In an ADC, we can calculate the output voltage from the formula
a) Step size / Vin
b) Step size * Vin
c) Vin / step size
d) Vref / step size
Answer: c
Explanation: The output voltage can be calculated by using the formula Vin / step size.
3. ADC0848 is a ____________ bit converter?
a) 16
b) 4
c) 8
d) 48
Answer: c
Explanation: ADC0848 is a 8 bit converter.
4. Which of the following factors can affect the step size calculation?
a) number of bits
b) input current
c) output current
d) all of the mentioned
Answer: a
Explanation: There are mainly two factors that can affect the step size calculation of an ADC converter, they are the
number of bits and the Vref voltage.
5. MAX1112 is a _________ type of ADC converter?
a) parallel
b) 12 bit
c) serial
d) all of the mentioned
Answer: c
Explanation: MAX1112 is a serial ADC converter, as it has only one pin for the data output.
6. Why do we connect a capacitor between the Vref and the Gnd pin?
a) to remove the leakage
b) to ensure more current at that place
c) to make more Vref
d) to make Vref stable and also to increase the precision of the ADC
Answer: d
Explanation: A capacitor is connected between the Vref and the Gnd pin in order to stabilize the Vref value and also
to increase the precision of the ADc converter.
7. Which of the following are the registers that are used for controlling the ADC conversion in the AVR?
a) ADCSRA
b) ADMUX
c) SPIOR
d) All of the mentioned
Answer: d
Explanation: For programming the ADC conversion in an AVR, we require the following registers. They are ADCS
RA, ADMUX, SPIOR. There are two more registers used for handling the output data, they are ADCH and ADCL r
egisters.
8. What is the internal Vref of an Atmega32 series?
a) 5V
b) 3.3V
c) 2.56V
d) all of the mentioned
Answer: c
Explanation: 2.56V is the internal Vref selected for an Atmega32 series based microcontrollers.
9. The output of a DAC0808 is in the form of ____________
a) electrical pulse
b) current
c) voltage
d) all of the mentioned
Answer: b
Explanation: The output of a DAC0808 is in the form of a current.
10. In a DAC the input is ______ and the output is ______
a) analog, digital
b) current, voltage
c) digital, analog
d) analog, current
Answer: c
Explanation: In a DAC, the input is digital and the output is analog in nature.
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1. Which of the following is correct about the word sensors?
a) that senses something
b) it is a type of a transducer that converts one form of energy to another
c) it can produce output in the form of electrical pulses, current or voltage
d) all of the mentioned
Answer: d
Explanation: Sensors are the devices that are used to sense a particular thing by converting one form of energy into a
nother, this converted form can be in the form of some analog output, or in the form of current or the voltage as the c
ase may be.
2. Why do we need to apply the concept of signal conditioning to a sensor?
a) in order to convert it into a desirable form of energy
b) for testing
c) for sensing something
d) all of the mentioned
Answer: a
Explanation: Signal Conditioning is the concept that is used for data acquisition of the signal. For measuring and ana
lyzing this value at a practical stage, by converting it into a desirable form of energy.
3. Which of the following is correct about LM35 based sensors?
a) its output voltage is directly proportional to the Celsius scale
b) its output voltage is directly proportional to the Fahrenheit scale
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: LM35 based sensors are those sensors whose output voltage is directly proportional to the Celsius scale
.
4. What is the difference between the LM34 and the LM35 based sensors?
a) one requires external calibration while other does not
b) one has output voltage proportional to the Celsius scale while others have to the Fahrenheit scale
c) one is fast other is slow
d) all of the mentioned
Answer: b
Explanation: LM35 has the output voltage proportional to the Celsius scale while the LM35 based sensors have outp
ut voltage proportional to the Fahrenheit scale.
5. Every transducer must be connected with the signal conditioning circuit?
a) true
b) false
c) can’t say
d) depends on the conditions
Answer: a
Explanation: For analyzing purposes, every transducer must be connected to a signal conditioning circuit in order to
measure its value as a practical platform.
6. LM35 provides _______ V for each degree count?
a) 1
b) 0.1
c) 0.001
d) 10
Answer: c
Explanation: LM35 provides 10mV for every degree change of the Celsius scale.
7. Why for the 8 bit analog input we select Vref as the 2.56V?
a) to obtain each degree count as the 2.56V
b) to get 2.56V at the output
c) to obtain each degree count as the 10mV
d) to get 10mV as the output
Answer: c
Explanation: For an 8 bit analog input, each degree count is calculated as the Vref/256, so if Vref is selected as 2.56
V then we can obtain 10mV for each degree count of the scale.
8. What is the temperature for LM35 sensor if the analog output is 0011 1001?
a) 3
b) 9
c) 57
d) 41
Answer: c
Explanation: The binary for the above output is 57, so in case of LM35 sensors we obtain the output as 57 C.
9. In an external hardware, there are how many pins available for the LM35 and the LM34 based sensors?
a) 2
b) 3
c) 10
d) 1
Answer: b
Explanation: LM35 consists of mainly 3 pins, they are Vcc, Gnd, analog output.
10. Do LM34 and LM35 based sensors have linear output?
a) yes
b) no
c) depends on the conditions
d) can’t say
Answer: a
Explanation: LM34 and the LM35 based sensors are linearly proportional to their corresponding Fahrenheit and the
Celsius scale, so they are linear by nature.
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1. The 8255 is a ______ chip.
a) Input/Output
b) Analog to Digital
c) Digital to analog
d) None of the mentioned
Answer: a
Explanation: The 8255 is Input/Output (I/O) chip. It has three separate accessible ports. The 8255 chip is used to exp
and the I/O ports of microcontrollers.
2. Which pins of a microcontroller are directly connected with 8255?
a) RD
b) WR
c) D0-D7
d) All of the mentioned
Answer: d
Explanation: RD, WR, D0-D7 all are directly connected to the 8051 for telling the chip about the control signals and
also for transferring the data.
3. Find the control word for PA= out, PB= in, PCL=out, PCH=out (Mode0)?
a) 0x02H
b) 0x82H
c) 0x83H
d) 0x03H
Answer: b
Explanation: The value that is being loaded in the control word is 10000010b for PB as an input port and all others a
s the output ports being operated in mode0. The hex equivalent of 10000010b → 0x82H.
4. Which pins are used to select the ports and the control register?
a) CS
b) A1
c) A0
d) All of the mentioned
Answer: d
Explanation: CS pin is an active low input pin for 8255 and it is used for selecting a chip. A0 and A1 pins are used f
or select ports and the control register.
5. What is the value of the control register when RESET button is set to zero?
a) 0x00H
b) 0xFFH
c) 0x11H
d) value remains the same
Answer: d
Explanation: RESET is active-high signal input into the 8255 used to clear the control register. When RESET is acti
vated (i.e. set to high), all ports are initialized as input mode. Hence the value of the control register remains the sam
e as it is even when the RESET button is set to zero.
6. Why MOVX instruction is being used to access the ports of the 8255?
a) because 8255 is connecting a microcontroller in memory mapped I/O configuration
b) because 8255 is used to access the external communication
c) because 8255 is used to access the data transfer
d) because 8255 is used to access the interfacing of LCD, motor etc
Answer: a
Explanation: As 8255 is connecting a microcontroller in memory mapped I/O configuration. This means that memor
y space used to access 8255 (i.e. 8255 is treated as external memory). MOVX instruction is used to access external
memory locations.
7. What is correct about the BSR mode from below?
a) In BSR mode, only the individual bits of PORT A can be programmed
b) In BSR mode, only the individual bits of PORT B can be programmed
c) In BSR mode, only the individual bits of PORT C can be programmed
d) none of the mentioned
Answer: c
Explanation: BSR (Bit Set/Rest) mode is used to program individual bits of PORT C only.
8. How many pins of the 8255 can be used as the I/O ports?
a) 8
b) 16
c) 24
d) 32
Answer: c
Explanation: They are 3 ports available in the 8255 so 24 pins are available for the I/O ports pins.
9. 8255 is a ____ pin IC.
a) 16
b) 8
c) 40
d) 60
Answer: c
Explanation: 8255 is a 40 pin IC.
10. 8255 has handshaking capability?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: 8255 is a device that with the help of its handshaking property gets interfaced with any microcontroller
.
11. The 8255 can be programmed in any of the __________
a) 2 modes
b) 3 modes
c) 4 modes
d) 5 modes
Answer: c
Explanation: 8255 can be programmed in any of the 4 modes.
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1. RTC is used for __________
a) conversion
b) communication
c) real time and clock measurement
d) memory management
Answer: c
Explanation: RTC is a device that is basically used for all the real time clock related issues.
2. RTC chips use ______ to compute time, date when the power is off.
a) ac supply
b) generators
c) rectifiers
d) battery
Answer: d
Explanation: RTC chips require batteries in order to calculate the time and date when the power of the device is off.
3. DS12887 is known for as a ________
a) Communication device
b) Good battery device
c) RTC chip
d) All of the mentioned
Answer: c
Explanation: DS12887 is known as an RTC chip.
4. DS1307 is a parallel RTC with I2C bus.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: DS1307 is a serial RTC with I2C bus.
5. DS1307 is a _______ pin IC and operates on _______ clock frequency.
a) 16, 8Mhz
b) 8, 16Mhz
c) 16, 32Mhz
d) 8, 32Khz
Answer: d
Explanation: DS1307 is a 8 pin IC and operates on a 32KHz clock frequency.
6. Vbat requires a positive signal of
a) 3V
b) 5V
c) 9V
d) 12V
Answer: a
Explanation: Vbat requires a positive signal of 3V which can be obtained through a battery.
7. In DS1307, which out of the following is correct about the SQW pin?
a) input pin
b) output pin
c) i/o pin
d) none of the mentioned
Answer: b
Explanation: In DS1307, SQW pin is an output pin. It provides a clock of frequency 1khz, 4khz, 8khz, 32khz if the p
in is enabled.
8. DS1307 has a total of _______ bytes of RAM space.
a) 32
b) 64
c) 128
d) 256
Answer: c
Explanation: DS1307 has a total of 64 bytes(00-3F) of RAM space.
9. DS1307 control register has an address of _________
a) 00H
b) 03H
c) 07H
d) 10H
Answer: b
Explanation: DS1307 control register has an address of 07H.
PSST! You better watch out, something's buggy above.
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1. Why are relays used for driving the motors?
a) they can be used as switch as well as they provide isolation
b) they increase the current capability required by the motors
c) they are used to reduce the back emf from the motors
d) all of the mentioned
Answer: a
Explanation: Relay is the electrically controlled switch and it allows isolation of two separate sections of the system.
It has three main components: the coil, the common pole and the contacts. When an electric field is applied to the c
oil; it gets energized and generates a magnetic field which will force the common pole to change contact from Norm
ally Closed to Normally Open.
2. Why are ULN2803 normally used between the microcontrollers and the relays?
a) for switching purposes
b) for increasing the current capability required by a relay
c) for increasing the voltage capability required by a relay
d) all of the mentioned
Answer: b
Explanation: More current is desired for driving a motor with the help of a relay, so a ULN2803 is used for increasin
g the current as per the requirement of the relay.
3. Why are opto isolators normally used between the microcontrollers and the ULN2803?
a) to optimize the current
b) to reduce the back emf
c) to increase the current
d) to increase the voltage
Answer: b
Explanation: Opto isolators are used between the microcontrollers and the ULN2803 chips in order to decrease the b
ack emf from the ULN2803 and to save the microcontrollers for a long time.
4. Which of the following is a type of an electromagnetic relay?
a) SPST
b) SPDT
c) DPDT
d) All of the mentioned
Answer: d
Explanation: There are normally three kinds of electromagnetic relays. They are SPST(single pole single throw), SP
DT(single pole double throw) and the DPDT(double pole double throw) relays.
5. Reed switches show connectivity whenever they are in the presence of an electrical field?
a) true
b) false
c) can’t say
d) depends on the conditions
Answer: b
Explanation: Reed switches are the devices that show connectivity whenever they are in the presence of some magne
tic field.
6. Which of the following is an application of stepper motors?
a) in printers
b) in robots
c) in vehicles
d) all of the mentioned
Answer: d
Explanation: Stepper motors are used wherever there is a need of a movement at an angle, maybe it in printers, in m
otors or in vehicles stepper motors are used everywhere.
7. What are normal 4 step sequence of a stepper motor if we start to move in clockwise direction with 0110 value?
a) 1100,1001,0011,0110
b) 0011,1001,1100,0110
c) 1001,1100,0110,0011
d) 0101,1010,0101,1010
Answer: b
Explanation: For a normal 4 step sequence of a stepper motor, if we start to move in a clockwise direction then we r
otate towards right direction with every rotation.
8. What is the meaning of a step angle?
a) angle which a stepper motor has
b) angle between the two windings of the stator in a stepper motor
c) minimum degree of rotation associated with a single step
d) angle between the stator and the rotor
Answer: c
Explanation: Step angle is the minimum degree of rotation associated with a single step.
9. For a normal 4 step sequence, what are the number of teeth required to accomplish a 2 degree step angle?
a) 180
b) 90
c) 360
d) 45
Answer: d
Explanation: For a 2 degree step angle there will be 180 step per rotation, so the total number of rotor teeth are (180/
4=45).
10. Ounch-inch is a unit of a torque.
a) true
b) false
c) can’t say
d) depends on the situation
Answer: a
Explanation: Torque is a quantity which is obtained by multiplying the amount of force that is applied at a particular
angle. It is measured in terms of ounch-inch.
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1. Why do we make the connection of the SCLK for communicating serially between two devices?
a) to get a clock output from the device
b) to synchronize the two devices
c) to obtain an analog output
d) all of the mentioned
Answer: d
Explanation: We need an SCLK in order for the two devices to communicate with each other properly. It acts as a p
ulse according to which one device sends a message and the other receives it.
2. What is the function of the CE pin in SPI?
a) it is used for synchronization
b) it is used as a transmitting pin
c) it is used as a receiving pin
d) it is used to initiate and terminate the data transfer
Answer: c
Explanation: CE pin is used to initiate and terminate the data transfer in the controller via SPI interface.
3. Which of the following is correct?
a) MOSI has the same meaning as the SDO
b) SCLK is used to initiate and terminate the data transfer
c) In 3 wire SPI, there is only one pin for transmission and reception
d) In 3 wire SPI, there are three pins MOSI, MISO and SCLK
Answer: b
Explanation: In 3 wire SPI, there is only one pin for transmission and reception and the other two pins SCLK and C
E are used for synchronization of data and for initialization and termination of data.
4. If CPHA= 0 and CPOL=1, then which of the following is true?
a) read on rising edge, changed on a falling edge
b) read on falling edge, changed on a rising edge
c) write on rising edge, changed on a falling edge
d) write on rising edge, changed on a falling edge
Answer: b
Explanation: If CPOL= 1 and CPHA= 0, then reading operation is performed on the rising edge and the change occu
rs at every falling edge.
5. In SPI write, LSB goes first?
a) true
b) false
c) can’t be said
d) depends on the cases
Answer: d
Explanation: In SPI write, MSB goes first.
6. In AVR, which of the following registers are used for SPI?
a) SPSR
b) SPCR
c) SPDR
d) All of the mentioned
Answer: b
Explanation: In AVR, SPSR(SPI Status Register), SPCR(SPI Control Register) and SPDR(SPI Data Register) are us
ed for programming the SPI module.
7. How do we set the SPI, to operate in the master mode 1?
a) We set the MSTR bit, and make the CPOL= 1 and CPHA=0
b) We set the MSTR bit, and make the CPOL= 0 and CPHA=1
c) We reset the MSTR bit, and make the CPOL= 1 and CPHA=0
d) We reset the MSTR bit, and make the CPOL= 0 and CPHA=1
Answer: b
Explanation: In SPI, to make it work in the master mode, we make the MSTR bit is equal to 1 and for operating it in
the mode 1 we make the CPOL=0 and CPHA=1.
8. SPI can act as a half duplex transmission?
a) true
b) false
c) depends on the conditions
d) can’t be said
Answer: d
Explanation: No, SPI can’t work in the half duplex transmission mode.
9. Which frequency is not recommended for SPI clock?
a) fosc/4
b) fosc/64
c) fosc/16
d) fosc/2
Answer: a
Explanation: fosc/2 is not recommended frequency for SPI transfer in AVR.
PSST! You better watch out, something's buggy above.
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1. Which of the following is correct?
a) I2C is a technique by which data is transmitted with the help of only eight pins
b) SDA is used to synchronize data transfer between two chips
c) TWI is another name for I2C
d) All of the mentioned
Answer: c
Explanation: I2C is a technique by which data is transmitted between two devices by the help of only 2 pins so it is a
lso called Two wire Serial Interface.
2. Which of the following is true about the I2C protocols?
a) the data line cannot change when the clock line is high
b) the data line can change when the clock line is high
c) the clock line cannot change when the data line is high
d) the clock line can change when the data line is high
Answer: a
Explanation: According to I2C protocols, the data line(SD
a) changes only if the clock line(SCL) is at its active low level.
3. I2C is a connection oriented communication protocol.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: I2C is a connection oriented protocol i.e each transmission is initiated by a START condition and is ter
minated by a STOP condition.
4. The STOP condition is generated by a
a) high to low change in the SDA line when the SCL is low
b) high to low change in the SDA line when the SCL is high
c) low to high change in the SDA line when the SCL is low
d) low to high change in the SDA line when the SCL is high
Answer: c
Explanation: The STOP condition is generated when there is a low to high change in the SDA line when the SCL is l
ow.
5. For receiving the acknowledgment
a) SDA from the transmitter should be high
b) SDA from the transmitter should be low
c) SDA from receiver should be high
d) SDA from receiver should be low
Answer: d
Explanation: The packet format in I2C consists of 9 bits, out of which first 8 are the data bits while the ninth bit is th
e acknowledgment bit. For obtaining the acknowledgment, the SDA line of the receiver should be pushed to low.
6. What steps are followed to complete the data transfer?
a) START condition, STOP condition
b) Address packet
c) One or more data packet
d) All of the mentioned
Answer: d
Explanation: For having the complete data transfer, the steps that are actually being followed are START condition,
address packet, one or more data packet, STOP condition.
7. I2C is ideal for short distances?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: I2C is that module of the AVR, which is used for short distances.
8. Which of the following is a register used for programming AVR’s I2C module?
a) TWBR
b) TWCR
c) TWSR
d) All of the mentioned
Answer: d
Explanation: TWBR( TWI Bit rate register), TWCR( TWI Control Register), TWSR(TWI Status Register), TWAR(
TWI Address Register), TWDR( TWI Data Register) are used for programming an AVR’s I2C module.
9. Which bit is polled to know that whether the TWI is ready or not?
a) TWWC
b) TWINT
c) TWEA
d) All of the mentioned
Answer: b
Explanation: TWINT is the bit that is polled to know that whether the TWI is ready or not.
PSST! You better watch out, something's buggy above.
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1. In MSP430, the size of the status register is ________
a) 1 byte
b) 2 bytes
c) 1 bit
d) 2 bit
Answer: b
Explanation: In MSP430, the size of the status register is 2 bytes. The bits of the status register consists of the C flag
, Z flag, N flag, GIE flag, CPU off, OSC off, SCG0, SCG1, V flag and 7 reserved bits.
2. Which of the following bit/s of the status register that allows the microcontroller to operate in its low power mode
?
a) Z
b) Reserved
c) CPU off
d) N
Answer: d
Explanation: The CPU off bit, OSC off bit, SCG0 bit, SCG1 bit of the status register are used to allow the microcont
roller to operate in its low power mode.
3. What is actually done to improve the efficiency of a RISC processor?
a) instructions are reduced
b) they have two or more processors inbuilt connected between
c) they have many instructions that are interrelated to each other
d) they have one or more registers hard wired to the commonly used values
Answer: d
Explanation: To improve the efficiency of the RISC processor, the registers that are hard wired to commonly used v
alues are used instead of other ones.
4. To improve the efficiency of an MSP430 based microcontroller, for one register
a) there is only one value for all addressing modes
b) there are two values for each addressing mode
c) there are 2 values for four addressing modes
d) there are 4 values for four addressing modes
Answer: d
Explanation: In MSP430, there are namely 4 addressing modes. So the main advantage of this controller( which basi
cally increases its efficiency )is that for one register their exists 4 different values for 4 different addressing modes o
f the controller.
5. Their are_______________ number of emulated instructions found in the MSP430?
a) 4
b) 8
c) 16
d) 24
Answer: c
Explanation: The constants CG1 and CG2 are combined together to give 27 native instructions. These instructions ar
e further converted into 24 emulated instructions. So, there are 24 emulated instructions found in an MSP430 based
controller.
6. .w form is used for operations
a) that uses bytes
b) that uses words
c) that uses both
d) that uses none
Answer: b
Explanation: .w form is used for operations, that uses both bytes and words for operations.
7. Pre increment addressing is available in MSP430?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: MSP430 supports only post increment addressing. For performing pre increment addressing, we requir
e some special functions that accomplish that work.
8. Which out of the following is a correct emulated instruction?
a) ADC(.
b) dst
b) ADD(.
b) src,dst
c) ADDC(.
b) src,dst
d) AND(.
b) src,dst
Answer: a
Explanation: “ADC(.
b) dst” this is emulated to “ADDC.B #0,dst” hence this is an emulated instruction. The emulated instructions use cor
e instructions combined with the architecture and implementation of the CPU for higher code efficiency and faster e
xecution.
9. dadd instruction can act as _____________
a) valid BCD addition
b) valid adder with carry
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: Dadd instruction can act as a valid BCD addition instruction if the numbers are initially in BCD state(0
-9).
PSST! You better watch out, something's buggy above.
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1. There are _____ number of addressing modes found for the source and _____ number of modes for the destinatio
n part.
a) 4,4
b) 2,4
c) 7,4
d) 2,2
Answer: c
Explanation: In MSP430, Seven addressing modes for the source operand and four addressing modes for the destinat
ion operand can address the complete address space with no exceptions.
2. MSP430 describes reti instruction as ___________
a) Format1 addressing
b) Format2 addressing
c) Jump addressing
d) None of the mentioned
Answer: b
Explanation: MSP430 describes reti instruction as that type of addressing which consists of only single operand, so i
t comes under Format2 addressing.
3. mov.w R3, R4 takes _________
a) one cycle
b) two cycles
c) four cycles
d) eight cycles
Answer: a
Explanation: mov.w R3, R4 takes only one cycle to transfer the data from register R3 to R4. This type of mode of ad
dressing is called the register mode of addressing.
4. Indexed addressing can be used for _________
a) source
b) destination
c) source & destination
d) none of the mentioned
Answer: c
Explanation: Indexed addressing is used for both the source and the destination addresses.
5. What do you understand form this instruction mov.w X(PC), R6
a) R6 = X+PC
b) R6 = PC-X
c) R6 = -X-PC
d) R6 = -X+PC
Answer: a
Explanation: This instruction mov.w X(PC), R6 means that the contents of X+PC address are copied to the R6 regist
er.
6. Absolute mode uses which of the following operators?
a) %
b) /
c) $
d) &
Answer: d
Explanation: Absolute mode uses the & operator to transfer a constant to a register.
7. Indirect register mode is used by _________
a) source register
b) destination register
c) source & destination register
d) none of the mentioned
Answer: a
Explanation: Indirect addressing mode is used only by the source register.
8. Indirect mode and the indirect auto increment mode have which common operator in them
a) +
b) –
c) @
d) &
Answer: c
Explanation: Both the indirect and the indirect auto increment mode use the @ operator for the source register to tra
nsfer the data from one memory location to a register.
9. Are the following two instructions similar?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: MOV @R10,0(R11) → Move the contents of the source address (contents of R10) to the destination ad
dress (contents of R11).
10. MOV @R10,0(R11) is a type of ________
a) Register Mode
b) Indirect Register Mode
c) Immediate Mode
d) Indirect Autoincrement Mode
Answer: b
Explanation: The type of given instruction is Indirect Register Mode.
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1. Which instruction is used to call functions?
a) MOV
b) GO
c) CALL
d) All of the mentioned
Answer: c
Explanation: CALL instruction is used for going to a particular address in MSP430. It actually causes the pointer to j
ump at a particular address and push the current address of the PC to the stack.
2. ret instruction is used for _________
a) determining the end of the program
b) for returning back from the subroutine to the main program
c) for transferring data from one place to another
d) none of the mentioned
Answer: b
Explanation: Ret instruction is basically used for returning back from a subroutine. It actually pops the top address fr
om the stack and moves that address to its PC, so that it now returns to the main program and continue the execution
normally.
3. According to conventions being followed, R12 to R15 are used for _________
a) parameter passing
b) preserved for call
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: According to the conventions, R12 to R15 are used for parameter passing and hence are not preserved f
or the call.
4. We can store the temporary results across a call instruction with the help of which of the following registers
a) R1-R4
b) R4-R11
c) R12-R15
d) All of the mentioned
Answer: b
Explanation: Temporary results are stored by the registers R4-R11.
5. Can we allocate variables on the stack?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, we can allocate the variables on the stack, it is a very effective way of storing the variables.
6. Which registers are reserved for passing the parameters to a subroutine and then returning the final result?
a) R1-R4
b) R4-R11
c) R12-R15
d) All of the mentioned
Answer: c
Explanation: Originally, R12-R15 registers are reserved for passing the parameters to a subroutine and then returnin
g the final result.
7. What actually is the order of stack frame for a parameter to pass to a subroutine?
a) parameter passed to a subroutine
b) return address
c) saved copies of registers(R4-R11)
d) all of the mentioned
Answer: d
Explanation: All the steps i.e. parameter passed to a subroutine, return address, saved copies of registers(R4-R11), lo
cal variables in subroutines are required for passing a parameter to a subroutine.
8. When any subroutine is called, then the first value of stack will be
a) value of PC
b) the return address
c) none of the mentioned
d) both are one and the same things
Answer: d
Explanation: When any subroutine is called then the first place of the stack will be filled with the return address, or t
he address of the PC so that the pointer may return back to its appropriate place after the return instruction of the sub
routine.
9. Which of the following instruction/s is/are used to return back to the main program after the subroutine is complet
ed?
a) ret
b) reti
c) ret and reti
d) none of the mentioned
Answer: c
Explanation: For returning back from the subroutine, both ret and reti can be used, the main difference between the t
wo is that reti just resets the interrupt flag before the return, so that the interrupt can occur again.
10. Is the approach of making subroutines effective or not?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The approach of making subroutine is indeed very effective, as with its help we don’t need to retrace/w
rite a particular set of codes again and again. It makes our approach modular.
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1. MSP430 uses vectored interrupts?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: MSP430 has vectored interrupts i.e. the address of each ISR is stored in a vector table, that’s why it has
vectored interrupts.
2. Which of the following is true?
a) interrupts are required to wake a CPU from sleep
b) same vector address associated with multiple flags
c) most interrupts are maskable
d) all of the mentioned
Answer: d
Explanation: All of the above mentioned statements are true i.e. interrupts are required to wake a CPU from sleep, sa
me vector address associated with multiple flags and most of the interrupts are maskable.
3. After the interrupt has occurred, the stack is filled with ______________
a) return address
b) status register
c) return address & status register
d) none of the mentioned
Answer: c
Explanation: When an interrupt had occurred, the top place of the stack is filled with the return address, so that imm
ediately after the reti instruction the pointer moves to the main program, the stack is also filled with the bits of the st
atus register so that all the temporary values get stored in it.
4. What is the purpose of __interrupt() function?
a) it is used to enable the interrupt
b) it is used to disable the interrupt
c) it denotes that the routine is an ISR
d) all of the mentioned
Answer: c
Explanation: The purpose of __interrupt() function is to denote that the routine is an ISR.
5. What is the purpose of .intvec assembler directive?
a) it creates an interrupt vector entry that points to an interrupt routine name
b) one is used for storage, other for display
c) one stores locally other stores globally
d) the two are the same
Answer: a
Explanation: The .intvec directive creates an interrupt vector entry that points to an interrupt routine name.
6. For enabling any interrupt, firstly _____________
a) GIE=0
b) GIE=1
c) None of the mentioned
d) GIE=0 & 1
Answer: b
Explanation: If GIE is set to 1, then only other hardware interrupts are enabled.
7. Nonmaskable vectors are stored at different vector locations?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Nonmaskable interrupts are stored in the same vector location, it may be of higher or the lower priority
.
8. Which of the following can generate a nonmaskable interrupt?
a) access violation to flash memory, ACCVIFG
b) timer_A interrupt
c) compare / capture interrupt
d) all of the mentioned
Answer: a
Explanation: A nonmaskable interrupt is generated by an access violation to flash memory, ACCVIFG.
9. External RST/NMI pin is a nonmaskable interrupt?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, external RST/NMI pin is a nonmaskable interrupt( The function of the RST/NMI pin is configure
d in the control register for the watchdog timer module, WDTCTL).
10. How many cycles are used by MSP430, when reti instruction is executed?
a) 3
b) 4
c) 5
d) depends on the conditions
Answer: c
Explanation: When reti instruction is executed, five cycles are used because it firstly pops the stack register complet
ely and then takes the top of the stack into the PC to return to the next address of the main program.
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1. There are how many MSP430’s low power modes available in the chip?
a) two
b) three
c) four
d) five
Answer: d
Explanation: There are five low power modes available in the MSP430, out of which two are rarely employed in the
current devices.
2. Which of the following are the low power modes?
a) LPM0
b) LPM3
c) LPM4
d) All of the mentioned
Answer: d
Explanation: LPM0, LPM3, LPM4 all are the low power modes that are available in the MSP430.
3. Which of the following modes is also known as the RAM retention mode?
a) LPM0
b) LPM3
c) LPM4
d) All of the mentioned
Answer: c
Explanation: LPM4 is known as the RAM retention mode. Here, the CPU and all clocks are disabled, I ≈ 0.1A. The
device can be woken only by an external signal.
4. Waking a device simply means that switching that device’s operation from a low power mode to an active mode.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: When a device is operating in a low power mode, it can also be assumed that the device is sleeping, so
waking a device simply means to turn that device’s operation from a low power mode to an active mode.
5. When an interrupt is accepted, the contents of the status register are ___________
a) set
b) reset
c) remains the same
d) cant be said
Answer: d
Explanation: When an interrupt is accepted, the contents of the status register are cleared, it actually puts the process
or in the active mode.
6. Which of the following basic clock modules supplies clock signals to the MSP430?
a) ACLK
b) MCLK
c) SMCLK
d) All of the mentioned
Answer: a
Explanation: All of the mentioned options are correct. The basic clock module supplies the MSP430 with three cloc
k signals as follows:
7. _ _low_ power_mode_0() states the processor to __________
a) enable the interrupt
b) disable the interrupt
c) nothing
d) to go in an active mode
Answer: b
Explanation: _ _low_ power_mode_0() puts the processor in the LPM0 mode.
8. More power can be saved by using low_power mode 0 than low_power mode 3.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: More power is saved in low_ power mode 3.
9. _BIC_SR_IRQ() is used to _______________
a) set the particular bits of the SR
b) reset the particular bits of the SR
c) any of the above mentioned depending on the conditions
d) none of the mentioned
Answer: b
Explanation: _BIC_SR_IRQ() is used to clear the bits of the SR.
PSST! You better watch out, something's buggy above.
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1. Which of the following registers are related to port P1?
a) P1SEL
b) P1DIR
c) P1IES
d) All of the mentioned
Answer: d
Explanation: All of the mentioned registers are related to Port1.
2. A pull-up or pull-down resistor ___________
a) removes the full output drive on the output pin
b) gives only a feeble current through the pull-up to resistor
c) removes the full output drive on the output pin & gives only a feeble current through the pull-up to resistor
d) none of the mentioned
Answer: c
Explanation: A pull-up or pull-down resistor is used to remove the full output drive on the output pin. It also gives a
feeble current through the pull-up to a resistor.
3. P1.3 is the ___________
a) input CCI1A to Timer_A
b) is connected to the voltage reference VREF of SD16_A
c) is output TA0 from Timer_A
d) are digital inputs with pull-up resistors
Answer: b
Explanation: P1.3 is connected to the voltage reference VREF of SD16_A.
4. What actually is SD16_A?
a) it is an interrupt
b) it is a timer
c) it is an analog to Digital Converter
d) it is a serial communication module
Answer: c
Explanation: SD16_A is an analog to the digital module.
5. P1IE and P1IES are registers that are used to ___________
a) control the Port1 digital i/o ports
b) control the Port1 interrupts
c) control the Port1 serial communication interfaces
d) all of the mentioned
Answer: b
Explanation: P1IE and P1IES both registers are used to control the Port1 interrupts.
6. Unused pins must never be left unconnected in their default state as inputs.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Unused pins must never be left unconnected in their default state as inputs. This follows a general rule
that inputs to CMOS must never be left unconnected or “floating”.
7. Which of the following is an effect of a Schmidt trigger?
a) it turns slowly varying inputs, which might cause problems while they pass slowly through the undefined range of
input voltages, into abrupt, clean logical transitions
b) It eliminates the effect of noise on the input, provided that it is not large enough to span the gap between the upwa
rd and downward thresholds
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: Schmidt trigger has two of the above mentioned effects in it.
8. To ensure that a negative fluctuation does not trigger an unwanted downward transition by pulling the input down
through VIT−, we must choose
a) minimum hysteresis
b) maximum hysteresis
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: To ensure that a negative fluctuation does not trigger an unwanted downward transition by pulling the i
nput down through VIT−, we must choose a minimum hysteresis of 0.3V.
9. The SPDT switch can be used as a ___________
a) detecting circuit
b) debouncing circuit
c) devaluing circuit
d) degenerating circuit
Answer: b
Explanation: The SPDT(single pole, double pole) switch can be used as a debouncing circuit of a switch.
10. Debouncing can be carried out at a hardware as well as the software end?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Debouncing can be carried out at both the fronts both at the software as well as the hardware front, to c
arry out the process appropriately.
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1. What are the basic functions of a timer?
a) it provided a time delay
b) it can act as a counter
c) it can control the compare, capture mode
d) all of the mentioned
Answer: d
Explanation: Timers are used to provide a time delay, they can even act as a counter and control the compare capture
mode of a microcontroller.
2. Most of the MSP430’s devices have __________ number of timers in it.
a) three
b) four
c) five
d) seven
Answer: c
Explanation: MSP430 has mainly five types of timers in it. They are Watchdog Timer, Basic Timer1, Real clock Ti
me, Timer_A, Timer_B.
3. A Watchdog Timer can act as an interval timer?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: A Watchdog Timer can act as an interval timer if the protection is not needed for it.
4. Which out of the following is the main function of a Watchdog timer?
a) control the compare mode
b) control the capture mode
c) protection from failures to the system
d) all of the mentioned
Answer: c
Explanation: Its main function is to protect the system against malfunctions.
5. Basic Timer1 can provide __________
a) clock for the LCD
b) an internal timer
c) clock to the LCD and can & also used as an interval timer
d) none of the mentioned
Answer: c
Explanation: Basic Timer1 device is used to provide the clock to the LCD and can also be used as an interval timer.
6. LCD_A controllers make use of the Basic Timer1 timer for providing a clock to the LCD?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Basic Timer1 is not used in LCD_A controllers, because these provide an internal clock of its own to al
l of its devices.
7. Real time clock is an extension of Basic Timer1?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Real time clock is an extension of Basic Timer1 and is present in almost all devices for controlling its r
eal time clock.
8. Timer_A can be used to _________
a) generate interrupts
b) handle external inputs
c) drive outputs
d) all of the mentioned
Answer: d
Explanation: Timer_A can be used to generate the interrupts, handle the external inputs or for driving the outputs.
9. Time stamp inputs can be measured by a Timer_A?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, time stamp inputs can be measured by a Timer_A.
10. Timer_B includes _________
a) sampling inputs
b) driving outputs
c) sampling inputs & driving outputs
d) none of the mentioned
Answer: b
Explanation: Timer_B is used for driving the outputs as with Timer_A but it lacks the property of Timer_A of sampl
ing inputs.
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1. The watchdog counts up and resets the MSP430 when it reaches the limit?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The watchdog timer is used for the protection of the device. It keeps a track at the counter so that the c
ode doesn’t reach an infinite unending loop. So it actually resets the counter before this particular condition.
2. Which of the following is correct about WDTCTL?
a) it is a 16 bit register
b) it is guided against accidental writes that require a password
c) a reset will occur if a value with an incorrect password is written to WDTCTL
d) all of the mentioned
Answer: d
Explanation: WDTCTL is a 16 bit register that is used for protecting the microcontroller. It actually resets the value
when an incorrect password is written to WDTCTL.
3. WDTNMI is found in the _________
a) higher byte of WDTCTL
b) lower byte of WDTCTL
c) its first four bits
d) its last four bits
Answer: b
Explanation: WDTNMI is the fifth bit of the WDTCTL register.
4. Which of the following bits reads 0 under normal conditions but goes 1 when it wants to initiate some action?
a) WDTNMI
b) WDTHOLD
c) WDTTMSEL
d) WDTCNTCL
Answer: d
Explanation: WDTCNTCL is the bit that reads 0 under normal conditions but goes 1 when it wants to initiate some a
ction like resetting the counter.
5. WDTISx bits control the _________
a) period of the clock
b) act as “Nonmaskable Interrupts”
c) stop the watchdog timer
d) start the watchdog timer
Answer: a
Explanation: WDTISx bits of the WDTCTL register is responsible for controlling the period of the clock.
6. The process of setting the WDTCNTCL bit in WDTCTL is through
a) petting
b) feeding
c) kicking
d) all of the mentioned
Answer: d
Explanation: the process of setting the WDTCNTCL bit in the WDTCTL register is by the processes like petting, fee
ding and kicking.
7. What is the function of this instruction “WDTCTL = WDTPW | WDTCONFIG”, where **#define WDTCONFIG
(WDTCNTCL|WDTSSEL)**
a) it sets the watchdog timer
b) it configures and clears the watchdog timer
c) it stops the watchdog timer
d) it configures and sets the watchdog timer
Answer: b
Explanation: WDTCTL = WDTPW | WDTCONFIG instruction is used to clear and configure the watchdog timer of
a microcontroller.
8. Is this instruction correct?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: No WDTCTL_bit.WDTCNTCL = 1; is an incorrect way of setting the bits of the WDTCTL register be
cause it violates the password protection.
9. Setting the WDTTMSEL bit of the WDTCTL register makes the watchdog timer act as
a) interrupt
b) communication device
c) converter
d) interval timer
Answer: d
Explanation: The WDTTMSEL bit of the WDTCTL register makes the watchdog timer act as the interval timer.
10. WDTIFG flag gets cleared if
a) if is interrupt had occurred
b) if the interrupt is serviced
c) if there can be no interrupt
d) all of the mentioned
Answer: b
Explanation: WDTIFG flag gets cleared if the interrupt is serviced so that again the interrupt can occur.
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1. Which of the following is true about the FRFQx bits of the BTCTL register?
a) these bits are used for clock input
b) these bits are used for setting a particular frequency fLCD
c) these bits start the timer
d) these bits stop the timer
Answer: b
Explanation: FRFQx bits of the BTCTL register are used for selecting a particular frequency fLCD varying from fA
CLK/256 to fACLK/32.
2. Timer1 is responsible for ________
a) providing a clock to the LCD module
b) cause an interrupt
c) a pulse for the RTC
d) all of the mentioned
Answer: d
Explanation: Timer1 is responsible for providing a clock for the LCD module. It can also cause an interrupt if the B
TIE bit is high. It also provides the clock to the RTC.
3. For fACLK = 32 KHz, what would be the desirable range of fLCD?
a) 2hz-256hz
b) 12hz-512hz
c) 128hz-1khz
d) 1khz-10khz
Answer: c
Explanation: For fACLK = 32khz, the desirable range of the fLCD is the fACLK/256 to fACLK/32. This value com
es out to be in the range of 128hz-1khz.
4. Normally BTCNT1 only function is to provide a prescalar for the BNTCNT2?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: LCD’s controllers nowadays don’t require a clock pulse, so the only main function of the BTCNT1 is t
o provide a prescalar for the BNTCNT2.
5. BTCNT2 provides 2 output signals?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: BNTCNT2 has no outputs. Instead, it raises the BTIFG flag at a frequency determined by the BTIPx bi
ts.
6. RTCSEC, RTCMIN, RTCDOW etc. are the bytes of a set of registers that are used to store
a) seconds
b) minutes
c) days of a week
d) all of the mentioned
Answer: d
Explanation: The current time and date are held in a set of registers that contain the following bytes like RTCSEC, R
TCMIN, RTCHOUR, RTCDOW etc.
7. The RTC module is configured in the calendar mode if __________
a) RTCMODE bit is reset
b) RTCMODE is set
c) RTCRDY is reset
d) RTCRDY is set
Answer: d
Explanation: Calendar mode is selected when RTCMODE is set.
8. The RTC module makes use of the Basic Timer1 because of _________
a) its bytes are controlled in the Basic Timer1 register
b) it is started by timer1
c) it is ended by basic timer1
d) it needs a clock pulse of 1hz that is provided by basic timer1
Answer: c
Explanation: The RTC module requires a clock of worth 1hz that is provided by basic timer1 so that why it makes u
se of basic timer1.
9. IF RTCIE interrupt is generated then _________
a) BTIFG flag is set
b) RTCFG flag is set
c) Both flags are set
d) None of the flag is set
Answer: c
Explanation: When RTCIE interrupt is generated then both BTIFG and RTCFG flags are set simultaneously.
PSST! You better watch out, something's buggy above.
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1. All channels within Timer_A share the same timer block?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: There is only one TAR in Timer_A so all of its channels share the same timer block.
2. Timer_A has _________
a) RTC module in it
b) Compare/ capture channel
c) Communication channel
d) Converter channel
Answer: b
Explanation: Timer_A has compared/ capture channel inbuilt inside it.
3. TACLK and INCLK are _________
a) internally generated clock pulses
b) externally fed clock pulses
c) of no use in Timer_A
d) very slow
Answer: b
Explanation: TACLK and INCLK clock pulses are the externally fed pulses that are required by the Timer_A.
4. In continuous mode of the counter _________
a) counter moves from 0000-ffff
b) counter moves from ffff-0000-ffff
c) counter moves from 0000-ffff and then again returns to 0
d) all of the mentioned
Answer: c
Explanation: In a continuous mode of the counter, the counter firstly increases from 0000-ffff, then after this value t
he roll over condition comes and it again gets started from 0000. This particular mode is very useful for capturing in
puts.
5. TACLR bit in TACTL _________
a) clear the interrupt flag
b) clear the status flags
c) clear the count in TAR
d) all of the mentioned
Answer: c
Explanation: TACLR bit in TACTL clears the count in the TAR.
6. TAxCCTLn is a _________
a) set of 2 bits used for selecting the mode of operation of the timer
b) a register of 8 bits used for giving the count to the timer
c) a register of 16 bits used to select the compare/capture channel of the Timer_Ax
d) a register of 16 bits used to cause the timer interrupt
Answer: c
Explanation: TAxCCTLn is a register of 16 bits used to select the compare/capture channel of the Timer_Ax.
7. CCI1B comes from _________
a) ACLK
b) CAOUT
c) SCLK
d) TACLK
Answer: b
Explanation: CCI1B comes from CAOUT.
8. Which of the following parameters are given by the TAxCCRn?
a) Capture/compare input. The selected input signal can be read by this bit
b) Synchronized capture/compare input. The selected CCI input signal is latched with the EQUx signal and can be re
ad from this bit
c) Holds the data for the comparison to the timer value in the Timer_A Register, TAR
d) None of the mentioned
Answer: c
Explanation: Compare mode: TAxCCRn holds the data for the comparison to the timer value in the Timer_A Regist
er, TAR.
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1. Why Timer_B is not considered as most suitable one for receiving asynchronous signals?
a) because of the absence of the TBOUTH input pin
b) because of the presence of the TBOUTH input pin
c) because of the absence of the SCCI bit
d) because of the presence of the SCCI bit
Answer: c
Explanation: The SCCI bit is absent in the Timer_B which means that the sampling mode is absent in it that’s why it
is considered as unsuitable for receiving asynchronous signals.
2. There is double buffering in the immediate mode?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Immediate mode offers no double buffering condition. As here, values are copied to TBCLn as soon as
they are written to TBCCRn.
3. Double buffering protects channel 0.
a) as it acts as the limit in the Up and up/down modes
b) it doesn’t actually protect it
c) as it does not accept the inputs
d) none of the mentioned
Answer: a
Explanation: Double buffering protects channel 0 as it acts as the limit in the Up and Up/Down modes.
4. Timer_B has _________
a) three serial communication ports
b) seven LCD driver
c) seven compare/capture channels
d) three LED driver ports
Answer: c
Explanation: Timer_B has seven compare/capture channels.
5. The capture/compare registers TBCCRn are double-buffered when used for compare events?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The capture/compare registers TBCCRn are double-buffered when used for compare events.
6. The length of TBR can be programmed to be _________
a) 8 bits
b) 12 bits
c) 16 bits
d) all of the mentioned
Answer: d
Explanation: The length of TBR can be programmed to be 8, 12, 16 or 10 bits long.
7. TBOUTH can pin can be used to _________
a) values are moved from one place to another
b) the length of the number of bits is selected by this register
c) it can be used to put all the outputs of the Timer_B register in the high impedance state
d) it can be used for outputting the input values of the timers
Answer: c
Explanation: TBOUTH pin is used to put all the outputs of the Timer_B register in the high impedance state by a hig
h external signal applied to this pin.
8. TBCLn provided in each channel is actually _________
a) a comparator
b) compare latch
c) controller
d) control logic
Answer: b
Explanation: TBCLn is actually a compare latch that is provided in its every channel.
9. When TBR counts to zero?
a) TBCLn is updated from TBCCRn
b) CLLDx is updated to TBCCTLn
c) CLLDx is updated to TBCCRn
d) TBCLn is updated to CLLDx
Answer: a
Explanation: When TBR counts to zero, TBCLn is updated from TBCCRn.
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1. Which of the following is the analog to digital converter that is present in the MSP430 based processors?
a) comparator
b) successive approximation ADC
c) sigma delta ADC
d) all of the mentioned
Answer: d
Explanation: A comparator module, a successive approximation ADC module and a sigma delta ADC converters are
found in the MSP based processors.
2. Higher resolution along with the slow speed is given by which ADC module?
a) comparator
b) successive approximation ADC
c) sigma delta ADC
d) all of the mentioned
Answer: c
Explanation: Higher resolution along with the slow speed is given by the sigma delta ADC module.
3. The technical terms that help us in differentiating between converters are:
a) resolution
b) accuracy
c) precision
d) all of the mentioned
Answer: d
Explanation: While selecting the converter, necessary for our work we had to take care of the factors like resolution,
accuracy and precision in it.
4. The number of repeated closeness to the true value is accounted by
a) resolution
b) accuracy
c) precision
d) all of the mentioned
Answer: c
Explanation: The degree of closeness of the measured value to the actual true value is its accuracy, while on the othe
r hand the measure of the repeated accuracy is termed as the precision.
5. Resolution is _________
a) change in measured value from the true value
b) the amount of change in the input value for the corresponding change of 1 unit in the output value
c) as the measure of the repeated accuracy
d) all of the mentioned
Answer: b
Explanation: Resolution is defined as the amount of change in the input value for the corresponding change of 1 unit
in the output value.
6. The process of reduction of a continuous input to a discrete output is
a) levelling
b) signalling
c) quantization
d) converting
Answer: c
Explanation: The process of reduction of a continuous input to a discrete output is called as quantization.
7. Which of the following functions can be used for converting the nearest integer to its argument?
a) int
b) mint
c) uint
d) nint
Answer: d
Explanation: nint is the function that is priorly used for converting the nearest integer to its argument.
8. Integral nonlinearity is termed as
a) process of reduction of a continuous input to a discrete output
b) change in measured value from the true value
c) maximum deviation between this corrected staircase and the actual transfer characteristic
d) the function used in the quantization
Answer: c
Explanation: Integral nonlinearity is termed as the maximum deviation between this corrected staircase and the actua
l transfer characteristic.
9. The SNR_______ with the increase of the number of bits.
a) remains constant
b) goes up
c) goes down
d) goes asymmetrically
Answer: b
Explanation: The SNR goes up with the number of bits.
10. The intervals between the samples are obtained from _________
a) Fs
b) Ts
c) Us
d) Ks
Answer: b
Explanation: The intervals between the samples is obtained by Ts that is equal to 1/fs.
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1. Comparator_A+ is controlled by which of the following peripheral registers?
a) CACTL1
b) CACTL2
c) CACTL1 & CACTL2
d) None of the mentioned
Answer: c
Explanation: Comparator_A+ is controlled by the CACTL1 and the CACTL2 registers.
2. CAON bit is used to ___________
a) start a timer
b) start an A/D conversion
c) switch on the comparator module
d) switch on the bit transmission
Answer: c
Explanation: CAON bit is used to switch on the comparator module namely, Comparator_A+.
3. P2CA4-P2CA0 bits are used for _______
a) giving the power supply to the comparator module
b) for selecting the mode of operation of the comparator
c) for connecting the non inverting inputs to the CA0-CA2 pins
d) all of the mentioned
Answer: c
Explanation: P2CA4-P2CA0 bits are used for connecting the non inverting inputs to the CA0-CA2 pins.
4. CAREFx bits are used for _______
a) inputting a positive reference voltage
b) inputting a negative reference voltage
c) selecting the internal reference voltage
d) all of the mentioned
Answer: c
Explanation: CAREFx bits are used for selecting the appropriate reference voltage for the comparator.
5. Which of the following bits are not actually associated with the comparator module?
a) CAREFx
b) CLLDx
c) CAON
d) CAIFG
Answer: b
Explanation: CLLDx bit is related to the Timer_2 module. All others are related to the comparator module.
6. Flag CAIFG is raised,
a) at a low level triggered pulse
b) at a high level triggered pulse
c) at the falling and rising edge of the pulse
d) at the falling or rising edge of the pulse
Answer: d
Explanation: Flag CAIFG is raised, at the falling or rising edge of the pulse that is selected by the CAIES bit.
7. Setting a bit in the Port Disable register CAPD causes the circuits for the usual digital input and output buffers to
be disconnected from the appropriate pin.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Setting a bit in the Port Disable register CAPD causes the circuits for the usual digital input and output
buffers to be disconnected from the appropriate pin.
8. Which bit is used for exchanging the two inputs of the comparator and invert its output to compensate?
a) CAIFG
b) CASHORT
c) CAPD
d) CAEX
Answer: d
Explanation: CAEX is used for exchanging the two inputs of the comparator and invert its output to compensate.
9. Changes in Vcc changes the value of V+?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: When some variation is made in the value of Vcc, in the same manner, itself the value of the V+ chang
es because, the voltage from the potential divider is proportional to Vcc. This changing effect can be reduced if the s
imilar change takes place in the value of V- itself.
10. The relaxation oscillator circuit helps in _______
a) calculating the duration single RC transient
b) setting the reference voltage
c) setting the clock frequency
d) calculating the conversion speed
Answer: a
Explanation: The relaxation oscillator is a circuit that with the help of charging and discharging of an oscillator, help
us in calculating the duration of the single RC transient.
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1. The successive approximation converters have a resolution of _________
a) 8-10 bits
b) 10-12 bits
c) 12-16 bits
d) 16-32 bits
Answer: b
Explanation: The successive approximation converters have a resolution of about 10-12 bits in it.
2. In SAR based conversions, each bit typically requires one clock cycle (sometimes two) to make a comparison and
set up the new voltage.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: In SAR based conversions, each bit typically requires one clock cycle (sometimes two) to make a com
parison and set up the new voltage.
3. The main operations that are basically performed in a SAR ADC are?
a) logic to control the operation
b) some way of generating the voltages, for comparison
c) logic to control the operation and finding some way of generating the voltages for comparison
d) none of the mentioned
Answer: c
Explanation: The main operations that are basically performed in a SAR ADC are the logic to control the operation a
nd finding some way of generating the voltages, for comparison.
4. Usually, a capacitor is inserted between an analog input and the ground because
a) it blocks the analog voltage
b) it suppresses the noise
c) it increases the gain
d) none of the mentioned
Answer: b
Explanation: A capacitor is inserted between the analog input and the ground because it suppresses the noise.
5. ADC10 and ADC12 are _________
a) The converters
b) SAR modules available in the MSP430
c) Sigma delta modules available in the MSP430
d) Comparator modules available in the MSP430
Answer: b
Explanation: ADC10 and ADC12 are the SAR modules available in the MSP430.
6. ADC10 needs external capacitors on its voltage reference.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: ADC12 needs external capacitors on its voltage reference as compared to the ADC10 module.
7. ADC10CTL0 and ADC10CTL1 are registers
a) for controlling SAR module
b) for controlling the sigma delta module
c) for controlling the comparator module
d) all of the mentioned
Answer: a
Explanation: ADC10CTL0 and ADC10CTL1 are the registers that are used for controlling the SAR module in the
MSP430.
8. While conversion is in progress, which of the flag is affected.
a) ADC10ON
b) ADC10MEM
c) ADC10BUSY
d) ADC10DF
Answer: c
Explanation: While conversion is in progress, then ADC10BUSY flag is set.
9. ADC10SHTx bits allow_________cycles of the ADC10CLK.
a) 4
b) 8
c) 16
d) all of the mentioned
Answer: d
Explanation: ADC10SHTx bits allow 4,8,16 and 64 cycles of the ADC10CLK.
10. The input to the ADC10 is selected from_______bits of the ADC10CTL1 register?
a) INCHx
b) ADC10SC
c) ADC10ON
d) ENC
Answer: a
Explanation: The input to the ADC10 is selected from the INCHx bits of the ADC10CTL1 register.
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1. The basic idea behind the sigma delta converter is that
a) to carry out the conversion
b) to carry out communication
c) to reduce the circuit to its simplest way possible and then carry out the conversion
d) all of the mentioned
Answer: c
Explanation: The main idea behind the sigma delta converter is that to reduce the circuit to its simplest way possible
and then carry out the conversion.
2. Sigma delta converter is a __________
a) 1 bit converter
b) 2 bit converter
c) 3 bit converter
d) 4 bit converter
Answer: a
Explanation: Sigma delta converter is a 1 bit converter.
3. Sigma delta converter is having good resolution.
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Sigma delta converter is having poor resolution quality.
3. Oversampling ratio is defined as the _________
a) final frequency
b) oversampling frequency
c) oversampling frequency/final frequency
d) final frequency/oversampling frequency
Answer: c
Explanation: Oversampling ratio is defined as the ration of the oversampling frequency fm to the final frequency fs.
4. Here the word sigma represents _________
a) subtraction
b) differentiation
c) integration
d) none of the mentioned
Answer: c
Explanation: In a sigma delta converter, sigma word represents that the output obtained from the delta function is get
ting integrated.
5. SD16_A features are controlled by _________
a) memory mapped registers
b) register mapped registers
c) data mapped registers
d) none of the mentioned
Answer: a
Explanation: SD16_A features are controlled by the memory mapped registers.
6. The second part of the ADC handles purely digital signals.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The second part of the ADC handles purely digital signals.
7. The second part of the ADC’s output is in the form of _________
a) the fast stream of single bits
b) the fast stream of multiple bits
c) the slow stream of single bits
d) the slow stream of multiple bits
Answer: d
Explanation: The second part of the ADC take in fast stream of single bit and give out a slow stream of multiple bit
values.
8. The filtered digital signal is then decimated to
a) reduce the rate of samples from fm to fs
b) reduce the rate of samples from fs to fm
c) increase the rate of samples from fm to fs
d) increase the rate of samples from fs to fm
Answer: a
Explanation: The filtered digital output is then decimated in order to reduce the rate of samples from fm to fs.
9. Decimated means _________
a) multipled by 10
b) multiplied by 100
c) divided by 10
d) divided by 100
Answer: c
Explanation: Decimated means to divide the result by 10.
10. The SD16 has a second-order modulator with a _________
a) sinc filter
b) sinc2 filter
c) sinc3 fiter
d) rect filter
Answer: c
Explanation: The SD16 has a second-order modulator with a sinc3 filter.
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1. What actually is a bit bagging?
a) it actually refers to the technique of assigning the bits with their inputs
b) a technique by which an MSP430 can communicate through hardware
c) a technique by which MSP430 can communicate through software
d) a technique through which conversion becomes possible
Answer: c
Explanation: Bit bagging is the technique through which a processor can communicate to its associate partners when
an appropriate hardware is not available for its purpose. This communication is made possible through the software.
2. SPI, I2C, Asynchronous serial communication are the means of communicating a processor with its associate part
ners?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: SPI, I2C, Asynchronous serial communication are the means for the processor by which communicatio
n is made possible.
3. All digital communications don’t require any clock.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Clock is the prior need for any communication to occur. This is because synchronization is maintained
with the help of a clock.
4. SPI needs______ wires than I2C?
a) less
b) same
c) more
d) depends on the conditions
Answer: c
Explanation: In SPI, there is no control of transmission in software—no addresses or acknowledgment, that’s why it
requires more amount of wires.
5. USI handles _________
a) SPI
b) I2C
c) SPI & I2C
d) None of the mentioned
Answer: c
Explanation: USI(Universal Serial Interface) supports both the types of synchronous communication i.e. SPI and I2
C.
6. USCI consists of _________
a) one channel
b) two channels
c) three channels
d) four channels
Answer: b
Explanation: USCI consists of mainly two channels, A and B. These are largely independent but share a few register
s and interrupt vectors.
7. LIN is enabled in which of the following channels?
a) A
b) B
c) C
d) D
Answer: a
Explanation: Channel A is the asynchronous receiver/ transmitter channel. It can detect the baud rate of an incoming
signal, which enables its use on a local interconnect network (LIN).
8. Can one device have more than one USC interfaces?
a) yes
b) no
c) depends on the conditions
d) cant be said
Answer: a
Explanation: Yes, one device can have more than one USC interfaces. There is a small difference because the interru
pt flags and enable bits for the “0” modules are in a special function registers IFG2 and IE2, while those for the “1”
modules are in their own registers, UC1IFG and UC1IE.
9. Which of the following conditions is more difficult to attain?
a) synchronous masters
b) synchronous slaves
c) asynchronous masters
d) asynchronous slaves
Answer: d
Explanation: Synchronous slaves are the most difficult to attain because the problem is that the slave must react quic
kly when a clock transition arrives from the master.
10. Timer_A is used in _________
a) SPI
b) I2C
c) Asynchronous Serial Communication
d) All of the mentioned
Answer: c
Explanation: Timer_A is used in the Asynchronous Serial Communication.
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1. Is SPI a full duplex technique?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, SPI is a technique where a data can be transmitted/ received in both the directions.
2. The concept of SPI is based on __________
a) two counters
b) four flip flops
c) two shift registers
d) four steady state machines
Answer: c
Explanation: The concept of the SPI is based on the two shift registers, one for the transmitter and the other is there f
or the receiver terminal.
3. Writing on the trailing edge of the clock pulse and reading on the leading edge of the clock pulse is done when
a) CPHA is set
b) CPHA is reset
c) CPOL is set
d) CPOL is reset
Answer: b
Explanation: When CPHA is reset to zero, then writing on the trailing edge of the clock pulse and reading on the lea
ding edge of the clock pulse.
4. When CPOL=1 then,
a) clock idles high between transfers
b) clock idles low between transfers
c) bit idles high between transfers
d) bit ideals low between transfers
Answer: a
Explanation: When CPOL=1, clock idles high between transfers.
5. Is CPKH and CPOL the same.
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: CPKL=CPOL and CPKH=(not CPHA).
6. SPI with the USI can be selected by ________
a) setting the USII2C bit in the register USICTL1
b) clearing the USII2C bit in the register USICTL1
c) setting the USIPE5–7 bits in USICTL0
d) clearing the USIPE5–7 bits in USICTL0
Answer: b
Explanation: SPI with the USi can be selected by clearing the USII2C bit in the register USICTL1.
7. SCLK, SDO, and SDI are found ___________ on F20x3.
a) P1.0-2
b) P1.2-4
c) P1.4-6
d) P1.5-7
Answer: d
Explanation: SCLK, SDO, and SDI are found at P1.5-7 on F20x3.
8. Transmission and reception are made at a time in SPI?
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Transmission and reception occur at a time in SPI. This means that a value is received only if the trans
mitter is active.
9. When the buffer is ________ the low power mode is__________
a) empty, reset
b) having one byte, reset
c) full, reset
d) empty, two
Answer: c
Explanation: When the buffer is full, the low power mode is cleared.
10. Falling edge of the SS pin denotes ________
a) end of the transfer
b) starts a new transfer
c) selects a new master
d) none of the mentioned
Answer: b
Explanation: Falling edge of the SS pin denotes the start of a new transfer over SPI.
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1. The I2C bus uses which of the following lines?
a) CLK
b) MISO
c) SDA
d) All of the mentioned
Answer: c
Explanation: The I2C bus uses only two lines. They are SDA and SCL.
2. I2C is a faster means of data transfer than SPI?
a) yes
b) no
c) depends on the conditions
d) cant be said
Answer: b
Explanation: I2C is a slower means of transfer than SPI because here only one line is there for the two way commun
ication to occur.
3. Each slave has its unique address.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, in I2C protocol each slave has its own unique address, in order to differentiate it from others.
4. Pull-up resistors Rp keep the lines at VCC when _____________
a) all the drivers are active
b) none of the drivers are active
c) some the drivers are at sleep
d) none of the drivers is at sleep
Answer: b
Explanation: Pull-up resistors Rp keep the lines at VCC when all of the drivers are active.
5. Rising edge on SDA while SCL is high denotes __________
a) start condition (S)
b) stop condition (P)
c) transfer in progress
d) none of the mentioned
Answer: b
Explanation: Rising edge on SDA while SCL is high denotes the stop condition of the transfer.
6. Which of the following is an issue while programming I2C using the software?
a) open-collector output
b) open-drain output
c) totem pole output
d) all of the mentioned
Answer: b
Explanation: There are two main issues while programming I2C using software, they are the open-drain output and t
he detection of start and stop conditions.
7. Which of the following is the slave to be addressed when a device acts as a master?
a) UCB0I2COA
b) UCB0I2CSA
c) UCB0I2CIE
d) All of the mentioned
Answer: b
Explanation: UCB0I2CSA is the slave to be addressed when a device acts as a master.
8. Is baud rate selected in I2C?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, baud rate is also selected in the I2C module, as is the case with the SPI module.
9. How is I2C with USI different from I2C with USI_B?
a) there is only one common pin between the two devices
b) here in this case no synchronization is important
c) the outputs of SDA and SCL are open drain
d) none of the mentioned
Answer: c
Explanation: I2C is different in USI than that of USI_B module because here in this module, the output pins SDA an
d the SCL are open drains in nature.
10. UCB0RXIFG is set when ________
a) complete byte is acknowledged
b) complete byte is transmitted
c) complete byte is received
d) none of the mentioned
Answer: c
Explanation: UCB0RXIFG is set when the complete byte sent via I2C is received.
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1. Asynchronous serial communication usually requires two wires for each direction plus a common ground.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Asynchronous serial communication usually requires only a single wire for each direction plus a comm
on ground.
2. In an asynchronous mode of transmission, usually the data is sent along with the
a) the start bit
b) the stop bit
c) the start & stopbit
d) none of the mentioned
Answer: c
Explanation: In an asynchronous mode of transmission, both the start and the stop bits are present that are basically
used for intimating the other terminal that whether the data had received correctly the other destination or not.
3. The _____ rate gives the frequency at which the bits are transmitted on the line.
a) bit rate
b) packet rate
c) baud rate
d) data rate
Answer: c
Explanation: Baud rate is the rate which determines us the frequency at which the bits are transmitted on the line.
4. Baud rate is the reverse of the ________
a) baud time
b) baud period
c) bit time
d) bit period
Answer: b
Explanation: Baud rate is the reverse of the baud period.
5. Clock is transmitted in the asynchronous communication?
a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: No clock is transmitted in the asynchronous communication, so the transmitter and the receiver are allo
wed to work independently at their own terminals.
6. A framing error occurs is the bit is ________
a) high
b) low
c) same
d) changed
Answer: b
Explanation: Framing error occurs if the bit is low.
7. What is the non return to zero format?
a) the bits are either high or low and have no gaps between them
b) the bits are either high or low and have gaps between them
c) the bits are high and have gaps between them
d) the bits are low and have no gaps between them
Answer: a
Explanation: Non-return to zero format represents a format in which the bits are either high or low and have no gaps
between them.
8. LSB is sent first in case of the non return to zero format.
a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: In non-return to zero format, normally LSB is sent first.
9. There are _______ clocks in the USCI_A.
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: they are 3 clocks in the USCI_A. They are BRCLK, BITCLK and BITCLK16.
10. BITCLK16 is the ________
a) sampling clock in the undersampling mode
b) sampling clock in the oversampling mode
c) quantising clock in the undersampling mode
d) quantising clock in the oversampling mode
Answer: b
Explanation: BITCLK16 is the sampling clock in the oversampling mode.
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This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Machine Language Instruction Formats”.
1. Operation code field is present in :
a) programming language instruction
b) assembly language instruction
c) machine language instruction
d) none of the mentioned
Answer: c
Explanation: Machine language instruction format has one or more fields. The first one is the
operation code field.
2. A machine language instruction format consists of
a) Operand field
b) Operation code field
c) Operation code field & operand field
d) none of the mentioned
Answer: c
Explanation: Machine language instruction format has both the fields.
3. The length of the one-byte instruction is
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
Answer: b
Explanation: This format is only one byte long.
4. The instruction format ‘register to register’ has a length of
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
Answer: a
Explanation: This format is 2 bytes long.
5. The R/M field in a machine instruction format specifies
a) another register
b) another memory location
c) other operands
d) all of the mentioned
Answer: d
Explanation: The LSBs
leastsignificantbits
from 0 to 3 represent R/M field that specifies another register or memory location i.e. the other
operand.
6. In a machine instruction format, S-bit is the
a) status bit
b) sign bit
c) sign extension bit
d) none of the mentioned
Answer: c
Explanation: The S-bit known as sign extension bit is used along with W-bit to show the type of
operation.
7. The bit which is used by the ‘REP’ instruction is
a) W-bit
b) S-bit
c) V-bit
d) Z-bit
Answer: d
Explanation: The Z-bit is used by the REP instruction to control the loop.
8. If a W-bit value is ‘1’ then the operand is of
a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits
Answer: c
Explanation: If W-bit is ‘1’ then the operand is of 16-bits, and if it is ‘0’ then the operand is of
8-bits.
9. The instructions which after execution transfer control to the next instruction in the sequence
are called
a) Sequential control flow instructions
b) control transfer instructions
c) Sequential control flow & control transfer instructions
d) none of the mentioned
Answer: a
Explanation: The sequential control flow instructions follow sequence order in their execution.
10. The instructions that transfer the control to some predefined address or the address
specified in the instruction are called as
a) sequential control flow instructions
b) control transfer instructions
c) sequential control flow & control transfer instructions
d) none of the mentioned
Answer: b
Explanation: The control transfer instructions transfer control to the specified address.
11. The instruction “JUMP” belongs to
a) sequential control flow instructions
b) control transfer instructions
c) branch instructions
d) control transfer & branch instructions
Answer: d
Explanation: The JUMP instruction transfers the control to the address located in the instruction.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Addressing Modes of 8086”.
1. The instruction, MOV AX, 0005H belongs to the address mode
a) register
b) direct
c) immediate
d) register relative
Answer: c
Explanation: In Immediate addressing mode, immediate data is a part of instruction and appears
in the form of successive byte or bytes.
2. The instruction, MOV AX, 1234H is an example of
a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
Answer: c
Explanation: Since immediate data is present in the instruction.
3. The instruction, MOV AX, [2500H] is an example of
a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
Answer: b
Explanation: Since the address is directly specified in the instruction as a part of it.
4. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
Answer: b
Explanation: Since register is used to refer the address.
5. The instruction, MOV AX,[BX] is an example of
a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
Answer: d
Explanation: Since the register used to refer to the address is accessed indirectly.
6. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned
Answer: c
Explanation: In the indexed addressing mode, the offset of an operand is stored and in the rest
of them, address is stored.
7. The addressing mode that is used in unconditional branch instructions is
a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
Answer: b
Explanation: In intrasegment indirect mode, the branch address is found as the content of a
register or a memory location.
8. If the location to which the control is to be transferred lies in a different segment other than
the current one, then the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode
Answer: d
Explanation: In intersegment mode, the control to be transferred lies in a different segment.
9. The instruction, JMP 5000H:2000H;
is an example of
a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode
Answer: c
Explanation: Since in intersegment direct mode, the address to which the control is to be
transferred is in a different segment.
10. The contents of a base register are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode
Answer: d
Explanation: The effective address is formed by adding the contents of both base and index
registers to a default segment.
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Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Instruction Set of 8086/8088 – 1”.
1. The instruction that is used to transfer the data from source operand to destination operand is
a) data copy/transfer instruction
b) branch instruction
c) arithmetic/logical instruction
d) string instruction
Answer: a
Explanation: These instructions are used to copy and transfer the instructions.
2. Which of the following is not a data copy/transfer instruction?
a) MOV
b) PUSH
c) DAS
d) POP
Answer: c
Explanation: DAS
DecimalAdjustafterSubtraction
is an arithmetic instruction.
3. The instructions that involve various string manipulation operations are
a) branch instructions
b) flag manipulation instructions
c) shift and rotate instructions
d) string instructions
Answer: d
Explanation: The string instructions perform operations on strings such as load, move, scan,
compare etc.
4. Which of the following instruction is not valid?
a) MOV AX, BX
b) MOV DS, 5000H
c) MOV AX, 5000H
d) PUSH AX
Answer: b
Explanation: Both the source and destination operands cannot be memory locations except for
string instructions.
5. In PUSH instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
Answer: d
Explanation: The actual current stack-top is always occupied by the previously pushed data. So,
the push operation decrements SP by 2 and then stores the two bytes contents of the operand
onto the stack.
6. The instruction that pushes the contents of the specified register/memory location on to the
stack is
a) PUSHF
b) POPF
c) PUSH
d) POP
Answer: c
Explanation: Since PUSH operation transfers data to stack from a register or memory location.
7. In POP instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
Answer: c
Explanation: The actual current stack top is poped into the specific operand as the contents of
stack top memory is stored in AL&SP and further contents of the memory location pointed to by
SP are copied to AH & SP.
8. The instructions that are used for reading an input port and writing an output port respectively
are
a) MOV, XCHG
b) MOV, IN
c) IN, MOV
d) IN, OUT
Answer: d
Explanation: The address of the input/output port may be specified directly or indirectly.
Example for input port: IN AX, DX; This instruction reads data from a 16-bit port whose address
is in DX and stores it in AX
Example for output port: OUT 03H, AL; This sends data available in AL to a port whose address
is 03H.
9. The instruction that is used for finding out the codes in case of code conversion problems is
a) XCHG
b) XLAT
c) XOR
d) JCXZ
Answer: b
Explanation: The translate
XLAT
instruction is used to find codes.
10. The instruction that loads effective address formed by destination operand into the specified
source register is
a) LEA
b) LDS
c) LES
d) LAHF
Answer: a
Explanation: The instruction, LEA loads effective address and is more useful for assembly
language rather than for machine language.
11. The instruction that loads the AH register with the lower byte of the flag register is
a) SAHF
b) AH
c) LAHF
d) PUSHF
Answer: c
Explanation: The instruction LAHF
LoadAHfromalowerbyteofFlag
may be used to observe the status of all the condition code flags
exceptoverflowflag
at a time.
12. The instruction that pushes the flag register on to the stack is
a) PUSH
b) POP
c) PUSHF
d) POPF
Answer: c
Explanation: The instruction PUSHF
pushflagstostack
pushes the flag register on to the stack.
13. The instruction that loads the flag register completely from the word contents of the memory
location is
a) PUSH
b) POP
c) PUSHF
d) POPF
Answer: d
Explanation: POPF is pop flags to stack.
14. The instruction that adds immediate data/contents of the memory location specified in an
instruction/register to the contents of another register/memory location is
a) SUB
b) ADD
c) MUL
d) DIV
Answer: b
Explanation: ADD instruction adds the data.
15. The instruction that supports addition when carry exists is
a) ADD
b) ADC
c) ADD & ADC
d) None of the mentioned
Answer: b
Explanation: ADC
AddwithCarry
instruction performs the same operation as ADD operation, but adds the carry flag bit to the
result.
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Questions and Answers .
This set of Microprocessors Interview Questions and Answers focuses on “Instruction Set of
8086/8088 – 2”.
1. The instruction, “INC” increases the contents of the specified register or memory location by
a) 2
b) 0
c) 1
d) 3
Answer: c
Explanation: This instruction adds 1 to the contents of the operand and so increments by 1.
2. The instruction that subtracts 1 from the contents of the specified register/memory location is
a) INC
b) SUBB
c) SUB
d) DEC
Answer: d
Explanation: The DEC instruction decrements the contents of a specified register/memory
location by 1.
3. The instruction that enables subtraction with borrow is
a) DEC
b) SUB
c) SBB
d) None of the mentioned
Answer: c
Explanation: The SBB instruction subtracts the source operand and the borrow flag from the
destination operand.
4. The flag that acts as Borrow flag in the instruction, SBB is
a) direction flag
b) carry flag
c) parity flag
d) trap flag
Answer: b
Explanation: If borrow exists in the subtraction operation performed then carry flag is set.
5. In general, the source operand of an instruction can be
a) memory location
b) register
c) immediate data
d) all of the mentioned
Answer: d
Explanation: The source operand is the element which is data or data stored memory location
on which operation is performed.
6. In general, the destination operand of an instruction can be
a) memory location
b) register
c) immediate data
d) memory location and register
Answer: d
Explanation: Since the destination should be able to store the data, immediate data cannot be
considered as a destination operand.
7. The instruction, CMP to compare source and destination operands it performs
a) addition
b) subtraction
c) division
d) multiplication
Answer: b
Explanation: For comparison, the instruction CMP subtracts source operand from destination
operand.
8. During comparison operation, the result of comparing or subtraction is stored in
a) memory
b) registers
c) stack
d) no where
Answer: d
Explanation: The result of subtraction operation is not stored anywhere during a comparison.
9. The instruction that converts the result in an unpacked decimal digits is
a) AAA
b) AAS
c) AAM
d) All of the mentioned
Answer: d
Explanation: All the ASCII adjust instructions give result in unpacked decimal form and so are
called as “Unpacked BCD arithmetic instructions”.
10. Which of the following is a mnemonic?
a) ADD
b) ADC
c) AAA
d) ADD & ADC
Answer: c
Explanation: AAA is a mnemonic. It doesn’t have either a source or destination operand.
11. The instruction in which adjustment is made before performing the operation is
a) AAA
b) AAS
c) AAM
d) AAD
Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL. This adjustment must be made before dividing the two
unpacked BCD digits.
12. The expansion of DAA is
a) decimal adjust after addition
b) decimal adjust before addition
c) decimal adjust accumulator
d) decimal adjust auxiliary
Answer: c
Explanation: This instruction performs conversion operation.
13. The instruction that is used to convert the result of the addition of two packed BCD numbers
to a valid BCD number is
a) DAA
b) DAS
c) AAA
d) AAS
Answer: a
Explanation: In this conversion, the result has to be only in AL.
14. The ROR instruction rotates the contents of the destination operand to
a) left
b) right
c) left and then right
d) right and then left
Answer: b
Explanation: ROR stands for Rotate Right without carry. so, the instruction rotates right.
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Choice Questions and Answers .
This set of Microprocessors Questions and Answers for Freshers focuses on “Instruction Set of
8086/8088 – 3”.
1. The mnemonic that is placed before the arithmetic operation is performed is
a) AAA
b) AAS
c) AAM
d) AAD
Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL.
2. The Carry flag is undefined after performing the operation
a) AAA
b) ADC
c) AAM
d) AAD
Answer: d
Explanation: Since the operation, AAD is performed before division operation is performed, the
carry flag, auxiliary flag and overflow flag are undefined.
3. The instruction that performs logical AND operation and the result of the operation is not
available is
a) AAA
b) AND
c) TEST
d) XOR
Answer: c
Explanation: In the TEST instruction, the logical AND operation is performed and the result is
not stored but flags are affected.
4. In the RCL instruction, the contents of the destination operand undergo function as
a) carry flag is pushed into LSB & MSB is pushed into the carry flag
b) carry flag is pushed into MSB & LSB is pushed into the carry flag
c) auxiliary flag is pushed into LSB & MSB is pushed into the carry flag
d) parity flag is pushed into MSB & LSB is pushed into the carry flag
Answer: a
Explanation: In RCL
Rotaterightthroughcarry
, for each operation, the carry flag is pushed into LSB and the MSB of the operand is pushed
into carry flag.
5. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX
register becomes zero is
a) SCAS
b) REP
c) CMPS
d) STOS
Answer: b
Explanation: The instruction to which the REP is prefix, is executed repeatedly until CX register
becomes zero. When CX becomes zero, the execution proceeds to the next instruction in
sequence.
6. Match the following
A) MOvSB/SW 1) loads AL/AX register by content of a string
B) CMPS 2) moves a string of bytes stored in source to destination
C) SCAS 3) compares two strings of bytes or words whose length is stored in CX register
D) LODS 4) scans a string of bytes or words
a) A-3,B-4,C-2,D-1
b) A-2,B-1,C-4,D-3
c) A-2,B-3,C-1,D-4
d) A-2,B-3,C-4,D-1
Answer: d
Explanation: By using the string instructions, the operations on strings can be performed.
7. The instructions that are used to call a subroutine from the main program and return to the
main program after execution of called function are
a) CALL, JMP
b) JMP, IRET
c) CALL, RET
d) JMP, RET
Answer: c
Explanation: At each CALL instruction, the IP and CS of the next instruction are pushed onto the
stack, before the control is transferred to the procedure. At the end of the procedure, the RET
instruction must be executed to retrieve the stored contents of IP & CS registers from a stack.
8. The instruction that unconditionally transfers the control of execution to the specified address
is
a) CALL
b) JMP
c) RET
d) IRET
Answer: b
Explanation: In this the control transfers to the address specified in the instruction and flags are
not affected by this instruction.
9. Which instruction cannot force the 8086 processor out of ‘halt’ state?
a) Interrupt request
b) Reset
c) Both interrupt request and reset
d) Hold
Answer: d
Explanation: Only an interrupt request or Reset will force the 8086 processor to come out of the
‘halt’ state.
10. NOP instruction introduces
a) Address
b) Delay
c) Memory location
d) None of the mentioned
Answer: b
Explanation: NOP is the No operation. It means that the processor performs no operation for the
clock cycle and thus there exists a delay.
11. Which of the following is not a machine controlled instruction?
a) HLT
b) CLC
c) LOCK
d) ESC
Answer: b
Explanation: Since CLC is a flag manipulation instruction where CLC stands for Clear Carry
Flag.
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Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Assembler Directives and Operators”.
1. The assembler directives which are the hints using some predefined alphabetical strings are
given to
a) processor
b) memory
c) assembler
d) processor & assembler
Answer: c
Explanation: These directives help the assembler to correctly understand the assembly
language programs to prepare the codes.
2. The directive used to inform the assembler, the names of the logical segments to be assumed
for different segments used in the program is
a) ASSUME
b) SEGMENT
c) SHORT
d) DB
Answer: a
Explanation: In ALP, each segment is given a name by using the directive ASSUME
SYNTAX: ASSUME segment:segment_name
Eg: ASSUME CS:Code
here CS is the Code segment and code is the name assumed to the segment.
3. Match the following
a) DB 1) used to direct the assembler to reserve only 10-bytes
b) DT 2) used to direct the assembler to reserve only 4 words
c) DW 3) used to direct the assembler to reserve byte or bytes
d) DQ 4) used to direct the assembler to reserve words
a) a-3, b-2, c-4, d-1
b) a-2, b-3, c-1, d-4
c) a-3, b-1, c-2, d-4
d) a-3, b-1, c-4, d-2
Answer: d
Explanation: These directives are used for allocating memory locations in the available memory.
4. The directive that marks the end of an assembly language program is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
Answer: b
Explanation: The directive END is used to denote the completion of the program.
5. The directive that marks the end of a logical segment is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
Answer: a
Explanation: The directive ENDS is used to end a segment where as the directive END is used
to end the program.
6. The directive that updates the location counter to the next even address while executing a
series of instructions is
a) EVN
b) EVEN
c) EVNE
d) EQU
Answer: b
Explanation: The directive updates location counter to next even address if the current location
counter contents are not even.
7. The directive that directs the assembler to start the memory allotment for a particular
segment/block/code from the declared address is
a) OFFSET
b) LABEL
c) ORG
d) GROUP
Answer: c
Explanation: If an ORG is written then the assembler initiates the location counter to keep the
track of allotted address for the module as mentioned in the directive.
If the directive is not present, then the location counter is initialized to 0000H.
8. The directive that marks the starting of the logical segment is
a) SEG
b) SEGMENT
c) SEG & SEGMENT
d) PROC
Answer: b
Explanation: The directive SEGMENT indicates the beginning of the segment.
9. The recurrence of the numerical values or constants in a program code is reduced by
a) ASSUME
b) LOCAL
c) LABEL
d) EQU
Answer: d
Explanation: In this, the recurring/repeating value is assigned with a label. The label is placed
instead of the numerical value in the entire program code.
10. The labels or constants that can be used by any module in the program is possible when
they are declared as
a) PUBLIC
b) LOCAL
c) GLOBAL
d) Either PUBLIC or GLOBAL
Answer: c
Explanation: The labels, constants, variables, procedures declared as GLOBAL can be used by
any module in the program.
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Questions and Answers .
This set of Microprocessors Technical Interview Questions & Answers focuses on “Do’s and
Don’ts While Using Instructions”.
1. The logic required for implementing a program can be expressed in terms of
a) flowchart
b) algorithm
c) flowchart & algorithm
d) none of the mentioned
Answer: c
Explanation: The logic required for implementing a program must be visualized clearly which is
possible by flowchart and algorithm.
2. The operands, source and destination in an instruction cannot be
a) register, register
b) memory location, memory location
c) memory location, register
d) immediate data, register
Answer: b
Explanation: Only one memory operand can be specified in one instruction.
3. The instruction that is not possible among the following is
a) MOV AX, BX
b) MOV AX, [BX].
c) MOV 55H, BL
d) MOV AL, 55H
Answer: c
Explanation: 8-bit or 16-bit operand cannot be used as a destination operand.
4. The instruction that is not possible among the following is
a) MOV AX, [BX].
b) MOV AX, 5555H
c) MOV AX, [SI].
d) MOV [SI], [DI].
Answer: d
Explanation: Both the operands cannot be memory operands.
5. Both the operands source and destination of an instruction cannot be
a) register, register
b) immediate data, register
c) register, immediate data
d) immediate data, memory location
Answer: c
Explanation: Since destination operand should not be immediate data.
6. The registers that cannot be used as operands for arithmetic and logical instructions are
a) general purpose registers
b) pointers
c) index registers
d) segment registers
Answer: d
Explanation: Segment registers are not allowed as operands for arithmetic and logical
instructions.
7. The operands of an instruction cannot be
a) registers
b) memory operands and immediate operands
c) immediate operands
d) memory operands
Answer: b
Explanation: Both the operands should not be immediate operands and memory operands.
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Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Programming With An Assembler”.
1. The disadvantage of machine level programming is
a) time consuming
b) chances of error are more
c) debugging is difficult
d) all of the mentioned
Answer: d
Explanation: The machine level programming is complicated.
2. The coded object modules of the program to be assembled are present in
a) .ASM file
b) .OBJ file
c) .EXE file
d) .OBJECT file
Answer: b
Explanation: .OBJ file is created with same name as source file and extension .OBJ. It contains
the coded object modules of the program to be assembled.
3. The advantages of assembly level programming are
a) flexibility of programming is more
b) chances of error are less
c) debugging is easy
d) all of the mentioned
Answer: d
Explanation: The assembly level programming is more advantageous than the machine level
programming.
4. The extension that is essential for every assembly level program is
a) .ASP
b) .ALP
c) .ASM
d) .PGM
Answer: c
Explanation: All the files should have the extension, .ASM.
5. The directory that is under work must have the files that are related to
a) Norton’s editor
b) Assembler
c) Linker
d) All of the mentioned
Answer: d
Explanation: Before starting the process of entering a small program on PC, ensure that all the
files namely Norton’s editor, assembler, linker and debugger are available in the same directory
in which work is been done.
6. The listing file is identified by
a) source file name
b) extension .LSF
c) source file name and an extension .LSF
d) source file name and an extension .LST
Answer: d
Explanation: The listing file is automatically generated in the assembly process and is identified
by the entered or source file name and an extension .LST.
7. The extension file that is must for a file to be accepted by the LINK as a valid object file is
a) .OBJ file
b) .EXE file
c) .MASM file
d) DEBUG file
Answer: a
Explanation: The .OBJ extension is a must for a file to be accepted by the LINK as a valid object
file.
8. The listing file contains
a) total offset map of a source file
b) offset address and labels
c) memory allotments for different labels
d) all of the mentioned
Answer: d
Explanation: The listing file contains total offset map of source file including labels, offset
addresses, opcodes, memory allotments for different directives and labels and relocation
information.
9. DEBUG.COM facilitates the
a) debugging
b) trouble shooting
c) debugging and trouble shooting
d) debugging and assembling
Answer: c
Explanation: DEBUG.COM is a DOS utility that facilitates the debugging and trouble shooting.
10. DEBUG is able to troubleshoot only
a) .EXE files
b) .OBJ files
c) .EXE file and .OBJ file
d) .EXE flie and .LST file
Answer: a
Explanation: The DEBUG may be used either to debug a source program or to observe the
results of execution of an .EXE file.
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Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Stack”.
1. The Stack follows the sequence
a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out
Answer: c
Explanation: The stack follows last-in-first-out sequence.
2. If the processor is executing the main program that calls a subroutine, then after executing
the main program up to the CALL instruction, the control will be transferred to
a) address of main program
b) subroutine address
c) address of CALL instruction
d) none of the mentioned
Answer: b
Explanation: Since subroutine is called, to start the execution of the subroutine, the control is
transferred to the subroutine address.
3. The stack is useful for
a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned
Answer: d
Explanation: Stack is used for temporary storage of contents of registers and memory locations,
status of registers.
4. The Stack is accessed using
a) SP register
b) SS register
c) SP and SS register
d) None of the mentioned
Answer: c
Explanation: The stack is accessed using a pointer that is implemented using SP and SS
registers.
5. As the storing of data words onto the stack is increased, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
Answer: d
Explanation: The data is stored from top address of the stack and is decremented by 2.
6. While retrieving data from the stack, the stack pointer is
a) incremented by 1
b) incremented by 2
c) decremented by 1
d) decremented by 2
Answer: b
Explanation: The data in the stack, may again be transferred back from a stack to register. At
that time, the stack pointer is incremented by 2.
7. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into
Answer: c
Explanation: The data is pushed into the stack while loading the stack.
8. The reverse process of transferring the data back from the stack to the CPU register is known
as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack
Answer: d
Explanation: The data retrieved from stack is called popping off.
9. The books arranged one on the other on a table is an example of
a) queue
b) queue and first-in-first out
c) stack
d) stack and last-in-first-out
Answer: d
Explanation: If the books are arranged one on the other, then the book that is placed last will be
the first out.
10. The PID temperature controller using 8086 has
a) data flow
b) data flow and uses queue
c) sequential flow
d) sequential flow and uses stack
Answer: d
Explanation: Since PID temperature controller has steps that need to be sequentially executed
such as sampling the output, conversion of a signal with ADC, finding errors, deriving control
signals and applying the control signal to control flow of energy.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Stack Structure of 8086/8088”.
1. The stack pointer register contains
a) address of the stack segment
b) pointer address of the stack segment
c) offset of address of stack segment
d) data present in the stack segment
Answer: c
Explanation: The stack pointer register contains the offset of the address of the stack segment.
2. The stack segment register contains
a) address of the stack segment
b) base address of the stack segment
c) pointer address of the stack segment
d) data in the stack segment
Answer: b
Explanation: The stack segment register contains base address of the stack segment in the
memory. The stack pointer register
sP
and stack segment register
SS
together address the stack-top.
3. PUSH operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
Answer: a
Explanation: Each PUSH operation decrements the SP
StackPointer
register.
4. POP operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
Answer: b
Explanation: Each POP operation increments the SP
StackPointer
register.
5. The register or memory location that is pushed into the stack at the end must be
a) popped off last
b) pushed off first
c) popped off first
d) pushed off last
Answer: c
Explanation: The data can be retrieved by POP operation and as in stack, the data that is
pushed at the end must be popped off first.
6. In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK
the ASSUME directive directs to the assembler the
a) address of the stack segment
b) pointer address of the stack segment
c) name of the stack segment
d) name of the stack, code and data segments
Answer: d
Explanation: The directive ASSUME facilitates to name the segments with the desired name
that is not a mnemonic or keyword.
7. When a stack segment is initialised then
a) SS and SP are initialised
b) only SS is initialised
c) only SP is initialised
d) SS and SP need not be initialised
Answer: a
Explanation: Though the Stack segment is initialised, the SS and SP pointers must be
initialised.
8. The number of PUSH instructions and POP instructions in a subroutine must be
a) PUSH instructions must be greater than POP instructions
b) POP instructions must be greater than PUSH instructions
c) Both must be equal
d) Instructions may be any kind
Answer: c
Explanation: The number of PUSH instructions must be equal to the number of POP
instructions.
9. 8086 does not support
a) Arithmetic operations
b) logical operations
c) BCD operations
d) Direct BCD packed multiplication
Answer: d
Explanation: The 8086 microprocessor does not support direct BCD packed operations.
10. For 8086 microprocessor, the stack segment may have a memory block of a maximum of
a) 32K bytes
b) 64K bytes
c) 16K bytes
d) NONE
Answer: b
Explanation: In 8086 microprocessor, the memory segments each have a memory of 64K bytes.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interrupts and Interrupt Service Routines”.
1. While CPU is executing a program, an interrupt exists then it
a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
Answer: c
Explanation: An interrupt function is to break the sequence of operation.
2. An interrupt breaks the execution of instructions and diverts its execution to
a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit
Answer: a
Explanation: An interrupt transfers the control to interrupt service routine
ISR
. After executing ISR, the control is transferred back again to the main program.
3. While executing the main program, if two or more interrupts occur, then the sequence of
appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt
Answer: d
Explanation: If an interrupt occurs while executing a program, and the processor is executing
the interrupt, if one more interrupt occurs again, then it is called a nested interrupt.
4. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to
handle them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability
Answer: c
Explanation: The processor if handles more devices as interrupts then it has multiple interrupt
processing ability.
5. NMI stands for
a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none of the mentioned
Answer: a
Explanation: NMI is the acronym for nonmaskable interrupt.
7. If any interrupt request given to an input pin cannot be disabled by any means then the input
pin is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
d) none of the mentioned
Answer: b
Explanation: A nonmaskable interrupt input pin is one which means that any interrupt request at
NMI
nonmaskableinterrupt
input cannot be masked or disabled by any means.
8. The INTR interrupt may be
a) maskable
b) nonmaskable
c) maskable and nonmaskable
d) none of the mentioned
Answer: a
Explanation: the INTR
interruptrequest
is maskable or can be disabled.
9. The Programmable interrupt controller is required to
a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request
Answer: b
Explanation: If more than one interrupt request
INTR
occurs at a time, then an external chip called programmable interrupt controller is required to
handle them.
10. The INTR interrupt may be masked using the flag
a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag
Answer: c
Explanation: If a microprocessor wants to serve any interrupt then interrupt flag, IF=1. If interrupt
flag, IF=0, then the processor ignores the service.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interrupt Cycle of 8086/8088”.
1. If an interrupt is generated from outside the processor then it is an
a) internal interrupt
b) external interrupt
c) interrupt
d) none of the mentioned
Answer: b
Explanation: If an external device or a signal interrupts the processor from outside then it is an
external interrupt.
2. If the interrupt is generated by the execution of an interrupt instruction then it is
a) internal interrupt
b) external interrupt
c) interrupt-in-interrupt
d) none of the mentioned
Answer: a
Explanation: The internal interrupt is generated internally by the processor circuit or by the
execution of an interrupt instruction.
3. Example of an external interrupt is
a) divide by zero interrupt
b) keyboard interrupt
c) overflow interrupt
d) type2 interrupt
Answer: b
Explanation: Since the keyboard is external to the processor, it is an external interrupt.
4. Example of an internal interrupt is
a) divide by zero interrupt
b) overflow interrupt
c) interrupt due to INT
d) all of the mentioned
Answer: d
Explanation: Since the interrupts occur within the processor itself, they are called internal
interrupts.
5. The interrupt request that is independent of IF flag is
a) NMI
b) TRAP
c) Divide by zero
d) All of the mentioned
Answer: d
Explanation: These requests are independent of IF flag.
6. The type of the interrupt may be passed to the interrupt structure of CPU from
a) interrupt service routine
b) stack
c) interrupt controller
d) none of the mentioned
Answer: c
Explanation: After an interrupt is acknowledged, the CPU computes the vector address from the
type of the interrupt that may be passed to the internal structure of the CPU from an interrupt
controller in case of external interrupts.
7. During the execution of an interrupt, the data pushed into the stack is the content of
a) IP
b) CS
c) PSW
d) All of the mentioned
Answer: d
Explanation: The contents of IP, CS and PSW are pushed into the stack during the execution.
8. After every response to the single step interrupt the flag that is cleared is
a) IF
InterruptFlag
b) TF
TrapFlag
c) OF
OverflowFlag
d) None of the mentioned
Answer: b
Explanation: If the trap flag is set then the processor enters the single step execution mode.
After the execution, the trap flag is cleared.
9. At the end of ISR, the instruction should be
a) END
b) ENDS
c) IRET
d) INTR
Answer: c
Explanation: After the execution of the ISR, the control must go to the previous program
maybemainprogram
which was being executed. To execute it, IRET is placed at the end of ISR.
10. When the CPU executes IRET,
a) contents of IP and CS are retrieved
b) the control transfers from ISR to main program
c) clears the trap flag
d) clears the interrupt flag
Answer: a
Explanation: When the instruction IRET is executed, the contents of flags, IP and CS which
were saved at the stack by the CALL instruction are retrieved to the respective registers.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Non Maskable Interrupt and Maskable Interrupt
INTR
”.
1. The interrupt for which the processor has the highest priority among all the external interrupts
is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
Answer: c
Explanation: The Non-Maskable Interrupt input pin has the highest priority among all the
external interrupts.
2. The interrupt for which the processor has highest priority among all the internal interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
Answer: b
Explanation: TRAP is the internal interrupt that has highest priority among all the interrupts
except the Divide By Zero
Type0
exception.
3. In case of string instructions, the NMI interrupt will be served only after
a) initialisation of string
b) execution of some part of the string
c) complete string is manipulated
d) the occurrence of the interrupt
Answer: c
Explanation: When NMI is activated, the current instruction being executed is completed and
then NMI is served. In the case of string instructions, it is served after the complete string is
manipulated.
4. The NMI pin should remain high for atleast
a) 4 clock cycles
b) 3 clock cycles
c) 1 clock cycle
d) 2 clock cycles
Answer: d
Explanation: The NMI pin should remain high for atleast 2 clock cycles and need not be
synchronized with the clock for being sensed.
5. The INTR signal can be masked by resetting the
a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag
Answer: b
Explanation: The INTR signal can be masked by resetting the interrupt flag.
6. For the INTR signal, to be responded to in the next instruction cycle, it must go ________ in
the last clock cycle of the current instruction
a) high
b) low
c) high or low
d) unchanged
Answer: a
Explanation: The INTR signal must go high in the clock cycle of the current instruction in order
to respond in the next instruction cycle.
7. The status of the pending interrupts is checked at
a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle
Answer: d
Explanation: At the end of each instruction, the status of the pending interrupts is checked.
8. Once the processor responds to an INTR signal, the IF is automatically
a) set
b) reset
c) high
d) low
Answer: b
Explanation: The IF is automatically reset when the processor responds to an INTR signal. If the
processor wants to respond to any type of INTR signal further then, the IF should again be set.
9. If the pin LOCK
activelowbased
is low at the trailing edge of the first ALE pulse, then till the start of the next machine cycle, the
pin LOCK
activelow
is
a) low
b) high
c) low or high
d) none of the mentioned
Answer: a
Explanation: The pin LOCK
activelow
remains low till the start of the next machine cycle.
10. With the trailing edge of the LOCK
activelow
, the INTA
activelow
goes low and remains in it for
a) 0 clock cycle
b) 1 clock cycle
c) 2 clock cycles
d) 3 clock cycles
Answer: c
Explanation: The INTA
activelow
goes low and remains low for two clock cycles before returning back to the high state.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Interview Questions and Answers for freshers focuses on “Interrupt
Programming, Passing Parameters to Procedures, Handling Programs of Size More Than
64KB”.
1. The method of defining the interrupt service routine for software is
a) same as that of hardware
b) difficult than hardware
c) easier than software
d) none of the mentioned
Answer: a
Explanation: For both software and hardware, the method of defining the interrupt service
routine is the same.
2. While programming for any type of interrupt, the interrupt vector table is set
a) externally
b) through a program
c) either externally or through the program
d) externally and through the program
Answer: c
Explanation: The programmer must, either externally or through the program, set the interrupt
vector table for that type preferably with the CS and IP addresses of the interrupt service
routine.
3. To execute a program one should
a) assemble the program
b) link the program
c) apply external pulse
d) all of the mentioned
Answer: d
Explanation: To execute a program, first assemble it, link it and then execute it. After execution,
a new file RESULT is created in the directory. Then external pulse is applied to IRQ2 pin, and
this will again cause the execution of ISR into the file.
4. Procedures are also known as
a) macros
b) segment
c) subroutines
d) none
Answer: c
Explanation: Procedures are also known as subroutines.
5. Procedures, for their execution, require
a) input data
b) output data
c) constants
d) input data or constants
Answer: d
Explanation: Procedures require input data or constants for their execution. Their data or
constants may be passed to the subroutine by the main program.
6. The technique that is used to pass the data or parameter to procedures in assembly
language program is by using
a) global declared variable
b) registers
c) stack
d) all of the mentioned
Answer: d
Explanation: The techniques that are used to pass the data or parameter to procedures are by
using global declared variable, registers of CPU, memory locations, stack, PUBLIC & EXTRN.
7. If a procedure is interactive, then
a) it accepts inputs directly from input devices
b) it uses global declared variable technique
c) it uses stack
d) it uses memory locations
Answer: a
Explanation: If a procedure is interactive, then it accepts the inputs directly from input devices.
8. For passing the parameters to procedures using the PUBLIC & EXTRN directives, it must be
declared PUBLIC in the
a) subroutine
b) procedure
c) main routine
d) main routine and subroutine
Answer: c
Explanation: For passing the parameters to procedures, it must be declared PUBLIC in the main
routine and the same should be declared EXTRN in the procedure.
9. The technique to estimate the size of an executable program, before it is assembled and
linked is
a) memory location technique
b) global variable technique
c) stack
d) none
Answer: d
Explanation: There is no technique to estimate the size of an executable program before it is
assembled and linked.
10. To estimate the size of an executable program before it is assembled and linked, the
programming methodology concerned is by writing
a) programs with more than one segment for data and code
b) programs with FAR subroutines each of size up to 64KB
c) programs with more than one segment for stack
d) all of the mentioned
Answer: d
Explanation: By writing programs with more than one segment for data, code or stack or by
writing programs with FAR subroutines each of size 64KB, the size of an executable program
can be estimated.
To practice all areas of Microprocessors for Interviews, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Macros”.
1. If a number of instructions are repeating through the main program, then to reduce the length
of the program, __________ is used.
a) procedure
b) subroutine
c) macro
d) none of the mentioned
Answer: c
Explanation: For a certain number of instructions that are repeated in the main program, when
macro is defined then the code of a program is reduced by placing the name of the macro at
which the set of instructions are needed to be repeated.
2. The process of assigning a label or macroname to the string is called
a) initialising macro
b) initialising string macro
c) defining a string macro
d) defining a macro
Answer: d
Explanation: The process of assigning a label to the string is called defining a macro.
3. A macro within a macro is called
a) macro-within-macro
b) nested macro
c) macro-in-macro
d) none of the mentioned
Answer: b
Explanation: A macro may be called from inside a macro. This type of macro is called nested
macro.
4. A macro can be defined as
a) beginning of a program
b) end of a program
c) after initialisation of program
d) anywhere in a program
Answer: d
Explanation: A macro can be defined anywhere in a program.
5. A macro can be used as ________
a) in data segment
b) to represent directives
c) to represent statements
d) all of the mentioned
Answer: d
Explanation: A macro may be used in data segment and can also be used to represent
statements and directives.
6. The end of a macro can be represented by the directive.
a) END
b) ENDS
c) ENDM
d) ENDD
Answer: c
Explanation: The ENDM directive marks the end of the instructions or statements sequence
assigned with the macro name.
7. Inserting the statements and instructions represented by macro, directly at the place of the
macroname, in the program, is known as
a) calling a macro
b) inserting a macro
c) initializing a macro
d) none of the mentioned
Answer: a
Explanation: Inserting the statements and instructions at the place of macroname, in the
program, is known as calling a macro.
8. The time required for execution of a macro is ________ that of the procedure.
a) greater than
b) less than
c) equal to
d) none of the mentioned
Answer: b
Explanation: The time required for execution of a macro is less than that of procedure as it does
not contain CALL and RET instructions as the procedures do.
9. Which of the following statements is incorrect?
a) complete code of instruction string is inserted at each place, wherever the macroname
appears
b) macro requires less time of execution than that of procedure
c) macro uses stack memory
d) macroname can be anything except registers and mnemonics
Answer: c
Explanation: Macro does not require stack memory and hence has less time for execution.
10. The beginning of the macro can be represented as
a) START
b) BEGIN
c) MACRO
d) None of the mentioned
Answer: c
Explanation: The beginning of the macro is represented as macroname followed by the directive
MACRO.
SYNTAX: macroname MACRO
EXAMPLE: STRINGS MACRO.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Timings and Delays”.
1. If ‘n’ denotes the number of clock cycles and ‘T’ denotes period of the clock at which the
microprocessor is running, then the duration of execution of loop once can be denoted by
a) n+T
b) n-T
c) n*T
d) n/T
Answer: c
Explanation: The duration of execution of the loop is the product of number of clock cycles and
the period of the clock cycle at which microprocessor is running.
2. The number of instructions actually executed by the microprocessor depends on the
a) stack
b) loop count
c) program counter
d) time duration
Answer: b
Explanation: As the microprocessor executes each instruction corresponding loop counter value
decreases and the microprocessor executes the instructions till the loop counter becomes zero.
3. In case of subroutines, the actual number of instructions executed by the processor depends
on
a) loop count
b) length of interrupt service routine
c) length of procedure
d) none
Answer: c
Explanation: In case of subroutines or interrupt service routines, the number of instructions
executed by the processor depends on the length of procedure
orsubroutine
or length of interrupt service routine along with the main calling program.
4. The step included in generating delays is
a) determining exact required delay
b) selecting instructions for delay loop
c) finding period of clock frequency
d) all of the mentioned
Answer: d
Explanation: The delays can be generated step wise.
5. The Count, N can be defined as
a) required delay/duration for execution
b) duration of execution/required delay
c) required delay/number of clock cycles
d) required delay/period of clock frequency
Answer: a
Explanation: The count N can be defined as the required time delay by the duration for
execution of the loop once.
Count, N = required delay
Td
/duration for execution of the loop once
n∗T
.
6. In the instruction set,
MOV CX, BA03H
WAIT: DEC CX
NOP
JNZ WAIT
RET
if the zeroth condition is satisfied then, for execution, the JNZ instruction takes
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
Answer: d
Explanation: The JNZ instruction takes only 4 clock cycles if the zeroth condition is satisfied.
7. In the instruction set,
MOV CX, BA03H
WAIT: DEC CX
NOP
JNZ WAIT
RET
if the zeroth condition is not satisfied, then the JNZ instruction takes
a) 2 clock cycles
b) 8 clock cycles
c) 16 clock cycles
d) 64 clock cycles
Answer: c
Explanation: The JNZ instruction takes 16 clock cycles if the zeroth condition is not satisfied.
8. The maximum count value of 16-bit count register puts a limitation on
a) memory usage
b) storage of address of registers
c) to generate clock pulse
d) to generate maximum delay
Answer: d
Explanation: The maximum count value of 16-bit count register is FFFFH. This may put the
limitation on the maximum delay that can be generated using the instructions.
9. When large delays are required, then to serve the purpose
a) one or more count registers can be used
b) one or more shift registers can be used
c) one or more pointer registers can be used
d) one or more index registers can be used
Answer: a
Explanation: One or more count registers can be used to serve large delays.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Semiconductor Memory Interfacing”.
1. The semiconductor memories are organised as __________ dimension
of array of memory locations.
a) one dimensional
b) two dimensional
c) three dimensional
d) none
Answer: b
Explanation: The semiconductor memories are organised as two dimensions of an array which
consists of rows and columns.
2. If a location is selected, then all the bits in it are accessible using a group of conductors called
a) control bus
b) address bus
c) data bus
d) either address bus or data bus
Answer: c
Explanation: The bits in a selected location are accessible using data bus.
3. To address a memory location out of N memory locations, the number of address lines
required is
a) log N
tothebase2
b) log N
tothebase10
c) log N
tothebasee
d) log
2N
tothebasee
Answer: a
Explanation: For n memory locations, log n
tothebaseof2
address lines are required. For addressing 4K bytes of memory, 12 address lines are required
since log
4KB
=log
4∗1024
=log(2 12 )=12.
4. If the microprocessor has 10 address lines, then the number of memory locations it is able to
address is
a) 512
b) 1024
c) 2048
d) none
Answer: b
Explanation: Since for n address lines, the number of memory locations able to address is 2^n.
5. In static memory, the upper 8-bit bank of an available 16-bit memory chip is called
a) upper address memory bank
b) even address memory bank
c) static upper memory
d) odd address memory bank
Answer: d
Explanation: In static memory, the upper 8-bit bank is called odd address memory bank.
6. In static memory, the lower 8-bit bank of an available 16-bit memory chip is called
a) lower address memory bank
b) even address memory bank
c) static lower memory bank
d) odd address memory bank
Answer: b
Explanation: In static memory, the lower 8-bit bank is called even address memory bank.
7. In most of the cases, the method used for decoding that may be used to minimise the
required hardware is
a) absolute decoding
b) non-linear decoding
c) linear decoding
d) none
Answer: c
Explanation: In general, linear decoding is used to minimise the required hardware.
8. To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
a) parallel
b) serial
c) both serial and parallel
d) neither serial nor parallel
Answer: a
Explanation: The two 4K*8 chips of RAM and ROM are arranged in parallel.
9. If
addressline
Ao=0 then, the status of address and memory are
a) address is even and memory is in ROM
b) address is odd and memory is in ROM
c) address is even and memory is in RAM
d) address is odd and memory is in RAM
Answer: c
Explanation: If Ao=0 then address is even and is in RAM. If Ao=1 then, address is odd and is in
RAM.
10. If at a time Ao and BHE
activelow
both are zero then, the chip
selected will be
a) RAM
b) ROM
c) RAM and ROM
d) ONLY RAM
Answer: c
Explanation: If at a time Ao and BHE
activelow
both are zero, then both RAM and ROM are selected.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Dynamic RAM Interfacing”.
1. The advantage of dynamic RAM is
a) high packing density
b) low cost
c) less power consumption
d) all of the mentioned
Answer: d
Explanation: The dynamic RAM is advantageous than the static RAM as it has a higher packing
density, lower cost and less power consumption.
2. Whenever a large memory is required in a microcomputer system, the memory subsystem is
generally designed using
a) Static RAM
b) Dynamic RAM
c) Both static and dynamic RAM
d) ROM
Answer: b
Explanation: Dynamic RAM is preferred for large memory.
3. If a typical static RAM cell requires 6 transistors then corresponding dynamic RAM requires
a) 1 transistor along with capacitance
b) 2 transistors along with resistance
c) 3 transistors along with diode
d) 2 transistors along with capacitance
Answer: a
Explanation: The hardware complexity of dynamic RAM is lesser than that of static RAM.
4. To store the charge as a representation of data, the basic dynamic RAM cell uses
a) resistor
b) capacitor
c) diode
d) transistor
Answer: c
Explanation: The basic dynamic RAM cell uses capacitance to store the charge as a
representation of data. This capacitor is manufactured as a diode that is reverse biased so that
the storage capacitance is obtained.
5. The process of refreshing the data in the RAM to reduce the possibility of data loss is known
as
a) data cycle
b) regain cycle
c) retain cycle
d) refresh cycle
Answer: d
Explanation: The data storage in RAM which is capacitance
reverse−biaseddiode
may have a leakage current that tends to discharge the capacitor giving rise to possibility of
data loss. To avoid this, the data must be refreshed after a fixed time interval regularly.
6. The field in which dynamic RAM is more complicated than static RAM is
a) complexity
b) interfacing circuit
c) execution unit
d) cost
Answer: b
Explanation: The refresh mechanism and the additional hardware required makes the
interfacing circuit of dynamic RAM more complicated than that of static RAM.
7. Memory refresh activity is
a) initialised by processor
b) initialised by external bus master
c) initialised by refresh mechanism
d) initialised either by processor or by external bus
Answer: c
Explanation: The refresh operation is independent regular activity that is initialised and carried
out by the refresh mechanism.
8. The number of memory chips that are enabled at a time for refresh activity is
a) 2
b) 4
c) 8
d) more than 1
Answer: d
Explanation: More than one memory chip can be enabled at a time to refresh activity to reduce
the number of total memory refresh cycles.
9. A timer that derives pulse for refreshing action or time for which a dynamic RAM cell can hold
data charge level practically constant is
a) constant timer
b) data managing timer
c) refresh timer
d) qualitative timer
Answer: c
Explanation: Refresh timer derives a pulse for refreshing action after each refresh interval which
can be qualitatively defined as the time for which a dynamic RAM cell can hold data charge
level practically constant.
10. If ‘n’ denotes the number of rows that are to be refreshed in a single refresh interval, ‘td’
denotes the range of time it may take then, refresh time
tr
can be defined as
a) n*td
b) td/n
c) n/td
d) td n
Answer: b
Explanation: Refresh time is the ratio of time duration taken for refreshing to the number of rows
that are refreshed. Refresh frequency is the reciprocal of refresh time.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interfacing I/O Ports”.
1. The device that enables the microprocessor to read data from the external devices is
a) printer
b) joystick
c) display
d) reader
Answer: b
Explanation: Since joystick is an input device, it reads data from the external devices.
2. The example of output device is
a) CRT display
b) 7-segment display
c) Printer
d) All of the mentioned
Answer: d
Explanation: The output device transfers data from the microprocessor to the external devices.
3. The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read
Answer: c
Explanation: The input activity is similar to read operation and the output activity is similar to
write operation.
4. The operation, IOWR
activelow
performs
a) write operation on input data
b) write operation on output data
c) read operation on input data
d) read operation on output data
Answer: b
Explanation: IOWR
activelow
operation means writing data to an output device and not an input device.
5. The latch or IC 74LS373 acts as
a) good input port
b) bad input port
c) good output port
d) bad output port
Answer: c
Explanation: If the output port is to source large currents, the port lines must be buffered. So,
the latch is used as it acts as a good output port.
6. While performing read operation, one must take care that much current should not be
a) sourced from data lines
b) sinked from data lines
c) sourced or sinked from data lines
d) sinked from address lines
Answer: c
Explanation: More current should not be sourced or sinked from data lines while reading to
avoid loading.
7. To avoid loading during read operation, the device used is
a) latch
b) flipflop
c) buffer
d) tristate buffer
Answer: d
Explanation: A tristate buffer is used as an input device to overcome loading.
8. The chip 74LS245 is
a) bidirectional buffer
b) 8-bit input port
c) one that has 8 buffers
d) all of the mentioned
Answer: d
Explanation: The chip 74LS245 is a bidirectional buffer that contains 8 buffers and may be used
as an 8-bit input port. But while using as an input device, only one direction is useful.
9. In 74LS245, if DIR is 1, then the direction is from
a) inputs to outputs
b) outputs to inputs
c) source to sink
d) sink to source
Answer: a
Explanation: If DIR is 1, then the direction is from A
inputs
to B
outputs
.
10. In memory-mapped scheme, the devices are viewed as
a) distinct I/O devices
b) memory locations
c) only input devices
d) only output devices
Answer: b
Explanation: In memory-mapped scheme, the devices are viewed as memory locations and are
addressed likewise.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “PIO 8255
ProgrammableInput–OutputPort
”.
1. Programmable peripheral input-output port is another name for
a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port
Answer: b
Explanation: The parallel input-output port chip 8255 is also known as programmable peripheral
input-output port.
2. Port C of 8255 can function independently as
a) input port
b) output port
c) either input or output ports
d) both input and output ports
Answer: c
Explanation: Port C can function independently either as input or as output ports.
3. All the functions of the ports of 8255 are achieved by programming the bits of an internal
register called
a) data bus control
b) read logic control
c) control word register
d) none of the mentioned
Answer: c
Explanation: By programming the bits of control word register, the operations of the ports are
specified.
4. The data bus buffer is controlled by
a) control word register
b) read/write control logic
c) data bus
d) none of the mentioned
Answer: b
Explanation: The data bus buffer is controlled by read/write control logic.
5. The input provided by the microprocessor to the read/write control logic is
a) RESET
b) A1
c) WR
ACTIVELOW
d) All of the mentioned
Answer: d
Explanation: RD
ACTIVELOW
, WR
ACTIVELOW
, A1, A0, RESET are the inputs provided by the microprocessor to the read/write control logic of
8255.
6. The device that receives or transmits data upon the execution of input or output instructions
by the microprocessor is
a) control word register
b) read/write control logic
c) 3-state bidirectional buffer
d) none of the mentioned
Answer: c
Explanation: 3-state bidirectional buffer is used to receives or transmits data upon the execution
of input or output instructions by the microprocessor.
7. The port that is used for the generation of handshake lines in mode 1 or mode 2 is
a) port A
b) port B
c) port C Lower
d) port C Upper
Answer: d
Explanation: Port C upper is used for the generation of handshake lines in mode 1 or mode 2.
8. If A1=0, A0=1 then the input read cycle is performed from
a) port A to data bus
b) port B to data bus
c) port C to data bus
d) CWR to data bus
Answer: b
Explanation: If A1=0, A0=1 then the input read cycle is performed from port B to data bus.
9. The function, ‘data bus tristated’ is performed when
a) CS
activelow
=1
b) CS
activelow
=0
c) CS
activelow
= 0, RD
activelow
= 1, WR
activelow
=1
d) CS
activelow
= 1 OR CS
activelow
= 0, RD
activelow
= 1, WR
activelow
=1
Answer: d
Explanation: The data bus is tristated when chip select pin=1 or chip select pin=0 and read and
write signals are high i.e 1.
10. The pin that clears the control word register of 8255 when enabled is
a) CLEAR
b) SET
c) RESET
d) CLK
Answer: c
Explanation: If reset pin is enabled then the control word register is cleared.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Modes of Operation of 8255”.
1. In the I/O mode, the 8255 ports work as
a) reset pins
b) set pins
c) programmable I/O ports
d) only output ports
Answer: c
Explanation: In the I/O mode, the 8255 ports work as programmable I/O ports.
2. In BSR mode, only port C can be used to
a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports
Answer: c
Explanation: In BSR
BitSet−Reset
Mode, port C can be used to set and reset its individual port bits.
3. The feature of mode 0 is
a) any port can be used as input or output
b) output ports are latched
c) maximum of 4 ports are available
d) all of the mentioned
Answer: d
Explanation: In mode 0, any port can be used as input or output and output ports are latched.
4. The strobed input/output mode is another name of
a) mode 0
b) mode 1
c) mode 2
d) none
Answer: b
Explanation: In this mode, the handshaking signals control the input or output action of the
specified port.
5. If the value of the pin STB
StrobeInput
falls to low level, then
a) input port is loaded into input latches
b) input port is loaded into output latches
c) output port is loaded into input latches
d) output port is loaded into output latches
Answer: a
Explanation: If the value of the pin STB
StrobeInput
falls to low level, the input port is loaded into input latches.
6. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of
a) Control word register
b) CPU
c) Printer
d) Ports
Answer: c
Explanation: This signal indicates that the printer is selected.
7. The pulse width of the signal INIT at the receiving terminal must be more than
a) 10 microseconds
b) 20 microseconds
c) 40 microseconds
d) 50 microseconds
Answer: d
Explanation: The pulse width of the signal must be more than 50microseconds at the receiving
terminal.
8. The level of the signal ERROR
activelow
becomes ‘low’ when the printer is in
a) Paper end state
b) Offline state
c) Error state
d) All of the mentioned
Answer: d
Explanation: The level of the signal ERROR
activelow
becomes ‘low’ when the printer is in the Paper end state, Offline state and Error state.
9. The signals that are provided to maintain proper data flow and synchronization between the
data transmitter and receiver are
a) handshaking signals
b) control signals
c) input signals
d) none
Answer: a
Explanation: Handshaking signals maintain proper data flow and synchronization.
10. The feature of mode 2 of 8255 is
a) single 8-bit port is available
b) both inputs and outputs are latched
c) port C is used for generating handshake signals
d) all of the mentioned
Answer: d
Explanation: In mode 2 of 8255, a single 8-bit port is available i.e group A.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Puzzles focuses on “Interfacing Analog to Digital Data Converters”.
1. The time taken by the ADC from the active edge of SOC
startofconversion
pulse till the active edge of EOC
endofconversion
signal is called
a) edge time
b) conversion time
c) conversion delay
d) time delay
Answer: c
Explanation: Broadly speaking, the time taken by the converter to calculate the equivalent digital
data output from the moment of the start of conversion is called conversion delay.
2. The popular technique that is used in the integration of ADC chips is
a) successive approximation
b) dual slope integration
c) successive approximation and dual slope integration
d) none
Answer: c
Explanation: Successive approximation and dual slope integration are the most popular
techniques that are used in the integrated ADC chips.
3. The procedure of algorithm for interfacing ADC contain
a) ensuring stability of analog input
b) issuing start of conversion pulse to ADC
c) reading digital data output of ADC as equivalent digital output
d) all of the mentioned
Answer: d
Explanation: The general algorithm for interfacing ADC contains ensuring the stability of analog
input, issuing start of conversion pulse to ADC, reading end of conversion signal to mark the
end of a conversion process, reading digital data output of ADC as equivalent digital output.
4. Which is the ADC among the following?
a) AD 7523
b) 74373
c) 74245
d) ICL7109
Answer: d
Explanation: AD 7523 is a DAC
Digitaltoanalogconverter
, 74373 is a latch, 74245 is transceiver and ICL7109 is an ADC.
5. The conversion delay in a successive approximation of an ADC 0808/0809 is
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 milliseconds
Answer: b
Explanation: The conversion delay is 100microseconds which is low as compared to other
converters.
6. The number of inputs that can be connected at a time to an ADC that is integrated with
successive approximation is
a) 4
b) 2
c) 8
d) 16
Answer: c
Explanation: As these converters internally have 3:8 analog multiplexer, at a time 8 different
analog inputs can be connected to the chip.
7. ADC 7109 integrated by Dual slope integration technique is used for
a) low cost option
b) slow practical applications
c) low complexity
d) all of the mentioned
Answer: d
Explanation: Compared to other 12-bit ADCs, it is of very low cost and useful for slow practical
applications.
8. Which of the following is not one of the phases of the total conversion cycle?
a) autozero phase
b) conversion phase
c) signal integrate phase
d) disintegrate phase
Answer: b
Explanation: Autozero phase, signal integrate phase and disintegrate phase are the three
phases of total conversion cycle.
9. Which of the following phase contain feedback loop in it?
a) autozero phase
b) signal integrate phase
c) disintegrate phase
d) none
Answer: a
Explanation: A feedback loop is closed around the system to charge the autozero capacitor to
compensate for the offset voltages in the buffer amplifier, integrator and comparator.
10. In the signal integrate phase, the differential input voltage between IN LO
inputlow
and IN HI
inputhigh
pins is integrated by the internal integrator for a fixed period of
a) 256 clock cycles
b) 1024 clock cycles
c) 2048 clock cycles
d) 4096 clock cycles
Answer: c
Explanation: The internal integrator needs 2048 clock cycles to integrate voltage difference
between input low and input high.
To practice all Puzzles on Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Questions and Answers for Experienced people focuses on
“Interfacing Digital to Analog Converters, Stepper Motor Interfacing and Control of High Power
Devices Using 8255”.
1. DAC
DigitaltoAnalogConverter
finds application in
a) digitally controlled gains
b) motor speed controls
c) programmable gain amplifiers
d) all of the mentioned
Answer: d
Explanation: DAC is used in digitally controlled gains, motor speed controls and programmable
gain amplifiers.
2. To save the DAC from negative transients the device connected between OUT1 and OUT2 of
AD 7523 is
a) p-n junction diode
b) Zener
c) FET
d) BJT
BipolarJunctiontransistor
Answer: b
Explanation: Zener is connected between OUT1 and OUT2 pins of AD7523 to save from
negative transients.
3. An operational amplifier connected to the output of AD 7523 is used
a) to convert current output to output voltage
b) to provide additional driving capability
c) as current-to-voltage converter
d) all of the mentioned
Answer: d
Explanation: An operational amplifier is used as a current-to-voltage converter to convert the
current output to output voltage and also provides additional driving capability to the DAC.
4. The DAC 0800 has a settling time of
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 microseconds
Answer: a
Explanation: DAC 0800 has a settling time of 100 milliseconds.
5. The device that is used to obtain an accurate position control of rotating shafts in terms of
steps is
a) DC motor
b) AC motor
c) Stepper motor
d) Servo motor
Answer: c
Explanation: Stepper motor employs rotation of its shaft in terms of steps, rather than
continuous rotation as in case of AC or DC motors.
6. The internal schematic of a typical stepper motor has
a) 1 winding
b) 2 windings
c) 3 windings
d) 4 windings
Answer: d
Explanation: The internal schematic of a typical stepper motor has 4 windings.
7. The number of pulses required for one complete rotation of the shaft of the stepper motor is
equal to the
a) number of internal teeth on a rotor
b) number of internal teeth on a stator
c) number of internal teeth on a rotor and stator
d) number of external teeth on a stator
Answer: a
Explanation: The number of pulses required for one complete rotation of the shaft of the stepper
motor is equal to the number of internal teeth on its rotor.
8. A simple scheme for rotating the shaft of a stepper motor is called
a) rotating scheme
b) shaft scheme
c) wave scheme
d) none
Answer: c
Explanation: In this scheme, the windings are applied with the required voltage pulses, in a
cyclic fashion.
9. The firing angles of thyristors are controlled by
a) pulse generating circuits
b) relaxation oscillators
c) microprocessor
d) all of the mentioned
Answer: d
Explanation: In early days, the firing angles were controlled by a pulse generating circuits like
relaxation oscillators and now, they are accurately fired using a microprocessor.
10. The Isolation transformers are generally used for
a) protecting low power circuit
b) isolation
c) protecting low power circuit and isolation
d) none
Answer: c
Explanation: Any switching component of a high power circuit may be sufficient to damage the
microprocessor system. So, to protect the low power circuit isolation transformers are used.
They are also used if isolation is necessary.
To practice all areas of Microprocessors for Experienced people, here is complete set of 1000+
Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Programmable Interval Timer 8254”.
1. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: There are three counters that can be used as either counters or delay generators.
2. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
Answer: b
Explanation: The control word register can only be written and cannot be read.
3. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3
Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.
4. In mode 2, if N is loaded as the count value, then after
N−1
cycles, the output becomes low for
a) 1 clockcycle
b) 2 clockcycles
c) 3 clockcycles
d) 4 clockcycles
Answer: a
Explanation: After
N−1
cycles, the output becomes low for only 1 clockcycle. If the count N is reloaded and again the
output becomes high and remains so for
N−1
clock pulses.
5. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Answer: c
Explanation: When the count N loaded is even, then for half of the count, the output remains
high and for the remaining half it remains low. If the count loaded is odd, the first clock pulse
decrements it by 1 resulting in an even count value.
6. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
Answer: b
Explanation: SC denotes select counter.
7. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.
8. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is BCD count.
9. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.
10. The control word register contents are used for
a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes
mode0−mode4
ii) selection of counters
counter0−counter2
iii) choosing binary or BCD counters
iv) loading of the counter registers.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Programmable Interrupt Controller 8259A”.
1. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7
Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these five, four pins
were alloted fixed vector addresses but the pin INTR was not alloted by vector address, rather
an external device was supposed to hand over the type of the interrupt to the microprocessor.
2. The register that stores all the interrupt requests in it in order to serve them one by one on a
priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request Register
internally.
3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR
InterruptRequestRegister
at the direction of the Priority Resolver.
4. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
Answer: d
Explanation: The interrupt control logic performs all the operations that are involved within the
interrupts like accepting and managing interrupt acknowledge signals, interrupts.
5. In a cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64 vectored
interrupts can be provided.
6. When the PS
activelow
/EN
activelow
pin of 8259A used in buffered mode, then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a buffer enable to
control buffer transreceivers. If it is not used in buffered mode, then the pin is used as input to
designate whether the chip is used as a master or a slave.
7. Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
Answer: d
Explanation: The initialization procedure involves
i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.
8. When non-specific EOI command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will automatically reset the
highest ISR.
9. In the application where all the interrupting devices are of equal priority, the mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
Answer: a
Explanation: The automatic rotation is used in the applications where all the interrupting devices
are of equal priority.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “the Keyboard/Display Controller 8279”.
1. The registers that store the keyboard and display modes and operations programmed by
CPU are
a) I/O control and data buffers
b) Control and timing registers
c) Return buffers
d) Display address registers
Answer: b
Explanation: The control and timing register to store the keyboard and display modes and other
operations programmed by CPU.
2. The sensor RAM acts as 8-byte first-in-first-out RAM in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
Answer: c
Explanation: In this mode, each key code of the pressed key is entered in the order of the entry,
and in the meantime, read by the CPU, till the RAM becomes empty.
3. The registers that hold the address of the word currently being written by the CPU from the
display RAM are
a) control and timing register
b) control and timing register and timing control
c) display RAM
d) display address registers
Answer: d
Explanation: The display address registers holds the address of the word currently being written
or read by the CPU to or from the display RAM.
4. When a key is pressed, a debounce logic comes into operation in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Answer: c
Explanation: In scanned keyboard mode with 2 key lockout mode of operation, when a key is
pressed, a debounce logic comes into operation. During the next two scans, other keys are
checked for closure and if no other key is pressed then the first pressed key is identified.
5. The mode that is programmed using “end interrupt/error mode set command” is
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Answer: a
Explanation: The scanned keyboard special error mode is programmed using end interrupt/error
mode set command. This mode is valid only under the N-key rollover mode.
6. When a key is pressed, the debounce circuit waits for 2 keyboard scans and then checks
whether the key is still depressed in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Answer: b
Explanation: In this mode, When a key is pressed, the debounce circuit waits for 2 keyboard
scans and then checks whether the key is still depressed. If it is still depressed, the code is
entered in FIFO RAM.
7. The data that is entered from the left side of the display unit is of
a) left entry mode
b) right entry mode
c) left and right entry modes
d) none
Answer: a
Explanation: The data that is entered from the left side of the display unit is of left entry mode,
as in a type-writer the first character typed appears at the left-most position, while the
subsequent characters appear successively to the right of the first one.
8. The FIFO status word is used to indicate the error in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
Answer: c
Explanation: Overrun error occurs when an already full FIFO has attempted an entry. Underrun
error occurs when an empty FIFO read is attempted.
9. The flag that increments automatically after each read or write operation to the display RAM
is
a) IF
b) RF
c) AI
d) WF
Answer: c
Explanation: AI refers to auto increment flag.
10. If any change in sensor value is detected at the end of a sensor matrix scan, then the IRQ
line
a) goes low
b) goes high
c) remains unchanged
d) none
Answer: b
Explanation: In sensor matrix mode, the IRQ line goes high, if any change in sensor value is
detected at the end of a sensor matrix scan or the sensor RAM has a previous entry to be read
by the CPU.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Programmable Communication Interface 8251 USART”.
1. Which of the following is not a mode of data transmission?
a) simplex
b) duplex
c) semi duplex
d) half duplex
Answer: c
Explanation: Basically, there are three modes of data transmission. simplex, duplex and half
duplex.
2. If the data is transmitted only in one direction over a single communication channel, then it is
of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: a
Explanation: In simplex mode, the data transmission is unidirectional. For example, a CPU may
transmit data for a CRT display unit in this mode.
3. If the data transmission takes place in either direction, but at a time data may be transmitted
only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: d
Explanation: In half duplex mode, data transmission is bidirectional but not at a time. For
example, Walkie-Talkie.
4. In 8251A, the pin that controls the rate at which the character is to be transmitted is
a) TXC
activelow
b) TXC
activehigh
c) TXD
activelow
d) RXC
activelow
Answer: a
Explanation: Transmitter Clock Input
TXC(activelow
) is a pin that controls the rate at which the character is to be transmitted.
5. TXD
TransmittedDataOutput
pin carries serial stream of the transmitted data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned
Answer: d
Explanation: Transmitted Data Output pin carries a serial stream of the transmitted data bits
along with other information like start bits, stop bits and parity bits etc.
6. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY
Transmitterready
b) RXRDY
Receiverreadyoutput
c) DSR
activelow
d) DTR
activelow
Answer: b
Explanation: RXRDY
Receiverreadyoutput
may be used either to interrupt the CPU or polled by the CPU.
7. The disadvantage of RS-232C is
a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned
Answer: d
Explanation: RS232C has been used for long and has a few disadvantages like limited speed of
communication, high-voltage level signaling and big-size communication adapters.
8. The USB supports the signaling rate of
a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned
Answer: d
Explanation: The USB standards support the signaling rates. Also, USB signaling is
implemented in a differential in low- and full-speed options.
9. The bit packet that commands the device either to receive data or transmit data in
transmission of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
Answer: b
Explanation: The token packet is the second type of packet which commands the device either
to receive data or transmit data.
10. High speed USB devices neglect
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
Answer: c
Explanation: PRE packets are only of importance to low-speed USB devices.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “DMA Controller 8257”.
1. In direct memory access mode, the data transfer takes place
a) directly
b) indirectly
c) directly and indirectly
d) none of the mentioned
Answer: a
Explanation: In direct memory access mode, the data may transfer directly without the
interference from the CPU.
2. In 8257
DMA
, each of the four channels has
a) a pair of two 8-bit registers
b) a pair of two 16-bit registers
c) one 16-bit register
d) one 8-bit register
Answer: b
Explanation: The DMA supports four channels, and each of the channels has a pair of two 16-bit
registers, namely DMA address register and a terminal count register.
3. The common register
for all the four channels of 8257 is
a) DMA address register
b) Terminal count register
c) Mode set register and status register
d) None of the mentioned
Answer: c
Explanation: The two common registers for all the four channels of DMA are mode set register
and status register.
4. In 8257 register format, the selected channel is disabled after the terminal count condition is
reached when
a) Auto load is set
b) Auto load is reset
c) TC STOP bit is reset
d) TC STOP bit is set
Answer: d
Explanation: If the TC STOP bit is set, the selected channel is disabled after the terminal count
condition is reached, and it further prevents any DMA cycle on the channel.
5. The IOR
activelow
input line acts as output in
a) slave mode
b) master mode
c) master and slave mode
d) none of the mentioned
Answer: b
Explanation: The IOR
activelow
is an active low bidirectional tristate input line, that acts as input in the slave mode, and acts as
output in the master mode. In master mode, this signal is used to read data from a peripheral
during a memory write cycle.
6. The IOW
activelow
in its slave mode loads the contents of a data bus to
a) 8-bit mode register
b) upper/lower byte of 16-bit DMA address register
c) terminal count register
d) all of the mentioned
Answer: d
Explanation: In its slave mode, the IOW
activelow
loads the contents of a data bus to 8-bit mode register, upper/lower byte of 16-bit DMA address
register or terminal count register.
7. The pin that disables all the DMA channels by clearing the mode registers is
a) MARK
b) CLEAR
c) RESET
d) READY
Answer: c
Explanation: The RESET pin which is asynchronous input disables all the DMA channels by
clearing the mode registers, and tristate all the control lines.
8. The pin that requests the access of the system bus is
a) HLDA
b) HRQ
c) ADSTB
d) None of the mentioned
Answer: b
Explanation: The hold request output requests the access of the system bus.
9. The pin that is used to write data to the addressed memory location, during DMA write
operation is
a) MEMR
activelow
b) AEN
c) MEMW
activelow
d) IOW
activelow
Answer: c
Explanation: The MEMW
activelow
is used to write data to the addressed memory location, during DMA write operation.
10. The pin that strobes the higher byte of the memory address, generated by the DMA
controller into the latches is
a) AEN
b) ADSTB
c) TC
d) None of the mentioned
Answer: b
Explanation: The pin ADSTB strobes the higher byte of the memory address, generated by the
DMA controller into the latches.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “DMA Transfers and Operations”.
1. The 8257 is able to accomplish the operation of
a) verifying DMA operation
b) write operation
c) read operation
d) all of the mentioned
Answer: d
Explanation: The 8257 can accomplish three types of operations and they are
i) verify DMA operation
ii) write operation
iii) read operation.
2. The bus is available when the DMA controller receives the signal
a) HRQ
b) HLDA
c) DACK
d) All of the mentioned
Answer: b
Explanation: If the HLDA signal is received by the DMA controller, it indicates that the bus is
available.
3. To indicate the I/O device that its request for the DMA transfer has been honored by the CPU,
the DMA controller pulls
a) HLDA signal
b) HRQ signal
c) DACK
activelow
d) DACK
activehigh
Answer: c
Explanation: The DACK
activelow
line of the used channel is pulled down by the DMA controller to indicate the I/O device that its
request for the DMA transfer has been honored by the CPU.
4. If more than one channel requests service simultaneously, the transfer will occur as
a) multi transfer
b) simultaneous transfer
c) burst transfer
d) none of the mentioned
Answer: c
Explanation: If more than one channel requests service simultaneously, then the transfer occurs
as a burst or continuous transfer.
5. The continuous transfer may be interrupted by an external device by pulling down the signal
a) HRQ
b) DACK
activelow
c) DACK
activehigh
d) HLDA
Answer: d
Explanation: The burst or continuous transfer may be interrupted by an external device by
pulling down the HLDA line.
6. The number of clock cycles required for an 8257 to complete a transfer is
a) 2
b) 4
c) 8
d) none of the mentioned
Answer: b
Explanation: The 8257 uses four clock cycles to complete a transfer.
7. In 8257, if each device connected to a channel is assigned to a fixed priority then it is said to
be in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned
Answer: b
Explanation: In this scheme, the DRQ3 has the lowest priority followed by DRQ2 and DRQ1.
The DRQ0 has the highest priority.
8. The priority of the channels varies frequently in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned
Answer: a
Explanation: In this scheme, the priorities assigned to the channels are not fixed.
9. The register of 8257 that can only be written in is
a) DMA address register
b) Terminal count register
c) Mode set register
d) Status register
Answer: c
Explanation: The selected register may be read or written depending on the instruction executed
by the CPU. But only write operation can be performed on the mode set register.
10. The operation that can be performed on the status register is
a) write operation
b) read operation
c) read and write operations
d) none of the mentioned
Answer: b
Explanation: The status register can only be read.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Programmable DMA Interface 8237 -1”.
1. The block of 8237 that decodes the various commands given to the 8237 by the CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: b
Explanation: The program control block decodes various commands given to the 8237 by the
CPU before servicing a DMA request.
2. The priority between the DMA channels requesting the services can be resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: c
Explanation: The priority encoder block resolves the priority between the DMA channels
requesting the services.
3. The register that holds the current memory address is
a) current word register
b) current address register
c) base address register
d) command register
Answer: b
Explanation: The current address register holds the current memory address. The current
address register is accessed during the DMA transfer.
4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register
Answer: a
Explanation: The current word register is a 16-bit register that holds the data transfers. The
word count is decremented after each transfer, and the new value is stored again in the register.
5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP
endofprocess
is generated
d) Start of process is generated
Answer: c
Explanation: When the count becomes zero, the EOP signal is generated. This can be written in
successive bytes by the CPU, in program mode.
6. The current address register is programmed by the CPU as
a) bit-wise
b) byte-wise
c) bit-wise and byte-wise
d) none of the mentioned
Answer: b
Explanation: The current address register is byte-wise programmed by the CPU, i.e. lower byte
first and the higher byte later.
7. Which of these register’s contents is used for auto-initialization
internally
a) current word register
b) current address register
c) base address register
d) command register
Answer: c
Explanation: The contents of base address register cannot be read by the CPU. These contents
are used internally for auto-initialization.
8. The register that maintains an original copy of the respective initial current address register
and current word register is
a) mode register
b) base address register
c) command register
d) mask register
Answer: b
Explanation: The base address register maintains an original copy of the current address
register and current word register, before incrementing or decrementing.
9. The register that can be automatically incremented or decremented, after each DMA transfer
is
a) mask register
b) mode register
c) command register
d) current address register
Answer: d
Explanation: The address is automatically incremented or decremented after each DMA
transfer, and the resulting address value is again stored in the current address register.
10. Which of the following is a type of DMA transfer?
a) memory read
b) memory write
c) verify transfer
d) all of the mentioned
Answer: d
Explanation: Memory read, memory write and verify transfer are the three types of DMA
transfer.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Question Paper focuses on “Programmable DMA Interface 8237
-2”.
1. Each bit in the request register is cleared by
a) under program control
b) generation of TC
c) generation of an external EOP
d) all of the mentioned
Answer: d
Explanation: In the request register, each bit is set or reset under program control or is cleared
upon generation of a TC or an external EOP.
2. The register that holds the data during memory to memory data transfer is
a) mode register
b) temporary register
c) command register
d) mask register
Answer: b
Explanation: The temporary register holds the data during memory to memory data transfers.
After the completion of the transfer operation, the last word transferred remains in the temporary
register, until it is cleared by a reset operation.
3. The register that keeps track of all the DMA channel pending requests and status of their
terminal counts is
a) mask register
b) request register
c) status register
d) count register
Answer: c
Explanation: The status register keeps track of all the DMA channel pending requests, and
status of their terminal counts. These are cleared upon reset.
4. The pin that clears the command, request and temporary registers, and internal first/last
flipflop when it is set is
a) CLEAR
b) SET
c) HLDA
d) RESET
Answer: d
Explanation: A high on the reset pin clears the command, status, request and temporary
registers, and also clears the internal first/last flipflop.
5. The DMA request input pin that has the highest priority is
a) DREQ0
b) DREQ1
c) DREQ2
d) DREQ3
Answer: a
Explanation: DREQ0 has the highest priority while DREQ3 has the lowest one. The priorities of
the DREQ lines is programmable.
6. When interface 8237 does not have any valid pending DMA request then it is said to be in
a) active state
b) passive state
c) idle state
d) none of the mentioned
Answer: c
Explanation: If 8237 is in idle state, then CPU may program it in this state.
7. To complete a DMA transfer, a memory to memory transfer requires
a) a read from memory cycle
b) a write to memory cycle
c) a read-from and write-to memory cycle
d) none of the mentioned
Answer: c
Explanation: A memory to memory transfer is a two cycle operation and requires a read from
and write-to memory cycle, to complete each DMA transfer.
8. In demand transfer mode of 8237, the device stops data transfer when
a) a TC
terminalcount
is reached
b) an external EOP
activelow
is detected
c) the DREQ signal goes inactive
d) all of the mentioned
Answer: d
Explanation: In demand transfer mode, the device continues transfers till a TC is reached or an
external EOP is detected or the DREQ signal goes inactive.
9. The mode of 8237 in which the device transfers only one byte per request is
a) block transfer mode
b) single transfer mode
c) demand transfer mode
d) cascade mode
Answer: b
Explanation: In single mode, the device transfers only one byte per request. For each transfer,
the DREQ must be active until the DACK is activated.
10. The transfer of a block of data from one set of memory address to another takes place in
a) block transfer mode
b) demand transfer mode
c) memory to memory transfer mode
d) cascade mode
Answer: c
Explanation: To perform the transfer of a block of data from one set of a memory address to
another one, this transfer mode is used.
11. Which of the following command is used to make all the internal registers of 8237 clear?
a) clear first/last flipflop
b) master clear command
c) clear mask register
d) none of the mentioned
Answer: b
Explanation: Using master clear command, all the internal registers of 8237 are cleared, while
all the bits of the mask register are set.
To practice all questions papers on Microprocessors, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “High Storage Capacity Memory Devices”.
1. The basic principle of floppy disks involve
a) magnetic data reading
b) magnetic data recording
c) magnetic data recording and reading
d) none of the mentioned
Answer: c
Explanation: Whatever their physical sizes and storage formats, all the floppies incorporate the
basic principles of magnetic data recording and reading.
2. In floppy disk, the small hole that enables the drive to identify the beginning of a track and its
first sector is
a) inner hole
b) key hole
c) index hole
d) start hole
Answer: c
Explanation: The small hole called index hole, enables the drive to identify the beginning of a
track and its first sector.
3. Inside its jacket, the floppy media is rotated at the speed of
a) 200 RPM
b) 300 RPM
c) 150 RPM
d) 50 RPM
Answer: b
Explanation: The floppy media is rotated at the speed of 300 RPM
RevolutionPerMinute
inside its jacket.
4. The Double Density Double Sided disks on each side are organized with
a) 20 tracks
b) 30 tracks
c) 40 tracks
d) 50 tracks
Answer: c
Explanation: The Double Density Double Sided
DDDS
disks are organized with 40 tracks on each side of the disk.
5. The magnetic recording technique used for storing data onto the disks
floppydisks
is called
a) return to zero
b) non-return to zero
c) return to zero and Non-return to zero
d) none of the mentioned
Answer: b
Explanation: In this technique, the magnetic flux on the disk surface never returns to zero, i.e.
no erase operation is carried out.
6. For reading the disks DVD uses
a) blue laser
b) white laser
c) red laser
d) green laser
Answer: c
Explanation: A DVD is an optical disk that uses a red laser for reading the disks.
7. For reading the disks, the blue ray disk uses
a) high frequency red laser
b) low frequency red laser
c) high frequency blue laser
d) low frequency blue laser
Answer: c
Explanation: The blue ray disk uses a high frequency blue laser with a small wavelength to read
the disk.
8. A blue ray disk can store data upto _________ per layer.
a) 25 KB
b) 25 MB
c) 25 TB
d) 25 GB
Answer: d
Explanation: A blue ray disk can store data upto 25 GB per layer and is popularly used for
storing long duration videos like movies.
9. DVDRW is for
a) read-write DVD
b) rewriteable DVD
c) recordable DVD
d) none of the mentioned
Answer: b
Explanation: DVDRW is for rewriteable DVD and DVDR is for recordable DVD.
10. The HDD is also called as
a) hard disk
b) hard drive
c) fixed disk
d) all of the mentioned
Answer: d
Explanation: The Hard Disk Drive is also called as a hard disk, hard drive, fixed drive, fixed disk
or fixed disk drive.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interconnection Topologies”.
1. The memory of a microprocessor serves as
a) storage of individual instructions
b) temporary storage for the data
c) storing common instructions or data for all processors
d) all of the mentioned
Answer: d
Explanation: The memory serves the microprocessor in the same way, whether it is a single
microprocessor or a multi microprocessor.
2. In shared bus architecture, the required processor
to perform a bus cycle, for fetching data or instructions is
a) one processor
b) two processors
c) more than two processors
d) none of the mentioned
Answer: a
Explanation: In a shared bus architecture, only one processor performs bus cycle to fetch
instructions or data from the memory.
3. In multiport memory configuration, the processor
that address the multiport memory is
are
a) 1
b) 2
c) 3
d) many
Answer: b
Explanation: The processors P1 and P2 address a multiport memory, which can be accessed at
a time by both the processors.
4. The memory space of a processor that is mapped to other processor/processors and
vice-versa is known as
a) multi microprocessor system
b) memory technique
c) bus window technique
d) mapping technique
Answer: c
Explanation: The bus window technique is the correct method of interconnection between the
processors.
5. The disadvantage of the bus window technique is
a) both processors must know about bus window
b) both processors must know the address map
c) loss of effective local memory space
d) all of the mentioned
Answer: d
Explanation: The disadvantage of bus window technique is that both processors must know
implicitly about the existence of a bus window, its size and the address map. It also results in
loss of effective local memory space.
6. Bus switches are present in
a) bus window technique
b) crossbar switching
c) linked input/output
d) shared bus
Answer: b
Explanation: In crossbar switching type of interconnection topology, several parallel data paths
are possible. Each node of the crossbar represents a bus switch.
7. Which of the following is not a type of configuration that is based on physical interconnections
between the processors?
a) star configuration
b) loop configuration
c) regular topologies
d) incomplete interconnection
Answer: d
Explanation: Based on the physical interconnections between the processors, the configurations
are
i) star configuration
ii) loop or ring configuration
iii) complete interconnection
iv) regular topologies
v) irregular topologies.
8. The configuration, in which all the processing elements are connected to a central switching
element, that may be independent processor via dedicated paths is
a) star
b) loop
c) complete
d) irregular
Answer: a
Explanation: The switching element controls the interconnections between the processing
elements.
9. The configuration that is not suitable for a large number of processors is
a) star
b) loop
c) complete
d) regular
Answer: c
Explanation: For a large number of processors, the complete interconnection is impractical due
to a large number of interconnection paths.
10. The array processor architecture is an example of
a) star
b) loop
c) complete
d) regular
Answer: d
Explanation: In array processor architecture, the processing elements are arranged in a regular
fashion.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Software Aspects of Multimicroprocessor Systems”.
1. The interconnection topologies are implemented using _________ as a node.
a) control unit
b) microprocessor
c) processing unit
d) microprocessor or processing unit
Answer: d
Explanation: The microprocessors or processing unit is used as a node in interconnection
topologies. They may also work as stand-alone processors or subprocessing units, under the
control of other microprocessors or processing units.
2. The feature of the multi-microprocessor architecture is
a) task dependent
b) single bus provider for many processors
c) design is for a specific task
d) all of the mentioned
Answer: d
Explanation: The main feature of multi-microprocessor is that it is task dependent. If it is
designed for a specific task, then it may not be useful for other tasks.
3. The main objective in building the multi-microprocessor is
a) greater throughput
b) enhanced fault tolerance
c) greater throughput and enhanced fault tolerance
d) none of the mentioned
Answer: c
Explanation: Greater throughput and enhanced fault tolerance are the main objectives of the
multi-microprocessor system. These systems incorporate a multiplicity of hardware and
software, for the purpose.
4. An interface between the user or an application program, and the system resources are
a) microprocessor
b) microcontroller
c) multi-microprocessor
d) operating system
Answer: d
Explanation: The operating system acts as an interface, and is an important program that
resides in the computer memory.
5. An operating system provides
a) hardware and software resource management
b) input/output management
c) memory management
d) all of the mentioned
Answer: d
Explanation: An operating system provides a means of hardware and software resource
management including input/output and memory management.
6. Distributed systems are designed to run
a) serial process
b) parallel process
c) serial and parallel process
d) none of the mentioned
Answer: d
Explanation: Distributed systems are designed to run a parallel process. It is essential that a
proper environment exists for concurrent processes to communicate and cooperate, in order to
complete the allotted task.
7. A distributed operating system must provide a mechanism for
a) intraprocessor communication
b) intraprocess and intraprocessor communication
c) interprocess and interprocessor communication
d) interprocessor communication
Answer: c
Explanation: A distributed operating system must provide a mechanism for interprocess and
interprocessor communication.
8. A multiprocessor operating system should perform
a) a mechanism to split a task into concurrent subtasks
b) optimize the system performance
c) handling structural or architectural changes
d) all of the mentioned
Answer: d
Explanation: A multiprocessor operating system should have a mechanism to split a task,
optimise system performance, and should handle structural changes.
9. An operating system must possess
a) process-processor allocation strategies
b) mechanism to collect results of subtasks
c) software to improve overall performance
d) all of the mentioned
Answer: d
Explanation: An operating system must have process-processor allocation strategies, a
mechanism to collect results of subtasks and software to improve overall performance.
10. A multiprocessor operating system must take care of
a) authorized data access and data protection
b) unauthorized data access and data protection
c) authorized data access
d) data protection
Answer: b
Explanation: A multiprocessor operating system must take care of unauthorized data access
and data protection.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Numeric Processor 8087 -1”.
1. The unit that executes all the numeric processor instructions in 8087 is
a) Control unit
b) ALU
c) Numeric extension unit
d) None of the mentioned
Answer: c
Explanation: The 8087 is divided into two sections namely control unit and numeric extension
unit in which the numeric extension unit executes all the numeric processor instructions.
2. The unit that receives and decodes the instructions in 8087 is
a) Control unit
b) ALU
c) Numeric extension unit
d) None of the mentioned
Answer: a
Explanation: The control unit receives, decodes the instructions, and executes the 8087 control
instructions.
3. The control unit functions in
a) establishing communication between CPU and memory
b) coordinating the internal coprocessor execution
c) reads and writes memory operands
d) all of the mentioned
Answer: d
Explanation: The control unit is used for establishing communication between CPU and memory
and coordinating the internal coprocessor execution.
4. When the numeric extension unit
NEU
begins its execution, then the signal that is active is
a) BUSY
activehigh
b) BUSY
activelow
c) READY
activelow
d) RESET
activehigh
Answer: a
Explanation: When NEU begins its execution, the BUSY signal is pulled up. Also, this output
signal when high, indicates to the CPU that it is busy with the execution of an allotted
instruction.
5. The register that allows the register programmer to select the required processing options is
a) significant
b) exponent
c) control word register
d) none of the mentioned
Answer: c
Explanation: The control word register allows the register programmer to select the required
processing options out of available ones. It is used to control the operation of 8087.
6. Invalid operation is the exception generated due to
a) stack overflow
b) stack underflow
c) indeterminate form as result
d) all of the mentioned
Answer: d
Explanation: Invalid operation is generated due to stack overflow, stack underflow,
indeterminate form as result, or non-number
NAN
as operand.
7. The exception generated for a too big result to fit in the format is
a) invalid operation
b) overflow
c) denormalized operand
d) result overflow
Answer: b
Explanation: A too big result to fit in the format generates this exception. The condition code bits
indicate that the result is prohibitively large.
8. If the result is infinity, then the exception generated is
a) overflow
b) invalid operation
c) denormalized operand
d) zero divide
Answer: d
Explanation: If any non-zero finite operand is divided by zero, the zero divide exception is
generated. The resulting condition code bits indicate that the result is infinity, even if the
exception is masked.
9. To operate 8087 in maximum mode, the pin MN/MX
activelow
is
a) connected to Vcc or power supply
b) connected to ground
c) left unconnected
d) none of the mentioned
Answer: b
Explanation: The 8087 can operate in a maximum mode, only when the MN/MX
activelow
pin of the CPU is grounded. In maximum mode, all the control signals are derived using a
sequence chip known as a bus controller.
10. If the result is rounded according to the rounding control bits, then the exception generated
is
a) denormalized operand
b) underflow
c) inexact result
d) invalid operation
Answer: c
Explanation: If it is impossible to fit the actual result in the specified format, the result is rounded
according to the rounding control bits, and an exception is generated. This sets the precision
exception flag.
11. The instruction that stores a copy of top of the stack into the memory, and pops the top of
the stack is
a) FST
b) FSTP
c) FIST
d) FLD
Answer: b
Explanation: FSTP
storefloatingpointnumberandpop
stores a copy of top of the stack into memory or any coprocessor register, and then pops the
top of the stack.
12. The instruction that multiplies the content of the stack top by 2n is
a) FMUL
b) FPREM
c) FSCAL
d) FCSH
Answer: c
Explanation: FSCAL instruction multiplies the content of the stack top by 2n, where n is an
integral part of stack and stores the result in stack.
13. If the opcode bit is D=1, then the source and destination operands are
a) incremented
b) decremented
c) cleared
d) interchanged
Answer: d
Explanation: If D=1, then it interchanges the source and destination operands.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “I/O Processor 8089”.
1. The 8089 shares the system bus and memory with the host CPU in
a) tightly coupled configuration
b) loosely coupled configuration
c) tightly and loosely coupled configurations
d) none of the mentioned
Answer: a
Explanation: In a tightly coupled configuration, the 8089 shares the system bus and memory
with the host CPU using its RQ
activelow
or GT
activelow
pins.
2. The 8089 communicates with the host CPU using bus arbiter and controller in
a) tightly coupled configuration
b) loosely coupled configuration
c) tightly and loosely coupled configurations
d) none of the mentioned
Answer: b
Explanation: In a loosely coupled configuration, the 8089 has its own local bus and
communicates with the host CPU using bus arbiter and controller.
3. The number of address lines used by the I/O processor in 8089 is
a) 20
b) 12
c) 16
d) 8
Answer: c
Explanation: The 8089 I/O processor uses only 16 address lines, and thus it can address only
64KB of IO space.
4. The IO device that can be interfaced with 8089 is
a) 16-bit IO
b) 8-bit IO
c) 64-bit IO
d) 16-bit and 8-bit IO
Answer: d
Explanation: The 8089 handled IO devices need not have the same data bus width as that of
8089. This enables even 8-bit IO devices to be interfaced easily with 8089.
5. In the 8089 architecture, the address of memory table for channel-2 is calculated by
a) adding 16 to the contents of CCP
b) adding 8 to the contents of CCP
c) adding memory table address of channel-1
d) none of the mentioned
Answer: b
Explanation: The address of the memory table for channel-2 is calculated by adding 8 to the
contents of CCP or by adding memory table address for channel-1 to the contents of CCP.
6. Which of the following is not a general purpose register of 8089?
a) GA
b) BC
c) CX
d) MC
Answer: c
Explanation: The registers GA, GB, GC, BC, IX and MC can be used as general purpose
registers.
7. The registers that are used as source and destination pointers during DMA operations are
a) GB, GC
b) GC, BC
c) GC, GA
d) GA, GB
Answer: d
Explanation: GA register is used as source and GB as destination pointers during DMA
operations.
8. The pin that is used for data transfer control and operation termination signals is
a) SINTR
b) EXT
c) DRQ and EXT
d) RQ
activelow
or GT
activelow
Answer: c
Explanation: The DRQ and EXT are used for data transfer control and operation termination
signals during DMA operations.
9. The pin that is used to inform the CPU that the previous operation is completed is
a) RQ
activelow
b) GT
activelow
c) DRQ
d) SINTR
Answer: d
Explanation: The SINTR pins are used by the channels either to inform the CPU that the
previous operation is over or to ask for its attention or interference if required, before the
completion of the task.
10. The current channel status of program status word contains
a) source and destination address widths
b) bus load limit
c) interrupt control and servicing
d) all of the mentioned
Answer: d
Explanation: The program status word contains the current channel status, which contains
source and destination address widths, channel activity, interrupt control and servicing, bus load
limit and priority information.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Bus Arbitration and Control”.
1. Which of the following is an incorporated function to resolve interprocessor communication
problems?
a) bus allotment and control
b) bus arbitration
c) priority resolving
d) all of the mentioned
Answer: d
Explanation: To resolve the various bus contention and interprocessor communication problems,
different hardware strategies and algorithms are worked out. These incorporated functions like
bus allotment and control, bus arbitration and priority resolving into them.
2. The device that deals with the bus access control functions and bus handshake activities is
a) bus allotment controller
b) bus arbiter
c) priority resolver
d) none of the mentioned
Answer: b
Explanation: The bus arbiter or 8289 takes care of bus access control functions and bus
handshake activities.
3. The clock generator delays the READY signal until the signal _________ goes low
a) DEN
activehigh
b) DEN
activelow
c) AEN
activelow
d) AEN
activehigh
Answer: c
Explanation: If AEN
activelow
is high, the clock generator delays the READY signal till the AEN
activelow
goes low.
4. The bus controller relinquishes the bus if
a) READY
activelow
b) LOCK
activehigh
c) CBRQ
activelow
d) BPRO
activehigh
Answer: b
Explanation: The bus controller does not relinquish
releaseitscontrolon
the bus, till the LOCK
activelow
input is low.
5. The signals that are used by the bus arbitration in the independent request method is
a) BREQ
activelow
b) BPRN
activelow
c) CBRQ
activelow
d) All of the mentioned
Answer: d
Explanation: The four active low signals, bus request
BREQ
, bus priority in
BPRN
, common bus request
CBRQ
and bus priority out
BPRO
are used for bus arbitration.
6. The signal that is used to drive a priority resolving network that actually accepts the bus
request inputs is
a) BREQ
activelow
b) BPRN
activelow
c) CBRQ
activelow
d) BPRO
activelow
Answer: a
Explanation: The BREQ
activelow
is used to drive a priority resolving network that actually accepts the bus request inputs from all
the masters and derives the priority outputs which further drive the BPRN
activelow
inputs of all the masters.
7. Which of the following is the simplest and cheapest method of bus arbitration?
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned
Answer: a
Explanation: The daisy chaining method is the simplest one, as it has less hardware complexity.
8. The method of bus arbitration that does not contain priority resolving network in it is
a) daisy chaining
b) independent request
c) polling
d) none
Answer: a
Explanation: The daisy chaining method does not contain any priority resolving network, rather
the priorities of all the devices are essentially assumed to be in sequence.
9. Which of the following is the fastest method of bus arbitration?
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned
Answer: b
Explanation: The independent request scheme is quite fast because each of the masters can
independently communicate with the controller.
10. A set of address lines is driven by the controller in
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned
Answer: c
Explanation: In a polling scheme, a set of address lines is driven by the controller to address
each of the masters in sequence.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Tightly Coupled and Loosely Coupled Systems”.
1. The processors used in the multi-microprocessor are
a) coprocessors
b) independent processors
c) coprocessors or independent processors
d) none of the mentioned
Answer: c
Explanation: The processors used in the multi-microprocessor are either coprocessors or
independent processors.
2. The processor that executes the instructions fetched for it by the host processor is
a) microprocessor
b) coprocessor
c) independent processor
d) coprocessor and independent processor
Answer: b
Explanation: The coprocessor executes the instructions fetched for it by the host processor.
3. The processor that asks for bus access or may itself fetch the instructions and execute them
is
a) microprocessor
b) coprocessor
c) independent processor
d) coprocessor and independent processor
Answer: c
Explanation: The independent processor may ask for bus access, may fetch the instructions
itself, and execute them independently.
4. In tightly coupled systems, the microprocessors share
a) common clock
b) bus control logic
c) common clock and bus control logic
d) none of the mentioned
Answer: c
Explanation: The microprocessors share a common clock and bus control logic, in a tightly
coupled system.
5. Communication between processors using a common system bus and common memory
takes place in
a) loosely coupled system
b) tightly coupled system
c) tightly and loosely coupled system
d) none of the mentioned
Answer: b
Explanation: In tightly coupled systems, the two processors may communicate using a common
system bus or common memory.
6. The bus arbitration is handled by an external circuit in
a) loosely coupled system
b) tightly coupled system
c) tightly and loosely coupled system
d) none of the mentioned
Answer: a
Explanation: In a loosely coupled multiprocessor system, each CPU may have its own bus
control logic. The bus arbitration is handled by an external circuit, common to all the processors.
7. The loosely coupled system has an advantage of
a) more number of CPUs can be added
b) system structure is modular
c) more fault-tolerant and suitable for parallel applications
d) all of the mentioned
Answer: d
Explanation: The loosely coupled system is advantageous than the tightly coupled system as it
has advantages of more number of CPUs can be added to improve the system performance. A
fault in a single module does not lead to a complete system breakdown.
8. In a tightly coupled system, when a processor is using the bus then the local bus of other
processors is in
a) hold state
b) high impedance state
c) halt state
d) low impedance state
Answer: b
Explanation: When a processor is using the bus then the other processors maintain their local
buses in high impedance state.
9. The disadvantage of the loosely coupled system is
a) complex due to additional hardware
b) less portable
c) more expensive
d) all of the mentioned
Answer: d
Explanation: The loosely coupled systems are more complicated due to the required additional
communication hardware. They are less portable and more expensive due to additional
hardware.
10. To indicate the completion of task allocated in a closely
tightly
coupled system, the microprocessor uses
a) status bit in memory
b) interrupts the host
c) status bit in memory or interrupts the host
d) clock pulse
Answer: c
Explanation: The microprocessor in a closely coupled system either uses a status bit in memory
or interrupts the host to inform it about the completion of task allotted to it.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Design of a PC Based Multimicroprocessor System”.
1. The files that reside in the current drive and directory of the hard disk is
a) OBJ files
b) EXE files
c) SRC files
d) DEST files
Answer: b
Explanation: The files that reside in the current drive and directory of the hard disk is EXE files.
2. The master processor stores the result buffers on to the hard disk with the filename as
a) .EXE file
b) .OBJ file
c) .EXE file with extension .RES
d) .OBJ file with extension .RES
Answer: c
Explanation: The master processor stores the result buffers on to the hard disk with the filename
as .EXE file with extension .RES.
3. The 8288 bus controller chip derives the signals
a) ALE
b) DEN
c) DT/R
activelow
d) All of the mentioned
Answer: d
Explanation: The latches are enabled by ALE signal and data will be enabled by DEN signal.
The ALE, DEN and DT/R
activelow
signals are derived by a separate 8288 bus controller chip.
4. The EXE files should not exceed the size of
a) 30 KB
b) 50 KB
c) 60 KB
d) 40 KB
Answer: c
Explanation: The EXE files should not be more than 60 KB size.
5. A part of memory that can be addressed by more than one processor for communication is
known as
a) memory module
b) bus window
c) ram
d) memory management unit
Answer: b
Explanation: There are two slave processors and thus there are two bus windows.
6. When a subprocessor wants to communicate with the bus window, it informs the main
processor to
a) enable control buffer
b) storage buffer
c) disable tristate buffer
d) translation look aside buffer
Answer: c
Explanation: An 8255 IO card is used to control the tristate buffers that provide isolation. When
a subprocessor wants to communicate with the bus window, it informs the main processor to
disable tristate buffer.
7. When the subprocessor completes its execution, then the status on the status lines shows
a) hold status
b) halt status
c) high status
d) low status
Answer: b
Explanation: When the subprocessor completes its execution, then the status on the status lines
shows halt status.
8. For MEMR
activelow
and MEMWR
activelow
operations the mode of isolation buffer should respectively be in
a) receiver mode, receiver mode
b) transmit mode, receiver mode
c) receiver mode, transmit mode
d) transmit mode, transmit mode
Answer: c
Explanation: During MEMR
activelow
the data flow from memory to CPU so isolation buffer should be in receiver mode and data
flows from CPU to memory during MEMWR
activelow
operation and so buffer should be in transmit mode.
9. If the DIR pin of the isolation chip is high, then it enters into
a) receiver mode
b) virtual access mode
c) transmit or receive mode
d) transmit mode
Answer: d
Explanation: If the DIR pin of the isolation chip is high, then it enters into transmit mode and if it
is 0 then the isolation chip enters into receiver mode.
10. The complete software system is divided into
a) main program
b) Interrupt routine IRT2 for first subprocessing the unit
c) Interrupt routine IRT3 for first subprocessing the unit
d) all of the mentioned
Answer: d
Explanation: System software of the complete system consists of three parts. the first part main
control program controls the total operation of the system, and the remaining two parts are the
small local initialization programs for each of the subprocessors.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Salient Features of 80286”.
1. The 80286 is able to address the physical memory of
a) 8 MB
b) 16 MB
c) 24 MB
d) 64 MB
Answer: b
Explanation: The 80286 with its 24-bit address bus is able to address 16 Mbytes of physical
memory.
2. The 80286 is able to operate with the clock frequency of
a) 12.5 MHz
b) 10 MHz
c) 8 MHz
d) all of the mentioned
Answer: d
Explanation: Various versions of 80286 are available that run on 12.5 MHz, 10 MHz and 8 MHz
clock frequencies.
3. The management of the memory system required to ensure the smooth execution of the
running process is done by
a) control unit
b) memory
c) memory management unit
d) bus interface unit
Answer: c
Explanation: The memory management which is an important task of the operating system is
now supported by a hardware unit called a memory management unit.
4. The fetching of the program from secondary memory to place it in physical memory, during
the execution of CPU is called
a) mapping
b) swapping in
c) swapping out
d) pipelining
Answer: b
Explanation: Whenever the portion of a program is required for execution by the CPU, it is
fetched from the secondary memory and placed in the physical memory. This is called swapping
in of the program.
5. The process of making the physical memory free by storing the portion of program and partial
results in the secondary storage called
a) mapping
b) swapping in
c) swapping out
d) pipelining
Answer: c
Explanation: In swapping out, a portion of the program or important partial results required for
further execution, may be saved back on secondary storage to make the physical memory free,
for further execution of another required portion of the program.
6. The memory that is considered as a large logical memory space, that is not available
physically is
a) logical memory
b) auxiliary memory
c) imaginary memory
d) virtual memory
Answer: d
Explanation: To the user, there exists a very large logical memory space, which is actually not
available called virtual memory. This does not exist physically in a system. It is however,
possible to map a large virtual memory space onto the real physical memory.
7. Memory management deals with
a) data protection
b) unauthorized access prevention
c) segmented memory
d) all of the mentioned
Answer: d
Explanation: The important aspects of memory management are data protection, unauthorized
access prevention, and segmented memory.
8. The memory management and protection mechanisms are disabled when the 80286 is
operated in
a) normal mode
b) real address mode
c) virtual address mode
d) all of the mentioned
Answer: b
Explanation: In real address mode of 80286, all the memory management and protection
mechanisms are disabled.
9. The memory management and protection mechanisms are enabled with advanced instruction
set when 80286 is operated in
a) normal mode
b) real address mode
c) virtual address mode
d) all of the mentioned
Answer: c
Explanation: In virtual address mode, 80286 works with all of its memory management and
protection capabilities, with the advanced instruction set.
10. The 80286 is an upward object code compatible with 8086 or 8088 when operated in
a) normal mode
b) real address mode
c) virtual address mode
d) real and virtual address mode
Answer: d
Explanation: The 80286 is operated in two modes, namely real address mode and virtual
address mode. In both the modes, the 80286 is compatible with 8086/8088.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Internal Architecture of 80286”.
1. The CPU of 80286 contains
a) 16-bit general purpose registers
b) 16-bit segment registers
c) status and control register
d) all of the mentioned
Answer: d
Explanation: The CPU of 80286 contains the same set of registers as in 8086.
2. The bits that are modified according to the result of the execution of logical and arithmetic
instructions are called
a) byte addressable bit
b) control flag bits
c) status flag bit
d) none of the mentioned
Answer: c
Explanation: The flag register bits, D0, D2, D4, D6, D7 and D11 are modified according to the
result of the execution of logical and arithmetic instructions. These are called as status flag bits.
3. The flags that are used for controlling machine operation are called
a) status flags
b) control flags
c) machine controlled flags
d) all of the mentioned
Answer: b
Explanation: The flags such as trap flag
TF
and Interrupt flag
IF
bits are used for controlling the machine operation, and thus they are called control flags.
4. The additional field that is available in 80286 is
a) I/O Privilege field
b) nested task flag
c) protection enable
d) all of the mentioned
Answer: d
Explanation: The additional fields available in 80286 flag register are, I/O Privilege field, nested
task flag, protection enable, and monitor processor extension.
5. Which of the block is not considered as a block of an architecture of 80286?
a) address unit
b) bus unit
c) instruction unit
d) control unit
Answer: d
Explanation: The CPU may be viewed to contain four functional parts and they are
i) Address Unit
ii) Bus Unit
iii) Instruction Unit
iv) Execution Unit.
6. The unit that is responsible for calculating the address of instructions, and data that the CPU
wants to access is
a) bus unit
b) address unit
c) instruction unit
d) control unit
Answer: b
Explanation: The address unit is responsible for calculating the address of instructions, and data
that the CPU wants to access. Also, the address lines derived by this unit may be used to
address different peripherals.
7. The process of fetching the instructions in advance, and storing in the queue is called
a) mapping
b) swapping
c) instruction pipelining
d) storing
Answer: c
Explanation: The instructions are fetched in advance and stored in a queue to enable faster
execution of the instructions. This concept is known as instruction pipelining.
8. The CPU must flush out the prefetched instructions immediately following the branch
instruction in
a) conditional branch
b) unconditional branch
c) conditional and unconditional branches
d) none of the mentioned
Answer: b
Explanation: In case of unconditional branch, the CPU will have to flush out the prefetched
instructions, immediately following the branch instruction.
9. The device that interfaces and control the internal data bus with the system bus is
a) data interface
b) controller interface
c) data and control interface
d) data transreceiver
Answer: d
Explanation: The data transreceivers interface and control the internal data bus with the system
bus.
10. The register bank of Execution Unit of 80286 is used as
a) for storing data
b) scratch pad
c) special purpose registers
d) all of the mentioned
Answer: d
Explanation: The execution unit contains the register bank, used for storing the data as scratch
pad, or used as special purpose registers.
11. Which of the following is not an interrupt generated by 80286?
a) software interrupts
b) hardware or external interrupts
c) INT instruction
d) none of the mentioned
Answer: d
Explanation: The interrupts generated by 80286 may be divided into 3 categories as external or
hardware interrupts, INT instruction or software interrupts and interrupts generated by
exceptions.
12. For which of the following instruction does the return address point to instruction causing an
exception?
a) divide error exception
b) bound range exceeded exception
c) invalid opcode exception
d) all of the mentioned
Answer: d
Explanation: For the instructions, divide error, bound range exceeded and invalid opcode
exceptions, the return address points to the instruction causing exception.
13. The instruction that comes into action, if the trap flag is set is
a) maskable interrupt
b) non-maskable interrupt
c) single step interrupt
d) breakpoint interrupt
Answer: c
Explanation: Single step interrupt is an internal interrupt that comes into action if the trap flag
TF
is set.
14. The interrupt that has the highest priority among the following is
a) Single step
b) NMI
non−maskableinterrupt
c) INTR
d) Instruction exception
Answer: d
Explanation: The instruction exception has the highest priority followed by single step, NMI and
INTR instrution.
15. The interrupt that has the lowest priority among the following is
a) Processor extension segment overrun
b) INTR
c) INT instruction
d) NMI
Answer: c
Explanation: The INT instruction has the lowest priority. The order of priority of interrupts from
high to low is
1) instruction exception
2) single step
3) NMI
4) processor extension segment overrun
5) INTR
6) INT instruction.
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Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Signal Descriptions of 80286”.
1. The 80286 is available in the package as
a) 68-pin PLCC
plasticleadedchipcarrier
b) 68-pin LCC
leadlesschipcarrier
c) 68-pin PGA
pingridarray
d) all of the mentioned
Answer: d
Explanation: The 80286 is available in 68-pin PLCC
plasticleadedchipcarrier
, 68-pin LCC
leadlesschipcarrier
and 68-pin PGA
pingridarray
packages.
2. The clock frequency applied at the CLK pin is internally divided by
a) 2
b) 4
c) 8
d) 1
Answer: a
Explanation: The clock frequency is divided by two internally, and is used for deriving
fundamental timings for basic operations of the circuit.
3. The 8 address lines, A23-A16 of 80286 are zero during
a) memory transfer
b) address transfer
c) memory to processor transfer
d) I/O transfer
Answer: d
Explanation: The address lines, A23-A16 are zero during I/O transfers.
4. The signals S1
activelow
, S2
activelow
are
a) output signals
b) indicate initiation of bus cycle
c) define type of bus cycle with M/IO
activelow
d) all of the mentioned
Answer: d
Explanation: The signals S1
activelow
, S2
activelow
are active low status output signals, which indicate initiation of a bus cycle, and with M/IO
activelow
and COD/INTA
activelow
, they define the type of the bus cycle.
5. If M/IO
activelow
signal is ‘0’ then it indicates
a) I/O cycle
b) Memory cycle
c) I/O cycle or INTA cycle
d) I/O cycle or HALT cycle
Answer: c
Explanation: If M/IO
activelow
signal is ‘0’ then it indicates that an I/O cycle or INTA cycle is in the process, and if it is ‘1’, it
indicates that a memory or a HALT cycle is in progress.
6. The LOCK
activelow
is activated automatically by hardware using
a) XCHG signal
b) Interrupt acknowledge
c) Descriptor table access
d) All of the mentioned
Answer: d
Explanation: The lock pin is used to prevent the other masters from gaining the control of the
bus, for the current and the following bus cycles. This pin is activated by a “LOCK” instruction
prefix, or automatically by hardware during XCHG, interrupt acknowledge or descriptor table
access.
7. The pin that is used to insert wait states in a bus cycle is
a) WAIT
b) BHE
activelow
c) READY
activelow
d) WAIT
activelow
Answer: c
Explanation: The active low READY pin is used to insert wait states in a bus cycle, for
interfacing low speed peripherals. This signal is neglected during HLDA cycle.
8. The minimum number of clock cycles required in an input pulse width of the RESET pin is
a) 4
b) 2
c) 8
d) 16
Answer: d
Explanation: The active high RESET input clears the internal logic of 80286, and re-initializes it.
The reset input pulse width should be at least 16 clock cycles.
9. To filter the output, a 0.047microfarads, 12V capacitor is connected between the pins
a) CAP and ground
b) Output pin and ground
c) CAP and Vcc
d) NMI and ground
Answer: a
Explanation: A 0.047microfarads, 12V capacitor is connected between the CAP pin and ground,
to filter the output of the internal substrate bias generator.
10. The signal that causes the 80286 to perform the processor extension interrupt while
executing the WAIT and ESC instructions are
a) BUSY
activelow
b) PEACK
activelow
c) PEREQ
d) ERROR
activelow
Answer: d
Explanation: An active ERROR
activelow
signal causes the 80286 to perform the processor extension interrupt while executing the WAIT
and ESC instructions.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Real Addressing Mode”.
1. The 80286 CPU acts just like that of 8086 when operated in
a) real addressing mode
b) protected virtual address mode
c) real and protected virtual address modes
d) none of the mentioned
Answer: a
Explanation: In the real addressing mode of operation of 80286, it just acts as a fast 8086.
2. In real addressing mode, the 80286 addresses a physical memory of
a) 16 MB
b) 8 MB
c) 2 MB
d) 1 MB
Answer: d
Explanation: In real addressing mode, the 80286 addresses a physical memory of 1 Mbytes
using A0-A19. The lines A20-A23 are not used by the internal circuit of 80286 in this mode.
3. In real addressing mode, the 80286 operates at a speed
a) faster than that of 8086
b) half of that of 8086
c) slower than that of 8086
d) same as that of 8086
Answer: a
Explanation: Because of extra pipelining and other circuit level improvements, in real address
mode also, the 80286 operates at a much faster rate than 8086.
4. In physical memory, if the segment size limit is exceeded by the instruction or data then
a) instruction is not executed
b) exception is generated
c) saves to next segment automatically
d) none of the mentioned
Answer: b
Explanation: An exception is generated if the segment size limit is exceeded by the instruction
or the data.
5. The 80286 reserves fixed area of physical memory for
a) system initialization
b) interrupt vector table
c) system initialization and interrupt vector table
d) none of the mentioned
Answer: c
Explanation: The 80286 reserves two fixed areas of physical memory for system initialization
and interrupt vector table.
6. In the real mode, the memory that is reserved for interrupt vector table is
a) first 2 KB of memory
b) first 1 KB of memory
c) last 2 KB of memory
d) last 1 KB of memory
Answer: b
Explanation: In the real mode, the first 1 Kbyte of memory starting from the address 00000H to
003FFH, is reserved for interrupt vector table.
7. In the real mode, the memory that is reserved for system initialization is
a) from 004FFH to 0FFFFH
b) from 004FFH to 05FFFH
c) from FFFF0H to FFFFFH
d) from FFF00H to FFFFFH
Answer: c
Explanation: The addresses from FFFF0H to FFFFFH are reserved for system initialization, in
real addressing mode.
8. When 80286 is reset, it always starts its execution in
a) protected virtual addressing mode
b) real addressing mode
c) either real or protected virtual address modes
d) none of the mentioned
Answer: b
Explanation: When 80286 is reset, it always starts its execution in real addressing mode.
9. The 80286 in real addressing mode performs
a) initialization of IP
b) enables interrupts
c) sets up descriptor table
d) all of the mentioned
Answer: d
Explanation: The 80286 in real addressing mode performs the following functions: it initializes IP
and other registers of 80286, initializes the peripheral, enables interrupts, sets up descriptor
tables, and then prepares it for entering the protected virtual address mode.
10. In real address mode, while addressing the physical memory, the 80286 uses the signal
a) HLDA
b) BHE
activelow
c) CAP
d) HOLD
Answer: b
Explanation: In real address mode, while addressing the physical memory, the 80286 uses BHE
activelow
along with A0-A19.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Protected Virtual Address Mode
PVAM
-1”.
1. The procedure of fetching the chosen program segments or data from the secondary storage
into the physical memory is
a) mapping
b) swapping
c) unswapping
d) pipelining
Answer: b
Explanation: Swapping is the procedure of fetching the chosen program segments or data from
the secondary storage into the physical memory.
2. The procedure of storing back the partial results on to the secondary storage is called
a) mapping
b) swapping
c) unswapping
d) pipelining
Answer: c
Explanation: The procedure of storing back the partial results or data back on to the secondary
storage is called unswapping.
3. The ability of 80286 to address the virtual memory per task is
a) 1MB
b) 1GB
c) 1TB
d) none of the mentioned
Answer: b
Explanation: The 80286 is able to address 1Gbyte of virtual memory per task.
4. The branch instructions are handled by
a) swapping mechanism
b) unswapping mechanism
c) operating system
d) all of the mentioned
Answer: d
Explanation: The handling of branch instructions like JUMP and CALL is taken care of, by the
swapping and unswapping mechanism, and operating system.
5. A descriptor contains information of
a) program segment
b) page
c) regarding segment and its access rights
d) all of the mentioned
Answer: d
Explanation: The segments or pages have been associated with a data structure known as a
descriptor. The descriptor contains information on the page, and also carry relevant information
regarding a segment, and its access rights.
6. The descriptors that are used for subroutines and interrupt service routines are
a) data segment descriptors
b) gate descriptors
c) code segment descriptors
d) system segment descriptors
Answer: b
Explanation: For data segment, the corresponding descriptor may be data segment descriptor
and for code segment, there may be code segment descriptor. For subroutines and interrupt
service routines there are gate descriptors.
7. A segment with low privilege level is not allowed to access another segment of
a) low privilege level
b) high privilege level
c) low and high privilege level
d) none of the mentioned
Answer: b
Explanation: A segment with low privilege level is not allowed to access another segment with
high privilege level.
8. A descriptor is used to carry out
a) transfer of control
b) task switching
c) to store privilege level and segment limit
d) all of the mentioned
Answer: d
Explanation: A descriptor is used to carry out additional functions like transfer of control and
task switching.
9. The descriptor that is used for special system data segments and control transfer operations
is
a) data segment descriptors
b) gate descriptors
c) code segment descriptors
d) system segment descriptors
Answer: d
Explanation: The 80286 has system segment descriptor, that is used for special system data
segments, and control transfer operations.
10. A code segment descriptor contains
a) 16-bit segment limit
b) 24-bit segment base address
c) 8-bit access rights byte
d) all of the mentioned
Answer: d
Explanation: A code or data segment descriptor contains 16-bit segment limit, 24-bit segment
base address, 8-bit access rights byte and the remaining 16-bits are reserved by Intel for
upward compatibility.
11. In access rights byte, if P
Present
=1, then the segment is mapped into
a) physical memory
b) virtual memory
c) no mapping takes place
d) none of the mentioned
Answer: a
Explanation: If P=1, then the segment is mapped into physical memory.
12. In access rights byte, to select system segment descriptor, the condition is
a) S=1
b) S=0
c) S not equal to zero
d) none of the mentioned
Answer: b
Explanation: If S
segmentdescriptor
=0, then system segment descriptor or gate descriptor is selected.
13. If S
segmentdescriptor
=1, then the descriptor selected is
a) code segment descriptor
b) data segment descriptor
c) stack segment descriptor
d) all of the mentioned
Answer: d
Explanation: If S=1, then code or data
includingstack
segment descriptors are selected.
14. The memory of limit field is
a) 2 bits
b) 4 bits
c) 8 bits
d) 16 bits
Answer: d
Explanation: The limit field, which is the maximum allowed offset address, is of 16 bits.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Advanced Microprocessors Questions and Answers focuses on “Protected Virtual
Address Mode
PVAM
-2”.
1. Which of the following is a type of system segment descriptor?
a) system descriptor
b) gate descriptor
c) system descriptor and gate descriptor
d) none of the mentioned
Answer: c
Explanation: The system segment descriptors are of seven types. The types 1 to 3 are called
system descriptors and the types 4 to 7 are called gate descriptors.
2. Which of the following is a type of gate descriptor?
a) call gate
b) task gate
c) interrupt gate
d) all of the mentioned
Answer: d
Explanation: The gate descriptors are of four types namely, call gate, task gate, interrupt gate
and trap gate.
3. The gate descriptor contains the information of
a) destination of control transfer
b) stack manipulations
c) privilege level
d) all of the mentioned
Answer: d
Explanation: The gate descriptor contains the information regarding the destination of control
transfer, required stack manipulations, privilege level and its type.
4. The gate that is used to alter the privilege levels is
a) call gate
b) task gate
c) interrupt gate
d) trap gate
Answer: a
Explanation: Call gates are used to alter the privilege levels.
5. The gate that is used to specify a corresponding service routine is
a) call gate and trap gate
b) task gate and interrupt gate
c) interrupt gate and trap gate
d) task gate and trap gate
Answer: c
Explanation: Interrupt gates and trap gates are used to specify corresponding service routines.
6. The gate that is used to switch from one task to another is
a) trap gate
b) task gate
c) task gate and trap gate
d) none of the mentioned
Answer: b
Explanation: Task gate is used to switch from one task to another.
7. The gate that uses word count field is
a) trap gate
b) task gate
c) interrupt gate
d) call gate
Answer: d
Explanation: The word count field is only used by a call gate descriptor, to indicate the number
of bytes to be transferred from the stack of the calling routine to the stack of the called routine.
8. The memory that maintains the most frequently required data for execution, in a high speed
memory is called
a) virtual memory
b) physical memory
c) cache memory
d) ROM
readonlymemory
Answer: c
Explanation: To minimize the time required for fetching the frequently required descriptor
information, from the main memory, cache memory is used in which the most frequently
required data for execution is stored.
9. The selector field consists of
a) requested privilege level
RPL
b) table indicator
c) index
d) all of the mentioned
Answer: d
Explanation: In the protected mode, the contents of the segment registers are known as
selectors. The selector field consists of three fields namely, RPL, table indicator
TI
and index.
10. If table indicator, TI=0, then the descriptor table selected is
a) local descriptor table
b) global descriptor table
c) local and global descriptor table
d) none of the mentioned
Answer: b
Explanation: The type of descriptor table is global if TI=0 and local if TI=1.
11. The instruction that is executed at privilege level zero
is
a) LDT
b) LGDT and LLDT
c) GDT
d) None of the mentioned
Answer: b
Explanation: The LGDT and LLDT instructions are privileged, and may be executed only at
privilege level 0.
12. The instruction that loads a selector which refers to a local descriptor table, containing the
base address and limit for LDT is
a) LGT
b) GDT
c) LGDT
d) LLDT
Answer: d
Explanation: The LLDT instruction loads a selector, which refers to a local descriptor table,
containing the base address, and limit for LDT.
13. The descriptor that is used to store task gates, interrupt gates and trap gates is
a) system descriptor table
b) gate descriptor table
c) interrupt descriptor table
d) none of the mentioned
Answer: c
Explanation: The 80286 has a third type of descriptor table known as interrupt descriptor table,
which is used to store task gates, interrupt gates and trap gates.
14. The number of interrupt descriptors that the interrupt descriptor table
IDT
handles is
a) 16
b) 64
c) 128
d) 256
Answer: d
Explanation: The IDT is able to handle upto 256 interrupt descriptors.
15. The number of bytes required for an interrupt in an IDT is
a) 2
b) 4
c) 6
d) 8
Answer: c
Explanation: Six bytes are required for each interrupt in an interrupt descriptor table.
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set of 1000+ Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Privilege”.
1. By using privilege mechanism the protection from unauthorized accesses is done to
a) operating system
b) interrupt handlers
c) system software
d) all of the mentioned
Answer: d
Explanation: The operating system, interrupt handlers and other system softwares can be
protected from unauthorized accesses in virtual address space of each task using the privilege
mechanism.
2. The task privilege level at the instant of execution is called
a) Descriptor privilege level
DPL
b) Current privilege level
CPL
c) Effective privilege level
EPL
d) None of the mentioned
Answer: b
Explanation: Any one of the four privilege levels may be used to execute a task. The task
privilege level at that instant is called the Current Privilege Level
CPL
.
3. Once the CPL is selected, it can be changed by
a) hold
b) transferring control using system descriptors
c) transferring control using gate descriptors
d) transferring control using interrupt descriptors
Answer: c
Explanation: Once the CPL is selected, it cannot be changed during the execution normally in a
single code segment. It can only be changed by transferring the control, using gate descriptors,
to a new segment.
4. The data segments defined in GDT
globaldescriptortable
and the LDT
localdescriptortable
can be accessed by a task with
a) privilege level 0
b) privilege level 1
c) privilege level 2
d) privilege level 3
Answer: a
Explanation: A task executing at level 0, the most privileged level, can access all the data
segments defined in GDT and the LDT of the task.
5. A task with privilege level 0, doesn’t refer to all the lower level privilege descriptors in
a) GDT
globaldescriptortable
b) LDT
localdescriptortable
c) IDT
interruptdescriptortable
d) None of the mentioned
Answer: b
Explanation: The task with privilege level 0, refers to all the lower level privilege descriptors
which apply to all the descriptors except the LDT descriptors.
6. The selector RPL that uses a less trusted privilege than the current privilege level for further
use is known as
a) Least task privilege level
b) Descriptor privilege level
c) Effective privilege level
d) None of the mentioned
Answer: c
Explanation: A selector RPL uses a less trusted privilege than the current privilege level for
further use. This is known as the Effective Privilege Level of the task.
7. The effective privilege level is
a) maximum numeric of RPL and CPL
b) minimum privilege of RPL and CPL
c) numeric minimum and privilege maximum of RPL and CPL
d) none of the mentioned
Answer: c
Explanation: The effective privilege level is minimum in numeric and maximum in the privilege of
RPL and CPL.
8. The task requesting an access to a descriptor is allowed to access after checking the
a) type of descriptor
b) privilege level
c) type of descriptor and privilege level
d) corresponding segment
Answer: c
Explanation: The task requesting an access to a descriptor is allowed to access to it and to the
corresponding segment, only after checking the type of the descriptor and privilege level
CPL,RPL,DPL
.
9. A CALL instruction can reference only a code segment descriptor with
a) DPL less privilege than CPL
b) DPL equal privilege to CPL
c) DPL greater privilege than CPL
d) All of the mentioned
Answer: b
Explanation: A CALL or JUMP instruction can reference only a code segment descriptor with
DPL equal to CPL of the task or a segment with a DPL of equal or greater privilege than CPL.
10. The RPL of a selector that referred to the code descriptor must have
a) less privilege than CPL
b) greater privilege than CPL
c) equal privilege than CPL
d) any privilege regarding CPL
Answer: c
Explanation: The RPL of a selector that referred to the code descriptor must have the same
privilege as CPL.
11. The instruction that refers to only code segment descriptors with DPL equal to or less than
the task CPL is
a) CALL
b) IRET
c) ESC
d) RET and IRET
Answer: d
Explanation: The RET and IRET instructions are to refer to only code segment descriptors with
DPL equal to or less than the task CPL.
12. When a JUMP instruction references a Task State Segment
TSS
descriptor, then DPL must be
a) equally privileged as CPL
b) greater or equally privileged than CPL
c) less or equally privileged than CPL
d) less privileged than CPL
Answer: c
Explanation: When a CALL or JUMP instruction references a Task State Segment
TSS
descriptor, then DPL must be less or equally privileged than CPL.
13. The data segment access refers to
a) loading DS
b) loading ES
c) loading SS
d) all of the mentioned
Answer: d
Explanation: Loading DS, ES or SS for referring to a new descriptor comes under the data
segment access.
14. An exception is generated when
a) privilege test is negative
b) an improper segment is referenced
c) referenced segment is not present in physical memory
d) all of the mentioned
Answer: d
Explanation: If the privilege test is negative or an improper segment is referenced then an
exception 13 is generated. If the referenced segment is not present in physical memory, an
exception 11 is generated.
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Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Protection”.
1. The mechanism to provide protection, that is accomplished with the help of read/write
privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
Answer: a
Explanation: The restricted use of segments is accomplished with the help of read/write
privileges.
2. The Local descriptor table
LDT
and Global descriptor table
GDT
are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
Answer: c
Explanation: In restricted use of segments i.e. segment load check, the segment usages are
restricted by classifying the corresponding descriptors, under LDT and GDT.
3. The mechanism that is accomplished using descriptor usages limitations and rules of
privilege check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
Answer: b
Explanation: Restricted accesses to segment, also called, operation reference check, is
accomplished using descriptor usages limitations, and rules of privilege check.
4. The mechanism that is executed at certain privilege levels, determined by CPL
CurrentPrivilegeLevel
and I/O privilege level
IOPL
is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
Answer: c
Explanation: The privileged instructions or operations, also called, privileged instruction check,
is executed at certain privilege levels, determined by CPL and I/O privilege level
IOPL
, as defined by the flag register.
5. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) None of the mentioned
Answer: c
Explanation: The IRET and POPF instructions do not perform any of their functions, if CPL is
not of the required privilege level.
6. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
Answer: c
Explanation: IF remains unaffected if CPL is greater than zero. No exception is generated for
this condition.
7. The condition, “CPL not equals to zero” satisfies when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) All of the mentioned
Answer: d
Explanation: The condition, “CPL not equals to zero” satisfies, when executing the instructions,
LIDT, LGDT, LTR, LMSW, CTS and HLT.
8. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) All of the mentioned
Answer: c
Explanation: The condition CPL>IOPL exists, when executing the instructions, INs, IN, OUTS,
OUT, STI, CLI and LOCK.
9. The instruction at which the exception is generated, but the processor extension registers
contain the address of failing instruction is
a) LTR
b) INS
c) CTS
d) ESC
Answer: d
Explanation: At the ESC instruction, the exception is generated, but the processor extension
registers contain the address of failing instruction.
10. The exception that has no error code on a stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
Answer: b
Explanation: The processor extension segment overrun has no error code on the stack.
11. Which of the following is protected mode exception?
a) double exception detected
b) invalid task state segment
c) stack segment overrun
d) all of the mentioned
Answer: d
Explanation: Double exception detected, invalid task state segment, stack segment overrun,
processor extension segment overrun, are the protected mode exceptions.
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Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Special Operations”.
1. Which of the following operation is not carried out by 80286?
a) task switch operation
b) halt
c) processor reset
d) none of the mentioned
Answer: d
Explanation: The 80286 carries out six operations. They are:
1. processor reset and initialization
2. task switch operation
3. pointer testing instructions
4. protected mode initialization
5. how to enter protected mode?
6. halt.
2. After completion of the first cycle, the first task is again scheduled for the next cycle. This
process is known as
a) repetition
b) task switch operation
c) processor initiation
d) none of the mentioned
Answer: b
Explanation: After completion of the first cycle, the first task is again scheduled for the next
cycle, and the process continues. The previous task that was incomplete, may be completed
during its coming turns of the allotted CPU time slice. This switch-over operation from one task
to another is called task switch operation.
3. The operation that is provided by the internal architecture, to save the execution state of a
task is
a) processor reset
b) processor initialization
c) task switch operation
d) halt
Answer: c
Explanation: The 80286 internal architecture provides a task switch operation, to save the
execution state of a task, and to load a new task to be executed.
4. The instruction that can be used to carry out task switch operation is
a) software interrupt instruction
b) exception
c) external interrupt
d) all of the mentioned
Answer: d
Explanation: A software interrupt instruction, exception or external interrupt, can also be used to
carry out task switch operation.
5. The IRET instruction gets back the execution state of the previous task, if
a) NT
nestedtaskflag
=1
b) NT
nestedtaskflag
=0
c) IF
interruptflag
=1
d) IF
interruptflag
=0
Answer: a
Explanation: If NT = 1, the IRET instruction gets back the execution state of the previous task.
Otherwise, the IRET instruction lets the current task continue, after popping the required values
from the stack.
6. The NT flag is set by the task switch operation, that is initiated by
a) CALL
b) INT
c) CALL & INT
d) None of the mentioned
Answer: c
Explanation: The NT flag is set by CALL or INT initiated task switch operations.
7. The 80286 executes LMSW instruction to enter into
a) real addressing mode
b) protected mode
c) real addressing and protected modes
d) none of the mentioned
Answer: b
Explanation: To enter into protected mode, 80286 executes LMSW instruction, that sets PE flag.
8. The instruction that sets the zero flag, if the segment referred to, by the selector can be read
is
a) VERW
b) VERR
c) LSL
d) LAR
Answer: b
Explanation: The VERR
VERifytoRead
instruction sets the zero flag, if the segment referred to, by the selector, can be read.
9. The instruction that sets the zero flag, if the segment referred to by the selector, can be
written as
a) VERW
b) APRL
c) LSL
d) LAR
Answer: a
Explanation: The VERW
VERifytoWrite
instruction sets the zero flag, if the segment referred to, by the selector can be written.
10. The instruction that reads the descriptor access rights byte into the register is
a) VERW
b) APRL
c) LSL
d) LAR
Answer: d
Explanation: The LAR
LoadAccessRights
instruction reads the descriptor access rights byte into the register, if privilege rules allow.
11. The instruction that reads the segment limit into the register, if privilege rules and descriptor
type allow is
a) VERW
b) APRL
c) LSL
d) LAR
Answer: c
Explanation: The LSL
LoadSegmentLimit
instruction reads the segment limit into the register, if privilege rules, and descriptor type allow.
12. The instruction that adjusts the RPL
RequestedPrivilegeLevel
of the selector, to the numeric maximum of current selector RPL value is
a) LAR
b) VERR
c) LSL
d) APRL
Answer: d
Explanation: The APRL
AdjustRequestedPrivilegeLevel
adjusts the RPL
RequestedPrivilegeLevel
of the selector to the numeric maximum of current selector RPL value, and the RPL value in the
register.
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Questions and Answers .
This set of Microprocessors Interview Questions and Answers for Experienced people focuses
on “80286 Minimum System Configuration, Interfacing Memory and I/O Devices With 80286”.
1. Which of the following is a supporting chip of 80286?
a) interrupt controller
b) clock generator
c) bus controller
d) all of the mentioned
Answer: d
Explanation: The interrupt controller 8259A, clock generator 82C284, and bus controller 82C288
are the unavoidable members of the family, of supporting chips of 80286.
2. In minimum mode, the function of 80286 is
a) data transfers to/from memory or I/O
b) controls the data transfer of 80287
c) controls the instruction execution of 80287
d) all of the mentioned
Answer: d
Explanation: In a minimum mode, the 80286 carries out all the data transfers to/from memory or
I/O, controls the data transfer, and instruction execution of 80287.
3. The signal that is applied to the decoding logic, to differentiate between interrupt, code fetch
and data bus cycles is
a) COD
b) INTA
activelow
c) M/IO
activelow
d) All of the mentioned
Answer: d
Explanation: The COD, INTA
activelow
, M/IO
activelow
signals are applied to the decoding logic, to differentiate between interrupt, I/O, code fetch, and
data bus cycles.
4. By adding which of the following, the minimum mode of 80286 gives the multibus interface of
80286?
a) bus controller
b) bus arbiter
c) interrupt controller
d) all of the mentioned
Answer: b
Explanation: The addition of single chip 82C289 known as bus arbiter, to the configuration of
80286 minimum mode, gives the multibus structure of 80286.
5. The number of bus controllers that are used for interfacing of memory and I/O devices is
a) 1
b) 2
c) 3
d) none of the mentioned
Answer: b
Explanation: The interfacing of memory and I/O devices, uses two 82288 bus controllers, one
each for local, and system bus.
6. If the 80286 need to use system bus, then the signal that is to be active is
a) SRDY
b) SRDYEN
c) ARDYEN
d) ARDY
Answer: c
Explanation: The ARDYEN pin is to be activated if the 80286 is to use the system bus. The
SRDYEN pin is to be grounded.
7. If MBYTES input is high, then the pin serves as
a) AEN
b) CEN
c) AEN and CEN
d) None of the mentioned
Answer: a
Explanation: The MBYTES input selects the function of AEN/CEN pin. If MBYTES is high, the
pin serves as AEN, else it serves as CEN. The CEN pin is used for selecting one of the
available 82288s.
8. Latches are used in 80286 to
a) demultiplex the address and data lines
b) latch the address signals
c) decode the select signals
d) latch the address and decode the select signals
Answer: d
Explanation: The address and data lines are not multiplexed, hence no latches are required in
80286 system. Rather the addresses of the next bus cycle are displayed in advance, hence the
latches are required for latching the address, and decode the signals.
9. The I/O port addresses, that are not used, while designing practical systems around 80286
are
a) 0000H to 00FFH
b) 00FFH to FFFFH
c) 00F8H to 00FFH
d) 0000H to FFFFH
Answer: c
Explanation: The I/O port addresses 00F8H to 00FFH are reserved by Intel, hence these should
not be used while designing practical systems around 80286.
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Choice Questions and Answers .
This set of Microprocessors test focuses on “Priority of Bus Use By 80286, Bus Hold and HLDA
Sequence, Interrupt Acknowledge Sequence”.
1. Which of the following is the highest priority usage among them?
a) second transfer cycle of a processor extension data transfer
b) third transfer cycle of a processor extension data transfer
c) hold request
d) second byte transfer of 2-byte transfer at an odd address
Answer: d
Explanation: The second byte transfer of 2-byte transfer at an odd address, is the highest
priority usage among the given usages.
2. The highest priority usage than any other usage is
a) transfer with LOCK
activelow
signal
b) hold request
c) processor extension data transfer
d) data transfer performed by EU
executionunit
Answer: a
Explanation: The transfer with LOCK
activelow
signal is the highest priority usage than any other usage.
3. The lowest priority usage among the following is
a) hold request
b) processor extension data transfer
c) prefetch operation to fetch and arrange next instruction bytes in queue
d) data transfer performed by EU for instruction execution
Answer: c
Explanation: The order of priority usages, starting from the highest one to the lowest one, is
given as
1. transfer with LOCK
activelow
signal
2. second byte transfer of 2-byte transfer at an odd address
3. second or third transfer cycle of a processor extension data transfer
4. HOLD request
5. processor extension data transfer
6. data transfer performed by EU
executionunit
7. prefetch operation to fetch and arrange next instruction bytes in queue.
4. As a response to the valid bus hold request, the bus is pushed into
a) TH
hold
state
b) Ts
status
state
c) Tc
command
state
d) Ti
idle
state
Answer: a
Explanation: 80286 local bus is relinquished for another bus master if a valid bus hold request is
received at the HOLD input pin. As a response to a valid bus hold request, the bus is pushed
into TH state.
5. The bus arbiter relinquishes
a) Address
b) M/IO
activelow
c) COD/INTA
activelow
d) All of the mentioned
Answer: d
Explanation: The address, M/IO
activelow
and COD/INTA
activelow
are relinquished by bus arbiter.
6. A valid HOLD request is ascertained only after the completion of
a) 34 clockcycles
b) 24 clockcycles and 80286 is SET
c) 34 clockcycles and 80286 is SET
d) 34 clockcycles and 80286 is RESET
Answer: d
Explanation: Only after 34 clockcycles, after the 80286 is reset, a valid HOLD request should be
ascertained.
7. The master PIC 8259A decides which of its slave interrupt controllers is to return the vector
address, as a response of
a) first INTA
activelow
pulse from 80286
b) second INTA
activelow
pulse from 80286
c) third INTA
activelow
pulse from 80286
d) none of the mentioned
Answer: a
Explanation: In response to the first INTA
activelow
pulse from 80286, the master PIC 8259A decides, which of its slave interrupt controllers is to
return the vector address.
8. The slave
whichisselected
sends the vector on data bus after the
a) first INTA
activelow
pulse from 80286
b) second INTA
activelow
pulse from 80286
c) third INTA
activelow
pulse from 80286
d) none of the mentioned
Answer: b
Explanation: The interrupt acknowledge sequence consists of two INTA
activelow
pulses. After the second pulse, the selected slave sends the vector on D0-D7 data lines, and
80286 reads it.
9. The signal of 82C288, that enables the cascade address drivers, during INTA cycles is
a) DEN
b) DT/R
activelow
c) MCE
d) MB
Answer: c
Explanation: The MCE
MasterCascadeEnable
signal of 82C288 enables the cascade address drivers during INTA cycles, to select the slave
using the local address bus.
10. The LOCK
activelow
signal is activated during
a) Ti of first INTA cycle
b) Ts of first INTA cycle
c) Th of second INTA cycle
d) Ts of second INTA cycle
Answer: b
Explanation: The LOCK
activelow
signal is activated during Ts of first INTA cycle.
11. The number of idle states
Ti
, that is allowed between two INTA cycles, to meet the 8259A speed and cascade address
output delay is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: The 80286 allows three idle states
Ti
between the two INTA cycles, to meet the 8259A speed and cascade address output delay.
To practice all areas of Microprocessors for tests, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Instruction Set Features -1”.
1. In which of these modes, the immediate operand is included in the instruction itself?
a) register operand mode
b) immediate operand mode
c) register and immediate operand mode
d) none of the mentioned
Answer: b
Explanation: In immediate operand mode, the immediate operand is included in the instruction
itself.
2. In register address mode, the operand is stored in
a) 8-bit general purpose register
b) 16-bit general purpose register
c) si or di
d) all of the mentioned
Answer: d
Explanation: In register address mode, the operand is stored either in one of the 8-bit or 16-bit
general purpose registers or in SI, DI, BX or BP.
3. In which of the following addressing mode, the offset is obtained by adding displacement and
contents of one of the base registers?
a) direct mode
b) register mode
c) based mode
d) indexed mode
Answer: c
Explanation: In a based mode, the offset is obtained by adding displacement and contents of
one of the base registers, either BX or BP.
4. In which of the following addressing mode, the offset is obtained by adding displacement, with
the contents of SI?
a) direct mode
b) register mode
c) based mode
d) indexed mode
Answer: d
Explanation: In an indexed mode, the offset is obtained by adding displacement, with contents
of an index register, either SI or DI.
5. The address of a location of the operand is calculated by adding the contents of any of the
base registers, with the contents of any of index registers in
a) based indexed mode with displacement
b) based indexed mode
c) based mode
d) indexed mode
Answer: b
Explanation: In a based indexed mode, the operand is stored at a location, whose address is
calculated by adding the contents of any of the base registers, with the contents of any of the
index registers.
6. Which of the following is not a data type of 80286?
a) Ordinal or unsigned
b) ASCII
c) Packed BCD
d) None of the mentioned
Answer: d
Explanation: The 80286 supports seven data types. They are
1. integer
2. Ordinal
unsigned
3. pointer
4. string
5. ASCII
6. BCD
7. Packed BCD.
7. The representation of 8-bit or 16-bit signed binary operands using 2’s complement is a data
type of
a) Ordinal
b) ASCII
c) Packed BCD
d) integer
Answer: d
Explanation: In integer data type, 8-bit or 16-bit signed binary operands are represented using
2’s complement.
8. The instruction that pushes the general purpose registers, pointer and index registers on to
the stack is
a) POPF
b) PUSH Imd
c) PUSH*A
d) PUSHF
Answer: c
Explanation: The PUSH*A instruction, pushes the general purpose registers, AX, CX, DX and
BX, pointer and index registers, SP, BP, SI, DI, on to the stack.
9. While executing the PUSH*A instruction, the stack pointer is decremented by
a) 1 bit
b) 2 bits
c) 4 bits
d) 16 bits
Answer: b
Explanation: The stack pointer is decremented by 16
eight2−byteregisters
.
10. The statement that is true for the instruction POP*A is
a) flags are unaffected
b) no operands are required
c) exceptions generated are same as that of PUSH*A
d) all of the mentioned
Answer: d
Explanation: The POP*A instruction, pops all the contents of the registers DI, SI, BP, SP, BX,
DX, CX and AX from the stack in this sequence, that is exactly opposite to that of pushing.
11. The instruction that multiplies the content of AL with a signed immediate operand is
a) MUL
b) SMUL
c) IMUL
d) None of the mentioned
Answer: c
Explanation: The IMUL instruction multiplies the content of AL with a signed immediate operand,
and the signed 16-bit result is stored in AX.
12. The instruction that represents the ‘rotate source, count’ is
a) RCL
b) RCR
c) ROR
d) All of the mentioned
Answer: d
Explanation: The rotate source, count is a group of four instructions containing RCL, RCR, ROL,
ROR.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Quiz focuses on “Instruction Set Features -2”.
1. In ‘Rotate source, count’ instructions, if the CF is equal to MSB of operand
source
then
a) TF is cleared
b) OF is cleared
c) TF is set
d) OF is set
Answer: b
Explanation: If CF is equal to MSB of operand
source
, the overflow flag is cleared, otherwise, it is set to 1.
2. The instruction that affects the flags is
a) IMUL
b) INSW
c) INSB
d) POP*A
Answer: a
Explanation: No flags are affected by the instructions, INSW, INSB and POP*A.
3. A general protection exception is generated, if the value of
a) CPL is equal to that of IOPL
b) CPL is less than that of IOPL
c) CPL is greater than that of IOPL
d) None of the mentioned
Answer: c
Explanation: When the value of CPL is greater than that of IOPL, a general protection exception
is generated.
4. While executing the instruction, OUTSW, the SI is incremented by
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: The SI is automatically incremented by 1 for byte
OUTSB
and 2 for word
OUTSW
operations.
5. The instruction that is used to exit the procedure is
a) QUIT
b) STOP
c) LEAVE
d) EXIT
Answer: c
Explanation: The instruction, LEAVE, is generally used with high level languages, to exit a
procedure.
6. The instruction that determines the number of bytes, to be copied into the new stack frame,
from the previous stack is
a) ENTER
b) BOUND
c) CLTS
d) LEAVE
Answer: a
Explanation: The ENTER instruction prepares a stack structure for parameters of a procedure to
be executed further. This instruction determines the number of bytes to be copied, into the new
stack frame, from the previous stack.
7. The instruction that is used to check whether a signed array offset is within the limit, defined
for it by the starting and ending index is
a) ENTER
b) BOUND
c) CLTS
d) LEAVE
Answer: b
Explanation: The BOUND instruction is used to check whether a signed array offset is within the
limit defined for it, by the starting and ending index.
8. The CLTS
ClearTaskSwitchFlag
instruction records every execution of WAIT and ESC and is trapped if the flag
a) PE
ProtectionEnable
and TS
taskswitch
flags are set
b) Emulate Processor extension flag is set
c) MP flag and task switched flag is set
d) PE and MP flag is set
Answer: c
Explanation: The CLTS
ClearTaskSwitchFlag
instruction records every execution of WAIT and ESC, and is trapped, if the MP flag and task
switched flag is set.
9. The instruction that determines whether the segment pointed to, by a 16-bit register, can be
accessed from the current privilege level is
a) RPL
b) CPL
c) ARPL
d) VERR
Answer: d
Explanation: The VERR/VERW instructions determine whether the segment pointed to, by a
16-bit register, can be accessed from the current privilege level.
10. The instruction that loads 6 bytes from a memory block, pointed to by the effective address
of the operand, into global descriptor table register is
a) LLDT
b) SGDT
c) LGDT
d) None of the mentioned
Answer: c
Explanation: The LGDT
loadglobaldescriptortableregister
loads 6 bytes from a memory block, pointed to by the effective address of the operand, into
global descriptor table register.
11. In LGDT instruction, while loading 6 bytes, the first word is loaded into the field of
a) LIMIT field
b) BASE field
c) Either LIMIT or BASE field
d) None of the mentioned
Answer: a
Explanation: While loading the 6 bytes, the first word is loaded into the LIMIT field of the
descriptor table register. The next three bytes are loaded into the BASE field of the register, and
the remaining byte is ignored.
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Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “80287 Math Coprocessor -1”.
1. Which of the following is not a block of an architecture of 80287?
a) bus control logic
b) data interface and control unit
c) floating point unit
d) none of the mentioned
Answer: d
Explanation: The three blocks of an internal architecture of 80287 are:
1. bus control logic
2. data interface and control unit
3. floating point unit.
2. The unit that provides and controls the interface, between the internal 80287 bus and 80286
bus via data buffer is
a) bus control logic
b) data interface and control unit
c) floating point unit
d) none of the mentioned
Answer: a
Explanation: The bus control logic provides and controls the interface, between the internal
80287 bus and 80286 bus via data buffer.
3. The data interface and control unit consists of
a) status and control words
b) tag words and error pointers
c) instruction decoders
d) all of the mentioned
Answer: d
Explanation: The data interface and control unit contains status and controls words, TAG words
and error pointers.
4. The word that optimizes the NDP performance, by maintaining a record of empty and
non-empty register locations is
a) Status and control words
b) TAG words
c) Error pointers
d) All of the mentioned
Answer: b
Explanation: The TAG word optimizes the NDP performance by maintaining a record of empty
and non-empty register locations. It helps the exception handler to identify special values in the
contents of the stack locations.
5. The part of the data interface and control unit, that points to the source of exception
generated is
a) Status and control words
b) TAG words
c) Error pointers
d) None of the mentioned
Answer: c
Explanation: The error pointers point to the source of exception
addressoftheinstructionthatgeneratedtheexception
generated.
6. The data bus in a floating point unit is of
a) 16 bits
b) 32 bits
c) 64 bits
d) 84 bits
Answer: d
Explanation: The data bus in a floating point unit is of 84-bits. Out of this 84-bits, the lower 68
bits are significant
mantissa
data bit, the next 16 bits are used for the exponent.
7. The arrangement of data that is to be shifted successively, whenever required for the
execution, is done by
a) error pointer
b) data buffer
c) barrel shifter
d) none of the mentioned
Answer: c
Explanation: The barrel shifter arranges and presents the data to be shifted successively,
whenever required for the execution.
8. The word that is used to select one of the processing options, among the provided ones is
a) status word
b) control word
c) status and control words
d) none of the mentioned
Answer: b
Explanation: The control word is used to select one of the processing options, among the ones
provided by 80287.
9. After reset of 80287, the control bit that is initialized to zero is
a) masking bits
b) precision control bits
c) rounding control bits
d) infinity control bits
Answer: d
Explanation: The infinity control bit is initialized to zero after reset.
10. The bits that are modified depending upon the result of the execution of arithmetic
instructions are
a) masking bits
b) rounding control bits
c) condition code bits
d) error summary bits
Answer: c
Explanation: The condition code bits are similar to the flags of a CPU. These are modified
depending upon the result of the execution of arithmetic instructions.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors MCQs focuses on “80287 Math Coprocessor -2”.
1. If the stack flag is set, and condition code bit C1=1, then the stack is
a) full
b) overflown
c) underflown
d) empty
Answer: b
Explanation: If the stack flag is set, and condition code bit C1=1, then the stack has overflown.
2. If the stack flag is set, and condition code bit C1=0, then the stack is
a) full
b) overflown
c) underflown
d) empty
Answer: c
Explanation: If the stack flag is set, and condition code bit C1=0, then the stack has underflown.
3. The bits that affect the result of arithmetic operations like ADD, SUB, MUL, DIV are
a) condition code bits
b) rounding control bits
c) masking bits
d) precision control bits
Answer: d
Explanation: The precision control bits affect ADD, SUB, MUL, DIV and SQRT results.
4. The precision is decided by the
a) opcode
b) extended precision format
c) opcode or extended precision format
d) none of the mentioned
Answer: c
Explanation: For other than the arithmetic instructions
likeADD,SUB,MUL,DIVandSQRT
, the precision is decided by opcode or extended precision format.
5. If Numeric Processor Write
NPWR
active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
Answer: c
Explanation: If Numeric Processor Write
NPWR
active-low input pin is activated, then it enables a data transfer from 80286 to 80287.
6. If Numeric Processor Read
NPRD
active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
Answer: b
Explanation: If Numeric Processor Read
NPRD
active-low input pin is activated, then it enables a data transfer from 80287 to 80286.
7. Which of the input line
indicate that the CPU is performing an escape operation, and enables 80287 to execute the
next instruction?
a) NPWR
activelow
and NPRD
activelow
b) NPS1 and NPS2
activelow
c) NPS1
activelow
and NPS2
d) CMD0 and CMD1
Answer: c
Explanation: The Numeric Processor select input lines, NPS1
activelow
and NPS2, indicate that the CPU is performing an escape operation, and enables 80287 to
execute the next instruction.
8. For which pin of 80286 is the active low pin, BUSY of 80287, connected?
a) ERROR
activelow
b) BUSY
activelow
c) HLDA
d) TEST
activelow
Answer: d
Explanation: The BUSY
activelow
is connected to the TEST
activelow
pin of 80286.
9. If Clock Mode
CM
input pin is held low, then the CLK input is divided by
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: If Clock Mode
CM
input pin is held high, then the CLK input is directly used for deriving the internal timings. Else,
it is divided by 2.
10. Which of the following pin is not involved in the interface of 80287 with 80286?
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answer: c
Explanation: The 10 pins, PEREQ, PEACK#, BUSY#, ERROR#, NPRD
activelow
#, NPWR
activelow
#, NPS1
activelow
#, NPS2#, CMD0 and CMD1.
11. The PEACK
activelow
when activated, the pin that goes into deactivation is
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answer: a
Explanation: When the data transfer is over, the CPU activates PEACK
activelow
# pin, which results in deactivating the PEREQ pin by 80287.
To practice MCQs on all areas of Microprocessors, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Salient Features of 80386DX”.
1. The 80386DX is a processor that supports
a) 8-bit data operand
b) 16-bit data operand
c) 32-bit data operand
d) all of the mentioned
Answer: d
Explanation: The 80386DX is a 32-bit processor that supports, 8-bit/16-bit/32-bit data operands.
2. The 80386DX has an address bus of
a) 8 address lines
b) 16 address lines
c) 32 address lines
d) 64 address lines
Answer: c
Explanation: The 80386, with its 32-bit address bus, can address up to 4 GB of physical
memory.
3. The number of debug registers that are available in 80386, for hardware debugging and
control is
a) 2
b) 4
c) 8
d) 16
Answer: c
Explanation: The 80386 offers a set of total eight debug registers DR0-DR7, for hardware
debugging and control.
4. The memory management of 80386 supports
a) virtual memory
b) paging
c) four levels of protection
d) all of the mentioned
Answer: d
Explanation: The memory management section of 80386 supports the virtual memory, paging
and four levels of protection, maintaining full compatibility with 80286.
5. The 80386 enables itself to organize the available physical memory into pages, which is
known as
a) segmentation
b) paging
c) memory division
d) none of the mentioned
Answer: b
Explanation: The concept of paging which is introduced in 80386, enables it to organize the
available physical memory into pages of size 4 KB each, under the segmented memory.
6. The 80386 consists of
a) on-chip address translation cache
b) instruction set of predecessors with upward compatibility
c) virtual memory space of 64TB
d) all of the mentioned
Answer: d
Explanation: The 80386 has on-chip address translation cache, and the instruction set is
upward compatible with all its predecessors.
7. 80386DX is available in a grid array package of
a) 64 pin
b) 128 pin
c) 132 pin
d) 142 pin
Answer: c
Explanation: The 80386DX is available in a 132-pin grid array package.
8. The operating frequency of 80386DX is
a) 12 MHz and 20 MHz
b) 20 MHz and 33 MHz
c) 32 MHz and 12 MHz
d) all of the mentioned
Answer: b
Explanation: The operating frequency of 80386DX is 20MHz and 33 MHz.
9. The 80386 in its protected mode, in its virtual mode of operation, can run the applications of
a) 8086
b) 80286
c) 80287
d) 80387
Answer: a
Explanation: The 80386 can run the applications under protected mode, in its virtual 8086 mode
of operation.
10. The 80386 in protected mode, supports all software written for
a) 8086 and 80287
b) 80286 and 80287
c) 80287 and 80387
d) 80286 and 8086
Answer: d
Explanation: The 80386 in protected mode, supports all software written for 8086 and 80286
tobeexecutedunderthecontrolofmemorymanagementandprotectionabilitiesof80386
.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Architecture and Signal Descriptions of 80386”.
1. Which of the units is not a part of the internal architecture of 80386?
a) central processing unit
b) memory management unit
c) bus interface unit
d) none of the mentioned
Answer: d
Explanation: The internal architecture of 80386 is divided into three sections namely, central
processing unit, memory management unit and bus interface unit.
2. The central processing unit has a sub-division of
a) memory unit and control unit
b) memory unit and ALU
c) execution unit and instruction unit
d) execution unit and memory unit
Answer: c
Explanation: The central processing unit is further divided into the execution unit and instruction
unit.
3. The unit that is used for handling data, and calculates offset address is
a) memory management unit
b) execution unit
c) instruction unit
d) bus interface unit
Answer: b
Explanation: The execution unit has eight general purpose and eight special purpose registers,
which are either used for handling the data or calculating the offset addresses.
4. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
Answer: c
Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte
instruction code queue, after decoding them so as to pass it to the control section, for deriving
the necessary control signals.
5. The unit that increases the speed of all shift and rotate operations is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
Answer: d
Explanation: The barrel shifter speeds up all shift and rotate operations.
6. The memory management unit consists of
a) segmentation unit
b) paging unit
c) segmentation and paging units
d) none of the mentioned
Answer: c
Explanation: The memory management unit consists of a segmentation unit and a paging unit.
7. The segmentation unit allows
a) maximum size of 4GB segments
b) use of segment address components
c) use of offset address components
d) all of the mentioned
Answer: d
Explanation: The segmentation unit allows the use of two address components. They are:
segment and offset for relocation and sharing of code and data.
8. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit
b) execution unit
c) paging unit
d) instruction unit
Answer: c
Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size
each.
9. The paging unit works under the control of
a) memory management unit
b) segmentation unit
c) execution unit
d) instruction unit
Answer: b
Explanation: The paging unit works under the control of the segmentation unit; i.e. each
segment is further divided into pages.
10. The unit that provides a four level protection mechanism, for system’s code and data against
application program is
a) central processing unit
b) segmentation unit
c) bus interface unit
d) none of the mentioned
Answer: b
Explanation: The segmentation unit provides a four level protection mechanism, for protecting
and isolating the system’s code and data, from those of the application program.
11. The unit that has a prioritizer to resolve the priority of the various bus requests is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
Answer: c
Explanation: The bus control unit has a prioritizer to resolve the priority of the various bus
requests.
12. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
Answer: b
Explanation: The data buffer interfaces the internal data bus with the system bus.
13. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit
b) bus driving unit
c) address driver
d) bus driver
Answer: c
Explanation: The address driver drives the bus enable and address signals A0-A31.
14. Which of the following pin when activated, allows address pipelining?
a) ADS
b) NA
c) AP
d) None of the mentioned
Answer: b
Explanation: The Next Address
NA
input pin, if activated, allows address pipelining, during 80386 bus cycles.
15. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD
b) HLDA
c) READY
d) PEREQ
Answer: c
Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for
interfacing of slow devices with the CPU.
16. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY
b) NMI
c) HLDA
d) PEREQ
Answer: d
Explanation: The Processor Extension Request
PEREQ
output signal indicates to the CPU to fetch a data word for the coprocessor.
17. The pipeline and dynamic bus sizing units handle
a) data signals
b) address signals
c) control signals
d) all of the mentioned
Answer: c
Explanation: The pipeline and dynamic bus sizing units handle the related control signals.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Register Organisation of 80386 -1”.
1. The 16-bit registers are available with their extended size of 32 bits, by adding the registers
with a prefix of
a) X
b) E
c) 32
d) XX
Answer: b
Explanation: A 32 bit register, known as an extended register, is represented by the register
name with a prefix of E.
2. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by
a) LSP
b) FSP
c) SP
d) None of the mentioned
Answer: c
Explanation: Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the
names BP, SP, SI and DI represent the lower 16-bits.
3. Which of the following is a data segment register of 80386?
a) ES
b) FS
c) GS
d) All of the mentioned
Answer: d
Explanation: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out
of which DS, ES, FS and GS are the four data segment registers.
4. The register width used by the 32-bit addressing modes is
a) 8 bits
b) 16 bits
c) 32 bits
d) all of the mentioned
Answer: d
Explanation: The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.
5. The flag that is additional in flag register of 80386, compared to that of 80286 is
a) VM flag
b) RF flag
c) VM and RF flag
d) None of the mentioned
Answer: c
Explanation: The VM and RF flags are added to the 80286 flag register, to derive the flag
register of 80386.
6. The VM
virtualmode
flag is to be set, only when 80386 is in
a) virtual mode
b) protected mode
c) either virtual or protected mode
d) all of the mentioned
Answer: b
Explanation: If VM flag is set, the 80386 enters the virtual 8086 mode within the protected
mode. This is to be set only when the 80386 is in protected mode.
7. In protected mode of 80386, the VM flag is set by using
a) IRET instruction
b) Task switch operation
c) IRET instruction or task switch operation
d) None of the mentioned
Answer: c
Explanation: The VM flag can be set using the IRET instruction or any task switch operation,
only in the protected mode.
8. During the instruction cycle of 80386, any debug fault can be ignored if
a) VM flag is set
b) VM flag is cleared
c) RF is cleared
d) RF is set
Answer: d
Explanation: If RF
resumeflag
is set, any debug fault is ignored during the instruction cycle.
9. The RF is not automatically reset after the execution of
a) IRET
b) POPA
c) IRET and POPF
d) IRET and PUSHF
Answer: c
Explanation: The RF is automatically reset after the execution of every instruction, except for the
IRET and POPF instructions. Also, it is not cleared automatically after the successful execution
of JMP, CALL and INT instructions causing a task switch.
10. The segment descriptor register is used to store
a) attributes
b) limit address of segments
c) base address of segments
d) all of the mentioned
Answer: d
Explanation: The segment descriptor register is used to store the descriptor information like
attributes, limit and base addresses of segments.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Multiple Choice Questions & Answers focuses on “Register
Organisation of 80386 -2”.
1. The 32-bit control register, that is used to hold global machine status, independent of the
executed task is
a) CR0
b) CR2
c) CR3
d) All of the mentioned
Answer: d
Explanation: The 80386 has three 32-bit control registers CR0, CR2 and CR3, to hold global
machine status, independent of the executed task.
2. The descriptor table that the 80386 supports is
a) GDT
Globaldescriptortable
b) IDT
Interruptdescriptortable
c) LDT
Localdescriptortable
d) All of the mentioned
Answer: d
Explanation: The 80386 supports four types of descriptor tables. They are, GDT, IDT, LDT and
TSS.
3. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR
Answer: a
Explanation: The GDTR and IDTR are known as system address registers.
4. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) None of the mentioned
Answer: b
Explanation: The LDTR and TR are known as system segment registers.
5. The test register
that is provided by 80386 for page caching is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers
Answer: c
Explanation: Two test registers are provided by 80386 for page caching, namely test control and
test status registers.
6. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7
Answer: b
Explanation: Out of the eight debug registers, the two registers DR4 and DR5 are Intel reserved.
7. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3
Answer: d
Explanation: The initial four registers, DR0-DR3 store four program controllable break point
addresses.
8. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned
Answer: a
Explanation: The registers DR6 and DR7 respectively hold break point status and break point
control information.
9. The flag bits that indicate the privilege level of current IO operations are
a) Virtual mode flag bits
b) IOPL flag bits
c) Resume flag bits
d) None of the mentioned
Answer: b
Explanation: The IOPL flag bits indicate the privilege level of current IO operations.
10. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers
Answer: c
Explanation: The segment descriptor registers of 80386 are not available for programmers,
rather, they are internally used to store the descriptor information.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Addressing Modes of 80386, Data Types of 80386”.
1. Which of the following is not a scale factor of addressing modes of 80386?
a) 2
b) 4
c) 6
d) 8
Answer: c
Explanation: In case of the scaled the modes, any of the index register values can be multiplied
by a valid scale factor to obtain the displacement. The valid scale factors are 1, 2, 4 and 8.
2. Contents of an index register are multiplied by a scale factor that may be added further to get
the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
Answer: b
Explanation: In scaled indexed mode, contents of an index register are multiplied by a scale
factor that may be added further to get the operand offset.
3. Contents of an index register are multiplied by a scale factor and then added to base register
to get the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
Answer: a
Explanation: In base scaled indexed mode, contents of an index register are multiplied by a
scale factor and then added to base register to get the operand offset.
4. In the based scaled indexed mode with displacement mode, the contents of an index register
are multiplied by a scale factor and are added to
a) base register
b) displacement
c) base register and displacement
d) none of the mentioned
Answer: c
Explanation: Contents of an index register are multiplied by a scale factor and the result is
added to a base register and a displacement to get the offset of an operand.
5. The following statement of ALP is an example of
MOV EBX, [EDX*4] [ECX].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
Answer: a
Explanation: Since in base scaled indexed mode, contents of an index register are multiplied by
a scale factor and then added to base register to get the operand offset.
6. The following statement is an example of
MOV EBX, LIST [ESI*2].
MUL ECX, LIST [EBP*4].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
Answer: b
Explanation: Since in scaled indexed mode, contents of an index register are multiplied by a
scale factor that may be added further to get the operand offset.
7. Bit field can be defined as a group of
a) 8 bits
b) 16 bits
c) 32 bits
d) 64 bits
Answer: c
Explanation: A group of at the most 32 bits
4bytes
is defined as a bit field.
8. The maximum length of the string in a bit string of contiguous bits is
a) 2 MB
b) 4 MB
c) 2 GB
d) 4 GB
Answer: d
Explanation: Bit string is a string of contiguous bits of maximum 4Gbytes in length.
9. The integer word is defined as
a) signed 8-bit data
b) unsigned 16-bit data
c) signed 16-bit data
d) signed 32-bit data
Answer: c
Explanation: The integer word is the signed 16-bit data.
10. A 16-bit displacement that references a memory location using any of the addressing modes
is
a) Pointer
b) Character
c) BCD
d) Offset
Answer: d
Explanation: Offset is a 16-bit or 32-bit displacement that references a memory location using
any of the addressing modes.
11. A decimal digit can be represented by
a) unsigned integer
b) signed integer
c) unpacked BCD
d) packed BCD
Answer: c
Explanation: Decimal digits from 0-9 are represented by unpacked bytes.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Real Address Mode of 80386, Protected Mode of 80386”.
1. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned
Answer: b
Explanation: All the instructions of 80386 are available in this mode except for those designed to
work with or for protected address mode.
2. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit
Answer: c
Explanation: The paging unit is disabled in real address mode.
3. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned
Answer: d
Explanation: To form a physical memory address, appropriate segment register contents are
shifted by left by 4 positions and then added to 16-bit offset address formed using one of
addressing modes, in same way as in the 80386 real address mode.
4. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d) none of the mentioned
Answer: c
Explanation: The segments in 80386 real mode are may be overlapped or non-overlapped.
5. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned
Answer: d
Explanation: The segments in 80386 real mode can be read, written or executed, i.e. no
protection is available.
6. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned
Answer: d
Explanation: In protected mode, the contents of segment registers are used as selectors to
address descriptors which contain the segment limit, base address and access rights byte of the
segment.
7. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address
Answer: a
Explanation: The effective address
offset
is added with segment base address to calculate linear address.
8. If the paging unit is enabled, then it converts a linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
Answer: b
Explanation: The paging unit when enabled, it converts a linear address into physical address.
9. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
Answer: b
Explanation: The linear address is used as a physical address if the paging unit is disabled.
10. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned
Answer: c
Explanation: The paging unit is enabled only in protected mode.
11. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB
Answer: d
Explanation: In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of
virtual memory per task.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Segmentation”.
1. The bit that indicates whether the segment has been accessed by the CPU or not is
a) base address
b) attribute bit
c) present bit
d) granular bit
Answer: b
Explanation: The accessed bit or attribute bit
A
indicates whether the segment has been accessed by the CPU or not.
2. The TYPE field of a descriptor is used to find the
a) descriptor type
b) segment type
c) descriptor and segment type
d) none
Answer: c
Explanation: The type field decides the descriptor type and hence the segment type.
3. If the segment descriptor bit, S=0, then the descriptor is
a) data segment descriptor
b) code segment descriptor
c) system descriptor
d) all of the mentioned
Answer: c
Explanation: If S=0, then system descriptor. If S=1, then code or data segment descriptor.
4. The bit that indicates whether the segment is page addressable is
a) base address
b) attribute bit
c) present bit
d) granularity bit
Answer: d
Explanation: The granularity bit indicates whether the segment is page addressable.
5. If the Default operation size bit, D=1, the code segment operation size selected is
a) 8-bit
b) 16-bit
c) 32-bit
d) 64-bit
Answer: c
Explanation: If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand
segment.
6. The segment descriptor contains
a) access rights
b) limit
c) base address
d) all of the mentioned
Answer: d
Explanation: The segment descriptors are 8-byte quantities containing access right or attribute
bits along with the base and limit of the segments.
7. Which of the following is not a type of segment descriptor?
a) system descriptors
b) local descriptors
c) gate descriptors
d) none
Answer: d
Explanation: The five types of segment descriptors of 80386 are:
1. Code or data segment descriptors
2. System descriptors
3. Local descriptors
4. TSS
taskstatesegment
descriptors
5. Gate descriptors.
8. The limit field of the descriptor is of
a) 10 bits
b) 8 bits
c) 16 bits
d) 20 bits
Answer: d
Explanation: The limit field of the descriptor is of 20 bits.
9. The starting address of the segment in physical memory is decided by
a) physical memory
b) segment descriptors
c) operating system
d) base address
Answer: c
Explanation: The base address that marks the starting address of the segment in physical
memory is decided by the operating system and is of 32 bits.
10. The total descriptors that the 80386 can handle is
a) 2K
b) 8K
c) 4K
d) 16K
Answer: d
Explanation: 80386 can handle total 16K descriptors and hence segments.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Paging”.
1. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
Answer: d
Explanation: The advantage of paging scheme is that the complete segment of a task need not
be in the physical memory at any time. Only a few pages of the segments, which are required
currently for the execution, need to be available in the physical memory.
2. The size of the pages in the paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
Answer: b
Explanation: The paging divides the memory into fixed size pages.
3. To convert linear addresses into physical addresses, the mechanism that the paging unit uses
is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
Answer: d
Explanation: The paging unit of 80386 uses a two level table mechanism, to convert the linear
addresses provided by the segmentation unit, into physical addresses.
4. The control register that stores the 32-bit linear address, at which the previous page fault is
detected is
a) CR0
b) CR1
c) CR2
d) CR3
Answer: c
Explanation: The control register, CR2, is used to store the 32-bit linear address, at which the
previous page fault is detected.
5. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
Answer: b
Explanation: The paging unit handles every task in terms of three components namely page
directory, page table and the page itself.
6. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
Answer: d
Explanation: The control register, CR3, is used as page directory physical base address
register, to store the physical starting address of the page directory.
7. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
Answer: d
Explanation: The lower 12 bits of CR3 are always zero to ensure the page size aligned with the
directory.
8. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
Answer: b
Explanation: Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a
directory.
9. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
Answer: c
Explanation: Each page table is of 4 Kbytes in size, and may contain a maximum of 1024
entries.
10. The dirty bit
is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
Answer: a
Explanation: The dirty bit
D
is set before a write operation to the page is carried out.
11. The bit that is undefined for page directory entries is
a) P-bit
b) A-bit
c) D-bit
d) All of the mentioned
Answer: c
Explanation: The D-bit is undefined for page directory entries.
12. The bit that is used for providing protection is
a) User/Supervisor bit
b) Read bit
c) Write bit
d) all of the mentioned
Answer: d
Explanation: The User/Supervisor
U/S
bit and Read/Write
R/W
bit are used to provide protection.
13. The storage of 32 recently accessed page table entries to optimize the time, is known as
a) page table
b) page descriptor base register
c) page table cache
d) none of the mentioned
Answer: c
Explanation: To optimize the considerable time taken for conversion, a page table cache is
provided, which stores the 32 recently accessed page table entries.
14. The page table cache is also known as
a) page table storage
b) storage buffer
c) translation look aside buffer
d) all of the mentioned
Answer: c
Explanation: The page table cache is also known as translation look aside buffer.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Virtual 8086 Mode, the Coprocessor 80387”.
1. If the 80386 enters the protected mode from the real address mode, then it returns back to
the real mode, by performing the operation of
a) read
b) write
c) terminate
d) reset
Answer: d
Explanation: If the 80386 enters the protected mode from the real address mode, then it cannot
return back to the real mode without a reset operation.
2. The unit that is needed for virtual mode 80386, only to run the 8086 programs, which require
more than 1 Mbyte of memory for memory management functions, is
a) execution unit
b) central processing unit
c) paging unit
d) segmentation unit
Answer: c
Explanation: Paging unit is not necessarily enabled in the virtual mode, but may be needed to
run the 8086 programs, which require more than 1 Mbyte of memory, for memory management
functions.
3. The number of pages that the paging unit allows, in the virtual mode of 80386 is
a) 64
b) 128
c) 256
d) 512
Answer: c
Explanation: In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size. Each
of the pages may be located anywhere within the maximum 4Gbytes physical memory.
4. The privilege level at which the real mode programs are executed is
a) level 0
b) level 1
c) level 2
d) level 3
Answer: a
Explanation: The real mode programs are executed at the highest privilege level i.e. level 0.
5. The instructions to prepare the processor for protected mode can only be executed at the
privilege level
a) level 0
b) level 1
c) level 2
d) level 3
Answer: a
Explanation: The instructions to prepare the processor for protected mode can only be executed
at the level 0.
6. The instruction that is unable to set or read the VM
VirtualMode
bit is
a) PUSHF
b) IRET
c) POPF
d) PUSHF and POPF
Answer: d
Explanation: The PUSHF and POPF instructions are unable to set or read the VM
VirtualMode
bit, as they do not access it. The virtual mode can be entered by using IRET instruction.
7. If the CKM pin of 80387 is high, then 80387 is operated in
a) real address mode
b) protected mode
c) synchronous mode
d) asynchronous mode
Answer: c
Explanation: If the CKM pin of 80387 is high, then 80387 is operated in synchronous mode. If it
is low, then 80387 is operated in asynchronous mode.
8. The unit that handles the data and directs it to either FIFO or instruction decoder depending
on the bus control logic directive is
a) paging unit
b) central processing unit
c) segmentation unit
d) data interface and control unit
Answer: d
Explanation: The data interface and control unit handles the data, and direct it to either FIFO or
instruction decoder, depending on the bus control logic directive.
9. The unit that is responsible for carrying out all the floating point calculations, allotted to the
coprocessor by 80386, is
a) Central processing unit
b) ALU
c) FPU
d) None of the mentioned
Answer: c
Explanation: The FPU
floatingpointunit
is responsible for carrying out all the floating point calculations, allotted to the coprocessor by
80386.
10. The sizes of instruction and data pointer registers of 80387 respectively are
a) 32-bit, 32-bit
b) 48-bit, 32-bit
c) 32-bit, 48-bit
d) 48-bit, 48-bit
Answer: d
Explanation: 80387 consists of two 48-bit registers, known as instruction and data pointer
registers.
11. To inform 80387 that the CPU wants to communicate with NPS1, the NPS1 line is directly
connected to
a) A31
b) A30
c) M/IO
d) D31
Answer: c
Explanation: The NPS1 and NPS2 lines are directly connected with M/IO and A31 respectively,
to inform 80387 that the CPU wants to communicate with it
NPS1
, and it is using one of the reserved I/O addresses for 80387
NPS2
.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Enhanced Instruction Set of 80386”.
1. Which of the following is not a newly added instruction of 80386, that are not present in
80286?
a) bit scan instructions
b) bit test instructions
c) shift double instructions
d) none of the mentioned
Answer: d
Explanation: The newly added instructions of 80386 are categorized into
1. bit scan instructions
2. bit test instructions
3. conditional set byte instructions
4. shift double instructions
5. control transfer via gates instructions.
2. The BSF
bitscanforward
instruction scans the operand in the order
a) from left to right
b) from right to left
c) from upper nibble
d) none of the mentioned
Answer: b
Explanation: The BSF
bitscanforward
instruction scans the operand from right to left.
3. The BSR
bitscanreverse
instruction scans the operand in the order
a) from left to right
b) from right to left
c) from upper nibble
d) none of the mentioned
Answer: a
Explanation: The BSR
bitscanreverse
instruction scans the operand from left to right.
4. If a ‘1’ is encountered when an operand is scanned by BSF, then
a) zero flag is reset
b) zero flag is set
c) VM flag is set
d) RF flag is reset
Answer: b
Explanation: The BSF instruction scans the operand from right to left. If a ‘1’ is encountered
during the scan, zero flag is set, and the bit position of ‘1’ is stored into the destination operand.
5. If a ‘1’ is not encountered when an operand is scanned by BSR, then
a) zero flag is reset
b) zero flag is set
c) VM flag is reset
d) RF flag is set
Answer: a
Explanation: The BSR instruction scans the operand from left to right. If a ‘1’ is not encountered
during the scan, zero flag is reset whether the scan is BSF or BSR.
6. Which of the following is not a bit test instruction?
a) BTC
b) BTS
c) BSF
d) BTR
Answer: c
Explanation: The instruction, BSF, is a bit scan instruction. The four bit test instructions are:
BT
TestaBit
, BTC
TestaBitandComplement
, BTR
TestandResetaBit
and BTS
TestandSetabit
.
7. In case of BT instruction, if the bit position in the destination operand specified by the source
operand, is ‘1’, then
a) zero flag is reset
b) carry flag is set
c) VM flag is set
d) RF flag is reset
Answer: b
Explanation: In case of BT instruction, if the bit position in the destination operand specified by
the source operand, is ‘1’, the carry flag is set, otherwise it is cleared.
8. Which of the following is not a conditional set byte instruction?
a) SETNP
b) SETO
c) SETNAE
d) SHRD
Answer: d
Explanation: The SHRD
ShiftRightDouble
is a shift double instruction.
9. The instruction that shifts the specified number of bits in the instruction, from the upper side
of the source operand into the lower side of the destination operand is
a) SHRD
b) SHLD
c) SETNS
d) None of the mentioned
Answer: b
Explanation: The SHLD instruction shifts the specified number of bits in the instruction, from the
upper side
i.e.MSB
of the source operand into the lower side
i.e.LSB
of the destination operand.
10. The instruction that shifts 8 LSB bits of ECX into the MSB positions of EAX, one by one
starting from LSB of ECX is
a) SHLD ECX,EAX,8
b) SHLD EAX,ECX,8
c) SHRD ECX,EAX,8
d) SHRD EAX,ECX,8
Answer: d
Explanation: The SHRD instruction shifts the specified number of bits in the instruction, from the
lower side
i.e.LSB
of the source operand into the upper side
i.e.MSB
of the destination operand.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Numeric Coprocessor – 80486DX”.
1. The first processor with an inbuilt floating point unit is
a) 80386
b) 80486
c) 80286
d) 8086
Answer: b
Explanation: The 32-bit CPU 80486 from Intel is the first processor with an inbuilt floating point
unit. 80486DX is the first CPU with an on chip floating point unit.
2. Which of the following signal is handled by bus control and request sequencer?
a) ADS#
b) PWT
c) RDY#
d) All of the mentioned
Answer: d
Explanation: The bus control and request sequencer handle the signals like ADS#, PWT, RDY#,
W/R#, INTR, NMI, LOCK#, HOLD, HLDA, RESET and M/IO# which basically controls the bus
access and operations.
3. The unit that subjects the processor operation to boundary scan tests is
a) parity generation and control unit
b) prefetcher unit
c) boundary scan and control unit
d) segmentation unit
Answer: c
Explanation: The boundary scan and control unit subjects the processor operation to boundary
scan tests to ensure the correct operation of various components of the mother board.
4. The management of the virtual memory of the system and adequate protection to data or
codes in the physical memory is provided by
a) segmentation unit
b) paging unit
c) attribute PLA
d) all of the mentioned
Answer: d
Explanation: The segmentation unit, paging unit, attribute PLA, descriptor registers, translation
look aside buffer and limit work together to manage the virtual memory of the system and
provide the adequate protection to the codes or data in the physical memory.
5. The flag that is added to 80486 in additional to the flags similar to 80386 is
a) alignment check flag
b) parity check flag
c) conditional flag
d) all of the mentioned
Answer: a
Explanation: The register set of 80486 is similar to that of the 80386 but only a flag called as
alignment check flag is added to the flag register of 80386 to obtain the flag register of 80486.
6. The major limitation of 80386-387 system is
a) low speed
b) 80386 sends data using an I/O handshake technique
c) 80386 returns to real mode by reset operation
d) none of the mentioned
Answer: b
Explanation: The major limitation of 80386-387 system is that the 80386 sends instruction or
data to 80387 using an I/O handshake technique. To perform this handshaking and to carry
additional house keeping tasks, 80386 requires 15 clock cycles or more.
7. The datatype that the 80486 doesnot support is
a) Signed and unsigned
b) ASCII
c) Floating point
d) None
Answer: d
Explanation: The datatypes that 80486 supports are
1. Signed
2. Unsigned
3. Floating point
4. BCD
5. String
6. ASCII.
8. In Little Endian data format, the data is stored as
a) MSB is stored at lower memory address and LSB at higher memory address
b) LSB is stored at lower memory address and MSB at higher memory address
c) MSB is stored at general purpose registers
d) LSB is stored at general purpose registers
Answer: b
Explanation: In Little Endian data format, for a data of size bigger than 1 byte, the LSB is stored
at lower memory address and MSB at higher memory address.
9. The on-chip cache is used for storing
a) addresses of data
b) opcodes and data
c) data and their addresses
d) opcodes and their addresses
Answer: b
Explanation: The unique feature of 80486 that is not available in 80386 is that the on-chip is
used for storing opcodes and data.
10. The on-chip cache is controlled by
a) Cache disable
CD
b) No write through
NW
c) Cache disable and No write through
d) None of the mentioned
Answer: c
Explanation: Cache disable
CD
and No write through
NW
bits of control register CR0. To completely disable cache, the CD and NW bits must be 11.
11. The on-chip cache can be flushed using external hardware using
a) FLUSH pin
b) TERMINATE pin
c) FLOW pin
d) Pin FLUSH# or using software
Answer: d
Explanation: The on-chip cache can be flushed using external hardware using pin FLUSH# or
using the software. The flushing operation clears all the valid bits for all the cache lines.
To practice all areas of Microprocessors and Micro-controllers, here is complete set of 1000+
Multiple Choice Questions and Answers .
This set of Microprocessors online test focuses on “Features of 80586
Pentium
, Concepts of Computer Architecture, Branch Prediction”.
1. The salient feature of Pentium is
a) superscalar architecture
b) superpipelined architecture
c) superscalar and superpipelined architecture
d) none of the mentioned
Answer: c
Explanation: The salient feature of Pentium is its superscalar, superpipelined architecture.
2. The number of stages of the integer pipeline, U, of Pentium is
a) 2
b) 4
c) 3
d) 6
Answer: b
Explanation: The Pentium has two integer pipelines, U and V, where each one is a 4-stage
pipeline.
3. Which of the following is a cache of Pentium?
a) data cache
b) data cache and instruction cache
c) instruction cache
d) none of the mentioned
Answer: b
Explanation: The Pentium has two separate caches. They are data cache and instruction cache.
4. The speed of integer arithmetic of Pentium is increased to a large extent by
a) on-chip floating point unit
b) superscalar architecture
c) 4-stage pipelines
d) all of the mentioned
Answer: c
Explanation: The Pentium has two integer pipelines, U and V, where each one is a 4-stage
pipeline. This enhances the speed of integer arithmetic of Pentium to a large extent.
5. For enhancement of processor performance, beyond one instruction per cycle, the computer
architects employ the technique of
a) super pipelined technique
b) multiple instruction issue
c) super pipelined technique and multiple instruction issue
d) none of the mentioned
Answer: b
Explanation: For enhancement of processor performance, beyond one instruction per cycle, the
computer architects employ the technique of multiple instruction issue.
6. Which of the following is a class of architecture of MII
multipleinstructionissue
a) super pipelined architecture
b) multiple instruction issue
c) very small instruction word architecture
d) super scalar architecture
Answer: d
Explanation: The MII architecture may again be classified into two categories:
1. Very long instruction word architecture
2. Superscalar architecture.
7. The compiler reorders the sequential stream of code that is coming from memory into a fixed
size instruction group in
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) super scalar architecture
Answer: c
Explanation: In VLIW processors, the compiler reorders the sequential stream of code that is
coming from memory into a fixed size instruction group, and issues them in parallel for
execution.
8. The architecture in which the hardware decides which instructions are to be issued
concurrently at run time is
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) superscalar architecture
Answer: d
Explanation: In the superscalar architecture, the hardware decides which instructions are to be
issued concurrently at run time.
9. The CPU has to wait until the execution stage to determine whether the condition is met in
a) unconditional branch
b) conditional branch
c) pipelined execution branch
d) none of the mentioned
Answer: b
Explanation: In conditional branch, the CPU has to wait until the execution stage to determine
whether the condition is met or not. When the condition satisfies, a branch is to be taken.
10. The memory device that holds branch target addresses for previously executed branches is
a) Tristate buffer
b) RAM
c) ROM
d) Branch target buffer
Answer: d
Explanation: The branch target buffer in Pentium CPU holds branch target addresses for
previously executed branches.
11. The branch target buffer is
a) four-way set-associative memory
b) has branch instruction address
c) has destination address
d) all of the mentioned
Answer: d
Explanation: The branch target buffer is a four-way set-associative memory. Whenever a branch
is taken, the CPU enters the branch instruction address, and also the destination address in the
branch target buffer.
To practice all areas of Microprocessors for online tests, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “System Architecture”.
1. The stage in which the CPU fetches the instructions from the instruction cache in superscalar
organization is
a) Prefetch stage
b) D1
firstdecode
stage
c) D2
seconddecode
stage
d) Final stage
Answer: a
Explanation: In the prefetch stage of pipeline, the CPU fetches the instructions from the
instruction cache, which stores the instructions to be executed. In this stage, CPU also aligns
the codes appropriately.
2. The CPU decodes the instructions and generates control words in
a) Prefetch stage
b) D1
firstdecode
stage
c) D2
seconddecode
stage
d) Final stage
Answer: b
Explanation: In D1 stage, the CPU decodes the instructions and generates control words. For
simple RISC instructions, only single control word is enough for starting the execution.
3. The fifth stage of pipeline is also known as
a) read back stage
b) read forward stage
c) write back stage
d) none of the mentioned
Answer: c
Explanation: The fifth stage or final stage of pipeline is also known as “Write back
WB
stage”.
4. In the execution stage the function performed is
a) CPU accesses data cache
b) executes arithmetic/logic computations
c) executes floating point operations in execution unit
d) all of the mentioned
Answer: d
Explanation: In the execution stage, known as E-stage, the CPU accesses data cache,
executes arithmetic/logic computations, and floating point operations in execution unit.
5. The stage in which the CPU generates an address for data memory references in this stage
is
a) prefetch stage
b) D1
firstdecode
stage
c) D2
seconddecode
stage
d) execution stage
Answer: c
Explanation: In the D2
seconddecode
stage, CPU generates an address for data memory references in this stage. This stage is
required where the control word from D1 stage is again decoded for final execution.
6. The feature of separated caches is
a) supports the superscalar organization
b) high bandwidth
c) low hit ratio
d) all of the mentioned
Answer: d
Explanation: The separated caches have low hit ratio compared to a unified cache, but have the
advantage of supporting the superscalar organization and high bandwidth.
7. In the operand fetch stage, the FPU
FloatingPointUnit
fetches the operands from
a) floating point unit
b) instruction cache
c) floating point register file or data cache
d) floating point register file or instruction cache
Answer: c
Explanation: In the operand fetch stage, the FPU
FloatingPointUnit
fetches the operands from either floating point register file or data cache.
8. The FPU
FloatingPointUnit
writes the results to the floating point register file in
a) X1 execution state
b) X2 execution state
c) write back stage
d) none of the mentioned
Answer: c
Explanation: In the two execution stages of X1 and X2, the floating point unit reads the data
from the data cache and executes the floating point computation. In the “write back stage” of
pipeline, the FPU
FloatingPointUnit
writes the results to the floating point register file.
9. The floating point multiplier segment performs floating point multiplication in
a) single precision
b) double precision
c) extended precision
d) all of the mentioned
Answer: d
Explanation: The floating point multiplier segment performs floating point multiplication in single
precision, double precision and extended precision.
10. The instruction or segment that executes the floating point square root instructions is
a) floating point square root segment
b) floating point division and square root segment
c) floating point divider segment
d) none of the mentioned
Answer: c
Explanation: The floating point divider segment executes the floating point division and square
root instructions.
11. The floating point rounder segment performs rounding off operation at
a) after write back stage
b) before write back stage
c) before arithmetic operations
d) none of the mentioned
Answer: b
Explanation: The results of floating point addition or division process may be required to be
rounded off, before write back stage to the floating point registers.
12. Which of the following is a floating point exception that is generated in case of integer
arithmetic?
a) divide by zero
b) overflow
c) denormal operand
d) all of the mentioned
Answer: d
Explanation: In the case of integer arithmetic, the possible floating point exceptions in Pentium
are:
1. divide by zero
2. overflow
3. denormal operand
4. underflow
5. invalid operation.
13. The mechanism that determines whether a floating point operation will be executed without
creating any exception is
a) Multiple Instruction Issue
b) Multiple Exception Issue
c) Safe Instruction Recognition
d) Safe Exception Recognition
Answer: c
Explanation: A mechanism known as Safe Exception Recognition
SER
had been employed in Pentium which determines whether a floating point operation will be
executed without creating any exception.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Tricky Microprocessors Questions and Answers focuses on “Enhanced Instruction
Set of Pentium, Intel MMX Architecture”.
1. Which of the following is not a transcendental instruction?
a) FSIN
b) FCOS
c) FMUL
d) FPTAN
Answer: c
Explanation: The FMUL instruction is a float point multiplication, which is not a transcendental
instruction.
2. The transcendental instruction that supports computation of sine and cosine is
a) FCOSSIN
b) FSNE
c) FSINFCOS
d) FSINCOS
Answer: d
Explanation: The instruction, FSINCOS, supports to compute sine and cosine.
3. The instruction that computes tan
is
a) FTAN
b) FTNGNT
c) FPTAN
d) FXTAN
Answer: c
Explanation: The instruction, FPTAN, computes tan
x
.
4. The instruction that computes arctan
is
a) FTAN
b) FACTN
c) FARCTAN
d) FPATAN
Answer: d
Explanation: The instruction, FPATAN, computes arctan
x
which is arc tangent of x.
5. The instruction, F2XMI, is used to compute
a) 2X
b) 2X-1
c) 2X+1
d) 2X+2
Answer: b
Explanation: The instruction, F2XMI, is used to compute 2X-1.
6. The instruction, FYL2XP, supports to compute the expression
a) Y*logX
b) Y*log2X
c) Y*log
2X+1
d) Y*log2
X+1
Answer: d
Explanation: The instruction, FYL2XP, supports to compute the expression Y*log2
X+1
.
7. The size of a general purpose floating point register of floating point unit is
a) 4 bytes
b) 40 bytes
c) 8 bytes
d) 80 bits
Answer: d
Explanation: There are eight general purpose floating point registers in the floating point unit.
Each of these eight registers are of 80-bits width.
8. For floating point operations, the bits used by mantissa in a floating point register is
a) 32
b) 64
c) 72
d) 79
Answer: b
Explanation: For floating point operations, 64 bits are used for the mantissa, and the rest 16 bits
for exponent.
9. The multimedia applications mainly require the architecture of
a) single instruction stream single data stream
b) multiple instruction stream single data stream
c) single instruction stream multiple data stream
d) multiple instruction stream multiple data stream
Answer: c
Explanation: Most of the multimedia applications mainly require the architecture of single
instruction stream multiple data stream.
10. The size of each MMX
MultimediaExtension
register is
a) 32 bits
b) 64 bits
c) 128 bits
d) 256 bits
Answer: b
Explanation: The MMX registers use only the 64-bit mantissa portion of the general purpose
floating point registers, to store MMX operands. Thus, the MMX programmers virtually get eight
new MMX registers, each of 64 bits.
11. After a sequence of MMX instructions is executed, the MMX registers should be cleared by
an instruction,
a) CLEAR
b) RESET
c) EMM
d) EMMS
Answer: d
Explanation: After a sequence of MMX instructions is executed, the MMX registers should be
cleared by an instruction, EMMS, which implies Empty the MMX Stack.
12. The number of pixels that can be manipulated in a single register by the CPU using MMX
architecture is
a) 4
b) 6
c) 8
d) 10
Answer: c
Explanation: Any CPU can manipulate only one pixel at a time. But by using MMX architecture,
we can manipulate eight such pixels, packed in a single 64-bit register.
13. After executing the floating point instructions, the floating point registers should be cleared
by an instruction,
a) CLEAR
b) EFPR
c) EMMF
d) EMMS
Answer: d
Explanation: After executing the floating point instructions, the floating point registers should be
cleared by an instruction, EMMS.
To practice tricky questions and answers on all areas of Microprocessors, here is complete set
of 1000+ Multiple Choice Questions and Answers .
This set of Microprocessors online quiz focuses on “MMX Data Types, Wrap-around and
Saturation Arithmetic, Multimedia Application Programming, Pentium III
P−III
CPU”.
1. In the data type, packed byte, the number of bytes that can be packed into one 64-bit quantity
is
a) 2
b) 4
c) 8
d) 16
Answer: c
Explanation: In packed byte data type, eight bytes can be packed into one 64-bit quantity.
2. Four words can be packed into 64-bit by using the data type,
a) unpacked word
b) packed word
c) packed doubled word
d) one quad word
Answer: b
Explanation: By using the packed word data type, four words can be packed into 64-bits.
3. The number of double words that can be packed into 64-bit register using packed double
word is
a) 2
b) 4
c) 6
d) 8
Answer: a
Explanation: Using packed double word, two double words can be packed into 64-bit.
4. The data type, “one quad word” packs __________ into 64-bit.
a) two 32-bit quantities
b) four 16-bit words
c) one 32-bit and two 16-bit quantities
d) one single 64-bit quantity
Answer: d
Explanation: The data type, “one quad word” packs one single 64-bit quantity into 64-bit register.
5. If the result of an operation is overflowed
exceededthan16bits
or underflowed then, only the lower 16-bits of the result are stored in the register and this effect
is known as
a) overflow/underflow effect
b) wrap-around effect
c) exceeding memory effect
d) none
Answer: b
Explanation: If the result of an operation is overflowed
exceededthan16bits
or underflowed then, only the lower 16-bits of the result are stored in the register, and this effect
is known as wrap-around effect.
6. In a multitasking operating system environment, each task should return to its own processor
state which is
a) contents of integer registers
b) contents of floating point registers
c) contents of MMX registers
d) all of the mentioned
Answer: d
Explanation: In a multitasking operating system environment, each task should return to its own
processor state, which should be saved when the task switching occurs. The processor state
here means the contents of the registers, both integer and floating point or MMX register.
7. Which of the following exception generated by MMX is the same type of memory access
exception as the X86 instructions?
a) page fault
b) segment not present
c) limit violation
d) all of the mentioned
Answer: d
Explanation: The MMX instruction set generates the same type of memory access exception as
the X86 instructions namely; page fault, segment does not present and limit violation.
8. When an MMX instruction is getting executed, the floating-point tag word is marked
a) 11
b) 10
c) 00
d) 01
Answer: c
Explanation: When an MMX instruction is getting executed, the floating-point tag word is marked
valid i.e. 00.
9. In a preemptive multitasking O.S., the saving and restoring of FP and MMX states are
performed by
a) Control unit
b) O.S.
c) MMX instructions
d) MMX registers
Answer: b
Explanation: In a preemptive multitasking O.S., the application does not know when it is
preemptied. It is the job of the O.S. to save and restore the FP and MMX states, when
performing a context switch. Thus the user need not save or restore the state.
10. The instruction of MMX that is essential when a floating-point routine calls an MMX routine
or viceversa is
a) MOV
b) PADD
c) EMMS
d) None of the mentioned
Answer: c
Explanation: The EMMS instruction is imperative when a floating point routine calls an MMX
routine or vice-versa. If we do not use EMMS at the end of MMX routine, subsequent
floating-point instructions will produce erratic results.
11. Pentium III is used in computers which run on the operating system of
a) windows NT
b) windows 98
c) unix
d) all of the mentioned
Answer: d
Explanation: Pentium III is the best option to use in computers from high performance desktop
to workstations and servers, running on operating systems like Windows NT, Windows 98 and
UNIX.
12. The architecture of CPU of Pentium III is suitable for
a) multimedia
b) image processing
c) speech processing
d) all of the mentioned
Answer: d
Explanation: The architecture of CPU of Pentium III is suitable for applications like imaging,
image processing, speech processing, multimedia and internet applications.
13. The Pentium III has the operating frequencies as
a) 300MHz,350MHz,400MHz
b) 400MHz,450MHz,500MHz
c) 350MHz,400MHz,450MHz
d) 450MHz,500MHz,550MHz
Answer: d
Explanation: The Pentium III has three versions operating at frequencies, 450MHz, 500MHz and
550MHz, which are all commercially available.
14. The Pentium III consists of
a) dual independent bus architecture
b) 512 Kbyte cache
c) eight 64-wide Intel MMX registers
d) all of the mentioned
Answer: d
Explanation: The Pentium III has dual independent bus architecture that increases the
bandwidth. It has a 512 Kbyte unified, non-blocking level2 cache and eight 64-wide Intel MMX
registers.
To practice all areas of Microprocessors for online Quizzes, here is complete set of 1000+
Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “MMX Instruction Set”.
1. The additional instructions that are designed especially for performing multimedia tasks are
known as
a) additional MMX instructions
b) multimedia MMX instructions
c) enhanced MMX instructions
d) none of the mentioned
Answer: c
Explanation: The MMX technology adds 57 new instructions to the instruction set of processors.
These instructions are known as enhanced MMX instructions and are designed specifically for
performing multimedia tasks.
2. The MMX instruction, EMMS consists of __________ on which it operates.
a) source operand
b) destination operand
c) source and destination operand
d) none of the mentioned
Answer: d
Explanation: The instruction, EMMS, does not have any operand.
3. In all the MMX instructions, the destination operand resides in
a) Memory
b) RAM
c) Either in an MMX register or in memory
d) MMX register
Answer: d
Explanation: In all the MMX instructions, the source operand is found either in an MMX register
or in memory, and the destination operand resides in MMX register.
4. For the MMX instructions, the prefix, P, is used to represent the mode of
a) real addressing mode
b) virtual mode
c) packed mode
d) programmable mode
Answer: c
Explanation: In the MMX instructions, if the operands are in the packed mode, the prefix, P, is
used to indicate packed data.
5. For the MMX instructions, the suffix, S, is used to represent
a) status
b) saturation
c) signed saturation
d) unsigned saturation
Answer: c
Explanation: For the MMX instructions, the suffix “S” indicates signed saturation, and “US”
indicates unsigned saturation, while executing arithmetic computation in saturation mode.
6. The instruction that is used for quadword is
a) PADD
b) PCMPEQ
c) PAND
d) None of the mentioned
Answer: d
Explanation: The instructions, PADD, PCMPEQ and PAND are used for packed byte, word and
double word.
7. The instruction, PSUBB, performs subtraction in
a) packed word
b) packed byte
c) packed double word
d) unpacked word
Answer: b
Explanation: The instruction, PSUBB, performs subtraction in a packed byte.
8. The instruction, PCMPGT, is used to compare two data types and check
a) equal to condition
b) less than condition
c) greater than condition
d) equal to and greater than condition
Answer: c
Explanation: The instruction, PCMPGT, compares to check the greater than condition in packed
bytes, packed words and packed double words.
9. The instruction that is not operated on quad word is
a) MOV
b) PSLL
c) PSRA
d) All of the mentioned
Answer: c
Explanation: The instruction, PSRA, performs arithmetic shift, right in a single cycle. It supports
only the shifting of packed word and double word data types.
10. When the instruction, PMULLW, is performed, then the lower order 16-bits of the 32 bit
products are stored in
a) source operand
b) destination operand
c) no storage of lower order
d) either source or destination
Answer: b
Explanation: In the instruction, PMULLW, four 16 X 16 multiplications are performed, and the
lower order 16 bits of the 32-bit products are stored in destination.
11. When the instruction, PMULHW, is performed, then the higher order 16-bits of the 32 bit
products are stored in
a) source operand
b) destination operand
c) no storage of lower order
d) either source or destination
Answer: b
Explanation: In the instruction, PMULHW, four 16 X 16 multiplications are performed, and the
higher order 16 bits of the 32-bit products are stored in destination.
12. The instruction in which both multiplication and addition are performed is
a) PAND
b) PMULHW
c) PADD
d) PMADDWD
Answer: d
Explanation: PMADDWD is an important multimedia instruction, which multiplies the four signed
words of the destination operand, with four signed words of source operand. This results in
32-bit double words which are added, and the result is stored in the higher double word of the
destination operand.
13. If the result of PCMPEQ, which is a comparison of two packed data types, is a success, then
the mask generated is
a) mask 0s
b) mask 1s
c) mask 2s
d) mask 3s
Answer: b
Explanation: If the result of PCMPEQ, which is a comparison of two packed data types is a
success, then the mask 1s is generated, otherwise a mask of 0s is generated, in the destination
operand.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Pentium – Pro and Pentium-II -1”.
1. The instructions that pass through the fetch, decode and execution stages sequentially is
known as
a) sequential instruction
b) sequence of fetch, decode and execution
c) linear instruction sequencing
d) non-linear instruction sequencing
Answer: c
Explanation: The linear instruction sequencing is the one in which the instructions that pass
through the fetch, decode and execution stages sequentially.
2. During the execution of instructions, if an instruction is executed, then next instruction is
executed only when the data is read by
a) control unit
b) bus interface unit
c) execution unit
d) cpu
Answer: b
Explanation: During the execution of instructions, only after the bus interface unit of CPU reads
the data from the main memory and returns it to the register, the next instruction execution will
commence.
3. Because of Pentium’s superscalar architecture, the number of instructions that are executed
per clock cycle is
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: Pentium’s superscalar architecture employs five stage pipeline with U and V pipes.
Thus it can execute two instructions per clock.
4. The type of execution which means that the CPU should speculate which of the next
instructions can be executed earlier is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
Answer: a
Explanation: The speculative execution is an execution which means that the CPU should
speculate which of the next instructions can be executed earlier.
5. The execution in which the consecutive instruction execution in a sequential flow is hampered
is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
Answer: b
Explanation: In the out of turn execution, the consecutive instruction execution in a sequential
flow is hampered and the CPU should be able to execute out of turn instructions.
6. A dual independent bus has
a) Enhanced system bandwidth
b) CPU that can access both cache and memory simultaneously
c) High throughput
d) All of the mentioned
Answer: d
Explanation: A dual independent bus architecture is incorporated by Pentium-Pro to get an
enhanced system bandwidth and it also yields high throughput. It has the CPU which can
access both main memory and the cache simultaneously.
7. The unit that is used to implement the multiple branch prediction in Pentium-Pro is
a) control unit
b) bus interface unit
c) branch target buffer
d) branch instruction register
Answer: c
Explanation: The processor uses an associative memory called branch target buffer for
implementing the algorithm, multiple branch prediction.
8. Which of the following is not an independent engine of Pentium-Pro?
a) fetch-decode unit
b) dispatch-execute unit
c) control-execute unit
d) retire unit
Answer: c
Explanation: Pentium-Pro incorporates three independent engines, 1. Fetch-decode unit 2.
Dispatch-execute unit 3. Retire unit.
9. The unit that accepts the sequence of instructions from the instruction cache as input is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) none
Answer: a
Explanation: The fetch-decode unit accepts the sequence of instructions from the instruction
cache as input and then decodes them.
10. In fetch-decode unit, the number of parallel decoders that accept the stream of fetched
instructions and decode them is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: A set of three parallel decoders accepts the stream of fetched instructions and
decode them.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Question Bank focuses on “Pro and Pentium-II -2”.
1. The decoder unit in fetch-decode unit converts the instructions into
a) executable statements
b) machine language statements
c) MMX instructions
d) micro operations
Answer: d
Explanation: The decoder unit converts the fetched instructions into micro operations.
2. The logical source
and logical destination
that the micro operation has respectively are
a) 2,2
b) 1,3
c) 3,1
d) 3,2
Answer: c
Explanation: Each microoperation contains two logical sources and one logical destination.
3. The microoperations that are converted by decoder are directly transferred to
a) decoder register
b) dispatch-execute unit
c) retire unit
d) register alias table
Answer: d
Explanation: The microoperations are sent to the register alias table
RAT
. The RAT translates the logical register references to the physical register set actually available
in the CPU.
4. The pool of instructions that are fetched is stored in an addressable memory called
a) tristate buffer
b) branch target buffer
c) reorder buffer
d) order buffer
Answer: c
Explanation: The pool of instructions that are fetched is stored in an array of content
addressable memory called reorder buffer.
5. The unit that performs scheduling of instructions by determining the data dependencies is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) none
Answer: b
Explanation: The dispatch-execute unit performs scheduling of instructions by determining the
data dependencies after which the microoperations of the scheduled instructions are executed
in the execution unit.
6. The unit that reads the instruction pool and removes the microoperations which have been
executed instruction pool is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) decoding unit
Answer: c
Explanation: The retire unit reads the instruction pool containing the instructions and removes
the microoperations which have been executed instruction pool.
7. The speed of Pentium-Pro when compared to that of Pentium is
a) equal
b) twice
c) thrice
d) two-third
Answer: b
Explanation: The features incorporated in Pentium-Pro enhances the speed of Pentium-Pro and
is twice as that of Pentium.
8. Which of the following is not supported by Pentium-Pro?
a) multiple branch prediction
b) mmx instruction set
c) speculative execution
d) none
Answer: b
Explanation: The Pentium-Pro does not support the MMX instruction set.
9. The feature of Pentium II is
a) high cache
b) operates at 2.8 volts
c) supports intel’s MMX instructions
d) all of the mentioned
Answer: d
Explanation: The Pentium II has a higher cache and it can operate at 2.8 volts, thereby reducing
power consumption. The most important change of Pentium II is that it can support Intel’s MMX
instructions.
10. The results of speculative instruction execution is stored in
a) visible CPU registers
b) permanent memory
c) temporary memory
d) none
Answer: c
Explanation: The results of speculative instruction execution should not be stored in CPU
registers and are temporarily stored, since they may have to be discarded, in case if there is a
branch instruction before these speculative instruction executions.
To practice Microprocessors Question Bank, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Features of Pentium 4, Netburst Microarchitecture For Pentium4 – 1”.
1. The feature of Pentium 4 is
a) works based on NetBurst microarchitecture
b) clock speed ranges from 1.4GHz to 1.7GHz
c) has hyper-pipelined technology
d) all of the mentioned
Answer: d
Explanation: Pentium 4 is based on NetBurst microarchitecture. Clock speed varies from
1.4GHz to 1.7GHz. It has hyper-pipelined technology.
2. Which of the following is not a module of Pentium 4 architecture?
a) front end module
b) execution module
c) control module
d) none
Answer: c
Explanation: Pentium 4 architecture may be viewed having four basic modules.
1. Front end module
2. Out of order execution engine
3. Execution module
4. Memory subsystem module.
3. The front module of Pentium 4 consists of
a) trace cache
b) microcode ROM
c) front end branch predictor
d) all of the mentioned
Answer: d
Explanation: The front module of Pentium 4 contains
1. IA 32 Instruction decoder
2. Trace cache
3. Microcode ROM
4. Front end branch predictor.
4. The unit that decodes the instructions concurrently and translate them into micro-operations
is
a) trace cache
b) instruction decoder
c) execution module
d) front end branch predictor
Answer: b
Explanation: The role of instruction decoder is to decode the instructions concurrently and
translate them into micro-operations known as micro-ops.
5. In complex instructions, when the instruction needs to be translated into more than 4
micro-operations, then the decoder transfers the task to
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
Answer: c
Explanation: In case of complex instructions, when the instruction needs to be translated into
more than 4 micro-operations, then the decoder transfers the task to microcode ROM.
6. The unit that does not store the instructions, but the decoded stream of instructions is
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
Answer: a
Explanation: The trace cache is a special instruction cache because it does not store the
instructions, but the decoded stream of instructions.
7. Trace cache can store the micro-ops upto a range of
a) 6 K decoded micro-ops
b) 8 K decoded micro-ops
c) 10 K decoded micro-ops
d) 12 K decoded micro-ops
Answer: d
Explanation: Trace cache can store upto 12K micro-ops. The cache assembles the decoded
micro-ops into ordered sequence of micro-ops called traces.
8. The unit that predicts the locations from where the next instruction bytes are fetched is
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
Answer: b
Explanation: The front end branch predictor predicts the locations from where the next
instruction bytes are fetched.
9. If complex instructions like interrupt handling, string manipulation appear, then the control
from trace cache transfers to
a) microcode ROM
b) front end branch predictor
c) execution module
d) instruction decoder
Answer: a
Explanation: When some complex instructions like interrupt handling, string manipulation
appear, then the control from trace cache transfers to microcode ROM.
10. After the micro-ops are issued by the microcode ROM, the control goes to
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
Answer: a
Explanation: After the micro-ops are issued by the microcode ROM, the control goes to Trace
cache once again. The micro-ops delivered by the trace cache and the microcode ROM are
buffered in a queue in an orderly fashion.
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Questions and Answers .
This set of Microprocessors Questions and Answers for Entrance exams focuses on “Netburst
Microarchitecture For Pentium4 -2, Instruction Translation Lookaside Buffer
ITLB
and Branch Prediction”.
1. If the logical processors want to execute complex IA-32 instructions simultaneously then the
number of microcode instruction pointers required is
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: If both the logical processors want to execute complex IA-32 instructions
simultaneously then two microcode instruction pointers are required, which will access the
microcode ROM.
2. Which of the following is a type of branch prediction?
a) static prediction
b) dynamic prediction
c) static and dynamic prediction
d) none
Answer: c
Explanation: There are two types of branch prediction namely static prediction and dynamic
prediction.
3. The prediction that is based on a statistical assumption that the majority of backward
branches occur in repetitive loops is
a) static prediction
b) dynamic prediction
c) branch prediction
d) none
Answer: a
Explanation: The static prediction is based on a statistical assumption that the majority of
backward branches occur in the context of repetitive loops.
4. The advantage of static prediction is
a) simple and fast
b) does not require table lookups or calculations
c) performs without much degradation
d) all of the mentioned
Answer: d
Explanation: The static prediction is simple and fast. It does not require table lookups or
calculations. In case if a program contains a number of loops, static prediction performs without
much degradation.
5. The dynamic branch prediction algorithms use
a) Branch History Table
BHT
b) Branch Target Buffer
BTB
c) Branch History Table and Branch Target Buffer
d) None
Answer: c
Explanation: The dynamic branch prediction algorithms use two types of tables, namely Branch
History Table
BHT
and Branch Target Buffer
BTB
.
6. The unit that preserves the history of each conditional branch is
a) Branch Target Buffer
BTB
b) Branch History Table
BHT
c) Static prediction
d) Dynamic prediction
Answer: b
Explanation: The Branch History Table
BHT
preserves the history of each conditional branch that the speculative branch prediction unit
encounters during the last several cycles.
7. The BHT keeps a record that indicates the likelihood of the branches grouped as
a) strongly taken
b) taken
c) not taken
d) all of the mentioned
Answer: d
Explanation: The BHT keeps a record that indicates the likelihood that the branch will be taken
based on its past history. The branches may be grouped as ‘strongly taken’, ‘taken’, ‘not taken’
and ‘strongly not taken’.
8. Each logical processor has
a) one 64-byte streaming buffer
b) one 32-byte streaming buffer
c) two 64-byte streaming buffers
d) two 32-byte streaming buffers
Answer: c
Explanation: Each logic processor has its own set of two 64-byte streaming buffers, which store
the instruction bytes and subsequently they are dispatched to the instruction decode stage.
9. If there is a trace cache miss, then the instruction bytes are required to be fetched from the
a) instruction decoder
b) Level2 cache
c) execution module
d) none of the mentioned
Answer: b
Explanation: If there is a trace cache miss, then the instruction bytes are required to be fetched
from the Level2 cache.
10. The Instruction Translation Lookaside Buffer
ITLB
is present in
a) trace cache
b) instruction decoder
c) logical processors
d) all of the mentioned
Answer: c
Explanation: Since there are two logical processors, there are two ITLBs. Thus each logical
processor has its own ITLB and its own instruction pointer to track the progress of instruction
fetch for each of them.
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Multiple Choice Questions and Answers .
This set of Tough Microprocessors Questions and Answers focuses on “Rapid Execution
Module, Memory Subsystem, Hyperthreading Technology”.
1. The units that are primarily used to resolve indirect mode of memory addressing is called
a) ALU
b) AGU
c) ALU and AGU
d) NONE
Answer: b
Explanation: The AGUs
AddressGenerationUnits
are primarily used to resolve indirect mode of memory addressing.
2. The AGUs work at a speed of
a) equal to that of processor
b) twice the processor
c) thrice the processor
d) none
Answer: b
Explanation: The AGUs run at twice the processor speed.
3. Pentium 4 consists of
a) 4 ALUs
b) 4 AGUs
c) 2 ALUs and 2 AGUs
d) 4 ALUs and 4 AGUs
Answer: c
Explanation: Pentium 4 consists of 2 ALUs and 2 AGUs.
4. The number of instructions that can be executed per clock cycle by the ALU or AGU is
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: As the speed of the units, ALU and AGU are doubled, which means that twice the
number of instructions being executed per clock cycle.
5. The paging mechanism of IA-32 architecture has an extension as
a) page memory extension
b) page size extension
c) page address extension and page size extension
d) page memory extension and page size extension
Answer: c
Explanation: IA-32 architecture’s paging mechanism includes an extension that support
1. Page address extension to address space greater than 4GB.
2. Page size extension to map linear address to physical address in 4MB.
6. The linear address space is mapped into the processors physical address space either
directly or through paging by
a) flat memory model
b) segmented memory model
c) flat or segmented memory model
d) none
Answer: c
Explanation: With the flat or segmented memory model, linear address space is mapped into
the processors physical address space either directly or through paging.
7. The features of thread in threading process is
a) threads can be bunched together
b) threads are simple and light weight
c) threads are independent
d) all of the mentioned
Answer: d
Explanation: Threads may be bunched together in a process. Threads are independent, simple
in structure and are lightweight in the sense that they may enhance the speed of operation of an
overall process.
8. The process in which multiple threads correspond to the tracking of each individual object is
known as
a) multiple thread system
b) multi thread parallelism
c) thread level parallelism
d) multi level parallelism
Answer: c
Explanation: The mutiple threads correspond to the tracking of each individual object. This kind
of parallelism is known as thread level parallelism
TLP
.
9. Which of the following is not a type of context switching?
a) time-slice multithreading
b) on chip multiprocessing
c) hyperthreading
d) none
Answer: d
Explanation: A single processor can execute multiple threads by switching between them. The
scheme of context switching may be several types. They are
1. Time-slice multithreading
2. On chip multiprocessing
3. Hyperthreading.
10. The thread level parallelism is a process of
a) saving the context of currently executing process
b) flushing the CPU of the same process
c) loading the context of new next process
d) all of the mentioned
Answer: d
Explanation: The thread level parallelism is a process of
1. Saving the context of currently executing process.
2. Flushing the CPU of the same process.
3. Loading the context of new next process is called a context switch.
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of 1000+ Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Hyperthreading In Pentium”.
1. Which of the following is a resource sharing strategy that had been investigated by the
developers?
a) partitioned resources
b) threshold sharing
c) full sharing
d) all of the mentioned
Answer: d
Explanation: Several resource sharing strategies have been investigated by the developers.
Some of these are
1. Partitioned resources
2. Threshold sharing
3. Full sharing.
2. The feature of hyperthreading is
a) simultaneous multithreading
b) switching is not required
c) effective use of processor resources
d) all of the mentioned
Answer: d
Explanation: Hyperthreading used the concept of simultaneous multithreading, where multiple
threads can be executed on a single processor without switching.
3. Each logical processor maintains a set of architecture state which consists of
a) general purpose registers
b) machine state register
c) advanced programmed interrupt controller
d) all of the mentioned
Answer: d
Explanation: Each logical processor maintains a set of architecture state which consists of
1. Registers including the general purpose registers
2. The control register
3. Advanced programmed interrupt controller
4. Machine state register.
4. A logical processor may be temporarily stalled for
a) including servicing cache misses
b) handling branch mispredictions
c) waiting for results of previous instructions
d) all of the mentioned
Answer: d
Explanation: A logical processor may be temporarily stalled for a variety of reasons like
including servicing cache misses, handling branch mispredictions and waiting for results of
previous instructions.
5. The hyperthreading technology automatically involves the
a) decrease of die area
b) increase of die area
c) decrease of die area to half
d) none
Answer: b
Explanation: The hyperthreading technology automatically involves the increase of die area.
6. The instruction that is used when either of the logical processors is idle is
a) HOLD
b) HLDA
c) HALT
d) NONE
Answer: c
Explanation: An optimization may require the use of HALT instruction, when either of the two
logical processors is idle.
7. The mode that is available when there is only one software thread to execute is
a) single task mode
b) multi task mode
c) single task and multi task mode
d) dual task mode
Answer: c
Explanation: When there is only one software thread to execute, there are two modes namely
single task mode and multi task mode.
8. The HALT instruction is a privileged instruction that can be only used by
a) execution unit
b) operating system
c) control unit
d) memory unit
Answer: b
Explanation: The HALT instruction is a privileged instruction that can be only used by operating
system.
9. When the operating system uses HALT instruction on a processor which supports
multithreading, the operation moves from
a) Single task to multi task mode
b) ST1 to ST0
c) Multi task to single task mode
d) None
Answer: c
Explanation: When the operating system uses HALT instruction on a processor which supports
multithreading, the operation moves from multi tasking mode to single tasking mode.
10. The Xeon TM processor on which hyperthreading technology was first implemented consists
of
a) one logical processor per physical processor
b) two logical processor per physical processor
c) three logical processor per physical processor
d) zero logical processor per physical processor
Answer: b
Explanation: The Xeon TM processor on which hyperthreading technology was first
implemented consists of two logical processor per physical processor.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Basic Microprocessors Questions and Answers focuses on “Extended Instruction Set
In Advanced Pentium Processors, Formal Verification”.
1. The MMX instructions support only
a) character data type
b) float data type
c) integer data type
d) string data type
Answer: c
Explanation: The MMX instructions support only integer data type.
2. For single precision floating point numbers, the SSE instructions are
a) MMX instructions
b) SIMD instructions
c) Floating point executions
d) None
Answer: b
Explanation: The SSE instructions are SIMD
SingleInstructionMultipleDataStream
instructions for single precision floating point numbers.
3. The feature of SSE among the following is
a) operate on four 32-bit floating points
b) register size is of 128 bits
c) no switching from one mode to other
d) all of the mentioned
Answer: d
Explanation: The features of SSE
StreamingSIMDextensions
are
1. SSE instructions are SIMD instructions for single precision floating point numbers.
2. They operate on four 32-bit floating points.
3. The register size is of 128 bits
4. No necessity to switch from one mode to other.
4. The new instructions that are added in SSE for floating point operations are of
a) 72
b) 50
c) 25
d) 8
Answer: b
Explanation: The new instructions that are added in SSE for floating point operations are 50.
5. The SSE instructions can operate on
a) packed data
b) unpacked data
c) dynamic data
d) all of the mentioned
Answer: a
Explanation: The SSE instructions can operate on packed data or scalar data.
6. Which of the following group is not of SSE instructions?
a) jump or branch group of instruction
b) logic and comparison group of instruction
c) shuffle instructions
d) all of the mentioned
Answer: d
Explanation: The SSE instructions can be grouped to many types. Some of them are
1. Data transfer instructions
2. Arithmetic, logic and comparison group of instruction
3. shuffle instructions
4. Cacheability instructions.
7. Which of the following is true about SSE2 instructions in Pentium III and Pentium 4?
a) SSE increases the accuracy of double precision floating point operations
b) SSE supports new formats of packed data
c) SSE increases the speed of manipulation of SIMD integer operations
d) All of the mentioned
Answer: d
Explanation: The SSE new instruction set increases the accuracy of double precision floating
point operations, supports new formats of packed data.
8. The data type that the SSE2 instructions doesn’t support is
a) single precision floating points
b) double precision floating points
c) single and double precision floating points
d) none of the mentioned
Answer: d
Explanation: The SSE2 instructions support new data types such as double precision floating
points along with single precision floating points.
9. The additional instructions of SSE3 over SSE2 contains
a) video encoding
b) complex arithmetic operation
c) thread synchronization
d) all of the mentioned
Answer: d
Explanation: The SSE3 contains 13 additional SIMD instructions over SSE2. These instructions
comprise five types.
i. floating point to integer conversion
ii. complex arithmetic operation
iii. video encoding
iv. SIMD floating point operations using array of structures format
v. thread synchronization.
10. The unit that may acts as an interface between the Front end and the Out of order execution
engine in the pipeline flow is
a) micro-op queue
b) micro-op stack
c) micro-ops
d) none
Answer: a
Explanation: The micro-op queue acts as an interface between the Front end and the Out of
order execution engine in the pipeline flow.
11. The verification of the logic using formal mathematical tools is called
a) arithmetic verification
b) formal verification
c) mathematical verification
d) logical verification
Answer: b
Explanation: The verification of the logic using formal mathematical tools is called formal
verification.
12. The formal verification is important for
a) developing the tools
b) developing the methodologies
c) to detect the bugs in design
d) all of the mentioned
Answer: d
Explanation: The formal verification is important to develop the tools and methodologies to
handle a large number of proofs using which it will be possible to detect the bugs in the design.
13. By using the techniques of formal verification, one can detect the logical bugs of
a) more than 50
b) less than 50
c) more than 100
d) less than 100
Answer: c
Explanation: By using the techniques of formal verification, one can detect more than 100
logical bugs.
14. The modern processors are designed to achieve
a) high speed
b) operate at low operating voltage
c) uses cooling technology
d) all of the mentioned
Answer: d
Explanation: The modern processors are designed to operate at a very high speed and even
with the lower operating voltages, the power consumption is high enough to require expensive
cooling technology.
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of 1000+ Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Hybrid Architecture -RISC and CISC Convergence, Advantages of RISC, Design
Issues of RISC Processors -1”.
1. The disadvantage of CISC design processors is
a) low burden on compiler developers
b) wide availability of existing software
c) complex in nature
d) none
Answer: c
Explanation: Some computers are used in preference to CISC design due to its low burden on
compiler developers and wide availability of existing software. But they are complex in nature.
2. The RISC architecture is preferred to CISC because RISC architecture has
a) simplicity
b) efficiency
c) high speed
d) all of the mentioned
Answer: d
Explanation: The RISC architecture is preferred to CISC because RISC architecture is simple,
highly efficient and the processors using RISC architecture have high speed.
3. The feature of RISC that is not present in CISC is
a) branch prediction
b) pipelining
c) branch prediction and pipelining
d) none
Answer: c
Explanation: A RISC core allows performance enhancing features, such as branch prediction
and pipelining. Traditionally, these have only been possible in RISC designs.
4. The feature of hybrid CISC-RISC architecture is
a) consume a lot of power
b) not applicable to mobile applications
c) processed by RISC core
d) all of the mentioned
Answer: d
Explanation: The CISC-RISC hybrids continue to consume a lot of power and are not best
candidates for mobile and embedded applications.
5. Which of the following is an application of RISC architecture by adding more instructions?
a) multimedia applications
b) telecommunication encoding
c) image conversion
d) all of the mentioned
Answer: d
Explanation: By adding more instructions to the RISC architecture, some applications can be
run much faster like multimedia applications, telecommunication encoding/decoding, image
conversion and video processing.
6. Which of the following processor belongs to hybrid RISC-CISC architecture?
a) Intel Pentium III
b) Intel Itanium 64
c) AMD’s X86-64
d) All of the mentioned
Answer: d
Explanation: The processors, Intel Pentium III, Intel Itanium 64 and AMD’s X86-64 consists of
hybrid RISC-CISC architecture.
7. In order to implement complex instructions, CISC architectures use
a) macroprogramming
b) hardwire
c) microprogramming
d) none
Answer: c
Explanation: In order to implement complex instructions, CISC architectures use
microprogramming.
8. The advantage of RISC processors is
a) can operate at high clock frequency
b) shorter design cycle
c) simple and fast
d) all of the mentioned
Answer: d
Explanation: The advantages of RISC processors are that they can work at high clock
frequency, can be designed, developed and tested more quickly with a high speed.
9. The additional functionality that can be placed on the same chip of RISC is
a) Memory management units
b) Floating point units
c) Memory management and floating point arithmetic units
d) RAM, ROM
Answer: c
Explanation: Several extra functionalities, such as memory management units or floating point
arithmetic units, can also be placed on the same chip of RISC.
10. The number of clockcycles that take to wait until the length of the instruction is known in
order to start decoding is
a) 0
b) 1
c) 2
d) 3
Answer: a
Explanation: The loading and decoding the instructions in a RISC processor is simple and fast.
It is not needed to wait until the length of the instruction is known in order to start the decoding.
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Questions and Answers .
This set of Microprocessors Problems focuses on “Hybrid Architecture -RISC and CISC
Convergence, Advantages of RISC, Design Issues of RISC Processors -2”.
1. The number of CPIs
ClockPerInstruction
for an instruction of RISC processors is
a) 0
b) 1
c) 2
d) 3
Answer: b
Explanation: RISC processors have unity CPI
ClockPerInstruction
, which is due to the optimization of each instruction on the CPU and massive pipelining
embedded in a RISC processor.
2. Which of the following is not true about RISC processors?
a) addressing modes are less
b) pipelining is key for high speed
c) microcoding is required
d) single machine cycle instructions
Answer: c
Explanation: Unlike the CISC, in RISC architecture, instruction microcoding is not required.
3. The RISC processors that support variable length instructions are from
a) Intel
b) Motorola
c) AMD
d) Intel and Motorola
Answer: d
Explanation: In RISC, each instruction is of the same length, so that it may be fetched in a
single operation. The traditional microprocessors from Intel or Motorola support variable length
instructions.
4. Which of the following is true about register windowing?
a) chips expose 32 registers to programmer
b) puts demands on multiplexers
c) puts enormous demands on register ports
d) all of the mentioned
Answer: d
Explanation: The register windowing involves a mechanism where the chips expose 32 registers
to the programmer at any one time. It puts enormous demands on multiplexers and register
ports to make any physical register appear to be any logical register.
5. The disadvantage of register windowing is
a) high speed
b) puts demands on multiplexers/register ports
c) consumes less cycles
d) doesn’t handle overflow/underflow
Answer: d
Explanation: It is impossible to predict when the register file will overflow or underflow, so
performance is unpredictable. It generates a software fault, which the operating system has to
handle, consuming more cycles.
6. The register window is used to point the number of physical registers is
a) infinite
b) that are currently used
c) finite
d) that are unused
Answer: c
Explanation: The register window only helps us to point the number of physical registers is finite.
7. Which of the following is not a stage of pipeline of a RISC processor?
a) read registers and decode the instructions
b) fetch instructions from registers
c) write result into a register
d) access an operand in data memory
Answer: b
Explanation: There are 5 stages in pipelining. They are
1. Fetch instructions from memory
2. Read registers and decode the instructions
3. Execute the instructions or calculate an address
4. Access an operand in data memory
5. Write result into a register.
8. When an instruction depends on the results of the previous instructions then
a) error occurs
b) software fault occurs
c) data dependency occurs
d) hardware fault occurs
Answer: c
Explanation: A data dependency occurs when an instruction depends on the results of the
previous instructions.
9. The instructions that instruct the processor to make a decision about the next instruction to be
executed are
a) data dependency instructions
b) branch instructions
c) control transfer instructions
d) none
Answer: b
Explanation: The branch instructions are those which instruct the processor to make a decision
about the next instruction to be executed, depending upon whether the condition is satisfied or
not.
10. The reason for which the RISC processor goes to idle state
orstall
is
a) delay in reading information from memory
b) poor instruction set design
c) dependencies between instructions
d) all of the mentioned
Answer: d
Explanation: There are a variety of reasons, including delays in reading information from
memory, poor instruction set design, or dependencies between instructions for the RISC
processor to remain idle.
To practice all areas of Microprocessors Problems, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Architecture of 8051”.
1. The register that may be used as an operand register is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
Answer: d
Explanation: In some instructions, the Accumulator and B register are used to store the
operands.
2. The register that can be used as a scratch pad is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
Answer: b
Explanation: B register is used to store one of the operands for multiply and divide instructions.
In other instructions, it may just be used as a scratch pad.
3. The registers that contain the status information is
a) control registers
b) instruction registers
c) program status word
d) all of the mentioned
Answer: c
Explanation: The set of flags of program status word contains the status information and is
considered as one of the special function registers.
4. Which of the processor’s stack does not contain the top-down data structure?
a) 8086
b) 80286
c) 8051
d) 80386
Answer: c
Explanation: The 8051 stack is not a top-down data structure, like other Intel processors.
5. The architecture of 8051 consists of
a) 4 latches
b) 2 timer registers
c) 4 on-chip I/O ports
d) all of the mentioned
Answer: d
Explanation: The architecture of 8051 consists of 4 latches and driver pairs are allotted to each
of the four on-chip I/O ports. It contains two 16-bit timer registers.
6. The transmit buffer of serial data buffer is a
a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register
Answer: b
Explanation: The transmit buffer of serial data buffer is a parallel-in serial-out register.
7. The receive buffer of serial data buffer is a
a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register
Answer: a
Explanation: The serial data register has two buffers. The transmit buffer is a parallel-in
serial-out register and receive buffer is a parallel-in serial-out register.
8. The register that provides control and status information about counters is
a) IP
b) TMOD
c) TSCON
d) PCON
Answer: b
Explanation: The registers, TMOD and TCON contain control and status information about
timers/counters.
9. The register that provides control and status information about serial port is
a) IP
b) IE
c) TSCON
d) PCON and SCON
Answer: d
Explanation: The registers, PCON and SCON contain control and status information about serial
port.
10. The device that generates the basic timing clock signal for the operation of the circuit using
crystal oscillator is
a) timing unit
b) timing and control unit
c) oscillator
d) clock generator
Answer: c
Explanation: The oscillator circuit generates the basic timing clock signal for the operation of the
circuit using crystal oscillator.
11. The registers that are not accessible by the user are
a) Accumulator and B register
b) IP and IE
c) Instruction registers
d) TMP1 and TMP2
Answer: d
Explanation: The arithmetic operations are performed over the operands held by the temporary
registers, TMP1 and TMP2. Users cannot access these temporary registers.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Register Set of 8051”.
1. Which of the following is an 8-bit register?
a) PSW
ProgramStatusWord
b) TCON
TimerControlRegister
c) Accumulator
d) All of the mentioned
Answer: d
Explanation: The registers, PSW, TCON and Accumulator are 8-bit registers.
2. Which of the following register can be addressed as a byte?
a) P1
b) SCON
c) TMOD
d) TCON
Answer: c
Explanation: The registers, TMOD, SP, TH0, TH1, TL0, TL1 are to be addressed as bytes.
3. Which of the following is bit-addressable register?
a) SBUF
b) PCON
c) TMOD
d) SCON
Answer: d
Explanation: The registers, accumulator, PSW, B, P0, P1, P2, P3, IP, IE, TCON and SCON are
all bit-addressable registers.
4. The higher and lower bytes of a 16-bit register DPTR are represented respectively as
a) LDPTR and HDPTR
b) DPTRL and DPTRH
c) DPH and DPL
d) HDP and LDP
Answer: c
Explanation: The registers, DPH and DPL are the higher and lower bytes of a 16-bit register
DPTR.
5. The register that is used for accessing external data memory is
a) DPH
b) DPL
c) DPTR
d) NONE
Answer: c
Explanation: The Data Pointer
DPTR
is used for accessing external data memory which means that it includes both DPH and DPL.
6. Among the four groups of register banks, the number of groups that can be accessed at a
time is
a) 1
b) 2
c) 3
d) all the four
Answer: a
Explanation: At a time, only one of the four register banks can be accessed.
7. The number of 8-bit registers that a register bank contain is
a) 2
b) 4
c) 6
d) 8
Answer: d
Explanation: The 32, 8-bit registers are divided into four groups of 8 registers each, called
register banks.
8. If RS1=1, RS0=0, then the register bank selected is
a) register bank 0
b) register bank 1
c) register bank 2
d) register bank 3
Answer: c
Explanation: If RS1=1, RS0=0, then the register bank selected is register bank 2.
9. If RS1=1, RS0=1, then the register bank selected is
a) register bank 0
b) register bank 1
c) register bank 2
d) register bank 3
Answer: d
Explanation: If RS1=1, RS0=1, then the register bank selected is register bank 3. If RS1=0,
RS0=0, then selected bank is register bank 0.
10. The PCON register consists of
a) power mode bit
b) power idle bit
c) power ideal bit
d) power down bit and idle bit
Answer: d
Explanation: The power control register, PCON consists of power down bit and idle bit which
activate the power down mode and idle mode in 80C51BH.
11. The on-chip oscillator is stopped in
a) power mode
b) power down mode
c) idle mode
d) ideal mode
Answer: b
Explanation: In power down mode, the on-chip oscillator is stopped.
12. In idle mode, the device that is disabled is
a) serial port
b) timer block
c) clock to CPU
d) all of the mentioned
Answer: c
Explanation: In idle mode, the oscillator continues to run and the interrupt, serial port and timer
blocks are active but the clock to the CPU is disabled.
13. The only way to terminate the power down mode is to
a) CLEAR
b) RESET
c) HOLD
d) HLT
Answer: b
Explanation: The only way to terminate the power down mode is hardware reset. The reset
redefines all the SFRs but the RAM contents are left unchanged.
14. The idle mode can be terminated by
a) PRESET
b) CLEAR
c) Interrupt
d) Interrupt or reset
Answer: d
Explanation: The idle mode can be terminated with a hardware interrupt or hardware reset
signal.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interrupt and Stack of 8051 -1”.
1. Which of the following is an external interrupt?
a) INT0
activelow
b) INT2
activelow
c) Timer0 interrupt
d) Timer1 interrupt
Answer: a
Explanation: INT0
activelow
and INT1
activelow
are two external interrupt inputs provided by 8051.
2. The interrupts, INT0
activelow
and INT1
activelow
are processed internally by flags
a) IE0 and IE1
b) IE0 and IF1
c) IF0 and IE1
d) IF0 and IF1
Answer: a
Explanation: The interrupts, INT0
activelow
and INT1
activelow
are processed internally by the flags IE0 and IE1.
3. The flags IE0 and IE1, are automatically cleared after the control is transferred to respective
vector if the interrupt is
a) level-sensitive
b) edge-sensitive
c) in serial port
d) in parallel port
Answer: b
Explanation: If the interrupts are programmed as edge sensitive, the flags IE0 and IE1 are
automatically cleared after the control is transferred to respective vector.
4. If the external interrupt sources control the flags IE0 and IE1, then the interrupt programmed
is
a) level-sensitive
b) edge-sensitive
c) in serial port
d) in parallel port
Answer: a
Explanation: If the interrupts are programmed as level sensitive, then the flags IE0 and IE1 are
controlled by external interrupt sources themselves.
5. The pulses at T0 or T1 pin are counted in
a) timer mode
b) counter mode
c) idle mode
d) power down mode
Answer: b
Explanation: In counter mode, the pulses are counted at T0 or T1 pin.
6. In timer mode, the oscillator clock is divided by a prescalar
a)
1/8
b)
1/4
c)
1/16
d)
1/32
Answer: d
Explanation: In timer mode, the oscillator clock is divided by a prescalar
1/32
and then given to the timer.
7. The serial port interrupt is generated if
a) RI is set
b) RI and TI are set
c) Either RI or TI is set
d) RI and TI are reset
Answer: c
Explanation: The serial port interrupt is generated if atleast one of the two bits, RI and TI is set.
8. In serial port interrupt, after the control is transferred to the interrupt service routine, the flag
that is cleared is
a) RI
b) TI
c) RI and TI
d) None
Answer: d
Explanation: In serial port interrupt, after the control is transferred to the interrupt service
routine, neither of the flags are cleared.
9. The atleast number of machine cycles for which the external interrupts that are programmed
level-sensitive should remain high is
a) 1
b) 2
c) 3
d) 0
Answer: b
Explanation: The external interrupts, programmed level-sensitive should remain high for atleast
2 machine cycles.
10. If the external interrupts are programmed edge sensitive, then they should remain high for
atleast
a) 0 machine cycle
b) 2 machine cycles
c) 1 machine cycle
d) 3 machine cycles
Answer: c
Explanation: If the external interrupts are programmed edge sensitive, then they should remain
high for atleast one machine cycle and low for atleast one machine cycle, for being sensed.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Assessment Questions and Answers focuses on “Interrupt and
Stack of 8051 – 2”.
1. The timer generates an interrupt, if the count value reaches to
a) 00FFH
b) FF00H
c) 0FFFH
d) FFFFH
Answer: d
Explanation: The timer is an up-counter and generates an interrupt when the count has reached
FFFFH.
2. The external interrupt that has the lowest priority among the following is
a) TF0
b) TF1
c) IE1
d) NONE
Answer: c
Explanation: The order of given interrupts from high to low priority is TF0, IE1 and TF1.
3. Among the five interrupts generated by 8051, the lowest priority is given to the interrupt
a) IE0
b) TF1
c) TF0
d) RI
Answer: d
Explanation: The interrupt, RI=TI
serialport
is given the lowest priority among all the interrupts.
4. Among the five interrupts generated by 8051, the highest priority is given to the interrupt
a) IE0
b) TF1
c) TF0
d) IE1
Answer: a
Explanation: The interrupt, IE0
ExternalINT0
is given the highest priority among all the interrupts.
5. All the interrupts are enabled using a special function register called
a) interrupt priority register
b) interrupt register
c) interrupt function register
d) interrupt enable register
Answer: d
Explanation: All the interrupts are enabled using a special function register called interrupt
enable register
IE
and their priorities are programmed using another special function register called interrupt
priority register
IP
.
6. The number of bytes stored on the stack during one operation of PUSH or POP is
a) 1
b) 2
c) 3
d) 4
Answer: a
Explanation: As 8051 stack operations are 8-bit wide i.e. in an operation using PUSH or POP
instruction, one byte of data is stored on a stack or retrieved from the stack. For implementing
16-bit operations, two 8-bit operations are cascaded.
7. The step involved in PUSH operation is
a) increment stack by 2 and store 8-bit content to address pointed to by SP
b) decrement stack by 1 and store 16-bit content to address pointed to by SP
c) increment stack by 1 and store 8-bit content to address pointed to by SP
d) store 8-bit content to address pointed to by SP and then increment stack by 1
Answer: c
Explanation: The PUSH instruction follows two steps.
1. Increment stack by 1
2. Store 8-bit content of the 8-bit address specified in the instruction to the address pointed to by
SP.
8. The step involved in POP operation is
a) decrement stack by 2 and store 8-bit content to address pointed to by SP
b) store 16-bit content to address pointed to by SP and decrement stack by 1
c) decrement stack by 1 and store content of top of stack to address pointed to by SP
d) store content of top of stack to address pointed to by SP and then decrement stack by 1
Answer: d
Explanation: The POP instruction follows two steps.
1. Store the contents of top of stack pointed to by SP register to the 8-bit memory specified in
the instruction.
2. Decrement stack by 1.
9. The 8051 stack is
a) auto-decrement during PUSH operations
b) auto-increment during POP operations
c) auto-decrement during POP operations
d) auto-increment during PUSH operations
Answer: d
Explanation: The 8051 stack is opposite to that in 8085 or 8086 i.e. in 8085 it is auto-decrement
while in 8051 it is auto-increment during PUSH operations.
10. After reset, the stack pointer
SP
is initialized to the address of
a) internal ROM
b) internal RAM
c) external ROM
d) external RAM
Answer: b
Explanation: The stack pointer
SP
is an 8-bit register and is initialized to internal RAM address 07H after reset.
To practice all areas of Microprocessors Assessment Questions, here is complete set of 1000+
Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Addressing Modes of 8051”.
1. Which of the following is not an addressing mode of 8051?
a) register instructions
b) register specific instructions
c) indexed addressing
d) none
Answer: d
Explanation: The six addressing modes of 8051 are
1. Direct addressing
2. Indirect addressing
3. Register instructions
4. Register specific
RegisterImplicit
instructions
5. Immediate mode
6. Indexed addressing.
2. The symbol, ‘addr 16’ represents the 16-bit address which is used by the instructions to
specify the
a) destination address of CALL
b) source address of JUMP
c) destination address of call or jump
d) source address of call or jump
Answer: c
Explanation: The symbol, ‘addr 16’ represents the 16-bit destination address which is used by
the LCALL or LJMP instruction to specify the call or jump destination address, within 64 Kbytes
program memory.
3. The storage of addresses that can be directly accessed is
a) external data RAM
b) internal data ROM
c) internal data RAM and SFRS
d) external data ROM and SFRS
Answer: c
Explanation: Only internal data RAM and SFRS can be directly addressed in direct addressing
mode.
4. The address register for storing the 16-bit addresses can only be
a) stack pointer
b) data pointer
c) instruction register
d) accumulator
Answer: b
Explanation: The address register for storing the 16-bit addresses can only be data pointer.
5. The address register for storing the 8-bit addresses can be
a) R0 of the selected bank of register
b) R1 of the selected bank of register
c) Stack pointer
d) All of the mentioned
Answer: d
Explanation: The registers R0 and R1 of the selected bank of registers or stack pointer can be
used as address registers for storing the 8-bit addresses.
6. The instruction, ADD A, R7 is an example of
a) register instructions
b) register specific instructions
c) indexed addressing
d) none
Answer: a
Explanation: In register instructions addressing mode, operands are stored in the registers
R0-R7 of the selected register bank. One of these registers is specified in the instruction.
7. The addressing mode, in which the instructions has no source and destination operands is
a) register instructions
b) register specific instructions
c) direct addressing
d) indirect addressing
Answer: b
Explanation: In register specific instructions addressing mode, the instructions don’t have
source and destination operands. Some of the instructions always operate only on a specific
register.
8. The instruction, RLA performs
a) rotation of address register to left
b) rotation of accumulator to left
c) rotation of address register to right
d) rotation of accumulator to right
Answer: b
Explanation: The instruction, RLA rotates accumulator left.
9. The instruction, ADD A, #100 performs
a) 100
decimal
is added to contents of address register
b) 100
decimal
is subtracted from the accumulator
c) 100
decimal
is added to contents of an accumulator
d) none
Answer: c
Explanation: Immediate data 100
decimal
is added to the contents of the accumulator.
10. In which of these addressing modes, a constant is specified in the instruction, after the
opcode byte?
a) register instructions
b) register specific instructions
c) direct addressing
d) immediate mode
Answer: d
Explanation: In immediate mode, an immediate data, i.e. a constant is specified in the
instruction, after the opcode byte.
11. The only memory which can be accessed using indexed addressing mode is
a) RAM
b) ROM
c) Main memory
d) Program memory
Answer: d
Explanation: Only program memory can be accessed using the indexed addressing mode.
12. The data address of look-up table is found by adding the contents of
a) accumulator with that of program counter
b) accumulator with that of program counter or data pointer
c) data register with that of program counter or accumulator
d) data register with that of program counter or data pointer
Answer: b
Explanation: The look-up table data address is found out by adding the contents of register
accumulator with that of the program counter or data pointer.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “8051 Instruction Set -1”.
1. Which of the following is not an instruction of 8051 instructions?
a) arithmetic instructions
b) boolean instructions
c) logical instructions
d) none
Answer: d
Explanation: The 8051 instructions are categorized as
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Boolean instructions
5. Control transfer instructions.
2. The operations performed by data transfer instructions are on
a) bit data
b) byte data
c) 16-bit data
d) all of the mentioned
Answer: d
Explanation: The data transfer instructions implement a bit, byte, 16-bit data transfer operations
between the SRC
source
and DST
destination
operands.
3. Which of the following is true while executing data transfer instructions?
a) program counter is not accessible
b) restricted bit-transfer operations are allowed
c) both operands can be direct/indirect register operands
d) all of the mentioned
Answer: c
Explanation: In data transfer instructions,
1. Program counter is not accessible.
2. Restricted bit-transfer operations are allowed.
3. Both operands can be direct/indirect register operands.
4. BOth operands can be internal direct data memory operands.
4. The logical instruction that affects the carry flag during its execution is
a) XRL A;
b) ANL A;
c) ORL A;
d) RLC A;
Answer: d
Explanation: The logical instructions that doesn’t affect the carry flag are, ANL, ORL and XRL.
The logical instructions that affect the carry flag during its execution are RL, RLC, RRC and RR.
5. The instruction that is used to complement or invert the bit of a bit addressable SFR is
a) CLR C
b) CPL C
c) CPL Bit
d) ANL Bit
Answer: c
Explanation: The instruction, CPL Bit is used to complement or invert the bit of a bit addressable
SFR or RAM.
6. The instructions that change the sequence of execution are
a) conditional instructions
b) logical instructions
c) control transfer instructions
d) data transfer instructions
Answer: c
Explanation: The control transfer instructions transfer the control of execution or change the
sequence of execution conditionally or unconditionally.
7. The control transfer instructions are divided into
a) explicit and implicit control transfer instructions
b) conditional and unconditional control transfer instructions
c) auto control and self control transfer instructions
d) all of the mentioned
Answer: b
Explanation: The control transfer instructions are divided into conditional and unconditional
control transfer instructions.
8. The conditional control transfer instructions check a bit condition which includes any bit of
a) bit addressable RAM
b) bit addressable SFRs
c) content of accumulator
d) all of the mentioned
Answer: d
Explanation: The conditional control transfer instructions check a bit condition which includes
any bit of bit addressable RAM or bit addressable SFRs or content of accumulator for
transferring the control to the specified jump location.
9. All conditional jumps are
a) absolute jumps
b) long jumps
c) short jumps
d) none
Answer: c
Explanation: All conditional jumps are short jumps.
10. The first byte of a short jump instruction represents
a) opcode byte
b) relative address
c) opcode field
d) none
Answer: a
Explanation: The short jump instruction has two byte instruction. The first byte represents
opcode byte and second byte represents an 8-bit relative address.
11. In logical instructions, the immediate data can be an operand for
a) increment operation
b) decrement operation
c) single operand instruction
d) none
Answer: d
Explanation: In logical instructions, the immediate data can’t be an operand for
increment/decrement or any other single operand instruction.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Questions and Answers for Aptitude test focuses on “8051
Instruction Set -2”.
1. If the most significant bit of relative address byte is 1, then the short jump instruction is
a) forward jump
b) back jump
c) either forward or back jump
d) none
Answer: b
Explanation: If the most significant bit of relative address byte is 1, then the short jump
instruction is back jump, else it is considered as forward jump.
2. The first byte of an absolute jump instruction consists of
a) 3 LSBs of opcode and 5 MSBs of 11-bit address
b) 5 MSBs of opcode and 3 LSBs of 11-bit address
c) 6 MSBs of opcode and 1 LSB of 11-bit address
d) 5 LSBs of opcode and 3 MSBs of 11-bit address
Answer: d
Explanation: The first byte of an absolute jump instruction consists of 5 LSBs of opcode and 3
MSBs of 11-bit address. The next byte carries the least significant 8 bits of the 11-bit address.
3. The third byte of the long jump instruction is
a) opcode
b) 5 LSBs of opcode
c) higher byte of jump location or subroutine
d) lower byte of jump location or subroutine
Answer: c
Explanation: The third byte of the long jump instruction is a higher byte of jump location or
subroutine.
4. The absolute jump instruction is intended mainly for a jump within a memory space of
a) 2 bytes
b) 2 Kbytes
c) 2 Mbytes
d) none
Answer: b
Explanation: The absolute jump instruction is intended mainly for a jump within a memory space
of 2 Kbytes.
5. The LJMP instruction is very useful in programming in the external code memory space of
a) 32 MB
b) 64 MB
c) 32 KB
d) 64 KB
Answer: d
Explanation: The LJMP instruction is very useful in programming in the external code memory
space of 64 KB.
6. Which of the following is not an unconditional control transfer instruction?
a) JMP
b) RET
c) JNC
d) CALL
Answer: c
Explanation: The instructions, JMP, RET, RETI, CALL are the unconditional control transfer
instructions.
7. The conditional control transfer instructions use
a) status flags
b) bits of bit addressable RAM
c) SFRs termed bit
d) all of the mentioned
Answer: d
Explanation: The conditional control transfer instructions use status flags or bits of bit
addressable RAM or SFRs termed bit.
8. Which of the following is not a conditional control transfer instruction?
a) JC
b) JBC
c) JNC
d) NONE
Answer: d
Explanation: The instructions, JC, JBC, JNC, JB and JNB are the conditional control transfer
instructions.
9. The mnemonic used to perform a subtraction of source with an 8-bit data and jumps to
specified relative address if subtraction is non-zero is
a) DJNZ
b) CJNE
c) JZ
d) JNC
Answer: b
Explanation: The CJNE instruction perform a subtraction of source with an 8-bit data and jumps
to specified relative address only if the result of the subtraction is non-zero, else continues to
the next instruction.
10. The mnemonic, JNB is used to jump to the specified relative address only if
a) specified bit=1
b) specified bit=0
c) specified bit is non-recursive
d) none
Answer: a
Explanation: The mnemonic, JNB is used to jump to the specified relative address only if
specified bit=1, else continues to the next instruction.
11. The type of operand that is not allowed to use in boolean instructions of 8051 is
a) direct register operands
b) indirect register operands
c) immediate bit
d) none
Answer: c
Explanation: In boolean instructions, the immediate bit is not allowed as an operand.
12. In boolean instructions, the flag that is the only allowed destination operand for two operand
instructions is
a) overflow flag
b) underflow flag
c) auxiliary flag
d) carry flag
Answer: d
Explanation: Carry flag
C
is the only allowed destination operand for two operand instructions in boolean instructions.
To practice all areas of Microprocessors for Aptitude test, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interfacing With 8051 Ports -1”.
1. Which of the following is not one of the SFR addresses of the ports of 8051?
a) 80H
b) 90H
c) A0H
d) NONE
Answer: d
Explanation: The SFR addresses of the ports P0, P1, P2 and P3 are 80H, 90H, A0H and B0H
respectively.
2. Each port line of a port can individually source a current of upto
a) 0.2 mA
b) 0.25 mA
c) 0.5 mA
d) 0.75 mA
Answer: c
Explanation: Each port line of a port can individually source a current of upto 0.5 mA.
3. Each port line of a port can individually sink a current of upto
a) 2 mA
b) 8 mA
c) 5 mA
d) 1 mA
Answer: b
Explanation: Each port line of a port can individually sink a current of upto 8 mA.
4. The number of TTL inputs that can be sinked by the port 0 when a logic 0 is sent to a port line
as an output port is
a) 2
b) 4
c) 6
d) 8
Answer: d
Explanation: When a logic 0 is sent to a port line as an output port, it can sink 8 LS TTL inputs.
Port 0 is used as data bus during external interfacing whenever required.
5. The open drain bidirectional
inputoroutput
port with internal pullups is
a) Port 0
b) Port 1
c) Port 2
d) Port 3
Answer: a
Explanation: Port 0 is an open drain bidirectional
inputoroutput
port with internal pullups. Port 1, Port 2, Port 3 are 8-bit bidirectional ports.
6. The port that can source or sink 4 LS TTL inputs when being used as an output port on each
of its line is
a) Port 1
b) Port 2
c) Port 3
d) all of the mentioned
Answer: d
Explanation: The ports P1, P2 and P3 can source or sink 4 LS TTL inputs when being used as
an output port on each of its line.
7. The port that will source a current of 500 micro amperes when being used as input ports is
a) 0.5 mA
b) 0.25 mA
c) 250 micro amperes
d) 500 micro amperes
Answer: d
Explanation: Port 3 pins which are externally pulled low when being used as input pins will
source current of 500 micro amperes.
8. If the EA
activelow
signal is grounded then the execution
a) directly start from main memory
b) directly start from 16 bit address in main memory
c) directly start from 16 bit address in program memory
d) directly start from RAM
Answer: c
Explanation: For interfacing external program memory, EA
activelow
pin must be grounded. If the EA
activelow
signal is grounded then the execution will start directly from the 16-bit address 0000H in
external program memory.
9. When the port lines of a port are to be used as input lines then the value that must be written
to the port address is
a) F0H
b) 0FH
c) FFH
d) 00H
Answer: c
Explanation: When the port lines of a port are to be used as input lines then ‘FF’H must be
written to the port address.
10. Port 1 lines are used during programming of
a) external EPROM and EEPROM
b) external ROM and RAM
c) internal ROM and RAM
d) internal EPROM and EEPROM
Answer: d
Explanation: Port 1 lines are used as lower byte of 16-bit address bus during programming of
internal EPROM or EEPROM.
11. The configuration in which each LED receives operating current of 8 mA from power supply
while the port lines sink the current on each port line is
a) common port configuration
b) common anode configuration
c) common cathode configuration
d) none of the mentioned
Answer: b
Explanation: The common anode configuration is preferred to that of other configurations as in
common anode configuration, each LED receives operating current of 8 mA from power supply
while the port lines sink the current on each port line.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Questions and Answers for Campus interviews focuses on
“Interfacing With 8051 Ports -2”.
1. If EA
activelow
signal =1, then the execution starts from
a) internal EPROM
b) flash RAM
c) internal EPROM or flash RAM
d) none
Answer: c
Explanation: If EA
activelow
signal =1, then the execution starts from an internal EPROM or flash RAM address 000H, can
continue upto FFFH address and then for higher addresses it will go into external memory.
2. The pin that is grounded for interfacing external EPROM is
a) EA
activelow
b) PSEN
activelow
c) OE
activelow
d) All of the mentioned
Answer: a
Explanation: The EA
activelow
pin is grounded for interfacing external EPROM. The PSEN
activelow
is used for interfacing EPROM i.e. it acts as an OE
activelow
input to EPROM.
3. The step that is involved in the procedure of memory interfacing with 8051 is
a) data bus is connected to data lines of memory chips
b) PSEN
activelow
is connected to OE
activelow
of EPROM chips
c) writing address map of memory chip in bit form
d) all of the mentioned
Answer: d
Explanation: The procedure of memory interfacing with 8051 includes, data bus connection to
data lines of memory chips, PSEN
activelow
connected to OE
activelow
of EPROM chips and writing address map of memory chip in bit form.
4. The device that is used for deriving chip select signals is
a) Logic gates
b) Multiplexers
c) PLAs and EPROMs
d) All of the mentioned
Answer: d
Explanation: The logic gates and multiplexers are most commonly used for deriving chip select
signals. The advanced circuits like PLAs and EPROMs are also used for deriving chip select
signals.
5. For deriving chip selects of isolated memory or IO devices, the gates that are traditionally
used are
a) NOR and NAND
b) NAND and NOT
c) NOT and NOR
d) AND, OR and NOT
Answer: b
Explanation: For deriving chip selects of isolated memory or IO devices, the NAND and NOT
gates are traditionally used.
6. The current that is required for a LED for an appropriate glow is
a) 6-8 mA
b) 4-6 mA
c) 8-10 mA
d) 10-12 mA
Answer: c
Explanation: For appropriate glow, a LED typically requires 8-10 mA with around 1.6 Volts.
7. The maximum current that can be sinked totally by all the ports of 8051 is
a) 61 mA
b) 81 mA
c) 91 mA
d) 71 mA
Answer: d
Explanation: All the ports together
4ports
should not be made to sink more than 71 mA.
8. The number of LEDs that can be connected to a port of 8051, if all are expected to glow
simultaneously is
a) 6
b) 8
c) 10
d) 12
Answer: b
Explanation: If 8 LEDs are connected to a port of 8051, and if all are expected to glow
simultaneously, the total current sinked by the 8051 port will be 8×8=64 mA
sinceminvoltageforanLEDtoglow=8mA
which is less than the maximum 71 mA.
9. Which is true in interfacing 7 segment code display?
a) transmitted by second port
b) display is selected by third port
c) display is selected by second port
d) none of the mentioned
Answer: c
Explanation: The 7-segment code of a digit is transmitted by the first port and the display is
selected by second port. As soon as the display is selected by the second port, the digit starts
glowing on that display position.
10. After the display is selected by second port, then the digit
LED
glows for a duration of
a) 5 msec
b) 10 msec
c) 2 msec
d) 6 msec
Answer: a
Explanation: The unit
LED
glows for a duration of 5 msec.
11. The number of scans of the complete 8-digit display that can be carried out in one second is
a) 15
b) 25
c) 35
d) 55
Answer: b
Explanation: Starting from either right most or left most digit, every digit glows for 5 msec one by
one. Thus one scan of the 8 digit display requires 40 msec. Thus in one second, 25 scans of the
complete 8-digit display can be carried out.
12. To convert its current output into a voltage, the DAC 0808 is connected with
a) Transistor
BJT
externally
b) FET externally
c) OPAMP externally
d) OPAMP internally
Answer: c
Explanation: the DAC 0808 is connected with OPAMP externally, to convert its current output
into voltage.
To practice all areas of Microprocessors for Campus Interviews, here is complete set of 1000+
Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interrupt Structure of 8051”.
1. The external interrupts of 8051 can be enabled by
a) 4 LSBs of TCON register
b) Interrupt enable
c) priority register
d) all of the mentioned
Answer: d
Explanation: The external interrupts namely INT0
activelow
and INT1
activelow
can be enabled and programmed using the least significant four bits of TCON register and the
Interrupt enable and priority registers.
2. The bits that control the external interrupts are
a) ET0 and ET1
b) ET1 and ET2
c) EX0 and EX1
d) EX1 and EX2
Answer: c
Explanation: The bits, EX0 and EX1 individually control the external interrupts, INT0
activelow
and INT1
activelow
. If INT0
activelow
and INT1
activelow
interrupts are to be enabled then the bits EX0 and EX1 must be set respectively.
3. EA bit is used to
a) enable or disable external interrupts
b) enable or disable internal interrupts
c) enable or disable all the interrupts
d) none of the mentioned
Answer: c
Explanation: Using EA bit, all the interrupts can be enabled or disabled. Using the individual
respective bit, the respective interrupt can be enabled or disabled.
4. The number of priority levels that each interrupt of 8051 have is
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: Each interrupts level of 8051 can have two levels of priority namely level 0 and
level 1. Level 1 is considered as a higher priority level compared to level 0.
5. The priority level of an interrupt of 8051 for which SI
serialinterrupt
interrupt is programmed is
a) level 0
b) level 1
c) level 0 or level 1
d) none
Answer: b
Explanation: SI interrupt is programmed for level 1 priority.
6. The interrupt bit that when set works at level 1, and otherwise at level 0 is
a) PT1
b) PT0
c) PX1
d) All of the mentioned
Answer: d
Explanation: The bits, PT1, PT0, PX0 and PX1 when set, work at level 1, otherwise at level 0.
7. All the interrupts at level 1 are polled in the second clock cycle of the
a) forth T state
b) fifth T state
c) third T state
d) none
Answer: b
Explanation: All the interrupts at level 1 are polled or sensed in the second clock cycle of the
fifth T state or 9th clock cycle out of 12 clock cycles. Then all the interrupts at level 0 are also
polled in the same cycle.
8. The minimum duration of the active low interrupt pulse for being sensed without being lost
must be
a) greater than one machine cycle
b) equal to one machine cycle
c) greater than 2 machine cycles
d) equal to 2 machine cycles
Answer: b
Explanation: The minimum duration of the active low interrupt pulse should be equal to the
duration of one machine cycle for being sensed, else it will be lost.
9. If two interrupts, of higher priority and lower priority occur simultaneously, then the service
provided is for
a) interrupt of lower priority
b) interrupt of higher priority
c) lower & higher priority interrupts
d) none of the mentioned
Answer: b
Explanation: If two interrupts, occur simultaneously, then the one with higher priority level and
early polling sequence will receive service. The other one with lower priority may get lost there,
as there is no mechanism for storing the interrupt requests.
10. For an interrupt to be guaranteed served it should have duration of
a) one machine cycle
b) three machine cycles
c) two machine cycles
d) four machine cycles
Answer: c
Explanation: For an interrupt to be guaranteed served it should have duration of two machine
cycles.
11. The service to an interrupt will be delayed if it appears during the execution of
a) RETI instruction
b) Instruction that writes to IE register
c) Instruction that writes to IP register
d) All of the mentioned
Answer: d
Explanation: The service to an interrupt will be delayed if it appears during the execution of
RETI instruction or the instruction that writes to IE/IP registers.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Serial Communication Unit”.
1. The serial communication is
a) cheaper communication
b) requires less number of conductors
c) slow process of communication
d) all of the mentioned
Answer: d
Explanation: The serial communication requires less number of conductors and thus it is
cheaper. It is slow as the bits are transmitted one by one along with start, stop and parity bits.
2. The serial communication is used for
a) short distance communication
b) long distance communication
c) short and long distance communication
d) communication for a certain range of distance
Answer: b
Explanation: Serial communication is more popular for communication over longer distances as
it requires less number of conductors.
3. The mcs 51 architecture supports
a) serial transmission and reception
b) simultaneous transmission and reception
c) transmission and reception of data using serial communication interface
d) all of the mentioned
Answer: d
Explanation: The mcs 51 architecture supports simultaneous transmission and reception of
binary data byte by byte i.e. full duplex mode of communication. It supports serial transmission
and reception of data using standard serial communication interface and baud rates.
4. The number of bits transmitted or received per second is defined as
a) transmission rate
b) reception rate
c) transceiver rate
d) baud rate
Answer: d
Explanation: Here, baud rate can be defined as the number of bits transmitted or received per
second.
5. The task of converting the byte into serial form and transmitting it bit by bit along with start,
stop and parity bits is carried out by
a) reception unit
b) serial communication unit
c) transmission unit
d) all of the mentioned
Answer: c
Explanation: the serial communication unit consists of transmission unit and reception unit. The
task of converting the byte into serial form and transmitting it bit by bit along with start, stop and
parity bits is carried out by transmission unit.
6. The transmission unit does not require assistance from processor if once a byte for
transmission is written to
a) SCON register
b) SBUF register
c) SFR address
d) Any of the mentioned
Answer: b
Explanation: once a byte for transmission is written to the serial buffer
SBUF
register, the transmission unit does not require assistance from a processor.
7. The common unit shared by the receiver unit and transmission unit of serial communication
unit is
a) SCON
SerialPortControl
Register
b) SBUF
SerialBuffer
register
c) 8-bit serial data interface
d) All of the mentioned
Answer: d
Explanation: The transmission unit and receiver unit both are controlled by using a common
SCON
SerialPortControl
Register. Also both units share a common serial buffer
SBUF
register which is a common 8-bit serial data interface.
8. During serial reception, the buffer that receives serial bits and converts to a byte is
a) receive buffer 0
b) receive buffer 1
c) receive buffer 2
d) none
Answer: b
Explanation: During serial reception, the receive buffer 1 receives serial bits and converts to a
byte, it then transfers the received parallel byte in receive buffer 2.
9. If SM0=1, SM1=0, then the transceiver selected is
a) 8-bit synchronous
b) 9-bit synchronous
c) 8-bit asynchronous
d) 9-bit asynchronous
Answer: d
Explanation: If SM0=1, SM1=0, then the 9-bit asynchronous transceiver is selected.
10. If the microcontroller is expected to communicate in a multiprocessor system, then the
required condition is
a) SM0 is set
b) SM1 is set
c) SM2 is set
d) REN is set
Answer: c
Explanation: The bit, SM2 is set if the microcontroller is expected to communicate in a
multiprocessor system.
11. In mode 2, the baud rate depends only on
a) SMOD bit
b) SCON bit
c) Oscillator clock frequency
d) SMOD bit and oscillator clock frequency
Answer: d
Explanation: In mode 2, the baud rate depends only on SMOD bit and oscillator clock frequency.
12. The mode that offers the most secured parity enabled data communication at lower baud
rates is
a) mode 2
b) mode 1
c) mode 0
d) all of the mentioned
Answer: a
Explanation: The mode 3 offers the most secured parity enabled data communication at lower
baud rates of mode 1.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Power Control Register”.
1. The power control register is
a) used for power saving during idle state
b) used for eventual power off to 8051 chip
c) non-bit addressable register
d) all of the mentioned
Answer: d
Explanation: The power control register is used for power saving during idle state of the
microcontroller and eventual power off to the microcontroller chip. It has SMOD bit which is used
to double the baud rate.
2. The state of signals in idle mode is
a) ALE is high
b) PSEN is high
c) PSEN
activelow
is high
d) ALE and PSEN
activelow
are high
Answer: d
Explanation: ALE and PSEN
activelow
remain high in Idle mode.
3. To come out of idle mode, the external interrupt that is enabled is
a) SI
serial
b) INT0
c) INT1
d) All of the mentioned
Answer: d
Explanation: To come out of idle mode, any external interrupt that is enabled like SI
Serial
, INT0 and INT1.
4. The microcontroller enters into power down mode when
a) SMOD bit of PCON is set
b) GF1 bit of PCON is set
c) PD bit of PCON is set
d) GF2 bit of PCON is set
Answer: c
Explanation: If the PD bit of PCON register is set, it enters power down mode.
5. The clock signal is disabled to all parts of 8051 in
a) normal mode
b) idle mode
c) power down mode
d) addressing mode
Answer: c
Explanation: In power down mode, the clock signal to all parts of 8051 chip is disabled.
6. During power down to save battery, the supply voltage can be reduced to a value of
a) 4 volts
b) 2 volts
c) 8 volts
d) 1 volt
Answer: b
Explanation: The supply voltage can be reduced to a value of around 2 volts, during power
down to save battery.
7. The signal that only pulls the microcontroller
8051
out of the power down mode is
a) CLEAR
b) LEAVE
c) RESET
d) EXIT
Answer: c
Explanation: Only Reset signal can pull 8051 out of the power down mode.
8. The state of signals in power down mode is
a) ALE is high
b) PSEN is low
c) ALE and PSEN
activelow
are high
d) ALE and PSEN
activelow
are low
Answer: d
Explanation: ALE and PSEN
activelow
remain low in power down mode of 8051.
9. In power down mode,
a) Port pins maintain their logic levels
b) SFRs maintain their logic levels
c) Clock signal is disabled
d) All of the mentioned
Answer: d
Explanation: In power down mode, the clock signal is disabled and all the port pins and
respective SFRs maintain their logic levels.
10. The SMOD bit is used to
a) decrease the baud rate by 2
b) increase the baud rate by 4
c) increase the baud rate by 2
d) triple the baud rate
Answer: c
Explanation: The SMOD bit is used to double the baud rate.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
MICROPROCESSOR (KCS 403)
1) Which is the microprocessor comprises:
a) Register section
b) One or more ALU
c) Control unit
d) All of these
2) What is the store by register?
a) Data
b) Operands
c) Memory
d) None of these
3) Accumulator based microprocessor examples are:
a) Intel 8085
b) Intel 8086
c) a and b both
d) None of these
4) A set of register which contain are:
a) Data
b) memory addresses
c) result
d) all of these
5) There are primarily two types of register
a) General purpose register
b) Dedicated register
c) A and B
d) none of these
6) Name of typical dedicated register is
a) PC
b) IR
c) SP
d) All of these
7) BCD stands for
a) Binary coded decimal
b) Binary coded decoded
c) Both a
&b
d) None of
these
8) The processor 80386/ 80486 and Pentium processor uses ____ bits address bus
a) 16
b) 32
c) 36
d) 64
9) Which is not the control bus signal:
a) READ
b) WRITE
c) RESET
MICROPROCESSOR (KCS 403)
d) None of these
10) PROM stands for:
a) Programmable read-only memory
b) Programmable read write memory
c) Programmer read and write memory
d) None of these
11) EPROM stands for:
a) Erasable Programmable read-only memory
b) Electrically Programmable read write memory
c) Electrically Programmable read-only memory
d) None of these
12) Each memory location has
a) Address
b) Contents
c) Both a and b
d) None of these
13) Customized ROMS are called
a) Mask ROM
b) Flash ROM
c) EPROM
d) None of these
14) A microprocessor retries instructions from
a) Control memory
b) Cache memory
c) Main memory
d) Virtual memory
15) Which causes the microprocessor to immediately terminate its present activity
a) RESET signal
b) INTERUPT signal
c) Both
d) None of these
16) INTR : it implies the signal:
a) INTRRUPT REQUEST
b) INTRRUPT RIGHT
c) INTRRUPT WRONG
d) INTRRUPT RESET
17) Which of the following are the two main components of the CPU?
a) Control Unit and Registers
b) Registers and Main Memory
c) Control unit and ALU
d) ALU and Bus
18) The language that the computer can understand and execute is called
a) Machine language
b) Application software
c) System program
MICROPROCESSOR (KCS 403)
d) All of the above
19) Which of the following memories needs refresh?
a) SRAM
b) DRAM
c) ROM
d) ALL of the above
20) The memory which is programmed at the time it is manufactured
a) PROM
b) RAM
c) PPROM
d) EPROM
21) The first microprocessor built by the Intel Corporation was called
a) 8008
b) 8080
c) 4004
d) 8800
22) Which is the type of memory for information that does not change on
your computer?
a) RAM
b) ROM
c) ERAM
d) RW/RAM
23) Which company is the biggest player in the microprocessor industry?
a) Motorola
b) IBM
c) INTEL
d) AMD
24) The term giga byte refers to
a) 1024 bytes
b) 1024 kilobytes
c) 1024 megabytes
d) 1024 gigabytes
25) 4GB ROM consist of
a) 12 Address lines
b) 32 Address lines
c) 4 Address lines
d) 10 Address lines
26) Which 3x8 decoder IC used for interfacing
a) 74HS13
b) 74LS17
c) 74LS138
d) 9955
27) FFH equivalent to in binary
a) 00001111
MICROPROCESSOR (KCS 403)
b) 11001100
c) 11001111
d) 11111111
28) Universal logic gates are
a) AND, OR
b) OR, NOT
c) NAND, NOR
d) NAND, OR
29) C and C++ is
a) Low level language
b) High level language
c) Assembly level language
d) None of these
30) 32-bit microprocessor consist
of
a) 32 data lines
b) 16 data lines
c) 32 address lines
d) 16 address lines
31. 8085 microprocessor Instruction LHLD 1234H is having following Addressing Mode:
a) Register addressing mode
b) Direct addressing mode
c) Indirect addressing mode
d) Implied addressing mode
32. What is the purpose of the READY signal in 8085
a) It is used to provide WAIT states when the 8085 is communicating with a slow
peripheral device.
b)It indicates that the 8085 is ready to receive inputs
c) It indicates that the 8085 is ready to provide Direct Memory Access
d) It indicates that the 8085 is ready to send outputs
33. Number of machine cycles required to execute LXI H, 7835H instruction in 8085 will
be:
a) 1 machine cycle
b) 3 machine cycles
c) 5 machine cycles
d) 2 machine cycles
34. Number of T states required to execute JMP 5012H instruction is:
a) 10
b) 16
c) 13
d) 7
35. If Register A=59H and Register D= 4DH then after execution of ADD D value of Carry
and Zero flag will be:
a)CF= 0, ZF=0
b) CF= 0, ZF=1
c) CF= 1, ZF=0
MICROPROCESSOR (KCS 403)
d) CF= 1, ZF=1
36. In memory read machine cycle in 8085 , values of status signals are :
a) S0= 0, S1=0
b) S0= 1, S1=0
c) S0= 0, S1=1
d) S0= 1, S1=1
37. Memory handling capacity of 8085 microprocessor is:
a) 64 KB
b) 1MB
c) 16 MB
d) 4 MB
38. A programming model of a microprocessor is ____.
a) list of all I/O devices that can be connected
b) diagrams of the internal bus architecture
c) part of the block diagram that a programmer can affect using the instruction set
d) the entire block diagram
39. The frequency of 8085 microprocessor is
a) 3MHz
b) 1Hz
c) 2Hz
d) 3KHz
40. The vector address of TRAP is
a) 0024H
b) 0038H
c) 002AH
d) 0020H
41. Non-Maskable Interrupt is
a) RST 7.5
b) RST 5.5
c) INTR
d) TRAP
42. Which pin is used for de-multiplexing of buses
a) ALE
b) BHE
c) RD
d) WR
43. The instruction size of LDA 3000H is
a) 3 Byte
b) 2 Byte
c) 1 Byte
MICROPROCESSOR (KCS 403)
d) 4 Byte
44. Example of Immediate addressing mode is
a) STA 3000H
b) LDA 3000H
c) MVI A, 32H
d) HLT
45. 8085 consist of I/O ports:
a) 256
b) 128
c) 32
d) 8
46. 8085 consist of address lines:
a) 24
b) 16
c) 8
d) 32
47. SP and PC are known as
a) Stack program and Program coin
b) Stack pointer and Program counter
c) Static pointer and Permanent counter
d) Stack Program and Programmable counter
48. Which flag is used for checking number of 1’s in data
a) Carry
b) Sign
c) Zero
d) Parity
49. INR A is used for
a) Checking accumulator content
b) Increment accumulator content by one
c) Increment accumulator content by two
d) Decrement accumulator
50. Temp. registers in 8085 are
a) W and Z
b) X and Y
c) A and B
d) Y and Z
MICROPROCESSOR (KCS 403)
51. For 8085, the size of accumulator is
a) 4-bit
b) 8-bit
c) 16-bit
d) 24-bit
52. For 8085, the size of PC is
a) 4-bit
b) 8-bit
c) 16-bit
d) 24-bit
53. Which is not flag in 8085
a) Carry
b) Sign
c) Direction
d) Zero
54. ADD M is type of
a) Register addressing mode
b) Immediate addressing mode
c) Implied addressing mode
d) Indirect addressing mode
55. Which register pair has been used as by default memory pointer in 8085
a) H and L
b) W and Z
c) B and C
d) D and E
56. 8085 operating voltage is
a) +5V
b) -5V
c) +10V
d) -3V
57. HOLD and HLDA pins are related to
a) Serial data transfer
b) Parallel data transfer
c) DMA
d) None of these
58. Which machine cycle is used for fetching the data from input location:
MICROPROCESSOR (KCS 403)
a) Opcode fetch
b) I/O Read
c) I/O write
d) I/O fetch
59. Memory read consist of
a) 3T
b) 4T
c) 5T
d) 6T
60. After execution of MVI A, 00H, accumulator consist of
a) 32H
b) 00H
c) 24H
d) None of these
61. To execute one instruction at a time (single stepping execution) following flag bit is
used in 8086 microprocessor
a) Trap Flag
b) Interrupt Flag
c) Direction Flag
d) Overflow Flag
62. The maximum size of each segment in memory segmentation of 8086 is:
a) 16 KB
b) 32 KB
c) 48 KB
d) 64 KB
63. In 8086 one of the following statement is not true:
a) Coprocessor is interfaced in MIN mode.
b) Coprocessor is interfaced in MAX mode.
c) I/O can be interfaced in MIN/MAX mode.
d) Supports pipeline architecture
64. For Direction Flag(DF)=1, if starting address of string is 51004H then second string
element address will be:
a) 51003H
b) 51004H
c) 51005H
d) 51003H or 51005H.
65. In 8086 Microprocessor Overflow flag will set when
a) The sum is more than 16 bit.
b) Sign and Carry flag bits are set
c) Only sign flag is set.
d) Signed numbers go out of their range after arithmetic operation.
66. BIU in 8086 contains an instruction queue of size
MICROPROCESSOR (KCS 403)
a) 2 Bytes.
b) 4Bytes
c) 6 Bytes.
d) 8 Bytes.
67. EU in 8086 stands for
a) Extended unit.
b) End unit
c) Execution unit.
d) Encapsulation unit.
68. Which statement is false about EU in 8086 Microprocessor
a) It decodes various instructions.
b) It generates necessary control signals
c) It fetches instructions from memory.
d) It performs various arithmetic operations using ALU.
69. For CS= 1234H and IP= ABCDH, 20 bit physical address of the instruction will be:
a) 0BE01H.
b) 1FC0DH
c) 1CF0DH .
d) ACE04H.
70. For DS=1234H, Maximum Possible physical Address for an element in data segment
will be:
a) 2323F H
b) 21223F H
c) 2233F H
d) 2212F H
71. Which of the following index/pointer register cannot be used to provide offset address
with DS register to locate an element in data segment:
a) BX
b) IP
c) SI
d) DI
72. Memory handling capacity of 8086 microprocessor is:
a) 64 KB
b) 1MB
c) 16 MB
d) 4 MB
73. For 8086 microprocessor, following statement is false:
a) It supports memory segmentation.
b) It supports pipelined architecture
c) It supports multiprogramming.
d) It has a 20 bit data bus.
74. The number of segment registers available in 8086 microprocessor are:
a) 3
b) 4
c) 5
d) 6
MICROPROCESSOR (KCS 403)
75. 8086 microprocessor supports ______ number of flag bits.
e) 5
f) 7
g) 9
h) 11
76. 8086 consist of address lines:
a) 20
b) 16
c) 8
d) 24
77. 8086 microprocessor supports ______ number of software interrupts
e) 8
f) 16
g) 128
h) 256
78. Software interrupt which corresponds to division by zero error is:
e) TYPE 0
f) TYPE 1
g) TYPE 2
h) TYPE 3
79. INC instruction increases the content of destination register by:
a) 1
b) 2
c) 4
d) 8
80. Software interrupt which represents a break-point interrupt is:
a) TYPE 0
b) TYPE 1
c) TYPE 2
d) TYPE 3
81. in 8086 microprocessor, IP register is ____ bits length
e) 4-bit
f) 8-bit
g) 16-bit
h) 24-bit
82. For 8086, IF flag bit is recognized as:
e) Indicate flag
MICROPROCESSOR (KCS 403)
f) Inter flag
g) Interrupt flag
h) Initial flag
83. Which is true about hardware interrupts in 8086 microprocessor:
e) It supports only one hardware interrupt NMI
f) It supports two hardware interrupts NMI and INTR
g) It supports three hardware interrupts NMI, INTR and TRAP
h) It supports only one hardware interrupt INTR
84. Offset address is not provided by following____ register in 8086 microprocessor:
e) CS
f) SP
g) BP
h) IP
85. In 8086, ____Register is used to provide offset address in calculation of physical
address of next instruction is:
e) IP
f) BP
g) BX
h) SP
86. STC instruction is having following addressing mode:
a) Register addressing mode
b) Direct addressing mode
c) Indirect addressing mode
d) Implied addressing mode
87. MOV CL, DH instruction is having following addressing mode:
a) Register addressing mode
b) Direct addressing mode
c) Indirect addressing mode
d) Implied addressing mode
88. To clear the carry flag in 8086 microprocessor, following instruction is used:
a) STC
b) CLC
c) CMC
d) CLD
89. To set the direction flag in 8086 microprocessor, following instruction is used:
a) STC
b) STD
c) SETD
d) OLD
90. Software interrupt used for single step execution of program is:
a) TYPE 0
MICROPROCESSOR (KCS 403)
b) TYPE 1
c) TYPE 2
d) TYPE 3
91. A sequence of two register that multiplies the content of DE register pair by two and store
the result in HL register pair is
(a) XCHG and DAD B
(b) XTHL and DAD H
(c) PCHL and DAD B
(d) XCHG and DAD H
92. Consider the sequence of 8085 instruction given below.
LXI H, 9258H
MOV A,M
CMA
MOV M,A
Which one of the following is performed by this sequence?
(a) Contents of location 9258H are moved to accumulator
(b) Contents of location 9258H are compared with the contents of the accumulator
(c) Contents of location 9258H are complemented and stored in location 9258H
(d) Contents of location 5892H are complemented and stored in location 5892H
93. It is desired to multiply the numbers 0AH by 0BH and store the result in the accumulator.
The numbers are available in register B and C respectively. A part of the 8085 program
for this purpose is given below:
MVI A, 00H
Loop:_____________
___________________
HLT
END
The sequence of instructions to complete the program would be
(a) JNZ LOOP, ADD B, DCR C
(b) ADD B, JNZ LOOP, DCR C
(c) DCR C, JNZ LOOP, ADD B
(d) ADD B, DCR C, JNZ LOOP
94. The following program starts at location 0100H.
LXI SP, 00FFH
LXI H, 0107H
MVI A, 20H
SUB M
The content of accumulator when the program counter reaches 0109H is
(a) 20H
(b) 02H
(c) 00H
(d) FFH
95. For 8085 microprocessor, the following program is executed.
MVI A, 05H;
MICROPROCESSOR (KCS 403)
MVI B, 05H;
PTR: ADD B;
DCR B;
JNZ PTR;
ADI 03H;
HLT;
At the end of program, accumulator contains
(a) 17H
(b) 20H
(c) 23H
(d) 05H
96. An 8085 assembly language program is given below. Assume that the carry flag is
initially unset. The content of the accumulator after the execution of the program is
MVI A, 07H
RLC
MOV B,A
RLC
RLC
ADD B
RRC
(a) 8CH
(b) 64H
(c) 23H
(d) 15H
97. For the 8085 assembly language program given below, the content of the accumulator
after the execution of the program is
3000 MVI A, 45H
3002 MOV B, A
3003 STC
3004 CMC
3005 RAR
3006 XRA B
(a) 00H (b) 45H (c) 67H (d) E7H
98. An 8085 executes the following instructions
2710 LXI H, 30A0 H
2713 DAD H
2714 PCHL
All address and constants are in Hex. Let PC be the contents of the program counter and
HL be the contents of the HL register pair just after executing PCHL. Which of the
following statements is correct?
(a) PC=2715H HL=30A0H
(b) PC=30A0H HL=2715H
(c) PC=6140H HL=6140H
(d) PC=6140H HL=2715H
99. An 8085 assembly language program is given below.
MVI A, B5H
MICROPROCESSOR (KCS 403)
MVI B, 0EH
XRI 69H
ADD B
ANI 9BH
CPI 9FH
STA 3010H
HLT
The contents of the accumulator just execution of ADD instruction in line 4 will be
(a) C3H (b) EAH (c) DCH
(d) 69H
100. From question no. 9, after execution of line 7 of the program, the status of the CY
and Z flags will be
(a) CY=0, Z=0
(b) CY=0, Z=1
(c) CY=1, Z=0
(d) CY=1, Z=1
101. Following is the segment of a 8085 assembly language program
LXI SP, EFFFH
CALL 3000H
-
-
-
3000H: LXI H, 3CF4H
PUSH PSW
SPHL
POP PSW
RET
On completion of RET execution, the contents of SP is
(a) 3CF0 H (b) 3CF8 H (c) EFFD H (d) EFFF H
102. The following program starts at location 0100H.
LXI SP, 00FF
LXI H, 0701
MVI A, 20H
SUB M
The content of accumulator when the program counter reaches 0109 H is
(a) 20 H (b) 02 H (c) 00 H (d) FF H
103. Continuation of question no. 12, if in addition following code exists from 019H
onwards,
ORI 40 H
ADD M
What will be the result in the accumulator after the last instruction is executed
(a) 40 H (b) 20 H (c) 60 H (d) 42H
104. Consider the following assembly language program
MVI B, 87H
MOV A, B
START: JMP NEXT
MICROPROCESSOR (KCS 403)
MVI B, 00H
XRA B
OUT PORT1
HLT
NEXT: XRA B
JP START
OUT PORT2
HLT
The execution of above program in an 8085 microprocessor will result in
(a) an output of 87H at PORT1
(b) an output of 87H at PORT2
(c) infinite looping of the program execution with accumulator data remaining at 00H
(d) infinite looping of the program execution with accumulator data alternating between
00H and 87H
105. The contents of register (B) and accumulator (A) of 8085 microprocessor are 49J
are 3AH respectively. The contents of A and status of carry (CY) and sign (S) after
execution SUB B instructions are
(a) A = F1, CY = 1, S = 1
(b) A = 0F, CY = 1, S = 1
(c) A = F0, CY = 0, S = 0
(d) A = 1F, CY = 1, S = 1
106. The following instructions have been executed by an 8085 MP
ADDRESS (HEX) INSTRUCTION
6010 LXI H, 8 A 79 H
6013 MOV A, L
6015 ADDH
6016 DAA
6017 MOV H, A
6018 PCHL
From which address will the next instruction be fetched?
(a) 6019 (b) 6379 (c) 6979 (d) None of the above
107. The following sequence of instructions are executed by an 8085 microprocessor:
1000 LXI SP, 27 FF
1003 CALL 1006
1006 POP H
The contents of the stack pointer (SP) and the HL, register pair on completion of
execution of these instruction are
(a) SP = 27 FF, HL = 1003
(b) SP = 27 FD, HL = 1003
(c) SP = 27 FF, HL = 1006
(d) SP = 27 FD, HL = 1006
108. In a microprocessor system, the stack is a used for
(a) Storing the program return address whenever a subroutine jump instruction is
executed
(b) Transmitting and receiving input output data
(c) Storing all important CPU register contents whenever an interrupt is to be serviced
MICROPROCESSOR (KCS 403)
(d) Storing program instructions for interrupt service routine
109. In a microprocessor , the register which holds the address of the next instruction
to be fetched is
(a) Accumulator (b) Program Counter (c) Stack pointer (d) Instruction register
110. In an 8085 microprocessor , which one of the following instruction changes the
contents of accumulator?
(a) MOV B,M (b) PCHL (c) RNZ (d) SBI BEH
111. In an 8085 microprocessor, the contents of the accumulator and the carry flag are
A7H and 0 respectively. If the instruction RLC is executed, the nt contents of
accumulator and the carry flag respectively , will be
(a) 4EH and 0 (b) 4EH and 1 (c) 4F and 0 (d) 4F and 1
112. The following program is run on an 8085 microprocessor
Memory address Instruction
2000H LXI SP,1000H
2003H PUSH H
2004H PUSH D
2005H CALL 2050H
2008H POP H
2009H HLT
At the completion of execution of the program, contents of PC and SP is
(a) PC=200A, SP=1000H (b) PC=200A, SP=0FFEH (c) none (d) All
113. An 8085 microprocessor executes “STA 1234H” with starting address location
1FFEH. While the instruction is fetched and executed, the sequence of values written at
the address pin A15-A8 is
(a) 1FH,1FH,20H,12H (b) 1FH,1FH,12H,12H (c) both (d) none
114. Which one of the following 8085 microprocessor programs correctly calculates
the product of two 8 bit number stored in register B and C?
(a) MVI A,00H (C) both
CMP C
LOOP DCR B
HLT
(b) MVI A, 00H (d) None
LOOP ADD C
DCR B
JNZ LOOP
HLT
115. In an 8085 system, a PUSH operation requires more clock cycle than a POP
operation. Which one of the following options is the correct reason for this
(a) Memory write operations are slower than memory read operations in 8085 based
system
(b) The stack pointer needs to be pre decremented before writing registers in a PUSH,
whereas a POP operation uses the address already in stack pointer
(c) Both
(d) None
116. Which assembler are used to convert 8086 assembly language program into
machine language program
MICROPROCESSOR (KCS 403)
(a) MASM (b) TASM (c) DOS (d) All
117. Meaning of inter-segment jump in 8086 is
(a) Operation of jumping from one code segment to another
(b) Operation of jumping within same code segment
(c) Both
(d) None
118. Meaning of intra-segment jump in 8086 is
(a) Operation of jumping from one code segment to another
(b) Operation of jumping within same code segment
(c) Both
(d) None
119. Write an instruction set to initialize DS with the value 3000H
(a) MOV DS, AX (C) both
MOV AX, 3000H
(b) MOV AX,3000H (d) none
MOV DS, AX
120. What is full form of MASM
(a) Macro assembler (b) Micro assembler (c) both (d) none
121. The block of 8237 that decodes the various commands given to the 8237 by the
CPU is
a) Timing and control block
b) Program command control block
c) Priority block
d) None of the mentioned
122. The priority between the DMA channels requesting the services can be resolved by
a) Timing and control block
b) Program command control block
c) Priority block
d) None of the mentioned
123. The register that holds the current memory address is
a) Current word registers
b) Current address registers
c) Base address register
d) Command register
124. The register that holds the data byte transfers to be carried out is
a) Current word register
b) Current address register
c) Base address register
d) Command register
125. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated
126. The current address register is programmed by the CPU as
a) Bit-wise
MICROPROCESSOR (KCS 403)
b) Byte-wise
c) Bit-wise and byte-wise
d) None of the mentioned
127. Which of these register’s contents is used for auto-initialization (internally)?
a) Current word register
b) Current address register
c) Base address register
d) Command register
128. The register that maintains an original copy of the respective initial current address register
and current word register is
a) mode register
b) Base address register
c) Command register
d) Mask register
129. The register that can be automatically incremented or decremented, after each DMA
transfer is
a) Mask register
b) Mode register
c) Command register
d) Current address register
130. Which of the following is a type of DMA transfer?
a) memory read
b) memory write
c) verify transfer
d) all of the mentioned
131. Programmable peripheral input-output port is another name for
a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port
132. Port C of 8255 can function independently as
a) input port
b) output port
c) either input or output ports
d) both input and output ports
133. All the functions of the ports of 8255 are achieved by programming the bits of an internal
register called
a) data bus control
b) read logic control
c) control word register
d) none of the mentioned
134. The data bus buffer is controlled by
a) control word register
b) read/write control logic
c) data bus
MICROPROCESSOR (KCS 403)
d) none of the mentioned
135. The input provided by the microprocessor to the read/write control logic is
a) RESET
b) A1
c) WR (ACTIVE LOW)
d) All of the mentioned
136. How many pins does the 8255 PPI IC contains?
a) 24
b) 20
c) 32
d) 40
137. In which mode do all the Ports of the 8255 PPI work as Input-Output units for data transfer?
a) BSR mode
b) Mode 0 of I/O mode
c) Mode 1 of I/O mode
d) Mode 2 of I/O mode
138. Which of the following pins are responsible for handling the on the Read Write control
Logic unit of the 8255 PPI?
a) CS'
b) RD'
c) WR'
d) ALL of the above
139. In which of the following modes is the 8255 PPI capable of transferring data while
handshaking with the interfaced device?
a) BSR mode
b) Mode 0 of I/O mode
c) Mode 1 of I/O mode
d) Mode 2 of I/O mode
140. How many bits of data can be transferred between the 8255 PPI and the interfaced device at
a time? or What is the size of internal bus of the 8255 PPI?
a) 16 bits
b) 12 bits
c) 8 bits
d) None of the above
141. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7
142. The register that stores all the interrupt requests in it in order to serve them one by one on a
priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
MICROPROCESSOR (KCS 403)
d) Interrupt Mask Register
143. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
144. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
145. In a cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
146. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
147. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
148. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) Mode 1
c) Mode 2
d) Mode 3
149. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low
for
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
150. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Answers
1. D
MICROPROCESSOR (KCS 403)
2. A
3. C
4. D
5. C
6. D
7. A
8. B
9. C
10. A
11. A
12. C
13. A
14. C
15. B
16. A
17. C
18. A
19. B
20. A
21. C
22. B
23. C
24. C
25. B
26. C
27. D
28. C
29. B
30. A
31. B
32. A
33. B
34. A
35. A
36. C
37. A
38. C
39. A
40. A
41. D
42. A
43. A
44. C
45. A
46. B
MICROPROCESSOR (KCS 403)
47. B
48. D
49. B
50. A
51. B
52. C
53. C
54. D
55. A
56. A
57. C
58. B
59. A
60. A
61. A
62. D
63. A
64. A
65. D
66. C
67. C
68. C
69. C
70. C
71. B
72. B
73. D
74. B
75. C
76. A
77. D
78. A
79. A
80. D
81. C
82. C
83. B
84. A
85. A
86. D
87. A
88. B
89. B
90. B
91. D
92. C
MICROPROCESSOR (KCS 403)
93. D
94. C
95. A
96. C
97. C
98. C
99. B
100. C
101. B
102. C
103. C
104. B
105. A
106. C
107. C
108. C
109. B
110. D
111. D
112. A
113. A
114. B
115. B
116. D
117. A
118. B
119. B
120. A
121. B
122. C
123. B
124. A
125. C
126. B
127. C
128. B
129. D
130. D
131. B
132. C
133. C
134. B
135. D
136. D
137. B
138. D
MICROPROCESSOR (KCS 403)
139. C
140. C
141. C
142. A
143. C
144. D
145. D
146. C
147. B
148. A
149. A
150. C
Microprocessor Unit 1
1. When referring to instruction words, a mnemonic is:
a) A short abbreviation for the operand address
b) A short abbreviation for the operation to be performed
c) A short abbreviation for the data word stored at the operand address
d) A short abbreviation for the machine language
2. Identify the register that holds the instruction that is currently being executed or decoded
a) Instruction Register
b) Program Counter
c) MAR
d) MDR
3.……is a binary pattern that instructs a microprocessor to perform a specific task
a) Microprocessor
b) Instruction
c) Computer
d) Addressing mode
4. Find a group of circuits that performs all the computations in the computer
a) Arithmetic Logic Unit
b) Control Unit
c) Memory
d) I/O Unit
5. When reset key is pressed:
a) Processor transfers the control to a specific memory location mentioned in vector table
b) Processor executes the ISR
c) The internal operations are suspended and the program counter is cleared.
d) Microprocessor waits for the data from slow devices
6. Mnemonic based language is called….
a) Machine language
b) Assembly language
c) Binary language
d) High level language
7. Select the program that converts mnemonic based language into microprocessor language
a) Compiler
b) Interpreter
c) Assembler
d) translator
8. Analyze and match the following.
A. Microprocessor initiated operations
B. Externally or peripheral initiated operations
C. Microprocessor internal operations
1. Memory Read and Memory Write, Input Read and output Write
2. Determining how and what operations can be performed with the data
3. Reset, Ready, Interrupt and Hold
a) A-1 B-3 C-2
b) A-1 B-2 C-3
c) A-2 B-3 C-1
9-----defines the number of steps by the microprocessor to complete to complete an instruction
a) Cycle
b) Instruction cycle
c) Machine cycle
d) T-state
10.Define T-state by selecting best description related to term t-state:
A. It is equivalent to a clock period
B. It is equivalent to a clock
C. It represents the subdivision of the operation performed in a clock cycle.
D. It represents the whole process
a) A and B
b) A and C
c) B and C
d) A and D
11.VLSI stands for
a) Very Large Scale Integration
b) Virtual Large Scale Integration
c) Very Low Scale Integration
d) Volatile Large Scale Integration
12. When the data itself present in the instruction then the addressing mode is referred to as
a) Direct Addressing Mode
b) Indirect Addressing Mode
c) Register Addressing Mode
d) Immediate Addressing Mode
13. A Direct memory access transfer represents
a) Direct transfer of data between memory and accumulator
b) Direct transfer of data between memory and I/O devices without use of microprocessor
c) Transfer of data exclusively with in the microprocessor registers
d) A fast data transfer between microprocessor and I/O devices
14. Differentiate between D-flip flop and D-latch by selecting the statement given below:
a) D-FF is edge triggered and D-latch is level triggered
b) D-FF is level triggered and D-latch is edge triggered
15. The addressing mode which uses the PC instead of a general purpose register is ______
a) Indexed with offset
b) Relative
c) Direct
d) Both Indexed with offset and direct
16. In the following data transfer technique, the CPU enters in a loop until the I/O device indicates that it is
ready to transfer the data
a) Programmed I/O
b) Interrupt Driven I/O technique
c) DMA technique
d) All of the mentioned techniques
17. The system that has multiple processors in the same computer sharing the bus, memory, and I/O is called
a) Multiprocessor system
b) Multi core system
c) Microprocessor system
d) Single processor system
18. Select the 16 bit microprocessor from the given list:
a) 8080
b) 8085
c) 8086
d) 80386
19. Define the purpose of the interfacing devices by selecting the best statement matching with your definition.
a) Interfacing devices are the semiconductor chips that are needed to connect peripheral to the bus
b) Interfacing devices are necessary to interconnect the components of a bus oriented system
c) Encoders and decoders can be used as the interfacing devices
d) All of the mentioned
20. Which addressing modes are used in pointers and arrays?
a) Immediate , indirect
b) Direct, indexed
c) Indirect, indexed
d) Indexed, register indirect
21. Which architecture is followed by microprocessor?
a) von neumann architecture
b) harvard architecture
22. Which architecture is followed by microcontroller
a) von neumann architecture
b) harvard architecture
23. A nibble corresponds to
a) 2 bits
b) 4 bits
c) 8 bits
d) 16 bits
24. What is not true about microprocessor?
a) Microprocessor is a controlling unit of a micro-computer
b) It is fabricated on a small chip capable of performing ALU (Arithmetic Logical Unit) operations
c) It also communicates with the other devices connected to it.
d) It stores the data permanently
25. Which mode of Data Transfer Schemes (DTS) has the highest efficiency?
a) Cycle stealing mode
b) Burst mode
c) None
d) Both
26. Handshaking programmed data transfer is also known as
a) Asynchronous transfer
b) Synchronous transfer
c) Interrupt driver transfer
d) Both (a) and (c)
27. A machine language instruction format consists of -
a) Operation code field
b) Operation code field & operand field
c) Operand field
d) None of the mentioned
28. For memory mapped I/O, which of the following is true?
a) Devices are accessed using IN and OUT instructions
b) Devices have 8-bit address line
c) There can be max of 256 input devices and 256 output devices
d) Arithmetic and logic operations can be directly performed with the I/O data
29. It determines the number of operations per second?
a) Bandwidth
b) Word Length
c) Clock Speed
d) Operations Speed
30. Clock Speed is also known as?
A. Clock Rate.
B. Clock Length.
C. Clock Set.
D. Clock Type.
31. The __________ controls the flow of data and instructions within the computer.
a) Control Unit
b) Register Array
c) Accumulator
d) Alu
32. Which of the following is not a feature of a Microprocessor?
a) Versatility
b) Reliability
c) Low Bandwidth
d) Low Power Consumption
34.The addressing mode shown in the given figure is
a) Immediate addressing mode
b) Direct addressing mode
c) Register indirect addressing mode
d) Register addressing mode
35. FPGA:
a) Forward Programmable Gate Array
b) Forward Parallel Gate Array
c) Field Programmable Gate Array
d) Field Parallel Gate Array
36. If a microprocessor uses 10 MHz oscillator then duration of one T state is
a) 1 microsecond
b) 5 Milliseconds
c) 0.1 microseconds
d) 2 milliseconds
37. DSP stands for?
a) Digital Signal Processor
b) Digital Signal Preprocessor
c) Digital Signal Program
d) Data Signal Processor
38. A microprocessor can be classified into?
A. 2
B. 3
C. 4
D. 5
Explanation: A microprocessor can be classified into three categories: RISC, CISC and special processors
39. Output of the assembler in machine codes is referred to as -
a) Source program
b) Macroinstruction
c) Object program
d) Symbolic addressing
40. A machine language instruction format consists of -
a) Operation code field
b) Operation code field & operand field
c) Operand field
d) none of the mentioned
41.The software used to drive microprocessor-based systems is called-
a) firmware
b) machine language code
c) BASIC interpreter instructions
d) assembly language
42. The first digital computer build with IC chips was known as -
a) Apple -1
b) IBM 7090
c) IBM system / 360
d) VAX - 10
43. Which of the following are advantage of Loosely Coupled Configuration?
A. Having more than one processor results in increased efficiency.
B. easy to achieve parallel processing.
C. system structure is flexible
D. All of the above
44. The _________ handles all the communication between the processor and the memory
A. numeric extension unit
B. Packed Unit
C. control unit
D. Binary Unit
Explanation: The control unit handles all the communication between the processor and the memory
45. How many types of Interfacing?
A. 2
B. 3
C. 4
D. 5
Explanation: Interface is the path for communication between two components. Interfacing is of two types,
memory interfacing and I/O interfacing.
46.In which type of communication, the interface gets a single byte of data from the microprocessor and sends it
bit by bit to the other system serially and vice-a-versa?
A. Parallel Communication Interface
B. Serial Communication Interface
C. Both A and B
D. None of the above
Explanation: Serial Communication Interface : In this type of communication, the interface gets a single byte of
data from the microprocessor and sends it bit by bit to the other system serially and vice-a-versa.
47. What is true about microcontroller?
A. A microcontroller is a small and low-cost microcomputer
B. It is designed to perform the specific tasks of embedded systems
C. microcontroller consists of the processor, the memory, Serial ports, peripherals.
. All of the above
48. Which is false about microcontroller?
A. Microcontrollers are used to execute a single task within an application.
B. It consists of CPU, RAM, ROM, I/O ports.
C. Its power consumption is high because it has to control the entire system.
D. It is built with CMOS technology
Explanation: It is built with CMOS technology, which requires less power to operate.
49. This type of microcontroller is generally used in automatically controlled appliances like automatic
operational machines.
A. 8-bit microcontroller
B. 16-bit microcontroller
C. 32-bit microcontroller
D. 64-bit microcontroller
Explanation: 32-bit microcontroller : This type of microcontroller is generally used in automatically controlled
appliances like automatic operational machines.
50. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
51.The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one of the
following?
A. Clock cycle
B. Memory cycle
C. Machine cycle
D. Instruction cycle
52. The RISC architecture is preferred to CISC because RISC architecture has
A. simplicity
B. efficiency
C. high speed
D. all of the mentioned
53. The disadvantage of CISC design processors is
A. low burden on compiler developers
B. wide availability of existing software
C. complex in nature
D. none of the above
54. The feature of RISC that is not present in CISC is
A. branch prediction
B. pipelining
C. branch prediction and pipelining
D. none of the above
55. The feature of hybrid CISC-RISC architecture is
A. consume a lot of power
B. not applicable for mobile applications
C. processed by RISC core
D. all of the mentioned
56. Which of the following is an application of RISC architecture by adding more instructions?
A. multimedia applications
B. telecommunication encoding
C. image conversion
D. all of the mentioned
57. Which of the following processor belongs to hybrid RISC-CISC architecture?
A. Intel Pentium III
B. Intel Itanium 64
C. AMD’s X86-64
D. all of the mentioned
58. In order to implement complex instructions, CISC architectures use
A. macroprogramming
B. hardwire
C. microprogramming
D. none of the above
59. The advantage of RISC processors is
A. can operate at high clock frequency
B. shorter design cycle
C. simple and fast
D. all of the mentioned
60. The additional functionality that can be placed on the same chip of RISC is
A. memory management units
B. floating point units
C. memory management and floating point arithmetic units
D. RAM, ROM
61. The technique of assigning a memory address to each I/O device in the computer system is called:
A. memory-mapped I/O
B. ported I/O
C. dedicated I/O
D. wired I/O
62. What type of circuit is used at the interface point of an output port?
A. decoder
B. latch
C. tristate buffer
D. none of the above
63. I/O mapped systems identify their input/output devices by giving them a(n) ________.
A. 8-bit port number
B. 16-bit port number
C. 8-bit buffer number
D. 8-bit instruction
64. What type of circuit is used at the interface point of an input port?
A. decoder
B. latch
C. tristate buffer
D. none of the above
65. Because microprocessor CPUs do not understand mnemonics as they are, they have to be converted to
________.
A. hexadecimal machine code
B. binary machine code
C. assembly language
D. all of the above
66. What is the difference between a mnemonic code and machine code?
A. There is no difference.
B. Machine codes are in binary, mnemonic codes are in shorthand English.
C. Machine codes are in shorthand English, mnemonic codes are in binary.
D. None of the above
67. What kind of computer program is used to convert mnemonic code to machine code?
A. debug
B. assembler
C. Interpreter
D. Compiler
68. Which one of the following is not a vectored interrupt?
A. TRAP
B. INTR
C. RST 7.5
D. RST 3
69. Designing logic circuits and writing instructions to enable the microprocessor to communicate with
peripheral is called _________.
A. interfacing
B. monitoring
C. polling
D. pulling
70. ______ means at the same time, the transmitter and receiver are synchronized with the same clock.
A. asynchronous
B. serial data
C. synchronous
D. parallel data
71. Synchronization bit at the beginning of character is called ________.
A. stop bit
B. simplex
C. half duplex
D. start bit
72. Customized ROMS are called
A. Masked ROM
B. Flash ROM
C. EPROM
D. None of these
73. Each memory location has
A. Address
B. Contents
C. Both a and b
D. None of these
74. Most important advantage of an IC is its
A. Easy replacement in case of circuit failure
B. Extremely high reliability
C. Reduced cost
D. Low powers consumption
75. A 32 bit microprocessor has the word length equal to
A. 2 byte
B. 32 byte
C. 4 byte
D. 8 byte
76. The 16 bit register is separated into groups of 4 bit where each groups is called:
A. BCD
B. Nibble
C. Half byte
D. None of these
77. A nibble can be represented in the from of:
A. Octal digit
B. Decimal
C. Hexadecimal
D. None of these
78. The output data lines of microprocessor and memories are usually tristated because
a) More than one device can transmit information over the data bus by enabling only one device at
a time
b) More than one device can transmit over the data bus at the same time
c) The data line can be multiplexed for both input and output
d) It increases the speed of data transfer over the data bus
79. The first microprocessor to include virtual memory in the intel microprocessor family is
a) 80286
b) 80386
c) 80486
d) Pentium
Explanation: 80286 is a 16 bit microprocessor consisting of virtual memory.
Microprocessor Unit 2
1. A stack pointer stores the ____.
a) Address of bottom of stack
b) Address of instruction being executed
c) Address of instruction to be executed
d) Address of top of stack
2. The Program Counter (PC) in a microprocessor is used to
a) specify the address of the instruction to be executed
b) specify the address of the instruction currently executing
c) specify the number of instructions executed
d) none of these
3. If the source and destination addresses are made implicit the length of instruction is reduced.
a) True
b) False
4. What type of instructions can potentially change the sequence of operations in a program?
a) Logical instructions
b) Data transfer instructions
c) Branch instructions
d) Arithmetic instructions
5. The instructions which after execution transfer control to the next instruction in the sequence are called
a) Sequential control flow instructions
b) control transfer instructions
c) Sequential control flow & control transfer instructions
d) none of the mentioned
Explanation: The sequential control flow instructions follow sequence order in their execution.
6. The instructions that transfer the control to some predefined address or the address specified in the instruction
are called as
a) sequential control flow instructions
b) control transfer instructions
c) sequential control flow & control transfer instructions
d) none of the mentioned
7. The instruction “JUMP” belongs to
a) sequential control flow instructions
b) control transfer instructions
c) branch instructions
d) control transfer & branch instructions
8. 8085 microprocessor is an 8-bit microprocessor designed by?
A. IBM
B. Dell
C. Intel
D. VAX
9. In 8085, 16-bit address bus, which can address upto?
A. 16KB
B. 32KB
C. 64KB
D. 128KB
10.There are _______ general purpose registers in 8085 processor
A. 5
B. 6
C. 7
D. 8
Explanation: There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register can
hold 8-bit data.
11. It is also a 16-bit register works like stack, which is always incremented /decremented by 2 during push &
pop operations.
A. Stack pointer
B. Temporary register
C. Flag register
D. Program counter
12. Flag register is an 8-bit register having __________ 1-bit flip-flops.
A. 3
B. 4
C. 5
D. 6
Explanation: These are the set of 5 flip-flops : Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P) and Carry
(C)
13. What is true about Program counter in 8085 microprocessor?
A. It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.
B. When an instruction is fetched from memory then it is stored in the program counter
C. It provides timing and control signal to the microprocessor
D. It is a 16-bit register used to store the memory address location of the next instruction to be
executed.
14. This signal indicates that another master is requesting the use of the address and data buses.
A. READY
B. HOLD
C. HLDA
D. INTA
Explanation: HOLD : This signal indicates that another master is requesting the use of the address and data
buses.
15. This signal is used as the system clock for devices connected with the microprocessor.
A. X1, X2
B. CLK OUT
C. CLK IN
D. IO/M
Explanation: CLK OUT : This signal is used as the system clock for devices connected with the microprocessor.
16. Which of the following is true about Control and status signals?
A. These signals are used to identify the nature of operation.
B. There are 3 control signal and 3 status signals.
C. Three status signals are IO/M, S0 & S1.
D. All of the above
17. MVI D, 01H is an example of?
A. Immediate addressing mode
B. Register addressing mode
C. Direct addressing mode
D. Indirect addressing mode
18. Consider the following mnemonics. Which of the following belong to data transfer group
1. LHLD
2. PCHL
3. ADI
4. ANA
a) 1 and 2 only
b) 1 and 3 only
c) 1, 2 and 3 only
d) 1, 2, 3 and 4
19. The program counter in 8085 microprocessor is a 16- bit register because
a) It counts 16 bits at a time
b) There are 16 address lines
c) It facilitates the user storing 16 bit data temporarily
d) It has to fetch two 8-bit data at a time
20. What will be the value in the memory location 1001H after the execution of the following code? The data at
memory location 1000 is 40H.
LXI H, 1000H
MOV A, M
CMA
ADI 06H
STA 1001H
HLT
a) 59H
b) C5H
c) 5AH
d) 5CH
21. Which instruction must be included at the end of each and every subroutine?
a) Return
b) RET
c) CALL
d) EI
22. Which of the statements is correct for “CMP M”?
a) Compares the content of accumulator with register M
b) Compares the content of accumulator with the content of a memory location, the address of that
memory location is in HL register pair
c) Compares the content of accumulator with the content of a memory location, the address of that
memory location is in DE register pair
d) Compares the content of accumulator with register A
23. XCHG instruction of 8085 exchanges the content of
a) Top of the stack with the contents of register pair
b) BC and DE register pair
c) HL and DE register pair
d) Accumulator and DE register pair
24. Which flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0?
A. Binary bit
B. Zero flag
C. Sign flag
D. Overflow flag
25. Which flag represents the result when the system capacity is exceeded?
A. Carry flag
B. Auxiliary flag
C. Trap flag
D. Overflow flag
26. It is an edge triggered input, which causes an interrupt request to the microprocessor.
A. NMI
B. INTR
C. INTA
D. ALE
Explanation: The non-maskable interrupt (NMI) is an edge-triggered input that requests an interrupt on the
positive edge (0-to-1 transition). The NMI input is often used for parity errors and other major faults, such as
power failures.
27. It is used to write the data into the memory or the output device depending on the status of M/IO signal.
A. IR
B. HLDA
C. HR
D. WR’
28. Assertion (A): Microprocessor 8085 has an on-chip oscillator with an inbuilt crystal.
Reason (R): For frequency stability crystal oscillator is preferred.
a) Both A and R are correct and R is the correct explanation of A
b) Both A and R are correct but R is not the correct explanation of A
c) A is correct R is wrong
d) A is wrong R is correct
An oscillator is a circuit which produces a continuous, repeated, alternating waveform without any input.
Oscillators basically convert unidirectional current flow from a DC source into an alternating waveform which
is of the desired frequency, as decided by its circuit components
29. RIM is used to check whether, _____
a) The interrupt is Masked or not
b) The write operation is done or not
c) both 1 & 2
d) None of these
30. It is a power supply signal, which requires +5V supply for the operation of the circuit.
A. VCA
B. VDD
C. VCC
D. INTA
31. ALU (Arithmetic and Logic Unit ) of 8085 microprocessor consists of-
a) Accumulator, arithmetic, logic circuits and five flags
b) Accumulator, arithmetic and logic circuits
c) Accumulator, temporary register, arithmetic, logic circuits and five flags
d) Accumulator, temporary register, arithmetic and logic circuits
32. Which of the following are known as Higher Address Bus?
A. A15 - A8
B. AD7 - AD0
C. READY
D. WR
33. Operation code field is present in :
a) programming language instruction
b) assembly language instruction
c) machine language instruction
d) none of the mentioned
34. In PUSH instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
35.The instruction that pushes the contents of the specified register/memory location on to the stack is
a) PUSHF
b) POPF
c) PUSH
d) POP
36. In POP instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
37. The instructions that are used for reading an input port and writing an output port respectively are
a) MOV, XCHG
b) MOV, IN
c) IN, MOV
d) IN, OUT
38. The instruction that supports addition when carry exists is
a) ADD
b) ADC
c) ADD & ADC
d) None of the mentioned
Explanation: ADC (Add with Carry) instruction performs the same operation as ADD operation, but adds the
carry flag bit to the result.
39. In an intel 8085A microprocessor, why is READY signal used?
A. To indicate to user that the microprocessor is working and is ready for use.
B. To provide proper WAIT states when the microprocessor is communicating with a slow
peripheral device.
C. To slow down a fast peripheral device so as to communicate at the microprocessor‟s device.
D. None of the above
40. Consider the following statements:
In 8085 microprocessor, data-bus and address bus are multiplexed in order to
I) Increase the speed of microprocessor.
II) Reduce the number of pins.
III) Connect more peripheral chips.
Which of these statements is/are correct?
A. (I) only
B. (II) only
C. (II) & (III)
D. (I), (II) & (III)
41.In intel 8085A microprocessor ALE signal is made high to
A. Enable the data bus to be used as low order address bus
B. To latch data D0-D7 from data bus
C. To disable data bus
D. To achieve all the functions listed above
42. The flags are affected in which category of instructions in 8085 microprocessor
A. Data Transfer group
B. Arithmetic Group and logical group
C. Branch group
D. Machine control group
43. In 8085 microprocessor, the RST6 instruction transfer programme execution to following location
a) 0030H.
b) 0024H.
c) 0048H.
d) 0060H.
44. The number of output pins in 8085 microprocessors are
a) 27.
b) 40.
c) 21.
d) 19.
45. Which components are NOT found on chip in a microprocessor but may be found on chip in a
microcontroller?
a) SRAM & USART
b) EPROM & PORTS
c) EPROM, USART & PORTS
d) SRAM, EPROM & PORTS
46. The clock speed of 8085 is
a) 1MHz.
b) 1KHz.
c) 3.2KHz.
d) 3.2MHz.
8085 requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.
47. There is a „cross-over frequency‟ below which the period mode is preferred. Assuming the crystal
oscillator frequency to be 4MHz, the crossover frequency is given by
a) 8 Mhz.
b) 2 Mhz.
c) 2 Khz.
d) 1Khz.
Explanation: As we know crossover frequency is the half of oscillator frequency.
48. Consider the following statements: Arithmetic Logic Unit (ALU)
1.Performs arithmetic operations
2.Performs comparisons.
3. Communicates with I/O devices
4.Keeps watch on the system Which of these statements are correct?
a) 1, 2, 3 and 4
b) 1, 2 and 3
c) 1 and 2 only
d) 3 and 4 only
49. Ready pin of microprocessor is used
a) to indicate that microprocessor is ready to receive inputs
b) to indicate that microprocessor is ready to receive outputs
c) to introduce wait state
d) to provide direct memory access
50. Consider the following registers:
1. Accumulator and flag register
2. B and C register
3. D and E register
4. H and L register
Which of these 8-bit registers of 8085 microprocessor can be paired together to make a 16-bit register?
a) 1, 3 and 4
b) 2, 3 and 4
c) 1, 2 and 3
d) 1, 2 and 4
51. HLDA signal in 8085 performs the following operation:
a) Indicates that another master is requesting the use of the address and data buses.
b) Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the
next clock cycle.
c) Indicates that the CPU has not received the HOLD request.
d) Hold the data in the accumulator until the microprocessor is turned OFF.
HLDA or Hold Acknowledge indicates that the CPU has received the HOLD request and that it will relinquish
the bus in the next clock cycle.
HLDA goes low after the Hold request is removed. The CPU takes the bus one half-clock cycle after HLDA
goes low.
52. The characteristics of RESET OUT signal is/are
a) indicates that µp is being reset.
b) This signal can be used to reset other devices.
c) The signal is synchronized to the processor clock.
d) All of the mentioned
RESET OUT signal indicates that microprocessor is being reset. This signal can be used to reset other devices.
The signal is synchronized to the processor clock and lasts an integral number of clock periods.
53. RST0 - RST7 are the __________ in 8085.
a) hardware interrupts
b) logical interrupts
c) software interrupts
d) conditional interrupts
Software Interrupts are those which are inserted in between the program which means these are mnemonics of
microprocessor. There are 8 software interrupts in 8085 microprocessor. They are – RST 0, RST 1, RST 2, RST
3, RST 4, RST 5, RST 6, RST 7.
54. Assertion(A): Ready signal of microprocessor is used to detect whether a peripheral is ready for the data
transfer or not.
Reason(R): In the microprocessor during data transfer operations, the wait states are added by forcing the ready
signal low.
a) Both A & R are true and R is the correct explanation of A.
b) Both A & R are true but R is not the correct explanation of A .
c) A is true but R is false.
d) A is false but R is true.
Both are correct and (R) is the correct explanation of (A)
Microprocessor Unit 3
1. 8086 Microprocessor supports _______ modes of operation.
A. Minimum
B. Maximum
C. Both the mentioned
D. None of the mentioned
2. The work of EU
Encoding
Decoding
Calculation
Processing
3. In 8086 microprocessor, the address bus is bit wide
A. 12 bit
B. 10 bit
C. 16 bit
D. 20 bit
4. Which of the following is not a feature of 8086?
A. It uses two stages of pipelining
B. It is available in 3 versions based on the frequency of operation
C. Fetch stage can pre-fetch up to 6 bytes of instructions
D. It has 512 vectored interrupts.
Explanation: It has 256 vectored interrupts is true features of 8086.
5. If MN/MX’ is low the 8086 operates in mode
A. Minimum
B. Maximum
C. both (A) and (B)
D. medium
6. 8086 can access up to?
A. 512KB
B. 1MB
C. 2Mb
D. 256KB
7. 8086 has ___ address bus.
A. 16-bit
B. 18-bit
C. 20-bit
D. 24-bit
8. Which instruction is used to load the address of operand into the provided register?
A. LEA
B. LDS
C. LES
D. LAHF
Explanation: LEA : Used to load the address of operand into the provided register.
9. LDS copies to consecutive words from memory to register and
A. ES
B. DS
C. SS
D. CS
10. The different ways in which a source operand is denoted/specified in an instruction is known as
A. Instruction Set
B. Interrupts
C. 8086 Configuration
D. Addressing Modes
11. How many types of basic multiprocessor configurations?
A. 2
B. 3
C. 4
D. 5
Explanation: Multiprocessor means a multiple set of processors that executes instructions simultaneously. There
are three basic multiprocessor configurations: Coprocessor configuration, closely coupled configuration and
loosely coupled configuration.
12. _____________ is a specially designed circuit on microprocessor chip which can perform the same task
very quickly, which the microprocessor performs
A. Coprocessor configuration
B. Closely coupled configuration
C. Loosely coupled configuration
D. None of the above
Explanation: A Coprocessor is a specially designed circuit on microprocessor chip which can perform the same
task very quickly, which the microprocessor performs.
13. The coprocessor and the processor are connected via?
A. TEST
B. QS0
C. QS1
D. All of the above
Explanation: The coprocessor and the processor is connected via TEST, RQ-/GT- and QS0 & QS1 signals.
14. In which year, 8086 microprocessor was introduced?
a) 1978
b) 1979
c) 1977
d) 1981
15. _________signal takes care of the coprocessor's activity, i.e. the coprocessor is busy or idle.
A. TEST
B. QS0
C. QS1
D. None of the above
Explanation: TEST signal takes care of the coprocessor's activity, i.e. the coprocessor is busy or idle.
16. Which of following load the stack pointer
bgt
LDS
bhs
RTS
17. 8087 numeric data processor is also known as?
A. Math co-processor
B. Numeric processor extension
C. Floating point unit
D. All of the above
Explanation: 8087 numeric data processor is also known as Math co-processor, Numeric processor extension
and Floating point unit.
18. 8087 Numeric Data Processor designed by?
A. Intel
B. IBM
C. Microsoft
D. VAX
Explanation: It was the first math coprocessor designed by Intel to pair with 8086/8088 resulting in easier and
faster calculation.
19. The R/M field in a machine instruction format specifies
a) another register
b) another memory location
c) other operands
d) all of the mentioned
20. In a machine instruction format, S-bit is the
a) status bit
b) sign bit
c) sign extension bit
d) none of the mentioned
Explanation: The S-bit known as sign extension bit is used along with W-bit to show the type of operation.
21. The instruction, MOV AX, 0005H belongs to the address mode
a) register
b) direct
c) immediate
d) register relative
Explanation: In Immediate addressing mode, immediate data is a part of instruction and appears in the form of
successive byte or bytes.
22. The instruction, MOV AX, [2500H] is an example of
a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
Explanation: Since the address is directly specified in the instruction as a part of it.
23. The instruction, MOV AX, [BX] is an example of
a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
24. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned
Explanation: In the indexed addressing mode, the offset of an operand is stored and in the rest of them, address
is stored.
25. The addressing mode that is used in unconditional branch instructions is
a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
Explanation: In intrasegment indirect mode, the branch address is found as the content of a register or a memory
location.
26. Which of the following is not a data copy/transfer instruction?
a) MOV
b) PUSH
c) DAS
d) POP
Explanation: DAS (Decimal Adjust after Subtraction) is an arithmetic instruction.
27. The instructions that involve various string manipulation operations are
a) branch instructions
b) flag manipulation instructions
c) shift and rotate instructions
d) string instructions
28. The instruction that is used for finding out the codes in case of code conversion problems is
a) XCHG
b) XLAT
c) XOR
d) JCXZ
Explanation: The translate (XLAT) instruction is used to find codes.
29. The instruction that loads the AH register with the lower byte of the flag register is
a) SAHF
b) AH
c) LAHF
d) PUSHF
Explanation: The instruction LAHF (Load AH from a lower byte of Flag) may be used to observe the status of
all the condition code flags(except overflow flag) at a time.
30. Which are the four categories of registers in 8086 microprocessor:
A. General‐ purpose register
B. Pointer or index registers
C. Segment registers
D. All of these
31. Pseudo instructions are basically
A. false instructions
B. instructions that are ignored by the microprocessor
C. assembler directives
D. instructions that are treated like comments
32. The length of bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate number of
wait state clock cycles denoted by Tw. The wait states are always inserted between
a) T1 & T2
b) T2 & T3
c) T3 & T4
d) T4 & T1
33. Bus Interface Unit (BIU) in 8086 performs the following functions:
a) Instruction decoding.
b) Instruction fetch.
c) Arithmatic and Logic operations.
d) All the above.
34. The control flags in 8086 are:
a) the Trap flag(TF).
b) the interrupt flag(IF).
c) the direction flag(DF).
d) All of the above.
35. The instruction, MOV AX, 1234H is an example of -
a) register addressing mode
b) immediate addressing mode
c) based indexed addressing mode
d) direct addressing mode
36. Address line for TRAP is?
A. 0023H
B. 0024H
C. 0033H
D. 0099H
37. In 8086 microprocessor one of the following statements is not true?
A. coprocessor is interfaced in max mode.
B. coprocessor is interfaced in min mode.
C. I /O can be interfaced in max / min mode.
D. supports pipelining
38. In 8086 the overflow flag is set when .
A. the sum is more than 16 bits.
B. signed numbers go out of their range after an arithmetic operation.
C. carry and sign flags are set.
D. subtraction
39. The instruction format ‘register to register’ has a length of
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
40. The R/M field in a machine instruction format specifies
a) another register
b) another memory location
c) other operands
d) all of the mentioned
41. The bit which is used by the ‘REP’ instruction is
a) W-bit
b) S-bit
c) V-bit
d) Z-bit
Explanation: The Z-bit is used by the REP instruction to control the loop.
42. If a W-bit value is ‘1’ then the operand is of
a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits
43. Which of the following instruction is not valid?
a) MOV AX, BX
b) MOV DS, 5000H
c) MOV AX, 5000H
d) PUSH AX
Explanation: Both the source and destination operands cannot be memory locations except for string
instructions.
44. The directive used to inform the assembler, the names of the logical segments to be assumed for different
segments used in the program is
a) ASSUME
b) SEGMENT
c) SHORT
d) DB
Explanation: In ALP, each segment is given a name by using the directive ASSUME
SYNTAX: ASSUME segment:segment_name
Eg: ASSUME CS:Code
Here CS is the Code segment and code is the name assumed to the segment.
45. Match the following
a) DB 1) used to direct the assembler to reserve only 10-bytes
b) DT 2) used to direct the assembler to reserve only 4 words
c) DW 3) used to direct the assembler to reserve byte or bytes
d) DQ 4) used to direct the assembler to reserve words
a) a-3, b-2, c-4, d-1
b) a-2, b-3, c-1, d-4
c) a-3, b-1, c-2, d-4
d) a-3, b-1, c-4, d-2
46. The directive that marks the end of a logical segment is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
47. The directive that updates the location counter to the next even address while executing a series of
instructions is
a) EVN
b) EVEN
c) EVNE
d) EQU
48. The directive that directs the assembler to start the memory allotment for a particular segment/block/code
from the declared address is
a) OFFSET
b) LABEL
c) ORG
d) GROUP
Explanation: If an ORG is written then the assembler initiates the location counter to keep the track of allotted
address for the module as mentioned in the directive.
If the directive is not present, then the location counter is initialized to 0000H.
49. The directive that marks the starting of the logical segment is
a) SEG
b) SEGMENT
c) SEG & SEGMENT
d) PROC
50. The labels or constants that can be used by any module in the program is possible when they are declared as
a) PUBLIC
b) LOCAL
c) GLOBAL
d) Either PUBLIC or GLOBAL
Explanation: The labels, constants, variables, procedures declared as GLOBAL can be used by any module in
the program.
51. The recurrence of the numerical values or constants in a program code is reduced by
a) ASSUME
b) LOCAL
c) LABEL
d) EQU
52. If an interrupt is generated from outside the processor then it is an
a) internal interrupt
b) external interrupt
c) interrupt
d) none of the mentioned
53. If the interrupt is generated by the execution of an interrupt instruction then it is
a) internal interrupt
b) external interrupt
c) interrupt-in-interrupt
d) none of the mentioned
54. Example of an external interrupt is
a) divide by zero interrupt
b) keyboard interrupt
c) overflow interrupt
d) type2 interrupt
55. Example of an internal interrupt is
a) divide by zero interrupt
b) overflow interrupt
c) interrupt due to INT
d) all of the mentioned
56. The interrupt request that is independent of IF flag is
a) NMI
b) TRAP
c) Divide by zero
d) All of the mentioned
57. During the execution of an interrupt, the data pushed into the stack is the content of
a) IP
b) CS
c) PSW
d) All of the mentioned
58. After every response to the single step interrupt the flag that is cleared is
a) IF (Interrupt Flag)
b) TF (Trap Flag)
c) OF (Overflow Flag)
d) None of the mentioned
59. At the end of ISR, the instruction should be
a) END
b) ENDS
c) IRET
d) INTR
60 When the CPU executes IRET,
a) contents of IP and CS are retrieved
b) the control transfers from ISR to main program
c) clears the trap flag
d) clears the interrupt flag
61. The interrupt for which the processor has the highest priority among all the external interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
62. The interrupt for which the processor has highest priority among all the internal interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
63. The NMI pin should remain high for atleast
a) 4 clock cycles
b) 3 clock cycles
c) 1 clock cycle
d) 2 clock cycles
Explanation: The NMI pin should remain high for atleast 2 clock cycles and need not be synchronized with the
clock for being sensed.
64. The INTR signal can be masked by resetting the
a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag
65. For the INTR signal, to be responded to in the next instruction cycle, it must go ________ in the last clock
cycle of the current instruction
a) high
b) low
c) high or low
d) unchanged
Explanation: The INTR signal must go high in the clock cycle of the current instruction in order to respond in
the next instruction cycle.
66. The status of the pending interrupts is checked at
a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle
67. Once the processor responds to an INTR signal, the IF is automatically
a) set
b) reset
c) high
d) low
Explanation: The IF is automatically reset when the processor responds to an INTR signal. If the processor
wants to respond to any type of INTR signal further then, the IF should again be set.
68. If the pin LOCK (active low based) is low at the trailing edge of the first ALE pulse, then till the start of the
next machine cycle, the pin LOCK (active low) is
a) low
b) high
c) low or high
d) none of the mentioned
Explanation: The pin LOCK (active low) remains low till the start of the next machine cycle.
69. With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in it for
a) 0 clock cycle
b) 1 clock cycle
c) 2 clock cycles
d) 3 clock cycles
70. The stack segment register contains
a) address of the stack segment
b) base address of the stack segment
c) pointer address of the stack segment
d) data in the stack segment
71. The stack pointer register contains
a) address of the stack segment
b) pointer address of the stack segment
c) offset of address of stack segment
d) data present in the stack segment
72. In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK
the ASSUME directive directs to the assembler the
a) address of the stack segment
b) pointer address of the stack segment
c) name of the stack segment
d) name of the stack, code and data segments
Explanation: The directive ASSUME facilitates to name the segments with the desired name that is not a
mnemonic or keyword.
73. When a stack segment is initialised then
a) SS and SP are initialised
b) only SS is initialised
c) only SP is initialised
d) SS and SP need not be initialised
74. 8086 does not support
a) Arithmetic operations
b) logical operations
c) BCD operations
d) Direct BCD packed multiplication
75. For 8086 microprocessor, the stack segment may have a memory block of a maximum of
a) 32K bytes
b) 64K bytes
c) 16K bytes
d) NONE
Microprocessor Unit 4
1. The instruction that is used to transfer the data from source operand to destination operand is
a) data transfer instruction
b) branch instruction
c) arithmetic/logical instruction
d) string instruction
2. Interrupts are recognized during execution of EI instruction
A. True
B. False
3. Interrupts are recognized during execution of DI instruction
A. True
B. False
4. Placing an EI instruction on the bus in response to INTA’ during an INA cycles is prohibited
A. True
B. False
5. How many T-states is taken by the HLT instruction in 8085 microprocessor
A. 3
B. 4
C. 5
D. 10
6. Which of the following instruction is used to provide delay?
A. HLT
B. RIM
C. NOP
D. EI
7. RIM stands for
A. Read Interrupt Mask
B. Reuse Interrupt Mask
C. Reset Interrupt Mask
D. Retain Interrupt Mask
8. What is the working of RIM instruction?
RIM loads the data (status) into the accumulator related to the interrupts and the serial input
Current interrupt mask for RST 5.5-RST7.5
Current interrupt enable flag status
Hardware interrupt pending (received but not yet serviced)
Serial input data
SIM (Set Interrupt Mask)
9. What is the working of the SIM INSTRUCTION?
The execution of the SIM instruction uses the content of the accumulator (which must be previously loaded)
Program the interrupt mask for RST 5.5-RST7.5
Reset the edge-triggered RST7.5 input latch
Load the SOD output latch
10. Which of the following is not true during the execution of an interrupt service routine, which does not
contain any EI instructions
a) the microprocessor can be interrupted by a non-mask able interrupt
b) the microprocessor cannot be interrupted by any interrupt
c) the microprocessor cannot be interrupted by any maskable interrupt
d) all interrupts except non-maskable interrupt are disabled
11. In which of the following addressing mode, the offset is obtained by adding displacement and contents of
one of the base registers?
a) direct mode
b) register mode
c) based mode
d) indexed mode
12. In which of the following addressing mode, the offset is obtained by adding displacement, with the contents
of SI?
a) direct mode
b) register mode
c) based mode
d) indexed mode
13. The address of a location of the operand is calculated by adding the contents of any of the base registers,
with the contents of any of index registers in
a) based indexed mode with displacement
b) based indexed mode
c) based mode
d) indexed mode
14. The representation of 8-bit or 16-bit signed binary operands using 2’s complement is a data type of
a) Ordinal
b) ASCII
c) Packed BCD
d) integer
15. Which of the following instruction is not possible in 8085?
POP PSW
POP B
POP D
POP 30 H
16. The instruction that pushes the general purpose registers, pointer and index registers on to the stack is
a) POPF
b) PUSH Imd
c) PUSH
d) PUSHF
17. The instruction that pushes all the flags to the word onto the stack is
a) POPF
b) PUSH Imd
c) PUSH
d) PUSHF
Note: During PUSH and PUSHF flags are not affected
18. While executing the PUSH instruction, the stack pointer is decremented by
a) 1
b) 2
c) 4
d) 16
19. While executing the POP instruction, the stack pointer is incremented by
a) 1
b) 2
c) 4
d) 16
20. Which of the following is not a data copy/transfer instruction?
a) MOV
b) PUSH
c) DAS
d) POP
Explanation: DAS (Decimal Adjust after Subtraction) is an arithmetic instruction.
21. The instruction that is used for finding out the codes in case of code conversion problems is
a) XCHG
b) XLAT
c) XOR
d) JCXZ
22. The instruction that loads effective address formed by destination operand into the specified source register
is
a) LEA
b) LDS
c) LES
d) LAHF
23. The instruction that loads the AH register with the lower byte of the flag register is
a) SAHF
b) AH
c) LAHF
d) PUSHF
24. The instruction that loads the flag register completely from the word contents of the memory location is
a) PUSH
b) POP
c) PUSHF
d) POPF
25. The instruction that supports addition when carry exists is
a) ADD
b) ADC
c) ADD & ADC
d) None of the mentioned
26. The instruction that enables subtraction with borrow is
a) DEC
b) SUB
c) SBB
d) None of the mentioned
27. The flag that acts as Borrow flag in the instruction, SBB is
a) direction flag
b) carry flag
c) parity flag
d) trap flag
28. In general, the source operand of an instruction can be
a) memory location
b) register
c) immediate data
d) all of the mentioned
29. In general, the destination operand of an instruction can be
a) memory location
b) register
c) immediate data
d) memory location and register
30. The instruction, CMP to compare source and destination operands it performs
a) addition
b) subtraction
c) division
d) multiplication
31. During comparison operation, the result of comparing or subtraction is stored in
a) memory
b) registers
c) stack
d) no where
32. CMP instruction affects the flags
A. Carry Flag
B. Zero Flag
C. Carry Flag and Zero Flag
D. All flags
33. How many T-states are required for execution of OUT 80H instruction?
a) 10
b) 13
c) 16
d) 7
OUT operation means Output data from Accumulator to a port with 8 bit address. The contents of the
accumulator are copied into the output port. It is a two byte operation with 3 machine cycles and 10 T states.
10T states 4 for Opcode fetch, 3 for Memory read and 3 for I/O write operation.
34. How many machine cycles are required for execution of IN 30H instruction
a) 3
b) 4
c) 5
d) 6
IN instruction means Input data to Accumulator from a port with 8-bit address.IN 30H is a 2 byte instruction
which requires 3 machine cycles i.e. Opcode fetch, read, read(operand read from the 8 bit port address).
35. While INX B instruction execute,
a) only carry flag will be affected
b) all flags will be affected
c) only carry and zero flags will be affected
d) no flags will be affected
The flags (flip flop) are affected by the arithmetical and logical operations in the ALU. Flags generally reflects
the data conditions in the accumulator with some exception. INX B is a instruction which increment the content
of the register pair BC by 1 and it does not affect any of the flags.
36. Which instruction is required to rotate the content of accumulator one bit right along with carry?
a) RLC
b) RAL
c) RRC
d) RAR
RAR instruction means rotate accumulator right through carry. By this instruction each bit of the accumulator is
rotated right by one position through the carry flag. The carry flag is set by the least significant digit and content
of the carry flag is placed in the most significant position. Example : accumulator contents before instruction is
10100111 and the flag is set by 0. After the instruction executes the accumulator content is 01010011 and the
flag is set by 1.
37. Which flag will be affected by the execution of RLC /RRC/ RAL/ CMC instruction?
a) only carry flag will be affected
b) all flags will be affected
c) only carry and zero flags will be affected
d) no flags will be affected
38. A good assembly language programmer should use general purpose registers rather than memory in
maximum possible ways for data processing. This is because:
a) Data processing with registers is easier than with memory
b) Data processing with memory requires more instructions in the program than that with registers
c) Of limited set of instructions for data processing with memory
d) Data processing with registers takes fewer cycles than that with memory
39. What are the sets of commands in a program which are not translated into machine instructions during
assembly process, called?
a) Mnemonics
b) Directives
c) Identifiers
d) Operands
40. How many bytes in a zero memory page should be reserved for vectors used by RST instructions?
a) 16.
b) 32.
c) 64.
d) 128.
First 64 bytes in a zero memory page should be reserved for vectors used by RST instructions.
41. CALL instruction is a ______ instruction.
a) 4 bytes
b) 2 bytes
c) 1 bytes
d) 3 bytes
42. XCHG instruction exchanges the content of H-L with ______ register pair.
a) B-C
b) PSW
c) D-E
d) Stack Pointer
43. ________used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by setting various bits to
form masks or generate output data via the Serial Output Data (SOD) line.
a) RIM
b) SIM
c) EI
d) DI
Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by
setting various bits to form masks or generate output data via the Serial Output Data (SOD) line. First the
required value is loaded in accumulator then SIM will take the bit pattern from it.
44. _____________is used to read the status of the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading
into the A register a byte which defines the condition of the mask bits for the interrupts.
a) SIM
b) RIM
c) DI
d) EI
Microprocessor Unit 5
Unit 5 questions
1. The block of 8237 that decodes the various commands given to the 8237 by the CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
2. The priority between the DMA channels requesting the services can be resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
3. The register that holds the current memory address is
a) current word register
b) current address register
c) base address register
d) command register
4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register
Explanation: The current word register is a 16-bit register that holds the data transfers. The word count is
decremented after each transfer, and the new value is stored again in the register.
5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated
6. Which of these register’s contents is used for auto-initialization (internally)?
a) current word register
b) current address register
c) base address register
d) command register
Explanation: The contents of base address register cannot be read by the CPU. These contents are used
internally for auto-initialization.
7. The register that can be automatically incremented or decremented, after each DMA transfer is
a) mask register
b) mode register
c) command register
d) current address register
8. Which of the following is a type of DMA transfer?
a) memory read
b) memory write
c) verify transfer
d) all of the mentioned
9. 8237 contains three basic blocks of its operational logic.
a. Timing block
b. Control block
c. Program command control block
d. All of d above
10. These maintain an original copy of respective initial current register and current word register before
incrementing or decrementing
a. Mode register
b. Base address and base word count registers
c. Only b
d. Both
11. Each of 4 DMA channels of 8237 has ___ bit current address register.
a. 16
b. 32
c. 64
d. 124
12. ____ register controls the complete operation of 8237
a. Code register
b. Count register
c. Command register
d. None of the above
13. Command register is ___ bit
a. 16
b. 32
c. 8
d. 64
14. Command register is programmed by ___ and cleared by __.
a. CPU, reset
b. ALU
c. BIU
d. None of the above
15. In mode register bits __ and __ determine which of the 4 channels mode register are to be written
a. 0 and 1
b. 2 and 3
c. 1 and 0
d. None of the above
16. Bits __ and ___indicate the type of DMA transfer
a. 0 and 1
b. 2 and 3
c. 1 and 0
d. None of the above
17. Bit ____ indicates whether address incremented or address decremented mode is selected
a. 0
b. 5
c. 3
d. 2
18. _____ register holds data during memory –memory data transfer
a. Temporary register
b. Command register
c. Mode register
d. None of the above
19. ____ register keeps the track of all DMA channel pending requests and the status of terminal counts
a. Temporary register
b. Command register
c. Mode register
d. Status register
20. ___ signal is required for deriving the internal timings requiredfpr circuit operations
a. GND
b. CLK
c. READY
d. RESET
21. High on this input line clears the command, status, request and temporary register
a. RESET
b. CLK
c. READY
d. none
22. This active- high input is used to match the read or write speed of 8237 with slow memories or i/o devices
a. READY
b. RESET
c. CLK
d. None
23. Signal used to indicate that cpu has relinquished the control of the bus, as a response to bus request
a. HLDA
b. READY
c. RESET
d. CLK
24. DREQo has ____ priority
a. Highest
b. Lowest
c. None of these
25. DREQ3 has ____ priority
a. Lowest
b. Highest
c. None
26. Data bus is ____ lines used to transfer data to /from I/O or memory
a. Unidirectional
b. Bidirectional
c. None
27. An output pin used to request the control of the system bus from cpu
a. HRQ
b. HOLD
c. HLDA
8259
28. In 8259, The register that stores all the interrupt requests in it in order to serve them one by one on a priority
basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
29. In 8259, The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
30. In 8259, When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used
as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
Explanation: When the pin is used in buffered mode, then it can be used as a buffer enable to control buffer
transreceivers. If it is not used in buffered mode, then the pin is used as input to designate whether the chip is
used as a master or a slave.
31. In 8259, Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
Explanation: The initialization procedure involves
i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.
32. In 8259, When non-specific EOI command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
Explanation: When non-specific EOI command is issued to 8259A it will automatically reset the highest ISR.
33. In 8259 application where all the interrupting devices are of equal priority, the mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
34. In automatic rotation , the device , after being serviced , receives the ________ priority
A Lowest
B Highest
C Intermediate
D Cannot predict
35. In SFNM which of the following statement is correct?
A When servicing an interrupt request from slave, the slave is not allowed to place any
further requests.
B When servicing an interrupt request from a slave , the slave the slave is allowed to place
further request
C Sometimes A sometimes B
D Cannot predict
36. Which of the following is not a mode of data transmission?
a) simplex
b) duplex
c) semi duplex
d) half duplex
37. If the data is transmitted only in one direction over a single communication channel, then it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
38. If the data transmission takes place in either direction, but at a time data may be transmitted only in one
direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
39. In 8251A, the pin that controls the rate at which the character is to be transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)
40. TXD(Transmitted Data Output) pin carries serial stream of the transmitted data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned
41. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY(Transmitter ready)
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)
42. The disadvantage of RS-232C is
a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned
43. What must be the contents of the control word of Intel 8255 for Mode 0 (operation) and for the following
ports configuration :
Port A-output, Port B-output, Port C lower-Output, Port C upper-input
(A) 85 H
(B) 86 H
(C) 87 H
(D) 88 H
44. Ports are used to connect the CPU to which of the following units ?
1. Printer
2. Floppy disk drives
3. Video display unit
4. Incoming power supply
Select the correct answer using the codes given below :
(A) 1 and 2
(B) 2 and 3
(C) 3 and 4
(D) 1 and 3
45. 8251 is a
(A) UART
(B) USART
(C) Programmable Interrupt controller
(D) Programmable interval timer/counter Ans. B
46. When the 8255 is reset, its I/O ports are all initializes as
(A) output port using mode 0
(B) Input port using mode 1
(C) output port using mode 1
(D) Input port using mode 0
47. Which pins are general purpose I/O pins during mode-2 operation of the 8255?
(A) PA0 – PA7
(B) PB0-PB7
(C) PC3-PC7
(D) PC0-PC2
48. Which is the commonly used programmable interface and particular used to provide handshaking:
A 8251
B 8254
C 8259
D 8255
49. Which provide a mechanism to establish a link between the microprocessor and i/o device:
A. Input interface
B. Output interface
C. Both a and b
D. None of these
50. In which the processor uses a protection of the memory address to represent I/O ports:
a. Memory mapped I/O
b. I/O memory mapped
c. Both a and b
d. None of these
51. The standard I /O is also called:
a. I/O mapped I/O
b. Isolated I/O
c. Both a and b
d. None of these
52. The processor of knowing the status of device and transferring the data with matching speeds is called:
a. Handshaking
b. Peripheral
c. Ports
d. None of these
53. Which is designed to automatically manage the handshake operation:
a. 8251
b. 8254
c. 8255
d. 8259
54. Which mode is used for single handshake in 8255:
a. Mode 0
b. Mode 1
c. Mode 2
d. None of these
55. Which mode is used for double handshake in 8255:
a. Mode 0
b. Mode 1
c. Mode 2
d. None of these
56. Which mode is used for simple input or output without handshaking:
a. Mode 0
b. Mode 1
c. Mode 2
d. None of these
57. Which PORT C pins are used for port B in 8255 mode 1:
a. PC0-PC2
b. PC3-PC7
c. PC6-PC7
d. PC3-PC5
58. Which are used for port A in 8255 mode 1:
a. PC0-PC2
b. PC3-PC7
c. PC6-PC7
d. PC3-PC5
59. Which are used for handshake lines for port A in 8255 mode 2:
a. PC0-PC2
b. PC3-PC7
c. PC6-PC7
d. PC3-PC5
60. A handshake signal in a data transfer is transmitted
(A) Along with the data bits
(B) Before the data transfer
(C) After the data transfer
(D) Either along with the bits or after the data transfer
61. How many ports do 8255 have?
A. 3
B. 4
C. 5
D. 6
62. How many modes do 8255 have?
A. 3
B. 4
C. 5
D. 6
63. Which of the following mode of 8255 is Strobed Bi-directional I/O?
A. Mode 0
B. Mode 1
C. Mode 2
D. Mode 4
64. Which of the following port can be programmed nibble wise (separately)?
A. Port A
B. Port B
C. Port C
D. Port D
65. Port A and lower nibble of Port C come under Group.
A. A
B. B
C. C
D. None
66. In BSR (bit set reset) mode, individual bits of port C can be accessed.
A. True
B. False
67. What is the purpose of B3B2B1 bits of control word in mode 0 (BSR mode)?
A. For BSR mode or I/O modes
B. for port B
C. For port C
D. for port C lower
68. What is the status of port bit if it is configured as an output port?
A0
B. 1
C. 10
D. 11
69. Give the control word address if port C lower bit is to be configured as input Port, port A as an output port in
mode 0 and port B is not used in I/O mode?
A. 80H
B. 81H
C. 87H
D. 07H
70. In 8255 following port is used for bidirectional data transfer
A. Port A
B. Port B
C. Port C
D. All of above
71. What is size of I/O ports in 8255
A.8 Bits
B. 16 Bits
C. 4 Bits
D. 2 Bits
8251
72. Register must be initialized before any use of 8251.
a. Command word register
b. Control word register
c. Mode word register
d. Both Command word register and Mode word register.
73. In asynchronous mode D7, D6 defines number of bits.
a. Stop
b. Parity
c. Character length
d. None of these
74. Setting of parity error flag (PE) will not stop the operation of receiver
a. True
b. False
75. The asynchronous mode is programmed by mode word format
a. True
b. False
76. When transmitter is enabled & ready to transmit the data value of CTS will be
a. 0
b. 1
c. 00
d. 11
77. Bits are transmitted serially on edge of TxC clock pulse
a. Falling
b. Rising
c. Trailing
d. None of these
78. Bits are received on edge of Txc clock pulse
b. Falling
c. Rising
d. Trailing
e. None of these
79. Signal is used to inform CPU about availability of data in receiver & CPU must
read this data
a. RxRDY
b. TxRDY
c. TxE
d. None of these
80. line is made high & sync characters are transmitted on TxD line
a. RxRDY
b. TxRDY
c. TxE
d. None of these.
81. When the data byte is loaded by CPU…………………
a. TxE line is low
b. TxE line is high
c. TxD line is low
d. TxD line is high
82. 8251 contains following blocks
a. Data bus buffer
b. Read write control logic
c. Transmitter section
d. Receiver section
e. Modem control
Ans: All of the above
83. 8251 accepts on data & decides which part to activate when……………….
a. CS=0
b. C/D=0
c. CS=1
d. C/D=1
84. 8251 contains data buffer registers
a. 2
b. 4
c. 1
d. None of these
85. When modem is ready for data transmission/reception it generate a signal to
indicate its readiness for data transfer.
a. DTR
b. DSR
c. CTS
d. Both a & c
86. 8251 support both synchronous & asynchronous communication.
a. True
b. False
87. Which is the programmable communication interface?
a. 8255
b. 8251
c. 8254
d. 8259
88. The communication between processor & 8251 can be done in ………mode only.
a. Parallel
b. Serial
c. Both a & b
d. None of these
89. 8251 converts… data for transmission to communicate with microprocessor.
a. Parallel to serial
b. Serial to parallel
c. Both a & b
d. None of these
90. 8251A support full duplex transmission & reception
a. True
b. False
91. The transmitter section converts a word received from microprocessor to
………..bits & transmits them over the TxD line to the peripheral.
a. Parallel, serial
b. Serial,parallel
c. Any, any
d. None of these
92. 8251 is a ……………..
a. UART
b. USART
c. Programable interrupt controller
d. Programable interval timer/counter
93. 8251 USART has built in baud rate generator.
a. True
b. False
94. 8251 USART provides double buffering of data in the transmission section & in the receiver section.
a. True
b. False
95. 8251 synchronous baud rate is……………..
a. 64K
b. 19.2K
c. 32K
d. 12K
96. Which of these errors are recognized by 8251 provides error detection logic , which detects parity, over run,
framing errors?
a. Parity
b. Overrun
c. Frame
d. All of these
97. 8251 has…… pin DIP package.
a. 28
b. 32
c. 26
d. 30
98. 8251 is having……………….. ,V supply.
a. Single,5
b. Single,8
c. Dual,5
d. Dual,8
99. Which of the following is a permissible character lengths applicable in 8251 asynchronous mode?
a. 6 bits
b. 7 bits
c. 8 bits
d. All of these
100. To detect SYNC character 8251A has to be in… mode.
a. Asynchronous
b. Character synchronization
c. Enter HUNT
d. None of these
101. 8251A sets…. pin high to indicate that the synchronization is achieved.
a. DSR
b. SYNDET
c. PE
d. FE
102………….controls the operation of USART within its basic frame work established by
the mode instruction.
a. Status word
b. Command instruction
c. Mode instruction
d. None of these
103. In mode instruction of 8251A… bit is added to the data bits only if parity isenabled
a. START
b. STOP
c. Parity
d. All of the above
104. In asynchronous mode USART transmitter always adds……………
a. Start bits
b. Stop bit
c. Parity bit
d. All of the above
105. 8251 when used as a modem control… indicates that the terminal is ready to
communicate.
a. DSR
b. DTR
c. CTS
d. RTS
106. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
107. In 8254, the operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
108. In 8254, the mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3
109. In 8254, the generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
110. In 8254, in control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
111. In 8254, the counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
112. In 8254, the control word register contents are used for
a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter regis
113. Signal voltage ranges for a logic high and for a logic low in RS-232C standard are
A. Low = 0 volt to 1.8 volt, high = 2.0 volt to 5 volt
B. Low =-15 volt to –3 vol, high = +3 volt to +15 volt
C. Low = +3 volt to +15 volt, high = -3 volt to -15 volt
D. Low = 2 volt to 5.0 volt, high = 0 volt to 1.8 volt
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Machine Language Instruction Formats”.
1. Operation code field is present in :
a) programming language instruction
b) assembly language instruction
c) machine language instruction
d) none of the mentioned
Answer: c
Explanation: Machine language instruction format has one or more fields. The first one is the
operation code field.
2. A machine language instruction format consists of
a) Operand field
b) Operation code field
c) Operation code field & operand field
d) none of the mentioned
Answer: c
Explanation: Machine language instruction format has both the fields.
3. The length of the one-byte instruction is
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
Answer: b
Explanation: This format is only one byte long.
4. The instruction format ‘register to register’ has a length of
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
Answer: a
Explanation: This format is 2 bytes long.
5. The R/M field in a machine instruction format specifies
a) another register
b) another memory location
c) other operands
d) all of the mentioned
Answer: d
Explanation: The LSBs
leastsignificantbits
from 0 to 3 represent R/M field that specifies another register or memory location i.e. the other
operand.
6. In a machine instruction format, S-bit is the
a) status bit
b) sign bit
c) sign extension bit
d) none of the mentioned
Answer: c
Explanation: The S-bit known as sign extension bit is used along with W-bit to show the type of
operation.
7. The bit which is used by the ‘REP’ instruction is
a) W-bit
b) S-bit
c) V-bit
d) Z-bit
Answer: d
Explanation: The Z-bit is used by the REP instruction to control the loop.
8. If a W-bit value is ‘1’ then the operand is of
a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits
Answer: c
Explanation: If W-bit is ‘1’ then the operand is of 16-bits, and if it is ‘0’ then the operand is of
8-bits.
9. The instructions which after execution transfer control to the next instruction in the sequence
are called
a) Sequential control flow instructions
b) control transfer instructions
c) Sequential control flow & control transfer instructions
d) none of the mentioned
Answer: a
Explanation: The sequential control flow instructions follow sequence order in their execution.
10. The instructions that transfer the control to some predefined address or the address
specified in the instruction are called as
a) sequential control flow instructions
b) control transfer instructions
c) sequential control flow & control transfer instructions
d) none of the mentioned
Answer: b
Explanation: The control transfer instructions transfer control to the specified address.
11. The instruction “JUMP” belongs to
a) sequential control flow instructions
b) control transfer instructions
c) branch instructions
d) control transfer & branch instructions
Answer: d
Explanation: The JUMP instruction transfers the control to the address located in the instruction.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Addressing Modes of 8086”.
1. The instruction, MOV AX, 0005H belongs to the address mode
a) register
b) direct
c) immediate
d) register relative
Answer: c
Explanation: In Immediate addressing mode, immediate data is a part of instruction and appears
in the form of successive byte or bytes.
2. The instruction, MOV AX, 1234H is an example of
a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
Answer: c
Explanation: Since immediate data is present in the instruction.
3. The instruction, MOV AX, [2500H] is an example of
a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
Answer: b
Explanation: Since the address is directly specified in the instruction as a part of it.
4. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
Answer: b
Explanation: Since register is used to refer the address.
5. The instruction, MOV AX,[BX] is an example of
a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
Answer: d
Explanation: Since the register used to refer to the address is accessed indirectly.
6. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned
Answer: c
Explanation: In the indexed addressing mode, the offset of an operand is stored and in the rest
of them, address is stored.
7. The addressing mode that is used in unconditional branch instructions is
a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
Answer: b
Explanation: In intrasegment indirect mode, the branch address is found as the content of a
register or a memory location.
8. If the location to which the control is to be transferred lies in a different segment other than
the current one, then the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode
Answer: d
Explanation: In intersegment mode, the control to be transferred lies in a different segment.
9. The instruction, JMP 5000H:2000H;
is an example of
a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode
Answer: c
Explanation: Since in intersegment direct mode, the address to which the control is to be
transferred is in a different segment.
10. The contents of a base register are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode
Answer: d
Explanation: The effective address is formed by adding the contents of both base and index
registers to a default segment.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Instruction Set of 8086/8088 – 1”.
1. The instruction that is used to transfer the data from source operand to destination operand is
a) data copy/transfer instruction
b) branch instruction
c) arithmetic/logical instruction
d) string instruction
Answer: a
Explanation: These instructions are used to copy and transfer the instructions.
2. Which of the following is not a data copy/transfer instruction?
a) MOV
b) PUSH
c) DAS
d) POP
Answer: c
Explanation: DAS
DecimalAdjustafterSubtraction
is an arithmetic instruction.
3. The instructions that involve various string manipulation operations are
a) branch instructions
b) flag manipulation instructions
c) shift and rotate instructions
d) string instructions
Answer: d
Explanation: The string instructions perform operations on strings such as load, move, scan,
compare etc.
4. Which of the following instruction is not valid?
a) MOV AX, BX
b) MOV DS, 5000H
c) MOV AX, 5000H
d) PUSH AX
Answer: b
Explanation: Both the source and destination operands cannot be memory locations except for
string instructions.
5. In PUSH instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
Answer: d
Explanation: The actual current stack-top is always occupied by the previously pushed data. So,
the push operation decrements SP by 2 and then stores the two bytes contents of the operand
onto the stack.
6. The instruction that pushes the contents of the specified register/memory location on to the
stack is
a) PUSHF
b) POPF
c) PUSH
d) POP
Answer: c
Explanation: Since PUSH operation transfers data to stack from a register or memory location.
7. In POP instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
Answer: c
Explanation: The actual current stack top is poped into the specific operand as the contents of
stack top memory is stored in AL&SP and further contents of the memory location pointed to by
SP are copied to AH & SP.
8. The instructions that are used for reading an input port and writing an output port respectively
are
a) MOV, XCHG
b) MOV, IN
c) IN, MOV
d) IN, OUT
Answer: d
Explanation: The address of the input/output port may be specified directly or indirectly.
Example for input port: IN AX, DX; This instruction reads data from a 16-bit port whose address
is in DX and stores it in AX
Example for output port: OUT 03H, AL; This sends data available in AL to a port whose address
is 03H.
9. The instruction that is used for finding out the codes in case of code conversion problems is
a) XCHG
b) XLAT
c) XOR
d) JCXZ
Answer: b
Explanation: The translate
XLAT
instruction is used to find codes.
10. The instruction that loads effective address formed by destination operand into the specified
source register is
a) LEA
b) LDS
c) LES
d) LAHF
Answer: a
Explanation: The instruction, LEA loads effective address and is more useful for assembly
language rather than for machine language.
11. The instruction that loads the AH register with the lower byte of the flag register is
a) SAHF
b) AH
c) LAHF
d) PUSHF
Answer: c
Explanation: The instruction LAHF
LoadAHfromalowerbyteofFlag
may be used to observe the status of all the condition code flags
exceptoverflowflag
at a time.
12. The instruction that pushes the flag register on to the stack is
a) PUSH
b) POP
c) PUSHF
d) POPF
Answer: c
Explanation: The instruction PUSHF
pushflagstostack
pushes the flag register on to the stack.
13. The instruction that loads the flag register completely from the word contents of the memory
location is
a) PUSH
b) POP
c) PUSHF
d) POPF
Answer: d
Explanation: POPF is pop flags to stack.
14. The instruction that adds immediate data/contents of the memory location specified in an
instruction/register to the contents of another register/memory location is
a) SUB
b) ADD
c) MUL
d) DIV
Answer: b
Explanation: ADD instruction adds the data.
15. The instruction that supports addition when carry exists is
a) ADD
b) ADC
c) ADD & ADC
d) None of the mentioned
Answer: b
Explanation: ADC
AddwithCarry
instruction performs the same operation as ADD operation, but adds the carry flag bit to the
result.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Interview Questions and Answers focuses on “Instruction Set of
8086/8088 – 2”.
1. The instruction, “INC” increases the contents of the specified register or memory location by
a) 2
b) 0
c) 1
d) 3
Answer: c
Explanation: This instruction adds 1 to the contents of the operand and so increments by 1.
2. The instruction that subtracts 1 from the contents of the specified register/memory location is
a) INC
b) SUBB
c) SUB
d) DEC
Answer: d
Explanation: The DEC instruction decrements the contents of a specified register/memory
location by 1.
3. The instruction that enables subtraction with borrow is
a) DEC
b) SUB
c) SBB
d) None of the mentioned
Answer: c
Explanation: The SBB instruction subtracts the source operand and the borrow flag from the
destination operand.
4. The flag that acts as Borrow flag in the instruction, SBB is
a) direction flag
b) carry flag
c) parity flag
d) trap flag
Answer: b
Explanation: If borrow exists in the subtraction operation performed then carry flag is set.
5. In general, the source operand of an instruction can be
a) memory location
b) register
c) immediate data
d) all of the mentioned
Answer: d
Explanation: The source operand is the element which is data or data stored memory location
on which operation is performed.
6. In general, the destination operand of an instruction can be
a) memory location
b) register
c) immediate data
d) memory location and register
Answer: d
Explanation: Since the destination should be able to store the data, immediate data cannot be
considered as a destination operand.
7. The instruction, CMP to compare source and destination operands it performs
a) addition
b) subtraction
c) division
d) multiplication
Answer: b
Explanation: For comparison, the instruction CMP subtracts source operand from destination
operand.
8. During comparison operation, the result of comparing or subtraction is stored in
a) memory
b) registers
c) stack
d) no where
Answer: d
Explanation: The result of subtraction operation is not stored anywhere during a comparison.
9. The instruction that converts the result in an unpacked decimal digits is
a) AAA
b) AAS
c) AAM
d) All of the mentioned
Answer: d
Explanation: All the ASCII adjust instructions give result in unpacked decimal form and so are
called as “Unpacked BCD arithmetic instructions”.
10. Which of the following is a mnemonic?
a) ADD
b) ADC
c) AAA
d) ADD & ADC
Answer: c
Explanation: AAA is a mnemonic. It doesn’t have either a source or destination operand.
11. The instruction in which adjustment is made before performing the operation is
a) AAA
b) AAS
c) AAM
d) AAD
Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL. This adjustment must be made before dividing the two
unpacked BCD digits.
12. The expansion of DAA is
a) decimal adjust after addition
b) decimal adjust before addition
c) decimal adjust accumulator
d) decimal adjust auxiliary
Answer: c
Explanation: This instruction performs conversion operation.
13. The instruction that is used to convert the result of the addition of two packed BCD numbers
to a valid BCD number is
a) DAA
b) DAS
c) AAA
d) AAS
Answer: a
Explanation: In this conversion, the result has to be only in AL.
14. The ROR instruction rotates the contents of the destination operand to
a) left
b) right
c) left and then right
d) right and then left
Answer: b
Explanation: ROR stands for Rotate Right without carry. so, the instruction rotates right.
To practice all areas of Microprocessors for Interviews, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessors Questions and Answers for Freshers focuses on “Instruction Set of
8086/8088 – 3”.
1. The mnemonic that is placed before the arithmetic operation is performed is
a) AAA
b) AAS
c) AAM
d) AAD
Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL.
2. The Carry flag is undefined after performing the operation
a) AAA
b) ADC
c) AAM
d) AAD
Answer: d
Explanation: Since the operation, AAD is performed before division operation is performed, the
carry flag, auxiliary flag and overflow flag are undefined.
3. The instruction that performs logical AND operation and the result of the operation is not
available is
a) AAA
b) AND
c) TEST
d) XOR
Answer: c
Explanation: In the TEST instruction, the logical AND operation is performed and the result is
not stored but flags are affected.
4. In the RCL instruction, the contents of the destination operand undergo function as
a) carry flag is pushed into LSB & MSB is pushed into the carry flag
b) carry flag is pushed into MSB & LSB is pushed into the carry flag
c) auxiliary flag is pushed into LSB & MSB is pushed into the carry flag
d) parity flag is pushed into MSB & LSB is pushed into the carry flag
Answer: a
Explanation: In RCL
Rotaterightthroughcarry
, for each operation, the carry flag is pushed into LSB and the MSB of the operand is pushed
into carry flag.
5. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX
register becomes zero is
a) SCAS
b) REP
c) CMPS
d) STOS
Answer: b
Explanation: The instruction to which the REP is prefix, is executed repeatedly until CX register
becomes zero. When CX becomes zero, the execution proceeds to the next instruction in
sequence.
6. Match the following
A) MOvSB/SW 1) loads AL/AX register by content of a string
B) CMPS 2) moves a string of bytes stored in source to destination
C) SCAS 3) compares two strings of bytes or words whose length is stored in CX register
D) LODS 4) scans a string of bytes or words
a) A-3,B-4,C-2,D-1
b) A-2,B-1,C-4,D-3
c) A-2,B-3,C-1,D-4
d) A-2,B-3,C-4,D-1
Answer: d
Explanation: By using the string instructions, the operations on strings can be performed.
7. The instructions that are used to call a subroutine from the main program and return to the
main program after execution of called function are
a) CALL, JMP
b) JMP, IRET
c) CALL, RET
d) JMP, RET
Answer: c
Explanation: At each CALL instruction, the IP and CS of the next instruction are pushed onto the
stack, before the control is transferred to the procedure. At the end of the procedure, the RET
instruction must be executed to retrieve the stored contents of IP & CS registers from a stack.
8. The instruction that unconditionally transfers the control of execution to the specified address
is
a) CALL
b) JMP
c) RET
d) IRET
Answer: b
Explanation: In this the control transfers to the address specified in the instruction and flags are
not affected by this instruction.
9. Which instruction cannot force the 8086 processor out of ‘halt’ state?
a) Interrupt request
b) Reset
c) Both interrupt request and reset
d) Hold
Answer: d
Explanation: Only an interrupt request or Reset will force the 8086 processor to come out of the
‘halt’ state.
10. NOP instruction introduces
a) Address
b) Delay
c) Memory location
d) None of the mentioned
Answer: b
Explanation: NOP is the No operation. It means that the processor performs no operation for the
clock cycle and thus there exists a delay.
11. Which of the following is not a machine controlled instruction?
a) HLT
b) CLC
c) LOCK
d) ESC
Answer: b
Explanation: Since CLC is a flag manipulation instruction where CLC stands for Clear Carry
Flag.
To practice all areas of Microprocessors for Freshers, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Assembler Directives and Operators”.
1. The assembler directives which are the hints using some predefined alphabetical strings are
given to
a) processor
b) memory
c) assembler
d) processor & assembler
Answer: c
Explanation: These directives help the assembler to correctly understand the assembly
language programs to prepare the codes.
2. The directive used to inform the assembler, the names of the logical segments to be assumed
for different segments used in the program is
a) ASSUME
b) SEGMENT
c) SHORT
d) DB
Answer: a
Explanation: In ALP, each segment is given a name by using the directive ASSUME
SYNTAX: ASSUME segment:segment_name
Eg: ASSUME CS:Code
here CS is the Code segment and code is the name assumed to the segment.
3. Match the following
a) DB 1) used to direct the assembler to reserve only 10-bytes
b) DT 2) used to direct the assembler to reserve only 4 words
c) DW 3) used to direct the assembler to reserve byte or bytes
d) DQ 4) used to direct the assembler to reserve words
a) a-3, b-2, c-4, d-1
b) a-2, b-3, c-1, d-4
c) a-3, b-1, c-2, d-4
d) a-3, b-1, c-4, d-2
Answer: d
Explanation: These directives are used for allocating memory locations in the available memory.
4. The directive that marks the end of an assembly language program is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
Answer: b
Explanation: The directive END is used to denote the completion of the program.
5. The directive that marks the end of a logical segment is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
Answer: a
Explanation: The directive ENDS is used to end a segment where as the directive END is used
to end the program.
6. The directive that updates the location counter to the next even address while executing a
series of instructions is
a) EVN
b) EVEN
c) EVNE
d) EQU
Answer: b
Explanation: The directive updates location counter to next even address if the current location
counter contents are not even.
7. The directive that directs the assembler to start the memory allotment for a particular
segment/block/code from the declared address is
a) OFFSET
b) LABEL
c) ORG
d) GROUP
Answer: c
Explanation: If an ORG is written then the assembler initiates the location counter to keep the
track of allotted address for the module as mentioned in the directive.
If the directive is not present, then the location counter is initialized to 0000H.
8. The directive that marks the starting of the logical segment is
a) SEG
b) SEGMENT
c) SEG & SEGMENT
d) PROC
Answer: b
Explanation: The directive SEGMENT indicates the beginning of the segment.
9. The recurrence of the numerical values or constants in a program code is reduced by
a) ASSUME
b) LOCAL
c) LABEL
d) EQU
Answer: d
Explanation: In this, the recurring/repeating value is assigned with a label. The label is placed
instead of the numerical value in the entire program code.
10. The labels or constants that can be used by any module in the program is possible when
they are declared as
a) PUBLIC
b) LOCAL
c) GLOBAL
d) Either PUBLIC or GLOBAL
Answer: c
Explanation: The labels, constants, variables, procedures declared as GLOBAL can be used by
any module in the program.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Technical Interview Questions & Answers focuses on “Do’s and
Don’ts While Using Instructions”.
1. The logic required for implementing a program can be expressed in terms of
a) flowchart
b) algorithm
c) flowchart & algorithm
d) none of the mentioned
Answer: c
Explanation: The logic required for implementing a program must be visualized clearly which is
possible by flowchart and algorithm.
2. The operands, source and destination in an instruction cannot be
a) register, register
b) memory location, memory location
c) memory location, register
d) immediate data, register
Answer: b
Explanation: Only one memory operand can be specified in one instruction.
3. The instruction that is not possible among the following is
a) MOV AX, BX
b) MOV AX, [BX].
c) MOV 55H, BL
d) MOV AL, 55H
Answer: c
Explanation: 8-bit or 16-bit operand cannot be used as a destination operand.
4. The instruction that is not possible among the following is
a) MOV AX, [BX].
b) MOV AX, 5555H
c) MOV AX, [SI].
d) MOV [SI], [DI].
Answer: d
Explanation: Both the operands cannot be memory operands.
5. Both the operands source and destination of an instruction cannot be
a) register, register
b) immediate data, register
c) register, immediate data
d) immediate data, memory location
Answer: c
Explanation: Since destination operand should not be immediate data.
6. The registers that cannot be used as operands for arithmetic and logical instructions are
a) general purpose registers
b) pointers
c) index registers
d) segment registers
Answer: d
Explanation: Segment registers are not allowed as operands for arithmetic and logical
instructions.
7. The operands of an instruction cannot be
a) registers
b) memory operands and immediate operands
c) immediate operands
d) memory operands
Answer: b
Explanation: Both the operands should not be immediate operands and memory operands.
To practice all technical interview questions on Microprocessors, here is complete set of 1000+
Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Programming With An Assembler”.
1. The disadvantage of machine level programming is
a) time consuming
b) chances of error are more
c) debugging is difficult
d) all of the mentioned
Answer: d
Explanation: The machine level programming is complicated.
2. The coded object modules of the program to be assembled are present in
a) .ASM file
b) .OBJ file
c) .EXE file
d) .OBJECT file
Answer: b
Explanation: .OBJ file is created with same name as source file and extension .OBJ. It contains
the coded object modules of the program to be assembled.
3. The advantages of assembly level programming are
a) flexibility of programming is more
b) chances of error are less
c) debugging is easy
d) all of the mentioned
Answer: d
Explanation: The assembly level programming is more advantageous than the machine level
programming.
4. The extension that is essential for every assembly level program is
a) .ASP
b) .ALP
c) .ASM
d) .PGM
Answer: c
Explanation: All the files should have the extension, .ASM.
5. The directory that is under work must have the files that are related to
a) Norton’s editor
b) Assembler
c) Linker
d) All of the mentioned
Answer: d
Explanation: Before starting the process of entering a small program on PC, ensure that all the
files namely Norton’s editor, assembler, linker and debugger are available in the same directory
in which work is been done.
6. The listing file is identified by
a) source file name
b) extension .LSF
c) source file name and an extension .LSF
d) source file name and an extension .LST
Answer: d
Explanation: The listing file is automatically generated in the assembly process and is identified
by the entered or source file name and an extension .LST.
7. The extension file that is must for a file to be accepted by the LINK as a valid object file is
a) .OBJ file
b) .EXE file
c) .MASM file
d) DEBUG file
Answer: a
Explanation: The .OBJ extension is a must for a file to be accepted by the LINK as a valid object
file.
8. The listing file contains
a) total offset map of a source file
b) offset address and labels
c) memory allotments for different labels
d) all of the mentioned
Answer: d
Explanation: The listing file contains total offset map of source file including labels, offset
addresses, opcodes, memory allotments for different directives and labels and relocation
information.
9. DEBUG.COM facilitates the
a) debugging
b) trouble shooting
c) debugging and trouble shooting
d) debugging and assembling
Answer: c
Explanation: DEBUG.COM is a DOS utility that facilitates the debugging and trouble shooting.
10. DEBUG is able to troubleshoot only
a) .EXE files
b) .OBJ files
c) .EXE file and .OBJ file
d) .EXE flie and .LST file
Answer: a
Explanation: The DEBUG may be used either to debug a source program or to observe the
results of execution of an .EXE file.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Stack”.
1. The Stack follows the sequence
a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out
Answer: c
Explanation: The stack follows last-in-first-out sequence.
2. If the processor is executing the main program that calls a subroutine, then after executing
the main program up to the CALL instruction, the control will be transferred to
a) address of main program
b) subroutine address
c) address of CALL instruction
d) none of the mentioned
Answer: b
Explanation: Since subroutine is called, to start the execution of the subroutine, the control is
transferred to the subroutine address.
3. The stack is useful for
a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned
Answer: d
Explanation: Stack is used for temporary storage of contents of registers and memory locations,
status of registers.
4. The Stack is accessed using
a) SP register
b) SS register
c) SP and SS register
d) None of the mentioned
Answer: c
Explanation: The stack is accessed using a pointer that is implemented using SP and SS
registers.
5. As the storing of data words onto the stack is increased, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
Answer: d
Explanation: The data is stored from top address of the stack and is decremented by 2.
6. While retrieving data from the stack, the stack pointer is
a) incremented by 1
b) incremented by 2
c) decremented by 1
d) decremented by 2
Answer: b
Explanation: The data in the stack, may again be transferred back from a stack to register. At
that time, the stack pointer is incremented by 2.
7. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into
Answer: c
Explanation: The data is pushed into the stack while loading the stack.
8. The reverse process of transferring the data back from the stack to the CPU register is known
as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack
Answer: d
Explanation: The data retrieved from stack is called popping off.
9. The books arranged one on the other on a table is an example of
a) queue
b) queue and first-in-first out
c) stack
d) stack and last-in-first-out
Answer: d
Explanation: If the books are arranged one on the other, then the book that is placed last will be
the first out.
10. The PID temperature controller using 8086 has
a) data flow
b) data flow and uses queue
c) sequential flow
d) sequential flow and uses stack
Answer: d
Explanation: Since PID temperature controller has steps that need to be sequentially executed
such as sampling the output, conversion of a signal with ADC, finding errors, deriving control
signals and applying the control signal to control flow of energy.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Stack Structure of 8086/8088”.
1. The stack pointer register contains
a) address of the stack segment
b) pointer address of the stack segment
c) offset of address of stack segment
d) data present in the stack segment
Answer: c
Explanation: The stack pointer register contains the offset of the address of the stack segment.
2. The stack segment register contains
a) address of the stack segment
b) base address of the stack segment
c) pointer address of the stack segment
d) data in the stack segment
Answer: b
Explanation: The stack segment register contains base address of the stack segment in the
memory. The stack pointer register
sP
and stack segment register
SS
together address the stack-top.
3. PUSH operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
Answer: a
Explanation: Each PUSH operation decrements the SP
StackPointer
register.
4. POP operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
Answer: b
Explanation: Each POP operation increments the SP
StackPointer
register.
5. The register or memory location that is pushed into the stack at the end must be
a) popped off last
b) pushed off first
c) popped off first
d) pushed off last
Answer: c
Explanation: The data can be retrieved by POP operation and as in stack, the data that is
pushed at the end must be popped off first.
6. In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK
the ASSUME directive directs to the assembler the
a) address of the stack segment
b) pointer address of the stack segment
c) name of the stack segment
d) name of the stack, code and data segments
Answer: d
Explanation: The directive ASSUME facilitates to name the segments with the desired name
that is not a mnemonic or keyword.
7. When a stack segment is initialised then
a) SS and SP are initialised
b) only SS is initialised
c) only SP is initialised
d) SS and SP need not be initialised
Answer: a
Explanation: Though the Stack segment is initialised, the SS and SP pointers must be
initialised.
8. The number of PUSH instructions and POP instructions in a subroutine must be
a) PUSH instructions must be greater than POP instructions
b) POP instructions must be greater than PUSH instructions
c) Both must be equal
d) Instructions may be any kind
Answer: c
Explanation: The number of PUSH instructions must be equal to the number of POP
instructions.
9. 8086 does not support
a) Arithmetic operations
b) logical operations
c) BCD operations
d) Direct BCD packed multiplication
Answer: d
Explanation: The 8086 microprocessor does not support direct BCD packed operations.
10. For 8086 microprocessor, the stack segment may have a memory block of a maximum of
a) 32K bytes
b) 64K bytes
c) 16K bytes
d) NONE
Answer: b
Explanation: In 8086 microprocessor, the memory segments each have a memory of 64K bytes.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interrupts and Interrupt Service Routines”.
1. While CPU is executing a program, an interrupt exists then it
a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
Answer: c
Explanation: An interrupt function is to break the sequence of operation.
2. An interrupt breaks the execution of instructions and diverts its execution to
a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit
Answer: a
Explanation: An interrupt transfers the control to interrupt service routine
ISR
. After executing ISR, the control is transferred back again to the main program.
3. While executing the main program, if two or more interrupts occur, then the sequence of
appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt
Answer: d
Explanation: If an interrupt occurs while executing a program, and the processor is executing
the interrupt, if one more interrupt occurs again, then it is called a nested interrupt.
4. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to
handle them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability
Answer: c
Explanation: The processor if handles more devices as interrupts then it has multiple interrupt
processing ability.
5. NMI stands for
a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none of the mentioned
Answer: a
Explanation: NMI is the acronym for nonmaskable interrupt.
7. If any interrupt request given to an input pin cannot be disabled by any means then the input
pin is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
d) none of the mentioned
Answer: b
Explanation: A nonmaskable interrupt input pin is one which means that any interrupt request at
NMI
nonmaskableinterrupt
input cannot be masked or disabled by any means.
8. The INTR interrupt may be
a) maskable
b) nonmaskable
c) maskable and nonmaskable
d) none of the mentioned
Answer: a
Explanation: the INTR
interruptrequest
is maskable or can be disabled.
9. The Programmable interrupt controller is required to
a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request
Answer: b
Explanation: If more than one interrupt request
INTR
occurs at a time, then an external chip called programmable interrupt controller is required to
handle them.
10. The INTR interrupt may be masked using the flag
a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag
Answer: c
Explanation: If a microprocessor wants to serve any interrupt then interrupt flag, IF=1. If interrupt
flag, IF=0, then the processor ignores the service.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interrupt Cycle of 8086/8088”.
1. If an interrupt is generated from outside the processor then it is an
a) internal interrupt
b) external interrupt
c) interrupt
d) none of the mentioned
Answer: b
Explanation: If an external device or a signal interrupts the processor from outside then it is an
external interrupt.
2. If the interrupt is generated by the execution of an interrupt instruction then it is
a) internal interrupt
b) external interrupt
c) interrupt-in-interrupt
d) none of the mentioned
Answer: a
Explanation: The internal interrupt is generated internally by the processor circuit or by the
execution of an interrupt instruction.
3. Example of an external interrupt is
a) divide by zero interrupt
b) keyboard interrupt
c) overflow interrupt
d) type2 interrupt
Answer: b
Explanation: Since the keyboard is external to the processor, it is an external interrupt.
4. Example of an internal interrupt is
a) divide by zero interrupt
b) overflow interrupt
c) interrupt due to INT
d) all of the mentioned
Answer: d
Explanation: Since the interrupts occur within the processor itself, they are called internal
interrupts.
5. The interrupt request that is independent of IF flag is
a) NMI
b) TRAP
c) Divide by zero
d) All of the mentioned
Answer: d
Explanation: These requests are independent of IF flag.
6. The type of the interrupt may be passed to the interrupt structure of CPU from
a) interrupt service routine
b) stack
c) interrupt controller
d) none of the mentioned
Answer: c
Explanation: After an interrupt is acknowledged, the CPU computes the vector address from the
type of the interrupt that may be passed to the internal structure of the CPU from an interrupt
controller in case of external interrupts.
7. During the execution of an interrupt, the data pushed into the stack is the content of
a) IP
b) CS
c) PSW
d) All of the mentioned
Answer: d
Explanation: The contents of IP, CS and PSW are pushed into the stack during the execution.
8. After every response to the single step interrupt the flag that is cleared is
a) IF
InterruptFlag
b) TF
TrapFlag
c) OF
OverflowFlag
d) None of the mentioned
Answer: b
Explanation: If the trap flag is set then the processor enters the single step execution mode.
After the execution, the trap flag is cleared.
9. At the end of ISR, the instruction should be
a) END
b) ENDS
c) IRET
d) INTR
Answer: c
Explanation: After the execution of the ISR, the control must go to the previous program
maybemainprogram
which was being executed. To execute it, IRET is placed at the end of ISR.
10. When the CPU executes IRET,
a) contents of IP and CS are retrieved
b) the control transfers from ISR to main program
c) clears the trap flag
d) clears the interrupt flag
Answer: a
Explanation: When the instruction IRET is executed, the contents of flags, IP and CS which
were saved at the stack by the CALL instruction are retrieved to the respective registers.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Non Maskable Interrupt and Maskable Interrupt
INTR
”.
1. The interrupt for which the processor has the highest priority among all the external interrupts
is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
Answer: c
Explanation: The Non-Maskable Interrupt input pin has the highest priority among all the
external interrupts.
2. The interrupt for which the processor has highest priority among all the internal interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
Answer: b
Explanation: TRAP is the internal interrupt that has highest priority among all the interrupts
except the Divide By Zero
Type0
exception.
3. In case of string instructions, the NMI interrupt will be served only after
a) initialisation of string
b) execution of some part of the string
c) complete string is manipulated
d) the occurrence of the interrupt
Answer: c
Explanation: When NMI is activated, the current instruction being executed is completed and
then NMI is served. In the case of string instructions, it is served after the complete string is
manipulated.
4. The NMI pin should remain high for atleast
a) 4 clock cycles
b) 3 clock cycles
c) 1 clock cycle
d) 2 clock cycles
Answer: d
Explanation: The NMI pin should remain high for atleast 2 clock cycles and need not be
synchronized with the clock for being sensed.
5. The INTR signal can be masked by resetting the
a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag
Answer: b
Explanation: The INTR signal can be masked by resetting the interrupt flag.
6. For the INTR signal, to be responded to in the next instruction cycle, it must go ________ in
the last clock cycle of the current instruction
a) high
b) low
c) high or low
d) unchanged
Answer: a
Explanation: The INTR signal must go high in the clock cycle of the current instruction in order
to respond in the next instruction cycle.
7. The status of the pending interrupts is checked at
a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle
Answer: d
Explanation: At the end of each instruction, the status of the pending interrupts is checked.
8. Once the processor responds to an INTR signal, the IF is automatically
a) set
b) reset
c) high
d) low
Answer: b
Explanation: The IF is automatically reset when the processor responds to an INTR signal. If the
processor wants to respond to any type of INTR signal further then, the IF should again be set.
9. If the pin LOCK
activelowbased
is low at the trailing edge of the first ALE pulse, then till the start of the next machine cycle, the
pin LOCK
activelow
is
a) low
b) high
c) low or high
d) none of the mentioned
Answer: a
Explanation: The pin LOCK
activelow
remains low till the start of the next machine cycle.
10. With the trailing edge of the LOCK
activelow
, the INTA
activelow
goes low and remains in it for
a) 0 clock cycle
b) 1 clock cycle
c) 2 clock cycles
d) 3 clock cycles
Answer: c
Explanation: The INTA
activelow
goes low and remains low for two clock cycles before returning back to the high state.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Interview Questions and Answers for freshers focuses on “Interrupt
Programming, Passing Parameters to Procedures, Handling Programs of Size More Than
64KB”.
1. The method of defining the interrupt service routine for software is
a) same as that of hardware
b) difficult than hardware
c) easier than software
d) none of the mentioned
Answer: a
Explanation: For both software and hardware, the method of defining the interrupt service
routine is the same.
2. While programming for any type of interrupt, the interrupt vector table is set
a) externally
b) through a program
c) either externally or through the program
d) externally and through the program
Answer: c
Explanation: The programmer must, either externally or through the program, set the interrupt
vector table for that type preferably with the CS and IP addresses of the interrupt service
routine.
3. To execute a program one should
a) assemble the program
b) link the program
c) apply external pulse
d) all of the mentioned
Answer: d
Explanation: To execute a program, first assemble it, link it and then execute it. After execution,
a new file RESULT is created in the directory. Then external pulse is applied to IRQ2 pin, and
this will again cause the execution of ISR into the file.
4. Procedures are also known as
a) macros
b) segment
c) subroutines
d) none
Answer: c
Explanation: Procedures are also known as subroutines.
5. Procedures, for their execution, require
a) input data
b) output data
c) constants
d) input data or constants
Answer: d
Explanation: Procedures require input data or constants for their execution. Their data or
constants may be passed to the subroutine by the main program.
6. The technique that is used to pass the data or parameter to procedures in assembly
language program is by using
a) global declared variable
b) registers
c) stack
d) all of the mentioned
Answer: d
Explanation: The techniques that are used to pass the data or parameter to procedures are by
using global declared variable, registers of CPU, memory locations, stack, PUBLIC & EXTRN.
7. If a procedure is interactive, then
a) it accepts inputs directly from input devices
b) it uses global declared variable technique
c) it uses stack
d) it uses memory locations
Answer: a
Explanation: If a procedure is interactive, then it accepts the inputs directly from input devices.
8. For passing the parameters to procedures using the PUBLIC & EXTRN directives, it must be
declared PUBLIC in the
a) subroutine
b) procedure
c) main routine
d) main routine and subroutine
Answer: c
Explanation: For passing the parameters to procedures, it must be declared PUBLIC in the main
routine and the same should be declared EXTRN in the procedure.
9. The technique to estimate the size of an executable program, before it is assembled and
linked is
a) memory location technique
b) global variable technique
c) stack
d) none
Answer: d
Explanation: There is no technique to estimate the size of an executable program before it is
assembled and linked.
10. To estimate the size of an executable program before it is assembled and linked, the
programming methodology concerned is by writing
a) programs with more than one segment for data and code
b) programs with FAR subroutines each of size up to 64KB
c) programs with more than one segment for stack
d) all of the mentioned
Answer: d
Explanation: By writing programs with more than one segment for data, code or stack or by
writing programs with FAR subroutines each of size 64KB, the size of an executable program
can be estimated.
To practice all areas of Microprocessors for Interviews, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Macros”.
1. If a number of instructions are repeating through the main program, then to reduce the length
of the program, __________ is used.
a) procedure
b) subroutine
c) macro
d) none of the mentioned
Answer: c
Explanation: For a certain number of instructions that are repeated in the main program, when
macro is defined then the code of a program is reduced by placing the name of the macro at
which the set of instructions are needed to be repeated.
2. The process of assigning a label or macroname to the string is called
a) initialising macro
b) initialising string macro
c) defining a string macro
d) defining a macro
Answer: d
Explanation: The process of assigning a label to the string is called defining a macro.
3. A macro within a macro is called
a) macro-within-macro
b) nested macro
c) macro-in-macro
d) none of the mentioned
Answer: b
Explanation: A macro may be called from inside a macro. This type of macro is called nested
macro.
4. A macro can be defined as
a) beginning of a program
b) end of a program
c) after initialisation of program
d) anywhere in a program
Answer: d
Explanation: A macro can be defined anywhere in a program.
5. A macro can be used as ________
a) in data segment
b) to represent directives
c) to represent statements
d) all of the mentioned
Answer: d
Explanation: A macro may be used in data segment and can also be used to represent
statements and directives.
6. The end of a macro can be represented by the directive.
a) END
b) ENDS
c) ENDM
d) ENDD
Answer: c
Explanation: The ENDM directive marks the end of the instructions or statements sequence
assigned with the macro name.
7. Inserting the statements and instructions represented by macro, directly at the place of the
macroname, in the program, is known as
a) calling a macro
b) inserting a macro
c) initializing a macro
d) none of the mentioned
Answer: a
Explanation: Inserting the statements and instructions at the place of macroname, in the
program, is known as calling a macro.
8. The time required for execution of a macro is ________ that of the procedure.
a) greater than
b) less than
c) equal to
d) none of the mentioned
Answer: b
Explanation: The time required for execution of a macro is less than that of procedure as it does
not contain CALL and RET instructions as the procedures do.
9. Which of the following statements is incorrect?
a) complete code of instruction string is inserted at each place, wherever the macroname
appears
b) macro requires less time of execution than that of procedure
c) macro uses stack memory
d) macroname can be anything except registers and mnemonics
Answer: c
Explanation: Macro does not require stack memory and hence has less time for execution.
10. The beginning of the macro can be represented as
a) START
b) BEGIN
c) MACRO
d) None of the mentioned
Answer: c
Explanation: The beginning of the macro is represented as macroname followed by the directive
MACRO.
SYNTAX: macroname MACRO
EXAMPLE: STRINGS MACRO.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Timings and Delays”.
1. If ‘n’ denotes the number of clock cycles and ‘T’ denotes period of the clock at which the
microprocessor is running, then the duration of execution of loop once can be denoted by
a) n+T
b) n-T
c) n*T
d) n/T
Answer: c
Explanation: The duration of execution of the loop is the product of number of clock cycles and
the period of the clock cycle at which microprocessor is running.
2. The number of instructions actually executed by the microprocessor depends on the
a) stack
b) loop count
c) program counter
d) time duration
Answer: b
Explanation: As the microprocessor executes each instruction corresponding loop counter value
decreases and the microprocessor executes the instructions till the loop counter becomes zero.
3. In case of subroutines, the actual number of instructions executed by the processor depends
on
a) loop count
b) length of interrupt service routine
c) length of procedure
d) none
Answer: c
Explanation: In case of subroutines or interrupt service routines, the number of instructions
executed by the processor depends on the length of procedure
orsubroutine
or length of interrupt service routine along with the main calling program.
4. The step included in generating delays is
a) determining exact required delay
b) selecting instructions for delay loop
c) finding period of clock frequency
d) all of the mentioned
Answer: d
Explanation: The delays can be generated step wise.
5. The Count, N can be defined as
a) required delay/duration for execution
b) duration of execution/required delay
c) required delay/number of clock cycles
d) required delay/period of clock frequency
Answer: a
Explanation: The count N can be defined as the required time delay by the duration for
execution of the loop once.
Count, N = required delay
Td
/duration for execution of the loop once
n∗T
.
6. In the instruction set,
MOV CX, BA03H
WAIT: DEC CX
NOP
JNZ WAIT
RET
if the zeroth condition is satisfied then, for execution, the JNZ instruction takes
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
Answer: d
Explanation: The JNZ instruction takes only 4 clock cycles if the zeroth condition is satisfied.
7. In the instruction set,
MOV CX, BA03H
WAIT: DEC CX
NOP
JNZ WAIT
RET
if the zeroth condition is not satisfied, then the JNZ instruction takes
a) 2 clock cycles
b) 8 clock cycles
c) 16 clock cycles
d) 64 clock cycles
Answer: c
Explanation: The JNZ instruction takes 16 clock cycles if the zeroth condition is not satisfied.
8. The maximum count value of 16-bit count register puts a limitation on
a) memory usage
b) storage of address of registers
c) to generate clock pulse
d) to generate maximum delay
Answer: d
Explanation: The maximum count value of 16-bit count register is FFFFH. This may put the
limitation on the maximum delay that can be generated using the instructions.
9. When large delays are required, then to serve the purpose
a) one or more count registers can be used
b) one or more shift registers can be used
c) one or more pointer registers can be used
d) one or more index registers can be used
Answer: a
Explanation: One or more count registers can be used to serve large delays.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Semiconductor Memory Interfacing”.
1. The semiconductor memories are organised as __________ dimension
of array of memory locations.
a) one dimensional
b) two dimensional
c) three dimensional
d) none
Answer: b
Explanation: The semiconductor memories are organised as two dimensions of an array which
consists of rows and columns.
2. If a location is selected, then all the bits in it are accessible using a group of conductors called
a) control bus
b) address bus
c) data bus
d) either address bus or data bus
Answer: c
Explanation: The bits in a selected location are accessible using data bus.
3. To address a memory location out of N memory locations, the number of address lines
required is
a) log N
tothebase2
b) log N
tothebase10
c) log N
tothebasee
d) log
2N
tothebasee
Answer: a
Explanation: For n memory locations, log n
tothebaseof2
address lines are required. For addressing 4K bytes of memory, 12 address lines are required
since log
4KB
=log
4∗1024
=log(2 12 )=12.
4. If the microprocessor has 10 address lines, then the number of memory locations it is able to
address is
a) 512
b) 1024
c) 2048
d) none
Answer: b
Explanation: Since for n address lines, the number of memory locations able to address is 2^n.
5. In static memory, the upper 8-bit bank of an available 16-bit memory chip is called
a) upper address memory bank
b) even address memory bank
c) static upper memory
d) odd address memory bank
Answer: d
Explanation: In static memory, the upper 8-bit bank is called odd address memory bank.
6. In static memory, the lower 8-bit bank of an available 16-bit memory chip is called
a) lower address memory bank
b) even address memory bank
c) static lower memory bank
d) odd address memory bank
Answer: b
Explanation: In static memory, the lower 8-bit bank is called even address memory bank.
7. In most of the cases, the method used for decoding that may be used to minimise the
required hardware is
a) absolute decoding
b) non-linear decoding
c) linear decoding
d) none
Answer: c
Explanation: In general, linear decoding is used to minimise the required hardware.
8. To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
a) parallel
b) serial
c) both serial and parallel
d) neither serial nor parallel
Answer: a
Explanation: The two 4K*8 chips of RAM and ROM are arranged in parallel.
9. If
addressline
Ao=0 then, the status of address and memory are
a) address is even and memory is in ROM
b) address is odd and memory is in ROM
c) address is even and memory is in RAM
d) address is odd and memory is in RAM
Answer: c
Explanation: If Ao=0 then address is even and is in RAM. If Ao=1 then, address is odd and is in
RAM.
10. If at a time Ao and BHE
activelow
both are zero then, the chip
selected will be
a) RAM
b) ROM
c) RAM and ROM
d) ONLY RAM
Answer: c
Explanation: If at a time Ao and BHE
activelow
both are zero, then both RAM and ROM are selected.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Dynamic RAM Interfacing”.
1. The advantage of dynamic RAM is
a) high packing density
b) low cost
c) less power consumption
d) all of the mentioned
Answer: d
Explanation: The dynamic RAM is advantageous than the static RAM as it has a higher packing
density, lower cost and less power consumption.
2. Whenever a large memory is required in a microcomputer system, the memory subsystem is
generally designed using
a) Static RAM
b) Dynamic RAM
c) Both static and dynamic RAM
d) ROM
Answer: b
Explanation: Dynamic RAM is preferred for large memory.
3. If a typical static RAM cell requires 6 transistors then corresponding dynamic RAM requires
a) 1 transistor along with capacitance
b) 2 transistors along with resistance
c) 3 transistors along with diode
d) 2 transistors along with capacitance
Answer: a
Explanation: The hardware complexity of dynamic RAM is lesser than that of static RAM.
4. To store the charge as a representation of data, the basic dynamic RAM cell uses
a) resistor
b) capacitor
c) diode
d) transistor
Answer: c
Explanation: The basic dynamic RAM cell uses capacitance to store the charge as a
representation of data. This capacitor is manufactured as a diode that is reverse biased so that
the storage capacitance is obtained.
5. The process of refreshing the data in the RAM to reduce the possibility of data loss is known
as
a) data cycle
b) regain cycle
c) retain cycle
d) refresh cycle
Answer: d
Explanation: The data storage in RAM which is capacitance
reverse−biaseddiode
may have a leakage current that tends to discharge the capacitor giving rise to possibility of
data loss. To avoid this, the data must be refreshed after a fixed time interval regularly.
6. The field in which dynamic RAM is more complicated than static RAM is
a) complexity
b) interfacing circuit
c) execution unit
d) cost
Answer: b
Explanation: The refresh mechanism and the additional hardware required makes the
interfacing circuit of dynamic RAM more complicated than that of static RAM.
7. Memory refresh activity is
a) initialised by processor
b) initialised by external bus master
c) initialised by refresh mechanism
d) initialised either by processor or by external bus
Answer: c
Explanation: The refresh operation is independent regular activity that is initialised and carried
out by the refresh mechanism.
8. The number of memory chips that are enabled at a time for refresh activity is
a) 2
b) 4
c) 8
d) more than 1
Answer: d
Explanation: More than one memory chip can be enabled at a time to refresh activity to reduce
the number of total memory refresh cycles.
9. A timer that derives pulse for refreshing action or time for which a dynamic RAM cell can hold
data charge level practically constant is
a) constant timer
b) data managing timer
c) refresh timer
d) qualitative timer
Answer: c
Explanation: Refresh timer derives a pulse for refreshing action after each refresh interval which
can be qualitatively defined as the time for which a dynamic RAM cell can hold data charge
level practically constant.
10. If ‘n’ denotes the number of rows that are to be refreshed in a single refresh interval, ‘td’
denotes the range of time it may take then, refresh time
tr
can be defined as
a) n*td
b) td/n
c) n/td
d) td n
Answer: b
Explanation: Refresh time is the ratio of time duration taken for refreshing to the number of rows
that are refreshed. Refresh frequency is the reciprocal of refresh time.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interfacing I/O Ports”.
1. The device that enables the microprocessor to read data from the external devices is
a) printer
b) joystick
c) display
d) reader
Answer: b
Explanation: Since joystick is an input device, it reads data from the external devices.
2. The example of output device is
a) CRT display
b) 7-segment display
c) Printer
d) All of the mentioned
Answer: d
Explanation: The output device transfers data from the microprocessor to the external devices.
3. The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read
Answer: c
Explanation: The input activity is similar to read operation and the output activity is similar to
write operation.
4. The operation, IOWR
activelow
performs
a) write operation on input data
b) write operation on output data
c) read operation on input data
d) read operation on output data
Answer: b
Explanation: IOWR
activelow
operation means writing data to an output device and not an input device.
5. The latch or IC 74LS373 acts as
a) good input port
b) bad input port
c) good output port
d) bad output port
Answer: c
Explanation: If the output port is to source large currents, the port lines must be buffered. So,
the latch is used as it acts as a good output port.
6. While performing read operation, one must take care that much current should not be
a) sourced from data lines
b) sinked from data lines
c) sourced or sinked from data lines
d) sinked from address lines
Answer: c
Explanation: More current should not be sourced or sinked from data lines while reading to
avoid loading.
7. To avoid loading during read operation, the device used is
a) latch
b) flipflop
c) buffer
d) tristate buffer
Answer: d
Explanation: A tristate buffer is used as an input device to overcome loading.
8. The chip 74LS245 is
a) bidirectional buffer
b) 8-bit input port
c) one that has 8 buffers
d) all of the mentioned
Answer: d
Explanation: The chip 74LS245 is a bidirectional buffer that contains 8 buffers and may be used
as an 8-bit input port. But while using as an input device, only one direction is useful.
9. In 74LS245, if DIR is 1, then the direction is from
a) inputs to outputs
b) outputs to inputs
c) source to sink
d) sink to source
Answer: a
Explanation: If DIR is 1, then the direction is from A
inputs
to B
outputs
.
10. In memory-mapped scheme, the devices are viewed as
a) distinct I/O devices
b) memory locations
c) only input devices
d) only output devices
Answer: b
Explanation: In memory-mapped scheme, the devices are viewed as memory locations and are
addressed likewise.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “PIO 8255
ProgrammableInput–OutputPort
”.
1. Programmable peripheral input-output port is another name for
a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port
Answer: b
Explanation: The parallel input-output port chip 8255 is also known as programmable peripheral
input-output port.
2. Port C of 8255 can function independently as
a) input port
b) output port
c) either input or output ports
d) both input and output ports
Answer: c
Explanation: Port C can function independently either as input or as output ports.
3. All the functions of the ports of 8255 are achieved by programming the bits of an internal
register called
a) data bus control
b) read logic control
c) control word register
d) none of the mentioned
Answer: c
Explanation: By programming the bits of control word register, the operations of the ports are
specified.
4. The data bus buffer is controlled by
a) control word register
b) read/write control logic
c) data bus
d) none of the mentioned
Answer: b
Explanation: The data bus buffer is controlled by read/write control logic.
5. The input provided by the microprocessor to the read/write control logic is
a) RESET
b) A1
c) WR
ACTIVELOW
d) All of the mentioned
Answer: d
Explanation: RD
ACTIVELOW
, WR
ACTIVELOW
, A1, A0, RESET are the inputs provided by the microprocessor to the read/write control logic of
8255.
6. The device that receives or transmits data upon the execution of input or output instructions
by the microprocessor is
a) control word register
b) read/write control logic
c) 3-state bidirectional buffer
d) none of the mentioned
Answer: c
Explanation: 3-state bidirectional buffer is used to receives or transmits data upon the execution
of input or output instructions by the microprocessor.
7. The port that is used for the generation of handshake lines in mode 1 or mode 2 is
a) port A
b) port B
c) port C Lower
d) port C Upper
Answer: d
Explanation: Port C upper is used for the generation of handshake lines in mode 1 or mode 2.
8. If A1=0, A0=1 then the input read cycle is performed from
a) port A to data bus
b) port B to data bus
c) port C to data bus
d) CWR to data bus
Answer: b
Explanation: If A1=0, A0=1 then the input read cycle is performed from port B to data bus.
9. The function, ‘data bus tristated’ is performed when
a) CS
activelow
=1
b) CS
activelow
=0
c) CS
activelow
= 0, RD
activelow
= 1, WR
activelow
=1
d) CS
activelow
= 1 OR CS
activelow
= 0, RD
activelow
= 1, WR
activelow
=1
Answer: d
Explanation: The data bus is tristated when chip select pin=1 or chip select pin=0 and read and
write signals are high i.e 1.
10. The pin that clears the control word register of 8255 when enabled is
a) CLEAR
b) SET
c) RESET
d) CLK
Answer: c
Explanation: If reset pin is enabled then the control word register is cleared.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Modes of Operation of 8255”.
1. In the I/O mode, the 8255 ports work as
a) reset pins
b) set pins
c) programmable I/O ports
d) only output ports
Answer: c
Explanation: In the I/O mode, the 8255 ports work as programmable I/O ports.
2. In BSR mode, only port C can be used to
a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports
Answer: c
Explanation: In BSR
BitSet−Reset
Mode, port C can be used to set and reset its individual port bits.
3. The feature of mode 0 is
a) any port can be used as input or output
b) output ports are latched
c) maximum of 4 ports are available
d) all of the mentioned
Answer: d
Explanation: In mode 0, any port can be used as input or output and output ports are latched.
4. The strobed input/output mode is another name of
a) mode 0
b) mode 1
c) mode 2
d) none
Answer: b
Explanation: In this mode, the handshaking signals control the input or output action of the
specified port.
5. If the value of the pin STB
StrobeInput
falls to low level, then
a) input port is loaded into input latches
b) input port is loaded into output latches
c) output port is loaded into input latches
d) output port is loaded into output latches
Answer: a
Explanation: If the value of the pin STB
StrobeInput
falls to low level, the input port is loaded into input latches.
6. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of
a) Control word register
b) CPU
c) Printer
d) Ports
Answer: c
Explanation: This signal indicates that the printer is selected.
7. The pulse width of the signal INIT at the receiving terminal must be more than
a) 10 microseconds
b) 20 microseconds
c) 40 microseconds
d) 50 microseconds
Answer: d
Explanation: The pulse width of the signal must be more than 50microseconds at the receiving
terminal.
8. The level of the signal ERROR
activelow
becomes ‘low’ when the printer is in
a) Paper end state
b) Offline state
c) Error state
d) All of the mentioned
Answer: d
Explanation: The level of the signal ERROR
activelow
becomes ‘low’ when the printer is in the Paper end state, Offline state and Error state.
9. The signals that are provided to maintain proper data flow and synchronization between the
data transmitter and receiver are
a) handshaking signals
b) control signals
c) input signals
d) none
Answer: a
Explanation: Handshaking signals maintain proper data flow and synchronization.
10. The feature of mode 2 of 8255 is
a) single 8-bit port is available
b) both inputs and outputs are latched
c) port C is used for generating handshake signals
d) all of the mentioned
Answer: d
Explanation: In mode 2 of 8255, a single 8-bit port is available i.e group A.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Puzzles focuses on “Interfacing Analog to Digital Data Converters”.
1. The time taken by the ADC from the active edge of SOC
startofconversion
pulse till the active edge of EOC
endofconversion
signal is called
a) edge time
b) conversion time
c) conversion delay
d) time delay
Answer: c
Explanation: Broadly speaking, the time taken by the converter to calculate the equivalent digital
data output from the moment of the start of conversion is called conversion delay.
2. The popular technique that is used in the integration of ADC chips is
a) successive approximation
b) dual slope integration
c) successive approximation and dual slope integration
d) none
Answer: c
Explanation: Successive approximation and dual slope integration are the most popular
techniques that are used in the integrated ADC chips.
3. The procedure of algorithm for interfacing ADC contain
a) ensuring stability of analog input
b) issuing start of conversion pulse to ADC
c) reading digital data output of ADC as equivalent digital output
d) all of the mentioned
Answer: d
Explanation: The general algorithm for interfacing ADC contains ensuring the stability of analog
input, issuing start of conversion pulse to ADC, reading end of conversion signal to mark the
end of a conversion process, reading digital data output of ADC as equivalent digital output.
4. Which is the ADC among the following?
a) AD 7523
b) 74373
c) 74245
d) ICL7109
Answer: d
Explanation: AD 7523 is a DAC
Digitaltoanalogconverter
, 74373 is a latch, 74245 is transceiver and ICL7109 is an ADC.
5. The conversion delay in a successive approximation of an ADC 0808/0809 is
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 milliseconds
Answer: b
Explanation: The conversion delay is 100microseconds which is low as compared to other
converters.
6. The number of inputs that can be connected at a time to an ADC that is integrated with
successive approximation is
a) 4
b) 2
c) 8
d) 16
Answer: c
Explanation: As these converters internally have 3:8 analog multiplexer, at a time 8 different
analog inputs can be connected to the chip.
7. ADC 7109 integrated by Dual slope integration technique is used for
a) low cost option
b) slow practical applications
c) low complexity
d) all of the mentioned
Answer: d
Explanation: Compared to other 12-bit ADCs, it is of very low cost and useful for slow practical
applications.
8. Which of the following is not one of the phases of the total conversion cycle?
a) autozero phase
b) conversion phase
c) signal integrate phase
d) disintegrate phase
Answer: b
Explanation: Autozero phase, signal integrate phase and disintegrate phase are the three
phases of total conversion cycle.
9. Which of the following phase contain feedback loop in it?
a) autozero phase
b) signal integrate phase
c) disintegrate phase
d) none
Answer: a
Explanation: A feedback loop is closed around the system to charge the autozero capacitor to
compensate for the offset voltages in the buffer amplifier, integrator and comparator.
10. In the signal integrate phase, the differential input voltage between IN LO
inputlow
and IN HI
inputhigh
pins is integrated by the internal integrator for a fixed period of
a) 256 clock cycles
b) 1024 clock cycles
c) 2048 clock cycles
d) 4096 clock cycles
Answer: c
Explanation: The internal integrator needs 2048 clock cycles to integrate voltage difference
between input low and input high.
To practice all Puzzles on Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Questions and Answers for Experienced people focuses on
“Interfacing Digital to Analog Converters, Stepper Motor Interfacing and Control of High Power
Devices Using 8255”.
1. DAC
DigitaltoAnalogConverter
finds application in
a) digitally controlled gains
b) motor speed controls
c) programmable gain amplifiers
d) all of the mentioned
Answer: d
Explanation: DAC is used in digitally controlled gains, motor speed controls and programmable
gain amplifiers.
2. To save the DAC from negative transients the device connected between OUT1 and OUT2 of
AD 7523 is
a) p-n junction diode
b) Zener
c) FET
d) BJT
BipolarJunctiontransistor
Answer: b
Explanation: Zener is connected between OUT1 and OUT2 pins of AD7523 to save from
negative transients.
3. An operational amplifier connected to the output of AD 7523 is used
a) to convert current output to output voltage
b) to provide additional driving capability
c) as current-to-voltage converter
d) all of the mentioned
Answer: d
Explanation: An operational amplifier is used as a current-to-voltage converter to convert the
current output to output voltage and also provides additional driving capability to the DAC.
4. The DAC 0800 has a settling time of
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 microseconds
Answer: a
Explanation: DAC 0800 has a settling time of 100 milliseconds.
5. The device that is used to obtain an accurate position control of rotating shafts in terms of
steps is
a) DC motor
b) AC motor
c) Stepper motor
d) Servo motor
Answer: c
Explanation: Stepper motor employs rotation of its shaft in terms of steps, rather than
continuous rotation as in case of AC or DC motors.
6. The internal schematic of a typical stepper motor has
a) 1 winding
b) 2 windings
c) 3 windings
d) 4 windings
Answer: d
Explanation: The internal schematic of a typical stepper motor has 4 windings.
7. The number of pulses required for one complete rotation of the shaft of the stepper motor is
equal to the
a) number of internal teeth on a rotor
b) number of internal teeth on a stator
c) number of internal teeth on a rotor and stator
d) number of external teeth on a stator
Answer: a
Explanation: The number of pulses required for one complete rotation of the shaft of the stepper
motor is equal to the number of internal teeth on its rotor.
8. A simple scheme for rotating the shaft of a stepper motor is called
a) rotating scheme
b) shaft scheme
c) wave scheme
d) none
Answer: c
Explanation: In this scheme, the windings are applied with the required voltage pulses, in a
cyclic fashion.
9. The firing angles of thyristors are controlled by
a) pulse generating circuits
b) relaxation oscillators
c) microprocessor
d) all of the mentioned
Answer: d
Explanation: In early days, the firing angles were controlled by a pulse generating circuits like
relaxation oscillators and now, they are accurately fired using a microprocessor.
10. The Isolation transformers are generally used for
a) protecting low power circuit
b) isolation
c) protecting low power circuit and isolation
d) none
Answer: c
Explanation: Any switching component of a high power circuit may be sufficient to damage the
microprocessor system. So, to protect the low power circuit isolation transformers are used.
They are also used if isolation is necessary.
To practice all areas of Microprocessors for Experienced people, here is complete set of 1000+
Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Programmable Interval Timer 8254”.
1. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: There are three counters that can be used as either counters or delay generators.
2. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
Answer: b
Explanation: The control word register can only be written and cannot be read.
3. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3
Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.
4. In mode 2, if N is loaded as the count value, then after
N−1
cycles, the output becomes low for
a) 1 clockcycle
b) 2 clockcycles
c) 3 clockcycles
d) 4 clockcycles
Answer: a
Explanation: After
N−1
cycles, the output becomes low for only 1 clockcycle. If the count N is reloaded and again the
output becomes high and remains so for
N−1
clock pulses.
5. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Answer: c
Explanation: When the count N loaded is even, then for half of the count, the output remains
high and for the remaining half it remains low. If the count loaded is odd, the first clock pulse
decrements it by 1 resulting in an even count value.
6. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
Answer: b
Explanation: SC denotes select counter.
7. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.
8. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is BCD count.
9. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.
10. The control word register contents are used for
a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes
mode0−mode4
ii) selection of counters
counter0−counter2
iii) choosing binary or BCD counters
iv) loading of the counter registers.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Programmable Interrupt Controller 8259A”.
1. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7
Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these five, four pins
were alloted fixed vector addresses but the pin INTR was not alloted by vector address, rather
an external device was supposed to hand over the type of the interrupt to the microprocessor.
2. The register that stores all the interrupt requests in it in order to serve them one by one on a
priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request Register
internally.
3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR
InterruptRequestRegister
at the direction of the Priority Resolver.
4. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
Answer: d
Explanation: The interrupt control logic performs all the operations that are involved within the
interrupts like accepting and managing interrupt acknowledge signals, interrupts.
5. In a cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64 vectored
interrupts can be provided.
6. When the PS
activelow
/EN
activelow
pin of 8259A used in buffered mode, then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a buffer enable to
control buffer transreceivers. If it is not used in buffered mode, then the pin is used as input to
designate whether the chip is used as a master or a slave.
7. Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
Answer: d
Explanation: The initialization procedure involves
i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.
8. When non-specific EOI command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will automatically reset the
highest ISR.
9. In the application where all the interrupting devices are of equal priority, the mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
Answer: a
Explanation: The automatic rotation is used in the applications where all the interrupting devices
are of equal priority.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “the Keyboard/Display Controller 8279”.
1. The registers that store the keyboard and display modes and operations programmed by
CPU are
a) I/O control and data buffers
b) Control and timing registers
c) Return buffers
d) Display address registers
Answer: b
Explanation: The control and timing register to store the keyboard and display modes and other
operations programmed by CPU.
2. The sensor RAM acts as 8-byte first-in-first-out RAM in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
Answer: c
Explanation: In this mode, each key code of the pressed key is entered in the order of the entry,
and in the meantime, read by the CPU, till the RAM becomes empty.
3. The registers that hold the address of the word currently being written by the CPU from the
display RAM are
a) control and timing register
b) control and timing register and timing control
c) display RAM
d) display address registers
Answer: d
Explanation: The display address registers holds the address of the word currently being written
or read by the CPU to or from the display RAM.
4. When a key is pressed, a debounce logic comes into operation in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Answer: c
Explanation: In scanned keyboard mode with 2 key lockout mode of operation, when a key is
pressed, a debounce logic comes into operation. During the next two scans, other keys are
checked for closure and if no other key is pressed then the first pressed key is identified.
5. The mode that is programmed using “end interrupt/error mode set command” is
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Answer: a
Explanation: The scanned keyboard special error mode is programmed using end interrupt/error
mode set command. This mode is valid only under the N-key rollover mode.
6. When a key is pressed, the debounce circuit waits for 2 keyboard scans and then checks
whether the key is still depressed in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Answer: b
Explanation: In this mode, When a key is pressed, the debounce circuit waits for 2 keyboard
scans and then checks whether the key is still depressed. If it is still depressed, the code is
entered in FIFO RAM.
7. The data that is entered from the left side of the display unit is of
a) left entry mode
b) right entry mode
c) left and right entry modes
d) none
Answer: a
Explanation: The data that is entered from the left side of the display unit is of left entry mode,
as in a type-writer the first character typed appears at the left-most position, while the
subsequent characters appear successively to the right of the first one.
8. The FIFO status word is used to indicate the error in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
Answer: c
Explanation: Overrun error occurs when an already full FIFO has attempted an entry. Underrun
error occurs when an empty FIFO read is attempted.
9. The flag that increments automatically after each read or write operation to the display RAM
is
a) IF
b) RF
c) AI
d) WF
Answer: c
Explanation: AI refers to auto increment flag.
10. If any change in sensor value is detected at the end of a sensor matrix scan, then the IRQ
line
a) goes low
b) goes high
c) remains unchanged
d) none
Answer: b
Explanation: In sensor matrix mode, the IRQ line goes high, if any change in sensor value is
detected at the end of a sensor matrix scan or the sensor RAM has a previous entry to be read
by the CPU.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Programmable Communication Interface 8251 USART”.
1. Which of the following is not a mode of data transmission?
a) simplex
b) duplex
c) semi duplex
d) half duplex
Answer: c
Explanation: Basically, there are three modes of data transmission. simplex, duplex and half
duplex.
2. If the data is transmitted only in one direction over a single communication channel, then it is
of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: a
Explanation: In simplex mode, the data transmission is unidirectional. For example, a CPU may
transmit data for a CRT display unit in this mode.
3. If the data transmission takes place in either direction, but at a time data may be transmitted
only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: d
Explanation: In half duplex mode, data transmission is bidirectional but not at a time. For
example, Walkie-Talkie.
4. In 8251A, the pin that controls the rate at which the character is to be transmitted is
a) TXC
activelow
b) TXC
activehigh
c) TXD
activelow
d) RXC
activelow
Answer: a
Explanation: Transmitter Clock Input
TXC(activelow
) is a pin that controls the rate at which the character is to be transmitted.
5. TXD
TransmittedDataOutput
pin carries serial stream of the transmitted data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned
Answer: d
Explanation: Transmitted Data Output pin carries a serial stream of the transmitted data bits
along with other information like start bits, stop bits and parity bits etc.
6. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY
Transmitterready
b) RXRDY
Receiverreadyoutput
c) DSR
activelow
d) DTR
activelow
Answer: b
Explanation: RXRDY
Receiverreadyoutput
may be used either to interrupt the CPU or polled by the CPU.
7. The disadvantage of RS-232C is
a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned
Answer: d
Explanation: RS232C has been used for long and has a few disadvantages like limited speed of
communication, high-voltage level signaling and big-size communication adapters.
8. The USB supports the signaling rate of
a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned
Answer: d
Explanation: The USB standards support the signaling rates. Also, USB signaling is
implemented in a differential in low- and full-speed options.
9. The bit packet that commands the device either to receive data or transmit data in
transmission of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
Answer: b
Explanation: The token packet is the second type of packet which commands the device either
to receive data or transmit data.
10. High speed USB devices neglect
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
Answer: c
Explanation: PRE packets are only of importance to low-speed USB devices.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “DMA Controller 8257”.
1. In direct memory access mode, the data transfer takes place
a) directly
b) indirectly
c) directly and indirectly
d) none of the mentioned
Answer: a
Explanation: In direct memory access mode, the data may transfer directly without the
interference from the CPU.
2. In 8257
DMA
, each of the four channels has
a) a pair of two 8-bit registers
b) a pair of two 16-bit registers
c) one 16-bit register
d) one 8-bit register
Answer: b
Explanation: The DMA supports four channels, and each of the channels has a pair of two 16-bit
registers, namely DMA address register and a terminal count register.
3. The common register
for all the four channels of 8257 is
a) DMA address register
b) Terminal count register
c) Mode set register and status register
d) None of the mentioned
Answer: c
Explanation: The two common registers for all the four channels of DMA are mode set register
and status register.
4. In 8257 register format, the selected channel is disabled after the terminal count condition is
reached when
a) Auto load is set
b) Auto load is reset
c) TC STOP bit is reset
d) TC STOP bit is set
Answer: d
Explanation: If the TC STOP bit is set, the selected channel is disabled after the terminal count
condition is reached, and it further prevents any DMA cycle on the channel.
5. The IOR
activelow
input line acts as output in
a) slave mode
b) master mode
c) master and slave mode
d) none of the mentioned
Answer: b
Explanation: The IOR
activelow
is an active low bidirectional tristate input line, that acts as input in the slave mode, and acts as
output in the master mode. In master mode, this signal is used to read data from a peripheral
during a memory write cycle.
6. The IOW
activelow
in its slave mode loads the contents of a data bus to
a) 8-bit mode register
b) upper/lower byte of 16-bit DMA address register
c) terminal count register
d) all of the mentioned
Answer: d
Explanation: In its slave mode, the IOW
activelow
loads the contents of a data bus to 8-bit mode register, upper/lower byte of 16-bit DMA address
register or terminal count register.
7. The pin that disables all the DMA channels by clearing the mode registers is
a) MARK
b) CLEAR
c) RESET
d) READY
Answer: c
Explanation: The RESET pin which is asynchronous input disables all the DMA channels by
clearing the mode registers, and tristate all the control lines.
8. The pin that requests the access of the system bus is
a) HLDA
b) HRQ
c) ADSTB
d) None of the mentioned
Answer: b
Explanation: The hold request output requests the access of the system bus.
9. The pin that is used to write data to the addressed memory location, during DMA write
operation is
a) MEMR
activelow
b) AEN
c) MEMW
activelow
d) IOW
activelow
Answer: c
Explanation: The MEMW
activelow
is used to write data to the addressed memory location, during DMA write operation.
10. The pin that strobes the higher byte of the memory address, generated by the DMA
controller into the latches is
a) AEN
b) ADSTB
c) TC
d) None of the mentioned
Answer: b
Explanation: The pin ADSTB strobes the higher byte of the memory address, generated by the
DMA controller into the latches.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “DMA Transfers and Operations”.
1. The 8257 is able to accomplish the operation of
a) verifying DMA operation
b) write operation
c) read operation
d) all of the mentioned
Answer: d
Explanation: The 8257 can accomplish three types of operations and they are
i) verify DMA operation
ii) write operation
iii) read operation.
2. The bus is available when the DMA controller receives the signal
a) HRQ
b) HLDA
c) DACK
d) All of the mentioned
Answer: b
Explanation: If the HLDA signal is received by the DMA controller, it indicates that the bus is
available.
3. To indicate the I/O device that its request for the DMA transfer has been honored by the CPU,
the DMA controller pulls
a) HLDA signal
b) HRQ signal
c) DACK
activelow
d) DACK
activehigh
Answer: c
Explanation: The DACK
activelow
line of the used channel is pulled down by the DMA controller to indicate the I/O device that its
request for the DMA transfer has been honored by the CPU.
4. If more than one channel requests service simultaneously, the transfer will occur as
a) multi transfer
b) simultaneous transfer
c) burst transfer
d) none of the mentioned
Answer: c
Explanation: If more than one channel requests service simultaneously, then the transfer occurs
as a burst or continuous transfer.
5. The continuous transfer may be interrupted by an external device by pulling down the signal
a) HRQ
b) DACK
activelow
c) DACK
activehigh
d) HLDA
Answer: d
Explanation: The burst or continuous transfer may be interrupted by an external device by
pulling down the HLDA line.
6. The number of clock cycles required for an 8257 to complete a transfer is
a) 2
b) 4
c) 8
d) none of the mentioned
Answer: b
Explanation: The 8257 uses four clock cycles to complete a transfer.
7. In 8257, if each device connected to a channel is assigned to a fixed priority then it is said to
be in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned
Answer: b
Explanation: In this scheme, the DRQ3 has the lowest priority followed by DRQ2 and DRQ1.
The DRQ0 has the highest priority.
8. The priority of the channels varies frequently in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned
Answer: a
Explanation: In this scheme, the priorities assigned to the channels are not fixed.
9. The register of 8257 that can only be written in is
a) DMA address register
b) Terminal count register
c) Mode set register
d) Status register
Answer: c
Explanation: The selected register may be read or written depending on the instruction executed
by the CPU. But only write operation can be performed on the mode set register.
10. The operation that can be performed on the status register is
a) write operation
b) read operation
c) read and write operations
d) none of the mentioned
Answer: b
Explanation: The status register can only be read.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Programmable DMA Interface 8237 -1”.
1. The block of 8237 that decodes the various commands given to the 8237 by the CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: b
Explanation: The program control block decodes various commands given to the 8237 by the
CPU before servicing a DMA request.
2. The priority between the DMA channels requesting the services can be resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: c
Explanation: The priority encoder block resolves the priority between the DMA channels
requesting the services.
3. The register that holds the current memory address is
a) current word register
b) current address register
c) base address register
d) command register
Answer: b
Explanation: The current address register holds the current memory address. The current
address register is accessed during the DMA transfer.
4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register
Answer: a
Explanation: The current word register is a 16-bit register that holds the data transfers. The
word count is decremented after each transfer, and the new value is stored again in the register.
5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP
endofprocess
is generated
d) Start of process is generated
Answer: c
Explanation: When the count becomes zero, the EOP signal is generated. This can be written in
successive bytes by the CPU, in program mode.
6. The current address register is programmed by the CPU as
a) bit-wise
b) byte-wise
c) bit-wise and byte-wise
d) none of the mentioned
Answer: b
Explanation: The current address register is byte-wise programmed by the CPU, i.e. lower byte
first and the higher byte later.
7. Which of these register’s contents is used for auto-initialization
internally
a) current word register
b) current address register
c) base address register
d) command register
Answer: c
Explanation: The contents of base address register cannot be read by the CPU. These contents
are used internally for auto-initialization.
8. The register that maintains an original copy of the respective initial current address register
and current word register is
a) mode register
b) base address register
c) command register
d) mask register
Answer: b
Explanation: The base address register maintains an original copy of the current address
register and current word register, before incrementing or decrementing.
9. The register that can be automatically incremented or decremented, after each DMA transfer
is
a) mask register
b) mode register
c) command register
d) current address register
Answer: d
Explanation: The address is automatically incremented or decremented after each DMA
transfer, and the resulting address value is again stored in the current address register.
10. Which of the following is a type of DMA transfer?
a) memory read
b) memory write
c) verify transfer
d) all of the mentioned
Answer: d
Explanation: Memory read, memory write and verify transfer are the three types of DMA
transfer.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Question Paper focuses on “Programmable DMA Interface 8237
-2”.
1. Each bit in the request register is cleared by
a) under program control
b) generation of TC
c) generation of an external EOP
d) all of the mentioned
Answer: d
Explanation: In the request register, each bit is set or reset under program control or is cleared
upon generation of a TC or an external EOP.
2. The register that holds the data during memory to memory data transfer is
a) mode register
b) temporary register
c) command register
d) mask register
Answer: b
Explanation: The temporary register holds the data during memory to memory data transfers.
After the completion of the transfer operation, the last word transferred remains in the temporary
register, until it is cleared by a reset operation.
3. The register that keeps track of all the DMA channel pending requests and status of their
terminal counts is
a) mask register
b) request register
c) status register
d) count register
Answer: c
Explanation: The status register keeps track of all the DMA channel pending requests, and
status of their terminal counts. These are cleared upon reset.
4. The pin that clears the command, request and temporary registers, and internal first/last
flipflop when it is set is
a) CLEAR
b) SET
c) HLDA
d) RESET
Answer: d
Explanation: A high on the reset pin clears the command, status, request and temporary
registers, and also clears the internal first/last flipflop.
5. The DMA request input pin that has the highest priority is
a) DREQ0
b) DREQ1
c) DREQ2
d) DREQ3
Answer: a
Explanation: DREQ0 has the highest priority while DREQ3 has the lowest one. The priorities of
the DREQ lines is programmable.
6. When interface 8237 does not have any valid pending DMA request then it is said to be in
a) active state
b) passive state
c) idle state
d) none of the mentioned
Answer: c
Explanation: If 8237 is in idle state, then CPU may program it in this state.
7. To complete a DMA transfer, a memory to memory transfer requires
a) a read from memory cycle
b) a write to memory cycle
c) a read-from and write-to memory cycle
d) none of the mentioned
Answer: c
Explanation: A memory to memory transfer is a two cycle operation and requires a read from
and write-to memory cycle, to complete each DMA transfer.
8. In demand transfer mode of 8237, the device stops data transfer when
a) a TC
terminalcount
is reached
b) an external EOP
activelow
is detected
c) the DREQ signal goes inactive
d) all of the mentioned
Answer: d
Explanation: In demand transfer mode, the device continues transfers till a TC is reached or an
external EOP is detected or the DREQ signal goes inactive.
9. The mode of 8237 in which the device transfers only one byte per request is
a) block transfer mode
b) single transfer mode
c) demand transfer mode
d) cascade mode
Answer: b
Explanation: In single mode, the device transfers only one byte per request. For each transfer,
the DREQ must be active until the DACK is activated.
10. The transfer of a block of data from one set of memory address to another takes place in
a) block transfer mode
b) demand transfer mode
c) memory to memory transfer mode
d) cascade mode
Answer: c
Explanation: To perform the transfer of a block of data from one set of a memory address to
another one, this transfer mode is used.
11. Which of the following command is used to make all the internal registers of 8237 clear?
a) clear first/last flipflop
b) master clear command
c) clear mask register
d) none of the mentioned
Answer: b
Explanation: Using master clear command, all the internal registers of 8237 are cleared, while
all the bits of the mask register are set.
To practice all questions papers on Microprocessors, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “High Storage Capacity Memory Devices”.
1. The basic principle of floppy disks involve
a) magnetic data reading
b) magnetic data recording
c) magnetic data recording and reading
d) none of the mentioned
Answer: c
Explanation: Whatever their physical sizes and storage formats, all the floppies incorporate the
basic principles of magnetic data recording and reading.
2. In floppy disk, the small hole that enables the drive to identify the beginning of a track and its
first sector is
a) inner hole
b) key hole
c) index hole
d) start hole
Answer: c
Explanation: The small hole called index hole, enables the drive to identify the beginning of a
track and its first sector.
3. Inside its jacket, the floppy media is rotated at the speed of
a) 200 RPM
b) 300 RPM
c) 150 RPM
d) 50 RPM
Answer: b
Explanation: The floppy media is rotated at the speed of 300 RPM
RevolutionPerMinute
inside its jacket.
4. The Double Density Double Sided disks on each side are organized with
a) 20 tracks
b) 30 tracks
c) 40 tracks
d) 50 tracks
Answer: c
Explanation: The Double Density Double Sided
DDDS
disks are organized with 40 tracks on each side of the disk.
5. The magnetic recording technique used for storing data onto the disks
floppydisks
is called
a) return to zero
b) non-return to zero
c) return to zero and Non-return to zero
d) none of the mentioned
Answer: b
Explanation: In this technique, the magnetic flux on the disk surface never returns to zero, i.e.
no erase operation is carried out.
6. For reading the disks DVD uses
a) blue laser
b) white laser
c) red laser
d) green laser
Answer: c
Explanation: A DVD is an optical disk that uses a red laser for reading the disks.
7. For reading the disks, the blue ray disk uses
a) high frequency red laser
b) low frequency red laser
c) high frequency blue laser
d) low frequency blue laser
Answer: c
Explanation: The blue ray disk uses a high frequency blue laser with a small wavelength to read
the disk.
8. A blue ray disk can store data upto _________ per layer.
a) 25 KB
b) 25 MB
c) 25 TB
d) 25 GB
Answer: d
Explanation: A blue ray disk can store data upto 25 GB per layer and is popularly used for
storing long duration videos like movies.
9. DVDRW is for
a) read-write DVD
b) rewriteable DVD
c) recordable DVD
d) none of the mentioned
Answer: b
Explanation: DVDRW is for rewriteable DVD and DVDR is for recordable DVD.
10. The HDD is also called as
a) hard disk
b) hard drive
c) fixed disk
d) all of the mentioned
Answer: d
Explanation: The Hard Disk Drive is also called as a hard disk, hard drive, fixed drive, fixed disk
or fixed disk drive.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interconnection Topologies”.
1. The memory of a microprocessor serves as
a) storage of individual instructions
b) temporary storage for the data
c) storing common instructions or data for all processors
d) all of the mentioned
Answer: d
Explanation: The memory serves the microprocessor in the same way, whether it is a single
microprocessor or a multi microprocessor.
2. In shared bus architecture, the required processor
to perform a bus cycle, for fetching data or instructions is
a) one processor
b) two processors
c) more than two processors
d) none of the mentioned
Answer: a
Explanation: In a shared bus architecture, only one processor performs bus cycle to fetch
instructions or data from the memory.
3. In multiport memory configuration, the processor
that address the multiport memory is
are
a) 1
b) 2
c) 3
d) many
Answer: b
Explanation: The processors P1 and P2 address a multiport memory, which can be accessed at
a time by both the processors.
4. The memory space of a processor that is mapped to other processor/processors and
vice-versa is known as
a) multi microprocessor system
b) memory technique
c) bus window technique
d) mapping technique
Answer: c
Explanation: The bus window technique is the correct method of interconnection between the
processors.
5. The disadvantage of the bus window technique is
a) both processors must know about bus window
b) both processors must know the address map
c) loss of effective local memory space
d) all of the mentioned
Answer: d
Explanation: The disadvantage of bus window technique is that both processors must know
implicitly about the existence of a bus window, its size and the address map. It also results in
loss of effective local memory space.
6. Bus switches are present in
a) bus window technique
b) crossbar switching
c) linked input/output
d) shared bus
Answer: b
Explanation: In crossbar switching type of interconnection topology, several parallel data paths
are possible. Each node of the crossbar represents a bus switch.
7. Which of the following is not a type of configuration that is based on physical interconnections
between the processors?
a) star configuration
b) loop configuration
c) regular topologies
d) incomplete interconnection
Answer: d
Explanation: Based on the physical interconnections between the processors, the configurations
are
i) star configuration
ii) loop or ring configuration
iii) complete interconnection
iv) regular topologies
v) irregular topologies.
8. The configuration, in which all the processing elements are connected to a central switching
element, that may be independent processor via dedicated paths is
a) star
b) loop
c) complete
d) irregular
Answer: a
Explanation: The switching element controls the interconnections between the processing
elements.
9. The configuration that is not suitable for a large number of processors is
a) star
b) loop
c) complete
d) regular
Answer: c
Explanation: For a large number of processors, the complete interconnection is impractical due
to a large number of interconnection paths.
10. The array processor architecture is an example of
a) star
b) loop
c) complete
d) regular
Answer: d
Explanation: In array processor architecture, the processing elements are arranged in a regular
fashion.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Software Aspects of Multimicroprocessor Systems”.
1. The interconnection topologies are implemented using _________ as a node.
a) control unit
b) microprocessor
c) processing unit
d) microprocessor or processing unit
Answer: d
Explanation: The microprocessors or processing unit is used as a node in interconnection
topologies. They may also work as stand-alone processors or subprocessing units, under the
control of other microprocessors or processing units.
2. The feature of the multi-microprocessor architecture is
a) task dependent
b) single bus provider for many processors
c) design is for a specific task
d) all of the mentioned
Answer: d
Explanation: The main feature of multi-microprocessor is that it is task dependent. If it is
designed for a specific task, then it may not be useful for other tasks.
3. The main objective in building the multi-microprocessor is
a) greater throughput
b) enhanced fault tolerance
c) greater throughput and enhanced fault tolerance
d) none of the mentioned
Answer: c
Explanation: Greater throughput and enhanced fault tolerance are the main objectives of the
multi-microprocessor system. These systems incorporate a multiplicity of hardware and
software, for the purpose.
4. An interface between the user or an application program, and the system resources are
a) microprocessor
b) microcontroller
c) multi-microprocessor
d) operating system
Answer: d
Explanation: The operating system acts as an interface, and is an important program that
resides in the computer memory.
5. An operating system provides
a) hardware and software resource management
b) input/output management
c) memory management
d) all of the mentioned
Answer: d
Explanation: An operating system provides a means of hardware and software resource
management including input/output and memory management.
6. Distributed systems are designed to run
a) serial process
b) parallel process
c) serial and parallel process
d) none of the mentioned
Answer: d
Explanation: Distributed systems are designed to run a parallel process. It is essential that a
proper environment exists for concurrent processes to communicate and cooperate, in order to
complete the allotted task.
7. A distributed operating system must provide a mechanism for
a) intraprocessor communication
b) intraprocess and intraprocessor communication
c) interprocess and interprocessor communication
d) interprocessor communication
Answer: c
Explanation: A distributed operating system must provide a mechanism for interprocess and
interprocessor communication.
8. A multiprocessor operating system should perform
a) a mechanism to split a task into concurrent subtasks
b) optimize the system performance
c) handling structural or architectural changes
d) all of the mentioned
Answer: d
Explanation: A multiprocessor operating system should have a mechanism to split a task,
optimise system performance, and should handle structural changes.
9. An operating system must possess
a) process-processor allocation strategies
b) mechanism to collect results of subtasks
c) software to improve overall performance
d) all of the mentioned
Answer: d
Explanation: An operating system must have process-processor allocation strategies, a
mechanism to collect results of subtasks and software to improve overall performance.
10. A multiprocessor operating system must take care of
a) authorized data access and data protection
b) unauthorized data access and data protection
c) authorized data access
d) data protection
Answer: b
Explanation: A multiprocessor operating system must take care of unauthorized data access
and data protection.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Numeric Processor 8087 -1”.
1. The unit that executes all the numeric processor instructions in 8087 is
a) Control unit
b) ALU
c) Numeric extension unit
d) None of the mentioned
Answer: c
Explanation: The 8087 is divided into two sections namely control unit and numeric extension
unit in which the numeric extension unit executes all the numeric processor instructions.
2. The unit that receives and decodes the instructions in 8087 is
a) Control unit
b) ALU
c) Numeric extension unit
d) None of the mentioned
Answer: a
Explanation: The control unit receives, decodes the instructions, and executes the 8087 control
instructions.
3. The control unit functions in
a) establishing communication between CPU and memory
b) coordinating the internal coprocessor execution
c) reads and writes memory operands
d) all of the mentioned
Answer: d
Explanation: The control unit is used for establishing communication between CPU and memory
and coordinating the internal coprocessor execution.
4. When the numeric extension unit
NEU
begins its execution, then the signal that is active is
a) BUSY
activehigh
b) BUSY
activelow
c) READY
activelow
d) RESET
activehigh
Answer: a
Explanation: When NEU begins its execution, the BUSY signal is pulled up. Also, this output
signal when high, indicates to the CPU that it is busy with the execution of an allotted
instruction.
5. The register that allows the register programmer to select the required processing options is
a) significant
b) exponent
c) control word register
d) none of the mentioned
Answer: c
Explanation: The control word register allows the register programmer to select the required
processing options out of available ones. It is used to control the operation of 8087.
6. Invalid operation is the exception generated due to
a) stack overflow
b) stack underflow
c) indeterminate form as result
d) all of the mentioned
Answer: d
Explanation: Invalid operation is generated due to stack overflow, stack underflow,
indeterminate form as result, or non-number
NAN
as operand.
7. The exception generated for a too big result to fit in the format is
a) invalid operation
b) overflow
c) denormalized operand
d) result overflow
Answer: b
Explanation: A too big result to fit in the format generates this exception. The condition code bits
indicate that the result is prohibitively large.
8. If the result is infinity, then the exception generated is
a) overflow
b) invalid operation
c) denormalized operand
d) zero divide
Answer: d
Explanation: If any non-zero finite operand is divided by zero, the zero divide exception is
generated. The resulting condition code bits indicate that the result is infinity, even if the
exception is masked.
9. To operate 8087 in maximum mode, the pin MN/MX
activelow
is
a) connected to Vcc or power supply
b) connected to ground
c) left unconnected
d) none of the mentioned
Answer: b
Explanation: The 8087 can operate in a maximum mode, only when the MN/MX
activelow
pin of the CPU is grounded. In maximum mode, all the control signals are derived using a
sequence chip known as a bus controller.
10. If the result is rounded according to the rounding control bits, then the exception generated
is
a) denormalized operand
b) underflow
c) inexact result
d) invalid operation
Answer: c
Explanation: If it is impossible to fit the actual result in the specified format, the result is rounded
according to the rounding control bits, and an exception is generated. This sets the precision
exception flag.
11. The instruction that stores a copy of top of the stack into the memory, and pops the top of
the stack is
a) FST
b) FSTP
c) FIST
d) FLD
Answer: b
Explanation: FSTP
storefloatingpointnumberandpop
stores a copy of top of the stack into memory or any coprocessor register, and then pops the
top of the stack.
12. The instruction that multiplies the content of the stack top by 2n is
a) FMUL
b) FPREM
c) FSCAL
d) FCSH
Answer: c
Explanation: FSCAL instruction multiplies the content of the stack top by 2n, where n is an
integral part of stack and stores the result in stack.
13. If the opcode bit is D=1, then the source and destination operands are
a) incremented
b) decremented
c) cleared
d) interchanged
Answer: d
Explanation: If D=1, then it interchanges the source and destination operands.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “I/O Processor 8089”.
1. The 8089 shares the system bus and memory with the host CPU in
a) tightly coupled configuration
b) loosely coupled configuration
c) tightly and loosely coupled configurations
d) none of the mentioned
Answer: a
Explanation: In a tightly coupled configuration, the 8089 shares the system bus and memory
with the host CPU using its RQ
activelow
or GT
activelow
pins.
2. The 8089 communicates with the host CPU using bus arbiter and controller in
a) tightly coupled configuration
b) loosely coupled configuration
c) tightly and loosely coupled configurations
d) none of the mentioned
Answer: b
Explanation: In a loosely coupled configuration, the 8089 has its own local bus and
communicates with the host CPU using bus arbiter and controller.
3. The number of address lines used by the I/O processor in 8089 is
a) 20
b) 12
c) 16
d) 8
Answer: c
Explanation: The 8089 I/O processor uses only 16 address lines, and thus it can address only
64KB of IO space.
4. The IO device that can be interfaced with 8089 is
a) 16-bit IO
b) 8-bit IO
c) 64-bit IO
d) 16-bit and 8-bit IO
Answer: d
Explanation: The 8089 handled IO devices need not have the same data bus width as that of
8089. This enables even 8-bit IO devices to be interfaced easily with 8089.
5. In the 8089 architecture, the address of memory table for channel-2 is calculated by
a) adding 16 to the contents of CCP
b) adding 8 to the contents of CCP
c) adding memory table address of channel-1
d) none of the mentioned
Answer: b
Explanation: The address of the memory table for channel-2 is calculated by adding 8 to the
contents of CCP or by adding memory table address for channel-1 to the contents of CCP.
6. Which of the following is not a general purpose register of 8089?
a) GA
b) BC
c) CX
d) MC
Answer: c
Explanation: The registers GA, GB, GC, BC, IX and MC can be used as general purpose
registers.
7. The registers that are used as source and destination pointers during DMA operations are
a) GB, GC
b) GC, BC
c) GC, GA
d) GA, GB
Answer: d
Explanation: GA register is used as source and GB as destination pointers during DMA
operations.
8. The pin that is used for data transfer control and operation termination signals is
a) SINTR
b) EXT
c) DRQ and EXT
d) RQ
activelow
or GT
activelow
Answer: c
Explanation: The DRQ and EXT are used for data transfer control and operation termination
signals during DMA operations.
9. The pin that is used to inform the CPU that the previous operation is completed is
a) RQ
activelow
b) GT
activelow
c) DRQ
d) SINTR
Answer: d
Explanation: The SINTR pins are used by the channels either to inform the CPU that the
previous operation is over or to ask for its attention or interference if required, before the
completion of the task.
10. The current channel status of program status word contains
a) source and destination address widths
b) bus load limit
c) interrupt control and servicing
d) all of the mentioned
Answer: d
Explanation: The program status word contains the current channel status, which contains
source and destination address widths, channel activity, interrupt control and servicing, bus load
limit and priority information.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Bus Arbitration and Control”.
1. Which of the following is an incorporated function to resolve interprocessor communication
problems?
a) bus allotment and control
b) bus arbitration
c) priority resolving
d) all of the mentioned
Answer: d
Explanation: To resolve the various bus contention and interprocessor communication problems,
different hardware strategies and algorithms are worked out. These incorporated functions like
bus allotment and control, bus arbitration and priority resolving into them.
2. The device that deals with the bus access control functions and bus handshake activities is
a) bus allotment controller
b) bus arbiter
c) priority resolver
d) none of the mentioned
Answer: b
Explanation: The bus arbiter or 8289 takes care of bus access control functions and bus
handshake activities.
3. The clock generator delays the READY signal until the signal _________ goes low
a) DEN
activehigh
b) DEN
activelow
c) AEN
activelow
d) AEN
activehigh
Answer: c
Explanation: If AEN
activelow
is high, the clock generator delays the READY signal till the AEN
activelow
goes low.
4. The bus controller relinquishes the bus if
a) READY
activelow
b) LOCK
activehigh
c) CBRQ
activelow
d) BPRO
activehigh
Answer: b
Explanation: The bus controller does not relinquish
releaseitscontrolon
the bus, till the LOCK
activelow
input is low.
5. The signals that are used by the bus arbitration in the independent request method is
a) BREQ
activelow
b) BPRN
activelow
c) CBRQ
activelow
d) All of the mentioned
Answer: d
Explanation: The four active low signals, bus request
BREQ
, bus priority in
BPRN
, common bus request
CBRQ
and bus priority out
BPRO
are used for bus arbitration.
6. The signal that is used to drive a priority resolving network that actually accepts the bus
request inputs is
a) BREQ
activelow
b) BPRN
activelow
c) CBRQ
activelow
d) BPRO
activelow
Answer: a
Explanation: The BREQ
activelow
is used to drive a priority resolving network that actually accepts the bus request inputs from all
the masters and derives the priority outputs which further drive the BPRN
activelow
inputs of all the masters.
7. Which of the following is the simplest and cheapest method of bus arbitration?
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned
Answer: a
Explanation: The daisy chaining method is the simplest one, as it has less hardware complexity.
8. The method of bus arbitration that does not contain priority resolving network in it is
a) daisy chaining
b) independent request
c) polling
d) none
Answer: a
Explanation: The daisy chaining method does not contain any priority resolving network, rather
the priorities of all the devices are essentially assumed to be in sequence.
9. Which of the following is the fastest method of bus arbitration?
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned
Answer: b
Explanation: The independent request scheme is quite fast because each of the masters can
independently communicate with the controller.
10. A set of address lines is driven by the controller in
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned
Answer: c
Explanation: In a polling scheme, a set of address lines is driven by the controller to address
each of the masters in sequence.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Tightly Coupled and Loosely Coupled Systems”.
1. The processors used in the multi-microprocessor are
a) coprocessors
b) independent processors
c) coprocessors or independent processors
d) none of the mentioned
Answer: c
Explanation: The processors used in the multi-microprocessor are either coprocessors or
independent processors.
2. The processor that executes the instructions fetched for it by the host processor is
a) microprocessor
b) coprocessor
c) independent processor
d) coprocessor and independent processor
Answer: b
Explanation: The coprocessor executes the instructions fetched for it by the host processor.
3. The processor that asks for bus access or may itself fetch the instructions and execute them
is
a) microprocessor
b) coprocessor
c) independent processor
d) coprocessor and independent processor
Answer: c
Explanation: The independent processor may ask for bus access, may fetch the instructions
itself, and execute them independently.
4. In tightly coupled systems, the microprocessors share
a) common clock
b) bus control logic
c) common clock and bus control logic
d) none of the mentioned
Answer: c
Explanation: The microprocessors share a common clock and bus control logic, in a tightly
coupled system.
5. Communication between processors using a common system bus and common memory
takes place in
a) loosely coupled system
b) tightly coupled system
c) tightly and loosely coupled system
d) none of the mentioned
Answer: b
Explanation: In tightly coupled systems, the two processors may communicate using a common
system bus or common memory.
6. The bus arbitration is handled by an external circuit in
a) loosely coupled system
b) tightly coupled system
c) tightly and loosely coupled system
d) none of the mentioned
Answer: a
Explanation: In a loosely coupled multiprocessor system, each CPU may have its own bus
control logic. The bus arbitration is handled by an external circuit, common to all the processors.
7. The loosely coupled system has an advantage of
a) more number of CPUs can be added
b) system structure is modular
c) more fault-tolerant and suitable for parallel applications
d) all of the mentioned
Answer: d
Explanation: The loosely coupled system is advantageous than the tightly coupled system as it
has advantages of more number of CPUs can be added to improve the system performance. A
fault in a single module does not lead to a complete system breakdown.
8. In a tightly coupled system, when a processor is using the bus then the local bus of other
processors is in
a) hold state
b) high impedance state
c) halt state
d) low impedance state
Answer: b
Explanation: When a processor is using the bus then the other processors maintain their local
buses in high impedance state.
9. The disadvantage of the loosely coupled system is
a) complex due to additional hardware
b) less portable
c) more expensive
d) all of the mentioned
Answer: d
Explanation: The loosely coupled systems are more complicated due to the required additional
communication hardware. They are less portable and more expensive due to additional
hardware.
10. To indicate the completion of task allocated in a closely
tightly
coupled system, the microprocessor uses
a) status bit in memory
b) interrupts the host
c) status bit in memory or interrupts the host
d) clock pulse
Answer: c
Explanation: The microprocessor in a closely coupled system either uses a status bit in memory
or interrupts the host to inform it about the completion of task allotted to it.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Design of a PC Based Multimicroprocessor System”.
1. The files that reside in the current drive and directory of the hard disk is
a) OBJ files
b) EXE files
c) SRC files
d) DEST files
Answer: b
Explanation: The files that reside in the current drive and directory of the hard disk is EXE files.
2. The master processor stores the result buffers on to the hard disk with the filename as
a) .EXE file
b) .OBJ file
c) .EXE file with extension .RES
d) .OBJ file with extension .RES
Answer: c
Explanation: The master processor stores the result buffers on to the hard disk with the filename
as .EXE file with extension .RES.
3. The 8288 bus controller chip derives the signals
a) ALE
b) DEN
c) DT/R
activelow
d) All of the mentioned
Answer: d
Explanation: The latches are enabled by ALE signal and data will be enabled by DEN signal.
The ALE, DEN and DT/R
activelow
signals are derived by a separate 8288 bus controller chip.
4. The EXE files should not exceed the size of
a) 30 KB
b) 50 KB
c) 60 KB
d) 40 KB
Answer: c
Explanation: The EXE files should not be more than 60 KB size.
5. A part of memory that can be addressed by more than one processor for communication is
known as
a) memory module
b) bus window
c) ram
d) memory management unit
Answer: b
Explanation: There are two slave processors and thus there are two bus windows.
6. When a subprocessor wants to communicate with the bus window, it informs the main
processor to
a) enable control buffer
b) storage buffer
c) disable tristate buffer
d) translation look aside buffer
Answer: c
Explanation: An 8255 IO card is used to control the tristate buffers that provide isolation. When
a subprocessor wants to communicate with the bus window, it informs the main processor to
disable tristate buffer.
7. When the subprocessor completes its execution, then the status on the status lines shows
a) hold status
b) halt status
c) high status
d) low status
Answer: b
Explanation: When the subprocessor completes its execution, then the status on the status lines
shows halt status.
8. For MEMR
activelow
and MEMWR
activelow
operations the mode of isolation buffer should respectively be in
a) receiver mode, receiver mode
b) transmit mode, receiver mode
c) receiver mode, transmit mode
d) transmit mode, transmit mode
Answer: c
Explanation: During MEMR
activelow
the data flow from memory to CPU so isolation buffer should be in receiver mode and data
flows from CPU to memory during MEMWR
activelow
operation and so buffer should be in transmit mode.
9. If the DIR pin of the isolation chip is high, then it enters into
a) receiver mode
b) virtual access mode
c) transmit or receive mode
d) transmit mode
Answer: d
Explanation: If the DIR pin of the isolation chip is high, then it enters into transmit mode and if it
is 0 then the isolation chip enters into receiver mode.
10. The complete software system is divided into
a) main program
b) Interrupt routine IRT2 for first subprocessing the unit
c) Interrupt routine IRT3 for first subprocessing the unit
d) all of the mentioned
Answer: d
Explanation: System software of the complete system consists of three parts. the first part main
control program controls the total operation of the system, and the remaining two parts are the
small local initialization programs for each of the subprocessors.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Salient Features of 80286”.
1. The 80286 is able to address the physical memory of
a) 8 MB
b) 16 MB
c) 24 MB
d) 64 MB
Answer: b
Explanation: The 80286 with its 24-bit address bus is able to address 16 Mbytes of physical
memory.
2. The 80286 is able to operate with the clock frequency of
a) 12.5 MHz
b) 10 MHz
c) 8 MHz
d) all of the mentioned
Answer: d
Explanation: Various versions of 80286 are available that run on 12.5 MHz, 10 MHz and 8 MHz
clock frequencies.
3. The management of the memory system required to ensure the smooth execution of the
running process is done by
a) control unit
b) memory
c) memory management unit
d) bus interface unit
Answer: c
Explanation: The memory management which is an important task of the operating system is
now supported by a hardware unit called a memory management unit.
4. The fetching of the program from secondary memory to place it in physical memory, during
the execution of CPU is called
a) mapping
b) swapping in
c) swapping out
d) pipelining
Answer: b
Explanation: Whenever the portion of a program is required for execution by the CPU, it is
fetched from the secondary memory and placed in the physical memory. This is called swapping
in of the program.
5. The process of making the physical memory free by storing the portion of program and partial
results in the secondary storage called
a) mapping
b) swapping in
c) swapping out
d) pipelining
Answer: c
Explanation: In swapping out, a portion of the program or important partial results required for
further execution, may be saved back on secondary storage to make the physical memory free,
for further execution of another required portion of the program.
6. The memory that is considered as a large logical memory space, that is not available
physically is
a) logical memory
b) auxiliary memory
c) imaginary memory
d) virtual memory
Answer: d
Explanation: To the user, there exists a very large logical memory space, which is actually not
available called virtual memory. This does not exist physically in a system. It is however,
possible to map a large virtual memory space onto the real physical memory.
7. Memory management deals with
a) data protection
b) unauthorized access prevention
c) segmented memory
d) all of the mentioned
Answer: d
Explanation: The important aspects of memory management are data protection, unauthorized
access prevention, and segmented memory.
8. The memory management and protection mechanisms are disabled when the 80286 is
operated in
a) normal mode
b) real address mode
c) virtual address mode
d) all of the mentioned
Answer: b
Explanation: In real address mode of 80286, all the memory management and protection
mechanisms are disabled.
9. The memory management and protection mechanisms are enabled with advanced instruction
set when 80286 is operated in
a) normal mode
b) real address mode
c) virtual address mode
d) all of the mentioned
Answer: c
Explanation: In virtual address mode, 80286 works with all of its memory management and
protection capabilities, with the advanced instruction set.
10. The 80286 is an upward object code compatible with 8086 or 8088 when operated in
a) normal mode
b) real address mode
c) virtual address mode
d) real and virtual address mode
Answer: d
Explanation: The 80286 is operated in two modes, namely real address mode and virtual
address mode. In both the modes, the 80286 is compatible with 8086/8088.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Internal Architecture of 80286”.
1. The CPU of 80286 contains
a) 16-bit general purpose registers
b) 16-bit segment registers
c) status and control register
d) all of the mentioned
Answer: d
Explanation: The CPU of 80286 contains the same set of registers as in 8086.
2. The bits that are modified according to the result of the execution of logical and arithmetic
instructions are called
a) byte addressable bit
b) control flag bits
c) status flag bit
d) none of the mentioned
Answer: c
Explanation: The flag register bits, D0, D2, D4, D6, D7 and D11 are modified according to the
result of the execution of logical and arithmetic instructions. These are called as status flag bits.
3. The flags that are used for controlling machine operation are called
a) status flags
b) control flags
c) machine controlled flags
d) all of the mentioned
Answer: b
Explanation: The flags such as trap flag
TF
and Interrupt flag
IF
bits are used for controlling the machine operation, and thus they are called control flags.
4. The additional field that is available in 80286 is
a) I/O Privilege field
b) nested task flag
c) protection enable
d) all of the mentioned
Answer: d
Explanation: The additional fields available in 80286 flag register are, I/O Privilege field, nested
task flag, protection enable, and monitor processor extension.
5. Which of the block is not considered as a block of an architecture of 80286?
a) address unit
b) bus unit
c) instruction unit
d) control unit
Answer: d
Explanation: The CPU may be viewed to contain four functional parts and they are
i) Address Unit
ii) Bus Unit
iii) Instruction Unit
iv) Execution Unit.
6. The unit that is responsible for calculating the address of instructions, and data that the CPU
wants to access is
a) bus unit
b) address unit
c) instruction unit
d) control unit
Answer: b
Explanation: The address unit is responsible for calculating the address of instructions, and data
that the CPU wants to access. Also, the address lines derived by this unit may be used to
address different peripherals.
7. The process of fetching the instructions in advance, and storing in the queue is called
a) mapping
b) swapping
c) instruction pipelining
d) storing
Answer: c
Explanation: The instructions are fetched in advance and stored in a queue to enable faster
execution of the instructions. This concept is known as instruction pipelining.
8. The CPU must flush out the prefetched instructions immediately following the branch
instruction in
a) conditional branch
b) unconditional branch
c) conditional and unconditional branches
d) none of the mentioned
Answer: b
Explanation: In case of unconditional branch, the CPU will have to flush out the prefetched
instructions, immediately following the branch instruction.
9. The device that interfaces and control the internal data bus with the system bus is
a) data interface
b) controller interface
c) data and control interface
d) data transreceiver
Answer: d
Explanation: The data transreceivers interface and control the internal data bus with the system
bus.
10. The register bank of Execution Unit of 80286 is used as
a) for storing data
b) scratch pad
c) special purpose registers
d) all of the mentioned
Answer: d
Explanation: The execution unit contains the register bank, used for storing the data as scratch
pad, or used as special purpose registers.
11. Which of the following is not an interrupt generated by 80286?
a) software interrupts
b) hardware or external interrupts
c) INT instruction
d) none of the mentioned
Answer: d
Explanation: The interrupts generated by 80286 may be divided into 3 categories as external or
hardware interrupts, INT instruction or software interrupts and interrupts generated by
exceptions.
12. For which of the following instruction does the return address point to instruction causing an
exception?
a) divide error exception
b) bound range exceeded exception
c) invalid opcode exception
d) all of the mentioned
Answer: d
Explanation: For the instructions, divide error, bound range exceeded and invalid opcode
exceptions, the return address points to the instruction causing exception.
13. The instruction that comes into action, if the trap flag is set is
a) maskable interrupt
b) non-maskable interrupt
c) single step interrupt
d) breakpoint interrupt
Answer: c
Explanation: Single step interrupt is an internal interrupt that comes into action if the trap flag
TF
is set.
14. The interrupt that has the highest priority among the following is
a) Single step
b) NMI
non−maskableinterrupt
c) INTR
d) Instruction exception
Answer: d
Explanation: The instruction exception has the highest priority followed by single step, NMI and
INTR instrution.
15. The interrupt that has the lowest priority among the following is
a) Processor extension segment overrun
b) INTR
c) INT instruction
d) NMI
Answer: c
Explanation: The INT instruction has the lowest priority. The order of priority of interrupts from
high to low is
1) instruction exception
2) single step
3) NMI
4) processor extension segment overrun
5) INTR
6) INT instruction.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Signal Descriptions of 80286”.
1. The 80286 is available in the package as
a) 68-pin PLCC
plasticleadedchipcarrier
b) 68-pin LCC
leadlesschipcarrier
c) 68-pin PGA
pingridarray
d) all of the mentioned
Answer: d
Explanation: The 80286 is available in 68-pin PLCC
plasticleadedchipcarrier
, 68-pin LCC
leadlesschipcarrier
and 68-pin PGA
pingridarray
packages.
2. The clock frequency applied at the CLK pin is internally divided by
a) 2
b) 4
c) 8
d) 1
Answer: a
Explanation: The clock frequency is divided by two internally, and is used for deriving
fundamental timings for basic operations of the circuit.
3. The 8 address lines, A23-A16 of 80286 are zero during
a) memory transfer
b) address transfer
c) memory to processor transfer
d) I/O transfer
Answer: d
Explanation: The address lines, A23-A16 are zero during I/O transfers.
4. The signals S1
activelow
, S2
activelow
are
a) output signals
b) indicate initiation of bus cycle
c) define type of bus cycle with M/IO
activelow
d) all of the mentioned
Answer: d
Explanation: The signals S1
activelow
, S2
activelow
are active low status output signals, which indicate initiation of a bus cycle, and with M/IO
activelow
and COD/INTA
activelow
, they define the type of the bus cycle.
5. If M/IO
activelow
signal is ‘0’ then it indicates
a) I/O cycle
b) Memory cycle
c) I/O cycle or INTA cycle
d) I/O cycle or HALT cycle
Answer: c
Explanation: If M/IO
activelow
signal is ‘0’ then it indicates that an I/O cycle or INTA cycle is in the process, and if it is ‘1’, it
indicates that a memory or a HALT cycle is in progress.
6. The LOCK
activelow
is activated automatically by hardware using
a) XCHG signal
b) Interrupt acknowledge
c) Descriptor table access
d) All of the mentioned
Answer: d
Explanation: The lock pin is used to prevent the other masters from gaining the control of the
bus, for the current and the following bus cycles. This pin is activated by a “LOCK” instruction
prefix, or automatically by hardware during XCHG, interrupt acknowledge or descriptor table
access.
7. The pin that is used to insert wait states in a bus cycle is
a) WAIT
b) BHE
activelow
c) READY
activelow
d) WAIT
activelow
Answer: c
Explanation: The active low READY pin is used to insert wait states in a bus cycle, for
interfacing low speed peripherals. This signal is neglected during HLDA cycle.
8. The minimum number of clock cycles required in an input pulse width of the RESET pin is
a) 4
b) 2
c) 8
d) 16
Answer: d
Explanation: The active high RESET input clears the internal logic of 80286, and re-initializes it.
The reset input pulse width should be at least 16 clock cycles.
9. To filter the output, a 0.047microfarads, 12V capacitor is connected between the pins
a) CAP and ground
b) Output pin and ground
c) CAP and Vcc
d) NMI and ground
Answer: a
Explanation: A 0.047microfarads, 12V capacitor is connected between the CAP pin and ground,
to filter the output of the internal substrate bias generator.
10. The signal that causes the 80286 to perform the processor extension interrupt while
executing the WAIT and ESC instructions are
a) BUSY
activelow
b) PEACK
activelow
c) PEREQ
d) ERROR
activelow
Answer: d
Explanation: An active ERROR
activelow
signal causes the 80286 to perform the processor extension interrupt while executing the WAIT
and ESC instructions.
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Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Real Addressing Mode”.
1. The 80286 CPU acts just like that of 8086 when operated in
a) real addressing mode
b) protected virtual address mode
c) real and protected virtual address modes
d) none of the mentioned
Answer: a
Explanation: In the real addressing mode of operation of 80286, it just acts as a fast 8086.
2. In real addressing mode, the 80286 addresses a physical memory of
a) 16 MB
b) 8 MB
c) 2 MB
d) 1 MB
Answer: d
Explanation: In real addressing mode, the 80286 addresses a physical memory of 1 Mbytes
using A0-A19. The lines A20-A23 are not used by the internal circuit of 80286 in this mode.
3. In real addressing mode, the 80286 operates at a speed
a) faster than that of 8086
b) half of that of 8086
c) slower than that of 8086
d) same as that of 8086
Answer: a
Explanation: Because of extra pipelining and other circuit level improvements, in real address
mode also, the 80286 operates at a much faster rate than 8086.
4. In physical memory, if the segment size limit is exceeded by the instruction or data then
a) instruction is not executed
b) exception is generated
c) saves to next segment automatically
d) none of the mentioned
Answer: b
Explanation: An exception is generated if the segment size limit is exceeded by the instruction
or the data.
5. The 80286 reserves fixed area of physical memory for
a) system initialization
b) interrupt vector table
c) system initialization and interrupt vector table
d) none of the mentioned
Answer: c
Explanation: The 80286 reserves two fixed areas of physical memory for system initialization
and interrupt vector table.
6. In the real mode, the memory that is reserved for interrupt vector table is
a) first 2 KB of memory
b) first 1 KB of memory
c) last 2 KB of memory
d) last 1 KB of memory
Answer: b
Explanation: In the real mode, the first 1 Kbyte of memory starting from the address 00000H to
003FFH, is reserved for interrupt vector table.
7. In the real mode, the memory that is reserved for system initialization is
a) from 004FFH to 0FFFFH
b) from 004FFH to 05FFFH
c) from FFFF0H to FFFFFH
d) from FFF00H to FFFFFH
Answer: c
Explanation: The addresses from FFFF0H to FFFFFH are reserved for system initialization, in
real addressing mode.
8. When 80286 is reset, it always starts its execution in
a) protected virtual addressing mode
b) real addressing mode
c) either real or protected virtual address modes
d) none of the mentioned
Answer: b
Explanation: When 80286 is reset, it always starts its execution in real addressing mode.
9. The 80286 in real addressing mode performs
a) initialization of IP
b) enables interrupts
c) sets up descriptor table
d) all of the mentioned
Answer: d
Explanation: The 80286 in real addressing mode performs the following functions: it initializes IP
and other registers of 80286, initializes the peripheral, enables interrupts, sets up descriptor
tables, and then prepares it for entering the protected virtual address mode.
10. In real address mode, while addressing the physical memory, the 80286 uses the signal
a) HLDA
b) BHE
activelow
c) CAP
d) HOLD
Answer: b
Explanation: In real address mode, while addressing the physical memory, the 80286 uses BHE
activelow
along with A0-A19.
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Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Protected Virtual Address Mode
PVAM
-1”.
1. The procedure of fetching the chosen program segments or data from the secondary storage
into the physical memory is
a) mapping
b) swapping
c) unswapping
d) pipelining
Answer: b
Explanation: Swapping is the procedure of fetching the chosen program segments or data from
the secondary storage into the physical memory.
2. The procedure of storing back the partial results on to the secondary storage is called
a) mapping
b) swapping
c) unswapping
d) pipelining
Answer: c
Explanation: The procedure of storing back the partial results or data back on to the secondary
storage is called unswapping.
3. The ability of 80286 to address the virtual memory per task is
a) 1MB
b) 1GB
c) 1TB
d) none of the mentioned
Answer: b
Explanation: The 80286 is able to address 1Gbyte of virtual memory per task.
4. The branch instructions are handled by
a) swapping mechanism
b) unswapping mechanism
c) operating system
d) all of the mentioned
Answer: d
Explanation: The handling of branch instructions like JUMP and CALL is taken care of, by the
swapping and unswapping mechanism, and operating system.
5. A descriptor contains information of
a) program segment
b) page
c) regarding segment and its access rights
d) all of the mentioned
Answer: d
Explanation: The segments or pages have been associated with a data structure known as a
descriptor. The descriptor contains information on the page, and also carry relevant information
regarding a segment, and its access rights.
6. The descriptors that are used for subroutines and interrupt service routines are
a) data segment descriptors
b) gate descriptors
c) code segment descriptors
d) system segment descriptors
Answer: b
Explanation: For data segment, the corresponding descriptor may be data segment descriptor
and for code segment, there may be code segment descriptor. For subroutines and interrupt
service routines there are gate descriptors.
7. A segment with low privilege level is not allowed to access another segment of
a) low privilege level
b) high privilege level
c) low and high privilege level
d) none of the mentioned
Answer: b
Explanation: A segment with low privilege level is not allowed to access another segment with
high privilege level.
8. A descriptor is used to carry out
a) transfer of control
b) task switching
c) to store privilege level and segment limit
d) all of the mentioned
Answer: d
Explanation: A descriptor is used to carry out additional functions like transfer of control and
task switching.
9. The descriptor that is used for special system data segments and control transfer operations
is
a) data segment descriptors
b) gate descriptors
c) code segment descriptors
d) system segment descriptors
Answer: d
Explanation: The 80286 has system segment descriptor, that is used for special system data
segments, and control transfer operations.
10. A code segment descriptor contains
a) 16-bit segment limit
b) 24-bit segment base address
c) 8-bit access rights byte
d) all of the mentioned
Answer: d
Explanation: A code or data segment descriptor contains 16-bit segment limit, 24-bit segment
base address, 8-bit access rights byte and the remaining 16-bits are reserved by Intel for
upward compatibility.
11. In access rights byte, if P
Present
=1, then the segment is mapped into
a) physical memory
b) virtual memory
c) no mapping takes place
d) none of the mentioned
Answer: a
Explanation: If P=1, then the segment is mapped into physical memory.
12. In access rights byte, to select system segment descriptor, the condition is
a) S=1
b) S=0
c) S not equal to zero
d) none of the mentioned
Answer: b
Explanation: If S
segmentdescriptor
=0, then system segment descriptor or gate descriptor is selected.
13. If S
segmentdescriptor
=1, then the descriptor selected is
a) code segment descriptor
b) data segment descriptor
c) stack segment descriptor
d) all of the mentioned
Answer: d
Explanation: If S=1, then code or data
includingstack
segment descriptors are selected.
14. The memory of limit field is
a) 2 bits
b) 4 bits
c) 8 bits
d) 16 bits
Answer: d
Explanation: The limit field, which is the maximum allowed offset address, is of 16 bits.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Advanced Microprocessors Questions and Answers focuses on “Protected Virtual
Address Mode
PVAM
-2”.
1. Which of the following is a type of system segment descriptor?
a) system descriptor
b) gate descriptor
c) system descriptor and gate descriptor
d) none of the mentioned
Answer: c
Explanation: The system segment descriptors are of seven types. The types 1 to 3 are called
system descriptors and the types 4 to 7 are called gate descriptors.
2. Which of the following is a type of gate descriptor?
a) call gate
b) task gate
c) interrupt gate
d) all of the mentioned
Answer: d
Explanation: The gate descriptors are of four types namely, call gate, task gate, interrupt gate
and trap gate.
3. The gate descriptor contains the information of
a) destination of control transfer
b) stack manipulations
c) privilege level
d) all of the mentioned
Answer: d
Explanation: The gate descriptor contains the information regarding the destination of control
transfer, required stack manipulations, privilege level and its type.
4. The gate that is used to alter the privilege levels is
a) call gate
b) task gate
c) interrupt gate
d) trap gate
Answer: a
Explanation: Call gates are used to alter the privilege levels.
5. The gate that is used to specify a corresponding service routine is
a) call gate and trap gate
b) task gate and interrupt gate
c) interrupt gate and trap gate
d) task gate and trap gate
Answer: c
Explanation: Interrupt gates and trap gates are used to specify corresponding service routines.
6. The gate that is used to switch from one task to another is
a) trap gate
b) task gate
c) task gate and trap gate
d) none of the mentioned
Answer: b
Explanation: Task gate is used to switch from one task to another.
7. The gate that uses word count field is
a) trap gate
b) task gate
c) interrupt gate
d) call gate
Answer: d
Explanation: The word count field is only used by a call gate descriptor, to indicate the number
of bytes to be transferred from the stack of the calling routine to the stack of the called routine.
8. The memory that maintains the most frequently required data for execution, in a high speed
memory is called
a) virtual memory
b) physical memory
c) cache memory
d) ROM
readonlymemory
Answer: c
Explanation: To minimize the time required for fetching the frequently required descriptor
information, from the main memory, cache memory is used in which the most frequently
required data for execution is stored.
9. The selector field consists of
a) requested privilege level
RPL
b) table indicator
c) index
d) all of the mentioned
Answer: d
Explanation: In the protected mode, the contents of the segment registers are known as
selectors. The selector field consists of three fields namely, RPL, table indicator
TI
and index.
10. If table indicator, TI=0, then the descriptor table selected is
a) local descriptor table
b) global descriptor table
c) local and global descriptor table
d) none of the mentioned
Answer: b
Explanation: The type of descriptor table is global if TI=0 and local if TI=1.
11. The instruction that is executed at privilege level zero
is
a) LDT
b) LGDT and LLDT
c) GDT
d) None of the mentioned
Answer: b
Explanation: The LGDT and LLDT instructions are privileged, and may be executed only at
privilege level 0.
12. The instruction that loads a selector which refers to a local descriptor table, containing the
base address and limit for LDT is
a) LGT
b) GDT
c) LGDT
d) LLDT
Answer: d
Explanation: The LLDT instruction loads a selector, which refers to a local descriptor table,
containing the base address, and limit for LDT.
13. The descriptor that is used to store task gates, interrupt gates and trap gates is
a) system descriptor table
b) gate descriptor table
c) interrupt descriptor table
d) none of the mentioned
Answer: c
Explanation: The 80286 has a third type of descriptor table known as interrupt descriptor table,
which is used to store task gates, interrupt gates and trap gates.
14. The number of interrupt descriptors that the interrupt descriptor table
IDT
handles is
a) 16
b) 64
c) 128
d) 256
Answer: d
Explanation: The IDT is able to handle upto 256 interrupt descriptors.
15. The number of bytes required for an interrupt in an IDT is
a) 2
b) 4
c) 6
d) 8
Answer: c
Explanation: Six bytes are required for each interrupt in an interrupt descriptor table.
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set of 1000+ Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Privilege”.
1. By using privilege mechanism the protection from unauthorized accesses is done to
a) operating system
b) interrupt handlers
c) system software
d) all of the mentioned
Answer: d
Explanation: The operating system, interrupt handlers and other system softwares can be
protected from unauthorized accesses in virtual address space of each task using the privilege
mechanism.
2. The task privilege level at the instant of execution is called
a) Descriptor privilege level
DPL
b) Current privilege level
CPL
c) Effective privilege level
EPL
d) None of the mentioned
Answer: b
Explanation: Any one of the four privilege levels may be used to execute a task. The task
privilege level at that instant is called the Current Privilege Level
CPL
.
3. Once the CPL is selected, it can be changed by
a) hold
b) transferring control using system descriptors
c) transferring control using gate descriptors
d) transferring control using interrupt descriptors
Answer: c
Explanation: Once the CPL is selected, it cannot be changed during the execution normally in a
single code segment. It can only be changed by transferring the control, using gate descriptors,
to a new segment.
4. The data segments defined in GDT
globaldescriptortable
and the LDT
localdescriptortable
can be accessed by a task with
a) privilege level 0
b) privilege level 1
c) privilege level 2
d) privilege level 3
Answer: a
Explanation: A task executing at level 0, the most privileged level, can access all the data
segments defined in GDT and the LDT of the task.
5. A task with privilege level 0, doesn’t refer to all the lower level privilege descriptors in
a) GDT
globaldescriptortable
b) LDT
localdescriptortable
c) IDT
interruptdescriptortable
d) None of the mentioned
Answer: b
Explanation: The task with privilege level 0, refers to all the lower level privilege descriptors
which apply to all the descriptors except the LDT descriptors.
6. The selector RPL that uses a less trusted privilege than the current privilege level for further
use is known as
a) Least task privilege level
b) Descriptor privilege level
c) Effective privilege level
d) None of the mentioned
Answer: c
Explanation: A selector RPL uses a less trusted privilege than the current privilege level for
further use. This is known as the Effective Privilege Level of the task.
7. The effective privilege level is
a) maximum numeric of RPL and CPL
b) minimum privilege of RPL and CPL
c) numeric minimum and privilege maximum of RPL and CPL
d) none of the mentioned
Answer: c
Explanation: The effective privilege level is minimum in numeric and maximum in the privilege of
RPL and CPL.
8. The task requesting an access to a descriptor is allowed to access after checking the
a) type of descriptor
b) privilege level
c) type of descriptor and privilege level
d) corresponding segment
Answer: c
Explanation: The task requesting an access to a descriptor is allowed to access to it and to the
corresponding segment, only after checking the type of the descriptor and privilege level
CPL,RPL,DPL
.
9. A CALL instruction can reference only a code segment descriptor with
a) DPL less privilege than CPL
b) DPL equal privilege to CPL
c) DPL greater privilege than CPL
d) All of the mentioned
Answer: b
Explanation: A CALL or JUMP instruction can reference only a code segment descriptor with
DPL equal to CPL of the task or a segment with a DPL of equal or greater privilege than CPL.
10. The RPL of a selector that referred to the code descriptor must have
a) less privilege than CPL
b) greater privilege than CPL
c) equal privilege than CPL
d) any privilege regarding CPL
Answer: c
Explanation: The RPL of a selector that referred to the code descriptor must have the same
privilege as CPL.
11. The instruction that refers to only code segment descriptors with DPL equal to or less than
the task CPL is
a) CALL
b) IRET
c) ESC
d) RET and IRET
Answer: d
Explanation: The RET and IRET instructions are to refer to only code segment descriptors with
DPL equal to or less than the task CPL.
12. When a JUMP instruction references a Task State Segment
TSS
descriptor, then DPL must be
a) equally privileged as CPL
b) greater or equally privileged than CPL
c) less or equally privileged than CPL
d) less privileged than CPL
Answer: c
Explanation: When a CALL or JUMP instruction references a Task State Segment
TSS
descriptor, then DPL must be less or equally privileged than CPL.
13. The data segment access refers to
a) loading DS
b) loading ES
c) loading SS
d) all of the mentioned
Answer: d
Explanation: Loading DS, ES or SS for referring to a new descriptor comes under the data
segment access.
14. An exception is generated when
a) privilege test is negative
b) an improper segment is referenced
c) referenced segment is not present in physical memory
d) all of the mentioned
Answer: d
Explanation: If the privilege test is negative or an improper segment is referenced then an
exception 13 is generated. If the referenced segment is not present in physical memory, an
exception 11 is generated.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Protection”.
1. The mechanism to provide protection, that is accomplished with the help of read/write
privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
Answer: a
Explanation: The restricted use of segments is accomplished with the help of read/write
privileges.
2. The Local descriptor table
LDT
and Global descriptor table
GDT
are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
Answer: c
Explanation: In restricted use of segments i.e. segment load check, the segment usages are
restricted by classifying the corresponding descriptors, under LDT and GDT.
3. The mechanism that is accomplished using descriptor usages limitations and rules of
privilege check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
Answer: b
Explanation: Restricted accesses to segment, also called, operation reference check, is
accomplished using descriptor usages limitations, and rules of privilege check.
4. The mechanism that is executed at certain privilege levels, determined by CPL
CurrentPrivilegeLevel
and I/O privilege level
IOPL
is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
Answer: c
Explanation: The privileged instructions or operations, also called, privileged instruction check,
is executed at certain privilege levels, determined by CPL and I/O privilege level
IOPL
, as defined by the flag register.
5. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) None of the mentioned
Answer: c
Explanation: The IRET and POPF instructions do not perform any of their functions, if CPL is
not of the required privilege level.
6. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
Answer: c
Explanation: IF remains unaffected if CPL is greater than zero. No exception is generated for
this condition.
7. The condition, “CPL not equals to zero” satisfies when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) All of the mentioned
Answer: d
Explanation: The condition, “CPL not equals to zero” satisfies, when executing the instructions,
LIDT, LGDT, LTR, LMSW, CTS and HLT.
8. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) All of the mentioned
Answer: c
Explanation: The condition CPL>IOPL exists, when executing the instructions, INs, IN, OUTS,
OUT, STI, CLI and LOCK.
9. The instruction at which the exception is generated, but the processor extension registers
contain the address of failing instruction is
a) LTR
b) INS
c) CTS
d) ESC
Answer: d
Explanation: At the ESC instruction, the exception is generated, but the processor extension
registers contain the address of failing instruction.
10. The exception that has no error code on a stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
Answer: b
Explanation: The processor extension segment overrun has no error code on the stack.
11. Which of the following is protected mode exception?
a) double exception detected
b) invalid task state segment
c) stack segment overrun
d) all of the mentioned
Answer: d
Explanation: Double exception detected, invalid task state segment, stack segment overrun,
processor extension segment overrun, are the protected mode exceptions.
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Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Special Operations”.
1. Which of the following operation is not carried out by 80286?
a) task switch operation
b) halt
c) processor reset
d) none of the mentioned
Answer: d
Explanation: The 80286 carries out six operations. They are:
1. processor reset and initialization
2. task switch operation
3. pointer testing instructions
4. protected mode initialization
5. how to enter protected mode?
6. halt.
2. After completion of the first cycle, the first task is again scheduled for the next cycle. This
process is known as
a) repetition
b) task switch operation
c) processor initiation
d) none of the mentioned
Answer: b
Explanation: After completion of the first cycle, the first task is again scheduled for the next
cycle, and the process continues. The previous task that was incomplete, may be completed
during its coming turns of the allotted CPU time slice. This switch-over operation from one task
to another is called task switch operation.
3. The operation that is provided by the internal architecture, to save the execution state of a
task is
a) processor reset
b) processor initialization
c) task switch operation
d) halt
Answer: c
Explanation: The 80286 internal architecture provides a task switch operation, to save the
execution state of a task, and to load a new task to be executed.
4. The instruction that can be used to carry out task switch operation is
a) software interrupt instruction
b) exception
c) external interrupt
d) all of the mentioned
Answer: d
Explanation: A software interrupt instruction, exception or external interrupt, can also be used to
carry out task switch operation.
5. The IRET instruction gets back the execution state of the previous task, if
a) NT
nestedtaskflag
=1
b) NT
nestedtaskflag
=0
c) IF
interruptflag
=1
d) IF
interruptflag
=0
Answer: a
Explanation: If NT = 1, the IRET instruction gets back the execution state of the previous task.
Otherwise, the IRET instruction lets the current task continue, after popping the required values
from the stack.
6. The NT flag is set by the task switch operation, that is initiated by
a) CALL
b) INT
c) CALL & INT
d) None of the mentioned
Answer: c
Explanation: The NT flag is set by CALL or INT initiated task switch operations.
7. The 80286 executes LMSW instruction to enter into
a) real addressing mode
b) protected mode
c) real addressing and protected modes
d) none of the mentioned
Answer: b
Explanation: To enter into protected mode, 80286 executes LMSW instruction, that sets PE flag.
8. The instruction that sets the zero flag, if the segment referred to, by the selector can be read
is
a) VERW
b) VERR
c) LSL
d) LAR
Answer: b
Explanation: The VERR
VERifytoRead
instruction sets the zero flag, if the segment referred to, by the selector, can be read.
9. The instruction that sets the zero flag, if the segment referred to by the selector, can be
written as
a) VERW
b) APRL
c) LSL
d) LAR
Answer: a
Explanation: The VERW
VERifytoWrite
instruction sets the zero flag, if the segment referred to, by the selector can be written.
10. The instruction that reads the descriptor access rights byte into the register is
a) VERW
b) APRL
c) LSL
d) LAR
Answer: d
Explanation: The LAR
LoadAccessRights
instruction reads the descriptor access rights byte into the register, if privilege rules allow.
11. The instruction that reads the segment limit into the register, if privilege rules and descriptor
type allow is
a) VERW
b) APRL
c) LSL
d) LAR
Answer: c
Explanation: The LSL
LoadSegmentLimit
instruction reads the segment limit into the register, if privilege rules, and descriptor type allow.
12. The instruction that adjusts the RPL
RequestedPrivilegeLevel
of the selector, to the numeric maximum of current selector RPL value is
a) LAR
b) VERR
c) LSL
d) APRL
Answer: d
Explanation: The APRL
AdjustRequestedPrivilegeLevel
adjusts the RPL
RequestedPrivilegeLevel
of the selector to the numeric maximum of current selector RPL value, and the RPL value in the
register.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Interview Questions and Answers for Experienced people focuses
on “80286 Minimum System Configuration, Interfacing Memory and I/O Devices With 80286”.
1. Which of the following is a supporting chip of 80286?
a) interrupt controller
b) clock generator
c) bus controller
d) all of the mentioned
Answer: d
Explanation: The interrupt controller 8259A, clock generator 82C284, and bus controller 82C288
are the unavoidable members of the family, of supporting chips of 80286.
2. In minimum mode, the function of 80286 is
a) data transfers to/from memory or I/O
b) controls the data transfer of 80287
c) controls the instruction execution of 80287
d) all of the mentioned
Answer: d
Explanation: In a minimum mode, the 80286 carries out all the data transfers to/from memory or
I/O, controls the data transfer, and instruction execution of 80287.
3. The signal that is applied to the decoding logic, to differentiate between interrupt, code fetch
and data bus cycles is
a) COD
b) INTA
activelow
c) M/IO
activelow
d) All of the mentioned
Answer: d
Explanation: The COD, INTA
activelow
, M/IO
activelow
signals are applied to the decoding logic, to differentiate between interrupt, I/O, code fetch, and
data bus cycles.
4. By adding which of the following, the minimum mode of 80286 gives the multibus interface of
80286?
a) bus controller
b) bus arbiter
c) interrupt controller
d) all of the mentioned
Answer: b
Explanation: The addition of single chip 82C289 known as bus arbiter, to the configuration of
80286 minimum mode, gives the multibus structure of 80286.
5. The number of bus controllers that are used for interfacing of memory and I/O devices is
a) 1
b) 2
c) 3
d) none of the mentioned
Answer: b
Explanation: The interfacing of memory and I/O devices, uses two 82288 bus controllers, one
each for local, and system bus.
6. If the 80286 need to use system bus, then the signal that is to be active is
a) SRDY
b) SRDYEN
c) ARDYEN
d) ARDY
Answer: c
Explanation: The ARDYEN pin is to be activated if the 80286 is to use the system bus. The
SRDYEN pin is to be grounded.
7. If MBYTES input is high, then the pin serves as
a) AEN
b) CEN
c) AEN and CEN
d) None of the mentioned
Answer: a
Explanation: The MBYTES input selects the function of AEN/CEN pin. If MBYTES is high, the
pin serves as AEN, else it serves as CEN. The CEN pin is used for selecting one of the
available 82288s.
8. Latches are used in 80286 to
a) demultiplex the address and data lines
b) latch the address signals
c) decode the select signals
d) latch the address and decode the select signals
Answer: d
Explanation: The address and data lines are not multiplexed, hence no latches are required in
80286 system. Rather the addresses of the next bus cycle are displayed in advance, hence the
latches are required for latching the address, and decode the signals.
9. The I/O port addresses, that are not used, while designing practical systems around 80286
are
a) 0000H to 00FFH
b) 00FFH to FFFFH
c) 00F8H to 00FFH
d) 0000H to FFFFH
Answer: c
Explanation: The I/O port addresses 00F8H to 00FFH are reserved by Intel, hence these should
not be used while designing practical systems around 80286.
To practice all areas of Microprocessors for Interviews, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessors test focuses on “Priority of Bus Use By 80286, Bus Hold and HLDA
Sequence, Interrupt Acknowledge Sequence”.
1. Which of the following is the highest priority usage among them?
a) second transfer cycle of a processor extension data transfer
b) third transfer cycle of a processor extension data transfer
c) hold request
d) second byte transfer of 2-byte transfer at an odd address
Answer: d
Explanation: The second byte transfer of 2-byte transfer at an odd address, is the highest
priority usage among the given usages.
2. The highest priority usage than any other usage is
a) transfer with LOCK
activelow
signal
b) hold request
c) processor extension data transfer
d) data transfer performed by EU
executionunit
Answer: a
Explanation: The transfer with LOCK
activelow
signal is the highest priority usage than any other usage.
3. The lowest priority usage among the following is
a) hold request
b) processor extension data transfer
c) prefetch operation to fetch and arrange next instruction bytes in queue
d) data transfer performed by EU for instruction execution
Answer: c
Explanation: The order of priority usages, starting from the highest one to the lowest one, is
given as
1. transfer with LOCK
activelow
signal
2. second byte transfer of 2-byte transfer at an odd address
3. second or third transfer cycle of a processor extension data transfer
4. HOLD request
5. processor extension data transfer
6. data transfer performed by EU
executionunit
7. prefetch operation to fetch and arrange next instruction bytes in queue.
4. As a response to the valid bus hold request, the bus is pushed into
a) TH
hold
state
b) Ts
status
state
c) Tc
command
state
d) Ti
idle
state
Answer: a
Explanation: 80286 local bus is relinquished for another bus master if a valid bus hold request is
received at the HOLD input pin. As a response to a valid bus hold request, the bus is pushed
into TH state.
5. The bus arbiter relinquishes
a) Address
b) M/IO
activelow
c) COD/INTA
activelow
d) All of the mentioned
Answer: d
Explanation: The address, M/IO
activelow
and COD/INTA
activelow
are relinquished by bus arbiter.
6. A valid HOLD request is ascertained only after the completion of
a) 34 clockcycles
b) 24 clockcycles and 80286 is SET
c) 34 clockcycles and 80286 is SET
d) 34 clockcycles and 80286 is RESET
Answer: d
Explanation: Only after 34 clockcycles, after the 80286 is reset, a valid HOLD request should be
ascertained.
7. The master PIC 8259A decides which of its slave interrupt controllers is to return the vector
address, as a response of
a) first INTA
activelow
pulse from 80286
b) second INTA
activelow
pulse from 80286
c) third INTA
activelow
pulse from 80286
d) none of the mentioned
Answer: a
Explanation: In response to the first INTA
activelow
pulse from 80286, the master PIC 8259A decides, which of its slave interrupt controllers is to
return the vector address.
8. The slave
whichisselected
sends the vector on data bus after the
a) first INTA
activelow
pulse from 80286
b) second INTA
activelow
pulse from 80286
c) third INTA
activelow
pulse from 80286
d) none of the mentioned
Answer: b
Explanation: The interrupt acknowledge sequence consists of two INTA
activelow
pulses. After the second pulse, the selected slave sends the vector on D0-D7 data lines, and
80286 reads it.
9. The signal of 82C288, that enables the cascade address drivers, during INTA cycles is
a) DEN
b) DT/R
activelow
c) MCE
d) MB
Answer: c
Explanation: The MCE
MasterCascadeEnable
signal of 82C288 enables the cascade address drivers during INTA cycles, to select the slave
using the local address bus.
10. The LOCK
activelow
signal is activated during
a) Ti of first INTA cycle
b) Ts of first INTA cycle
c) Th of second INTA cycle
d) Ts of second INTA cycle
Answer: b
Explanation: The LOCK
activelow
signal is activated during Ts of first INTA cycle.
11. The number of idle states
Ti
, that is allowed between two INTA cycles, to meet the 8259A speed and cascade address
output delay is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: The 80286 allows three idle states
Ti
between the two INTA cycles, to meet the 8259A speed and cascade address output delay.
To practice all areas of Microprocessors for tests, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Instruction Set Features -1”.
1. In which of these modes, the immediate operand is included in the instruction itself?
a) register operand mode
b) immediate operand mode
c) register and immediate operand mode
d) none of the mentioned
Answer: b
Explanation: In immediate operand mode, the immediate operand is included in the instruction
itself.
2. In register address mode, the operand is stored in
a) 8-bit general purpose register
b) 16-bit general purpose register
c) si or di
d) all of the mentioned
Answer: d
Explanation: In register address mode, the operand is stored either in one of the 8-bit or 16-bit
general purpose registers or in SI, DI, BX or BP.
3. In which of the following addressing mode, the offset is obtained by adding displacement and
contents of one of the base registers?
a) direct mode
b) register mode
c) based mode
d) indexed mode
Answer: c
Explanation: In a based mode, the offset is obtained by adding displacement and contents of
one of the base registers, either BX or BP.
4. In which of the following addressing mode, the offset is obtained by adding displacement, with
the contents of SI?
a) direct mode
b) register mode
c) based mode
d) indexed mode
Answer: d
Explanation: In an indexed mode, the offset is obtained by adding displacement, with contents
of an index register, either SI or DI.
5. The address of a location of the operand is calculated by adding the contents of any of the
base registers, with the contents of any of index registers in
a) based indexed mode with displacement
b) based indexed mode
c) based mode
d) indexed mode
Answer: b
Explanation: In a based indexed mode, the operand is stored at a location, whose address is
calculated by adding the contents of any of the base registers, with the contents of any of the
index registers.
6. Which of the following is not a data type of 80286?
a) Ordinal or unsigned
b) ASCII
c) Packed BCD
d) None of the mentioned
Answer: d
Explanation: The 80286 supports seven data types. They are
1. integer
2. Ordinal
unsigned
3. pointer
4. string
5. ASCII
6. BCD
7. Packed BCD.
7. The representation of 8-bit or 16-bit signed binary operands using 2’s complement is a data
type of
a) Ordinal
b) ASCII
c) Packed BCD
d) integer
Answer: d
Explanation: In integer data type, 8-bit or 16-bit signed binary operands are represented using
2’s complement.
8. The instruction that pushes the general purpose registers, pointer and index registers on to
the stack is
a) POPF
b) PUSH Imd
c) PUSH*A
d) PUSHF
Answer: c
Explanation: The PUSH*A instruction, pushes the general purpose registers, AX, CX, DX and
BX, pointer and index registers, SP, BP, SI, DI, on to the stack.
9. While executing the PUSH*A instruction, the stack pointer is decremented by
a) 1 bit
b) 2 bits
c) 4 bits
d) 16 bits
Answer: b
Explanation: The stack pointer is decremented by 16
eight2−byteregisters
.
10. The statement that is true for the instruction POP*A is
a) flags are unaffected
b) no operands are required
c) exceptions generated are same as that of PUSH*A
d) all of the mentioned
Answer: d
Explanation: The POP*A instruction, pops all the contents of the registers DI, SI, BP, SP, BX,
DX, CX and AX from the stack in this sequence, that is exactly opposite to that of pushing.
11. The instruction that multiplies the content of AL with a signed immediate operand is
a) MUL
b) SMUL
c) IMUL
d) None of the mentioned
Answer: c
Explanation: The IMUL instruction multiplies the content of AL with a signed immediate operand,
and the signed 16-bit result is stored in AX.
12. The instruction that represents the ‘rotate source, count’ is
a) RCL
b) RCR
c) ROR
d) All of the mentioned
Answer: d
Explanation: The rotate source, count is a group of four instructions containing RCL, RCR, ROL,
ROR.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Quiz focuses on “Instruction Set Features -2”.
1. In ‘Rotate source, count’ instructions, if the CF is equal to MSB of operand
source
then
a) TF is cleared
b) OF is cleared
c) TF is set
d) OF is set
Answer: b
Explanation: If CF is equal to MSB of operand
source
, the overflow flag is cleared, otherwise, it is set to 1.
2. The instruction that affects the flags is
a) IMUL
b) INSW
c) INSB
d) POP*A
Answer: a
Explanation: No flags are affected by the instructions, INSW, INSB and POP*A.
3. A general protection exception is generated, if the value of
a) CPL is equal to that of IOPL
b) CPL is less than that of IOPL
c) CPL is greater than that of IOPL
d) None of the mentioned
Answer: c
Explanation: When the value of CPL is greater than that of IOPL, a general protection exception
is generated.
4. While executing the instruction, OUTSW, the SI is incremented by
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: The SI is automatically incremented by 1 for byte
OUTSB
and 2 for word
OUTSW
operations.
5. The instruction that is used to exit the procedure is
a) QUIT
b) STOP
c) LEAVE
d) EXIT
Answer: c
Explanation: The instruction, LEAVE, is generally used with high level languages, to exit a
procedure.
6. The instruction that determines the number of bytes, to be copied into the new stack frame,
from the previous stack is
a) ENTER
b) BOUND
c) CLTS
d) LEAVE
Answer: a
Explanation: The ENTER instruction prepares a stack structure for parameters of a procedure to
be executed further. This instruction determines the number of bytes to be copied, into the new
stack frame, from the previous stack.
7. The instruction that is used to check whether a signed array offset is within the limit, defined
for it by the starting and ending index is
a) ENTER
b) BOUND
c) CLTS
d) LEAVE
Answer: b
Explanation: The BOUND instruction is used to check whether a signed array offset is within the
limit defined for it, by the starting and ending index.
8. The CLTS
ClearTaskSwitchFlag
instruction records every execution of WAIT and ESC and is trapped if the flag
a) PE
ProtectionEnable
and TS
taskswitch
flags are set
b) Emulate Processor extension flag is set
c) MP flag and task switched flag is set
d) PE and MP flag is set
Answer: c
Explanation: The CLTS
ClearTaskSwitchFlag
instruction records every execution of WAIT and ESC, and is trapped, if the MP flag and task
switched flag is set.
9. The instruction that determines whether the segment pointed to, by a 16-bit register, can be
accessed from the current privilege level is
a) RPL
b) CPL
c) ARPL
d) VERR
Answer: d
Explanation: The VERR/VERW instructions determine whether the segment pointed to, by a
16-bit register, can be accessed from the current privilege level.
10. The instruction that loads 6 bytes from a memory block, pointed to by the effective address
of the operand, into global descriptor table register is
a) LLDT
b) SGDT
c) LGDT
d) None of the mentioned
Answer: c
Explanation: The LGDT
loadglobaldescriptortableregister
loads 6 bytes from a memory block, pointed to by the effective address of the operand, into
global descriptor table register.
11. In LGDT instruction, while loading 6 bytes, the first word is loaded into the field of
a) LIMIT field
b) BASE field
c) Either LIMIT or BASE field
d) None of the mentioned
Answer: a
Explanation: While loading the 6 bytes, the first word is loaded into the LIMIT field of the
descriptor table register. The next three bytes are loaded into the BASE field of the register, and
the remaining byte is ignored.
To practice all areas of Microprocessors for Quizzes, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “80287 Math Coprocessor -1”.
1. Which of the following is not a block of an architecture of 80287?
a) bus control logic
b) data interface and control unit
c) floating point unit
d) none of the mentioned
Answer: d
Explanation: The three blocks of an internal architecture of 80287 are:
1. bus control logic
2. data interface and control unit
3. floating point unit.
2. The unit that provides and controls the interface, between the internal 80287 bus and 80286
bus via data buffer is
a) bus control logic
b) data interface and control unit
c) floating point unit
d) none of the mentioned
Answer: a
Explanation: The bus control logic provides and controls the interface, between the internal
80287 bus and 80286 bus via data buffer.
3. The data interface and control unit consists of
a) status and control words
b) tag words and error pointers
c) instruction decoders
d) all of the mentioned
Answer: d
Explanation: The data interface and control unit contains status and controls words, TAG words
and error pointers.
4. The word that optimizes the NDP performance, by maintaining a record of empty and
non-empty register locations is
a) Status and control words
b) TAG words
c) Error pointers
d) All of the mentioned
Answer: b
Explanation: The TAG word optimizes the NDP performance by maintaining a record of empty
and non-empty register locations. It helps the exception handler to identify special values in the
contents of the stack locations.
5. The part of the data interface and control unit, that points to the source of exception
generated is
a) Status and control words
b) TAG words
c) Error pointers
d) None of the mentioned
Answer: c
Explanation: The error pointers point to the source of exception
addressoftheinstructionthatgeneratedtheexception
generated.
6. The data bus in a floating point unit is of
a) 16 bits
b) 32 bits
c) 64 bits
d) 84 bits
Answer: d
Explanation: The data bus in a floating point unit is of 84-bits. Out of this 84-bits, the lower 68
bits are significant
mantissa
data bit, the next 16 bits are used for the exponent.
7. The arrangement of data that is to be shifted successively, whenever required for the
execution, is done by
a) error pointer
b) data buffer
c) barrel shifter
d) none of the mentioned
Answer: c
Explanation: The barrel shifter arranges and presents the data to be shifted successively,
whenever required for the execution.
8. The word that is used to select one of the processing options, among the provided ones is
a) status word
b) control word
c) status and control words
d) none of the mentioned
Answer: b
Explanation: The control word is used to select one of the processing options, among the ones
provided by 80287.
9. After reset of 80287, the control bit that is initialized to zero is
a) masking bits
b) precision control bits
c) rounding control bits
d) infinity control bits
Answer: d
Explanation: The infinity control bit is initialized to zero after reset.
10. The bits that are modified depending upon the result of the execution of arithmetic
instructions are
a) masking bits
b) rounding control bits
c) condition code bits
d) error summary bits
Answer: c
Explanation: The condition code bits are similar to the flags of a CPU. These are modified
depending upon the result of the execution of arithmetic instructions.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors MCQs focuses on “80287 Math Coprocessor -2”.
1. If the stack flag is set, and condition code bit C1=1, then the stack is
a) full
b) overflown
c) underflown
d) empty
Answer: b
Explanation: If the stack flag is set, and condition code bit C1=1, then the stack has overflown.
2. If the stack flag is set, and condition code bit C1=0, then the stack is
a) full
b) overflown
c) underflown
d) empty
Answer: c
Explanation: If the stack flag is set, and condition code bit C1=0, then the stack has underflown.
3. The bits that affect the result of arithmetic operations like ADD, SUB, MUL, DIV are
a) condition code bits
b) rounding control bits
c) masking bits
d) precision control bits
Answer: d
Explanation: The precision control bits affect ADD, SUB, MUL, DIV and SQRT results.
4. The precision is decided by the
a) opcode
b) extended precision format
c) opcode or extended precision format
d) none of the mentioned
Answer: c
Explanation: For other than the arithmetic instructions
likeADD,SUB,MUL,DIVandSQRT
, the precision is decided by opcode or extended precision format.
5. If Numeric Processor Write
NPWR
active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
Answer: c
Explanation: If Numeric Processor Write
NPWR
active-low input pin is activated, then it enables a data transfer from 80286 to 80287.
6. If Numeric Processor Read
NPRD
active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
Answer: b
Explanation: If Numeric Processor Read
NPRD
active-low input pin is activated, then it enables a data transfer from 80287 to 80286.
7. Which of the input line
indicate that the CPU is performing an escape operation, and enables 80287 to execute the
next instruction?
a) NPWR
activelow
and NPRD
activelow
b) NPS1 and NPS2
activelow
c) NPS1
activelow
and NPS2
d) CMD0 and CMD1
Answer: c
Explanation: The Numeric Processor select input lines, NPS1
activelow
and NPS2, indicate that the CPU is performing an escape operation, and enables 80287 to
execute the next instruction.
8. For which pin of 80286 is the active low pin, BUSY of 80287, connected?
a) ERROR
activelow
b) BUSY
activelow
c) HLDA
d) TEST
activelow
Answer: d
Explanation: The BUSY
activelow
is connected to the TEST
activelow
pin of 80286.
9. If Clock Mode
CM
input pin is held low, then the CLK input is divided by
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: If Clock Mode
CM
input pin is held high, then the CLK input is directly used for deriving the internal timings. Else,
it is divided by 2.
10. Which of the following pin is not involved in the interface of 80287 with 80286?
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answer: c
Explanation: The 10 pins, PEREQ, PEACK#, BUSY#, ERROR#, NPRD
activelow
#, NPWR
activelow
#, NPS1
activelow
#, NPS2#, CMD0 and CMD1.
11. The PEACK
activelow
when activated, the pin that goes into deactivation is
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answer: a
Explanation: When the data transfer is over, the CPU activates PEACK
activelow
# pin, which results in deactivating the PEREQ pin by 80287.
To practice MCQs on all areas of Microprocessors, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Salient Features of 80386DX”.
1. The 80386DX is a processor that supports
a) 8-bit data operand
b) 16-bit data operand
c) 32-bit data operand
d) all of the mentioned
Answer: d
Explanation: The 80386DX is a 32-bit processor that supports, 8-bit/16-bit/32-bit data operands.
2. The 80386DX has an address bus of
a) 8 address lines
b) 16 address lines
c) 32 address lines
d) 64 address lines
Answer: c
Explanation: The 80386, with its 32-bit address bus, can address up to 4 GB of physical
memory.
3. The number of debug registers that are available in 80386, for hardware debugging and
control is
a) 2
b) 4
c) 8
d) 16
Answer: c
Explanation: The 80386 offers a set of total eight debug registers DR0-DR7, for hardware
debugging and control.
4. The memory management of 80386 supports
a) virtual memory
b) paging
c) four levels of protection
d) all of the mentioned
Answer: d
Explanation: The memory management section of 80386 supports the virtual memory, paging
and four levels of protection, maintaining full compatibility with 80286.
5. The 80386 enables itself to organize the available physical memory into pages, which is
known as
a) segmentation
b) paging
c) memory division
d) none of the mentioned
Answer: b
Explanation: The concept of paging which is introduced in 80386, enables it to organize the
available physical memory into pages of size 4 KB each, under the segmented memory.
6. The 80386 consists of
a) on-chip address translation cache
b) instruction set of predecessors with upward compatibility
c) virtual memory space of 64TB
d) all of the mentioned
Answer: d
Explanation: The 80386 has on-chip address translation cache, and the instruction set is
upward compatible with all its predecessors.
7. 80386DX is available in a grid array package of
a) 64 pin
b) 128 pin
c) 132 pin
d) 142 pin
Answer: c
Explanation: The 80386DX is available in a 132-pin grid array package.
8. The operating frequency of 80386DX is
a) 12 MHz and 20 MHz
b) 20 MHz and 33 MHz
c) 32 MHz and 12 MHz
d) all of the mentioned
Answer: b
Explanation: The operating frequency of 80386DX is 20MHz and 33 MHz.
9. The 80386 in its protected mode, in its virtual mode of operation, can run the applications of
a) 8086
b) 80286
c) 80287
d) 80387
Answer: a
Explanation: The 80386 can run the applications under protected mode, in its virtual 8086 mode
of operation.
10. The 80386 in protected mode, supports all software written for
a) 8086 and 80287
b) 80286 and 80287
c) 80287 and 80387
d) 80286 and 8086
Answer: d
Explanation: The 80386 in protected mode, supports all software written for 8086 and 80286
tobeexecutedunderthecontrolofmemorymanagementandprotectionabilitiesof80386
.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Architecture and Signal Descriptions of 80386”.
1. Which of the units is not a part of the internal architecture of 80386?
a) central processing unit
b) memory management unit
c) bus interface unit
d) none of the mentioned
Answer: d
Explanation: The internal architecture of 80386 is divided into three sections namely, central
processing unit, memory management unit and bus interface unit.
2. The central processing unit has a sub-division of
a) memory unit and control unit
b) memory unit and ALU
c) execution unit and instruction unit
d) execution unit and memory unit
Answer: c
Explanation: The central processing unit is further divided into the execution unit and instruction
unit.
3. The unit that is used for handling data, and calculates offset address is
a) memory management unit
b) execution unit
c) instruction unit
d) bus interface unit
Answer: b
Explanation: The execution unit has eight general purpose and eight special purpose registers,
which are either used for handling the data or calculating the offset addresses.
4. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
Answer: c
Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte
instruction code queue, after decoding them so as to pass it to the control section, for deriving
the necessary control signals.
5. The unit that increases the speed of all shift and rotate operations is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
Answer: d
Explanation: The barrel shifter speeds up all shift and rotate operations.
6. The memory management unit consists of
a) segmentation unit
b) paging unit
c) segmentation and paging units
d) none of the mentioned
Answer: c
Explanation: The memory management unit consists of a segmentation unit and a paging unit.
7. The segmentation unit allows
a) maximum size of 4GB segments
b) use of segment address components
c) use of offset address components
d) all of the mentioned
Answer: d
Explanation: The segmentation unit allows the use of two address components. They are:
segment and offset for relocation and sharing of code and data.
8. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit
b) execution unit
c) paging unit
d) instruction unit
Answer: c
Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size
each.
9. The paging unit works under the control of
a) memory management unit
b) segmentation unit
c) execution unit
d) instruction unit
Answer: b
Explanation: The paging unit works under the control of the segmentation unit; i.e. each
segment is further divided into pages.
10. The unit that provides a four level protection mechanism, for system’s code and data against
application program is
a) central processing unit
b) segmentation unit
c) bus interface unit
d) none of the mentioned
Answer: b
Explanation: The segmentation unit provides a four level protection mechanism, for protecting
and isolating the system’s code and data, from those of the application program.
11. The unit that has a prioritizer to resolve the priority of the various bus requests is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
Answer: c
Explanation: The bus control unit has a prioritizer to resolve the priority of the various bus
requests.
12. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
Answer: b
Explanation: The data buffer interfaces the internal data bus with the system bus.
13. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit
b) bus driving unit
c) address driver
d) bus driver
Answer: c
Explanation: The address driver drives the bus enable and address signals A0-A31.
14. Which of the following pin when activated, allows address pipelining?
a) ADS
b) NA
c) AP
d) None of the mentioned
Answer: b
Explanation: The Next Address
NA
input pin, if activated, allows address pipelining, during 80386 bus cycles.
15. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD
b) HLDA
c) READY
d) PEREQ
Answer: c
Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for
interfacing of slow devices with the CPU.
16. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY
b) NMI
c) HLDA
d) PEREQ
Answer: d
Explanation: The Processor Extension Request
PEREQ
output signal indicates to the CPU to fetch a data word for the coprocessor.
17. The pipeline and dynamic bus sizing units handle
a) data signals
b) address signals
c) control signals
d) all of the mentioned
Answer: c
Explanation: The pipeline and dynamic bus sizing units handle the related control signals.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Register Organisation of 80386 -1”.
1. The 16-bit registers are available with their extended size of 32 bits, by adding the registers
with a prefix of
a) X
b) E
c) 32
d) XX
Answer: b
Explanation: A 32 bit register, known as an extended register, is represented by the register
name with a prefix of E.
2. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by
a) LSP
b) FSP
c) SP
d) None of the mentioned
Answer: c
Explanation: Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the
names BP, SP, SI and DI represent the lower 16-bits.
3. Which of the following is a data segment register of 80386?
a) ES
b) FS
c) GS
d) All of the mentioned
Answer: d
Explanation: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out
of which DS, ES, FS and GS are the four data segment registers.
4. The register width used by the 32-bit addressing modes is
a) 8 bits
b) 16 bits
c) 32 bits
d) all of the mentioned
Answer: d
Explanation: The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.
5. The flag that is additional in flag register of 80386, compared to that of 80286 is
a) VM flag
b) RF flag
c) VM and RF flag
d) None of the mentioned
Answer: c
Explanation: The VM and RF flags are added to the 80286 flag register, to derive the flag
register of 80386.
6. The VM
virtualmode
flag is to be set, only when 80386 is in
a) virtual mode
b) protected mode
c) either virtual or protected mode
d) all of the mentioned
Answer: b
Explanation: If VM flag is set, the 80386 enters the virtual 8086 mode within the protected
mode. This is to be set only when the 80386 is in protected mode.
7. In protected mode of 80386, the VM flag is set by using
a) IRET instruction
b) Task switch operation
c) IRET instruction or task switch operation
d) None of the mentioned
Answer: c
Explanation: The VM flag can be set using the IRET instruction or any task switch operation,
only in the protected mode.
8. During the instruction cycle of 80386, any debug fault can be ignored if
a) VM flag is set
b) VM flag is cleared
c) RF is cleared
d) RF is set
Answer: d
Explanation: If RF
resumeflag
is set, any debug fault is ignored during the instruction cycle.
9. The RF is not automatically reset after the execution of
a) IRET
b) POPA
c) IRET and POPF
d) IRET and PUSHF
Answer: c
Explanation: The RF is automatically reset after the execution of every instruction, except for the
IRET and POPF instructions. Also, it is not cleared automatically after the successful execution
of JMP, CALL and INT instructions causing a task switch.
10. The segment descriptor register is used to store
a) attributes
b) limit address of segments
c) base address of segments
d) all of the mentioned
Answer: d
Explanation: The segment descriptor register is used to store the descriptor information like
attributes, limit and base addresses of segments.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Multiple Choice Questions & Answers focuses on “Register
Organisation of 80386 -2”.
1. The 32-bit control register, that is used to hold global machine status, independent of the
executed task is
a) CR0
b) CR2
c) CR3
d) All of the mentioned
Answer: d
Explanation: The 80386 has three 32-bit control registers CR0, CR2 and CR3, to hold global
machine status, independent of the executed task.
2. The descriptor table that the 80386 supports is
a) GDT
Globaldescriptortable
b) IDT
Interruptdescriptortable
c) LDT
Localdescriptortable
d) All of the mentioned
Answer: d
Explanation: The 80386 supports four types of descriptor tables. They are, GDT, IDT, LDT and
TSS.
3. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR
Answer: a
Explanation: The GDTR and IDTR are known as system address registers.
4. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) None of the mentioned
Answer: b
Explanation: The LDTR and TR are known as system segment registers.
5. The test register
that is provided by 80386 for page caching is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers
Answer: c
Explanation: Two test registers are provided by 80386 for page caching, namely test control and
test status registers.
6. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7
Answer: b
Explanation: Out of the eight debug registers, the two registers DR4 and DR5 are Intel reserved.
7. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3
Answer: d
Explanation: The initial four registers, DR0-DR3 store four program controllable break point
addresses.
8. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned
Answer: a
Explanation: The registers DR6 and DR7 respectively hold break point status and break point
control information.
9. The flag bits that indicate the privilege level of current IO operations are
a) Virtual mode flag bits
b) IOPL flag bits
c) Resume flag bits
d) None of the mentioned
Answer: b
Explanation: The IOPL flag bits indicate the privilege level of current IO operations.
10. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers
Answer: c
Explanation: The segment descriptor registers of 80386 are not available for programmers,
rather, they are internally used to store the descriptor information.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Addressing Modes of 80386, Data Types of 80386”.
1. Which of the following is not a scale factor of addressing modes of 80386?
a) 2
b) 4
c) 6
d) 8
Answer: c
Explanation: In case of the scaled the modes, any of the index register values can be multiplied
by a valid scale factor to obtain the displacement. The valid scale factors are 1, 2, 4 and 8.
2. Contents of an index register are multiplied by a scale factor that may be added further to get
the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
Answer: b
Explanation: In scaled indexed mode, contents of an index register are multiplied by a scale
factor that may be added further to get the operand offset.
3. Contents of an index register are multiplied by a scale factor and then added to base register
to get the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
Answer: a
Explanation: In base scaled indexed mode, contents of an index register are multiplied by a
scale factor and then added to base register to get the operand offset.
4. In the based scaled indexed mode with displacement mode, the contents of an index register
are multiplied by a scale factor and are added to
a) base register
b) displacement
c) base register and displacement
d) none of the mentioned
Answer: c
Explanation: Contents of an index register are multiplied by a scale factor and the result is
added to a base register and a displacement to get the offset of an operand.
5. The following statement of ALP is an example of
MOV EBX, [EDX*4] [ECX].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
Answer: a
Explanation: Since in base scaled indexed mode, contents of an index register are multiplied by
a scale factor and then added to base register to get the operand offset.
6. The following statement is an example of
MOV EBX, LIST [ESI*2].
MUL ECX, LIST [EBP*4].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
Answer: b
Explanation: Since in scaled indexed mode, contents of an index register are multiplied by a
scale factor that may be added further to get the operand offset.
7. Bit field can be defined as a group of
a) 8 bits
b) 16 bits
c) 32 bits
d) 64 bits
Answer: c
Explanation: A group of at the most 32 bits
4bytes
is defined as a bit field.
8. The maximum length of the string in a bit string of contiguous bits is
a) 2 MB
b) 4 MB
c) 2 GB
d) 4 GB
Answer: d
Explanation: Bit string is a string of contiguous bits of maximum 4Gbytes in length.
9. The integer word is defined as
a) signed 8-bit data
b) unsigned 16-bit data
c) signed 16-bit data
d) signed 32-bit data
Answer: c
Explanation: The integer word is the signed 16-bit data.
10. A 16-bit displacement that references a memory location using any of the addressing modes
is
a) Pointer
b) Character
c) BCD
d) Offset
Answer: d
Explanation: Offset is a 16-bit or 32-bit displacement that references a memory location using
any of the addressing modes.
11. A decimal digit can be represented by
a) unsigned integer
b) signed integer
c) unpacked BCD
d) packed BCD
Answer: c
Explanation: Decimal digits from 0-9 are represented by unpacked bytes.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Real Address Mode of 80386, Protected Mode of 80386”.
1. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned
Answer: b
Explanation: All the instructions of 80386 are available in this mode except for those designed to
work with or for protected address mode.
2. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit
Answer: c
Explanation: The paging unit is disabled in real address mode.
3. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned
Answer: d
Explanation: To form a physical memory address, appropriate segment register contents are
shifted by left by 4 positions and then added to 16-bit offset address formed using one of
addressing modes, in same way as in the 80386 real address mode.
4. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d) none of the mentioned
Answer: c
Explanation: The segments in 80386 real mode are may be overlapped or non-overlapped.
5. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned
Answer: d
Explanation: The segments in 80386 real mode can be read, written or executed, i.e. no
protection is available.
6. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned
Answer: d
Explanation: In protected mode, the contents of segment registers are used as selectors to
address descriptors which contain the segment limit, base address and access rights byte of the
segment.
7. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address
Answer: a
Explanation: The effective address
offset
is added with segment base address to calculate linear address.
8. If the paging unit is enabled, then it converts a linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
Answer: b
Explanation: The paging unit when enabled, it converts a linear address into physical address.
9. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
Answer: b
Explanation: The linear address is used as a physical address if the paging unit is disabled.
10. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned
Answer: c
Explanation: The paging unit is enabled only in protected mode.
11. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB
Answer: d
Explanation: In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of
virtual memory per task.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Segmentation”.
1. The bit that indicates whether the segment has been accessed by the CPU or not is
a) base address
b) attribute bit
c) present bit
d) granular bit
Answer: b
Explanation: The accessed bit or attribute bit
A
indicates whether the segment has been accessed by the CPU or not.
2. The TYPE field of a descriptor is used to find the
a) descriptor type
b) segment type
c) descriptor and segment type
d) none
Answer: c
Explanation: The type field decides the descriptor type and hence the segment type.
3. If the segment descriptor bit, S=0, then the descriptor is
a) data segment descriptor
b) code segment descriptor
c) system descriptor
d) all of the mentioned
Answer: c
Explanation: If S=0, then system descriptor. If S=1, then code or data segment descriptor.
4. The bit that indicates whether the segment is page addressable is
a) base address
b) attribute bit
c) present bit
d) granularity bit
Answer: d
Explanation: The granularity bit indicates whether the segment is page addressable.
5. If the Default operation size bit, D=1, the code segment operation size selected is
a) 8-bit
b) 16-bit
c) 32-bit
d) 64-bit
Answer: c
Explanation: If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand
segment.
6. The segment descriptor contains
a) access rights
b) limit
c) base address
d) all of the mentioned
Answer: d
Explanation: The segment descriptors are 8-byte quantities containing access right or attribute
bits along with the base and limit of the segments.
7. Which of the following is not a type of segment descriptor?
a) system descriptors
b) local descriptors
c) gate descriptors
d) none
Answer: d
Explanation: The five types of segment descriptors of 80386 are:
1. Code or data segment descriptors
2. System descriptors
3. Local descriptors
4. TSS
taskstatesegment
descriptors
5. Gate descriptors.
8. The limit field of the descriptor is of
a) 10 bits
b) 8 bits
c) 16 bits
d) 20 bits
Answer: d
Explanation: The limit field of the descriptor is of 20 bits.
9. The starting address of the segment in physical memory is decided by
a) physical memory
b) segment descriptors
c) operating system
d) base address
Answer: c
Explanation: The base address that marks the starting address of the segment in physical
memory is decided by the operating system and is of 32 bits.
10. The total descriptors that the 80386 can handle is
a) 2K
b) 8K
c) 4K
d) 16K
Answer: d
Explanation: 80386 can handle total 16K descriptors and hence segments.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Paging”.
1. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
Answer: d
Explanation: The advantage of paging scheme is that the complete segment of a task need not
be in the physical memory at any time. Only a few pages of the segments, which are required
currently for the execution, need to be available in the physical memory.
2. The size of the pages in the paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
Answer: b
Explanation: The paging divides the memory into fixed size pages.
3. To convert linear addresses into physical addresses, the mechanism that the paging unit uses
is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
Answer: d
Explanation: The paging unit of 80386 uses a two level table mechanism, to convert the linear
addresses provided by the segmentation unit, into physical addresses.
4. The control register that stores the 32-bit linear address, at which the previous page fault is
detected is
a) CR0
b) CR1
c) CR2
d) CR3
Answer: c
Explanation: The control register, CR2, is used to store the 32-bit linear address, at which the
previous page fault is detected.
5. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
Answer: b
Explanation: The paging unit handles every task in terms of three components namely page
directory, page table and the page itself.
6. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
Answer: d
Explanation: The control register, CR3, is used as page directory physical base address
register, to store the physical starting address of the page directory.
7. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
Answer: d
Explanation: The lower 12 bits of CR3 are always zero to ensure the page size aligned with the
directory.
8. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
Answer: b
Explanation: Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a
directory.
9. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
Answer: c
Explanation: Each page table is of 4 Kbytes in size, and may contain a maximum of 1024
entries.
10. The dirty bit
is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
Answer: a
Explanation: The dirty bit
D
is set before a write operation to the page is carried out.
11. The bit that is undefined for page directory entries is
a) P-bit
b) A-bit
c) D-bit
d) All of the mentioned
Answer: c
Explanation: The D-bit is undefined for page directory entries.
12. The bit that is used for providing protection is
a) User/Supervisor bit
b) Read bit
c) Write bit
d) all of the mentioned
Answer: d
Explanation: The User/Supervisor
U/S
bit and Read/Write
R/W
bit are used to provide protection.
13. The storage of 32 recently accessed page table entries to optimize the time, is known as
a) page table
b) page descriptor base register
c) page table cache
d) none of the mentioned
Answer: c
Explanation: To optimize the considerable time taken for conversion, a page table cache is
provided, which stores the 32 recently accessed page table entries.
14. The page table cache is also known as
a) page table storage
b) storage buffer
c) translation look aside buffer
d) all of the mentioned
Answer: c
Explanation: The page table cache is also known as translation look aside buffer.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Virtual 8086 Mode, the Coprocessor 80387”.
1. If the 80386 enters the protected mode from the real address mode, then it returns back to
the real mode, by performing the operation of
a) read
b) write
c) terminate
d) reset
Answer: d
Explanation: If the 80386 enters the protected mode from the real address mode, then it cannot
return back to the real mode without a reset operation.
2. The unit that is needed for virtual mode 80386, only to run the 8086 programs, which require
more than 1 Mbyte of memory for memory management functions, is
a) execution unit
b) central processing unit
c) paging unit
d) segmentation unit
Answer: c
Explanation: Paging unit is not necessarily enabled in the virtual mode, but may be needed to
run the 8086 programs, which require more than 1 Mbyte of memory, for memory management
functions.
3. The number of pages that the paging unit allows, in the virtual mode of 80386 is
a) 64
b) 128
c) 256
d) 512
Answer: c
Explanation: In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size. Each
of the pages may be located anywhere within the maximum 4Gbytes physical memory.
4. The privilege level at which the real mode programs are executed is
a) level 0
b) level 1
c) level 2
d) level 3
Answer: a
Explanation: The real mode programs are executed at the highest privilege level i.e. level 0.
5. The instructions to prepare the processor for protected mode can only be executed at the
privilege level
a) level 0
b) level 1
c) level 2
d) level 3
Answer: a
Explanation: The instructions to prepare the processor for protected mode can only be executed
at the level 0.
6. The instruction that is unable to set or read the VM
VirtualMode
bit is
a) PUSHF
b) IRET
c) POPF
d) PUSHF and POPF
Answer: d
Explanation: The PUSHF and POPF instructions are unable to set or read the VM
VirtualMode
bit, as they do not access it. The virtual mode can be entered by using IRET instruction.
7. If the CKM pin of 80387 is high, then 80387 is operated in
a) real address mode
b) protected mode
c) synchronous mode
d) asynchronous mode
Answer: c
Explanation: If the CKM pin of 80387 is high, then 80387 is operated in synchronous mode. If it
is low, then 80387 is operated in asynchronous mode.
8. The unit that handles the data and directs it to either FIFO or instruction decoder depending
on the bus control logic directive is
a) paging unit
b) central processing unit
c) segmentation unit
d) data interface and control unit
Answer: d
Explanation: The data interface and control unit handles the data, and direct it to either FIFO or
instruction decoder, depending on the bus control logic directive.
9. The unit that is responsible for carrying out all the floating point calculations, allotted to the
coprocessor by 80386, is
a) Central processing unit
b) ALU
c) FPU
d) None of the mentioned
Answer: c
Explanation: The FPU
floatingpointunit
is responsible for carrying out all the floating point calculations, allotted to the coprocessor by
80386.
10. The sizes of instruction and data pointer registers of 80387 respectively are
a) 32-bit, 32-bit
b) 48-bit, 32-bit
c) 32-bit, 48-bit
d) 48-bit, 48-bit
Answer: d
Explanation: 80387 consists of two 48-bit registers, known as instruction and data pointer
registers.
11. To inform 80387 that the CPU wants to communicate with NPS1, the NPS1 line is directly
connected to
a) A31
b) A30
c) M/IO
d) D31
Answer: c
Explanation: The NPS1 and NPS2 lines are directly connected with M/IO and A31 respectively,
to inform 80387 that the CPU wants to communicate with it
NPS1
, and it is using one of the reserved I/O addresses for 80387
NPS2
.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Enhanced Instruction Set of 80386”.
1. Which of the following is not a newly added instruction of 80386, that are not present in
80286?
a) bit scan instructions
b) bit test instructions
c) shift double instructions
d) none of the mentioned
Answer: d
Explanation: The newly added instructions of 80386 are categorized into
1. bit scan instructions
2. bit test instructions
3. conditional set byte instructions
4. shift double instructions
5. control transfer via gates instructions.
2. The BSF
bitscanforward
instruction scans the operand in the order
a) from left to right
b) from right to left
c) from upper nibble
d) none of the mentioned
Answer: b
Explanation: The BSF
bitscanforward
instruction scans the operand from right to left.
3. The BSR
bitscanreverse
instruction scans the operand in the order
a) from left to right
b) from right to left
c) from upper nibble
d) none of the mentioned
Answer: a
Explanation: The BSR
bitscanreverse
instruction scans the operand from left to right.
4. If a ‘1’ is encountered when an operand is scanned by BSF, then
a) zero flag is reset
b) zero flag is set
c) VM flag is set
d) RF flag is reset
Answer: b
Explanation: The BSF instruction scans the operand from right to left. If a ‘1’ is encountered
during the scan, zero flag is set, and the bit position of ‘1’ is stored into the destination operand.
5. If a ‘1’ is not encountered when an operand is scanned by BSR, then
a) zero flag is reset
b) zero flag is set
c) VM flag is reset
d) RF flag is set
Answer: a
Explanation: The BSR instruction scans the operand from left to right. If a ‘1’ is not encountered
during the scan, zero flag is reset whether the scan is BSF or BSR.
6. Which of the following is not a bit test instruction?
a) BTC
b) BTS
c) BSF
d) BTR
Answer: c
Explanation: The instruction, BSF, is a bit scan instruction. The four bit test instructions are:
BT
TestaBit
, BTC
TestaBitandComplement
, BTR
TestandResetaBit
and BTS
TestandSetabit
.
7. In case of BT instruction, if the bit position in the destination operand specified by the source
operand, is ‘1’, then
a) zero flag is reset
b) carry flag is set
c) VM flag is set
d) RF flag is reset
Answer: b
Explanation: In case of BT instruction, if the bit position in the destination operand specified by
the source operand, is ‘1’, the carry flag is set, otherwise it is cleared.
8. Which of the following is not a conditional set byte instruction?
a) SETNP
b) SETO
c) SETNAE
d) SHRD
Answer: d
Explanation: The SHRD
ShiftRightDouble
is a shift double instruction.
9. The instruction that shifts the specified number of bits in the instruction, from the upper side
of the source operand into the lower side of the destination operand is
a) SHRD
b) SHLD
c) SETNS
d) None of the mentioned
Answer: b
Explanation: The SHLD instruction shifts the specified number of bits in the instruction, from the
upper side
i.e.MSB
of the source operand into the lower side
i.e.LSB
of the destination operand.
10. The instruction that shifts 8 LSB bits of ECX into the MSB positions of EAX, one by one
starting from LSB of ECX is
a) SHLD ECX,EAX,8
b) SHLD EAX,ECX,8
c) SHRD ECX,EAX,8
d) SHRD EAX,ECX,8
Answer: d
Explanation: The SHRD instruction shifts the specified number of bits in the instruction, from the
lower side
i.e.LSB
of the source operand into the upper side
i.e.MSB
of the destination operand.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Numeric Coprocessor – 80486DX”.
1. The first processor with an inbuilt floating point unit is
a) 80386
b) 80486
c) 80286
d) 8086
Answer: b
Explanation: The 32-bit CPU 80486 from Intel is the first processor with an inbuilt floating point
unit. 80486DX is the first CPU with an on chip floating point unit.
2. Which of the following signal is handled by bus control and request sequencer?
a) ADS#
b) PWT
c) RDY#
d) All of the mentioned
Answer: d
Explanation: The bus control and request sequencer handle the signals like ADS#, PWT, RDY#,
W/R#, INTR, NMI, LOCK#, HOLD, HLDA, RESET and M/IO# which basically controls the bus
access and operations.
3. The unit that subjects the processor operation to boundary scan tests is
a) parity generation and control unit
b) prefetcher unit
c) boundary scan and control unit
d) segmentation unit
Answer: c
Explanation: The boundary scan and control unit subjects the processor operation to boundary
scan tests to ensure the correct operation of various components of the mother board.
4. The management of the virtual memory of the system and adequate protection to data or
codes in the physical memory is provided by
a) segmentation unit
b) paging unit
c) attribute PLA
d) all of the mentioned
Answer: d
Explanation: The segmentation unit, paging unit, attribute PLA, descriptor registers, translation
look aside buffer and limit work together to manage the virtual memory of the system and
provide the adequate protection to the codes or data in the physical memory.
5. The flag that is added to 80486 in additional to the flags similar to 80386 is
a) alignment check flag
b) parity check flag
c) conditional flag
d) all of the mentioned
Answer: a
Explanation: The register set of 80486 is similar to that of the 80386 but only a flag called as
alignment check flag is added to the flag register of 80386 to obtain the flag register of 80486.
6. The major limitation of 80386-387 system is
a) low speed
b) 80386 sends data using an I/O handshake technique
c) 80386 returns to real mode by reset operation
d) none of the mentioned
Answer: b
Explanation: The major limitation of 80386-387 system is that the 80386 sends instruction or
data to 80387 using an I/O handshake technique. To perform this handshaking and to carry
additional house keeping tasks, 80386 requires 15 clock cycles or more.
7. The datatype that the 80486 doesnot support is
a) Signed and unsigned
b) ASCII
c) Floating point
d) None
Answer: d
Explanation: The datatypes that 80486 supports are
1. Signed
2. Unsigned
3. Floating point
4. BCD
5. String
6. ASCII.
8. In Little Endian data format, the data is stored as
a) MSB is stored at lower memory address and LSB at higher memory address
b) LSB is stored at lower memory address and MSB at higher memory address
c) MSB is stored at general purpose registers
d) LSB is stored at general purpose registers
Answer: b
Explanation: In Little Endian data format, for a data of size bigger than 1 byte, the LSB is stored
at lower memory address and MSB at higher memory address.
9. The on-chip cache is used for storing
a) addresses of data
b) opcodes and data
c) data and their addresses
d) opcodes and their addresses
Answer: b
Explanation: The unique feature of 80486 that is not available in 80386 is that the on-chip is
used for storing opcodes and data.
10. The on-chip cache is controlled by
a) Cache disable
CD
b) No write through
NW
c) Cache disable and No write through
d) None of the mentioned
Answer: c
Explanation: Cache disable
CD
and No write through
NW
bits of control register CR0. To completely disable cache, the CD and NW bits must be 11.
11. The on-chip cache can be flushed using external hardware using
a) FLUSH pin
b) TERMINATE pin
c) FLOW pin
d) Pin FLUSH# or using software
Answer: d
Explanation: The on-chip cache can be flushed using external hardware using pin FLUSH# or
using the software. The flushing operation clears all the valid bits for all the cache lines.
To practice all areas of Microprocessors and Micro-controllers, here is complete set of 1000+
Multiple Choice Questions and Answers .
This set of Microprocessors online test focuses on “Features of 80586
Pentium
, Concepts of Computer Architecture, Branch Prediction”.
1. The salient feature of Pentium is
a) superscalar architecture
b) superpipelined architecture
c) superscalar and superpipelined architecture
d) none of the mentioned
Answer: c
Explanation: The salient feature of Pentium is its superscalar, superpipelined architecture.
2. The number of stages of the integer pipeline, U, of Pentium is
a) 2
b) 4
c) 3
d) 6
Answer: b
Explanation: The Pentium has two integer pipelines, U and V, where each one is a 4-stage
pipeline.
3. Which of the following is a cache of Pentium?
a) data cache
b) data cache and instruction cache
c) instruction cache
d) none of the mentioned
Answer: b
Explanation: The Pentium has two separate caches. They are data cache and instruction cache.
4. The speed of integer arithmetic of Pentium is increased to a large extent by
a) on-chip floating point unit
b) superscalar architecture
c) 4-stage pipelines
d) all of the mentioned
Answer: c
Explanation: The Pentium has two integer pipelines, U and V, where each one is a 4-stage
pipeline. This enhances the speed of integer arithmetic of Pentium to a large extent.
5. For enhancement of processor performance, beyond one instruction per cycle, the computer
architects employ the technique of
a) super pipelined technique
b) multiple instruction issue
c) super pipelined technique and multiple instruction issue
d) none of the mentioned
Answer: b
Explanation: For enhancement of processor performance, beyond one instruction per cycle, the
computer architects employ the technique of multiple instruction issue.
6. Which of the following is a class of architecture of MII
multipleinstructionissue
a) super pipelined architecture
b) multiple instruction issue
c) very small instruction word architecture
d) super scalar architecture
Answer: d
Explanation: The MII architecture may again be classified into two categories:
1. Very long instruction word architecture
2. Superscalar architecture.
7. The compiler reorders the sequential stream of code that is coming from memory into a fixed
size instruction group in
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) super scalar architecture
Answer: c
Explanation: In VLIW processors, the compiler reorders the sequential stream of code that is
coming from memory into a fixed size instruction group, and issues them in parallel for
execution.
8. The architecture in which the hardware decides which instructions are to be issued
concurrently at run time is
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) superscalar architecture
Answer: d
Explanation: In the superscalar architecture, the hardware decides which instructions are to be
issued concurrently at run time.
9. The CPU has to wait until the execution stage to determine whether the condition is met in
a) unconditional branch
b) conditional branch
c) pipelined execution branch
d) none of the mentioned
Answer: b
Explanation: In conditional branch, the CPU has to wait until the execution stage to determine
whether the condition is met or not. When the condition satisfies, a branch is to be taken.
10. The memory device that holds branch target addresses for previously executed branches is
a) Tristate buffer
b) RAM
c) ROM
d) Branch target buffer
Answer: d
Explanation: The branch target buffer in Pentium CPU holds branch target addresses for
previously executed branches.
11. The branch target buffer is
a) four-way set-associative memory
b) has branch instruction address
c) has destination address
d) all of the mentioned
Answer: d
Explanation: The branch target buffer is a four-way set-associative memory. Whenever a branch
is taken, the CPU enters the branch instruction address, and also the destination address in the
branch target buffer.
To practice all areas of Microprocessors for online tests, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “System Architecture”.
1. The stage in which the CPU fetches the instructions from the instruction cache in superscalar
organization is
a) Prefetch stage
b) D1
firstdecode
stage
c) D2
seconddecode
stage
d) Final stage
Answer: a
Explanation: In the prefetch stage of pipeline, the CPU fetches the instructions from the
instruction cache, which stores the instructions to be executed. In this stage, CPU also aligns
the codes appropriately.
2. The CPU decodes the instructions and generates control words in
a) Prefetch stage
b) D1
firstdecode
stage
c) D2
seconddecode
stage
d) Final stage
Answer: b
Explanation: In D1 stage, the CPU decodes the instructions and generates control words. For
simple RISC instructions, only single control word is enough for starting the execution.
3. The fifth stage of pipeline is also known as
a) read back stage
b) read forward stage
c) write back stage
d) none of the mentioned
Answer: c
Explanation: The fifth stage or final stage of pipeline is also known as “Write back
WB
stage”.
4. In the execution stage the function performed is
a) CPU accesses data cache
b) executes arithmetic/logic computations
c) executes floating point operations in execution unit
d) all of the mentioned
Answer: d
Explanation: In the execution stage, known as E-stage, the CPU accesses data cache,
executes arithmetic/logic computations, and floating point operations in execution unit.
5. The stage in which the CPU generates an address for data memory references in this stage
is
a) prefetch stage
b) D1
firstdecode
stage
c) D2
seconddecode
stage
d) execution stage
Answer: c
Explanation: In the D2
seconddecode
stage, CPU generates an address for data memory references in this stage. This stage is
required where the control word from D1 stage is again decoded for final execution.
6. The feature of separated caches is
a) supports the superscalar organization
b) high bandwidth
c) low hit ratio
d) all of the mentioned
Answer: d
Explanation: The separated caches have low hit ratio compared to a unified cache, but have the
advantage of supporting the superscalar organization and high bandwidth.
7. In the operand fetch stage, the FPU
FloatingPointUnit
fetches the operands from
a) floating point unit
b) instruction cache
c) floating point register file or data cache
d) floating point register file or instruction cache
Answer: c
Explanation: In the operand fetch stage, the FPU
FloatingPointUnit
fetches the operands from either floating point register file or data cache.
8. The FPU
FloatingPointUnit
writes the results to the floating point register file in
a) X1 execution state
b) X2 execution state
c) write back stage
d) none of the mentioned
Answer: c
Explanation: In the two execution stages of X1 and X2, the floating point unit reads the data
from the data cache and executes the floating point computation. In the “write back stage” of
pipeline, the FPU
FloatingPointUnit
writes the results to the floating point register file.
9. The floating point multiplier segment performs floating point multiplication in
a) single precision
b) double precision
c) extended precision
d) all of the mentioned
Answer: d
Explanation: The floating point multiplier segment performs floating point multiplication in single
precision, double precision and extended precision.
10. The instruction or segment that executes the floating point square root instructions is
a) floating point square root segment
b) floating point division and square root segment
c) floating point divider segment
d) none of the mentioned
Answer: c
Explanation: The floating point divider segment executes the floating point division and square
root instructions.
11. The floating point rounder segment performs rounding off operation at
a) after write back stage
b) before write back stage
c) before arithmetic operations
d) none of the mentioned
Answer: b
Explanation: The results of floating point addition or division process may be required to be
rounded off, before write back stage to the floating point registers.
12. Which of the following is a floating point exception that is generated in case of integer
arithmetic?
a) divide by zero
b) overflow
c) denormal operand
d) all of the mentioned
Answer: d
Explanation: In the case of integer arithmetic, the possible floating point exceptions in Pentium
are:
1. divide by zero
2. overflow
3. denormal operand
4. underflow
5. invalid operation.
13. The mechanism that determines whether a floating point operation will be executed without
creating any exception is
a) Multiple Instruction Issue
b) Multiple Exception Issue
c) Safe Instruction Recognition
d) Safe Exception Recognition
Answer: c
Explanation: A mechanism known as Safe Exception Recognition
SER
had been employed in Pentium which determines whether a floating point operation will be
executed without creating any exception.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Tricky Microprocessors Questions and Answers focuses on “Enhanced Instruction
Set of Pentium, Intel MMX Architecture”.
1. Which of the following is not a transcendental instruction?
a) FSIN
b) FCOS
c) FMUL
d) FPTAN
Answer: c
Explanation: The FMUL instruction is a float point multiplication, which is not a transcendental
instruction.
2. The transcendental instruction that supports computation of sine and cosine is
a) FCOSSIN
b) FSNE
c) FSINFCOS
d) FSINCOS
Answer: d
Explanation: The instruction, FSINCOS, supports to compute sine and cosine.
3. The instruction that computes tan
is
a) FTAN
b) FTNGNT
c) FPTAN
d) FXTAN
Answer: c
Explanation: The instruction, FPTAN, computes tan
x
.
4. The instruction that computes arctan
is
a) FTAN
b) FACTN
c) FARCTAN
d) FPATAN
Answer: d
Explanation: The instruction, FPATAN, computes arctan
x
which is arc tangent of x.
5. The instruction, F2XMI, is used to compute
a) 2X
b) 2X-1
c) 2X+1
d) 2X+2
Answer: b
Explanation: The instruction, F2XMI, is used to compute 2X-1.
6. The instruction, FYL2XP, supports to compute the expression
a) Y*logX
b) Y*log2X
c) Y*log
2X+1
d) Y*log2
X+1
Answer: d
Explanation: The instruction, FYL2XP, supports to compute the expression Y*log2
X+1
.
7. The size of a general purpose floating point register of floating point unit is
a) 4 bytes
b) 40 bytes
c) 8 bytes
d) 80 bits
Answer: d
Explanation: There are eight general purpose floating point registers in the floating point unit.
Each of these eight registers are of 80-bits width.
8. For floating point operations, the bits used by mantissa in a floating point register is
a) 32
b) 64
c) 72
d) 79
Answer: b
Explanation: For floating point operations, 64 bits are used for the mantissa, and the rest 16 bits
for exponent.
9. The multimedia applications mainly require the architecture of
a) single instruction stream single data stream
b) multiple instruction stream single data stream
c) single instruction stream multiple data stream
d) multiple instruction stream multiple data stream
Answer: c
Explanation: Most of the multimedia applications mainly require the architecture of single
instruction stream multiple data stream.
10. The size of each MMX
MultimediaExtension
register is
a) 32 bits
b) 64 bits
c) 128 bits
d) 256 bits
Answer: b
Explanation: The MMX registers use only the 64-bit mantissa portion of the general purpose
floating point registers, to store MMX operands. Thus, the MMX programmers virtually get eight
new MMX registers, each of 64 bits.
11. After a sequence of MMX instructions is executed, the MMX registers should be cleared by
an instruction,
a) CLEAR
b) RESET
c) EMM
d) EMMS
Answer: d
Explanation: After a sequence of MMX instructions is executed, the MMX registers should be
cleared by an instruction, EMMS, which implies Empty the MMX Stack.
12. The number of pixels that can be manipulated in a single register by the CPU using MMX
architecture is
a) 4
b) 6
c) 8
d) 10
Answer: c
Explanation: Any CPU can manipulate only one pixel at a time. But by using MMX architecture,
we can manipulate eight such pixels, packed in a single 64-bit register.
13. After executing the floating point instructions, the floating point registers should be cleared
by an instruction,
a) CLEAR
b) EFPR
c) EMMF
d) EMMS
Answer: d
Explanation: After executing the floating point instructions, the floating point registers should be
cleared by an instruction, EMMS.
To practice tricky questions and answers on all areas of Microprocessors, here is complete set
of 1000+ Multiple Choice Questions and Answers .
This set of Microprocessors online quiz focuses on “MMX Data Types, Wrap-around and
Saturation Arithmetic, Multimedia Application Programming, Pentium III
P−III
CPU”.
1. In the data type, packed byte, the number of bytes that can be packed into one 64-bit quantity
is
a) 2
b) 4
c) 8
d) 16
Answer: c
Explanation: In packed byte data type, eight bytes can be packed into one 64-bit quantity.
2. Four words can be packed into 64-bit by using the data type,
a) unpacked word
b) packed word
c) packed doubled word
d) one quad word
Answer: b
Explanation: By using the packed word data type, four words can be packed into 64-bits.
3. The number of double words that can be packed into 64-bit register using packed double
word is
a) 2
b) 4
c) 6
d) 8
Answer: a
Explanation: Using packed double word, two double words can be packed into 64-bit.
4. The data type, “one quad word” packs __________ into 64-bit.
a) two 32-bit quantities
b) four 16-bit words
c) one 32-bit and two 16-bit quantities
d) one single 64-bit quantity
Answer: d
Explanation: The data type, “one quad word” packs one single 64-bit quantity into 64-bit register.
5. If the result of an operation is overflowed
exceededthan16bits
or underflowed then, only the lower 16-bits of the result are stored in the register and this effect
is known as
a) overflow/underflow effect
b) wrap-around effect
c) exceeding memory effect
d) none
Answer: b
Explanation: If the result of an operation is overflowed
exceededthan16bits
or underflowed then, only the lower 16-bits of the result are stored in the register, and this effect
is known as wrap-around effect.
6. In a multitasking operating system environment, each task should return to its own processor
state which is
a) contents of integer registers
b) contents of floating point registers
c) contents of MMX registers
d) all of the mentioned
Answer: d
Explanation: In a multitasking operating system environment, each task should return to its own
processor state, which should be saved when the task switching occurs. The processor state
here means the contents of the registers, both integer and floating point or MMX register.
7. Which of the following exception generated by MMX is the same type of memory access
exception as the X86 instructions?
a) page fault
b) segment not present
c) limit violation
d) all of the mentioned
Answer: d
Explanation: The MMX instruction set generates the same type of memory access exception as
the X86 instructions namely; page fault, segment does not present and limit violation.
8. When an MMX instruction is getting executed, the floating-point tag word is marked
a) 11
b) 10
c) 00
d) 01
Answer: c
Explanation: When an MMX instruction is getting executed, the floating-point tag word is marked
valid i.e. 00.
9. In a preemptive multitasking O.S., the saving and restoring of FP and MMX states are
performed by
a) Control unit
b) O.S.
c) MMX instructions
d) MMX registers
Answer: b
Explanation: In a preemptive multitasking O.S., the application does not know when it is
preemptied. It is the job of the O.S. to save and restore the FP and MMX states, when
performing a context switch. Thus the user need not save or restore the state.
10. The instruction of MMX that is essential when a floating-point routine calls an MMX routine
or viceversa is
a) MOV
b) PADD
c) EMMS
d) None of the mentioned
Answer: c
Explanation: The EMMS instruction is imperative when a floating point routine calls an MMX
routine or vice-versa. If we do not use EMMS at the end of MMX routine, subsequent
floating-point instructions will produce erratic results.
11. Pentium III is used in computers which run on the operating system of
a) windows NT
b) windows 98
c) unix
d) all of the mentioned
Answer: d
Explanation: Pentium III is the best option to use in computers from high performance desktop
to workstations and servers, running on operating systems like Windows NT, Windows 98 and
UNIX.
12. The architecture of CPU of Pentium III is suitable for
a) multimedia
b) image processing
c) speech processing
d) all of the mentioned
Answer: d
Explanation: The architecture of CPU of Pentium III is suitable for applications like imaging,
image processing, speech processing, multimedia and internet applications.
13. The Pentium III has the operating frequencies as
a) 300MHz,350MHz,400MHz
b) 400MHz,450MHz,500MHz
c) 350MHz,400MHz,450MHz
d) 450MHz,500MHz,550MHz
Answer: d
Explanation: The Pentium III has three versions operating at frequencies, 450MHz, 500MHz and
550MHz, which are all commercially available.
14. The Pentium III consists of
a) dual independent bus architecture
b) 512 Kbyte cache
c) eight 64-wide Intel MMX registers
d) all of the mentioned
Answer: d
Explanation: The Pentium III has dual independent bus architecture that increases the
bandwidth. It has a 512 Kbyte unified, non-blocking level2 cache and eight 64-wide Intel MMX
registers.
To practice all areas of Microprocessors for online Quizzes, here is complete set of 1000+
Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “MMX Instruction Set”.
1. The additional instructions that are designed especially for performing multimedia tasks are
known as
a) additional MMX instructions
b) multimedia MMX instructions
c) enhanced MMX instructions
d) none of the mentioned
Answer: c
Explanation: The MMX technology adds 57 new instructions to the instruction set of processors.
These instructions are known as enhanced MMX instructions and are designed specifically for
performing multimedia tasks.
2. The MMX instruction, EMMS consists of __________ on which it operates.
a) source operand
b) destination operand
c) source and destination operand
d) none of the mentioned
Answer: d
Explanation: The instruction, EMMS, does not have any operand.
3. In all the MMX instructions, the destination operand resides in
a) Memory
b) RAM
c) Either in an MMX register or in memory
d) MMX register
Answer: d
Explanation: In all the MMX instructions, the source operand is found either in an MMX register
or in memory, and the destination operand resides in MMX register.
4. For the MMX instructions, the prefix, P, is used to represent the mode of
a) real addressing mode
b) virtual mode
c) packed mode
d) programmable mode
Answer: c
Explanation: In the MMX instructions, if the operands are in the packed mode, the prefix, P, is
used to indicate packed data.
5. For the MMX instructions, the suffix, S, is used to represent
a) status
b) saturation
c) signed saturation
d) unsigned saturation
Answer: c
Explanation: For the MMX instructions, the suffix “S” indicates signed saturation, and “US”
indicates unsigned saturation, while executing arithmetic computation in saturation mode.
6. The instruction that is used for quadword is
a) PADD
b) PCMPEQ
c) PAND
d) None of the mentioned
Answer: d
Explanation: The instructions, PADD, PCMPEQ and PAND are used for packed byte, word and
double word.
7. The instruction, PSUBB, performs subtraction in
a) packed word
b) packed byte
c) packed double word
d) unpacked word
Answer: b
Explanation: The instruction, PSUBB, performs subtraction in a packed byte.
8. The instruction, PCMPGT, is used to compare two data types and check
a) equal to condition
b) less than condition
c) greater than condition
d) equal to and greater than condition
Answer: c
Explanation: The instruction, PCMPGT, compares to check the greater than condition in packed
bytes, packed words and packed double words.
9. The instruction that is not operated on quad word is
a) MOV
b) PSLL
c) PSRA
d) All of the mentioned
Answer: c
Explanation: The instruction, PSRA, performs arithmetic shift, right in a single cycle. It supports
only the shifting of packed word and double word data types.
10. When the instruction, PMULLW, is performed, then the lower order 16-bits of the 32 bit
products are stored in
a) source operand
b) destination operand
c) no storage of lower order
d) either source or destination
Answer: b
Explanation: In the instruction, PMULLW, four 16 X 16 multiplications are performed, and the
lower order 16 bits of the 32-bit products are stored in destination.
11. When the instruction, PMULHW, is performed, then the higher order 16-bits of the 32 bit
products are stored in
a) source operand
b) destination operand
c) no storage of lower order
d) either source or destination
Answer: b
Explanation: In the instruction, PMULHW, four 16 X 16 multiplications are performed, and the
higher order 16 bits of the 32-bit products are stored in destination.
12. The instruction in which both multiplication and addition are performed is
a) PAND
b) PMULHW
c) PADD
d) PMADDWD
Answer: d
Explanation: PMADDWD is an important multimedia instruction, which multiplies the four signed
words of the destination operand, with four signed words of source operand. This results in
32-bit double words which are added, and the result is stored in the higher double word of the
destination operand.
13. If the result of PCMPEQ, which is a comparison of two packed data types, is a success, then
the mask generated is
a) mask 0s
b) mask 1s
c) mask 2s
d) mask 3s
Answer: b
Explanation: If the result of PCMPEQ, which is a comparison of two packed data types is a
success, then the mask 1s is generated, otherwise a mask of 0s is generated, in the destination
operand.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Pentium – Pro and Pentium-II -1”.
1. The instructions that pass through the fetch, decode and execution stages sequentially is
known as
a) sequential instruction
b) sequence of fetch, decode and execution
c) linear instruction sequencing
d) non-linear instruction sequencing
Answer: c
Explanation: The linear instruction sequencing is the one in which the instructions that pass
through the fetch, decode and execution stages sequentially.
2. During the execution of instructions, if an instruction is executed, then next instruction is
executed only when the data is read by
a) control unit
b) bus interface unit
c) execution unit
d) cpu
Answer: b
Explanation: During the execution of instructions, only after the bus interface unit of CPU reads
the data from the main memory and returns it to the register, the next instruction execution will
commence.
3. Because of Pentium’s superscalar architecture, the number of instructions that are executed
per clock cycle is
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: Pentium’s superscalar architecture employs five stage pipeline with U and V pipes.
Thus it can execute two instructions per clock.
4. The type of execution which means that the CPU should speculate which of the next
instructions can be executed earlier is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
Answer: a
Explanation: The speculative execution is an execution which means that the CPU should
speculate which of the next instructions can be executed earlier.
5. The execution in which the consecutive instruction execution in a sequential flow is hampered
is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
Answer: b
Explanation: In the out of turn execution, the consecutive instruction execution in a sequential
flow is hampered and the CPU should be able to execute out of turn instructions.
6. A dual independent bus has
a) Enhanced system bandwidth
b) CPU that can access both cache and memory simultaneously
c) High throughput
d) All of the mentioned
Answer: d
Explanation: A dual independent bus architecture is incorporated by Pentium-Pro to get an
enhanced system bandwidth and it also yields high throughput. It has the CPU which can
access both main memory and the cache simultaneously.
7. The unit that is used to implement the multiple branch prediction in Pentium-Pro is
a) control unit
b) bus interface unit
c) branch target buffer
d) branch instruction register
Answer: c
Explanation: The processor uses an associative memory called branch target buffer for
implementing the algorithm, multiple branch prediction.
8. Which of the following is not an independent engine of Pentium-Pro?
a) fetch-decode unit
b) dispatch-execute unit
c) control-execute unit
d) retire unit
Answer: c
Explanation: Pentium-Pro incorporates three independent engines, 1. Fetch-decode unit 2.
Dispatch-execute unit 3. Retire unit.
9. The unit that accepts the sequence of instructions from the instruction cache as input is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) none
Answer: a
Explanation: The fetch-decode unit accepts the sequence of instructions from the instruction
cache as input and then decodes them.
10. In fetch-decode unit, the number of parallel decoders that accept the stream of fetched
instructions and decode them is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: A set of three parallel decoders accepts the stream of fetched instructions and
decode them.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Question Bank focuses on “Pro and Pentium-II -2”.
1. The decoder unit in fetch-decode unit converts the instructions into
a) executable statements
b) machine language statements
c) MMX instructions
d) micro operations
Answer: d
Explanation: The decoder unit converts the fetched instructions into micro operations.
2. The logical source
and logical destination
that the micro operation has respectively are
a) 2,2
b) 1,3
c) 3,1
d) 3,2
Answer: c
Explanation: Each microoperation contains two logical sources and one logical destination.
3. The microoperations that are converted by decoder are directly transferred to
a) decoder register
b) dispatch-execute unit
c) retire unit
d) register alias table
Answer: d
Explanation: The microoperations are sent to the register alias table
RAT
. The RAT translates the logical register references to the physical register set actually available
in the CPU.
4. The pool of instructions that are fetched is stored in an addressable memory called
a) tristate buffer
b) branch target buffer
c) reorder buffer
d) order buffer
Answer: c
Explanation: The pool of instructions that are fetched is stored in an array of content
addressable memory called reorder buffer.
5. The unit that performs scheduling of instructions by determining the data dependencies is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) none
Answer: b
Explanation: The dispatch-execute unit performs scheduling of instructions by determining the
data dependencies after which the microoperations of the scheduled instructions are executed
in the execution unit.
6. The unit that reads the instruction pool and removes the microoperations which have been
executed instruction pool is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) decoding unit
Answer: c
Explanation: The retire unit reads the instruction pool containing the instructions and removes
the microoperations which have been executed instruction pool.
7. The speed of Pentium-Pro when compared to that of Pentium is
a) equal
b) twice
c) thrice
d) two-third
Answer: b
Explanation: The features incorporated in Pentium-Pro enhances the speed of Pentium-Pro and
is twice as that of Pentium.
8. Which of the following is not supported by Pentium-Pro?
a) multiple branch prediction
b) mmx instruction set
c) speculative execution
d) none
Answer: b
Explanation: The Pentium-Pro does not support the MMX instruction set.
9. The feature of Pentium II is
a) high cache
b) operates at 2.8 volts
c) supports intel’s MMX instructions
d) all of the mentioned
Answer: d
Explanation: The Pentium II has a higher cache and it can operate at 2.8 volts, thereby reducing
power consumption. The most important change of Pentium II is that it can support Intel’s MMX
instructions.
10. The results of speculative instruction execution is stored in
a) visible CPU registers
b) permanent memory
c) temporary memory
d) none
Answer: c
Explanation: The results of speculative instruction execution should not be stored in CPU
registers and are temporarily stored, since they may have to be discarded, in case if there is a
branch instruction before these speculative instruction executions.
To practice Microprocessors Question Bank, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Features of Pentium 4, Netburst Microarchitecture For Pentium4 – 1”.
1. The feature of Pentium 4 is
a) works based on NetBurst microarchitecture
b) clock speed ranges from 1.4GHz to 1.7GHz
c) has hyper-pipelined technology
d) all of the mentioned
Answer: d
Explanation: Pentium 4 is based on NetBurst microarchitecture. Clock speed varies from
1.4GHz to 1.7GHz. It has hyper-pipelined technology.
2. Which of the following is not a module of Pentium 4 architecture?
a) front end module
b) execution module
c) control module
d) none
Answer: c
Explanation: Pentium 4 architecture may be viewed having four basic modules.
1. Front end module
2. Out of order execution engine
3. Execution module
4. Memory subsystem module.
3. The front module of Pentium 4 consists of
a) trace cache
b) microcode ROM
c) front end branch predictor
d) all of the mentioned
Answer: d
Explanation: The front module of Pentium 4 contains
1. IA 32 Instruction decoder
2. Trace cache
3. Microcode ROM
4. Front end branch predictor.
4. The unit that decodes the instructions concurrently and translate them into micro-operations
is
a) trace cache
b) instruction decoder
c) execution module
d) front end branch predictor
Answer: b
Explanation: The role of instruction decoder is to decode the instructions concurrently and
translate them into micro-operations known as micro-ops.
5. In complex instructions, when the instruction needs to be translated into more than 4
micro-operations, then the decoder transfers the task to
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
Answer: c
Explanation: In case of complex instructions, when the instruction needs to be translated into
more than 4 micro-operations, then the decoder transfers the task to microcode ROM.
6. The unit that does not store the instructions, but the decoded stream of instructions is
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
Answer: a
Explanation: The trace cache is a special instruction cache because it does not store the
instructions, but the decoded stream of instructions.
7. Trace cache can store the micro-ops upto a range of
a) 6 K decoded micro-ops
b) 8 K decoded micro-ops
c) 10 K decoded micro-ops
d) 12 K decoded micro-ops
Answer: d
Explanation: Trace cache can store upto 12K micro-ops. The cache assembles the decoded
micro-ops into ordered sequence of micro-ops called traces.
8. The unit that predicts the locations from where the next instruction bytes are fetched is
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
Answer: b
Explanation: The front end branch predictor predicts the locations from where the next
instruction bytes are fetched.
9. If complex instructions like interrupt handling, string manipulation appear, then the control
from trace cache transfers to
a) microcode ROM
b) front end branch predictor
c) execution module
d) instruction decoder
Answer: a
Explanation: When some complex instructions like interrupt handling, string manipulation
appear, then the control from trace cache transfers to microcode ROM.
10. After the micro-ops are issued by the microcode ROM, the control goes to
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
Answer: a
Explanation: After the micro-ops are issued by the microcode ROM, the control goes to Trace
cache once again. The micro-ops delivered by the trace cache and the microcode ROM are
buffered in a queue in an orderly fashion.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Questions and Answers for Entrance exams focuses on “Netburst
Microarchitecture For Pentium4 -2, Instruction Translation Lookaside Buffer
ITLB
and Branch Prediction”.
1. If the logical processors want to execute complex IA-32 instructions simultaneously then the
number of microcode instruction pointers required is
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: If both the logical processors want to execute complex IA-32 instructions
simultaneously then two microcode instruction pointers are required, which will access the
microcode ROM.
2. Which of the following is a type of branch prediction?
a) static prediction
b) dynamic prediction
c) static and dynamic prediction
d) none
Answer: c
Explanation: There are two types of branch prediction namely static prediction and dynamic
prediction.
3. The prediction that is based on a statistical assumption that the majority of backward
branches occur in repetitive loops is
a) static prediction
b) dynamic prediction
c) branch prediction
d) none
Answer: a
Explanation: The static prediction is based on a statistical assumption that the majority of
backward branches occur in the context of repetitive loops.
4. The advantage of static prediction is
a) simple and fast
b) does not require table lookups or calculations
c) performs without much degradation
d) all of the mentioned
Answer: d
Explanation: The static prediction is simple and fast. It does not require table lookups or
calculations. In case if a program contains a number of loops, static prediction performs without
much degradation.
5. The dynamic branch prediction algorithms use
a) Branch History Table
BHT
b) Branch Target Buffer
BTB
c) Branch History Table and Branch Target Buffer
d) None
Answer: c
Explanation: The dynamic branch prediction algorithms use two types of tables, namely Branch
History Table
BHT
and Branch Target Buffer
BTB
.
6. The unit that preserves the history of each conditional branch is
a) Branch Target Buffer
BTB
b) Branch History Table
BHT
c) Static prediction
d) Dynamic prediction
Answer: b
Explanation: The Branch History Table
BHT
preserves the history of each conditional branch that the speculative branch prediction unit
encounters during the last several cycles.
7. The BHT keeps a record that indicates the likelihood of the branches grouped as
a) strongly taken
b) taken
c) not taken
d) all of the mentioned
Answer: d
Explanation: The BHT keeps a record that indicates the likelihood that the branch will be taken
based on its past history. The branches may be grouped as ‘strongly taken’, ‘taken’, ‘not taken’
and ‘strongly not taken’.
8. Each logical processor has
a) one 64-byte streaming buffer
b) one 32-byte streaming buffer
c) two 64-byte streaming buffers
d) two 32-byte streaming buffers
Answer: c
Explanation: Each logic processor has its own set of two 64-byte streaming buffers, which store
the instruction bytes and subsequently they are dispatched to the instruction decode stage.
9. If there is a trace cache miss, then the instruction bytes are required to be fetched from the
a) instruction decoder
b) Level2 cache
c) execution module
d) none of the mentioned
Answer: b
Explanation: If there is a trace cache miss, then the instruction bytes are required to be fetched
from the Level2 cache.
10. The Instruction Translation Lookaside Buffer
ITLB
is present in
a) trace cache
b) instruction decoder
c) logical processors
d) all of the mentioned
Answer: c
Explanation: Since there are two logical processors, there are two ITLBs. Thus each logical
processor has its own ITLB and its own instruction pointer to track the progress of instruction
fetch for each of them.
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Multiple Choice Questions and Answers .
This set of Tough Microprocessors Questions and Answers focuses on “Rapid Execution
Module, Memory Subsystem, Hyperthreading Technology”.
1. The units that are primarily used to resolve indirect mode of memory addressing is called
a) ALU
b) AGU
c) ALU and AGU
d) NONE
Answer: b
Explanation: The AGUs
AddressGenerationUnits
are primarily used to resolve indirect mode of memory addressing.
2. The AGUs work at a speed of
a) equal to that of processor
b) twice the processor
c) thrice the processor
d) none
Answer: b
Explanation: The AGUs run at twice the processor speed.
3. Pentium 4 consists of
a) 4 ALUs
b) 4 AGUs
c) 2 ALUs and 2 AGUs
d) 4 ALUs and 4 AGUs
Answer: c
Explanation: Pentium 4 consists of 2 ALUs and 2 AGUs.
4. The number of instructions that can be executed per clock cycle by the ALU or AGU is
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: As the speed of the units, ALU and AGU are doubled, which means that twice the
number of instructions being executed per clock cycle.
5. The paging mechanism of IA-32 architecture has an extension as
a) page memory extension
b) page size extension
c) page address extension and page size extension
d) page memory extension and page size extension
Answer: c
Explanation: IA-32 architecture’s paging mechanism includes an extension that support
1. Page address extension to address space greater than 4GB.
2. Page size extension to map linear address to physical address in 4MB.
6. The linear address space is mapped into the processors physical address space either
directly or through paging by
a) flat memory model
b) segmented memory model
c) flat or segmented memory model
d) none
Answer: c
Explanation: With the flat or segmented memory model, linear address space is mapped into
the processors physical address space either directly or through paging.
7. The features of thread in threading process is
a) threads can be bunched together
b) threads are simple and light weight
c) threads are independent
d) all of the mentioned
Answer: d
Explanation: Threads may be bunched together in a process. Threads are independent, simple
in structure and are lightweight in the sense that they may enhance the speed of operation of an
overall process.
8. The process in which multiple threads correspond to the tracking of each individual object is
known as
a) multiple thread system
b) multi thread parallelism
c) thread level parallelism
d) multi level parallelism
Answer: c
Explanation: The mutiple threads correspond to the tracking of each individual object. This kind
of parallelism is known as thread level parallelism
TLP
.
9. Which of the following is not a type of context switching?
a) time-slice multithreading
b) on chip multiprocessing
c) hyperthreading
d) none
Answer: d
Explanation: A single processor can execute multiple threads by switching between them. The
scheme of context switching may be several types. They are
1. Time-slice multithreading
2. On chip multiprocessing
3. Hyperthreading.
10. The thread level parallelism is a process of
a) saving the context of currently executing process
b) flushing the CPU of the same process
c) loading the context of new next process
d) all of the mentioned
Answer: d
Explanation: The thread level parallelism is a process of
1. Saving the context of currently executing process.
2. Flushing the CPU of the same process.
3. Loading the context of new next process is called a context switch.
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of 1000+ Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Hyperthreading In Pentium”.
1. Which of the following is a resource sharing strategy that had been investigated by the
developers?
a) partitioned resources
b) threshold sharing
c) full sharing
d) all of the mentioned
Answer: d
Explanation: Several resource sharing strategies have been investigated by the developers.
Some of these are
1. Partitioned resources
2. Threshold sharing
3. Full sharing.
2. The feature of hyperthreading is
a) simultaneous multithreading
b) switching is not required
c) effective use of processor resources
d) all of the mentioned
Answer: d
Explanation: Hyperthreading used the concept of simultaneous multithreading, where multiple
threads can be executed on a single processor without switching.
3. Each logical processor maintains a set of architecture state which consists of
a) general purpose registers
b) machine state register
c) advanced programmed interrupt controller
d) all of the mentioned
Answer: d
Explanation: Each logical processor maintains a set of architecture state which consists of
1. Registers including the general purpose registers
2. The control register
3. Advanced programmed interrupt controller
4. Machine state register.
4. A logical processor may be temporarily stalled for
a) including servicing cache misses
b) handling branch mispredictions
c) waiting for results of previous instructions
d) all of the mentioned
Answer: d
Explanation: A logical processor may be temporarily stalled for a variety of reasons like
including servicing cache misses, handling branch mispredictions and waiting for results of
previous instructions.
5. The hyperthreading technology automatically involves the
a) decrease of die area
b) increase of die area
c) decrease of die area to half
d) none
Answer: b
Explanation: The hyperthreading technology automatically involves the increase of die area.
6. The instruction that is used when either of the logical processors is idle is
a) HOLD
b) HLDA
c) HALT
d) NONE
Answer: c
Explanation: An optimization may require the use of HALT instruction, when either of the two
logical processors is idle.
7. The mode that is available when there is only one software thread to execute is
a) single task mode
b) multi task mode
c) single task and multi task mode
d) dual task mode
Answer: c
Explanation: When there is only one software thread to execute, there are two modes namely
single task mode and multi task mode.
8. The HALT instruction is a privileged instruction that can be only used by
a) execution unit
b) operating system
c) control unit
d) memory unit
Answer: b
Explanation: The HALT instruction is a privileged instruction that can be only used by operating
system.
9. When the operating system uses HALT instruction on a processor which supports
multithreading, the operation moves from
a) Single task to multi task mode
b) ST1 to ST0
c) Multi task to single task mode
d) None
Answer: c
Explanation: When the operating system uses HALT instruction on a processor which supports
multithreading, the operation moves from multi tasking mode to single tasking mode.
10. The Xeon TM processor on which hyperthreading technology was first implemented consists
of
a) one logical processor per physical processor
b) two logical processor per physical processor
c) three logical processor per physical processor
d) zero logical processor per physical processor
Answer: b
Explanation: The Xeon TM processor on which hyperthreading technology was first
implemented consists of two logical processor per physical processor.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Basic Microprocessors Questions and Answers focuses on “Extended Instruction Set
In Advanced Pentium Processors, Formal Verification”.
1. The MMX instructions support only
a) character data type
b) float data type
c) integer data type
d) string data type
Answer: c
Explanation: The MMX instructions support only integer data type.
2. For single precision floating point numbers, the SSE instructions are
a) MMX instructions
b) SIMD instructions
c) Floating point executions
d) None
Answer: b
Explanation: The SSE instructions are SIMD
SingleInstructionMultipleDataStream
instructions for single precision floating point numbers.
3. The feature of SSE among the following is
a) operate on four 32-bit floating points
b) register size is of 128 bits
c) no switching from one mode to other
d) all of the mentioned
Answer: d
Explanation: The features of SSE
StreamingSIMDextensions
are
1. SSE instructions are SIMD instructions for single precision floating point numbers.
2. They operate on four 32-bit floating points.
3. The register size is of 128 bits
4. No necessity to switch from one mode to other.
4. The new instructions that are added in SSE for floating point operations are of
a) 72
b) 50
c) 25
d) 8
Answer: b
Explanation: The new instructions that are added in SSE for floating point operations are 50.
5. The SSE instructions can operate on
a) packed data
b) unpacked data
c) dynamic data
d) all of the mentioned
Answer: a
Explanation: The SSE instructions can operate on packed data or scalar data.
6. Which of the following group is not of SSE instructions?
a) jump or branch group of instruction
b) logic and comparison group of instruction
c) shuffle instructions
d) all of the mentioned
Answer: d
Explanation: The SSE instructions can be grouped to many types. Some of them are
1. Data transfer instructions
2. Arithmetic, logic and comparison group of instruction
3. shuffle instructions
4. Cacheability instructions.
7. Which of the following is true about SSE2 instructions in Pentium III and Pentium 4?
a) SSE increases the accuracy of double precision floating point operations
b) SSE supports new formats of packed data
c) SSE increases the speed of manipulation of SIMD integer operations
d) All of the mentioned
Answer: d
Explanation: The SSE new instruction set increases the accuracy of double precision floating
point operations, supports new formats of packed data.
8. The data type that the SSE2 instructions doesn’t support is
a) single precision floating points
b) double precision floating points
c) single and double precision floating points
d) none of the mentioned
Answer: d
Explanation: The SSE2 instructions support new data types such as double precision floating
points along with single precision floating points.
9. The additional instructions of SSE3 over SSE2 contains
a) video encoding
b) complex arithmetic operation
c) thread synchronization
d) all of the mentioned
Answer: d
Explanation: The SSE3 contains 13 additional SIMD instructions over SSE2. These instructions
comprise five types.
i. floating point to integer conversion
ii. complex arithmetic operation
iii. video encoding
iv. SIMD floating point operations using array of structures format
v. thread synchronization.
10. The unit that may acts as an interface between the Front end and the Out of order execution
engine in the pipeline flow is
a) micro-op queue
b) micro-op stack
c) micro-ops
d) none
Answer: a
Explanation: The micro-op queue acts as an interface between the Front end and the Out of
order execution engine in the pipeline flow.
11. The verification of the logic using formal mathematical tools is called
a) arithmetic verification
b) formal verification
c) mathematical verification
d) logical verification
Answer: b
Explanation: The verification of the logic using formal mathematical tools is called formal
verification.
12. The formal verification is important for
a) developing the tools
b) developing the methodologies
c) to detect the bugs in design
d) all of the mentioned
Answer: d
Explanation: The formal verification is important to develop the tools and methodologies to
handle a large number of proofs using which it will be possible to detect the bugs in the design.
13. By using the techniques of formal verification, one can detect the logical bugs of
a) more than 50
b) less than 50
c) more than 100
d) less than 100
Answer: c
Explanation: By using the techniques of formal verification, one can detect more than 100
logical bugs.
14. The modern processors are designed to achieve
a) high speed
b) operate at low operating voltage
c) uses cooling technology
d) all of the mentioned
Answer: d
Explanation: The modern processors are designed to operate at a very high speed and even
with the lower operating voltages, the power consumption is high enough to require expensive
cooling technology.
To practice basic questions and answers on all areas of Microprocessors, here is complete set
of 1000+ Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Hybrid Architecture -RISC and CISC Convergence, Advantages of RISC, Design
Issues of RISC Processors -1”.
1. The disadvantage of CISC design processors is
a) low burden on compiler developers
b) wide availability of existing software
c) complex in nature
d) none
Answer: c
Explanation: Some computers are used in preference to CISC design due to its low burden on
compiler developers and wide availability of existing software. But they are complex in nature.
2. The RISC architecture is preferred to CISC because RISC architecture has
a) simplicity
b) efficiency
c) high speed
d) all of the mentioned
Answer: d
Explanation: The RISC architecture is preferred to CISC because RISC architecture is simple,
highly efficient and the processors using RISC architecture have high speed.
3. The feature of RISC that is not present in CISC is
a) branch prediction
b) pipelining
c) branch prediction and pipelining
d) none
Answer: c
Explanation: A RISC core allows performance enhancing features, such as branch prediction
and pipelining. Traditionally, these have only been possible in RISC designs.
4. The feature of hybrid CISC-RISC architecture is
a) consume a lot of power
b) not applicable to mobile applications
c) processed by RISC core
d) all of the mentioned
Answer: d
Explanation: The CISC-RISC hybrids continue to consume a lot of power and are not best
candidates for mobile and embedded applications.
5. Which of the following is an application of RISC architecture by adding more instructions?
a) multimedia applications
b) telecommunication encoding
c) image conversion
d) all of the mentioned
Answer: d
Explanation: By adding more instructions to the RISC architecture, some applications can be
run much faster like multimedia applications, telecommunication encoding/decoding, image
conversion and video processing.
6. Which of the following processor belongs to hybrid RISC-CISC architecture?
a) Intel Pentium III
b) Intel Itanium 64
c) AMD’s X86-64
d) All of the mentioned
Answer: d
Explanation: The processors, Intel Pentium III, Intel Itanium 64 and AMD’s X86-64 consists of
hybrid RISC-CISC architecture.
7. In order to implement complex instructions, CISC architectures use
a) macroprogramming
b) hardwire
c) microprogramming
d) none
Answer: c
Explanation: In order to implement complex instructions, CISC architectures use
microprogramming.
8. The advantage of RISC processors is
a) can operate at high clock frequency
b) shorter design cycle
c) simple and fast
d) all of the mentioned
Answer: d
Explanation: The advantages of RISC processors are that they can work at high clock
frequency, can be designed, developed and tested more quickly with a high speed.
9. The additional functionality that can be placed on the same chip of RISC is
a) Memory management units
b) Floating point units
c) Memory management and floating point arithmetic units
d) RAM, ROM
Answer: c
Explanation: Several extra functionalities, such as memory management units or floating point
arithmetic units, can also be placed on the same chip of RISC.
10. The number of clockcycles that take to wait until the length of the instruction is known in
order to start decoding is
a) 0
b) 1
c) 2
d) 3
Answer: a
Explanation: The loading and decoding the instructions in a RISC processor is simple and fast.
It is not needed to wait until the length of the instruction is known in order to start the decoding.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Problems focuses on “Hybrid Architecture -RISC and CISC
Convergence, Advantages of RISC, Design Issues of RISC Processors -2”.
1. The number of CPIs
ClockPerInstruction
for an instruction of RISC processors is
a) 0
b) 1
c) 2
d) 3
Answer: b
Explanation: RISC processors have unity CPI
ClockPerInstruction
, which is due to the optimization of each instruction on the CPU and massive pipelining
embedded in a RISC processor.
2. Which of the following is not true about RISC processors?
a) addressing modes are less
b) pipelining is key for high speed
c) microcoding is required
d) single machine cycle instructions
Answer: c
Explanation: Unlike the CISC, in RISC architecture, instruction microcoding is not required.
3. The RISC processors that support variable length instructions are from
a) Intel
b) Motorola
c) AMD
d) Intel and Motorola
Answer: d
Explanation: In RISC, each instruction is of the same length, so that it may be fetched in a
single operation. The traditional microprocessors from Intel or Motorola support variable length
instructions.
4. Which of the following is true about register windowing?
a) chips expose 32 registers to programmer
b) puts demands on multiplexers
c) puts enormous demands on register ports
d) all of the mentioned
Answer: d
Explanation: The register windowing involves a mechanism where the chips expose 32 registers
to the programmer at any one time. It puts enormous demands on multiplexers and register
ports to make any physical register appear to be any logical register.
5. The disadvantage of register windowing is
a) high speed
b) puts demands on multiplexers/register ports
c) consumes less cycles
d) doesn’t handle overflow/underflow
Answer: d
Explanation: It is impossible to predict when the register file will overflow or underflow, so
performance is unpredictable. It generates a software fault, which the operating system has to
handle, consuming more cycles.
6. The register window is used to point the number of physical registers is
a) infinite
b) that are currently used
c) finite
d) that are unused
Answer: c
Explanation: The register window only helps us to point the number of physical registers is finite.
7. Which of the following is not a stage of pipeline of a RISC processor?
a) read registers and decode the instructions
b) fetch instructions from registers
c) write result into a register
d) access an operand in data memory
Answer: b
Explanation: There are 5 stages in pipelining. They are
1. Fetch instructions from memory
2. Read registers and decode the instructions
3. Execute the instructions or calculate an address
4. Access an operand in data memory
5. Write result into a register.
8. When an instruction depends on the results of the previous instructions then
a) error occurs
b) software fault occurs
c) data dependency occurs
d) hardware fault occurs
Answer: c
Explanation: A data dependency occurs when an instruction depends on the results of the
previous instructions.
9. The instructions that instruct the processor to make a decision about the next instruction to be
executed are
a) data dependency instructions
b) branch instructions
c) control transfer instructions
d) none
Answer: b
Explanation: The branch instructions are those which instruct the processor to make a decision
about the next instruction to be executed, depending upon whether the condition is satisfied or
not.
10. The reason for which the RISC processor goes to idle state
orstall
is
a) delay in reading information from memory
b) poor instruction set design
c) dependencies between instructions
d) all of the mentioned
Answer: d
Explanation: There are a variety of reasons, including delays in reading information from
memory, poor instruction set design, or dependencies between instructions for the RISC
processor to remain idle.
To practice all areas of Microprocessors Problems, here is complete set of 1000+ Multiple
Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Architecture of 8051”.
1. The register that may be used as an operand register is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
Answer: d
Explanation: In some instructions, the Accumulator and B register are used to store the
operands.
2. The register that can be used as a scratch pad is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
Answer: b
Explanation: B register is used to store one of the operands for multiply and divide instructions.
In other instructions, it may just be used as a scratch pad.
3. The registers that contain the status information is
a) control registers
b) instruction registers
c) program status word
d) all of the mentioned
Answer: c
Explanation: The set of flags of program status word contains the status information and is
considered as one of the special function registers.
4. Which of the processor’s stack does not contain the top-down data structure?
a) 8086
b) 80286
c) 8051
d) 80386
Answer: c
Explanation: The 8051 stack is not a top-down data structure, like other Intel processors.
5. The architecture of 8051 consists of
a) 4 latches
b) 2 timer registers
c) 4 on-chip I/O ports
d) all of the mentioned
Answer: d
Explanation: The architecture of 8051 consists of 4 latches and driver pairs are allotted to each
of the four on-chip I/O ports. It contains two 16-bit timer registers.
6. The transmit buffer of serial data buffer is a
a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register
Answer: b
Explanation: The transmit buffer of serial data buffer is a parallel-in serial-out register.
7. The receive buffer of serial data buffer is a
a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register
Answer: a
Explanation: The serial data register has two buffers. The transmit buffer is a parallel-in
serial-out register and receive buffer is a parallel-in serial-out register.
8. The register that provides control and status information about counters is
a) IP
b) TMOD
c) TSCON
d) PCON
Answer: b
Explanation: The registers, TMOD and TCON contain control and status information about
timers/counters.
9. The register that provides control and status information about serial port is
a) IP
b) IE
c) TSCON
d) PCON and SCON
Answer: d
Explanation: The registers, PCON and SCON contain control and status information about serial
port.
10. The device that generates the basic timing clock signal for the operation of the circuit using
crystal oscillator is
a) timing unit
b) timing and control unit
c) oscillator
d) clock generator
Answer: c
Explanation: The oscillator circuit generates the basic timing clock signal for the operation of the
circuit using crystal oscillator.
11. The registers that are not accessible by the user are
a) Accumulator and B register
b) IP and IE
c) Instruction registers
d) TMP1 and TMP2
Answer: d
Explanation: The arithmetic operations are performed over the operands held by the temporary
registers, TMP1 and TMP2. Users cannot access these temporary registers.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Register Set of 8051”.
1. Which of the following is an 8-bit register?
a) PSW
ProgramStatusWord
b) TCON
TimerControlRegister
c) Accumulator
d) All of the mentioned
Answer: d
Explanation: The registers, PSW, TCON and Accumulator are 8-bit registers.
2. Which of the following register can be addressed as a byte?
a) P1
b) SCON
c) TMOD
d) TCON
Answer: c
Explanation: The registers, TMOD, SP, TH0, TH1, TL0, TL1 are to be addressed as bytes.
3. Which of the following is bit-addressable register?
a) SBUF
b) PCON
c) TMOD
d) SCON
Answer: d
Explanation: The registers, accumulator, PSW, B, P0, P1, P2, P3, IP, IE, TCON and SCON are
all bit-addressable registers.
4. The higher and lower bytes of a 16-bit register DPTR are represented respectively as
a) LDPTR and HDPTR
b) DPTRL and DPTRH
c) DPH and DPL
d) HDP and LDP
Answer: c
Explanation: The registers, DPH and DPL are the higher and lower bytes of a 16-bit register
DPTR.
5. The register that is used for accessing external data memory is
a) DPH
b) DPL
c) DPTR
d) NONE
Answer: c
Explanation: The Data Pointer
DPTR
is used for accessing external data memory which means that it includes both DPH and DPL.
6. Among the four groups of register banks, the number of groups that can be accessed at a
time is
a) 1
b) 2
c) 3
d) all the four
Answer: a
Explanation: At a time, only one of the four register banks can be accessed.
7. The number of 8-bit registers that a register bank contain is
a) 2
b) 4
c) 6
d) 8
Answer: d
Explanation: The 32, 8-bit registers are divided into four groups of 8 registers each, called
register banks.
8. If RS1=1, RS0=0, then the register bank selected is
a) register bank 0
b) register bank 1
c) register bank 2
d) register bank 3
Answer: c
Explanation: If RS1=1, RS0=0, then the register bank selected is register bank 2.
9. If RS1=1, RS0=1, then the register bank selected is
a) register bank 0
b) register bank 1
c) register bank 2
d) register bank 3
Answer: d
Explanation: If RS1=1, RS0=1, then the register bank selected is register bank 3. If RS1=0,
RS0=0, then selected bank is register bank 0.
10. The PCON register consists of
a) power mode bit
b) power idle bit
c) power ideal bit
d) power down bit and idle bit
Answer: d
Explanation: The power control register, PCON consists of power down bit and idle bit which
activate the power down mode and idle mode in 80C51BH.
11. The on-chip oscillator is stopped in
a) power mode
b) power down mode
c) idle mode
d) ideal mode
Answer: b
Explanation: In power down mode, the on-chip oscillator is stopped.
12. In idle mode, the device that is disabled is
a) serial port
b) timer block
c) clock to CPU
d) all of the mentioned
Answer: c
Explanation: In idle mode, the oscillator continues to run and the interrupt, serial port and timer
blocks are active but the clock to the CPU is disabled.
13. The only way to terminate the power down mode is to
a) CLEAR
b) RESET
c) HOLD
d) HLT
Answer: b
Explanation: The only way to terminate the power down mode is hardware reset. The reset
redefines all the SFRs but the RAM contents are left unchanged.
14. The idle mode can be terminated by
a) PRESET
b) CLEAR
c) Interrupt
d) Interrupt or reset
Answer: d
Explanation: The idle mode can be terminated with a hardware interrupt or hardware reset
signal.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interrupt and Stack of 8051 -1”.
1. Which of the following is an external interrupt?
a) INT0
activelow
b) INT2
activelow
c) Timer0 interrupt
d) Timer1 interrupt
Answer: a
Explanation: INT0
activelow
and INT1
activelow
are two external interrupt inputs provided by 8051.
2. The interrupts, INT0
activelow
and INT1
activelow
are processed internally by flags
a) IE0 and IE1
b) IE0 and IF1
c) IF0 and IE1
d) IF0 and IF1
Answer: a
Explanation: The interrupts, INT0
activelow
and INT1
activelow
are processed internally by the flags IE0 and IE1.
3. The flags IE0 and IE1, are automatically cleared after the control is transferred to respective
vector if the interrupt is
a) level-sensitive
b) edge-sensitive
c) in serial port
d) in parallel port
Answer: b
Explanation: If the interrupts are programmed as edge sensitive, the flags IE0 and IE1 are
automatically cleared after the control is transferred to respective vector.
4. If the external interrupt sources control the flags IE0 and IE1, then the interrupt programmed
is
a) level-sensitive
b) edge-sensitive
c) in serial port
d) in parallel port
Answer: a
Explanation: If the interrupts are programmed as level sensitive, then the flags IE0 and IE1 are
controlled by external interrupt sources themselves.
5. The pulses at T0 or T1 pin are counted in
a) timer mode
b) counter mode
c) idle mode
d) power down mode
Answer: b
Explanation: In counter mode, the pulses are counted at T0 or T1 pin.
6. In timer mode, the oscillator clock is divided by a prescalar
a)
1/8
b)
1/4
c)
1/16
d)
1/32
Answer: d
Explanation: In timer mode, the oscillator clock is divided by a prescalar
1/32
and then given to the timer.
7. The serial port interrupt is generated if
a) RI is set
b) RI and TI are set
c) Either RI or TI is set
d) RI and TI are reset
Answer: c
Explanation: The serial port interrupt is generated if atleast one of the two bits, RI and TI is set.
8. In serial port interrupt, after the control is transferred to the interrupt service routine, the flag
that is cleared is
a) RI
b) TI
c) RI and TI
d) None
Answer: d
Explanation: In serial port interrupt, after the control is transferred to the interrupt service
routine, neither of the flags are cleared.
9. The atleast number of machine cycles for which the external interrupts that are programmed
level-sensitive should remain high is
a) 1
b) 2
c) 3
d) 0
Answer: b
Explanation: The external interrupts, programmed level-sensitive should remain high for atleast
2 machine cycles.
10. If the external interrupts are programmed edge sensitive, then they should remain high for
atleast
a) 0 machine cycle
b) 2 machine cycles
c) 1 machine cycle
d) 3 machine cycles
Answer: c
Explanation: If the external interrupts are programmed edge sensitive, then they should remain
high for atleast one machine cycle and low for atleast one machine cycle, for being sensed.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Assessment Questions and Answers focuses on “Interrupt and
Stack of 8051 – 2”.
1. The timer generates an interrupt, if the count value reaches to
a) 00FFH
b) FF00H
c) 0FFFH
d) FFFFH
Answer: d
Explanation: The timer is an up-counter and generates an interrupt when the count has reached
FFFFH.
2. The external interrupt that has the lowest priority among the following is
a) TF0
b) TF1
c) IE1
d) NONE
Answer: c
Explanation: The order of given interrupts from high to low priority is TF0, IE1 and TF1.
3. Among the five interrupts generated by 8051, the lowest priority is given to the interrupt
a) IE0
b) TF1
c) TF0
d) RI
Answer: d
Explanation: The interrupt, RI=TI
serialport
is given the lowest priority among all the interrupts.
4. Among the five interrupts generated by 8051, the highest priority is given to the interrupt
a) IE0
b) TF1
c) TF0
d) IE1
Answer: a
Explanation: The interrupt, IE0
ExternalINT0
is given the highest priority among all the interrupts.
5. All the interrupts are enabled using a special function register called
a) interrupt priority register
b) interrupt register
c) interrupt function register
d) interrupt enable register
Answer: d
Explanation: All the interrupts are enabled using a special function register called interrupt
enable register
IE
and their priorities are programmed using another special function register called interrupt
priority register
IP
.
6. The number of bytes stored on the stack during one operation of PUSH or POP is
a) 1
b) 2
c) 3
d) 4
Answer: a
Explanation: As 8051 stack operations are 8-bit wide i.e. in an operation using PUSH or POP
instruction, one byte of data is stored on a stack or retrieved from the stack. For implementing
16-bit operations, two 8-bit operations are cascaded.
7. The step involved in PUSH operation is
a) increment stack by 2 and store 8-bit content to address pointed to by SP
b) decrement stack by 1 and store 16-bit content to address pointed to by SP
c) increment stack by 1 and store 8-bit content to address pointed to by SP
d) store 8-bit content to address pointed to by SP and then increment stack by 1
Answer: c
Explanation: The PUSH instruction follows two steps.
1. Increment stack by 1
2. Store 8-bit content of the 8-bit address specified in the instruction to the address pointed to by
SP.
8. The step involved in POP operation is
a) decrement stack by 2 and store 8-bit content to address pointed to by SP
b) store 16-bit content to address pointed to by SP and decrement stack by 1
c) decrement stack by 1 and store content of top of stack to address pointed to by SP
d) store content of top of stack to address pointed to by SP and then decrement stack by 1
Answer: d
Explanation: The POP instruction follows two steps.
1. Store the contents of top of stack pointed to by SP register to the 8-bit memory specified in
the instruction.
2. Decrement stack by 1.
9. The 8051 stack is
a) auto-decrement during PUSH operations
b) auto-increment during POP operations
c) auto-decrement during POP operations
d) auto-increment during PUSH operations
Answer: d
Explanation: The 8051 stack is opposite to that in 8085 or 8086 i.e. in 8085 it is auto-decrement
while in 8051 it is auto-increment during PUSH operations.
10. After reset, the stack pointer
SP
is initialized to the address of
a) internal ROM
b) internal RAM
c) external ROM
d) external RAM
Answer: b
Explanation: The stack pointer
SP
is an 8-bit register and is initialized to internal RAM address 07H after reset.
To practice all areas of Microprocessors Assessment Questions, here is complete set of 1000+
Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Addressing Modes of 8051”.
1. Which of the following is not an addressing mode of 8051?
a) register instructions
b) register specific instructions
c) indexed addressing
d) none
Answer: d
Explanation: The six addressing modes of 8051 are
1. Direct addressing
2. Indirect addressing
3. Register instructions
4. Register specific
RegisterImplicit
instructions
5. Immediate mode
6. Indexed addressing.
2. The symbol, ‘addr 16’ represents the 16-bit address which is used by the instructions to
specify the
a) destination address of CALL
b) source address of JUMP
c) destination address of call or jump
d) source address of call or jump
Answer: c
Explanation: The symbol, ‘addr 16’ represents the 16-bit destination address which is used by
the LCALL or LJMP instruction to specify the call or jump destination address, within 64 Kbytes
program memory.
3. The storage of addresses that can be directly accessed is
a) external data RAM
b) internal data ROM
c) internal data RAM and SFRS
d) external data ROM and SFRS
Answer: c
Explanation: Only internal data RAM and SFRS can be directly addressed in direct addressing
mode.
4. The address register for storing the 16-bit addresses can only be
a) stack pointer
b) data pointer
c) instruction register
d) accumulator
Answer: b
Explanation: The address register for storing the 16-bit addresses can only be data pointer.
5. The address register for storing the 8-bit addresses can be
a) R0 of the selected bank of register
b) R1 of the selected bank of register
c) Stack pointer
d) All of the mentioned
Answer: d
Explanation: The registers R0 and R1 of the selected bank of registers or stack pointer can be
used as address registers for storing the 8-bit addresses.
6. The instruction, ADD A, R7 is an example of
a) register instructions
b) register specific instructions
c) indexed addressing
d) none
Answer: a
Explanation: In register instructions addressing mode, operands are stored in the registers
R0-R7 of the selected register bank. One of these registers is specified in the instruction.
7. The addressing mode, in which the instructions has no source and destination operands is
a) register instructions
b) register specific instructions
c) direct addressing
d) indirect addressing
Answer: b
Explanation: In register specific instructions addressing mode, the instructions don’t have
source and destination operands. Some of the instructions always operate only on a specific
register.
8. The instruction, RLA performs
a) rotation of address register to left
b) rotation of accumulator to left
c) rotation of address register to right
d) rotation of accumulator to right
Answer: b
Explanation: The instruction, RLA rotates accumulator left.
9. The instruction, ADD A, #100 performs
a) 100
decimal
is added to contents of address register
b) 100
decimal
is subtracted from the accumulator
c) 100
decimal
is added to contents of an accumulator
d) none
Answer: c
Explanation: Immediate data 100
decimal
is added to the contents of the accumulator.
10. In which of these addressing modes, a constant is specified in the instruction, after the
opcode byte?
a) register instructions
b) register specific instructions
c) direct addressing
d) immediate mode
Answer: d
Explanation: In immediate mode, an immediate data, i.e. a constant is specified in the
instruction, after the opcode byte.
11. The only memory which can be accessed using indexed addressing mode is
a) RAM
b) ROM
c) Main memory
d) Program memory
Answer: d
Explanation: Only program memory can be accessed using the indexed addressing mode.
12. The data address of look-up table is found by adding the contents of
a) accumulator with that of program counter
b) accumulator with that of program counter or data pointer
c) data register with that of program counter or accumulator
d) data register with that of program counter or data pointer
Answer: b
Explanation: The look-up table data address is found out by adding the contents of register
accumulator with that of the program counter or data pointer.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “8051 Instruction Set -1”.
1. Which of the following is not an instruction of 8051 instructions?
a) arithmetic instructions
b) boolean instructions
c) logical instructions
d) none
Answer: d
Explanation: The 8051 instructions are categorized as
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Boolean instructions
5. Control transfer instructions.
2. The operations performed by data transfer instructions are on
a) bit data
b) byte data
c) 16-bit data
d) all of the mentioned
Answer: d
Explanation: The data transfer instructions implement a bit, byte, 16-bit data transfer operations
between the SRC
source
and DST
destination
operands.
3. Which of the following is true while executing data transfer instructions?
a) program counter is not accessible
b) restricted bit-transfer operations are allowed
c) both operands can be direct/indirect register operands
d) all of the mentioned
Answer: c
Explanation: In data transfer instructions,
1. Program counter is not accessible.
2. Restricted bit-transfer operations are allowed.
3. Both operands can be direct/indirect register operands.
4. BOth operands can be internal direct data memory operands.
4. The logical instruction that affects the carry flag during its execution is
a) XRL A;
b) ANL A;
c) ORL A;
d) RLC A;
Answer: d
Explanation: The logical instructions that doesn’t affect the carry flag are, ANL, ORL and XRL.
The logical instructions that affect the carry flag during its execution are RL, RLC, RRC and RR.
5. The instruction that is used to complement or invert the bit of a bit addressable SFR is
a) CLR C
b) CPL C
c) CPL Bit
d) ANL Bit
Answer: c
Explanation: The instruction, CPL Bit is used to complement or invert the bit of a bit addressable
SFR or RAM.
6. The instructions that change the sequence of execution are
a) conditional instructions
b) logical instructions
c) control transfer instructions
d) data transfer instructions
Answer: c
Explanation: The control transfer instructions transfer the control of execution or change the
sequence of execution conditionally or unconditionally.
7. The control transfer instructions are divided into
a) explicit and implicit control transfer instructions
b) conditional and unconditional control transfer instructions
c) auto control and self control transfer instructions
d) all of the mentioned
Answer: b
Explanation: The control transfer instructions are divided into conditional and unconditional
control transfer instructions.
8. The conditional control transfer instructions check a bit condition which includes any bit of
a) bit addressable RAM
b) bit addressable SFRs
c) content of accumulator
d) all of the mentioned
Answer: d
Explanation: The conditional control transfer instructions check a bit condition which includes
any bit of bit addressable RAM or bit addressable SFRs or content of accumulator for
transferring the control to the specified jump location.
9. All conditional jumps are
a) absolute jumps
b) long jumps
c) short jumps
d) none
Answer: c
Explanation: All conditional jumps are short jumps.
10. The first byte of a short jump instruction represents
a) opcode byte
b) relative address
c) opcode field
d) none
Answer: a
Explanation: The short jump instruction has two byte instruction. The first byte represents
opcode byte and second byte represents an 8-bit relative address.
11. In logical instructions, the immediate data can be an operand for
a) increment operation
b) decrement operation
c) single operand instruction
d) none
Answer: d
Explanation: In logical instructions, the immediate data can’t be an operand for
increment/decrement or any other single operand instruction.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Questions and Answers for Aptitude test focuses on “8051
Instruction Set -2”.
1. If the most significant bit of relative address byte is 1, then the short jump instruction is
a) forward jump
b) back jump
c) either forward or back jump
d) none
Answer: b
Explanation: If the most significant bit of relative address byte is 1, then the short jump
instruction is back jump, else it is considered as forward jump.
2. The first byte of an absolute jump instruction consists of
a) 3 LSBs of opcode and 5 MSBs of 11-bit address
b) 5 MSBs of opcode and 3 LSBs of 11-bit address
c) 6 MSBs of opcode and 1 LSB of 11-bit address
d) 5 LSBs of opcode and 3 MSBs of 11-bit address
Answer: d
Explanation: The first byte of an absolute jump instruction consists of 5 LSBs of opcode and 3
MSBs of 11-bit address. The next byte carries the least significant 8 bits of the 11-bit address.
3. The third byte of the long jump instruction is
a) opcode
b) 5 LSBs of opcode
c) higher byte of jump location or subroutine
d) lower byte of jump location or subroutine
Answer: c
Explanation: The third byte of the long jump instruction is a higher byte of jump location or
subroutine.
4. The absolute jump instruction is intended mainly for a jump within a memory space of
a) 2 bytes
b) 2 Kbytes
c) 2 Mbytes
d) none
Answer: b
Explanation: The absolute jump instruction is intended mainly for a jump within a memory space
of 2 Kbytes.
5. The LJMP instruction is very useful in programming in the external code memory space of
a) 32 MB
b) 64 MB
c) 32 KB
d) 64 KB
Answer: d
Explanation: The LJMP instruction is very useful in programming in the external code memory
space of 64 KB.
6. Which of the following is not an unconditional control transfer instruction?
a) JMP
b) RET
c) JNC
d) CALL
Answer: c
Explanation: The instructions, JMP, RET, RETI, CALL are the unconditional control transfer
instructions.
7. The conditional control transfer instructions use
a) status flags
b) bits of bit addressable RAM
c) SFRs termed bit
d) all of the mentioned
Answer: d
Explanation: The conditional control transfer instructions use status flags or bits of bit
addressable RAM or SFRs termed bit.
8. Which of the following is not a conditional control transfer instruction?
a) JC
b) JBC
c) JNC
d) NONE
Answer: d
Explanation: The instructions, JC, JBC, JNC, JB and JNB are the conditional control transfer
instructions.
9. The mnemonic used to perform a subtraction of source with an 8-bit data and jumps to
specified relative address if subtraction is non-zero is
a) DJNZ
b) CJNE
c) JZ
d) JNC
Answer: b
Explanation: The CJNE instruction perform a subtraction of source with an 8-bit data and jumps
to specified relative address only if the result of the subtraction is non-zero, else continues to
the next instruction.
10. The mnemonic, JNB is used to jump to the specified relative address only if
a) specified bit=1
b) specified bit=0
c) specified bit is non-recursive
d) none
Answer: a
Explanation: The mnemonic, JNB is used to jump to the specified relative address only if
specified bit=1, else continues to the next instruction.
11. The type of operand that is not allowed to use in boolean instructions of 8051 is
a) direct register operands
b) indirect register operands
c) immediate bit
d) none
Answer: c
Explanation: In boolean instructions, the immediate bit is not allowed as an operand.
12. In boolean instructions, the flag that is the only allowed destination operand for two operand
instructions is
a) overflow flag
b) underflow flag
c) auxiliary flag
d) carry flag
Answer: d
Explanation: Carry flag
C
is the only allowed destination operand for two operand instructions in boolean instructions.
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Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interfacing With 8051 Ports -1”.
1. Which of the following is not one of the SFR addresses of the ports of 8051?
a) 80H
b) 90H
c) A0H
d) NONE
Answer: d
Explanation: The SFR addresses of the ports P0, P1, P2 and P3 are 80H, 90H, A0H and B0H
respectively.
2. Each port line of a port can individually source a current of upto
a) 0.2 mA
b) 0.25 mA
c) 0.5 mA
d) 0.75 mA
Answer: c
Explanation: Each port line of a port can individually source a current of upto 0.5 mA.
3. Each port line of a port can individually sink a current of upto
a) 2 mA
b) 8 mA
c) 5 mA
d) 1 mA
Answer: b
Explanation: Each port line of a port can individually sink a current of upto 8 mA.
4. The number of TTL inputs that can be sinked by the port 0 when a logic 0 is sent to a port line
as an output port is
a) 2
b) 4
c) 6
d) 8
Answer: d
Explanation: When a logic 0 is sent to a port line as an output port, it can sink 8 LS TTL inputs.
Port 0 is used as data bus during external interfacing whenever required.
5. The open drain bidirectional
inputoroutput
port with internal pullups is
a) Port 0
b) Port 1
c) Port 2
d) Port 3
Answer: a
Explanation: Port 0 is an open drain bidirectional
inputoroutput
port with internal pullups. Port 1, Port 2, Port 3 are 8-bit bidirectional ports.
6. The port that can source or sink 4 LS TTL inputs when being used as an output port on each
of its line is
a) Port 1
b) Port 2
c) Port 3
d) all of the mentioned
Answer: d
Explanation: The ports P1, P2 and P3 can source or sink 4 LS TTL inputs when being used as
an output port on each of its line.
7. The port that will source a current of 500 micro amperes when being used as input ports is
a) 0.5 mA
b) 0.25 mA
c) 250 micro amperes
d) 500 micro amperes
Answer: d
Explanation: Port 3 pins which are externally pulled low when being used as input pins will
source current of 500 micro amperes.
8. If the EA
activelow
signal is grounded then the execution
a) directly start from main memory
b) directly start from 16 bit address in main memory
c) directly start from 16 bit address in program memory
d) directly start from RAM
Answer: c
Explanation: For interfacing external program memory, EA
activelow
pin must be grounded. If the EA
activelow
signal is grounded then the execution will start directly from the 16-bit address 0000H in
external program memory.
9. When the port lines of a port are to be used as input lines then the value that must be written
to the port address is
a) F0H
b) 0FH
c) FFH
d) 00H
Answer: c
Explanation: When the port lines of a port are to be used as input lines then ‘FF’H must be
written to the port address.
10. Port 1 lines are used during programming of
a) external EPROM and EEPROM
b) external ROM and RAM
c) internal ROM and RAM
d) internal EPROM and EEPROM
Answer: d
Explanation: Port 1 lines are used as lower byte of 16-bit address bus during programming of
internal EPROM or EEPROM.
11. The configuration in which each LED receives operating current of 8 mA from power supply
while the port lines sink the current on each port line is
a) common port configuration
b) common anode configuration
c) common cathode configuration
d) none of the mentioned
Answer: b
Explanation: The common anode configuration is preferred to that of other configurations as in
common anode configuration, each LED receives operating current of 8 mA from power supply
while the port lines sink the current on each port line.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessors Questions and Answers for Campus interviews focuses on
“Interfacing With 8051 Ports -2”.
1. If EA
activelow
signal =1, then the execution starts from
a) internal EPROM
b) flash RAM
c) internal EPROM or flash RAM
d) none
Answer: c
Explanation: If EA
activelow
signal =1, then the execution starts from an internal EPROM or flash RAM address 000H, can
continue upto FFFH address and then for higher addresses it will go into external memory.
2. The pin that is grounded for interfacing external EPROM is
a) EA
activelow
b) PSEN
activelow
c) OE
activelow
d) All of the mentioned
Answer: a
Explanation: The EA
activelow
pin is grounded for interfacing external EPROM. The PSEN
activelow
is used for interfacing EPROM i.e. it acts as an OE
activelow
input to EPROM.
3. The step that is involved in the procedure of memory interfacing with 8051 is
a) data bus is connected to data lines of memory chips
b) PSEN
activelow
is connected to OE
activelow
of EPROM chips
c) writing address map of memory chip in bit form
d) all of the mentioned
Answer: d
Explanation: The procedure of memory interfacing with 8051 includes, data bus connection to
data lines of memory chips, PSEN
activelow
connected to OE
activelow
of EPROM chips and writing address map of memory chip in bit form.
4. The device that is used for deriving chip select signals is
a) Logic gates
b) Multiplexers
c) PLAs and EPROMs
d) All of the mentioned
Answer: d
Explanation: The logic gates and multiplexers are most commonly used for deriving chip select
signals. The advanced circuits like PLAs and EPROMs are also used for deriving chip select
signals.
5. For deriving chip selects of isolated memory or IO devices, the gates that are traditionally
used are
a) NOR and NAND
b) NAND and NOT
c) NOT and NOR
d) AND, OR and NOT
Answer: b
Explanation: For deriving chip selects of isolated memory or IO devices, the NAND and NOT
gates are traditionally used.
6. The current that is required for a LED for an appropriate glow is
a) 6-8 mA
b) 4-6 mA
c) 8-10 mA
d) 10-12 mA
Answer: c
Explanation: For appropriate glow, a LED typically requires 8-10 mA with around 1.6 Volts.
7. The maximum current that can be sinked totally by all the ports of 8051 is
a) 61 mA
b) 81 mA
c) 91 mA
d) 71 mA
Answer: d
Explanation: All the ports together
4ports
should not be made to sink more than 71 mA.
8. The number of LEDs that can be connected to a port of 8051, if all are expected to glow
simultaneously is
a) 6
b) 8
c) 10
d) 12
Answer: b
Explanation: If 8 LEDs are connected to a port of 8051, and if all are expected to glow
simultaneously, the total current sinked by the 8051 port will be 8×8=64 mA
sinceminvoltageforanLEDtoglow=8mA
which is less than the maximum 71 mA.
9. Which is true in interfacing 7 segment code display?
a) transmitted by second port
b) display is selected by third port
c) display is selected by second port
d) none of the mentioned
Answer: c
Explanation: The 7-segment code of a digit is transmitted by the first port and the display is
selected by second port. As soon as the display is selected by the second port, the digit starts
glowing on that display position.
10. After the display is selected by second port, then the digit
LED
glows for a duration of
a) 5 msec
b) 10 msec
c) 2 msec
d) 6 msec
Answer: a
Explanation: The unit
LED
glows for a duration of 5 msec.
11. The number of scans of the complete 8-digit display that can be carried out in one second is
a) 15
b) 25
c) 35
d) 55
Answer: b
Explanation: Starting from either right most or left most digit, every digit glows for 5 msec one by
one. Thus one scan of the 8 digit display requires 40 msec. Thus in one second, 25 scans of the
complete 8-digit display can be carried out.
12. To convert its current output into a voltage, the DAC 0808 is connected with
a) Transistor
BJT
externally
b) FET externally
c) OPAMP externally
d) OPAMP internally
Answer: c
Explanation: the DAC 0808 is connected with OPAMP externally, to convert its current output
into voltage.
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Multiple Choice Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Interrupt Structure of 8051”.
1. The external interrupts of 8051 can be enabled by
a) 4 LSBs of TCON register
b) Interrupt enable
c) priority register
d) all of the mentioned
Answer: d
Explanation: The external interrupts namely INT0
activelow
and INT1
activelow
can be enabled and programmed using the least significant four bits of TCON register and the
Interrupt enable and priority registers.
2. The bits that control the external interrupts are
a) ET0 and ET1
b) ET1 and ET2
c) EX0 and EX1
d) EX1 and EX2
Answer: c
Explanation: The bits, EX0 and EX1 individually control the external interrupts, INT0
activelow
and INT1
activelow
. If INT0
activelow
and INT1
activelow
interrupts are to be enabled then the bits EX0 and EX1 must be set respectively.
3. EA bit is used to
a) enable or disable external interrupts
b) enable or disable internal interrupts
c) enable or disable all the interrupts
d) none of the mentioned
Answer: c
Explanation: Using EA bit, all the interrupts can be enabled or disabled. Using the individual
respective bit, the respective interrupt can be enabled or disabled.
4. The number of priority levels that each interrupt of 8051 have is
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: Each interrupts level of 8051 can have two levels of priority namely level 0 and
level 1. Level 1 is considered as a higher priority level compared to level 0.
5. The priority level of an interrupt of 8051 for which SI
serialinterrupt
interrupt is programmed is
a) level 0
b) level 1
c) level 0 or level 1
d) none
Answer: b
Explanation: SI interrupt is programmed for level 1 priority.
6. The interrupt bit that when set works at level 1, and otherwise at level 0 is
a) PT1
b) PT0
c) PX1
d) All of the mentioned
Answer: d
Explanation: The bits, PT1, PT0, PX0 and PX1 when set, work at level 1, otherwise at level 0.
7. All the interrupts at level 1 are polled in the second clock cycle of the
a) forth T state
b) fifth T state
c) third T state
d) none
Answer: b
Explanation: All the interrupts at level 1 are polled or sensed in the second clock cycle of the
fifth T state or 9th clock cycle out of 12 clock cycles. Then all the interrupts at level 0 are also
polled in the same cycle.
8. The minimum duration of the active low interrupt pulse for being sensed without being lost
must be
a) greater than one machine cycle
b) equal to one machine cycle
c) greater than 2 machine cycles
d) equal to 2 machine cycles
Answer: b
Explanation: The minimum duration of the active low interrupt pulse should be equal to the
duration of one machine cycle for being sensed, else it will be lost.
9. If two interrupts, of higher priority and lower priority occur simultaneously, then the service
provided is for
a) interrupt of lower priority
b) interrupt of higher priority
c) lower & higher priority interrupts
d) none of the mentioned
Answer: b
Explanation: If two interrupts, occur simultaneously, then the one with higher priority level and
early polling sequence will receive service. The other one with lower priority may get lost there,
as there is no mechanism for storing the interrupt requests.
10. For an interrupt to be guaranteed served it should have duration of
a) one machine cycle
b) three machine cycles
c) two machine cycles
d) four machine cycles
Answer: c
Explanation: For an interrupt to be guaranteed served it should have duration of two machine
cycles.
11. The service to an interrupt will be delayed if it appears during the execution of
a) RETI instruction
b) Instruction that writes to IE register
c) Instruction that writes to IP register
d) All of the mentioned
Answer: d
Explanation: The service to an interrupt will be delayed if it appears during the execution of
RETI instruction or the instruction that writes to IE/IP registers.
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Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Serial Communication Unit”.
1. The serial communication is
a) cheaper communication
b) requires less number of conductors
c) slow process of communication
d) all of the mentioned
Answer: d
Explanation: The serial communication requires less number of conductors and thus it is
cheaper. It is slow as the bits are transmitted one by one along with start, stop and parity bits.
2. The serial communication is used for
a) short distance communication
b) long distance communication
c) short and long distance communication
d) communication for a certain range of distance
Answer: b
Explanation: Serial communication is more popular for communication over longer distances as
it requires less number of conductors.
3. The mcs 51 architecture supports
a) serial transmission and reception
b) simultaneous transmission and reception
c) transmission and reception of data using serial communication interface
d) all of the mentioned
Answer: d
Explanation: The mcs 51 architecture supports simultaneous transmission and reception of
binary data byte by byte i.e. full duplex mode of communication. It supports serial transmission
and reception of data using standard serial communication interface and baud rates.
4. The number of bits transmitted or received per second is defined as
a) transmission rate
b) reception rate
c) transceiver rate
d) baud rate
Answer: d
Explanation: Here, baud rate can be defined as the number of bits transmitted or received per
second.
5. The task of converting the byte into serial form and transmitting it bit by bit along with start,
stop and parity bits is carried out by
a) reception unit
b) serial communication unit
c) transmission unit
d) all of the mentioned
Answer: c
Explanation: the serial communication unit consists of transmission unit and reception unit. The
task of converting the byte into serial form and transmitting it bit by bit along with start, stop and
parity bits is carried out by transmission unit.
6. The transmission unit does not require assistance from processor if once a byte for
transmission is written to
a) SCON register
b) SBUF register
c) SFR address
d) Any of the mentioned
Answer: b
Explanation: once a byte for transmission is written to the serial buffer
SBUF
register, the transmission unit does not require assistance from a processor.
7. The common unit shared by the receiver unit and transmission unit of serial communication
unit is
a) SCON
SerialPortControl
Register
b) SBUF
SerialBuffer
register
c) 8-bit serial data interface
d) All of the mentioned
Answer: d
Explanation: The transmission unit and receiver unit both are controlled by using a common
SCON
SerialPortControl
Register. Also both units share a common serial buffer
SBUF
register which is a common 8-bit serial data interface.
8. During serial reception, the buffer that receives serial bits and converts to a byte is
a) receive buffer 0
b) receive buffer 1
c) receive buffer 2
d) none
Answer: b
Explanation: During serial reception, the receive buffer 1 receives serial bits and converts to a
byte, it then transfers the received parallel byte in receive buffer 2.
9. If SM0=1, SM1=0, then the transceiver selected is
a) 8-bit synchronous
b) 9-bit synchronous
c) 8-bit asynchronous
d) 9-bit asynchronous
Answer: d
Explanation: If SM0=1, SM1=0, then the 9-bit asynchronous transceiver is selected.
10. If the microcontroller is expected to communicate in a multiprocessor system, then the
required condition is
a) SM0 is set
b) SM1 is set
c) SM2 is set
d) REN is set
Answer: c
Explanation: The bit, SM2 is set if the microcontroller is expected to communicate in a
multiprocessor system.
11. In mode 2, the baud rate depends only on
a) SMOD bit
b) SCON bit
c) Oscillator clock frequency
d) SMOD bit and oscillator clock frequency
Answer: d
Explanation: In mode 2, the baud rate depends only on SMOD bit and oscillator clock frequency.
12. The mode that offers the most secured parity enabled data communication at lower baud
rates is
a) mode 2
b) mode 1
c) mode 0
d) all of the mentioned
Answer: a
Explanation: The mode 3 offers the most secured parity enabled data communication at lower
baud rates of mode 1.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
This set of Microprocessor Multiple Choice Questions & Answers
MCQs
focuses on “Power Control Register”.
1. The power control register is
a) used for power saving during idle state
b) used for eventual power off to 8051 chip
c) non-bit addressable register
d) all of the mentioned
Answer: d
Explanation: The power control register is used for power saving during idle state of the
microcontroller and eventual power off to the microcontroller chip. It has SMOD bit which is used
to double the baud rate.
2. The state of signals in idle mode is
a) ALE is high
b) PSEN is high
c) PSEN
activelow
is high
d) ALE and PSEN
activelow
are high
Answer: d
Explanation: ALE and PSEN
activelow
remain high in Idle mode.
3. To come out of idle mode, the external interrupt that is enabled is
a) SI
serial
b) INT0
c) INT1
d) All of the mentioned
Answer: d
Explanation: To come out of idle mode, any external interrupt that is enabled like SI
Serial
, INT0 and INT1.
4. The microcontroller enters into power down mode when
a) SMOD bit of PCON is set
b) GF1 bit of PCON is set
c) PD bit of PCON is set
d) GF2 bit of PCON is set
Answer: c
Explanation: If the PD bit of PCON register is set, it enters power down mode.
5. The clock signal is disabled to all parts of 8051 in
a) normal mode
b) idle mode
c) power down mode
d) addressing mode
Answer: c
Explanation: In power down mode, the clock signal to all parts of 8051 chip is disabled.
6. During power down to save battery, the supply voltage can be reduced to a value of
a) 4 volts
b) 2 volts
c) 8 volts
d) 1 volt
Answer: b
Explanation: The supply voltage can be reduced to a value of around 2 volts, during power
down to save battery.
7. The signal that only pulls the microcontroller
8051
out of the power down mode is
a) CLEAR
b) LEAVE
c) RESET
d) EXIT
Answer: c
Explanation: Only Reset signal can pull 8051 out of the power down mode.
8. The state of signals in power down mode is
a) ALE is high
b) PSEN is low
c) ALE and PSEN
activelow
are high
d) ALE and PSEN
activelow
are low
Answer: d
Explanation: ALE and PSEN
activelow
remain low in power down mode of 8051.
9. In power down mode,
a) Port pins maintain their logic levels
b) SFRs maintain their logic levels
c) Clock signal is disabled
d) All of the mentioned
Answer: d
Explanation: In power down mode, the clock signal is disabled and all the port pins and
respective SFRs maintain their logic levels.
10. The SMOD bit is used to
a) decrease the baud rate by 2
b) increase the baud rate by 4
c) increase the baud rate by 2
d) triple the baud rate
Answer: c
Explanation: The SMOD bit is used to double the baud rate.
To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice
Questions and Answers .
Unit 1 quiz
In which of these modes, the operand is included in the instruction itself?
a. immediate
b. register indirect
c. register
d. implied
When referring to instruction words, a mnemonic is:
a. A short abbreviation for the operation to be performed
b. A short abbreviation for the machine language
c. A short abbreviation for the operand address
d. A short abbreviation for the data word stored at the operand address
Identify the register that holds the instruction that is currently being executed or decoded
a. Instruction Register
b. MDR
c. Program Counter
d. MAR
……is a binary pattern that instructs a microprocessor to perform a specific task
a. microprocessor
b. addressing mode
c. computer
d. Instruction
Find a group of circuits that performs all the computations in the computer
a. Arithmetic Logic Unit
b. Control Unit
c. I/O Unit
d. memory
Analyze the scenario when reset key is pressed:
a. The internal operations are suspended and the program counter is cleared.
b. Processor transfers the control to a specific memory location mentioned in vector table
c. Microprocessor waits for the data from slow devices
d. Processor executes the ISR
Mnemonic-based language is called….
a. Machine language
b. High level language
c. Binary language
d. Assembly language
Select the program that converts mnemonic based language into microprocessor language
a. Interpreter
b. Translator
c. Compiler
d. Assembler
Analyze and match the following.
A. Microprocessor initiated operations
B. Externally or peripheral initiated operations
C. Microprocessor internal operations
1. Memory Read and Memory Write, Input Read and output Write
2. Determining how and what operations can be performed with the data
3. Reset, Ready, Interrupt, and Hold
Select one:
a. A-1 B-2 C-3
b. A-2 B-3 C-1
c. A-1 B-3 C-2
-----defines the number of steps by the microprocessor to complete an instruction
a. Cycle
b. Machine cycle
c. Instruction cycle
d. T-state
Define T-state by selecting the best description related to term t-state :
A. It is equivalent to a clock period
B. It is equivalent to a clock
C. It represents the subdivision of the operation performed in a clock cycle.
D. It represents the whole process
a. A and B
b. B and C
c. A and D
d. A and C
VLSI stands for
a. Volatile Large Scale Integration
b. Very Large Scale Integration
c. Virtual Large Scale Integration
d. Very Low Scale Integration
When the data itself present in the instruction then the addressing mode is referred to as
a. Immediate Addressing Mode
b. Direct Addressing Mode
c. Indirect Addressing Mode
d. Register Addressing Mode
A Direct memory access transfer represents
a. Transfer of data exclusively with in the microprocessor registers
b. A fast data transfer between microprocessor and I/O devices
c. Direct transfer of data between memory and I/O devices without use of microprocessor
d. Direct transfer of data between memory and accumulator
Differentiate between D-flip flop and D-latch by selecting the statement given below:
a. D-FF is level triggered and D-latch is edge triggered
b. D-FF is edge triggered and D-latch is level triggered
The addressing mode which uses the PC instead of a general-purpose register is ______
a. Relative
b. Indexed with offset
c. Direct
d. Both Indexed with offset and direct
In the following data transfer technique, the CPU enters in a loop until the I/O device indicates that it is ready to
transfer the data
a. All of the mentioned techniques
b. DMA technique
c. Interrupt Driven I/O technique
d. Programmed I/O
Select the 16 bit microprocessor from the given list:
a. 8086
b. 8080
c. 8085
d. 80386
In the case of, Zero-address instruction method the operands are stored in _____
a. Accumulators
b. Registers
c. Stack
d. Cache
_____ addressing mode is most suitable to change the normal sequence of execution of instructions.
a. Immediate
b. Index with Offset
c. Indirect
d. Relative
…….defines the time required by the microprocessor to complete one operation of accessing memory or I/O
devices
a. Instruction cycle
b. Cycle
c. Machine cycle
d. T-state
Identify the technique that uses the same address space
a. Both the mentioned
b. Memory Mapped I/O technique
c. None of the mentioned
d. Isolated I/O technique
Define the purpose of the interfacing devices by selecting the best statement matching with your definition
a. All of the mentioned
b. Interfacing devices are necessary to interconnect the components of a bus oriented system
c. Interfacing devices are the semiconductor chips that are needed to connect peripheral to the bus
d. Encoders and decoders can be used as the interfacing devices
Which addressing modes are used in pointers and arrays?
a. Indirect, indexed
b. Immediate , indirect
c. Direct, indexed
d. Indexed, register indirect
The handshaking mode of data transfer is……..
a. Synchronous data transfer
b. Asynchronous data transfer
c. Interrupt driven data transfer
d. DMA Mode of data transfer
Unit 2 Quiz solution
Calculate the number of t-states is required to draw the timing diagram for machine read cycle
a. 3
b. 1
c. 2
d. 4
Calculate the number of t-states to read the complete instruction LXI, A, 2050H from the main memory
a. 3
b. 4
c. 7
d. 10
ALE stands for
a. Allocation Latch Enable
b. Access Latch Enable
c. Address Latch Enable
An MVI A, 70 H is ……byte and used as ……instruction
a. two, arithmetic
b. three, data transfer
c. two, data transfer
d. three, arithmetic
Evaluate the memory addressed by the 8-bit microprocessor having 16 bit address lines
a. None of the mentioned
b. 216 bits
c. 216 bytes
d. 216 word
The register that holds the information about the nature of the result of arithmetic and logical operations is
called as …….
a. Stack Pointer
b. Program counter
c. Accumulator
d. Flag register
The following control and status signal represents the memory write operation:
a. S0=1, S1=1, I/O/M’=0, WR’=0
b. S0=1, S1=0, I/O/M’=0, WR’=1
c. S0=1, S1=0, I/O/M’=0, WR’=0
d. S0=0, S1=1, I/O/M’=0, WR’=0
Separate address space is used in the following data transfer techniques
a. None of the mentioned
b. Both the mentioned
c. Memory Mapped I/O technique
d. Isolated I/O technique
Identify the register pair that can be used as a valid pair of registers in 8085 microprocessor
a. BD
b. BH
c. BE
d. BC
The following control and status signal represents the opcode fetching operation:
a. S0=1, S1=0, I/O/M’=0, RD’=1
b. S0=1, S1=1, I/O/M’=0, RD’=0
c. S0=1, S1=0, I/O/M’=0, RD’=0
d. S0=0, S1=1, I/O/M’=0, RD’=0
LDA, 2050H instruction defines
a. The content of address 2050H will be loaded in accumulator
b. Address 2050H will loaded to accumulator
c. Address 2050H will loaded to register A
d. The content of register A will be loaded to the address 2050H
Calculate the number of bytes used to represent the LDA 2050H instruction.
a. 3
b. 2
c. 4
d. 1
………………is an input signal to the processor indicating an event that needs immediate attention of
microprocessor?
a. Addressing modes
b. Reset
c. Interrupt
d. Hold
Identify the applications of microprocessor
a. None of the mentioned
b. Embedded system
c. As a reprogrammable system
d. Both the mentioned
Analyze the purpose of the Maskable interrupts in the system. And select the correct form the following:
a. To handle the lower priority tasks
b. None of the mentioned
c. Both the mentioned
d. To handle the higher priority tasks
Calculate the word length of 64-bit microprocessor in bytes
a. 16
b. 64
c. 32
d. 8
Group A
A. 4-bit
B. 8-bit
C. 16-bit
D. 32 bit
Group B
1. 4004
2. 8088
3. 80486
4. 8008
Select one:
a. A-4, B-3, C-2, D-1
b. A-4, B-3, C-1, D-2
c. A-1, B-4, C-2, D-3
d. A-1, B-2, C-3, D-4
Identify the type of address and data buses used in 8085 microprocessor:
a. Dedicated Buses
b. Both the mentioned
c. None of the mentioned
d. Multiplexed buses
Group 1:
X: Indirect addressing
Y: Immediate addressing
Z: Auto decrement addressing
Group-2:
1. Loops
2. Pointers
3. Constants
a. X-3, Y-1, Z-2
b. X-1, Y-3, Z-2
c. X-2, Y-3, Z-1
d. X-3, Y-2, Z-1
Analyze the scenario where an instruction is stored at location 300 with its address fields at location 301. The
address field has the value 400. A processor register RI contain the number 200.
Evaluate the effective address if the addressing mode of the instruction is Register indirect Addressing Mode:
a. 301
b. 300
c. 400
d. 200
The following control and status signal represents the output write operation:
a. S0=0, S1=1, I/O/M’=1, WR’=0
b. S0=1, S1=0, I/O/M’=1, WR’=1
c. S0=1, S1=1, I/O/M’=1, WR’=0
d. S0=1, S1=0, I/O/M’=1, WR’=0
Where does a call instruction jump to?
a. A line at some random position in the function that the instruction is calling
b. The last line of the function that the instruction is calling.
c. None of the mentioned
d. The first line of the function that the instruction is calling.
Parity Flag is set when
a. The number of 1’s present in the result is even
b. The number of 1’s present in the result is odd
The following pin is used to acknowledge the interrupt in 8085 microprocessor
a. INTA’
b. RESET
c. READY
d. INTR
The following control and status signal represents the memory read operation:
a. S0=0, S1=1, I/O/M’=0, RD’=0
b. S0=1, S1=1, I/O/M’=0, RD’=0
c. S0=1, S1=0, I/O/M’=0, RD’=0
d. S0=1, S1=0, I/O/M’=0, RD’=1
Unit 3 Quiz
The work of EU
a) Encoding
b) Decoding
c) Calculation
d) Processing
The 16-bit flag of the microprocessor is responsible to indicate
a) The condition of the result of ALU
b) The condition of memory
c) The result of addition
d) The result of subtraction
BIU prefetches the instruction from the memory and srore them in the
a) Queue
b) Stack
c) Register
d) Memory
The instruction format ‘register to register’ has a length of
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
The BIU contains the FIFO register of size …bytes
a) 4
b) 5
c) 6
d) 8
8086 prefetches the instruction from
a) Code segment
b) Data segment
c) Extra segment
d) Stack segment
The R/M field in a machine instruction format specifies
a) another register
b) another memory location
c) other operands
d) all of the mentioned
RD’, WR’ and IO/M control is heart for a ……………..mode
a) Minimum
b) Maximum
c) Control
d) Compatible
The control flags in 8086 are:
a) the Trap flag(TF).
b) the interrupt flag(IF).
c) the direction flag(DF).
d) All of the above.
Which is not part of the execution unit (EU)?
A. Arithmetic logic unit (ALU)
B. Clock
C. General registers
D. Flags
In 8086 microprocessor one of the following statements is not true?
A. coprocessor is interfaced in max mode.
B. coprocessor is interfaced in min mode.
C. I /O can be interfaced in max / min mode.
D. supports pipelining
In 8086 the overflow flag is set when .
A. the sum is more than 16 bits.
B. signed numbers go out of their range after an arithmetic operation.
C. carry and sign flags are set.
D. subtraction
What is DEN?
A. direct enable
B. data entered
C. data enable
D. data encoding
The bit which is used by the ‘REP’ instruction is
a) W-bit
b) S-bit
c) V-bit
d) Z-bit
Explanation: The Z-bit is used by the REP instruction to control the loop.
8. If a W-bit value is ‘1’ then the operand is of
a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits
Example of an external interrupt is
a) divide by zero interrupt
b) keyboard interrupt
c) overflow interrupt
d) type2 interrupt
The labels or constants that can be used by any module in the program is possible when they are declared as
a) PUBLIC
b) LOCAL
c) GLOBAL
d) Either PUBLIC or GLOBAL
Match the following
a) DB 1) used to direct the assembler to reserve only 10-bytes
b) DT 2) used to direct the assembler to reserve only 4 words
c) DW 3) used to direct the assembler to reserve byte or bytes
d) DQ 4) used to direct the assembler to reserve words
a) a-3, b-2, c-4, d-1
b) a-2, b-3, c-1, d-4
c) a-3, b-1, c-2, d-4
d) a-3, b-1, c-4, d-2
After every response to the single step interrupt the flag that is cleared is
a) IF (Interrupt Flag)
b) TF (Trap Flag)
c) OF (Overflow Flag)
d) None of the mentioned
The interrupt for which the processor has the highest priority among all the external interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
The interrupt for which the processor has highest priority among all the internal interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
The INTR signal can be masked by resetting the
a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag
The status of the pending interrupts is checked at
a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle
Once the processor responds to an INTR signal, the IF is automatically
a) set
b) reset
c) high
d) low
The stack pointer register contains
a) address of the stack segment
b) pointer address of the stack segment
c) offset of address of stack segment
d) data present in the stack segment
Unit 4 quiz
The instruction that is used to transfer the data from source operand to destination operand is
a. String instruction
b. branch instruction
c. arithmetic/logical instruction
d. data transfer instruction
Which of the following instruction is not possible in 8085?
a. POP PSW
b. POP 30 H
c. POP B
d. POP D
The instruction that loads the flag register completely from the word contents of the memory location is
a. PUSH
b. POPF
c. POP
d. PUSHF
The instruction that supports addition when carry exists is
a. ADC
b. ADD
c. ADD and ADC
d. None of the mentioned
The flag that acts as Borrow flag in the instruction, SBB is
a. zero flag
b. sign flag
c. carry flag
d. Borrow Flag
How many T-states are required for execution of OUT 80H instruction?
a. 11
b. 12
c. 10
d. 13
How many machine cycles are required for the execution of IN 30H INSTRUCTION?
a. 3
b. 6
c. 4
d. 5
While INX B instruction execute
a. all flags will be affected
b. no flags will be affected
c. only carry and zero flags will be affected
d. only carry flag will be affected
Which flag will be affected by the execution of RLC /RRC/ RAL/ CMC instruction?
a. no flags will be affected
b. all flags will be affected
c. only carry flag will be affected
d. only carry and zero flags will be affected
A good assembly language programmers should use general-purpose registers rather than memory in the
maximum possible ways for data processing. This is because:
a. Data processing with registers takes fewer cycles than that with memory
b. Data processing with registers is easier than with memory
c. Data processing with memory requires more instructions in the program than that with registers
d. Of limited set of instructions for data processing with memory
………….used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by setting various bits to
form masks or generate output data via the Serial Output Data (SOD) line.
a. RIM
b. SIM
c. DI
d. EI
Interrupts are recognized during the execution of EI instruction
a. True
b. False
................is used to read the status of the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the A
register a byte which defines the condition of the mask bits for the interrupts.
a. SIM
b. DI
c. EI
d. RIM
Interrupts are recognized during execution of DI instruction
a. False
b. True
Placing an EI instruction on the bus in response to INTA’ during an INA cycles is prohibited
a. False
b. True
How many T-states is taken by the HLT instruction in 8085 microprocessor
a. 4
b. 5
c. 2
d. 3
How many T-states is taken by the NOP instruction in 8085 microprocessor
a. 5
b. 4
c. 2
d. 3
How many T-states is taken by the EI/ DI/ RIM/ SIM instructions in 8085 microprocessor
a. 4
b. 3
c. 2
d. 5
Which of the following instruction is used to provide delay?
a. HLT
b. NOP
c. Delay
d. Time delay
In which of the following addressing mode, the offset is obtained by adding displacement and contents of one of
the base registers?
a. indexed addressing mode
b. based addressing mode
c. register addressing mode
d. based and indexed addressing mode
Unit 5 Quiz Answer:
The block of 8237 that decodes the various commands given to the 8237 by the CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
In 8237, which block generates the internal timings and external control signals.
a. Bus interface unit
b. Execution unit
c. Timing and control block
d. None of the above
_____ register holds data during memory –memory data transfer
a. Temporary register
b. Command register
c. Mode register
d. None of the above
____ register keeps the track of all DMA channel pending requests and the status of terminal counts
a. Temporary register
b. Command register
c. Mode register
d. Status register
8251 is a
(A) UART
(B) USART
(C) Programmable Interrupt controller
(D) Programmable interval timer/counter Ans. B
Which is the commonly used programmable interface and particular used to provide handshaking:
A 8251
B 8254
C 8259
D 8255
The processor of knowing the status of device and transferring the data with matching speeds is called:
a. Handshaking
b. Peripheral
c. Ports
d. None of these
Which mode is used for single handshake in 8255:
a. Mode 0
b. Mode 1
c. Mode 2
d. None of these
How many ports do 8255 have?
A. 3
B. 4
C. 5
D. 6
Which of the following mode of 8255 is Strobed Bi-directional I/O?
A. Mode 0
B. Mode 1
C. Mode 2
D. Mode 4
Register must be initialized before any use of 8251.
a. Command word register
b. Control word register
c. Mode word register
d. Both Command word register and Mode word register.
8251 contains following blocks
a. Data bus buffer
b. Read write control logic
c. Transmitter section
d. Receiver section
e. Modem control
Ans: All of the above
8251 accepts on data & decides which part to activate when……………….
a. CS=0
b. C/D=0
c. CS=1
d. C/D=1
8251 support both synchronous & asynchronous communication.
a. True
b. False
Which of the following is not a mode of data transmission?
a) simplex
b) duplex
c) semi duplex
d) half duplex
In automatic rotation , the device , after being serviced , receives the ________ priority
A Lowest
B Highest
C Intermediate
D Cannot predict
The register that stores all the interrupt requests in it in order to serve them one by one on a priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
In 8259, The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
In 8259 cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
In 8259 application where all the interrupting devices are of equal priority, the mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
8086 is interfaced to two 8259s. If 8259s are in master slave configuration, the number of interrupts available to
the 8086 microprocessor are_____.
A8
B 16
C 15
D 64
In 8259, The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
In 8254, the generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
In 8254, in control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
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1. Oper When referring to instruction words, a mnemonic is
a short abbreviation for the operation to be performed.
a short abbreviation for the operand address.
shorthand for machine language.
a short abbreviation for the data word stored at the operand address-right option
Correct
All instructions are consists of opcode and operand where opcode indicates operation to be performed
and opcode is on which operation to be done. Opcodes are always expressed as a short abbreviation
which is nothing but mnemonic.
tion code field is present in :
a) programming language instruction
b) assembly language instruction
c) machine language instruction
d) none of the mentioned
View Answer
Answer: c
Explanation: Machine language instruction format has one or more fields. The first one is the
operation code field.
2. A machine language instruction format consists of
a) Operand field
b) Operation code field
c) Operation code field & operand field
d) none of the mentioned
View Answer
Answer: c
Explanation: Machine language instruction format has both the fields.
3. The length of the one-byte instruction is
a) 2 bytes
b) 1 byte
c) 3 bytes
d. None of these
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d) 4 bytes
View Answer
Answer: b
Explanation: This format is only one byte long.
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4. The instruction format ‘register to register’ has a length of
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
View Answer
Answer: a
Explanation: This format is 2 bytes long.
5. The R/M field in a machine instruction format specifies
a) another register
b) another memory location
c) other operands
d) all of the mentioned
View Answer
Answer: d
Explanation: The LSBs(least significant bits) from 0 to 3 represent R/M field that specifies another
register or memory location i.e. the other operand.
6. In a machine instruction format, S-bit is the
a) status bit
b) sign bit
c) sign extension bit
d) none of the mentioned
View Answer
Answer: c
Explanation: The S-bit known as sign extension bit is used along with W-bit to show the type of
operation.
7. The bit which is used by the ‘REP’ instruction is
a) W-bit
b) S-bit
c) V-bit
d) Z-bit
View Answer
Answer: d
Explanation: The Z-bit is used by the REP instruction to control the loop.
8. If a W-bit value is ‘1’ then the operand is of
a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits
View Answer
d. None of these
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Answer: c
Explanation: If W-bit is ‘1’ then the operand is of 16-bits, and if it is ‘0’ then the operand is of 8-
bits.
9. The instructions which after execution transfer control to the next instruction in the sequence
are called
a) Sequential control flow instructions
b) control transfer instructions
c) Sequential control flow & control transfer instructions
d) none of the mentioned
View Answer
Answer: a
Explanation: The sequential control flow instructions follow sequence order in their execution.
10. The instructions that transfer the control to some predefined address or the address specified
in the instruction are called as
a) sequential control flow instructions
b) control transfer instructions
c) sequential control flow & control transfer instructions
d) none of the mentioned
View Answer
Answer: b
Explanation: The control transfer instructions transfer control to the specified address.
11. The instruction “JUMP” belongs to
a) sequential control flow instructions
b) control transfer instructions
c) branch instructions
d) control transfer & branch instructions
View Answer
Answer: d
Explanation: The JUMP instruction transfers the control to the address located in the instruction.
. The instruction, MOV AX, 0005H belongs to the address mode
a) register
b) direct
c) immediate
d) register relative
View Answer
Answer: c
Explanation: In Immediate addressing mode, immediate data is a part of instruction and appears
in the form of successive byte or bytes.
2. The instruction, MOV AX, 1234H is an example of
a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
View Answer
d. None of these
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Answer: c
Explanation: Since immediate data is present in the instruction.
3. The instruction, MOV AX, [2500H] is an example of
a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
View Answer
Answer: b
Explanation: Since the address is directly specified in the instruction as a part of it.
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4. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
View Answer
Answer: b
Explanation: Since register is used to refer the address.
5. The instruction, MOV AX,[BX] is an example of
a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
View Answer
Answer: d
Explanation: Since the register used to refer to the address is accessed indirectly.
6. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned
View Answer
Answer: c
Explanation: In the indexed addressing mode, the offset of an operand is stored and in the rest of
them, address is stored.
7. The addressing mode that is used in unconditional branch instructions is
a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
View Answer
Answer: b
Explanation: In intrasegment indirect mode, the branch address is found as the content of a
register or a memory location.
d. None of these
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8. If the location to which the control is to be transferred lies in a different segment other than the
current one, then the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode
View Answer
Answer: d
Explanation: In intersegment mode, the control to be transferred lies in a different segment.
9. The instruction, JMP 5000H:2000H;
is an example of
a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode
View Answer
Answer: c
Explanation: Since in intersegment direct mode, the address to which the control is to be
transferred is in a different segment.
10. The contents of a base register are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode
View Answer
Answer: d
Explanation: The effective address is formed by adding the contents of both base and index
registers to a default segment.
1. The instruction that is used to transfer the data from source operand to destination operand is
a) data copy/transfer instruction
b) branch instruction
c) arithmetic/logical instruction
d) string instruction
View Answer
Answer: a
Explanation: These instructions are used to copy and transfer the instructions.
2. Which of the following is not a data copy/transfer instruction?
a) MOV
b) PUSH
c) DAS
d) POP
View Answer
Answer: c
Explanation: DAS (Decimal Adjust after Subtraction) is an arithmetic instruction.
3. The instructions that involve various string manipulation operations are
a) branch instructions
d. None of these
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b) flag manipulation instructions
c) shift and rotate instructions
d) string instructions
View Answer
Answer: d
Explanation: The string instructions perform operations on strings such as load, move, scan,
compare etc.
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4. Which of the following instruction is not valid?
a) MOV AX, BX
b) MOV DS, 5000H
c) MOV AX, 5000H
d) PUSH AX
View Answer
Answer: b
Explanation: Both the source and destination operands cannot be memory locations except for
string instructions.
5. In PUSH instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
View Answer
Answer: d
Explanation: The actual current stack-top is always occupied by the previously pushed data. So,
the push operation decrements SP by 2 and then stores the two bytes contents of the operand
onto the stack.
6. The instruction that pushes the contents of the specified register/memory location on to the
stack is
a) PUSHF
b) POPF
c) PUSH
d) POP
View Answer
Answer: c
Explanation: Since PUSH operation transfers data to stack from a register or memory location.
7. In POP instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
View Answer
Answer: c
Explanation: The actual current stack top is poped into the specific operand as the contents of
stack top memory is stored in AL&SP and further contents of the memory location pointed to by
SP are copied to AH & SP.
d. None of these
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8. The instructions that are used for reading an input port and writing an output port respectively
are
a) MOV, XCHG
b) MOV, IN
c) IN, MOV
d) IN, OUT
View Answer
Answer: d
Explanation: The address of the input/output port may be specified directly or indirectly.
Example for input port: IN AX, DX; This instruction reads data from a 16-bit port whose address is
in DX and stores it in AX
Example for output port: OUT 03H, AL; This sends data available in AL to a port whose address
is 03H.
9. The instruction that is used for finding out the codes in case of code conversion problems is
a) XCHG
b) XLAT
c) XOR
d) JCXZ
View Answer
Answer: b
Explanation: The translate(XLAT) instruction is used to find codes.
10. The instruction that loads effective address formed by destination operand into the specified
source register is
a) LEA
b) LDS
c) LES
d) LAHF
View Answer
Answer: a
Explanation: The instruction, LEA loads effective address and is more useful for assembly
language rather than for machine language.
11. The instruction that loads the AH register with the lower byte of the flag register is
a) SAHF
b) AH
c) LAHF
d) PUSHF
View Answer
Answer: c
Explanation: The instruction LAHF(Load AH from a lower byte of Flag) may be used to observe
the status of all the condition code flags(except overflow flag) at a time.
12. The instruction that pushes the flag register on to the stack is
a) PUSH
b) POP
c) PUSHF
d) POPF
View Answer
d. None of these
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Answer: c
Explanation: The instruction PUSHF(push flags to stack) pushes the flag register on to the stack.
13. The instruction that loads the flag register completely from the word contents of the memory
location is
a) PUSH
b) POP
c) PUSHF
d) POPF
View Answer
Answer: d
Explanation: POPF is pop flags to stack.
14. The instruction that adds immediate data/contents of the memory location specified in an
instruction/register to the contents of another register/memory location is
a) SUB
b) ADD
c) MUL
d) DIV
View Answer
Answer: b
Explanation: ADD instruction adds the data.
15. The instruction that supports addition when carry exists is
a) ADD
b) ADC
c) ADD & ADC
d) None of the mentioned
View Answer
Answer: b
Explanation: ADC(Add with Carry) instruction performs the same operation as ADD operation, but
adds the carry flag bit to the result
1. The instruction, “INC” increases the contents of the specified register or memory location by
a) 2
b) 0
c) 1
d) 3
View Answer
Answer: c
Explanation: This instruction adds 1 to the contents of the operand and so increments by 1.
2. The instruction that subtracts 1 from the contents of the specified register/memory location is
a) INC
b) SUBB
c) SUB
d) DEC
View Answer
Answer: d
Explanation: The DEC instruction decrements the contents of a specified register/memory location
by 1.
d. None of these
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3. The instruction that enables subtraction with borrow is
a) DEC
b) SUB
c) SBB
d) None of the mentioned
View Answer
Answer: c
Explanation: The SBB instruction subtracts the source operand and the borrow flag from the
destination operand.
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4. The flag that acts as Borrow flag in the instruction, SBB is
a) direction flag
b) carry flag
c) parity flag
d) trap flag
View Answer
Answer: b
Explanation: If borrow exists in the subtraction operation performed then carry flag is set.
5. In general, the source operand of an instruction can be
a) memory location
b) register
c) immediate data
d) all of the mentioned
View Answer
Answer: d
Explanation: The source operand is the element which is data or data stored memory location on
which operation is performed.
6. In general, the destination operand of an instruction can be
a) memory location
b) register
c) immediate data
d) memory location and register
View Answer
Answer: d
Explanation: Since the destination should be able to store the data, immediate data cannot be
considered as a destination operand.
7. The instruction, CMP to compare source and destination operands it performs
a) addition
b) subtraction
c) division
d) multiplication
View Answer
Answer: b
Explanation: For comparison, the instruction CMP subtracts source operand from destination
operand.
d. None of these
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8. During comparison operation, the result of comparing or subtraction is stored in
a) memory
b) registers
c) stack
d) no where
View Answer
Answer: d
Explanation: The result of subtraction operation is not stored anywhere during a comparison.
9. The instruction that converts the result in an unpacked decimal digits is
a) AAA
b) AAS
c) AAM
d) All of the mentioned
View Answer
Answer: d
Explanation: All the ASCII adjust instructions give result in unpacked decimal form and so are
called as “Unpacked BCD arithmetic instructions”.
10. Which of the following is a mnemonic?
a) ADD
b) ADC
c) AAA
d) ADD & ADC
View Answer
Answer: c
Explanation: AAA is a mnemonic. It doesn’t have either a source or destination operand.
11. The instruction in which adjustment is made before performing the operation is
a) AAA
b) AAS
c) AAM
d) AAD
View Answer
Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL. This adjustment must be made before dividing the two unpacked
BCD digits.
12. The expansion of DAA is
a) decimal adjust after addition
b) decimal adjust before addition
c) decimal adjust accumulator
d) decimal adjust auxiliary
View Answer
Answer: c
Explanation: This instruction performs conversion operation.
13. The instruction that is used to convert the result of the addition of two packed BCD numbers
to a valid BCD number is
a) DAA
d. None of these
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b) DAS
c) AAA
d) AAS
View Answer
Answer: a
Explanation: In this conversion, the result has to be only in AL.
14. The ROR instruction rotates the contents of the destination operand to
a) left
b) right
c) left and then right
d) right and then left
View Answer
Answer: b
Explanation: ROR stands for Rotate Right without carry. so, the instruction rotates right
1. The mnemonic that is placed before the arithmetic operation is performed is
a) AAA
b) AAS
c) AAM
d) AAD
View Answer
Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL.
2. The Carry flag is undefined after performing the operation
a) AAA
b) ADC
c) AAM
d) AAD
View Answer
Answer: d
Explanation: Since the operation, AAD is performed before division operation is performed, the
carry flag, auxiliary flag and overflow flag are undefined.
3. The instruction that performs logical AND operation and the result of the operation is not
available is
a) AAA
b) AND
c) TEST
d) XOR
View Answer
Answer: c
Explanation: In the TEST instruction, the logical AND operation is performed and the result is not
stored but flags are affected.
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4. In the RCL instruction, the contents of the destination operand undergo function as
a) carry flag is pushed into LSB & MSB is pushed into the carry flag
b) carry flag is pushed into MSB & LSB is pushed into the carry flag
d. None of these
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c) auxiliary flag is pushed into LSB & MSB is pushed into the carry flag
d) parity flag is pushed into MSB & LSB is pushed into the carry flag
View Answer
Answer: a
Explanation: In RCL(Rotate right through carry), for each operation, the carry flag is pushed into
LSB and the MSB of the operand is pushed into carry flag.
5. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX
register becomes zero is
a) SCAS
b) REP
c) CMPS
d) STOS
View Answer
Answer: b
Explanation: The instruction to which the REP is prefix, is executed repeatedly until CX register
becomes zero. When CX becomes zero, the execution proceeds to the next instruction in
sequence.
6. Match the following
A) MOvSB/SW 1) loads AL/AX register by content of a string
B) CMPS 2) moves a string of bytes stored in source to destination
C) SCAS 3) compares two strings of bytes or words whose length is stored
in CX register
D) LODS 4) scans a string of bytes or words
a) A-3,B-4,C-2,D-1
b) A-2,B-1,C-4,D-3
c) A-2,B-3,C-1,D-4
d) A-2,B-3,C-4,D-1
View Answer
Answer: d
Explanation: By using the string instructions, the operations on strings can be performed.
7. The instructions that are used to call a subroutine from the main program and return to the main
program after execution of called function are
a) CALL, JMP
b) JMP, IRET
c) CALL, RET
d) JMP, RET
View Answer
Answer: c
Explanation: At each CALL instruction, the IP and CS of the next instruction are pushed onto the
stack, before the control is transferred to the procedure. At the end of the procedure, the RET
instruction must be executed to retrieve the stored contents of IP & CS registers from a stack.
8. The instruction that unconditionally transfers the control of execution to the specified address
is
a) CALL
b) JMP
c) RET
d. None of these
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d) IRET
View Answer
Answer: b
Explanation: In this the control transfers to the address specified in the instruction and flags are
not affected by this instruction.
9. Which instruction cannot force the 8086 processor out of ‘halt’ state?
a) Interrupt request
b) Reset
c) Both interrupt request and reset
d) Hold
View Answer
Answer: d
Explanation: Only an interrupt request or Reset will force the 8086 processor to come out of the
‘halt’ state.
10. NOP instruction introduces
a) Address
b) Delay
c) Memory location
d) None of the mentioned
View Answer
Answer: b
Explanation: NOP is the No operation. It means that the processor performs no operation for the
clock cycle and thus there exists a delay.
11. Which of the following is not a machine controlled instruction?
a) HLT
b) CLC
c) LOCK
d) ESC
View Answer
Answer: b
Explanation: Since CLC is a flag manipulation instruction where CLC stands for Clear Carry Flag
1. The assembler directives which are the hints using some predefined alphabetical strings are
given to
a) processor
b) memory
c) assembler
d) processor & assembler
View Answer
Answer: c
Explanation: These directives help the assembler to correctly understand the assembly language
programs to prepare the codes.
2. The directive used to inform the assembler, the names of the logical segments to be assumed
for different segments used in the program is
a) ASSUME
b) SEGMENT
c) SHORT
d. None of these
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d) DB
View Answer
Answer: a
Explanation: In ALP, each segment is given a name by using the directive ASSUME
SYNTAX: ASSUME segment:segment_name
Eg: ASSUME CS:Code
here CS is the Code segment and code is the name assumed to the segment.
3. Match the following
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a) DB 1) used to direct the assembler to reserve only 10-bytes
b) DT 2) used to direct the assembler to reserve only 4 words
c) DW 3) used to direct the assembler to reserve byte or bytes
d) DQ 4) used to direct the assembler to reserve words
a) a-3, b-2, c-4, d-1
b) a-2, b-3, c-1, d-4
c) a-3, b-1, c-2, d-4
d) a-3, b-1, c-4, d-2
View Answer
Answer: d
Explanation: These directives are used for allocating memory locations in the available memory.
4. The directive that marks the end of an assembly language program is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
View Answer
Answer: b
Explanation: The directive END is used to denote the completion of the program.
5. The directive that marks the end of a logical segment is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
View Answer
Answer: a
Explanation: The directive ENDS is used to end a segment where as the directive END is used to
end the program.
6. The directive that updates the location counter to the next even address while executing a series
of instructions is
a) EVN
b) EVEN
c) EVNE
d) EQU
View Answer
d. None of these
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Answer: b
Explanation: The directive updates location counter to next even address if the current location
counter contents are not even.
7. The directive that directs the assembler to start the memory allotment for a particular
segment/block/code from the declared address is
a) OFFSET
b) LABEL
c) ORG
d) GROUP
View Answer
Answer: c
Explanation: If an ORG is written then the assembler initiates the location counter to keep the
track of allotted address for the module as mentioned in the directive.
If the directive is not present, then the location counter is initialized to 0000H.
8. The directive that marks the starting of the logical segment is
a) SEG
b) SEGMENT
c) SEG & SEGMENT
d) PROC
View Answer
Answer: b
Explanation: The directive SEGMENT indicates the beginning of the segment.
9. The recurrence of the numerical values or constants in a program code is reduced by
a) ASSUME
b) LOCAL
c) LABEL
d) EQU
View Answer
Answer: d
Explanation: In this, the recurring/repeating value is assigned with a label. The label is placed
instead of the numerical value in the entire program code.
10. The labels or constants that can be used by any module in the program is possible when they
are declared as
a) PUBLIC
b) LOCAL
c) GLOBAL
d) Either PUBLIC or GLOBAL
View Answer
Answer: c
Explanation: The labels, constants, variables, procedures declared as GLOBAL can be used by
any module in the program.
1. The logic required for implementing a program can be expressed in terms of
a) flowchart
b) algorithm
c) flowchart & algorithm
d. None of these
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d) none of the mentioned
View Answer
Answer: c
Explanation: The logic required for implementing a program must be visualized clearly which is
possible by flowchart and algorithm.
2. The operands, source and destination in an instruction cannot be
a) register, register
b) memory location, memory location
c) memory location, register
d) immediate data, register
View Answer
Answer: b
Explanation: Only one memory operand can be specified in one instruction.
3. The instruction that is not possible among the following is
a) MOV AX, BX
b) MOV AX, [BX].
c) MOV 55H, BL
d) MOV AL, 55H
View Answer
Answer: c
Explanation: 8-bit or 16-bit operand cannot be used as a destination operand.
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4. The instruction that is not possible among the following is
a) MOV AX, [BX].
b) MOV AX, 5555H
c) MOV AX, [SI].
d) MOV [SI], [DI].
View Answer
Answer: d
Explanation: Both the operands cannot be memory operands.
5. Both the operands source and destination of an instruction cannot be
a) register, register
b) immediate data, register
c) register, immediate data
d) immediate data, memory location
View Answer
Answer: c
Explanation: Since destination operand should not be immediate data.
6. The registers that cannot be used as operands for arithmetic and logical instructions are
a) general purpose registers
b) pointers
c) index registers
d) segment registers
View Answer
Answer: d
Explanation: Segment registers are not allowed as operands for arithmetic and logical instructions.
d. None of these
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7. The operands of an instruction cannot be
a) registers
b) memory operands and immediate operands
c) immediate operands
d) memory operands
View Answer
Answer: b
Explanation: Both the operands should not be immediate operands and memory operands.
1. The disadvantage of machine level programming is
a) time consuming
b) chances of error are more
c) debugging is difficult
d) all of the mentioned
View Answer
Answer: d
Explanation: The machine level programming is complicated.
2. The coded object modules of the program to be assembled are present in
a) .ASM file
b) .OBJ file
c) .EXE file
d) .OBJECT file
View Answer
Answer: b
Explanation: .OBJ file is created with same name as source file and extension .OBJ. It contains
the coded object modules of the program to be assembled.
3. The advantages of assembly level programming are
a) flexibility of programming is more
b) chances of error are less
c) debugging is easy
d) all of the mentioned
View Answer
Answer: d
Explanation: The assembly level programming is more advantageous than the machine level
programming.
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4. The extension that is essential for every assembly level program is
a) .ASP
b) .ALP
c) .ASM
d) .PGM
View Answer
Answer: c
Explanation: All the files should have the extension, .ASM.
5. The directory that is under work must have the files that are related to
a) Norton’s editor
d. None of these
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b) Assembler
c) Linker
d) All of the mentioned
View Answer
Answer: d
Explanation: Before starting the process of entering a small program on PC, ensure that all the
files namely Norton’s editor, assembler, linker and debugger are available in the same directory
in which work is been done.
6. The listing file is identified by
a) source file name
b) extension .LSF
c) source file name and an extension .LSF
d) source file name and an extension .LST
View Answer
Answer: d
Explanation: The listing file is automatically generated in the assembly process and is identified
by the entered or source file name and an extension .LST.
7. The extension file that is must for a file to be accepted by the LINK as a valid object file is
a) .OBJ file
b) .EXE file
c) .MASM file
d) DEBUG file
View Answer
Answer: a
Explanation: The .OBJ extension is a must for a file to be accepted by the LINK as a valid object
file.
8. The listing file contains
a) total offset map of a source file
b) offset address and labels
c) memory allotments for different labels
d) all of the mentioned
View Answer
Answer: d
Explanation: The listing file contains total offset map of source file including labels, offset
addresses, opcodes, memory allotments for different directives and labels and relocation
information.
9. DEBUG.COM facilitates the
a) debugging
b) trouble shooting
c) debugging and trouble shooting
d) debugging and assembling
View Answer
Answer: c
Explanation: DEBUG.COM is a DOS utility that facilitates the debugging and trouble shooting.
10. DEBUG is able to troubleshoot only
a) .EXE files
d. None of these
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b) .OBJ files
c) .EXE file and .OBJ file
d) .EXE flie and .LST file
View Answer
Answer: a
Explanation: The DEBUG may be used either to debug a source program or to observe the results
of execution of an .EXE file.
1. The Stack follows the sequence
a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out
View Answer
Answer: c
Explanation: The stack follows last-in-first-out sequence.
2. If the processor is executing the main program that calls a subroutine, then after executing the
main program up to the CALL instruction, the control will be transferred to
a) address of main program
b) subroutine address
c) address of CALL instruction
d) none of the mentioned
View Answer
Answer: b
Explanation: Since subroutine is called, to start the execution of the subroutine, the control is
transferred to the subroutine address.
3. The stack is useful for
a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned
View Answer
Answer: d
Explanation: Stack is used for temporary storage of contents of registers and memory locations,
status of registers.
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4. The Stack is accessed using
a) SP register
b) SS register
c) SP and SS register
d) None of the mentioned
View Answer
Answer: c
Explanation: The stack is accessed using a pointer that is implemented using SP and SS registers.
5. As the storing of data words onto the stack is increased, the stack pointer is
a) incremented by 1
d. None of these
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b) decremented by 1
c) incremented by 2
d) decremented by 2
View Answer
Answer: d
Explanation: The data is stored from top address of the stack and is decremented by 2.
6. While retrieving data from the stack, the stack pointer is
a) incremented by 1
b) incremented by 2
c) decremented by 1
d) decremented by 2
View Answer
Answer: b
Explanation: The data in the stack, may again be transferred back from a stack to register. At that
time, the stack pointer is incremented by 2.
7. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into
View Answer
Answer: c
Explanation: The data is pushed into the stack while loading the stack.
8. The reverse process of transferring the data back from the stack to the CPU register is known
as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack
View Answer
Answer: d
Explanation: The data retrieved from stack is called popping off.
9. The books arranged one on the other on a table is an example of
a) queue
b) queue and first-in-first out
c) stack
d) stack and last-in-first-out
View Answer
Answer: d
Explanation: If the books are arranged one on the other, then the book that is placed last will be
the first out.
10. The PID temperature controller using 8086 has
a) data flow
b) data flow and uses queue
c) sequential flow
d. None of these
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d) sequential flow and uses stack
View Answer
Answer: d
Explanation: Since PID temperature controller has steps that need to be sequentially executed
such as sampling the output, conversion of a signal with ADC, finding errors, deriving control
signals and applying the control signal to control flow of energy.
1. The stack pointer register contains
a) address of the stack segment
b) pointer address of the stack segment
c) offset of address of stack segment
d) data present in the stack segment
View Answer
Answer: c
Explanation: The stack pointer register contains the offset of the address of the stack segment.
2. The stack segment register contains
a) address of the stack segment
b) base address of the stack segment
c) pointer address of the stack segment
d) data in the stack segment
View Answer
Answer: b
Explanation: The stack segment register contains base address of the stack segment in the
memory. The stack pointer register (sP) and stack segment register (SS) together address the
stack-top.
3. PUSH operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
View Answer
Answer: a
Explanation: Each PUSH operation decrements the SP ( Stack Pointer) register.
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4. POP operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
View Answer
Answer: b
Explanation: Each POP operation increments the SP ( Stack Pointer) register.
5. The register or memory location that is pushed into the stack at the end must be
a) popped off last
b) pushed off first
c) popped off first
d. None of these
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d) pushed off last
View Answer
Answer: c
Explanation: The data can be retrieved by POP operation and as in stack, the data that is pushed
at the end must be popped off first.
6. In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK
the ASSUME directive directs to the assembler the
a) address of the stack segment
b) pointer address of the stack segment
c) name of the stack segment
d) name of the stack, code and data segments
View Answer
Answer: d
Explanation: The directive ASSUME facilitates to name the segments with the desired name that
is not a mnemonic or keyword.
7. When a stack segment is initialised then
a) SS and SP are initialised
b) only SS is initialised
c) only SP is initialised
d) SS and SP need not be initialised
View Answer
Answer: a
Explanation: Though the Stack segment is initialised, the SS and SP pointers must be initialised.
8. The number of PUSH instructions and POP instructions in a subroutine must be
a) PUSH instructions must be greater than POP instructions
b) POP instructions must be greater than PUSH instructions
c) Both must be equal
d) Instructions may be any kind
View Answer
Answer: c
Explanation: The number of PUSH instructions must be equal to the number of POP instructions.
9. 8086 does not support
a) Arithmetic operations
b) logical operations
c) BCD operations
d) Direct BCD packed multiplication
View Answer
Answer: d
Explanation: The 8086 microprocessor does not support direct BCD packed operations.
10. For 8086 microprocessor, the stack segment may have a memory block of a maximum of
a) 32K bytes
b) 64K bytes
c) 16K bytes
d) NONE
View Answer
d. None of these
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Answer: b
Explanation: In 8086 microprocessor, the memory segments each have a memory of 64K bytes.
1. While CPU is executing a program, an interrupt exists then it
a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
View Answer
Answer: c
Explanation: An interrupt function is to break the sequence of operation.
2. An interrupt breaks the execution of instructions and diverts its execution to
a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit
View Answer
Answer: a
Explanation: An interrupt transfers the control to interrupt service routine (ISR). After executing
ISR, the control is transferred back again to the main program.
3. While executing the main program, if two or more interrupts occur, then the sequence of
appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt
View Answer
Answer: d
Explanation: If an interrupt occurs while executing a program, and the processor is executing the
interrupt, if one more interrupt occurs again, then it is called a nested interrupt.
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4. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to handle
them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability
View Answer
Answer: c
Explanation: The processor if handles more devices as interrupts then it has multiple interrupt
processing ability.
5. NMI stands for
a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none of the mentioned
View Answer
d. None of these
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Answer: a
Explanation: NMI is the acronym for nonmaskable interrupt.
7. If any interrupt request given to an input pin cannot be disabled by any means then the input
pin is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
d) none of the mentioned
View Answer
Answer: b
Explanation: A nonmaskable interrupt input pin is one which means that any interrupt request at
NMI (nonmaskable interrupt) input cannot be masked or disabled by any means.
8. The INTR interrupt may be
a) maskable
b) nonmaskable
c) maskable and nonmaskable
d) none of the mentioned
View Answer
Answer: a
Explanation: the INTR (interrupt request) is maskable or can be disabled.
9. The Programmable interrupt controller is required to
a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request
View Answer
Answer: b
Explanation: If more than one interrupt request (INTR) occurs at a time, then an external chip
called programmable interrupt controller is required to handle them.
10. The INTR interrupt may be masked using the flag
a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag
View Answer
Answer: c
Explanation: If a microprocessor wants to serve any interrupt then interrupt flag, IF=1. If interrupt
flag, IF=0, then the processor ignores the service.
1. If an interrupt is generated from outside the processor then it is an
a) internal interrupt
b) external interrupt
c) interrupt
d) none of the mentioned
View Answer
d. None of these
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Answer: b
Explanation: If an external device or a signal interrupts the processor from outside then it is an
external interrupt.
2. If the interrupt is generated by the execution of an interrupt instruction then it is
a) internal interrupt
b) external interrupt
c) interrupt-in-interrupt
d) none of the mentioned
View Answer
Answer: a
Explanation: The internal interrupt is generated internally by the processor circuit or by the
execution of an interrupt instruction.
3. Example of an external interrupt is
a) divide by zero interrupt
b) keyboard interrupt
c) overflow interrupt
d) type2 interrupt
View Answer
Answer: b
Explanation: Since the keyboard is external to the processor, it is an external interrupt.
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4. Example of an internal interrupt is
a) divide by zero interrupt
b) overflow interrupt
c) interrupt due to INT
d) all of the mentioned
View Answer
Answer: d
Explanation: Since the interrupts occur within the processor itself, they are called internal
interrupts.
5. The interrupt request that is independent of IF flag is
a) NMI
b) TRAP
c) Divide by zero
d) All of the mentioned
View Answer
Answer: d
Explanation: These requests are independent of IF flag.
6. The type of the interrupt may be passed to the interrupt structure of CPU from
a) interrupt service routine
b) stack
c) interrupt controller
d) none of the mentioned
View Answer
Answer: c
Explanation: After an interrupt is acknowledged, the CPU computes the vector address from the
d. None of these
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type of the interrupt that may be passed to the internal structure of the CPU from an interrupt
controller in case of external interrupts.
7. During the execution of an interrupt, the data pushed into the stack is the content of
a) IP
b) CS
c) PSW
d) All of the mentioned
View Answer
Answer: d
Explanation: The contents of IP, CS and PSW are pushed into the stack during the execution.
8. After every response to the single step interrupt the flag that is cleared is
a) IF (Interrupt Flag)
b) TF (Trap Flag)
c) OF (Overflow Flag)
d) None of the mentioned
View Answer
Answer: b
Explanation: If the trap flag is set then the processor enters the single step execution mode. After
the execution, the trap flag is cleared.
9. At the end of ISR, the instruction should be
a) END
b) ENDS
c) IRET
d) INTR
View Answer
Answer: c
Explanation: After the execution of the ISR, the control must go to the previous program (maybe
main program) which was being executed. To execute it, IRET is placed at the end of ISR.
10. When the CPU executes IRET,
a) contents of IP and CS are retrieved
b) the control transfers from ISR to main program
c) clears the trap flag
d) clears the interrupt flag
View Answer
Answer: a
Explanation: When the instruction IRET is executed, the contents of flags, IP and CS which were
saved at the stack by the CALL instruction are retrieved to the respective registers.
1. The interrupt for which the processor has the highest priority among all the external interrupts
is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
View Answer
d. None of these
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Answer: c
Explanation: The Non-Maskable Interrupt input pin has the highest priority among all the external
interrupts.
2. The interrupt for which the processor has highest priority among all the internal interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
View Answer
Answer: b
Explanation: TRAP is the internal interrupt that has highest priority among all the interrupts except
the Divide By Zero (Type 0) exception.
3. In case of string instructions, the NMI interrupt will be served only after
a) initialisation of string
b) execution of some part of the string
c) complete string is manipulated
d) the occurrence of the interrupt
View Answer
Answer: c
Explanation: When NMI is activated, the current instruction being executed is completed and then
NMI is served. In the case of string instructions, it is served after the complete string is
manipulated.
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4. The NMI pin should remain high for atleast
a) 4 clock cycles
b) 3 clock cycles
c) 1 clock cycle
d) 2 clock cycles
View Answer
Answer: d
Explanation: The NMI pin should remain high for atleast 2 clock cycles and need not be
synchronized with the clock for being sensed.
5. The INTR signal can be masked by resetting the
a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag
View Answer
Answer: b
Explanation: The INTR signal can be masked by resetting the interrupt flag.
6. For the INTR signal, to be responded to in the next instruction cycle, it must go ________ in the
last clock cycle of the current instruction
a) high
b) low
c) high or low
d. None of these
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d) unchanged
View Answer
Answer: a
Explanation: The INTR signal must go high in the clock cycle of the current instruction in order to
respond in the next instruction cycle.
7. The status of the pending interrupts is checked at
a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle
View Answer
Answer: d
Explanation: At the end of each instruction, the status of the pending interrupts is checked.
8. Once the processor responds to an INTR signal, the IF is automatically
a) set
b) reset
c) high
d) low
View Answer
Answer: b
Explanation: The IF is automatically reset when the processor responds to an INTR signal. If the
processor wants to respond to any type of INTR signal further then, the IF should again be set.
9. If the pin LOCK (active low based) is low at the trailing edge of the first ALE pulse, then till the
start of the next machine cycle, the pin LOCK (active low) is
a) low
b) high
c) low or high
d) none of the mentioned
View Answer
Answer: a
Explanation: The pin LOCK (active low) remains low till the start of the next machine cycle.
10. With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in
it for
a) 0 clock cycle
b) 1 clock cycle
c) 2 clock cycles
d) 3 clock cycles
View Answer
Answer: c
Explanation: The INTA (active low) goes low and remains low for two clock cycles before returning
back to the high state.
1. The method of defining the interrupt service routine for software is
a) same as that of hardware
b) difficult than hardware
c) easier than software
d. None of these
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d) none of the mentioned
View Answer
Answer: a
Explanation: For both software and hardware, the method of defining the interrupt service routine
is the same.
2. While programming for any type of interrupt, the interrupt vector table is set
a) externally
b) through a program
c) either externally or through the program
d) externally and through the program
View Answer
Answer: c
Explanation: The programmer must, either externally or through the program, set the interrupt
vector table for that type preferably with the CS and IP addresses of the interrupt service routine.
3. To execute a program one should
a) assemble the program
b) link the program
c) apply external pulse
d) all of the mentioned
View Answer
Answer: d
Explanation: To execute a program, first assemble it, link it and then execute it. After execution, a
new file RESULT is created in the directory. Then external pulse is applied to IRQ2 pin, and this
will again cause the execution of ISR into the file.
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4. Procedures are also known as
a) macros
b) segment
c) subroutines
d) none
View Answer
Answer: c
Explanation: Procedures are also known as subroutines.
5. Procedures, for their execution, require
a) input data
b) output data
c) constants
d) input data or constants
View Answer
Answer: d
Explanation: Procedures require input data or constants for their execution. Their data or
constants may be passed to the subroutine by the main program.
6. The technique that is used to pass the data or parameter to procedures in assembly language
program is by using
a) global declared variable
b) registers
d. None of these
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c) stack
d) all of the mentioned
View Answer
Answer: d
Explanation: The techniques that are used to pass the data or parameter to procedures are by
using global declared variable, registers of CPU, memory locations, stack, PUBLIC & EXTRN.
7. If a procedure is interactive, then
a) it accepts inputs directly from input devices
b) it uses global declared variable technique
c) it uses stack
d) it uses memory locations
View Answer
Answer: a
Explanation: If a procedure is interactive, then it accepts the inputs directly from input devices.
8. For passing the parameters to procedures using the PUBLIC & EXTRN directives, it must be
declared PUBLIC in the
a) subroutine
b) procedure
c) main routine
d) main routine and subroutine
View Answer
Answer: c
Explanation: For passing the parameters to procedures, it must be declared PUBLIC in the main
routine and the same should be declared EXTRN in the procedure.
9. The technique to estimate the size of an executable program, before it is assembled and linked
is
a) memory location technique
b) global variable technique
c) stack
d) none
View Answer
Answer: d
Explanation: There is no technique to estimate the size of an executable program before it is
assembled and linked.
10. To estimate the size of an executable program before it is assembled and linked, the
programming methodology concerned is by writing
a) programs with more than one segment for data and code
b) programs with FAR subroutines each of size up to 64KB
c) programs with more than one segment for stack
d) all of the mentioned
View Answer
Answer: d
Explanation: By writing programs with more than one segment for data, code or stack or by writing
programs with FAR subroutines each of size 64KB, the size of an executable program can be
estimated.
d. None of these
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1. If a number of instructions are repeating through the main program, then to reduce the length
of the program, __________ is used.
a) procedure
b) subroutine
c) macro
d) none of the mentioned
View Answer
Answer: c
Explanation: For a certain number of instructions that are repeated in the main program, when
macro is defined then the code of a program is reduced by placing the name of the macro at which
the set of instructions are needed to be repeated.
2. The process of assigning a label or macroname to the string is called
a) initialising macro
b) initialising string macro
c) defining a string macro
d) defining a macro
View Answer
Answer: d
Explanation: The process of assigning a label to the string is called defining a macro.
3. A macro within a macro is called
a) macro-within-macro
b) nested macro
c) macro-in-macro
d) none of the mentioned
View Answer
Answer: b
Explanation: A macro may be called from inside a macro. This type of macro is called nested
macro.
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4. A macro can be defined as
a) beginning of a program
b) end of a program
c) after initialisation of program
d) anywhere in a program
View Answer
Answer: d
Explanation: A macro can be defined anywhere in a program.
5. A macro can be used as ________
a) in data segment
b) to represent directives
c) to represent statements
d) all of the mentioned
View Answer
Answer: d
Explanation: A macro may be used in data segment and can also be used to represent statements
and directives.
d. None of these
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6. The end of a macro can be represented by the directive.
a) END
b) ENDS
c) ENDM
d) ENDD
View Answer
Answer: c
Explanation: The ENDM directive marks the end of the instructions or statements sequence
assigned with the macro name.
7. Inserting the statements and instructions represented by macro, directly at the place of the
macroname, in the program, is known as
a) calling a macro
b) inserting a macro
c) initializing a macro
d) none of the mentioned
View Answer
Answer: a
Explanation: Inserting the statements and instructions at the place of macroname, in the program,
is known as calling a macro.
8. The time required for execution of a macro is ________ that of the procedure.
a) greater than
b) less than
c) equal to
d) none of the mentioned
View Answer
Answer: b
Explanation: The time required for execution of a macro is less than that of procedure as it does
not contain CALL and RET instructions as the procedures do.
9. Which of the following statements is incorrect?
a) complete code of instruction string is inserted at each place, wherever the macroname appears
b) macro requires less time of execution than that of procedure
c) macro uses stack memory
d) macroname can be anything except registers and mnemonics
View Answer
Answer: c
Explanation: Macro does not require stack memory and hence has less time for execution.
10. The beginning of the macro can be represented as
a) START
b) BEGIN
c) MACRO
d) None of the mentioned
View Answer
Answer: c
Explanation: The beginning of the macro is represented as macroname followed by the directive
MACRO.
SYNTAX: macroname MACRO
EXAMPLE: STRINGS MACRO.
d. None of these
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Rooma, Kanpur – 208 008
1. If ‘n’ denotes the number of clock cycles and ‘T’ denotes period of the clock at which the
microprocessor is running, then the duration of execution of loop once can be denoted by
a) n+T
b) n-T
c) n*T
d) n/T
View Answer
Answer: c
Explanation: The duration of execution of the loop is the product of number of clock cycles and
the period of the clock cycle at which microprocessor is running.
2. The number of instructions actually executed by the microprocessor depends on the
a) stack
b) loop count
c) program counter
d) time duration
View Answer
Answer: b
Explanation: As the microprocessor executes each instruction corresponding loop counter value
decreases and the microprocessor executes the instructions till the loop counter becomes zero.
3. In case of subroutines, the actual number of instructions executed by the processor depends
on
a) loop count
b) length of interrupt service routine
c) length of procedure
d) none
View Answer
Answer: c
Explanation: In case of subroutines or interrupt service routines, the number of instructions
executed by the processor depends on the length of procedure (or subroutine) or length of interrupt
service routine along with the main calling program.
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4. The step included in generating delays is
a) determining exact required delay
b) selecting instructions for delay loop
c) finding period of clock frequency
d) all of the mentioned
View Answer
Answer: d
Explanation: The delays can be generated step wise.
5. The Count, N can be defined as
a) required delay/duration for execution
b) duration of execution/required delay
c) required delay/number of clock cycles
d) required delay/period of clock frequency
View Answer
d. None of these
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Answer: a
Explanation: The count N can be defined as the required time delay by the duration for execution
of the loop once.
Count, N = required delay (Td)/duration for execution of the loop once (n*T).
6. In the instruction set,
MOV CX, BA03H
WAIT: DEC CX
NOP
JNZ WAIT
RET
if the zeroth condition is satisfied then, for execution, the JNZ instruction takes
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
View Answer
Answer: d
Explanation: The JNZ instruction takes only 4 clock cycles if the zeroth condition is satisfied.
7. In the instruction set,
MOV CX, BA03H
WAIT: DEC CX
NOP
JNZ WAIT
RET
if the zeroth condition is not satisfied, then the JNZ instruction takes
a) 2 clock cycles
b) 8 clock cycles
c) 16 clock cycles
d) 64 clock cycles
View Answer
Answer: c
Explanation: The JNZ instruction takes 16 clock cycles if the zeroth condition is not satisfied.
8. The maximum count value of 16-bit count register puts a limitation on
a) memory usage
b) storage of address of registers
c) to generate clock pulse
d) to generate maximum delay
View Answer
Answer: d
Explanation: The maximum count value of 16-bit count register is FFFFH. This may put the
limitation on the maximum delay that can be generated using the instructions.
9. When large delays are required, then to serve the purpose
a) one or more count registers can be used
b) one or more shift registers can be used
c) one or more pointer registers can be used
d. None of these
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d) one or more index registers can be used
View Answer
Answer: a
Explanation: One or more count registers can be used to serve large delays.
1. The semiconductor memories are organised as __________ dimension(s) of array of memory
locations.
a) one dimensional
b) two dimensional
c) three dimensional
d) none
View Answer
Answer: b
Explanation: The semiconductor memories are organised as two dimensions of an array which
consists of rows and columns.
2. If a location is selected, then all the bits in it are accessible using a group of conductors called
a) control bus
b) address bus
c) data bus
d) either address bus or data bus
View Answer
Answer: c
Explanation: The bits in a selected location are accessible using data bus.
3. To address a memory location out of N memory locations, the number of address lines required
is
a) log N (to the base 2)
b) log N (to the base 10)
c) log N (to the base e)
d) log (2N) (to the base e)
View Answer
Answer: a
Explanation: For n memory locations, log n(to the base of 2) address lines are required. For
addressing 4K bytes of memory, 12 address lines are required since log(4KB)
=log(4*1024)=log(212)=12.
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4. If the microprocessor has 10 address lines, then the number of memory locations it is able to
address is
a) 512
b) 1024
c) 2048
d) none
View Answer
Answer: b
Explanation: Since for n address lines, the number of memory locations able to address is 2^n.
5. In static memory, the upper 8-bit bank of an available 16-bit memory chip is called
a) upper address memory bank
d. None of these
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b) even address memory bank
c) static upper memory
d) odd address memory bank
View Answer
Answer: d
Explanation: In static memory, the upper 8-bit bank is called odd address memory bank.
6. In static memory, the lower 8-bit bank of an available 16-bit memory chip is called
a) lower address memory bank
b) even address memory bank
c) static lower memory bank
d) odd address memory bank
View Answer
Answer: b
Explanation: In static memory, the lower 8-bit bank is called even address memory bank.
7. In most of the cases, the method used for decoding that may be used to minimise the required
hardware is
a) absolute decoding
b) non-linear decoding
c) linear decoding
d) none
View Answer
Answer: c
Explanation: In general, linear decoding is used to minimise the required hardware.
8. To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
a) parallel
b) serial
c) both serial and parallel
d) neither serial nor parallel
View Answer
Answer: a
Explanation: The two 4K*8 chips of RAM and ROM are arranged in parallel.
9. If (address line) Ao=0 then, the status of address and memory are
a) address is even and memory is in ROM
b) address is odd and memory is in ROM
c) address is even and memory is in RAM
d) address is odd and memory is in RAM
View Answer
Answer: c
Explanation: If Ao=0 then address is even and is in RAM. If Ao=1 then, address is odd and is in
RAM.
10. If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be
a) RAM
b) ROM
c) RAM and ROM
d) ONLY RAM
View Answer
d. None of these
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Answer: c
Explanation: If at a time Ao and BHE(active low) both are zero, then both RAM and ROM are
selected
1. The advantage of dynamic RAM is
a) high packing density
b) low cost
c) less power consumption
d) all of the mentioned
View Answer
Answer: d
Explanation: The dynamic RAM is advantageous than the static RAM as it has a higher packing
density, lower cost and less power consumption.
2. Whenever a large memory is required in a microcomputer system, the memory subsystem is
generally designed using
a) Static RAM
b) Dynamic RAM
c) Both static and dynamic RAM
d) ROM
View Answer
Answer: b
Explanation: Dynamic RAM is preferred for large memory.
3. If a typical static RAM cell requires 6 transistors then corresponding dynamic RAM requires
a) 1 transistor along with capacitance
b) 2 transistors along with resistance
c) 3 transistors along with diode
d) 2 transistors along with capacitance
View Answer
Answer: a
Explanation: The hardware complexity of dynamic RAM is lesser than that of static RAM.
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4. To store the charge as a representation of data, the basic dynamic RAM cell uses
a) resistor
b) capacitor
c) diode
d) transistor
View Answer
Answer: c
Explanation: The basic dynamic RAM cell uses capacitance to store the charge as a
representation of data. This capacitor is manufactured as a diode that is reverse biased so that
the storage capacitance is obtained.
5. The process of refreshing the data in the RAM to reduce the possibility of data loss is known as
a) data cycle
b) regain cycle
c) retain cycle
d) refresh cycle
View Answer
d. None of these
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Answer: d
Explanation: The data storage in RAM which is capacitance (reverse-biased diode) may have a
leakage current that tends to discharge the capacitor giving rise to possibility of data loss. To avoid
this, the data must be refreshed after a fixed time interval regularly.
6. The field in which dynamic RAM is more complicated than static RAM is
a) complexity
b) interfacing circuit
c) execution unit
d) cost
View Answer
Answer: b
Explanation: The refresh mechanism and the additional hardware required makes the interfacing
circuit of dynamic RAM more complicated than that of static RAM.
7. Memory refresh activity is
a) initialised by processor
b) initialised by external bus master
c) initialised by refresh mechanism
d) initialised either by processor or by external bus
View Answer
Answer: c
Explanation: The refresh operation is independent regular activity that is initialised and carried out
by the refresh mechanism.
8. The number of memory chips that are enabled at a time for refresh activity is
a) 2
b) 4
c) 8
d) more than 1
View Answer
Answer: d
Explanation: More than one memory chip can be enabled at a time to refresh activity to reduce
the number of total memory refresh cycles.
9. A timer that derives pulse for refreshing action or time for which a dynamic RAM cell can hold
data charge level practically constant is
a) constant timer
b) data managing timer
c) refresh timer
d) qualitative timer
View Answer
Answer: c
Explanation: Refresh timer derives a pulse for refreshing action after each refresh interval which
can be qualitatively defined as the time for which a dynamic RAM cell can hold data charge level
practically constant.
10. If ‘n’ denotes the number of rows that are to be refreshed in a single refresh interval, ‘td’
denotes the range of time it may take then, refresh time (tr) can be defined as
a) n*td
b) td/n
d. None of these
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c) n/td
d) tdn
View Answer
Answer: b
Explanation: Refresh time is the ratio of time duration taken for refreshing to the number of rows
that are refreshed. Refresh frequency is the reciprocal of refresh time.
1. The device that enables the microprocessor to read data from the external devices is
a) printer
b) joystick
c) display
d) reader
View Answer
Answer: b
Explanation: Since joystick is an input device, it reads data from the external devices.
2. The example of output device is
a) CRT display
b) 7-segment display
c) Printer
d) All of the mentioned
View Answer
Answer: d
Explanation: The output device transfers data from the microprocessor to the external devices.
3. The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read
View Answer
Answer: c
Explanation: The input activity is similar to read operation and the output activity is similar to write
operation.
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4. The operation, IOWR (active low) performs
a) write operation on input data
b) write operation on output data
c) read operation on input data
d) read operation on output data
View Answer
Answer: b
Explanation: IOWR (active low) operation means writing data to an output device and not an input
device.
5. The latch or IC 74LS373 acts as
a) good input port
b) bad input port
c) good output port
d. None of these
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d) bad output port
View Answer
Answer: c
Explanation: If the output port is to source large currents, the port lines must be buffered. So, the
latch is used as it acts as a good output port.
6. While performing read operation, one must take care that much current should not be
a) sourced from data lines
b) sinked from data lines
c) sourced or sinked from data lines
d) sinked from address lines
View Answer
Answer: c
Explanation: More current should not be sourced or sinked from data lines while reading to avoid
loading.
7. To avoid loading during read operation, the device used is
a) latch
b) flipflop
c) buffer
d) tristate buffer
View Answer
Answer: d
Explanation: A tristate buffer is used as an input device to overcome loading.
8. The chip 74LS245 is
a) bidirectional buffer
b) 8-bit input port
c) one that has 8 buffers
d) all of the mentioned
View Answer
Answer: d
Explanation: The chip 74LS245 is a bidirectional buffer that contains 8 buffers and may be used
as an 8-bit input port. But while using as an input device, only one direction is useful.
9. In 74LS245, if DIR is 1, then the direction is from
a) inputs to outputs
b) outputs to inputs
c) source to sink
d) sink to source
View Answer
Answer: a
Explanation: If DIR is 1, then the direction is from A(inputs) to B(outputs).
10. In memory-mapped scheme, the devices are viewed as
a) distinct I/O devices
b) memory locations
c) only input devices
d) only output devices
View Answer
d. None of these
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Answer: b
Explanation: In memory-mapped scheme, the devices are viewed as memory locations and are
addressed likewise.
1. Programmable peripheral input-output port is another name for
a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port
View Answer
Answer: b
Explanation: The parallel input-output port chip 8255 is also known as programmable peripheral
input-output port.
2. Port C of 8255 can function independently as
a) input port
b) output port
c) either input or output ports
d) both input and output ports
View Answer
Answer: c
Explanation: Port C can function independently either as input or as output ports.
3. All the functions of the ports of 8255 are achieved by programming the bits of an internal register
called
a) data bus control
b) read logic control
c) control word register
d) none of the mentioned
View Answer
Answer: c
Explanation: By programming the bits of control word register, the operations of the ports are
specified.
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4. The data bus buffer is controlled by
a) control word register
b) read/write control logic
c) data bus
d) none of the mentioned
View Answer
Answer: b
Explanation: The data bus buffer is controlled by read/write control logic.
5. The input provided by the microprocessor to the read/write control logic is
a) RESET
b) A1
c) WR(ACTIVE LOW)
d) All of the mentioned
View Answer
d. None of these
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Answer: d
Explanation: RD(ACTIVE LOW), WR(ACTIVE LOW), A1, A0, RESET are the inputs provided by
the microprocessor to the read/write control logic of 8255.
6. The device that receives or transmits data upon the execution of input or output instructions by
the microprocessor is
a) control word register
b) read/write control logic
c) 3-state bidirectional buffer
d) none of the mentioned
View Answer
Answer: c
Explanation: 3-state bidirectional buffer is used to receives or transmits data upon the execution
of input or output instructions by the microprocessor.
7. The port that is used for the generation of handshake lines in mode 1 or mode 2 is
a) port A
b) port B
c) port C Lower
d) port C Upper
View Answer
Answer: d
Explanation: Port C upper is used for the generation of handshake lines in mode 1 or mode 2.
8. If A1=0, A0=1 then the input read cycle is performed from
a) port A to data bus
b) port B to data bus
c) port C to data bus
d) CWR to data bus
View Answer
Answer: b
Explanation: If A1=0, A0=1 then the input read cycle is performed from port B to data bus.
9. The function, ‘data bus tristated’ is performed when
a) CS(active low) = 1
b) CS(active low) = 0
c) CS(active low) = 0, RD(active low) = 1, WR(active low) = 1
d) CS(active low) = 1 OR CS(active low) = 0, RD(active low) = 1, WR(active low) = 1
View Answer
Answer: d
Explanation: The data bus is tristated when chip select pin=1 or chip select pin=0 and read and
write signals are high i.e 1.
10. The pin that clears the control word register of 8255 when enabled is
a) CLEAR
b) SET
c) RESET
d) CLK
View Answer
Answer: c
Explanation: If reset pin is enabled then the control word register is cleared.
d. None of these
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1. In the I/O mode, the 8255 ports work as
a) reset pins
b) set pins
c) programmable I/O ports
d) only output ports
View Answer
Answer: c
Explanation: In the I/O mode, the 8255 ports work as programmable I/O ports.
2. In BSR mode, only port C can be used to
a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports
View Answer
Answer: c
Explanation: In BSR (Bit Set-Reset) Mode, port C can be used to set and reset its individual port
bits.
3. The feature of mode 0 is
a) any port can be used as input or output
b) output ports are latched
c) maximum of 4 ports are available
d) all of the mentioned
View Answer
Answer: d
Explanation: In mode 0, any port can be used as input or output and output ports are latched.
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4. The strobed input/output mode is another name of
a) mode 0
b) mode 1
c) mode 2
d) none
View Answer
Answer: b
Explanation: In this mode, the handshaking signals control the input or output action of the
specified port.
5. If the value of the pin STB (Strobe Input) falls to low level, then
a) input port is loaded into input latches
b) input port is loaded into output latches
c) output port is loaded into input latches
d) output port is loaded into output latches
View Answer
Answer: a
Explanation: If the value of the pin STB (Strobe Input) falls to low level, the input port is loaded
into input latches.
d. None of these
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6. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of
a) Control word register
b) CPU
c) Printer
d) Ports
View Answer
Answer: c
Explanation: This signal indicates that the printer is selected.
7. The pulse width of the signal INIT at the receiving terminal must be more than
a) 10 microseconds
b) 20 microseconds
c) 40 microseconds
d) 50 microseconds
View Answer
Answer: d
Explanation: The pulse width of the signal must be more than 50microseconds at the receiving
terminal.
8. The level of the signal ERROR(active low) becomes ‘low’ when the printer is in
a) Paper end state
b) Offline state
c) Error state
d) All of the mentioned
View Answer
Answer: d
Explanation: The level of the signal ERROR(active low) becomes ‘low’ when the printer is in the
Paper end state, Offline state and Error state.
9. The signals that are provided to maintain proper data flow and synchronization between the
data transmitter and receiver are
a) handshaking signals
b) control signals
c) input signals
d) none
View Answer
Answer: a
Explanation: Handshaking signals maintain proper data flow and synchronization.
10. The feature of mode 2 of 8255 is
a) single 8-bit port is available
b) both inputs and outputs are latched
c) port C is used for generating handshake signals
d) all of the mentioned
View Answer
Answer: d
Explanation: In mode 2 of 8255, a single 8-bit port is available i.e group A.
1. The time taken by the ADC from the active edge of SOC(start of conversion) pulse till the active
edge of EOC(end of conversion) signal is called
a) edge time
d. None of these
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b) conversion time
c) conversion delay
d) time delay
View Answer
Answer: c
Explanation: Broadly speaking, the time taken by the converter to calculate the equivalent digital
data output from the moment of the start of conversion is called conversion delay.
2. The popular technique that is used in the integration of ADC chips is
a) successive approximation
b) dual slope integration
c) successive approximation and dual slope integration
d) none
View Answer
Answer: c
Explanation: Successive approximation and dual slope integration are the most popular
techniques that are used in the integrated ADC chips.
3. The procedure of algorithm for interfacing ADC contain
a) ensuring stability of analog input
b) issuing start of conversion pulse to ADC
c) reading digital data output of ADC as equivalent digital output
d) all of the mentioned
View Answer
Answer: d
Explanation: The general algorithm for interfacing ADC contains ensuring the stability of analog
input, issuing start of conversion pulse to ADC, reading end of conversion signal to mark the end
of a conversion process, reading digital data output of ADC as equivalent digital output.
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4. Which is the ADC among the following?
a) AD 7523
b) 74373
c) 74245
d) ICL7109
View Answer
Answer: d
Explanation: AD 7523 is a DAC(Digital to analog converter), 74373 is a latch, 74245 is transceiver
and ICL7109 is an ADC.
5. The conversion delay in a successive approximation of an ADC 0808/0809 is
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 milliseconds
View Answer
Answer: b
Explanation: The conversion delay is 100microseconds which is low as compared to other
converters.
d. None of these
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6. The number of inputs that can be connected at a time to an ADC that is integrated with
successive approximation is
a) 4
b) 2
c) 8
d) 16
View Answer
Answer: c
Explanation: As these converters internally have 3:8 analog multiplexer, at a time 8 different
analog inputs can be connected to the chip.
7. ADC 7109 integrated by Dual slope integration technique is used for
a) low cost option
b) slow practical applications
c) low complexity
d) all of the mentioned
View Answer
Answer: d
Explanation: Compared to other 12-bit ADCs, it is of very low cost and useful for slow practical
applications.
8. Which of the following is not one of the phases of the total conversion cycle?
a) autozero phase
b) conversion phase
c) signal integrate phase
d) disintegrate phase
View Answer
Answer: b
Explanation: Autozero phase, signal integrate phase and disintegrate phase are the three phases
of total conversion cycle.
9. Which of the following phase contain feedback loop in it?
a) autozero phase
b) signal integrate phase
c) disintegrate phase
d) none
View Answer
Answer: a
Explanation: A feedback loop is closed around the system to charge the autozero capacitor to
compensate for the offset voltages in the buffer amplifier, integrator and comparator.
10. In the signal integrate phase, the differential input voltage between IN LO(input low) and IN
HI(input high) pins is integrated by the internal integrator for a fixed period of
a) 256 clock cycles
b) 1024 clock cycles
c) 2048 clock cycles
d) 4096 clock cycles
View Answer
Answer: c
Explanation: The internal integrator needs 2048 clock cycles to integrate voltage difference
between input low and input high.
d. None of these
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1. DAC (Digital to Analog Converter) finds application in
a) digitally controlled gains
b) motor speed controls
c) programmable gain amplifiers
d) all of the mentioned
View Answer
Answer: d
Explanation: DAC is used in digitally controlled gains, motor speed controls and programmable
gain amplifiers.
2. To save the DAC from negative transients the device connected between OUT1 and OUT2 of
AD 7523 is
a) p-n junction diode
b) Zener
c) FET
d) BJT (Bipolar Junction transistor)
View Answer
Answer: b
Explanation: Zener is connected between OUT1 and OUT2 pins of AD7523 to save from negative
transients.
3. An operational amplifier connected to the output of AD 7523 is used
a) to convert current output to output voltage
b) to provide additional driving capability
c) as current-to-voltage converter
d) all of the mentioned
View Answer
Answer: d
Explanation: An operational amplifier is used as a current-to-voltage converter to convert the
current output to output voltage and also provides additional driving capability to the DAC.
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4. The DAC 0800 has a settling time of
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 microseconds
View Answer
Answer: a
Explanation: DAC 0800 has a settling time of 100 milliseconds.
5. The device that is used to obtain an accurate position control of rotating shafts in terms of steps
is
a) DC motor
b) AC motor
c) Stepper motor
d) Servo motor
View Answer
d. None of these
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Answer: c
Explanation: Stepper motor employs rotation of its shaft in terms of steps, rather than continuous
rotation as in case of AC or DC motors.
6. The internal schematic of a typical stepper motor has
a) 1 winding
b) 2 windings
c) 3 windings
d) 4 windings
View Answer
Answer: d
Explanation: The internal schematic of a typical stepper motor has 4 windings.
7. The number of pulses required for one complete rotation of the shaft of the stepper motor is
equal to the
a) number of internal teeth on a rotor
b) number of internal teeth on a stator
c) number of internal teeth on a rotor and stator
d) number of external teeth on a stator
View Answer
Answer: a
Explanation: The number of pulses required for one complete rotation of the shaft of the stepper
motor is equal to the number of internal teeth on its rotor.
8. A simple scheme for rotating the shaft of a stepper motor is called
a) rotating scheme
b) shaft scheme
c) wave scheme
d) none
View Answer
Answer: c
Explanation: In this scheme, the windings are applied with the required voltage pulses, in a cyclic
fashion.
9. The firing angles of thyristors are controlled by
a) pulse generating circuits
b) relaxation oscillators
c) microprocessor
d) all of the mentioned
View Answer
Answer: d
Explanation: In early days, the firing angles were controlled by a pulse generating circuits like
relaxation oscillators and now, they are accurately fired using a microprocessor.
10. The Isolation transformers are generally used for
a) protecting low power circuit
b) isolation
c) protecting low power circuit and isolation
d) none
View Answer
d. None of these
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Answer: c
Explanation: Any switching component of a high power circuit may be sufficient to damage the
microprocessor system. So, to protect the low power circuit isolation transformers are used. They
are also used if isolation is necessary.
1. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: c
Explanation: There are three counters that can be used as either counters or delay generators.
2. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
View Answer
Answer: b
Explanation: The control word register can only be written and cannot be read.
3. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3
View Answer
Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.
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4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low for
a) 1 clockcycle
b) 2 clockcycles
c) 3 clockcycles
d) 4 clockcycles
View Answer
Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If the count N is
reloaded and again the output becomes high and remains so for (N-1) clock pulses.
5. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
View Answer
Answer: c
Explanation: When the count N loaded is even, then for half of the count, the output remains high
d. None of these
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and for the remaining half it remains low. If the count loaded is odd, the first clock pulse decrements
it by 1 resulting in an even count value.
6. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
View Answer
Answer: b
Explanation: SC denotes select counter.
7. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
View Answer
Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.
8. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
View Answer
Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is BCD count.
9. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
View Answer
Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.
10. The control word register contents are used for
a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
View Answer
Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.
d. None of these
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1. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7
View Answer
Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these five, four pins were
alloted fixed vector addresses but the pin INTR was not alloted by vector address, rather an
external device was supposed to hand over the type of the interrupt to the microprocessor.
2. The register that stores all the interrupt requests in it in order to serve them one by one on a
priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
View Answer
Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request Register internally.
3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
View Answer
Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request Register) at the
direction of the Priority Resolver.
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4. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
View Answer
Answer: d
Explanation: The interrupt control logic performs all the operations that are involved within the
interrupts like accepting and managing interrupt acknowledge signals, interrupts.
5. In a cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
View Answer
d. None of these
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Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64 vectored
interrupts can be provided.
6. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be
used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
View Answer
Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a buffer enable to
control buffer transreceivers. If it is not used in buffered mode, then the pin is used as input to
designate whether the chip is used as a master or a slave.
7. Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
View Answer
Answer: d
Explanation: The initialization procedure involves
i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.
8. When non-specific EOI command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
View Answer
Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will automatically reset the
highest ISR.
9. In the application where all the interrupting devices are of equal priority, the mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
View Answer
Answer: a
Explanation: The automatic rotation is used in the applications where all the interrupting devices
are of equal priority.
d. None of these
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1. The registers that store the keyboard and display modes and operations programmed by CPU
are
a) I/O control and data buffers
b) Control and timing registers
c) Return buffers
d) Display address registers
View Answer
Answer: b
Explanation: The control and timing register to store the keyboard and display modes and other
operations programmed by CPU.
2. The sensor RAM acts as 8-byte first-in-first-out RAM in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
View Answer
Answer: c
Explanation: In this mode, each key code of the pressed key is entered in the order of the entry,
and in the meantime, read by the CPU, till the RAM becomes empty.
3. The registers that hold the address of the word currently being written by the CPU from the
display RAM are
a) control and timing register
b) control and timing register and timing control
c) display RAM
d) display address registers
View Answer
Answer: d
Explanation: The display address registers holds the address of the word currently being written
or read by the CPU to or from the display RAM.
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4. When a key is pressed, a debounce logic comes into operation in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
View Answer
Answer: c
Explanation: In scanned keyboard mode with 2 key lockout mode of operation, when a key is
pressed, a debounce logic comes into operation. During the next two scans, other keys are
checked for closure and if no other key is pressed then the first pressed key is identified.
5. The mode that is programmed using “end interrupt/error mode set command” is
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d. None of these
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d) sensor matrix mode
View Answer
Answer: a
Explanation: The scanned keyboard special error mode is programmed using end interrupt/error
mode set command. This mode is valid only under the N-key rollover mode.
6. When a key is pressed, the debounce circuit waits for 2 keyboard scans and then checks
whether the key is still depressed in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
View Answer
Answer: b
Explanation: In this mode, When a key is pressed, the debounce circuit waits for 2 keyboard scans
and then checks whether the key is still depressed. If it is still depressed, the code is entered in
FIFO RAM.
7. The data that is entered from the left side of the display unit is of
a) left entry mode
b) right entry mode
c) left and right entry modes
d) none
View Answer
Answer: a
Explanation: The data that is entered from the left side of the display unit is of left entry mode, as
in a type-writer the first character typed appears at the left-most position, while the subsequent
characters appear successively to the right of the first one.
8. The FIFO status word is used to indicate the error in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
View Answer
Answer: c
Explanation: Overrun error occurs when an already full FIFO has attempted an entry. Underrun
error occurs when an empty FIFO read is attempted.
9. The flag that increments automatically after each read or write operation to the display RAM is
a) IF
b) RF
c) AI
d) WF
View Answer
Answer: c
Explanation: AI refers to auto increment flag.
10. If any change in sensor value is detected at the end of a sensor matrix scan, then the IRQ line
a) goes low
b) goes high
d. None of these
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c) remains unchanged
d) none
View Answer
Answer: b
Explanation: In sensor matrix mode, the IRQ line goes high, if any change in sensor value is
detected at the end of a sensor matrix scan or the sensor RAM has a previous entry to be read by
the CPU.
1. Which of the following is not a mode of data transmission?
a) simplex
b) duplex
c) semi duplex
d) half duplex
View Answer
Answer: c
Explanation: Basically, there are three modes of data transmission. simplex, duplex and half
duplex.
2. If the data is transmitted only in one direction over a single communication channel, then it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
View Answer
Answer: a
Explanation: In simplex mode, the data transmission is unidirectional. For example, a CPU may
transmit data for a CRT display unit in this mode.
3. If the data transmission takes place in either direction, but at a time data may be transmitted
only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
View Answer
Answer: d
Explanation: In half duplex mode, data transmission is bidirectional but not at a time. For example,
Walkie-Talkie.
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4. In 8251A, the pin that controls the rate at which the character is to be transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)
View Answer
Answer: a
Explanation: Transmitter Clock Input (TXC(active low)) is a pin that controls the rate at which the
character is to be transmitted.
d. None of these
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5. TXD(Transmitted Data Output) pin carries serial stream of the transmitted data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned
View Answer
Answer: d
Explanation: Transmitted Data Output pin carries a serial stream of the transmitted data bits along
with other information like start bits, stop bits and parity bits etc.
6. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY(Transmitter ready)
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)
View Answer
Answer: b
Explanation: RXRDY(Receiver ready output) may be used either to interrupt the CPU or polled by
the CPU.
7. The disadvantage of RS-232C is
a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned
View Answer
Answer: d
Explanation: RS232C has been used for long and has a few disadvantages like limited speed of
communication, high-voltage level signaling and big-size communication adapters.
8. The USB supports the signaling rate of
a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned
View Answer
Answer: d
Explanation: The USB standards support the signaling rates. Also, USB signaling is implemented
in a differential in low- and full-speed options.
9. The bit packet that commands the device either to receive data or transmit data in transmission
of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
View Answer
Answer: b
Explanation: The token packet is the second type of packet which commands the device either to
receive data or transmit data.
d. None of these
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10. High speed USB devices neglect
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
View Answer
Answer: c
Explanation: PRE packets are only of importance to low-speed USB devices.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “DMA
Controller 8257”.
1. In direct memory access mode, the data transfer takes place
a) directly
b) indirectly
c) directly and indirectly
d) none of the mentioned
View Answer
Answer: a
Explanation: In direct memory access mode, the data may transfer directly without the interference
from the CPU.
2. In 8257 (DMA), each of the four channels has
a) a pair of two 8-bit registers
b) a pair of two 16-bit registers
c) one 16-bit register
d) one 8-bit register
View Answer
Answer: b
Explanation: The DMA supports four channels, and each of the channels has a pair of two 16-bit
registers, namely DMA address register and a terminal count register.
3. The common register(s) for all the four channels of 8257 is
a) DMA address register
b) Terminal count register
c) Mode set register and status register
d) None of the mentioned
View Answer
Answer: c
Explanation: The two common registers for all the four channels of DMA are mode set register
and status register.
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4. In 8257 register format, the selected channel is disabled after the terminal count condition is
reached when
a) Auto load is set
b) Auto load is reset
c) TC STOP bit is reset
d) TC STOP bit is set
View Answer
d. None of these
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Answer: d
Explanation: If the TC STOP bit is set, the selected channel is disabled after the terminal count
condition is reached, and it further prevents any DMA cycle on the channel.
5. The IOR (active low) input line acts as output in
a) slave mode
b) master mode
c) master and slave mode
d) none of the mentioned
View Answer
Answer: b
Explanation: The IOR (active low) is an active low bidirectional tristate input line, that acts as input
in the slave mode, and acts as output in the master mode. In master mode, this signal is used to
read data from a peripheral during a memory write cycle.
6. The IOW (active low) in its slave mode loads the contents of a data bus to
a) 8-bit mode register
b) upper/lower byte of 16-bit DMA address register
c) terminal count register
d) all of the mentioned
View Answer
Answer: d
Explanation: In its slave mode, the IOW (active low) loads the contents of a data bus to 8-bit mode
register, upper/lower byte of 16-bit DMA address register or terminal count register.
7. The pin that disables all the DMA channels by clearing the mode registers is
a) MARK
b) CLEAR
c) RESET
d) READY
View Answer
Answer: c
Explanation: The RESET pin which is asynchronous input disables all the DMA channels by
clearing the mode registers, and tristate all the control lines.
8. The pin that requests the access of the system bus is
a) HLDA
b) HRQ
c) ADSTB
d) None of the mentioned
View Answer
Answer: b
Explanation: The hold request output requests the access of the system bus.
9. The pin that is used to write data to the addressed memory location, during DMA write operation
is
a) MEMR (active low)
b) AEN
c) MEMW (active low)
d) IOW (active low)
View Answer
d. None of these
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Answer: c
Explanation: The MEMW (active low) is used to write data to the addressed memory location,
during DMA write operation.
10. The pin that strobes the higher byte of the memory address, generated by the DMA controller
into the latches is
a) AEN
b) ADSTB
c) TC
d) None of the mentioned
View Answer
Answer: b
Explanation: The pin ADSTB strobes the higher byte of the memory address, generated by the
DMA controller into the latches.
1. The 8257 is able to accomplish the operation of
a) verifying DMA operation
b) write operation
c) read operation
d) all of the mentioned
View Answer
Answer: d
Explanation: The 8257 can accomplish three types of operations and they are
i) verify DMA operation
ii) write operation
iii) read operation.
2. The bus is available when the DMA controller receives the signal
a) HRQ
b) HLDA
c) DACK
d) All of the mentioned
View Answer
Answer: b
Explanation: If the HLDA signal is received by the DMA controller, it indicates that the bus is
available.
3. To indicate the I/O device that its request for the DMA transfer has been honored by the CPU,
the DMA controller pulls
a) HLDA signal
b) HRQ signal
c) DACK (active low)
d) DACK (active high)
View Answer
Answer: c
Explanation: The DACK (active low) line of the used channel is pulled down by the DMA controller
to indicate the I/O device that its request for the DMA transfer has been honored by the CPU.
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d. None of these
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4. If more than one channel requests service simultaneously, the transfer will occur as
a) multi transfer
b) simultaneous transfer
c) burst transfer
d) none of the mentioned
View Answer
5. The continuous transfer may be interrupted by an external device by pulling down the signal
a) HRQ
b) DACK (active low)
c) DACK (active high)
d) HLDA
View Answer
Answer: d
Explanation: The burst or continuous transfer may be interrupted by an external device by pulling
down the HLDA line.
6. The number of clock cycles required for an 8257 to complete a transfer is
a) 2
b) 4
c) 8
d) none of the mentioned
View Answer
Answer: b
Explanation: The 8257 uses four clock cycles to complete a transfer.
7. In 8257, if each device connected to a channel is assigned to a fixed priority then it is said to be
in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned
View Answer
Answer: b
Explanation: In this scheme, the DRQ3 has the lowest priority followed by DRQ2 and DRQ1. The
DRQ0 has the highest priority.
8. The priority of the channels varies frequently in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned
View Answer
Answer: a
Explanation: In this scheme, the priorities assigned to the channels are not fixed.
9. The register of 8257 that can only be written in is
a) DMA address register
b) Terminal count register
c) Mode set register
d) Status register
View Answer
d. None of these
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Answer: c
Explanation: The selected register may be read or written depending on the instruction executed
by the CPU. But only write operation can be performed on the mode set register.
10. The operation that can be performed on the status register is
a) write operation
b) read operation
c) read and write operations
d) none of the mentioned
View Answer
Answer: b
Explanation: The status register can only be read.
1. The block of 8237 that decodes the various commands given to the 8237 by the CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
View Answer
Answer: b
Explanation: The program control block decodes various commands given to the 8237 by the CPU
before servicing a DMA request.
2. The priority between the DMA channels requesting the services can be resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
View Answer
Answer: c
Explanation: The priority encoder block resolves the priority between the DMA channels
requesting the services.
3. The register that holds the current memory address is
a) current word register
b) current address register
c) base address register
d) command register
View Answer
Answer: b
Explanation: The current address register holds the current memory address. The current address
register is accessed during the DMA transfer.
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4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register
View Answer
d. None of these
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5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated
View Answer
Answer: c
Explanation: When the count becomes zero, the EOP signal is generated. This can be written in
successive bytes by the CPU, in program mode.
6. The current address register is programmed by the CPU as
a) bit-wise
b) byte-wise
c) bit-wise and byte-wise
d) none of the mentioned
View Answer
Answer: b
Explanation: The current address register is byte-wise programmed by the CPU, i.e. lower byte
first and the higher byte later.
7. Which of these register’s contents is used for auto-initialization (internally)?
a) current word register
b) current address register
c) base address register
d) command register
View Answer
Answer: c
Explanation: The contents of base address register cannot be read by the CPU. These contents
are used internally for auto-initialization.
8. The register that maintains an original copy of the respective initial current address register and
current word register is
a) mode register
b) base address register
c) command register
d) mask register
View Answer
Answer: b
Explanation: The base address register maintains an original copy of the current address register
and current word register, before incrementing or decrementing.
9. The register that can be automatically incremented or decremented, after each DMA transfer is
a) mask register
b) mode register
c) command register
d) current address register
View Answer
Answer: d
Explanation: The address is automatically incremented or decremented after each DMA transfer,
and the resulting address value is again stored in the current address register.
d. None of these
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10. Which of the following is a type of DMA transfer?
a) memory read
b) memory write
c) verify transfer
d) all of the mentioned
View Answer
Answer: d
Explanation: Memory read, memory write and verify transfer are the three types of DMA transfer.
1. Each bit in the request register is cleared by
a) under program control
b) generation of TC
c) generation of an external EOP
d) all of the mentioned
View Answer
2. The register that holds the data during memory to memory data transfer is
a) mode register
b) temporary register
c) command register
d) mask register
View Answer
Answer: b
Explanation: The temporary register holds the data during memory to memory data transfers. After
the completion of the transfer operation, the last word transferred remains in the temporary
register, until it is cleared by a reset operation.
3. The register that keeps track of all the DMA channel pending requests and status of their
terminal counts is
a) mask register
b) request register
c) status register
d) count register
View Answer
Answer: c
Explanation: The status register keeps track of all the DMA channel pending requests, and status
of their terminal counts. These are cleared upon reset.
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4. The pin that clears the command, request and temporary registers, and internal first/last flipflop
when it is set is
a) CLEAR
b) SET
c) HLDA
d) RESET
View Answer
Answer: d
Explanation: A high on the reset pin clears the command, status, request and temporary registers,
and also clears the internal first/last flipflop.
d. None of these
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5. The DMA request input pin that has the highest priority is
a) DREQ0
b) DREQ1
c) DREQ2
d) DREQ3
View Answer
Answer: a
Explanation: DREQ0 has the highest priority while DREQ3 has the lowest one. The priorities of
the DREQ lines is programmable.
6. When interface 8237 does not have any valid pending DMA request then it is said to be in
a) active state
b) passive state
c) idle state
d) none of the mentioned
View Answer
Answer: c
Explanation: If 8237 is in idle state, then CPU may program it in this state.
7. To complete a DMA transfer, a memory to memory transfer requires
a) a read from memory cycle
b) a write to memory cycle
c) a read-from and write-to memory cycle
d) none of the mentioned
View Answer
Answer: c
Explanation: A memory to memory transfer is a two cycle operation and requires a read from and
write-to memory cycle, to complete each DMA transfer.
8. In demand transfer mode of 8237, the device stops data transfer when
a) a TC (terminal count) is reached
b) an external EOP (active low) is detected
c) the DREQ signal goes inactive
d) all of the mentioned
View Answer
Answer: d
Explanation: In demand transfer mode, the device continues transfers till a TC is reached or an
external EOP is detected or the DREQ signal goes inactive.
9. The mode of 8237 in which the device transfers only one byte per request is
a) block transfer mode
b) single transfer mode
c) demand transfer mode
d) cascade mode
View Answer
Answer: b
Explanation: In single mode, the device transfers only one byte per request. For each transfer, the
DREQ must be active until the DACK is activated.
10. The transfer of a block of data from one set of memory address to another takes place in
a) block transfer mode
d. None of these
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b) demand transfer mode
c) memory to memory transfer mode
d) cascade mode
View Answer
Answer: c
Explanation: To perform the transfer of a block of data from one set of a memory address to
another one, this transfer mode is used.
11. Which of the following command is used to make all the internal registers of 8237 clear?
a) clear first/last flipflop
b) master clear command
c) clear mask register
d) none of the mentioned
View Answer
Answer: b
Explanation: Using master clear command, all the internal registers of 8237 are cleared, while all
the bits of the mask register are set.
1. The basic principle of floppy disks involve
a) magnetic data reading
b) magnetic data recording
c) magnetic data recording and reading
d) none of the mentioned
View Answer
Answer: c
Explanation: Whatever their physical sizes and storage formats, all the floppies incorporate the
basic principles of magnetic data recording and reading.
2. In floppy disk, the small hole that enables the drive to identify the beginning of a track and its
first sector is
a) inner hole
b) key hole
c) index hole
d) start hole
View Answer
Answer: c
Explanation: The small hole called index hole, enables the drive to identify the beginning of a track
and its first sector.
3. Inside its jacket, the floppy media is rotated at the speed of
a) 200 RPM
b) 300 RPM
c) 150 RPM
d) 50 RPM
View Answer
Answer: b
Explanation: The floppy media is rotated at the speed of 300 RPM (Revolution Per Minute) inside
its jacket.
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d. None of these
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4. The Double Density Double Sided disks on each side are organized with
a) 20 tracks
b) 30 tracks
c) 40 tracks
d) 50 tracks
View Answer
Answer: c
Explanation: The Double Density Double Sided (DDDS) disks are organized with 40 tracks on
each side of the disk.
5. The magnetic recording technique used for storing data onto the disks (floppy disks) is called
a) return to zero
b) non-return to zero
c) return to zero and Non-return to zero
d) none of the mentioned
View Answer
Answer: b
Explanation: In this technique, the magnetic flux on the disk surface never returns to zero, i.e. no
erase operation is carried out.
6. For reading the disks DVD uses
a) blue laser
b) white laser
c) red laser
d) green laser
View Answer
Answer: c
Explanation: A DVD is an optical disk that uses a red laser for reading the disks.
7. For reading the disks, the blue ray disk uses
a) high frequency red laser
b) low frequency red laser
c) high frequency blue laser
d) low frequency blue laser
View Answer
Answer: c
Explanation: The blue ray disk uses a high frequency blue laser with a small wavelength to read
the disk.
8. A blue ray disk can store data upto _________ per layer.
a) 25 KB
b) 25 MB
c) 25 TB
d) 25 GB
View Answer
Answer: d
Explanation: A blue ray disk can store data upto 25 GB per layer and is popularly used for storing
long duration videos like movies.
9. DVDRW is for
a) read-write DVD
d. None of these
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b) rewriteable DVD
c) recordable DVD
d) none of the mentioned
View Answer
Answer: b
Explanation: DVDRW is for rewriteable DVD and DVDR is for recordable DVD.
10. The HDD is also called as
a) hard disk
b) hard drive
c) fixed disk
d) all of the mentioned
View Answer
Answer: d
Explanation: The Hard Disk Drive is also called as a hard disk, hard drive, fixed drive, fixed disk
or fixed disk drive.
1. The memory of a microprocessor serves as
a) storage of individual instructions
b) temporary storage for the data
c) storing common instructions or data for all processors
d) all of the mentioned
View Answer
Answer: d
Explanation: The memory serves the microprocessor in the same way, whether it is a single
microprocessor or a multi microprocessor.
2. In shared bus architecture, the required processor(s) to perform a bus cycle, for fetching data
or instructions is
a) one processor
b) two processors
c) more than two processors
d) none of the mentioned
View Answer
Answer: a
Explanation: In a shared bus architecture, only one processor performs bus cycle to fetch
instructions or data from the memory.
3. In multiport memory configuration, the processor(s) that address the multiport memory is(are)
a) 1
b) 2
c) 3
d) many
View Answer
Answer: b
Explanation: The processors P1 and P2 address a multiport memory, which can be accessed at
a time by both the processors.
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4. The memory space of a processor that is mapped to other processor/processors and vice-versa
is known as
d. None of these
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a) multi microprocessor system
b) memory technique
c) bus window technique
d) mapping technique
View Answer
Answer: c
Explanation: The bus window technique is the correct method of interconnection between the
processors.
5. The disadvantage of the bus window technique is
a) both processors must know about bus window
b) both processors must know the address map
c) loss of effective local memory space
d) all of the mentioned
View Answer
Answer: d
Explanation: The disadvantage of bus window technique is that both processors must know
implicitly about the existence of a bus window, its size and the address map. It also results in loss
of effective local memory space.
6. Bus switches are present in
a) bus window technique
b) crossbar switching
c) linked input/output
d) shared bus
View Answer
Answer: b
Explanation: In crossbar switching type of interconnection topology, several parallel data paths
are possible. Each node of the crossbar represents a bus switch.
7. Which of the following is not a type of configuration that is based on physical interconnections
between the processors?
a) star configuration
b) loop configuration
c) regular topologies
d) incomplete interconnection
View Answer
Answer: d
Explanation: Based on the physical interconnections between the processors, the configurations
are
i) star configuration
ii) loop or ring configuration
iii) complete interconnection
iv) regular topologies
v) irregular topologies.
8. The configuration, in which all the processing elements are connected to a central switching
element, that may be independent processor via dedicated paths is
a) star
b) loop
c) complete
d. None of these
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d) irregular
View Answer
Answer: a
Explanation: The switching element controls the interconnections between the processing
elements.
9. The configuration that is not suitable for a large number of processors is
a) star
b) loop
c) complete
d) regular
View Answer
Answer: c
Explanation: For a large number of processors, the complete interconnection is impractical due to
a large number of interconnection paths.
10. The array processor architecture is an example of
a) star
b) loop
c) complete
d) regular
View Answer
Answer: d
Explanation: In array processor architecture, the processing elements are arranged in a regular
fashion.
1. The interconnection topologies are implemented using _________ as a node.
a) control unit
b) microprocessor
c) processing unit
d) microprocessor or processing unit
View Answer
Answer: d
Explanation: The microprocessors or processing unit is used as a node in interconnection
topologies. They may also work as stand-alone processors or subprocessing units, under the
control of other microprocessors or processing units.
2. The feature of the multi-microprocessor architecture is
a) task dependent
b) single bus provider for many processors
c) design is for a specific task
d) all of the mentioned
View Answer
Answer: d
Explanation: The main feature of multi-microprocessor is that it is task dependent. If it is designed
for a specific task, then it may not be useful for other tasks.
3. The main objective in building the multi-microprocessor is
a) greater throughput
b) enhanced fault tolerance
c) greater throughput and enhanced fault tolerance
d. None of these
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d) none of the mentioned
View Answer
Answer: c
Explanation: Greater throughput and enhanced fault tolerance are the main objectives of the multi-
microprocessor system. These systems incorporate a multiplicity of hardware and software, for
the purpose.
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4. An interface between the user or an application program, and the system resources are
a) microprocessor
b) microcontroller
c) multi-microprocessor
d) operating system
View Answer
Answer: d
Explanation: The operating system acts as an interface, and is an important program that resides
in the computer memory.
5. An operating system provides
a) hardware and software resource management
b) input/output management
c) memory management
d) all of the mentioned
View Answer
Answer: d
Explanation: An operating system provides a means of hardware and software resource
management including input/output and memory management.
6. Distributed systems are designed to run
a) serial process
b) parallel process
c) serial and parallel process
d) none of the mentioned
View Answer
Answer: d
Explanation: Distributed systems are designed to run a parallel process. It is essential that a proper
environment exists for concurrent processes to communicate and cooperate, in order to complete
the allotted task.
7. A distributed operating system must provide a mechanism for
a) intraprocessor communication
b) intraprocess and intraprocessor communication
c) interprocess and interprocessor communication
d) interprocessor communication
View Answer
Answer: c
Explanation: A distributed operating system must provide a mechanism for interprocess and
interprocessor communication.
8. A multiprocessor operating system should perform
a) a mechanism to split a task into concurrent subtasks
d. None of these
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b) optimize the system performance
c) handling structural or architectural changes
d) all of the mentioned
View Answer
Answer: d
Explanation: A multiprocessor operating system should have a mechanism to split a task, optimise
system performance, and should handle structural changes.
9. An operating system must possess
a) process-processor allocation strategies
b) mechanism to collect results of subtasks
c) software to improve overall performance
d) all of the mentioned
View Answer
Answer: d
Explanation: An operating system must have process-processor allocation strategies, a
mechanism to collect results of subtasks and software to improve overall performance.
10. A multiprocessor operating system must take care of
a) authorized data access and data protection
b) unauthorized data access and data protection
c) authorized data access
d) data protection
View Answer
Answer: b
Explanation: A multiprocessor operating system must take care of unauthorized data access and
data protection.
1. The unit that executes all the numeric processor instructions in 8087 is
a) Control unit
b) ALU
c) Numeric extension unit
d) None of the mentioned
View Answer
Answer: c
Explanation: The 8087 is divided into two sections namely control unit and numeric extension unit
in which the numeric extension unit executes all the numeric processor instructions.
2. The unit that receives and decodes the instructions in 8087 is
a) Control unit
b) ALU
c) Numeric extension unit
d) None of the mentioned
View Answer
Answer: a
Explanation: The control unit receives, decodes the instructions, and executes the 8087 control
instructions.
3. The control unit functions in
a) establishing communication between CPU and memory
d. None of these
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b) coordinating the internal coprocessor execution
c) reads and writes memory operands
d) all of the mentioned
View Answer
Answer: d
Explanation: The control unit is used for establishing communication between CPU and memory
and coordinating the internal coprocessor execution.
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4. When the numeric extension unit (NEU) begins its execution, then the signal that is active is
a) BUSY (active high)
b) BUSY (active low)
c) READY (active low)
d) RESET (active high)
View Answer
Answer: a
Explanation: When NEU begins its execution, the BUSY signal is pulled up. Also, this output signal
when high, indicates to the CPU that it is busy with the execution of an allotted instruction.
5. The register that allows the register programmer to select the required processing options is
a) significant
b) exponent
c) control word register
d) none of the mentioned
View Answer
Answer: c
Explanation: The control word register allows the register programmer to select the required
processing options out of available ones. It is used to control the operation of 8087.
6. Invalid operation is the exception generated due to
a) stack overflow
b) stack underflow
c) indeterminate form as result
d) all of the mentioned
View Answer
Answer: d
Explanation: Invalid operation is generated due to stack overflow, stack underflow, indeterminate
form as result, or non-number (NAN) as operand.
7. The exception generated for a too big result to fit in the format is
a) invalid operation
b) overflow
c) denormalized operand
d) result overflow
View Answer
Answer: b
Explanation: A too big result to fit in the format generates this exception. The condition code bits
indicate that the result is prohibitively large.
8. If the result is infinity, then the exception generated is
a) overflow
d. None of these
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b) invalid operation
c) denormalized operand
d) zero divide
View Answer
Answer: d
Explanation: If any non-zero finite operand is divided by zero, the zero divide exception is
generated. The resulting condition code bits indicate that the result is infinity, even if the exception
is masked.
9. To operate 8087 in maximum mode, the pin MN/MX (active low) is
a) connected to Vcc or power supply
b) connected to ground
c) left unconnected
d) none of the mentioned
View Answer
Answer: b
Explanation: The 8087 can operate in a maximum mode, only when the MN/MX (active low) pin
of the CPU is grounded. In maximum mode, all the control signals are derived using a sequence
chip known as a bus controller.
10. If the result is rounded according to the rounding control bits, then the exception generated is
a) denormalized operand
b) underflow
c) inexact result
d) invalid operation
View Answer
Answer: c
Explanation: If it is impossible to fit the actual result in the specified format, the result is rounded
according to the rounding control bits, and an exception is generated. This sets the precision
exception flag.
11. The instruction that stores a copy of top of the stack into the memory, and pops the top of the
stack is
a) FST
b) FSTP
c) FIST
d) FLD
View Answer
Answer: b
Explanation: FSTP (store floating point number and pop) stores a copy of top of the stack into
memory or any coprocessor register, and then pops the top of the stack.
12. The instruction that multiplies the content of the stack top by 2n is
a) FMUL
b) FPREM
c) FSCAL
d) FCSH
View Answer
Answer: c
Explanation: FSCAL instruction multiplies the content of the stack top by 2n, where n is an integral
part of stack and stores the result in stack.
d. None of these
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13. If the opcode bit is D=1, then the source and destination operands are
a) incremented
b) decremented
c) cleared
d) interchanged
View Answer
Answer: d
Explanation: If D=1, then it interchanges the source and destination operands.
1. Which of the following is not a data transfer instruction?
a) floating point data transfer
b) integer data transfer
c) arithmetic instruction
d) bcd data transfer
View Answer
Answer: c
Explanation: The data transfer instructions are grouped into floating point data transfer, integer
data transfer and BCD data transfer.
2. The instruction that performs real or integer multiplication of the specified operand with stack
top is
a) AMUL
b) IMUL
c) RMUL
d) FMUL
View Answer
Answer: d
Explanation: The FMUL instruction performs real or integer multiplication of the specified operand
with stack top. The specified operand may be a register or a memory location.
3. When the instruction, FDIV is performed, the destination is
a) memory
b) stack top
c) register
d) stack bottom
View Answer
Answer: b
Explanation: If the destination is not specified, the ST(Stack Top) is the destination and source
must be a memory operand of short real or long real type.
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4. When the instruction, FPREM, is performed, the data stored on to the stack top is
a) dividend
b) divisor
c) quotient
d) remainder
View Answer
d. None of these
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Answer: d
Explanation: The instruction divides the stack top (ST) by ST(1), and then stores the remainder to
the stack top (ST).
5. If ‘x’ is the value stored at the top of the stack, then the instruction F2XMI calculates the
expression
a) 2x
b) 2x+1
c) 2x-1
d) log(2x)
View Answer
Answer: c
Explanation: The instruction F2XMI calculates the expression, 2x-1, where the value ‘x’ is stored
at the top of the stack. The result is stored back at the top of the stack.
6. The content of the stack is compared with zero to check whether the content is zero, using the
instruction
a) FCOM
b) FIST
c) FCOMP
d) FXAM
View Answer
Answer: b
Explanation: The instruction FIST tests if the contents of the stack top is zero, and the condition
code flags are accordingly modified.
7. The instruction that loads log 10 (to the base 2) to stack top is
a) FLDPI
b) FLDLG2
c) FLD2T
d) FLDLN2
View Answer
Answer: c
Explanation: The instruction FLD2T loads the specified constant, log 10 (to the base 2) to the top
of the stack.
8. The instructions that are used to program the numeric processor or to handle the internal
housekeeping functions are
a) transcendental operations
b) comparison instructions
c) constant operations
d) coprocessor control instructions
View Answer
Answer: d
Explanation: The coprocessor control instructions are used either to program the numeric
processor or to handle the internal housekeeping functions like exception handling, flags
manipulations, and processor environment maintenance.
9. When the instruction FINIT performs its function, then the TAG status is
a) set
b) empty
d. None of these
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c) reset
d) zero
View Answer
Answer: b
Explanation: This instruction performs the same function as the hardware reset. The control word
is set to 03FF, and the TAG status is set to empty.
10. The instruction that enables the interrupt structure and response mechanism is
a) FINIT
b) FDISI
c) FENI
d) FLDCW
View Answer
Answer: c
Explanation: The instruction FENI enables the interrupt structure and response mechanism of
8087.
11. The instruction that is used to store the environment of the coprocessor to a destination
memory location is
a) FINCSTP
b) FLDENV
c) FFREE
d) FSTENV
View Answer
Answer: d
Explanation: The instruction FSTENV is used to store the environment of the coprocessor to a
destination memory location, specified in the instruction using any of the 8086 addressing modes.
12. The instruction that is the NOP instruction of the coprocessor is
a) CNOP
b) FNOP
c) SNOP
d) PNOP
View Answer
Answer: b
Explanation: The FNOP is a NOP instruction of the coprocessor. No internal status or control flag
bits change.
1. The 8089 shares the system bus and memory with the host CPU in
a) tightly coupled configuration
b) loosely coupled configuration
c) tightly and loosely coupled configurations
d) none of the mentioned
View Answer
Answer: a
Explanation: In a tightly coupled configuration, the 8089 shares the system bus and memory with
the host CPU using its RQ (active low) or GT (active low) pins.
2. The 8089 communicates with the host CPU using bus arbiter and controller in
a) tightly coupled configuration
d. None of these
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b) loosely coupled configuration
c) tightly and loosely coupled configurations
d) none of the mentioned
View Answer
Answer: b
Explanation: In a loosely coupled configuration, the 8089 has its own local bus and communicates
with the host CPU using bus arbiter and controller.
3. The number of address lines used by the I/O processor in 8089 is
a) 20
b) 12
c) 16
d) 8
View Answer
Answer: c
Explanation: The 8089 I/O processor uses only 16 address lines, and thus it can address only
64KB of IO space.
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4. The IO device that can be interfaced with 8089 is
a) 16-bit IO
b) 8-bit IO
c) 64-bit IO
d) 16-bit and 8-bit IO
View Answer
Answer: d
Explanation: The 8089 handled IO devices need not have the same data bus width as that of
8089. This enables even 8-bit IO devices to be interfaced easily with 8089.
5. In the 8089 architecture, the address of memory table for channel-2 is calculated by
a) adding 16 to the contents of CCP
b) adding 8 to the contents of CCP
c) adding memory table address of channel-1
d) none of the mentioned
View Answer
Answer: b
Explanation: The address of the memory table for channel-2 is calculated by adding 8 to the
contents of CCP or by adding memory table address for channel-1 to the contents of CCP.
6. Which of the following is not a general purpose register of 8089?
a) GA
b) BC
c) CX
d) MC
View Answer
Answer: c
Explanation: The registers GA, GB, GC, BC, IX and MC can be used as general purpose registers.
7. The registers that are used as source and destination pointers during DMA operations are
a) GB, GC
b) GC, BC
d. None of these
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c) GC, GA
d) GA, GB
View Answer
Answer: d
Explanation: GA register is used as source and GB as destination pointers during DMA operations.
8. The pin that is used for data transfer control and operation termination signals is
a) SINTR
b) EXT
c) DRQ and EXT
d) RQ (active low) or GT (active low)
View Answer
Answer: c
Explanation: The DRQ and EXT are used for data transfer control and operation termination
signals during DMA operations.
9. The pin that is used to inform the CPU that the previous operation is completed is
a) RQ (active low)
b) GT (active low)
c) DRQ
d) SINTR
View Answer
Answer: d
Explanation: The SINTR pins are used by the channels either to inform the CPU that the previous
operation is over or to ask for its attention or interference if required, before the completion of the
task.
10. The current channel status of program status word contains
a) source and destination address widths
b) bus load limit
c) interrupt control and servicing
d) all of the mentioned
View Answer
Answer: d
Explanation: The program status word contains the current channel status, which contains source
and destination address widths, channel activity, interrupt control and servicing, bus load limit and
priority information.
1. Which of the following is an incorporated function to resolve interprocessor communication
problems?
a) bus allotment and control
b) bus arbitration
c) priority resolving
d) all of the mentioned
View Answer
Answer: d
Explanation: To resolve the various bus contention and interprocessor communication problems,
different hardware strategies and algorithms are worked out. These incorporated functions like
bus allotment and control, bus arbitration and priority resolving into them.
d. None of these
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2. The device that deals with the bus access control functions and bus handshake activities is
a) bus allotment controller
b) bus arbiter
c) priority resolver
d) none of the mentioned
View Answer
Answer: b
Explanation: The bus arbiter or 8289 takes care of bus access control functions and bus
handshake activities.
3. The clock generator delays the READY signal until the signal _________ goes low
a) DEN (active high)
b) DEN (active low)
c) AEN (active low)
d) AEN (active high)
View Answer
Answer: c
Explanation: If AEN (active low) is high, the clock generator delays the READY signal till the AEN
(active low) goes low.
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4. The bus controller relinquishes the bus if
a) READY (active low)
b) LOCK (active high)
c) CBRQ (active low)
d) BPRO (active high)
View Answer
Answer: b
Explanation: The bus controller does not relinquish (release its control on) the bus, till the LOCK
(active low) input is low.
5. The signals that are used by the bus arbitration in the independent request method is
a) BREQ (active low)
b) BPRN (active low)
c) CBRQ (active low)
d) All of the mentioned
View Answer
Answer: d
Explanation: The four active low signals, bus request (BREQ), bus priority in (BPRN), common
bus request (CBRQ) and bus priority out (BPRO) are used for bus arbitration.
6. The signal that is used to drive a priority resolving network that actually accepts the bus request
inputs is
a) BREQ (active low)
b) BPRN (active low)
c) CBRQ (active low)
d) BPRO (active low)
View Answer
Answer: a
Explanation: The BREQ (active low) is used to drive a priority resolving network that actually
d. None of these
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accepts the bus request inputs from all the masters and derives the priority outputs which further
drive the BPRN (active low) inputs of all the masters.
7. Which of the following is the simplest and cheapest method of bus arbitration?
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned
View Answer
Answer: a
Explanation: The daisy chaining method is the simplest one, as it has less hardware complexity.
8. The method of bus arbitration that does not contain priority resolving network in it is
a) daisy chaining
b) independent request
c) polling
d) none
View Answer
Answer: a
Explanation: The daisy chaining method does not contain any priority resolving network, rather
the priorities of all the devices are essentially assumed to be in sequence.
9. Which of the following is the fastest method of bus arbitration?
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned
View Answer
Answer: b
Explanation: The independent request scheme is quite fast because each of the masters can
independently communicate with the controller.
10. A set of address lines is driven by the controller in
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned
View Answer
Answer: c
Explanation: In a polling scheme, a set of address lines is driven by the controller to address each
of the masters in sequence.
1. The processors used in the multi-microprocessor are
a) coprocessors
b) independent processors
c) coprocessors or independent processors
d) none of the mentioned
View Answer
d. None of these
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Answer: c
Explanation: The processors used in the multi-microprocessor are either coprocessors or
independent processors.
2. The processor that executes the instructions fetched for it by the host processor is
a) microprocessor
b) coprocessor
c) independent processor
d) coprocessor and independent processor
View Answer
Answer: b
Explanation: The coprocessor executes the instructions fetched for it by the host processor.
3. The processor that asks for bus access or may itself fetch the instructions and execute them is
a) microprocessor
b) coprocessor
c) independent processor
d) coprocessor and independent processor
View Answer
Answer: c
Explanation: The independent processor may ask for bus access, may fetch the instructions itself,
and execute them independently.
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4. In tightly coupled systems, the microprocessors share
a) common clock
b) bus control logic
c) common clock and bus control logic
d) none of the mentioned
View Answer
Answer: c
Explanation: The microprocessors share a common clock and bus control logic, in a tightly coupled
system.
5. Communication between processors using a common system bus and common memory takes
place in
a) loosely coupled system
b) tightly coupled system
c) tightly and loosely coupled system
d) none of the mentioned
View Answer
Answer: b
Explanation: In tightly coupled systems, the two processors may communicate using a common
system bus or common memory.
6. The bus arbitration is handled by an external circuit in
a) loosely coupled system
b) tightly coupled system
c) tightly and loosely coupled system
d) none of the mentioned
View Answer
d. None of these
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Answer: a
Explanation: In a loosely coupled multiprocessor system, each CPU may have its own bus control
logic. The bus arbitration is handled by an external circuit, common to all the processors.
7. The loosely coupled system has an advantage of
a) more number of CPUs can be added
b) system structure is modular
c) more fault-tolerant and suitable for parallel applications
d) all of the mentioned
View Answer
Answer: d
Explanation: The loosely coupled system is advantageous than the tightly coupled system as it
has advantages of more number of CPUs can be added to improve the system performance. A
fault in a single module does not lead to a complete system breakdown.
8. In a tightly coupled system, when a processor is using the bus then the local bus of other
processors is in
a) hold state
b) high impedance state
c) halt state
d) low impedance state
View Answer
Answer: b
Explanation: When a processor is using the bus then the other processors maintain their local
buses in high impedance state.
9. The disadvantage of the loosely coupled system is
a) complex due to additional hardware
b) less portable
c) more expensive
d) all of the mentioned
View Answer
Answer: d
Explanation: The loosely coupled systems are more complicated due to the required additional
communication hardware. They are less portable and more expensive due to additional hardware.
10. To indicate the completion of task allocated in a closely (tightly) coupled system, the
microprocessor uses
a) status bit in memory
b) interrupts the host
c) status bit in memory or interrupts the host
d) clock pulse
View Answer
Answer: c
Explanation: The microprocessor in a closely coupled system either uses a status bit in memory
or interrupts the host to inform it about the completion of task allotted to it
1. The files that reside in the current drive and directory of the hard disk is
a) OBJ files
b) EXE files
d. None of these
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c) SRC files
d) DEST files
View Answer
Answer: b
Explanation: The files that reside in the current drive and directory of the hard disk is EXE files.
2. The master processor stores the result buffers on to the hard disk with the filename as
a) .EXE file
b) .OBJ file
c) .EXE file with extension .RES
d) .OBJ file with extension .RES
View Answer
Answer: c
Explanation: The master processor stores the result buffers on to the hard disk with the filename
as .EXE file with extension .RES.
3. The 8288 bus controller chip derives the signals
a) ALE
b) DEN
c) DT/R(active low)
d) All of the mentioned
View Answer
Answer: d
Explanation: The latches are enabled by ALE signal and data will be enabled by DEN signal. The
ALE, DEN and DT/R(active low) signals are derived by a separate 8288 bus controller chip.
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4. The EXE files should not exceed the size of
a) 30 KB
b) 50 KB
c) 60 KB
d) 40 KB
View Answer
Answer: c
Explanation: The EXE files should not be more than 60 KB size.
5. A part of memory that can be addressed by more than one processor for communication is
known as
a) memory module
b) bus window
c) ram
d) memory management unit
View Answer
Answer: b
Explanation: There are two slave processors and thus there are two bus windows.
6. When a subprocessor wants to communicate with the bus window, it informs the main processor
to
a) enable control buffer
b) storage buffer
c) disable tristate buffer
d. None of these
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d) translation look aside buffer
View Answer
Answer: c
Explanation: An 8255 IO card is used to control the tristate buffers that provide isolation. When a
subprocessor wants to communicate with the bus window, it informs the main processor to disable
tristate buffer.
7. When the subprocessor completes its execution, then the status on the status lines shows
a) hold status
b) halt status
c) high status
d) low status
View Answer
Answer: b
Explanation: When the subprocessor completes its execution, then the status on the status lines
shows halt status.
8. For MEMR(active low) and MEMWR(active low) operations the mode of isolation buffer should
respectively be in
a) receiver mode, receiver mode
b) transmit mode, receiver mode
c) receiver mode, transmit mode
d) transmit mode, transmit mode
View Answer
Answer: c
Explanation: During MEMR(active low) the data flow from memory to CPU so isolation buffer
should be in receiver mode and data flows from CPU to memory during MEMWR(active low)
operation and so buffer should be in transmit mode.
9. If the DIR pin of the isolation chip is high, then it enters into
a) receiver mode
b) virtual access mode
c) transmit or receive mode
d) transmit mode
View Answer
Answer: d
Explanation: If the DIR pin of the isolation chip is high, then it enters into transmit mode and if it is
0 then the isolation chip enters into receiver mode.
10. The complete software system is divided into
a) main program
b) Interrupt routine IRT2 for first subprocessing the unit
c) Interrupt routine IRT3 for first subprocessing the unit
d) all of the mentioned
View Answer
Answer: d
Explanation: System software of the complete system consists of three parts. the first part main
control program controls the total operation of the system, and the remaining two parts are the
small local initialization programs for each of the subprocessors.
d. None of these
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1. The 80286 is able to address the physical memory of
a) 8 MB
b) 16 MB
c) 24 MB
d) 64 MB
View Answer
Answer: b
Explanation: The 80286 with its 24-bit address bus is able to address 16 Mbytes of physical
memory.
2. The 80286 is able to operate with the clock frequency of
a) 12.5 MHz
b) 10 MHz
c) 8 MHz
d) all of the mentioned
View Answer
Answer: d
Explanation: Various versions of 80286 are available that run on 12.5 MHz, 10 MHz and 8 MHz
clock frequencies.
3. The management of the memory system required to ensure the smooth execution of the running
process is done by
a) control unit
b) memory
c) memory management unit
d) bus interface unit
View Answer
Answer: c
Explanation: The memory management which is an important task of the operating system is now
supported by a hardware unit called a memory management unit.
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4. The fetching of the program from secondary memory to place it in physical memory, during the
execution of CPU is called
a) mapping
b) swapping in
c) swapping out
d) pipelining
View Answer
Answer: b
Explanation: Whenever the portion of a program is required for execution by the CPU, it is fetched
from the secondary memory and placed in the physical memory. This is called swapping in of the
program.
5. The process of making the physical memory free by storing the portion of program and partial
results in the secondary storage called
a) mapping
b) swapping in
c) swapping out
d. None of these
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d) pipelining
View Answer
Answer: c
Explanation: In swapping out, a portion of the program or important partial results required for
further execution, may be saved back on secondary storage to make the physical memory free,
for further execution of another required portion of the program.
6. The memory that is considered as a large logical memory space, that is not available physically
is
a) logical memory
b) auxiliary memory
c) imaginary memory
d) virtual memory
View Answer
Answer: d
Explanation: To the user, there exists a very large logical memory space, which is actually not
available called virtual memory. This does not exist physically in a system. It is however, possible
to map a large virtual memory space onto the real physical memory.
7. Memory management deals with
a) data protection
b) unauthorized access prevention
c) segmented memory
d) all of the mentioned
View Answer
Answer: d
Explanation: The important aspects of memory management are data protection, unauthorized
access prevention, and segmented memory.
8. The memory management and protection mechanisms are disabled when the 80286 is
operated in
a) normal mode
b) real address mode
c) virtual address mode
d) all of the mentioned
View Answer
Answer: b
Explanation: In real address mode of 80286, all the memory management and protection
mechanisms are disabled.
9. The memory management and protection mechanisms are enabled with advanced instruction
set when 80286 is operated in
a) normal mode
b) real address mode
c) virtual address mode
d) all of the mentioned
View Answer
Answer: c
Explanation: In virtual address mode, 80286 works with all of its memory management and
protection capabilities, with the advanced instruction set.
d. None of these
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10. The 80286 is an upward object code compatible with 8086 or 8088 when operated in
a) normal mode
b) real address mode
c) virtual address mode
d) real and virtual address mode
View Answer
Answer: d
Explanation: The 80286 is operated in two modes, namely real address mode and virtual address
mode. In both the modes, the 80286 is compatible with 8086/8088.
1. The CPU of 80286 contains
a) 16-bit general purpose registers
b) 16-bit segment registers
c) status and control register
d) all of the mentioned
View Answer
Answer: d
Explanation: The CPU of 80286 contains the same set of registers as in 8086.
2. The bits that are modified according to the result of the execution of logical and arithmetic
instructions are called
a) byte addressable bit
b) control flag bits
c) status flag bit
d) none of the mentioned
View Answer
Answer: c
Explanation: The flag register bits, D0, D2, D4, D6, D7 and D11 are modified according to the
result of the execution of logical and arithmetic instructions. These are called as status flag bits.
3. The flags that are used for controlling machine operation are called
a) status flags
b) control flags
c) machine controlled flags
d) all of the mentioned
View Answer
Answer: b
Explanation: The flags such as trap flag (TF) and Interrupt flag (IF) bits are used for controlling the
machine operation, and thus they are called control flags.
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4. The additional field that is available in 80286 is
a) I/O Privilege field
b) nested task flag
c) protection enable
d) all of the mentioned
View Answer
Answer: d
Explanation: The additional fields available in 80286 flag register are, I/O Privilege field, nested
task flag, protection enable, and monitor processor extension.
d. None of these
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5. Which of the block is not considered as a block of an architecture of 80286?
a) address unit
b) bus unit
c) instruction unit
d) control unit
View Answer
Answer: d
Explanation: The CPU may be viewed to contain four functional parts and they are
i) Address Unit
ii) Bus Unit
iii) Instruction Unit
iv) Execution Unit.
6. The unit that is responsible for calculating the address of instructions, and data that the CPU
wants to access is
a) bus unit
b) address unit
c) instruction unit
d) control unit
View Answer
Answer: b
Explanation: The address unit is responsible for calculating the address of instructions, and data
that the CPU wants to access. Also, the address lines derived by this unit may be used to address
different peripherals.
7. The process of fetching the instructions in advance, and storing in the queue is called
a) mapping
b) swapping
c) instruction pipelining
d) storing
View Answer
Answer: c
Explanation: The instructions are fetched in advance and stored in a queue to enable faster
execution of the instructions. This concept is known as instruction pipelining.
8. The CPU must flush out the prefetched instructions immediately following the branch instruction
in
a) conditional branch
b) unconditional branch
c) conditional and unconditional branches
d) none of the mentioned
View Answer
Answer: b
Explanation: In case of unconditional branch, the CPU will have to flush out the prefetched
instructions, immediately following the branch instruction.
9. The device that interfaces and control the internal data bus with the system bus is
a) data interface
b) controller interface
c) data and control interface
d. None of these
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d) data transreceiver
View Answer
Answer: d
Explanation: The data transreceivers interface and control the internal data bus with the system
bus.
10. The register bank of Execution Unit of 80286 is used as
a) for storing data
b) scratch pad
c) special purpose registers
d) all of the mentioned
View Answer
Answer: d
Explanation: The execution unit contains the register bank, used for storing the data as scratch
pad, or used as special purpose registers.
11. Which of the following is not an interrupt generated by 80286?
a) software interrupts
b) hardware or external interrupts
c) INT instruction
d) none of the mentioned
View Answer
Answer: d
Explanation: The interrupts generated by 80286 may be divided into 3 categories as external or
hardware interrupts, INT instruction or software interrupts and interrupts generated by exceptions.
12. For which of the following instruction does the return address point to instruction causing an
exception?
a) divide error exception
b) bound range exceeded exception
c) invalid opcode exception
d) all of the mentioned
View Answer
Answer: d
Explanation: For the instructions, divide error, bound range exceeded and invalid opcode
exceptions, the return address points to the instruction causing exception.
13. The instruction that comes into action, if the trap flag is set is
a) maskable interrupt
b) non-maskable interrupt
c) single step interrupt
d) breakpoint interrupt
View Answer
Answer: c
Explanation: Single step interrupt is an internal interrupt that comes into action if the trap flag (TF)
is set.
14. The interrupt that has the highest priority among the following is
a) Single step
b) NMI (non-maskable interrupt)
c) INTR
d. None of these
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d) Instruction exception
View Answer
Answer: d
Explanation: The instruction exception has the highest priority followed by single step, NMI and
INTR instrution.
15. The interrupt that has the lowest priority among the following is
a) Processor extension segment overrun
b) INTR
c) INT instruction
d) NMI
View Answer
Answer: c
Explanation: The INT instruction has the lowest priority. The order of priority of interrupts from high
to low is
1) instruction exception
2) single step
3) NMI
4) processor extension segment overrun
5) INTR
6) INT instruction.
1. The 80286 is available in the package as
a) 68-pin PLCC (plastic leaded chip carrier)
b) 68-pin LCC (lead less chip carrier)
c) 68-pin PGA (pin grid array)
d) all of the mentioned
View Answer
Answer: d
Explanation: The 80286 is available in 68-pin PLCC (plastic leaded chip carrier), 68-pin LCC (lead
less chip carrier) and 68-pin PGA (pin grid array) packages.
2. The clock frequency applied at the CLK pin is internally divided by
a) 2
b) 4
c) 8
d) 1
View Answer
Answer: a
Explanation: The clock frequency is divided by two internally, and is used for deriving fundamental
timings for basic operations of the circuit.
3. The 8 address lines, A23-A16 of 80286 are zero during
a) memory transfer
b) address transfer
c) memory to processor transfer
d) I/O transfer
View Answer
Answer: d
Explanation: The address lines, A23-A16 are zero during I/O transfers.
d. None of these
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4. The signals S1 (active low), S2 (active low) are
a) output signals
b) indicate initiation of bus cycle
c) define type of bus cycle with M/IO (active low)
d) all of the mentioned
View Answer
Answer: d
Explanation: The signals S1 (active low), S2 (active low) are active low status output signals, which
indicate initiation of a bus cycle, and with M/IO (active low) and COD/INTA (active low), they define
the type of the bus cycle.
5. If M/IO (active low) signal is ‘0’ then it indicates
a) I/O cycle
b) Memory cycle
c) I/O cycle or INTA cycle
d) I/O cycle or HALT cycle
View Answer
Answer: c
Explanation: If M/IO (active low) signal is ‘0’ then it indicates that an I/O cycle or INTA cycle is in
the process, and if it is ‘1’, it indicates that a memory or a HALT cycle is in progress.
6. The LOCK (active low) is activated automatically by hardware using
a) XCHG signal
b) Interrupt acknowledge
c) Descriptor table access
d) All of the mentioned
View Answer
Answer: d
Explanation: The lock pin is used to prevent the other masters from gaining the control of the bus,
for the current and the following bus cycles. This pin is activated by a “LOCK” instruction prefix, or
automatically by hardware during XCHG, interrupt acknowledge or descriptor table access.
7. The pin that is used to insert wait states in a bus cycle is
a) WAIT
b) BHE (active low)
c) READY (active low)
d) WAIT(active low)
View Answer
Answer: c
Explanation: The active low READY pin is used to insert wait states in a bus cycle, for interfacing
low speed peripherals. This signal is neglected during HLDA cycle.
8. The minimum number of clock cycles required in an input pulse width of the RESET pin is
a) 4
b) 2
c) 8
d) 16
View Answer
d. None of these
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Answer: d
Explanation: The active high RESET input clears the internal logic of 80286, and re-initializes it.
The reset input pulse width should be at least 16 clock cycles.
9. To filter the output, a 0.047microfarads, 12V capacitor is connected between the pins
a) CAP and ground
b) Output pin and ground
c) CAP and Vcc
d) NMI and ground
View Answer
Answer: a
Explanation: A 0.047microfarads, 12V capacitor is connected between the CAP pin and ground,
to filter the output of the internal substrate bias generator.
10. The signal that causes the 80286 to perform the processor extension interrupt while executing
the WAIT and ESC instructions are
a) BUSY (active low)
b) PEACK (active low)
c) PEREQ
d) ERROR (active low)
View Answer
Answer: d
Explanation: An active ERROR (active low) signal causes the 80286 to perform the processor
extension interrupt while executing the WAIT and ESC instructions.
1. The 80286 CPU acts just like that of 8086 when operated in
a) real addressing mode
b) protected virtual address mode
c) real and protected virtual address modes
d) none of the mentioned
View Answer
Answer: a
Explanation: In the real addressing mode of operation of 80286, it just acts as a fast 8086.
2. In real addressing mode, the 80286 addresses a physical memory of
a) 16 MB
b) 8 MB
c) 2 MB
d) 1 MB
View Answer
Answer: d
Explanation: In real addressing mode, the 80286 addresses a physical memory of 1 Mbytes using
A0-A19. The lines A20-A23 are not used by the internal circuit of 80286 in this mode.
3. In real addressing mode, the 80286 operates at a speed
a) faster than that of 8086
b) half of that of 8086
c) slower than that of 8086
d) same as that of 8086
View Answer
d. None of these
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Answer: a
Explanation: Because of extra pipelining and other circuit level improvements, in real address
mode also, the 80286 operates at a much faster rate than 8086.
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4. In physical memory, if the segment size limit is exceeded by the instruction or data then
a) instruction is not executed
b) exception is generated
c) saves to next segment automatically
d) none of the mentioned
View Answer
Answer: b
Explanation: An exception is generated if the segment size limit is exceeded by the instruction or
the data.
5. The 80286 reserves fixed area of physical memory for
a) system initialization
b) interrupt vector table
c) system initialization and interrupt vector table
d) none of the mentioned
View Answer
Answer: c
Explanation: The 80286 reserves two fixed areas of physical memory for system initialization and
interrupt vector table.
6. In the real mode, the memory that is reserved for interrupt vector table is
a) first 2 KB of memory
b) first 1 KB of memory
c) last 2 KB of memory
d) last 1 KB of memory
View Answer
Answer: b
Explanation: In the real mode, the first 1 Kbyte of memory starting from the address 00000H to
003FFH, is reserved for interrupt vector table.
7. In the real mode, the memory that is reserved for system initialization is
a) from 004FFH to 0FFFFH
b) from 004FFH to 05FFFH
c) from FFFF0H to FFFFFH
d) from FFF00H to FFFFFH
View Answer
Answer: c
Explanation: The addresses from FFFF0H to FFFFFH are reserved for system initialization, in real
addressing mode.
8. When 80286 is reset, it always starts its execution in
a) protected virtual addressing mode
b) real addressing mode
c) either real or protected virtual address modes
d) none of the mentioned
View Answer
d. None of these
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Answer: b
Explanation: When 80286 is reset, it always starts its execution in real addressing mode.
9. The 80286 in real addressing mode performs
a) initialization of IP
b) enables interrupts
c) sets up descriptor table
d) all of the mentioned
View Answer
Answer: d
Explanation: The 80286 in real addressing mode performs the following functions: it initializes IP
and other registers of 80286, initializes the peripheral, enables interrupts, sets up descriptor
tables, and then prepares it for entering the protected virtual address mode.
10. In real address mode, while addressing the physical memory, the 80286 uses the signal
a) HLDA
b) BHE (active low)
c) CAP
d) HOLD
View Answer
Answer: b
Explanation: In real address mode, while addressing the physical memory, the 80286 uses BHE
(active low) along with A0-A19.
ses on “Protected Virtual Address Mode (PVAM) -1”.
1. The procedure of fetching the chosen program segments or data from the secondary storage
into the physical memory is
a) mapping
b) swapping
c) unswapping
d) pipelining
View Answer
Answer: b
Explanation: Swapping is the procedure of fetching the chosen program segments or data from
the secondary storage into the physical memory.
2. The procedure of storing back the partial results on to the secondary storage is called
a) mapping
b) swapping
c) unswapping
d) pipelining
View Answer
Answer: c
Explanation: The procedure of storing back the partial results or data back on to the secondary
storage is called unswapping.
3. The ability of 80286 to address the virtual memory per task is
a) 1MB
b) 1GB
c) 1TB
d. None of these
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d) none of the mentioned
View Answer
Answer: b
Explanation: The 80286 is able to address 1Gbyte of virtual memory per task.
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4. The branch instructions are handled by
a) swapping mechanism
b) unswapping mechanism
c) operating system
d) all of the mentioned
View Answer
Answer: d
Explanation: The handling of branch instructions like JUMP and CALL is taken care of, by the
swapping and unswapping mechanism, and operating system.
5. A descriptor contains information of
a) program segment
b) page
c) regarding segment and its access rights
d) all of the mentioned
View Answer
Answer: d
Explanation: The segments or pages have been associated with a data structure known as a
descriptor. The descriptor contains information on the page, and also carry relevant information
regarding a segment, and its access rights.
6. The descriptors that are used for subroutines and interrupt service routines are
a) data segment descriptors
b) gate descriptors
c) code segment descriptors
d) system segment descriptors
View Answer
Answer: b
Explanation: For data segment, the corresponding descriptor may be data segment descriptor and
for code segment, there may be code segment descriptor. For subroutines and interrupt service
routines there are gate descriptors.
7. A segment with low privilege level is not allowed to access another segment of
a) low privilege level
b) high privilege level
c) low and high privilege level
d) none of the mentioned
View Answer
Answer: b
Explanation: A segment with low privilege level is not allowed to access another segment with
high privilege level.
8. A descriptor is used to carry out
a) transfer of control
b) task switching
d. None of these
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c) to store privilege level and segment limit
d) all of the mentioned
View Answer
Answer: d
Explanation: A descriptor is used to carry out additional functions like transfer of control and task
switching.
9. The descriptor that is used for special system data segments and control transfer operations is
a) data segment descriptors
b) gate descriptors
c) code segment descriptors
d) system segment descriptors
View Answer
Answer: d
Explanation: The 80286 has system segment descriptor, that is used for special system data
segments, and control transfer operations.
10. A code segment descriptor contains
a) 16-bit segment limit
b) 24-bit segment base address
c) 8-bit access rights byte
d) all of the mentioned
View Answer
Answer: d
Explanation: A code or data segment descriptor contains 16-bit segment limit, 24-bit segment base
address, 8-bit access rights byte and the remaining 16-bits are reserved by Intel for upward
compatibility.
11. In access rights byte, if P (Present)=1, then the segment is mapped into
a) physical memory
b) virtual memory
c) no mapping takes place
d) none of the mentioned
View Answer
Answer: a
Explanation: If P=1, then the segment is mapped into physical memory.
12. In access rights byte, to select system segment descriptor, the condition is
a) S=1
b) S=0
c) S not equal to zero
d) none of the mentioned
View Answer
Answer: b
Explanation: If S (segment descriptor)=0, then system segment descriptor or gate descriptor is
selected.
13. If S (segment descriptor)=1, then the descriptor selected is
a) code segment descriptor
b) data segment descriptor
c) stack segment descriptor
d. None of these
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d) all of the mentioned
View Answer
Answer: d
Explanation: If S=1, then code or data (including stack) segment descriptors are selected.
14. The memory of limit field is
a) 2 bits
b) 4 bits
c) 8 bits
d) 16 bits
View Answer
Answer: d
Explanation: The limit field, which is the maximum allowed offset address, is of 16 bits
1. Which of the following is a type of system segment descriptor?
a) system descriptor
b) gate descriptor
c) system descriptor and gate descriptor
d) none of the mentioned
View Answer
Answer: c
Explanation: The system segment descriptors are of seven types. The types 1 to 3 are called
system descriptors and the types 4 to 7 are called gate descriptors.
2. Which of the following is a type of gate descriptor?
a) call gate
b) task gate
c) interrupt gate
d) all of the mentioned
View Answer
Answer: d
Explanation: The gate descriptors are of four types namely, call gate, task gate, interrupt gate and
trap gate.
3. The gate descriptor contains the information of
a) destination of control transfer
b) stack manipulations
c) privilege level
d) all of the mentioned
View Answer
Answer: d
Explanation: The gate descriptor contains the information regarding the destination of control
transfer, required stack manipulations, privilege level and its type.
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4. The gate that is used to alter the privilege levels is
a) call gate
b) task gate
c) interrupt gate
d. None of these
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d) trap gate
View Answer
Answer: a
Explanation: Call gates are used to alter the privilege levels.
5. The gate that is used to specify a corresponding service routine is
a) call gate and trap gate
b) task gate and interrupt gate
c) interrupt gate and trap gate
d) task gate and trap gate
View Answer
Answer: c
Explanation: Interrupt gates and trap gates are used to specify corresponding service routines.
6. The gate that is used to switch from one task to another is
a) trap gate
b) task gate
c) task gate and trap gate
d) none of the mentioned
View Answer
Answer: b
Explanation: Task gate is used to switch from one task to another.
7. The gate that uses word count field is
a) trap gate
b) task gate
c) interrupt gate
d) call gate
View Answer
Answer: d
Explanation: The word count field is only used by a call gate descriptor, to indicate the number of
bytes to be transferred from the stack of the calling routine to the stack of the called routine.
8. The memory that maintains the most frequently required data for execution, in a high speed
memory is called
a) virtual memory
b) physical memory
c) cache memory
d) ROM (read only memory)
View Answer
Answer: c
Explanation: To minimize the time required for fetching the frequently required descriptor
information, from the main memory, cache memory is used in which the most frequently required
data for execution is stored.
9. The selector field consists of
a) requested privilege level (RPL)
b) table indicator
c) index
d) all of the mentioned
View Answer
d. None of these
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Answer: d
Explanation: In the protected mode, the contents of the segment registers are known as selectors.
The selector field consists of three fields namely, RPL, table indicator (TI) and index.
10. If table indicator, TI=0, then the descriptor table selected is
a) local descriptor table
b) global descriptor table
c) local and global descriptor table
d) none of the mentioned
View Answer
Answer: b
Explanation: The type of descriptor table is global if TI=0 and local if TI=1.
11. The instruction that is executed at privilege level zero (0) is
a) LDT
b) LGDT and LLDT
c) GDT
d) None of the mentioned
View Answer
Answer: b
Explanation: The LGDT and LLDT instructions are privileged, and may be executed only at
privilege level 0.
12. The instruction that loads a selector which refers to a local descriptor table, containing the
base address and limit for LDT is
a) LGT
b) GDT
c) LGDT
d) LLDT
View Answer
Answer: d
Explanation: The LLDT instruction loads a selector, which refers to a local descriptor table,
containing the base address, and limit for LDT.
13. The descriptor that is used to store task gates, interrupt gates and trap gates is
a) system descriptor table
b) gate descriptor table
c) interrupt descriptor table
d) none of the mentioned
View Answer
Answer: c
Explanation: The 80286 has a third type of descriptor table known as interrupt descriptor table,
which is used to store task gates, interrupt gates and trap gates.
14. The number of interrupt descriptors that the interrupt descriptor table (IDT) handles is
a) 16
b) 64
c) 128
d) 256
View Answer
d. None of these
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Answer: d
Explanation: The IDT is able to handle upto 256 interrupt descriptors.
15. The number of bytes required for an interrupt in an IDT is
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: c
Explanation: Six bytes are required for each interrupt in an interrupt descriptor table.
1. By using privilege mechanism the protection from unauthorized accesses is done to
a) operating system
b) interrupt handlers
c) system software
d) all of the mentioned
View Answer
Answer: d
Explanation: The operating system, interrupt handlers and other system softwares can be
protected from unauthorized accesses in virtual address space of each task using the privilege
mechanism.
2. The task privilege level at the instant of execution is called
a) Descriptor privilege level (DPL)
b) Current privilege level (CPL)
c) Effective privilege level (EPL)
d) None of the mentioned
View Answer
Answer: b
Explanation: Any one of the four privilege levels may be used to execute a task. The task privilege
level at that instant is called the Current Privilege Level (CPL).
3. Once the CPL is selected, it can be changed by
a) hold
b) transferring control using system descriptors
c) transferring control using gate descriptors
d) transferring control using interrupt descriptors
View Answer
Answer: c
Explanation: Once the CPL is selected, it cannot be changed during the execution normally in a
single code segment. It can only be changed by transferring the control, using gate descriptors, to
a new segment.
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4. The data segments defined in GDT (global descriptor table) and the LDT (local descriptor table)
can be accessed by a task with
a) privilege level 0
b) privilege level 1
c) privilege level 2
d. None of these
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d) privilege level 3
View Answer
Answer: a
Explanation: A task executing at level 0, the most privileged level, can access all the data
segments defined in GDT and the LDT of the task.
5. A task with privilege level 0, doesn’t refer to all the lower level privilege descriptors in
a) GDT (global descriptor table)
b) LDT (local descriptor table)
c) IDT (interrupt descriptor table)
d) None of the mentioned
View Answer
Answer: b
Explanation: The task with privilege level 0, refers to all the lower level privilege descriptors which
apply to all the descriptors except the LDT descriptors.
6. The selector RPL that uses a less trusted privilege than the current privilege level for further
use is known as
a) Least task privilege level
b) Descriptor privilege level
c) Effective privilege level
d) None of the mentioned
View Answer
Answer: c
Explanation: A selector RPL uses a less trusted privilege than the current privilege level for further
use. This is known as the Effective Privilege Level of the task.
7. The effective privilege level is
a) maximum numeric of RPL and CPL
b) minimum privilege of RPL and CPL
c) numeric minimum and privilege maximum of RPL and CPL
d) none of the mentioned
View Answer
Answer: c
Explanation: The effective privilege level is minimum in numeric and maximum in the privilege of
RPL and CPL.
8. The task requesting an access to a descriptor is allowed to access after checking the
a) type of descriptor
b) privilege level
c) type of descriptor and privilege level
d) corresponding segment
View Answer
Answer: c
Explanation: The task requesting an access to a descriptor is allowed to access to it and to the
corresponding segment, only after checking the type of the descriptor and privilege level(CPL,
RPL, DPL).
9. A CALL instruction can reference only a code segment descriptor with
a) DPL less privilege than CPL
b) DPL equal privilege to CPL
d. None of these
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c) DPL greater privilege than CPL
d) All of the mentioned
View Answer
Answer: b
Explanation: A CALL or JUMP instruction can reference only a code segment descriptor with DPL
equal to CPL of the task or a segment with a DPL of equal or greater privilege than CPL.
10. The RPL of a selector that referred to the code descriptor must have
a) less privilege than CPL
b) greater privilege than CPL
c) equal privilege than CPL
d) any privilege regarding CPL
View Answer
Answer: c
Explanation: The RPL of a selector that referred to the code descriptor must have the same
privilege as CPL.
11. The instruction that refers to only code segment descriptors with DPL equal to or less than the
task CPL is
a) CALL
b) IRET
c) ESC
d) RET and IRET
View Answer
Answer: d
Explanation: The RET and IRET instructions are to refer to only code segment descriptors with
DPL equal to or less than the task CPL.
12. When a JUMP instruction references a Task State Segment(TSS) descriptor, then DPL must
be
a) equally privileged as CPL
b) greater or equally privileged than CPL
c) less or equally privileged than CPL
d) less privileged than CPL
View Answer
Answer: c
Explanation: When a CALL or JUMP instruction references a Task State Segment(TSS)
descriptor, then DPL must be less or equally privileged than CPL.
13. The data segment access refers to
a) loading DS
b) loading ES
c) loading SS
d) all of the mentioned
View Answer
Answer: d
Explanation: Loading DS, ES or SS for referring to a new descriptor comes under the data
segment access.
14. An exception is generated when
a) privilege test is negative
d. None of these
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b) an improper segment is referenced
c) referenced segment is not present in physical memory
d) all of the mentioned
View Answer
Answer: d
Explanation: If the privilege test is negative or an improper segment is referenced then an
exception 13 is generated. If the referenced segment is not present in physical memory, an
exception 11 is generated.
of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Protection”.
1. The mechanism to provide protection, that is accomplished with the help of read/write privileges
is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
View Answer
Answer: a
Explanation: The restricted use of segments is accomplished with the help of read/write privileges.
2. The Local descriptor table (LDT) and Global descriptor table (GDT) are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
View Answer
Answer: c
Explanation: In restricted use of segments i.e. segment load check, the segment usages are
restricted by classifying the corresponding descriptors, under LDT and GDT.
3. The mechanism that is accomplished using descriptor usages limitations and rules of privilege
check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
View Answer
Answer: b
Explanation: Restricted accesses to segment, also called, operation reference check, is
accomplished using descriptor usages limitations, and rules of privilege check.
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4. The mechanism that is executed at certain privilege levels, determined by CPL (Current
Privilege Level) and I/O privilege level (IOPL) is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
View Answer
d. None of these
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Answer: c
Explanation: The privileged instructions or operations, also called, privileged instruction check, is
executed at certain privilege levels, determined by CPL and I/O privilege level(IOPL), as defined
by the flag register.
5. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) None of the mentioned
View Answer
Answer: c
Explanation: The IRET and POPF instructions do not perform any of their functions, if CPL is not
of the required privilege level.
6. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
View Answer
Answer: c
Explanation: IF remains unaffected if CPL is greater than zero. No exception is generated for this
condition.
7. The condition, “CPL not equals to zero” satisfies when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) All of the mentioned
View Answer
Answer: d
Explanation: The condition, “CPL not equals to zero” satisfies, when executing the instructions,
LIDT, LGDT, LTR, LMSW, CTS and HLT.
8. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) All of the mentioned
View Answer
Answer: c
Explanation: The condition CPL>IOPL exists, when executing the instructions, INs, IN, OUTS,
OUT, STI, CLI and LOCK.
9. The instruction at which the exception is generated, but the processor extension registers
contain the address of failing instruction is
a) LTR
b) INS
c) CTS
d. None of these
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d) ESC
View Answer
Answer: d
Explanation: At the ESC instruction, the exception is generated, but the processor extension
registers contain the address of failing instruction.
10. The exception that has no error code on a stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
View Answer
Answer: b
Explanation: The processor extension segment overrun has no error code on the stack.
11. Which of the following is protected mode exception?
a) double exception detected
b) invalid task state segment
c) stack segment overrun
d) all of the mentioned
View Answer
Answer: d
Explanation: Double exception detected, invalid task state segment, stack segment overrun,
processor extension segment overrun, are the protected mode exceptions.
1. Which of the following operation is not carried out by 80286?
a) task switch operation
b) halt
c) processor reset
d) none of the mentioned
View Answer
Answer: d
Explanation: The 80286 carries out six operations. They are:
1. processor reset and initialization
2. task switch operation
3. pointer testing instructions
4. protected mode initialization
5. how to enter protected mode?
6. halt.
2. After completion of the first cycle, the first task is again scheduled for the next cycle. This
process is known as
a) repetition
b) task switch operation
c) processor initiation
d) none of the mentioned
View Answer
Answer: b
Explanation: After completion of the first cycle, the first task is again scheduled for the next cycle,
and the process continues. The previous task that was incomplete, may be completed during its
d. None of these
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coming turns of the allotted CPU time slice. This switch-over operation from one task to another
is called task switch operation.
3. The operation that is provided by the internal architecture, to save the execution state of a task
is
a) processor reset
b) processor initialization
c) task switch operation
d) halt
View Answer
Answer: c
Explanation: The 80286 internal architecture provides a task switch operation, to save the
execution state of a task, and to load a new task to be executed.
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4. The instruction that can be used to carry out task switch operation is
a) software interrupt instruction
b) exception
c) external interrupt
d) all of the mentioned
View Answer
Answer: d
Explanation: A software interrupt instruction, exception or external interrupt, can also be used to
carry out task switch operation.
5. The IRET instruction gets back the execution state of the previous task, if
a) NT (nested task flag) = 1
b) NT (nested task flag) = 0
c) IF (interrupt flag) = 1
d) IF (interrupt flag) = 0
View Answer
Answer: a
Explanation: If NT = 1, the IRET instruction gets back the execution state of the previous task.
Otherwise, the IRET instruction lets the current task continue, after popping the required values
from the stack.
6. The NT flag is set by the task switch operation, that is initiated by
a) CALL
b) INT
c) CALL & INT
d) None of the mentioned
View Answer
Answer: c
Explanation: The NT flag is set by CALL or INT initiated task switch operations.
7. The 80286 executes LMSW instruction to enter into
a) real addressing mode
b) protected mode
c) real addressing and protected modes
d) none of the mentioned
View Answer
d. None of these
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Answer: b
Explanation: To enter into protected mode, 80286 executes LMSW instruction, that sets PE flag.
8. The instruction that sets the zero flag, if the segment referred to, by the selector can be read is
a) VERW
b) VERR
c) LSL
d) LAR
View Answer
Answer: b
Explanation: The VERR (VERify to Read) instruction sets the zero flag, if the segment referred to,
by the selector, can be read.
9. The instruction that sets the zero flag, if the segment referred to by the selector, can be written
as
a) VERW
b) APRL
c) LSL
d) LAR
View Answer
Answer: a
Explanation: The VERW (VERify to Write) instruction sets the zero flag, if the segment referred to,
by the selector can be written.
10. The instruction that reads the descriptor access rights byte into the register is
a) VERW
b) APRL
c) LSL
d) LAR
View Answer
Answer: d
Explanation: The LAR (Load Access Rights) instruction reads the descriptor access rights byte
into the register, if privilege rules allow.
11. The instruction that reads the segment limit into the register, if privilege rules and descriptor
type allow is
a) VERW
b) APRL
c) LSL
d) LAR
View Answer
Answer: c
Explanation: The LSL (Load Segment Limit) instruction reads the segment limit into the register,
if privilege rules, and descriptor type allow.
12. The instruction that adjusts the RPL (Requested Privilege Level) of the selector, to the numeric
maximum of current selector RPL value is
a) LAR
b) VERR
c) LSL
d. None of these
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d) APRL
View Answer
Answer: d
Explanation: The APRL (Adjust Requested Privilege Level) adjusts the RPL (Requested Privilege
Level) of the selector to the numeric maximum of current selector RPL value, and the RPL value
in the register.
1. Which of the following is a supporting chip of 80286?
a) interrupt controller
b) clock generator
c) bus controller
d) all of the mentioned
View Answer
Answer: d
Explanation: The interrupt controller 8259A, clock generator 82C284, and bus controller 82C288
are the unavoidable members of the family, of supporting chips of 80286.
2. In minimum mode, the function of 80286 is
a) data transfers to/from memory or I/O
b) controls the data transfer of 80287
c) controls the instruction execution of 80287
d) all of the mentioned
View Answer
Answer: d
Explanation: In a minimum mode, the 80286 carries out all the data transfers to/from memory or
I/O, controls the data transfer, and instruction execution of 80287.
3. The signal that is applied to the decoding logic, to differentiate between interrupt, code fetch
and data bus cycles is
a) COD
b) INTA (active low)
c) M/IO (active low)
d) All of the mentioned
View Answer
Answer: d
Explanation: The COD, INTA (active low), M/IO (active low) signals are applied to the decoding
logic, to differentiate between interrupt, I/O, code fetch, and data bus cycles.
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4. By adding which of the following, the minimum mode of 80286 gives the multibus interface of
80286?
a) bus controller
b) bus arbiter
c) interrupt controller
d) all of the mentioned
View Answer
Answer: b
Explanation: The addition of single chip 82C289 known as bus arbiter, to the configuration of
80286 minimum mode, gives the multibus structure of 80286.
d. None of these
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5. The number of bus controllers that are used for interfacing of memory and I/O devices is
a) 1
b) 2
c) 3
d) none of the mentioned
View Answer
Answer: b
Explanation: The interfacing of memory and I/O devices, uses two 82288 bus controllers, one each
for local, and system bus.
6. If the 80286 need to use system bus, then the signal that is to be active is
a) SRDY
b) SRDYEN
c) ARDYEN
d) ARDY
View Answer
Answer: c
Explanation: The ARDYEN pin is to be activated if the 80286 is to use the system bus. The
SRDYEN pin is to be grounded.
7. If MBYTES input is high, then the pin serves as
a) AEN
b) CEN
c) AEN and CEN
d) None of the mentioned
View Answer
Answer: a
Explanation: The MBYTES input selects the function of AEN/CEN pin. If MBYTES is high, the pin
serves as AEN, else it serves as CEN. The CEN pin is used for selecting one of the available
82288s.
8. Latches are used in 80286 to
a) demultiplex the address and data lines
b) latch the address signals
c) decode the select signals
d) latch the address and decode the select signals
View Answer
Answer: d
Explanation: The address and data lines are not multiplexed, hence no latches are required in
80286 system. Rather the addresses of the next bus cycle are displayed in advance, hence the
latches are required for latching the address, and decode the signals.
9. The I/O port addresses, that are not used, while designing practical systems around 80286 are
a) 0000H to 00FFH
b) 00FFH to FFFFH
c) 00F8H to 00FFH
d) 0000H to FFFFH
View Answer
Answer: c
Explanation: The I/O port addresses 00F8H to 00FFH are reserved by Intel, hence these should
not be used while designing practical systems around 80286.
d. None of these
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set of Microprocessors test focuses on “Priority of Bus Use By 80286, Bus Hold and HLDA
Sequence, Interrupt Acknowledge Sequence”.
1. Which of the following is the highest priority usage among them?
a) second transfer cycle of a processor extension data transfer
b) third transfer cycle of a processor extension data transfer
c) hold request
d) second byte transfer of 2-byte transfer at an odd address
View Answer
Answer: d
Explanation: The second byte transfer of 2-byte transfer at an odd address, is the highest priority
usage among the given usages.
2. The highest priority usage than any other usage is
a) transfer with LOCK (active low) signal
b) hold request
c) processor extension data transfer
d) data transfer performed by EU (execution unit)
View Answer
Answer: a
Explanation: The transfer with LOCK (active low) signal is the highest priority usage than any other
usage.
3. The lowest priority usage among the following is
a) hold request
b) processor extension data transfer
c) prefetch operation to fetch and arrange next instruction bytes in queue
d) data transfer performed by EU for instruction execution
View Answer
Answer: c
Explanation: The order of priority usages, starting from the highest one to the lowest one, is given
as
1. transfer with LOCK (active low) signal
2. second byte transfer of 2-byte transfer at an odd address
3. second or third transfer cycle of a processor extension data transfer
4. HOLD request
5. processor extension data transfer
6. data transfer performed by EU (execution unit)
7. prefetch operation to fetch and arrange next instruction bytes in queue.
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4. As a response to the valid bus hold request, the bus is pushed into
a) TH (hold) state
b) Ts (status) state
c) Tc (command) state
d) Ti (idle) state
View Answer
Answer: a
Explanation: 80286 local bus is relinquished for another bus master if a valid bus hold request is
d. None of these
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received at the HOLD input pin. As a response to a valid bus hold request, the bus is pushed into
TH state.
5. The bus arbiter relinquishes
a) Address
b) M/IO (active low)
c) COD/INTA (active low)
d) All of the mentioned
View Answer
Answer: d
Explanation: The address, M/IO (active low) and COD/INTA (active low) are relinquished by bus
arbiter.
6. A valid HOLD request is ascertained only after the completion of
a) 34 clockcycles
b) 24 clockcycles and 80286 is SET
c) 34 clockcycles and 80286 is SET
d) 34 clockcycles and 80286 is RESET
View Answer
Answer: d
Explanation: Only after 34 clockcycles, after the 80286 is reset, a valid HOLD request should be
ascertained.
7. The master PIC 8259A decides which of its slave interrupt controllers is to return the vector
address, as a response of
a) first INTA (active low) pulse from 80286
b) second INTA (active low) pulse from 80286
c) third INTA (active low) pulse from 80286
d) none of the mentioned
View Answer
Answer: a
Explanation: In response to the first INTA (active low) pulse from 80286, the master PIC 8259A
decides, which of its slave interrupt controllers is to return the vector address.
8. The slave (which is selected) sends the vector on data bus after the
a) first INTA (active low) pulse from 80286
b) second INTA (active low) pulse from 80286
c) third INTA (active low) pulse from 80286
d) none of the mentioned
View Answer
Answer: b
Explanation: The interrupt acknowledge sequence consists of two INTA (active low) pulses. After
the second pulse, the selected slave sends the vector on D0-D7 data lines, and 80286 reads it.
9. The signal of 82C288, that enables the cascade address drivers, during INTA cycles is
a) DEN
b) DT/R (active low)
c) MCE
d) MB
View Answer
d. None of these
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Answer: c
Explanation: The MCE (Master Cascade Enable) signal of 82C288 enables the cascade address
drivers during INTA cycles, to select the slave using the local address bus.
10. The LOCK (active low) signal is activated during
a) Ti of first INTA cycle
b) Ts of first INTA cycle
c) Th of second INTA cycle
d) Ts of second INTA cycle
View Answer
Answer: b
Explanation: The LOCK (active low) signal is activated during Ts of first INTA cycle.
11. The number of idle states (Ti), that is allowed between two INTA cycles, to meet the 8259A
speed and cascade address output delay is
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: c
Explanation: The 80286 allows three idle states (Ti) between the two INTA cycles, to meet the
8259A speed and cascade address output delay.
1. In which of these modes, the immediate operand is included in the instruction itself?
a) register operand mode
b) immediate operand mode
c) register and immediate operand mode
d) none of the mentioned
View Answer
Answer: b
Explanation: In immediate operand mode, the immediate operand is included in the instruction
itself.
2. In register address mode, the operand is stored in
a) 8-bit general purpose register
b) 16-bit general purpose register
c) si or di
d) all of the mentioned
View Answer
Answer: d
Explanation: In register address mode, the operand is stored either in one of the 8-bit or 16-bit
general purpose registers or in SI, DI, BX or BP.
3. In which of the following addressing mode, the offset is obtained by adding displacement and
contents of one of the base registers?
a) direct mode
b) register mode
c) based mode
d. None of these
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d) indexed mode
View Answer
Answer: c
Explanation: In a based mode, the offset is obtained by adding displacement and contents of one
of the base registers, either BX or BP.
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4. In which of the following addressing mode, the offset is obtained by adding displacement, with
the contents of SI?
a) direct mode
b) register mode
c) based mode
d) indexed mode
View Answer
Answer: d
Explanation: In an indexed mode, the offset is obtained by adding displacement, with contents of
an index register, either SI or DI.
5. The address of a location of the operand is calculated by adding the contents of any of the base
registers, with the contents of any of index registers in
a) based indexed mode with displacement
b) based indexed mode
c) based mode
d) indexed mode
View Answer
Answer: b
Explanation: In a based indexed mode, the operand is stored at a location, whose address is
calculated by adding the contents of any of the base registers, with the contents of any of the index
registers.
6. Which of the following is not a data type of 80286?
a) Ordinal or unsigned
b) ASCII
c) Packed BCD
d) None of the mentioned
View Answer
Answer: d
Explanation: The 80286 supports seven data types. They are
1. integer
2. Ordinal (unsigned)
3. pointer
4. string
5. ASCII
6. BCD
7. Packed BCD.
7. The representation of 8-bit or 16-bit signed binary operands using 2’s complement is a data
type of
a) Ordinal
b) ASCII
d. None of these
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c) Packed BCD
d) integer
View Answer
Answer: d
Explanation: In integer data type, 8-bit or 16-bit signed binary operands are represented using 2’s
complement.
8. The instruction that pushes the general purpose registers, pointer and index registers on to the
stack is
a) POPF
b) PUSH Imd
c) PUSH*A
d) PUSHF
View Answer
Answer: c
Explanation: The PUSH*A instruction, pushes the general purpose registers, AX, CX, DX and BX,
pointer and index registers, SP, BP, SI, DI, on to the stack.
9. While executing the PUSH*A instruction, the stack pointer is decremented by
a) 1 bit
b) 2 bits
c) 4 bits
d) 16 bits
View Answer
Answer: b
Explanation: The stack pointer is decremented by 16 (eight 2-byte registers).
10. The statement that is true for the instruction POP*A is
a) flags are unaffected
b) no operands are required
c) exceptions generated are same as that of PUSH*A
d) all of the mentioned
View Answer
Answer: d
Explanation: The POP*A instruction, pops all the contents of the registers DI, SI, BP, SP, BX, DX,
CX and AX from the stack in this sequence, that is exactly opposite to that of pushing.
11. The instruction that multiplies the content of AL with a signed immediate operand is
a) MUL
b) SMUL
c) IMUL
d) None of the mentioned
View Answer
Answer: c
Explanation: The IMUL instruction multiplies the content of AL with a signed immediate operand,
and the signed 16-bit result is stored in AX.
12. The instruction that represents the ‘rotate source, count’ is
a) RCL
b) RCR
c) ROR
d. None of these
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d) All of the mentioned
View Answer
Answer: d
Explanation: The rotate source, count is a group of four instructions containing RCL, RCR, ROL,
ROR
1. In ‘Rotate source, count’ instructions, if the CF is equal to MSB of operand (source) then
a) TF is cleared
b) OF is cleared
c) TF is set
d) OF is set
View Answer
Answer: b
Explanation: If CF is equal to MSB of operand (source), the overflow flag is cleared, otherwise, it
is set to 1.
2. The instruction that affects the flags is
a) IMUL
b) INSW
c) INSB
d) POP*A
View Answer
Answer: a
Explanation: No flags are affected by the instructions, INSW, INSB and POP*A.
3. A general protection exception is generated, if the value of
a) CPL is equal to that of IOPL
b) CPL is less than that of IOPL
c) CPL is greater than that of IOPL
d) None of the mentioned
View Answer
Answer: c
Explanation: When the value of CPL is greater than that of IOPL, a general protection exception
is generated.
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4. While executing the instruction, OUTSW, the SI is incremented by
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: b
Explanation: The SI is automatically incremented by 1 for byte (OUTSB) and 2 for word (OUTSW)
operations.
5. The instruction that is used to exit the procedure is
a) QUIT
b) STOP
c) LEAVE
d. None of these
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d) EXIT
View Answer
Answer: c
Explanation: The instruction, LEAVE, is generally used with high level languages, to exit a
procedure.
6. The instruction that determines the number of bytes, to be copied into the new stack frame,
from the previous stack is
a) ENTER
b) BOUND
c) CLTS
d) LEAVE
View Answer
Answer: a
Explanation: The ENTER instruction prepares a stack structure for parameters of a procedure to
be executed further. This instruction determines the number of bytes to be copied, into the new
stack frame, from the previous stack.
7. The instruction that is used to check whether a signed array offset is within the limit, defined for
it by the starting and ending index is
a) ENTER
b) BOUND
c) CLTS
d) LEAVE
View Answer
Answer: b
Explanation: The BOUND instruction is used to check whether a signed array offset is within the
limit defined for it, by the starting and ending index.
8. The CLTS (Clear Task Switch Flag) instruction records every execution of WAIT and ESC and
is trapped if the flag(s)
a) PE (Protection Enable) and TS (task switch) flags are set
b) Emulate Processor extension flag is set
c) MP flag and task switched flag is set
d) PE and MP flag is set
View Answer
Answer: c
Explanation: The CLTS (Clear Task Switch Flag) instruction records every execution of WAIT and
ESC, and is trapped, if the MP flag and task switched flag is set.
9. The instruction that determines whether the segment pointed to, by a 16-bit register, can be
accessed from the current privilege level is
a) RPL
b) CPL
c) ARPL
d) VERR
View Answer
Answer: d
Explanation: The VERR/VERW instructions determine whether the segment pointed to, by a 16-
bit register, can be accessed from the current privilege level.
d. None of these
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10. The instruction that loads 6 bytes from a memory block, pointed to by the effective address of
the operand, into global descriptor table register is
a) LLDT
b) SGDT
c) LGDT
d) None of the mentioned
View Answer
Answer: c
Explanation: The LGDT (load global descriptor table register) loads 6 bytes from a memory block,
pointed to by the effective address of the operand, into global descriptor table register.
11. In LGDT instruction, while loading 6 bytes, the first word is loaded into the field of
a) LIMIT field
b) BASE field
c) Either LIMIT or BASE field
d) None of the mentioned
View Answer
Answer: a
Explanation: While loading the 6 bytes, the first word is loaded into the LIMIT field of the descriptor
table register. The next three bytes are loaded into the BASE field of the register, and the
remaining byte is ignored.
1. Which of the following is not a block of an architecture of 80287?
a) bus control logic
b) data interface and control unit
c) floating point unit
d) none of the mentioned
View Answer
Answer: d
Explanation: The three blocks of an internal architecture of 80287 are:
1. bus control logic
2. data interface and control unit
3. floating point unit.
2. The unit that provides and controls the interface, between the internal 80287 bus and 80286
bus via data buffer is
a) bus control logic
b) data interface and control unit
c) floating point unit
d) none of the mentioned
View Answer
Answer: a
Explanation: The bus control logic provides and controls the interface, between the internal 80287
bus and 80286 bus via data buffer.
3. The data interface and control unit consists of
a) status and control words
b) tag words and error pointers
c) instruction decoders
d. None of these
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d) all of the mentioned
View Answer
Answer: d
Explanation: The data interface and control unit contains status and controls words, TAG words
and error pointers.
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4. The word that optimizes the NDP performance, by maintaining a record of empty and non-empty
register locations is
a) Status and control words
b) TAG words
c) Error pointers
d) All of the mentioned
View Answer
Answer: b
Explanation: The TAG word optimizes the NDP performance by maintaining a record of empty
and non-empty register locations. It helps the exception handler to identify special values in the
contents of the stack locations.
5. The part of the data interface and control unit, that points to the source of exception generated
is
a) Status and control words
b) TAG words
c) Error pointers
d) None of the mentioned
View Answer
Answer: c
Explanation: The error pointers point to the source of exception (address of the instruction that
generated the exception) generated.
6. The data bus in a floating point unit is of
a) 16 bits
b) 32 bits
c) 64 bits
d) 84 bits
View Answer
Answer: d
Explanation: The data bus in a floating point unit is of 84-bits. Out of this 84-bits, the lower 68 bits
are significant (mantissa) data bit, the next 16 bits are used for the exponent.
7. The arrangement of data that is to be shifted successively, whenever required for the execution,
is done by
a) error pointer
b) data buffer
c) barrel shifter
d) none of the mentioned
View Answer
Answer: c
Explanation: The barrel shifter arranges and presents the data to be shifted successively,
whenever required for the execution.
d. None of these
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8. The word that is used to select one of the processing options, among the provided ones is
a) status word
b) control word
c) status and control words
d) none of the mentioned
View Answer
Answer: b
Explanation: The control word is used to select one of the processing options, among the ones
provided by 80287.
9. After reset of 80287, the control bit that is initialized to zero is
a) masking bits
b) precision control bits
c) rounding control bits
d) infinity control bits
View Answer
Answer: d
Explanation: The infinity control bit is initialized to zero after reset.
10. The bits that are modified depending upon the result of the execution of arithmetic instructions
are
a) masking bits
b) rounding control bits
c) condition code bits
d) error summary bits
View Answer
Answer: c
Explanation: The condition code bits are similar to the flags of a CPU. These are modified
depending upon the result of the execution of arithmetic instructions.
1. If the stack flag is set, and condition code bit C1=1, then the stack is
a) full
b) overflown
c) underflown
d) empty
View Answer
Answer: b
Explanation: If the stack flag is set, and condition code bit C1=1, then the stack has overflown.
2. If the stack flag is set, and condition code bit C1=0, then the stack is
a) full
b) overflown
c) underflown
d) empty
View Answer
Answer: c
Explanation: If the stack flag is set, and condition code bit C1=0, then the stack has underflown.
3. The bits that affect the result of arithmetic operations like ADD, SUB, MUL, DIV are
a) condition code bits
b) rounding control bits
d. None of these
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c) masking bits
d) precision control bits
View Answer
Answer: d
Explanation: The precision control bits affect ADD, SUB, MUL, DIV and SQRT results.
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4. The precision is decided by the
a) opcode
b) extended precision format
c) opcode or extended precision format
d) none of the mentioned
View Answer
Answer: c
Explanation: For other than the arithmetic instructions (like ADD, SUB, MUL, DIV and SQRT), the
precision is decided by opcode or extended precision format.
5. If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables a data
transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
View Answer
Answer: c
Explanation: If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables
a data transfer from 80286 to 80287.
6. If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables a data
transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
View Answer
Answer: b
Explanation: If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables
a data transfer from 80287 to 80286.
7. Which of the input line(s) indicate that the CPU is performing an escape operation, and enables
80287 to execute the next instruction?
a) NPWR (active low) and NPRD (active low)
b) NPS1 and NPS2 (active low)
c) NPS1 (active low) and NPS2
d) CMD0 and CMD1
View Answer
Answer: c
Explanation: The Numeric Processor select input lines, NPS1 (active low) and NPS2, indicate that
the CPU is performing an escape operation, and enables 80287 to execute the next instruction.
d. None of these
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8. For which pin of 80286 is the active low pin, BUSY of 80287, connected?
a) ERROR (active low)
b) BUSY (active low)
c) HLDA
d) TEST (active low)
View Answer
Answer: d
Explanation: The BUSY (active low) is connected to the TEST (active low) pin of 80286.
9. If Clock Mode (CM) input pin is held low, then the CLK input is divided by
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: b
Explanation: If Clock Mode (CM) input pin is held high, then the CLK input is directly used for
deriving the internal timings. Else, it is divided by 2.
10. Which of the following pin is not involved in the interface of 80287 with 80286?
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
View Answer
Answer: c
Explanation: The 10 pins, PEREQ, PEACK#, BUSY#, ERROR#, NPRD(active low)#,
NPWR(active low)#, NPS1(active low)#, NPS2#, CMD0 and CMD1.
11. The PEACK (active low) when activated, the pin that goes into deactivation is
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
View Answer
Answer: a
Explanation: When the data transfer is over, the CPU activates PEACK (active low)# pin, which
results in deactivating the PEREQ pin by 80287.
1. The 80386DX is a processor that supports
a) 8-bit data operand
b) 16-bit data operand
c) 32-bit data operand
d) all of the mentioned
View Answer
Answer: d
Explanation: The 80386DX is a 32-bit processor that supports, 8-bit/16-bit/32-bit data operands.
2. The 80386DX has an address bus of
a) 8 address lines
d. None of these
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b) 16 address lines
c) 32 address lines
d) 64 address lines
View Answer
Answer: c
Explanation: The 80386, with its 32-bit address bus, can address up to 4 GB of physical memory.
3. The number of debug registers that are available in 80386, for hardware debugging and control
is
a) 2
b) 4
c) 8
d) 16
View Answer
Answer: c
Explanation: The 80386 offers a set of total eight debug registers DR0-DR7, for hardware
debugging and control.
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4. The memory management of 80386 supports
a) virtual memory
b) paging
c) four levels of protection
d) all of the mentioned
View Answer
Answer: d
Explanation: The memory management section of 80386 supports the virtual memory, paging and
four levels of protection, maintaining full compatibility with 80286.
5. The 80386 enables itself to organize the available physical memory into pages, which is known
as
a) segmentation
b) paging
c) memory division
d) none of the mentioned
View Answer
Answer: b
Explanation: The concept of paging which is introduced in 80386, enables it to organize the
available physical memory into pages of size 4 KB each, under the segmented memory.
6. The 80386 consists of
a) on-chip address translation cache
b) instruction set of predecessors with upward compatibility
c) virtual memory space of 64TB
d) all of the mentioned
View Answer
Answer: d
Explanation: The 80386 has on-chip address translation cache, and the instruction set is upward
compatible with all its predecessors.
d. None of these
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7. 80386DX is available in a grid array package of
a) 64 pin
b) 128 pin
c) 132 pin
d) 142 pin
View Answer
Answer: c
Explanation: The 80386DX is available in a 132-pin grid array package.
8. The operating frequency of 80386DX is
a) 12 MHz and 20 MHz
b) 20 MHz and 33 MHz
c) 32 MHz and 12 MHz
d) all of the mentioned
View Answer
Answer: b
Explanation: The operating frequency of 80386DX is 20MHz and 33 MHz.
9. The 80386 in its protected mode, in its virtual mode of operation, can run the applications of
a) 8086
b) 80286
c) 80287
d) 80387
View Answer
Answer: a
Explanation: The 80386 can run the applications under protected mode, in its virtual 8086 mode
of operation.
10. The 80386 in protected mode, supports all software written for
a) 8086 and 80287
b) 80286 and 80287
c) 80287 and 80387
d) 80286 and 8086
View Answer
Answer: d
Explanation: The 80386 in protected mode, supports all software written for 8086 and 80286 (to
be executed under the control of memory management and protection abilities of 80386).
1. Which of the units is not a part of the internal architecture of 80386?
a) central processing unit
b) memory management unit
c) bus interface unit
d) none of the mentioned
View Answer
Answer: d
Explanation: The internal architecture of 80386 is divided into three sections namely, central
processing unit, memory management unit and bus interface unit.
2. The central processing unit has a sub-division of
a) memory unit and control unit
b) memory unit and ALU
d. None of these
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c) execution unit and instruction unit
d) execution unit and memory unit
View Answer
Answer: c
Explanation: The central processing unit is further divided into the execution unit and instruction
unit.
3. The unit that is used for handling data, and calculates offset address is
a) memory management unit
b) execution unit
c) instruction unit
d) bus interface unit
View Answer
Answer: b
Explanation: The execution unit has eight general purpose and eight special purpose registers,
which are either used for handling the data or calculating the offset addresses.
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4. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
View Answer
Answer: c
Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte instruction
code queue, after decoding them so as to pass it to the control section, for deriving the necessary
control signals.
5. The unit that increases the speed of all shift and rotate operations is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
View Answer
Answer: d
Explanation: The barrel shifter speeds up all shift and rotate operations.
6. The memory management unit consists of
a) segmentation unit
b) paging unit
c) segmentation and paging units
d) none of the mentioned
View Answer
Answer: c
Explanation: The memory management unit consists of a segmentation unit and a paging unit.
7. The segmentation unit allows
a) maximum size of 4GB segments
b) use of segment address components
c) use of offset address components
d. None of these
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d) all of the mentioned
View Answer
Answer: d
Explanation: The segmentation unit allows the use of two address components. They are:
segment and offset for relocation and sharing of code and data.
8. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit
b) execution unit
c) paging unit
d) instruction unit
View Answer
Answer: c
Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size each.
9. The paging unit works under the control of
a) memory management unit
b) segmentation unit
c) execution unit
d) instruction unit
View Answer
Answer: b
Explanation: The paging unit works under the control of the segmentation unit; i.e. each segment
is further divided into pages.
10. The unit that provides a four level protection mechanism, for system’s code and data against
application program is
a) central processing unit
b) segmentation unit
c) bus interface unit
d) none of the mentioned
View Answer
Answer: b
Explanation: The segmentation unit provides a four level protection mechanism, for protecting and
isolating the system’s code and data, from those of the application program.
11. The unit that has a prioritizer to resolve the priority of the various bus requests is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
View Answer
Answer: c
Explanation: The bus control unit has a prioritizer to resolve the priority of the various bus requests.
12. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
View Answer
d. None of these
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Answer: b
Explanation: The data buffer interfaces the internal data bus with the system bus.
13. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit
b) bus driving unit
c) address driver
d) bus driver
View Answer
Answer: c
Explanation: The address driver drives the bus enable and address signals A0-A31.
14. Which of the following pin when activated, allows address pipelining?
a) ADS
b) NA
c) AP
d) None of the mentioned
View Answer
Answer: b
Explanation: The Next Address (NA) input pin, if activated, allows address pipelining, during 80386
bus cycles.
15. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD
b) HLDA
c) READY
d) PEREQ
View Answer
Answer: c
Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for
interfacing of slow devices with the CPU.
16. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY
b) NMI
c) HLDA
d) PEREQ
View Answer
Answer: d
Explanation: The Processor Extension Request (PEREQ) output signal indicates to the CPU to
fetch a data word for the coprocessor.
17. The pipeline and dynamic bus sizing units handle
a) data signals
b) address signals
c) control signals
d) all of the mentioned
View Answer
Answer: c
Explanation: The
d. None of these
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1. The 16-bit registers are available with their extended size of 32 bits, by adding the registers with
a prefix of
a) X
b) E
c) 32
d) XX
View Answer
Answer: b
Explanation: A 32 bit register, known as an extended register, is represented by the register name
with a prefix of E.
2. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by
a) LSP
b) FSP
c) SP
d) None of the mentioned
View Answer
Answer: c
Explanation: Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the
names BP, SP, SI and DI represent the lower 16-bits.
3. Which of the following is a data segment register of 80386?
a) ES
b) FS
c) GS
d) All of the mentioned
View Answer
Answer: d
Explanation: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out
of which DS, ES, FS and GS are the four data segment registers.
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4. The register width used by the 32-bit addressing modes is
a) 8 bits
b) 16 bits
c) 32 bits
d) all of the mentioned
View Answer
Answer: d
Explanation: The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.
5. The flag that is additional in flag register of 80386, compared to that of 80286 is
a) VM flag
b) RF flag
c) VM and RF flag
d) None of the mentioned
View Answer
d. None of these
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Answer: c
Explanation: The VM and RF flags are added to the 80286 flag register, to derive the flag register
of 80386.
6. The VM (virtual mode) flag is to be set, only when 80386 is in
a) virtual mode
b) protected mode
c) either virtual or protected mode
d) all of the mentioned
View Answer
Answer: b
Explanation: If VM flag is set, the 80386 enters the virtual 8086 mode within the protected mode.
This is to be set only when the 80386 is in protected mode.
7. In protected mode of 80386, the VM flag is set by using
a) IRET instruction
b) Task switch operation
c) IRET instruction or task switch operation
d) None of the mentioned
View Answer
Answer: c
Explanation: The VM flag can be set using the IRET instruction or any task switch operation, only
in the protected mode.
8. During the instruction cycle of 80386, any debug fault can be ignored if
a) VM flag is set
b) VM flag is cleared
c) RF is cleared
d) RF is set
View Answer
Answer: d
Explanation: If RF (resume flag) is set, any debug fault is ignored during the instruction cycle.
9. The RF is not automatically reset after the execution of
a) IRET
b) POPA
c) IRET and POPF
d) IRET and PUSHF
View Answer
Answer: c
Explanation: The RF is automatically reset after the execution of every instruction, except for the
IRET and POPF instructions. Also, it is not cleared automatically after the successful execution of
JMP, CALL and INT instructions causing a task switch.
10. The segment descriptor register is used to store
a) attributes
b) limit address of segments
c) base address of segments
d) all of the mentioned
View Answer
d. None of these
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Answer: d
Explanation: The segment descriptor register is used to store the descriptor information like
attributes, limit and base addresses of segments.
1. The 32-bit control register, that is used to hold global machine status, independent of the
executed task is
a) CR0
b) CR2
c) CR3
d) All of the mentioned
View Answer
Answer: d
Explanation: The 80386 has three 32-bit control registers CR0, CR2 and CR3, to hold global
machine status, independent of the executed task.
2. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) All of the mentioned
View Answer
Answer: d
Explanation: The 80386 supports four types of descriptor tables. They are, GDT, IDT, LDT and
TSS.
3. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR
View Answer
Answer: a
Explanation: The GDTR and IDTR are known as system address registers.
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4. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) None of the mentioned
View Answer
Answer: b
Explanation: The LDTR and TR are known as system segment registers.
5. The test register(s) that is provided by 80386 for page caching is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers
View Answer
d. None of these
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Answer: c
Explanation: Two test registers are provided by 80386 for page caching, namely test control and
test status registers.
6. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7
View Answer
Answer: b
Explanation: Out of the eight debug registers, the two registers DR4 and DR5 are Intel reserved.
7. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3
View Answer
Answer: d
Explanation: The initial four registers, DR0-DR3 store four program controllable break point
addresses.
8. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned
View Answer
Answer: a
Explanation: The registers DR6 and DR7 respectively hold break point status and break point
control information.
9. The flag bits that indicate the privilege level of current IO operations are
a) Virtual mode flag bits
b) IOPL flag bits
c) Resume flag bits
d) None of the mentioned
View Answer
Answer: b
Explanation: The IOPL flag bits indicate the privilege level of current IO operations.
10. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers
View Answer
Answer: c
Explanation: The segment descriptor registers of 80386 are not available for programmers, rather,
they are internally used to store the descriptor information.
d. None of these
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1. Which of the following is not a scale factor of addressing modes of 80386?
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: c
Explanation: In case of the scaled the modes, any of the index register values can be multiplied
by a valid scale factor to obtain the displacement. The valid scale factors are 1, 2, 4 and 8.
2. Contents of an index register are multiplied by a scale factor that may be added further to get
the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
View Answer
Answer: b
Explanation: In scaled indexed mode, contents of an index register are multiplied by a scale factor
that may be added further to get the operand offset.
3. Contents of an index register are multiplied by a scale factor and then added to base register
to get the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned
View Answer
Answer: a
Explanation: In base scaled indexed mode, contents of an index register are multiplied by a scale
factor and then added to base register to get the operand offset.
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4. In the based scaled indexed mode with displacement mode, the contents of an index register
are multiplied by a scale factor and are added to
a) base register
b) displacement
c) base register and displacement
d) none of the mentioned
View Answer
Answer: c
Explanation: Contents of an index register are multiplied by a scale factor and the result is added
to a base register and a displacement to get the offset of an operand.
5. The following statement of ALP is an example of
MOV EBX, [EDX*4] [ECX].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d. None of these
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d) based scaled indexed mode with displacement mode
View Answer
Answer: a
Explanation: Since in base scaled indexed mode, contents of an index register are multiplied by a
scale factor and then added to base register to get the operand offset.
6. The following statement is an example of
MOV EBX, LIST [ESI*2].
MUL ECX, LIST [EBP*4].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode
View Answer
Answer: b
Explanation: Since in scaled indexed mode, contents of an index register are multiplied by a scale
factor that may be added further to get the operand offset.
7. Bit field can be defined as a group of
a) 8 bits
b) 16 bits
c) 32 bits
d) 64 bits
View Answer
Answer: c
Explanation: A group of at the most 32 bits(4 bytes) is defined as a bit field.
8. The maximum length of the string in a bit string of contiguous bits is
a) 2 MB
b) 4 MB
c) 2 GB
d) 4 GB
View Answer
Answer: d
Explanation: Bit string is a string of contiguous bits of maximum 4Gbytes in length.
9. The integer word is defined as
a) signed 8-bit data
b) unsigned 16-bit data
c) signed 16-bit data
d) signed 32-bit data
View Answer
Answer: c
Explanation: The integer word is the signed 16-bit data.
10. A 16-bit displacement that references a memory location using any of the addressing modes
is
a) Pointer
b) Character
c) BCD
d. None of these
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d) Offset
View Answer
Answer: d
Explanation: Offset is a 16-bit or 32-bit displacement that references a memory location using any
of the addressing modes.
11. A decimal digit can be represented by
a) unsigned integer
b) signed integer
c) unpacked BCD
d) packed BCD
View Answer
Answer: c
Explanation: Decimal digits from 0-9 are represented by unpacked bytes.
1. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned
View Answer
Answer: b
Explanation: All the instructions of 80386 are available in this mode except for those designed to
work with or for protected address mode.
2. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit
View Answer
Answer: c
Explanation: The paging unit is disabled in real address mode.
3. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned
View Answer
Answer: d
Explanation: To form a physical memory address, appropriate segment register contents are
shifted by left by 4 positions and then added to 16-bit offset address formed using one of
addressing modes, in same way as in the 80386 real address mode.
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4. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d. None of these
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d) none of the mentioned
View Answer
Answer: c
Explanation: The segments in 80386 real mode are may be overlapped or non-overlapped.
5. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned
View Answer
Answer: d
Explanation: The segments in 80386 real mode can be read, written or executed, i.e. no protection
is available.
6. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned
View Answer
Answer: d
Explanation: In protected mode, the contents of segment registers are used as selectors to
address descriptors which contain the segment limit, base address and access rights byte of the
segment.
7. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address
View Answer
Answer: a
Explanation: The effective address(offset) is added with segment base address to calculate linear
address.
8. If the paging unit is enabled, then it converts a linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
Answer: b
Explanation: The paging unit when enabled, it converts a linear address into physical address.
9. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned
View Answer
d. None of these
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Answer: b
Explanation: The linear address is used as a physical address if the paging unit is disabled.
10. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned
View Answer
Answer: c
Explanation: The paging unit is enabled only in protected mode.
11. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB
View Answer
Answer: d
Explanation: In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of
virtual memory per task.
1. The bit that indicates whether the segment has been accessed by the CPU or not is
a) base address
b) attribute bit
c) present bit
d) granular bit
View Answer
Answer: b
Explanation: The accessed bit or attribute bit (A) indicates whether the segment has been
accessed by the CPU or not.
2. The TYPE field of a descriptor is used to find the
a) descriptor type
b) segment type
c) descriptor and segment type
d) none
View Answer
Answer: c
Explanation: The type field decides the descriptor type and hence the segment type.
3. If the segment descriptor bit, S=0, then the descriptor is
a) data segment descriptor
b) code segment descriptor
c) system descriptor
d) all of the mentioned
View Answer
Answer: c
Explanation: If S=0, then system descriptor. If S=1, then code or data segment descriptor.
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d. None of these
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4. The bit that indicates whether the segment is page addressable is
a) base address
b) attribute bit
c) present bit
d) granularity bit
View Answer
Answer: d
Explanation: The granularity bit indicates whether the segment is page addressable.
5. If the Default operation size bit, D=1, the code segment operation size selected is
a) 8-bit
b) 16-bit
c) 32-bit
d) 64-bit
View Answer
Answer: c
Explanation: If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand
segment.
6. The segment descriptor contains
a) access rights
b) limit
c) base address
d) all of the mentioned
View Answer
Answer: d
Explanation: The segment descriptors are 8-byte quantities containing access right or attribute
bits along with the base and limit of the segments.
7. Which of the following is not a type of segment descriptor?
a) system descriptors
b) local descriptors
c) gate descriptors
d) none
View Answer
Answer: d
Explanation: The five types of segment descriptors of 80386 are:
1. Code or data segment descriptors
2. System descriptors
3. Local descriptors
4. TSS(task state segment) descriptors
5. Gate descriptors.
8. The limit field of the descriptor is of
a) 10 bits
b) 8 bits
c) 16 bits
d) 20 bits
View Answer
Answer: d
Explanation: The limit field of the descriptor is of 20 bits.
d. None of these
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9. The starting address of the segment in physical memory is decided by
a) physical memory
b) segment descriptors
c) operating system
d) base address
View Answer
Answer: c
Explanation: The base address that marks the starting address of the segment in physical memory
is decided by the operating system and is of 32 bits.
10. The total descriptors that the 80386 can handle is
a) 2K
b) 8K
c) 4K
d) 16K
View Answer
Answer: d
Explanation: 80386 can handle total 16K descriptors and hence segments.
1. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
View Answer
Answer: d
Explanation: The advantage of paging scheme is that the complete segment of a task need not
be in the physical memory at any time. Only a few pages of the segments, which are required
currently for the execution, need to be available in the physical memory.
2. The size of the pages in the paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
View Answer
Answer: b
Explanation: The paging divides the memory into fixed size pages.
3. To convert linear addresses into physical addresses, the mechanism that the paging unit uses
is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
View Answer
Answer: d
Explanation: The paging unit of 80386 uses a two level table mechanism, to convert the linear
addresses provided by the segmentation unit, into physical addresses.
d. None of these
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4. The control register that stores the 32-bit linear address, at which the previous page fault is
detected is
a) CR0
b) CR1
c) CR2
d) CR3
View Answer
Answer: c
Explanation: The control register, CR2, is used to store the 32-bit linear address, at which the
previous page fault is detected.
5. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
View Answer
Answer: b
Explanation: The paging unit handles every task in terms of three components namely page
directory, page table and the page itself.
6. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
View Answer
Answer: d
Explanation: The control register, CR3, is used as page directory physical base address register,
to store the physical starting address of the page directory.
7. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
View Answer
Answer: d
Explanation: The lower 12 bits of CR3 are always zero to ensure the page size aligned with the
directory.
8. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
View Answer
d. None of these
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Answer: b
Explanation: Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a
directory.
9. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
View Answer
Answer: c
Explanation: Each page table is of 4 Kbytes in size, and may contain a maximum of 1024 entries.
10. The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
View Answer
Answer: a
Explanation: The dirty bit (D) is set before a write operation to the page is carried out.
11. The bit that is undefined for page directory entries is
a) P-bit
b) A-bit
c) D-bit
d) All of the mentioned
View Answer
Answer: c
Explanation: The D-bit is undefined for page directory entries.
12. The bit that is used for providing protection is
a) User/Supervisor bit
b) Read bit
c) Write bit
d) all of the mentioned
View Answer
Answer: d
Explanation: The User/Supervisor (U/S) bit and Read/Write (R/W) bit are used to provide
protection.
13. The storage of 32 recently accessed page table entries to optimize the time, is known as
a) page table
b) page descriptor base register
c) page table cache
d) none of the mentioned
View Answer
Answer: c
Explanation: To optimize the considerable time taken for conversion, a page table cache is
provided, which stores the 32 recently accessed page table entries.
d. None of these
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14. The page table cache is also known as
a) page table storage
b) storage buffer
c) translation look aside buffer
d) all of the mentioned
View Answer
Answer: c
Explanation: The page table cache is also known as translation look aside buffer.
1. If the 80386 enters the protected mode from the real address mode, then it returns back to the
real mode, by performing the operation of
a) read
b) write
c) terminate
d) reset
View Answer
Answer: d
Explanation: If the 80386 enters the protected mode from the real address mode, then it cannot
return back to the real mode without a reset operation.
2. The unit that is needed for virtual mode 80386, only to run the 8086 programs, which require
more than 1 Mbyte of memory for memory management functions, is
a) execution unit
b) central processing unit
c) paging unit
d) segmentation unit
View Answer
Answer: c
Explanation: Paging unit is not necessarily enabled in the virtual mode, but may be needed to run
the 8086 programs, which require more than 1 Mbyte of memory, for memory management
functions.
3. The number of pages that the paging unit allows, in the virtual mode of 80386 is
a) 64
b) 128
c) 256
d) 512
View Answer
Answer: c
Explanation: In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size. Each
of the pages may be located anywhere within the maximum 4Gbytes physical memory.
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4. The privilege level at which the real mode programs are executed is
a) level 0
b) level 1
c) level 2
d) level 3
View Answer
d. None of these
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Answer: a
Explanation: The real mode programs are executed at the highest privilege level i.e. level 0.
5. The instructions to prepare the processor for protected mode can only be executed at the
privilege level
a) level 0
b) level 1
c) level 2
d) level 3
View Answer
Answer: a
Explanation: The instructions to prepare the processor for protected mode can only be executed
at the level 0.
6. The instruction that is unable to set or read the VM (Virtual Mode) bit is
a) PUSHF
b) IRET
c) POPF
d) PUSHF and POPF
View Answer
Answer: d
Explanation: The PUSHF and POPF instructions are unable to set or read the VM (Virtual Mode)
bit, as they do not access it. The virtual mode can be entered by using IRET instruction.
7. If the CKM pin of 80387 is high, then 80387 is operated in
a) real address mode
b) protected mode
c) synchronous mode
d) asynchronous mode
View Answer
Answer: c
Explanation: If the CKM pin of 80387 is high, then 80387 is operated in synchronous mode. If it is
low, then 80387 is operated in asynchronous mode.
8. The unit that handles the data and directs it to either FIFO or instruction decoder depending on
the bus control logic directive is
a) paging unit
b) central processing unit
c) segmentation unit
d) data interface and control unit
View Answer
Answer: d
Explanation: The data interface and control unit handles the data, and direct it to either FIFO or
instruction decoder, depending on the bus control logic directive.
9. The unit that is responsible for carrying out all the floating point calculations, allotted to the
coprocessor by 80386, is
a) Central processing unit
b) ALU
c) FPU
d. None of these
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d) None of the mentioned
View Answer
Answer: c
Explanation: The FPU (floating point unit) is responsible for carrying out all the floating point
calculations, allotted to the coprocessor by 80386.
10. The sizes of instruction and data pointer registers of 80387 respectively are
a) 32-bit, 32-bit
b) 48-bit, 32-bit
c) 32-bit, 48-bit
d) 48-bit, 48-bit
View Answer
Answer: d
Explanation: 80387 consists of two 48-bit registers, known as instruction and data pointer
registers.
11. To inform 80387 that the CPU wants to communicate with NPS1, the NPS1 line is directly
connected to
a) A31
b) A30
c) M/IO
d) D31
View Answer
Answer: c
Explanation: The NPS1 and NPS2 lines are directly connected with M/IO and A31 respectively, to
inform 80387 that the CPU wants to communicate with it (NPS1), and it is using one of the reserved
I/O addresses for 80387 (NPS2).
1. Which of the following is not a newly added instruction of 80386, that are not present in 80286?
a) bit scan instructions
b) bit test instructions
c) shift double instructions
d) none of the mentioned
View Answer
Answer: d
Explanation: The newly added instructions of 80386 are categorized into
1. bit scan instructions
2. bit test instructions
3. conditional set byte instructions
4. shift double instructions
5. control transfer via gates instructions.
2. The BSF (bit scan forward) instruction scans the operand in the order
a) from left to right
b) from right to left
c) from upper nibble
d) none of the mentioned
View Answer
Answer: b
Explanation: The BSF (bit scan forward) instruction scans the operand from right to left.
d. None of these
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3. The BSR (bit scan reverse) instruction scans the operand in the order
a) from left to right
b) from right to left
c) from upper nibble
d) none of the mentioned
View Answer
Answer: a
Explanation: The BSR (bit scan reverse) instruction scans the operand from left to right.
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4. If a ‘1’ is encountered when an operand is scanned by BSF, then
a) zero flag is reset
b) zero flag is set
c) VM flag is set
d) RF flag is reset
View Answer
Answer: b
Explanation: The BSF instruction scans the operand from right to left. If a ‘1’ is encountered during
the scan, zero flag is set, and the bit position of ‘1’ is stored into the destination operand.
5. If a ‘1’ is not encountered when an operand is scanned by BSR, then
a) zero flag is reset
b) zero flag is set
c) VM flag is reset
d) RF flag is set
View Answer
Answer: a
Explanation: The BSR instruction scans the operand from left to right. If a ‘1’ is not encountered
during the scan, zero flag is reset whether the scan is BSF or BSR.
6. Which of the following is not a bit test instruction?
a) BTC
b) BTS
c) BSF
d) BTR
View Answer
Answer: c
Explanation: The instruction, BSF, is a bit scan instruction. The four bit test instructions are:
BT (Test a Bit), BTC (Test a Bit and Complement), BTR (Test and Reset a Bit) and BTS (Test and
Set a bit).
7. In case of BT instruction, if the bit position in the destination operand specified by the source
operand, is ‘1’, then
a) zero flag is reset
b) carry flag is set
c) VM flag is set
d) RF flag is reset
View Answer
d. None of these
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Answer: b
Explanation: In case of BT instruction, if the bit position in the destination operand specified by the
source operand, is ‘1’, the carry flag is set, otherwise it is cleared.
8. Which of the following is not a conditional set byte instruction?
a) SETNP
b) SETO
c) SETNAE
d) SHRD
View Answer
Answer: d
Explanation: The SHRD (Shift Right Double) is a shift double instruction.
9. The instruction that shifts the specified number of bits in the instruction, from the upper side of
the source operand into the lower side of the destination operand is
a) SHRD
b) SHLD
c) SETNS
d) None of the mentioned
View Answer
Answer: b
Explanation: The SHLD instruction shifts the specified number of bits in the instruction, from the
upper side (i.e. MSB) of the source operand into the lower side (i.e. LSB) of the destination
operand.
10. The instruction that shifts 8 LSB bits of ECX into the MSB positions of EAX, one by one starting
from LSB of ECX is
a) SHLD ECX,EAX,8
b) SHLD EAX,ECX,8
c) SHRD ECX,EAX,8
d) SHRD EAX,ECX,8
View Answer
Answer: d
Explanation: The SHRD instruction shifts the specified number of bits in the instruction, from the
lower side (i.e. LSB) of the source operand into the upper side (i.e. MSB) of the destination
operand.
1. The first processor with an inbuilt floating point unit is
a) 80386
b) 80486
c) 80286
d) 8086
View Answer
Answer: b
Explanation: The 32-bit CPU 80486 from Intel is the first processor with an inbuilt floating point
unit. 80486DX is the first CPU with an on chip floating point unit.
2. Which of the following signal is handled by bus control and request sequencer?
a) ADS#
b) PWT
d. None of these
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c) RDY#
d) All of the mentioned
View Answer
Answer: d
Explanation: The bus control and request sequencer handle the signals like ADS#, PWT, RDY#,
W/R#, INTR, NMI, LOCK#, HOLD, HLDA, RESET and M/IO# which basically controls the bus
access and operations.
3. The unit that subjects the processor operation to boundary scan tests is
a) parity generation and control unit
b) prefetcher unit
c) boundary scan and control unit
d) segmentation unit
View Answer
Answer: c
Explanation: The boundary scan and control unit subjects the processor operation to boundary
scan tests to ensure the correct operation of various components of the mother board.
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4. The management of the virtual memory of the system and adequate protection to data or codes
in the physical memory is provided by
a) segmentation unit
b) paging unit
c) attribute PLA
d) all of the mentioned
View Answer
Answer: d
Explanation: The segmentation unit, paging unit, attribute PLA, descriptor registers, translation
look aside buffer and limit work together to manage the virtual memory of the system and provide
the adequate protection to the codes or data in the physical memory.
5. The flag that is added to 80486 in additional to the flags similar to 80386 is
a) alignment check flag
b) parity check flag
c) conditional flag
d) all of the mentioned
View Answer
Answer: a
Explanation: The register set of 80486 is similar to that of the 80386 but only a flag called as
alignment check flag is added to the flag register of 80386 to obtain the flag register of 80486.
6. The major limitation of 80386-387 system is
a) low speed
b) 80386 sends data using an I/O handshake technique
c) 80386 returns to real mode by reset operation
d) none of the mentioned
View Answer
Answer: b
Explanation: The major limitation of 80386-387 system is that the 80386 sends instruction or data
d. None of these
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to 80387 using an I/O handshake technique. To perform this handshaking and to carry additional
house keeping tasks, 80386 requires 15 clock cycles or more.
7. The datatype that the 80486 doesnot support is
a) Signed and unsigned
b) ASCII
c) Floating point
d) None
View Answer
Answer: d
Explanation: The datatypes that 80486 supports are
1. Signed
2. Unsigned
3. Floating point
4. BCD
5. String
6. ASCII.
8. In Little Endian data format, the data is stored as
a) MSB is stored at lower memory address and LSB at higher memory address
b) LSB is stored at lower memory address and MSB at higher memory address
c) MSB is stored at general purpose registers
d) LSB is stored at general purpose registers
View Answer
Answer: b
Explanation: In Little Endian data format, for a data of size bigger than 1 byte, the LSB is stored
at lower memory address and MSB at higher memory address.
9. The on-chip cache is used for storing
a) addresses of data
b) opcodes and data
c) data and their addresses
d) opcodes and their addresses
View Answer
Answer: b
Explanation: The unique feature of 80486 that is not available in 80386 is that the on-chip is used
for storing opcodes and data.
10. The on-chip cache is controlled by
a) Cache disable(CD)
b) No write through(NW)
c) Cache disable and No write through
d) None of the mentioned
View Answer
Answer: c
Explanation: Cache disable(CD) and No write through(NW) bits of control register CR0. To
completely disable cache, the CD and NW bits must be 11.
11. The on-chip cache can be flushed using external hardware using
a) FLUSH pin
b) TERMINATE pin
d. None of these
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c) FLOW pin
d) Pin FLUSH# or using software
View Answer
Answer: d
Explanation: The on-chip cache can be flushed using external hardware using pin FLUSH# or
using the software. The flushing operation clears all the valid bits for all the cache lines.
1. The salient feature of Pentium is
a) superscalar architecture
b) superpipelined architecture
c) superscalar and superpipelined architecture
d) none of the mentioned
View Answer
Answer: c
Explanation: The salient feature of Pentium is its superscalar, superpipelined architecture.
2. The number of stages of the integer pipeline, U, of Pentium is
a) 2
b) 4
c) 3
d) 6
View Answer
Answer: b
Explanation: The Pentium has two integer pipelines, U and V, where each one is a 4-stage
pipeline.
3. Which of the following is a cache of Pentium?
a) data cache
b) data cache and instruction cache
c) instruction cache
d) none of the mentioned
View Answer
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4. The speed of integer arithmetic of Pentium is increased to a large extent by
a) on-chip floating point unit
b) superscalar architecture
c) 4-stage pipelines
d) all of the mentioned
View Answer
Answer: c
Explanation: The Pentium has two integer pipelines, U and V, where each one is a 4-stage
pipeline. This enhances the speed of integer arithmetic of Pentium to a large extent.
5. For enhancement of processor performance, beyond one instruction per cycle, the computer
architects employ the technique of
a) super pipelined technique
b) multiple instruction issue
c) super pipelined technique and multiple instruction issue
d) none of the mentioned
View Answer
d. None of these
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Answer: b
Explanation: For enhancement of processor performance, beyond one instruction per cycle, the
computer architects employ the technique of multiple instruction issue.
6. Which of the following is a class of architecture of MII (multiple instruction issue)?
a) super pipelined architecture
b) multiple instruction issue
c) very small instruction word architecture
d) super scalar architecture
View Answer
Answer: d
Explanation: The MII architecture may again be classified into two categories:
1. Very long instruction word architecture
2. Superscalar architecture.
7. The compiler reorders the sequential stream of code that is coming from memory into a fixed
size instruction group in
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) super scalar architecture
View Answer
Answer: c
Explanation: In VLIW processors, the compiler reorders the sequential stream of code that is
coming from memory into a fixed size instruction group, and issues them in parallel for execution.
8. The architecture in which the hardware decides which instructions are to be issued concurrently
at run time is
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) superscalar architecture
View Answer
Answer: d
Explanation: In the superscalar architecture, the hardware decides which instructions are to be
issued concurrently at run time.
9. The CPU has to wait until the execution stage to determine whether the condition is met in
a) unconditional branch
b) conditional branch
c) pipelined execution branch
d) none of the mentioned
View Answer
Answer: b
Explanation: In conditional branch, the CPU has to wait until the execution stage to determine
whether the condition is met or not. When the condition satisfies, a branch is to be taken.
10. The memory device that holds branch target addresses for previously executed branches is
a) Tristate buffer
b) RAM
c) ROM
d. None of these
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d) Branch target buffer
View Answer
Answer: d
Explanation: The branch target buffer in Pentium CPU holds branch target addresses for
previously executed branches.
11. The branch target buffer is
a) four-way set-associative memory
b) has branch instruction address
c) has destination address
d) all of the mentioned
View Answer
Answer: d
Explanation: The branch target buffer is a four-way set-associative memory. Whenever a branch
is taken, the CPU enters the branch instruction address, and also the destination address in the
branch target buffer.
1. The stage in which the CPU fetches the instructions from the instruction cache in superscalar
organization is
a) Prefetch stage
b) D1 (first decode) stage
c) D2 (second decode) stage
d) Final stage
View Answer
Answer: a
Explanation: In the prefetch stage of pipeline, the CPU fetches the instructions from the instruction
cache, which stores the instructions to be executed. In this stage, CPU also aligns the codes
appropriately.
2. The CPU decodes the instructions and generates control words in
a) Prefetch stage
b) D1 (first decode) stage
c) D2 (second decode) stage
d) Final stage
View Answer
Answer: b
Explanation: In D1 stage, the CPU decodes the instructions and generates control words. For
simple RISC instructions, only single control word is enough for starting the execution.
3. The fifth stage of pipeline is also known as
a) read back stage
b) read forward stage
c) write back stage
d) none of the mentioned
View Answer
Answer: c
Explanation: The fifth stage or final stage of pipeline is also known as “Write back (WB) stage”.
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4. In the execution stage the function performed is
a) CPU accesses data cache
d. None of these
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b) executes arithmetic/logic computations
c) executes floating point operations in execution unit
d) all of the mentioned
View Answer
Answer: d
Explanation: In the execution stage, known as E-stage, the CPU accesses data cache, executes
arithmetic/logic computations, and floating point operations in execution unit.
5. The stage in which the CPU generates an address for data memory references in this stage is
a) prefetch stage
b) D1 (first decode) stage
c) D2 (second decode) stage
d) execution stage
View Answer
Answer: c
Explanation: In the D2 (second decode) stage, CPU generates an address for data memory
references in this stage. This stage is required where the control word from D1 stage is again
decoded for final execution.
6. The feature of separated caches is
a) supports the superscalar organization
b) high bandwidth
c) low hit ratio
d) all of the mentioned
View Answer
Answer: d
Explanation: The separated caches have low hit ratio compared to a unified cache, but have the
advantage of supporting the superscalar organization and high bandwidth.
7. In the operand fetch stage, the FPU (Floating Point Unit) fetches the operands from
a) floating point unit
b) instruction cache
c) floating point register file or data cache
d) floating point register file or instruction cache
View Answer
Answer: c
Explanation: In the operand fetch stage, the FPU (Floating Point Unit) fetches the operands from
either floating point register file or data cache.
8. The FPU (Floating Point Unit) writes the results to the floating point register file in
a) X1 execution state
b) X2 execution state
c) write back stage
d) none of the mentioned
View Answer
Answer: c
Explanation: In the two execution stages of X1 and X2, the floating point unit reads the data from
the data cache and executes the floating point computation. In the “write back stage” of pipeline,
the FPU (Floating Point Unit) writes the results to the floating point register file.
d. None of these
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9. The floating point multiplier segment performs floating point multiplication in
a) single precision
b) double precision
c) extended precision
d) all of the mentioned
View Answer
Answer: d
Explanation: The floating point multiplier segment performs floating point multiplication in single
precision, double precision and extended precision.
10. The instruction or segment that executes the floating point square root instructions is
a) floating point square root segment
b) floating point division and square root segment
c) floating point divider segment
d) none of the mentioned
View Answer
Answer: c
Explanation: The floating point divider segment executes the floating point division and square
root instructions.
11. The floating point rounder segment performs rounding off operation at
a) after write back stage
b) before write back stage
c) before arithmetic operations
d) none of the mentioned
View Answer
Answer: b
Explanation: The results of floating point addition or division process may be required to be
rounded off, before write back stage to the floating point registers.
12. Which of the following is a floating point exception that is generated in case of integer
arithmetic?
a) divide by zero
b) overflow
c) denormal operand
d) all of the mentioned
View Answer
Answer: d
Explanation: In the case of integer arithmetic, the possible floating point exceptions in Pentium
are:
1. divide by zero
2. overflow
3. denormal operand
4. underflow
5. invalid operation.
13. The mechanism that determines whether a floating point operation will be executed without
creating any exception is
a) Multiple Instruction Issue
b) Multiple Exception Issue
c) Safe Instruction Recognition
d. None of these
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d) Safe Exception Recognition
View Answer
Answer: c
Explanation: A mechanism known as Safe Exception Recognition (SER) had been employed in
Pentium which determines whether a floating point operation will be executed without creating any
exception.
1. Which of the following is not a transcendental instruction?
a) FSIN
b) FCOS
c) FMUL
d) FPTAN
View Answer
Answer: c
Explanation: The FMUL instruction is a float point multiplication, which is not a transcendental
instruction.
2. The transcendental instruction that supports computation of sine and cosine is
a) FCOSSIN
b) FSNE
c) FSINFCOS
d) FSINCOS
View Answer
Answer: d
Explanation: The instruction, FSINCOS, supports to compute sine and cosine.
3. The instruction that computes tan(x) is
a) FTAN
b) FTNGNT
c) FPTAN
d) FXTAN
View Answer
Answer: c
Explanation: The instruction, FPTAN, computes tan(x).
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4. The instruction that computes arctan(x) is
a) FTAN
b) FACTN
c) FARCTAN
d) FPATAN
View Answer
Answer: d
Explanation: The instruction, FPATAN, computes arctan(x) which is arc tangent of x.
5. The instruction, F2XMI, is used to compute
a) 2X
b) 2X-1
c) 2X+1
d. None of these
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d) 2X+2
View Answer
Answer: b
Explanation: The instruction, F2XMI, is used to compute 2X-1.
6. The instruction, FYL2XP, supports to compute the expression
a) Y*logX
b) Y*log2X
c) Y*log(2X+1)
d) Y*log2(X+1)
View Answer
Answer: d
Explanation: The instruction, FYL2XP, supports to compute the expression Y*log2(X+1).
7. The size of a general purpose floating point register of floating point unit is
a) 4 bytes
b) 40 bytes
c) 8 bytes
d) 80 bits
View Answer
Answer: d
Explanation: There are eight general purpose floating point registers in the floating point unit. Each
of these eight registers are of 80-bits width.
8. For floating point operations, the bits used by mantissa in a floating point register is
a) 32
b) 64
c) 72
d) 79
View Answer
Answer: b
Explanation: For floating point operations, 64 bits are used for the mantissa, and the rest 16 bits
for exponent.
9. The multimedia applications mainly require the architecture of
a) single instruction stream single data stream
b) multiple instruction stream single data stream
c) single instruction stream multiple data stream
d) multiple instruction stream multiple data stream
View Answer
Answer: c
Explanation: Most of the multimedia applications mainly require the architecture of single
instruction stream multiple data stream.
10. The size of each MMX (Multimedia Extension) register is
a) 32 bits
b) 64 bits
c) 128 bits
d) 256 bits
View Answer
d. None of these
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Answer: b
Explanation: The MMX registers use only the 64-bit mantissa portion of the general purpose
floating point registers, to store MMX operands. Thus, the MMX programmers virtually get eight
new MMX registers, each of 64 bits.
11. After a sequence of MMX instructions is executed, the MMX registers should be cleared by an
instruction,
a) CLEAR
b) RESET
c) EMM
d) EMMS
View Answer
Answer: d
Explanation: After a sequence of MMX instructions is executed, the MMX registers should be
cleared by an instruction, EMMS, which implies Empty the MMX Stack.
12. The number of pixels that can be manipulated in a single register by the CPU using MMX
architecture is
a) 4
b) 6
c) 8
d) 10
View Answer
Answer: c
Explanation: Any CPU can manipulate only one pixel at a time. But by using MMX architecture,
we can manipulate eight such pixels, packed in a single 64-bit register.
13. After executing the floating point instructions, the floating point registers should be cleared by
an instruction,
a) CLEAR
b) EFPR
c) EMMF
d) EMMS
View Answer
Answer: d
Explanation: After executing the floating point instructions, the floating point registers should be
cleared by an instruction, EMMS.
1. In the data type, packed byte, the number of bytes that can be packed into one 64-bit quantity
is
a) 2
b) 4
c) 8
d) 16
View Answer
Answer: c
Explanation: In packed byte data type, eight bytes can be packed into one 64-bit quantity.
2. Four words can be packed into 64-bit by using the data type,
a) unpacked word
d. None of these
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b) packed word
c) packed doubled word
d) one quad word
View Answer
Answer: b
Explanation: By using the packed word data type, four words can be packed into 64-bits.
3. The number of double words that can be packed into 64-bit register using packed double word
is
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: a
Explanation: Using packed double word, two double words can be packed into 64-bit.
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4. The data type, “one quad word” packs __________ into 64-bit.
a) two 32-bit quantities
b) four 16-bit words
c) one 32-bit and two 16-bit quantities
d) one single 64-bit quantity
View Answer
Answer: d
Explanation: The data type, “one quad word” packs one single 64-bit quantity into 64-bit register.
5. If the result of an operation is overflowed(exceeded than 16 bits) or underflowed then, only the
lower 16-bits of the result are stored in the register and this effect is known as
a) overflow/underflow effect
b) wrap-around effect
c) exceeding memory effect
d) none
View Answer
Answer: b
Explanation: If the result of an operation is overflowed (exceeded than 16 bits) or underflowed
then, only the lower 16-bits of the result are stored in the register, and this effect is known as wrap-
around effect.
6. In a multitasking operating system environment, each task should return to its own processor
state which is
a) contents of integer registers
b) contents of floating point registers
c) contents of MMX registers
d) all of the mentioned
View Answer
Answer: d
Explanation: In a multitasking operating system environment, each task should return to its own
processor state, which should be saved when the task switching occurs. The processor state here
means the contents of the registers, both integer and floating point or MMX register.
d. None of these
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7. Which of the following exception generated by MMX is the same type of memory access
exception as the X86 instructions?
a) page fault
b) segment not present
c) limit violation
d) all of the mentioned
View Answer
Answer: d
Explanation: The MMX instruction set generates the same type of memory access exception as
the X86 instructions namely; page fault, segment does not present and limit violation.
8. When an MMX instruction is getting executed, the floating-point tag word is marked
a) 11
b) 10
c) 00
d) 01
View Answer
Answer: c
Explanation: When an MMX instruction is getting executed, the floating-point tag word is marked
valid i.e. 00.
9. In a preemptive multitasking O.S., the saving and restoring of FP and MMX states are performed
by
a) Control unit
b) O.S.
c) MMX instructions
d) MMX registers
View Answer
Answer: b
Explanation: In a preemptive multitasking O.S., the application does not know when it is
preemptied. It is the job of the O.S. to save and restore the FP and MMX states, when performing
a context switch. Thus the user need not save or restore the state.
10. The instruction of MMX that is essential when a floating-point routine calls an MMX routine or
viceversa is
a) MOV
b) PADD
c) EMMS
d) None of the mentioned
View Answer
Answer: c
Explanation: The EMMS instruction is imperative when a floating point routine calls an MMX
routine or vice-versa. If we do not use EMMS at the end of MMX routine, subsequent floating-point
instructions will produce erratic results.
11. Pentium III is used in computers which run on the operating system of
a) windows NT
b) windows 98
c) unix
d) all of the mentioned
View Answer
d. None of these
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Answer: d
Explanation: Pentium III is the best option to use in computers from high performance desktop to
workstations and servers, running on operating systems like Windows NT, Windows 98 and UNIX.
12. The architecture of CPU of Pentium III is suitable for
a) multimedia
b) image processing
c) speech processing
d) all of the mentioned
View Answer
Answer: d
Explanation: The architecture of CPU of Pentium III is suitable for applications like imaging, image
processing, speech processing, multimedia and internet applications.
13. The Pentium III has the operating frequencies as
a) 300MHz,350MHz,400MHz
b) 400MHz,450MHz,500MHz
c) 350MHz,400MHz,450MHz
d) 450MHz,500MHz,550MHz
View Answer
Answer: d
Explanation: The Pentium III has three versions operating at frequencies, 450MHz, 500MHz and
550MHz, which are all commercially available.
14. The Pentium III consists of
a) dual independent bus architecture
b) 512 Kbyte cache
c) eight 64-wide Intel MMX registers
d) all of the mentioned
View Answer
Answer: d
Explanation: The Pentium III has dual independent bus architecture that increases the bandwidth.
It has a 512 Kbyte unified, non-blocking level2 cache and eight 64-wide Intel MMX registers.
1. The additional instructions that are designed especially for performing multimedia tasks are
known as
a) additional MMX instructions
b) multimedia MMX instructions
c) enhanced MMX instructions
d) none of the mentioned
View Answer
Answer: c
Explanation: The MMX technology adds 57 new instructions to the instruction set of processors.
These instructions are known as enhanced MMX instructions and are designed specifically for
performing multimedia tasks.
2. The MMX instruction, EMMS consists of __________ on which it operates.
a) source operand
b) destination operand
c) source and destination operand
d. None of these
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d) none of the mentioned
View Answer
Answer: d
Explanation: The instruction, EMMS, does not have any operand.
3. In all the MMX instructions, the destination operand resides in
a) Memory
b) RAM
c) Either in an MMX register or in memory
d) MMX register
View Answer
Answer: d
Explanation: In all the MMX instructions, the source operand is found either in an MMX register or
in memory, and the destination operand resides in MMX register.
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4. For the MMX instructions, the prefix, P, is used to represent the mode of
a) real addressing mode
b) virtual mode
c) packed mode
d) programmable mode
View Answer
Answer: c
Explanation: In the MMX instructions, if the operands are in the packed mode, the prefix, P, is
used to indicate packed data.
5. For the MMX instructions, the suffix, S, is used to represent
a) status
b) saturation
c) signed saturation
d) unsigned saturation
View Answer
Answer: c
Explanation: For the MMX instructions, the suffix “S” indicates signed saturation, and “US”
indicates unsigned saturation, while executing arithmetic computation in saturation mode.
6. The instruction that is used for quadword is
a) PADD
b) PCMPEQ
c) PAND
d) None of the mentioned
View Answer
Answer: d
Explanation: The instructions, PADD, PCMPEQ and PAND are used for packed byte, word and
double word.
7. The instruction, PSUBB, performs subtraction in
a) packed word
b) packed byte
c) packed double word
d. None of these
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d) unpacked word
View Answer
Answer: b
Explanation: The instruction, PSUBB, performs subtraction in a packed byte.
8. The instruction, PCMPGT, is used to compare two data types and check
a) equal to condition
b) less than condition
c) greater than condition
d) equal to and greater than condition
View Answer
Answer: c
Explanation: The instruction, PCMPGT, compares to check the greater than condition in packed
bytes, packed words and packed double words.
9. The instruction that is not operated on quad word is
a) MOV
b) PSLL
c) PSRA
d) All of the mentioned
View Answer
Answer: c
Explanation: The instruction, PSRA, performs arithmetic shift, right in a single cycle. It supports
only the shifting of packed word and double word data types.
10. When the instruction, PMULLW, is performed, then the lower order 16-bits of the 32 bit
products are stored in
a) source operand
b) destination operand
c) no storage of lower order
d) either source or destination
View Answer
Answer: b
Explanation: In the instruction, PMULLW, four 16 X 16 multiplications are performed, and the lower
order 16 bits of the 32-bit products are stored in destination.
11. When the instruction, PMULHW, is performed, then the higher order 16-bits of the 32 bit
products are stored in
a) source operand
b) destination operand
c) no storage of lower order
d) either source or destination
View Answer
Answer: b
Explanation: In the instruction, PMULHW, four 16 X 16 multiplications are performed, and the
higher order 16 bits of the 32-bit products are stored in destination.
12. The instruction in which both multiplication and addition are performed is
a) PAND
b) PMULHW
c) PADD
d. None of these
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d) PMADDWD
View Answer
Answer: d
Explanation: PMADDWD is an important multimedia instruction, which multiplies the four signed
words of the destination operand, with four signed words of source operand. This results in 32-bit
double words which are added, and the result is stored in the higher double word of the destination
operand.
13. If the result of PCMPEQ, which is a comparison of two packed data types, is a success, then
the mask generated is
a) mask 0s
b) mask 1s
c) mask 2s
d) mask 3s
View Answer
Answer: b
Explanation: If the result of PCMPEQ, which is a comparison of two packed data types is a
success, then the mask 1s is generated, otherwise a mask of 0s is generated, in the destination
operand.
1. The instructions that pass through the fetch, decode and execution stages sequentially is known
as
a) sequential instruction
b) sequence of fetch, decode and execution
c) linear instruction sequencing
d) non-linear instruction sequencing
View Answer
Answer: c
Explanation: The linear instruction sequencing is the one in which the instructions that pass
through the fetch, decode and execution stages sequentially.
2. During the execution of instructions, if an instruction is executed, then next instruction is
executed only when the data is read by
a) control unit
b) bus interface unit
c) execution unit
d) cpu
View Answer
Answer: b
Explanation: During the execution of instructions, only after the bus interface unit of CPU reads
the data from the main memory and returns it to the register, the next instruction execution will
commence.
3. Because of Pentium’s superscalar architecture, the number of instructions that are executed
per clock cycle is
a) 1
b) 2
c) 3
d) 4
View Answer
d. None of these
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Answer: b
Explanation: Pentium’s superscalar architecture employs five stage pipeline with U and V pipes.
Thus it can execute two instructions per clock.
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4. The type of execution which means that the CPU should speculate which of the next instructions
can be executed earlier is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
View Answer
Answer: a
Explanation: The speculative execution is an execution which means that the CPU should
speculate which of the next instructions can be executed earlier.
5. The execution in which the consecutive instruction execution in a sequential flow is hampered
is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
View Answer
Answer: b
Explanation: In the out of turn execution, the consecutive instruction execution in a sequential flow
is hampered and the CPU should be able to execute out of turn instructions.
6. A dual independent bus has
a) Enhanced system bandwidth
b) CPU that can access both cache and memory simultaneously
c) High throughput
d) All of the mentioned
View Answer
Answer: d
Explanation: A dual independent bus architecture is incorporated by Pentium-Pro to get an
enhanced system bandwidth and it also yields high throughput. It has the CPU which can access
both main memory and the cache simultaneously.
7. The unit that is used to implement the multiple branch prediction in Pentium-Pro is
a) control unit
b) bus interface unit
c) branch target buffer
d) branch instruction register
View Answer
Answer: c
Explanation: The processor uses an associative memory called branch target buffer for
implementing the algorithm, multiple branch prediction.
8. Which of the following is not an independent engine of Pentium-Pro?
a) fetch-decode unit
b) dispatch-execute unit
d. None of these
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c) control-execute unit
d) retire unit
View Answer
Answer: c
Explanation: Pentium-Pro incorporates three independent engines, 1. Fetch-decode unit 2.
Dispatch-execute unit 3. Retire unit.
9. The unit that accepts the sequence of instructions from the instruction cache as input is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) none
View Answer
Answer: a
Explanation: The fetch-decode unit accepts the sequence of instructions from the instruction
cache as input and then decodes them.
10. In fetch-decode unit, the number of parallel decoders that accept the stream of fetched
instructions and decode them is
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: c
Explanation: A set of three parallel decoders accepts the stream of fetched instructions and
decode them.
1. The decoder unit in fetch-decode unit converts the instructions into
a) executable statements
b) machine language statements
c) MMX instructions
d) micro operations
View Answer
Answer: d
Explanation: The decoder unit converts the fetched instructions into micro operations.
2. The logical source(s) and logical destination(s) that the micro operation has respectively are
a) 2,2
b) 1,3
c) 3,1
d) 3,2
View Answer
Answer: c
Explanation: Each microoperation contains two logical sources and one logical destination.
3. The microoperations that are converted by decoder are directly transferred to
a) decoder register
b) dispatch-execute unit
c) retire unit
d. None of these
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d) register alias table
View Answer
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4. The pool of instructions that are fetched is stored in an addressable memory called
a) tristate buffer
b) branch target buffer
c) reorder buffer
d) order buffer
View Answer
Answer: c
Explanation: The pool of instructions that are fetched is stored in an array of content addressable
memory called reorder buffer.
5. The unit that performs scheduling of instructions by determining the data dependencies is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) none
View Answer
Answer: b
Explanation: The dispatch-execute unit performs scheduling of instructions by determining the
data dependencies after which the microoperations of the scheduled instructions are executed in
the execution unit.
6. The unit that reads the instruction pool and removes the microoperations which have been
executed instruction pool is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) decoding unit
View Answer
Answer: c
Explanation: The retire unit reads the instruction pool containing the instructions and removes the
microoperations which have been executed instruction pool.
7. The speed of Pentium-Pro when compared to that of Pentium is
a) equal
b) twice
c) thrice
d) two-third
View Answer
Answer: b
Explanation: The features incorporated in Pentium-Pro enhances the speed of Pentium-Pro and
is twice as that of Pentium.
8. Which of the following is not supported by Pentium-Pro?
a) multiple branch prediction
b) mmx instruction set
c) speculative execution
d. None of these
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d) none
View Answer
Answer: b
Explanation: The Pentium-Pro does not support the MMX instruction set.
9. The feature of Pentium II is
a) high cache
b) operates at 2.8 volts
c) supports intel’s MMX instructions
d) all of the mentioned
View Answer
Answer: d
Explanation: The Pentium II has a higher cache and it can operate at 2.8 volts, thereby reducing
power consumption. The most important change of Pentium II is that it can support Intel’s MMX
instructions.
10. The results of speculative instruction execution is stored in
a) visible CPU registers
b) permanent memory
c) temporary memory
d) none
View Answer
Answer: c
Explanation: The results of speculative instruction execution should not be stored in CPU registers
and are temporarily stored, since they may have to be discarded, in case if there is a branch
instruction before these speculative instruction executions.
1. The feature of Pentium 4 is
a) works based on NetBurst microarchitecture
b) clock speed ranges from 1.4GHz to 1.7GHz
c) has hyper-pipelined technology
d) all of the mentioned
View Answer
Answer: d
Explanation: Pentium 4 is based on NetBurst microarchitecture. Clock speed varies from 1.4GHz
to 1.7GHz. It has hyper-pipelined technology.
2. Which of the following is not a module of Pentium 4 architecture?
a) front end module
b) execution module
c) control module
d) none
View Answer
Answer: c
Explanation: Pentium 4 architecture may be viewed having four basic modules.
1. Front end module
2. Out of order execution engine
3. Execution module
4. Memory subsystem module.
d. None of these
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3. The front module of Pentium 4 consists of
a) trace cache
b) microcode ROM
c) front end branch predictor
d) all of the mentioned
View Answer
Answer: d
Explanation: The front module of Pentium 4 contains
1. IA 32 Instruction decoder
2. Trace cache
3. Microcode ROM
4. Front end branch predictor.
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4. The unit that decodes the instructions concurrently and translate them into micro-operations is
a) trace cache
b) instruction decoder
c) execution module
d) front end branch predictor
View Answer
Answer: b
Explanation: The role of instruction decoder is to decode the instructions concurrently and
translate them into micro-operations known as micro-ops.
5. In complex instructions, when the instruction needs to be translated into more than 4 micro-
operations, then the decoder transfers the task to
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
View Answer
Answer: c
Explanation: In case of complex instructions, when the instruction needs to be translated into more
than 4 micro-operations, then the decoder transfers the task to microcode ROM.
6. The unit that does not store the instructions, but the decoded stream of instructions is
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
View Answer
Answer: a
Explanation: The trace cache is a special instruction cache because it does not store the
instructions, but the decoded stream of instructions.
7. Trace cache can store the micro-ops upto a range of
a) 6 K decoded micro-ops
b) 8 K decoded micro-ops
c) 10 K decoded micro-ops
d. None of these
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d) 12 K decoded micro-ops
View Answer
Answer: d
Explanation: Trace cache can store upto 12K micro-ops. The cache assembles the decoded
micro-ops into ordered sequence of micro-ops called traces.
8. The unit that predicts the locations from where the next instruction bytes are fetched is
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
View Answer
Answer: b
Explanation: The front end branch predictor predicts the locations from where the next instruction
bytes are fetched.
9. If complex instructions like interrupt handling, string manipulation appear, then the control from
trace cache transfers to
a) microcode ROM
b) front end branch predictor
c) execution module
d) instruction decoder
View Answer
Answer: a
Explanation: When some complex instructions like interrupt handling, string manipulation appear,
then the control from trace cache transfers to microcode ROM.
10. After the micro-ops are issued by the microcode ROM, the control goes to
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
View Answer
Answer: a
Explanation: After the micro-ops are issued by the microcode ROM, the control goes to Trace
cache once again. The micro-ops delivered by the trace cache and the microcode ROM are
buffered in a queue in an orderly fashion.
1. If the logical processors want to execute complex IA-32 instructions simultaneously then the
number of microcode instruction pointers required is
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: b
Explanation: If both the logical processors want to execute complex IA-32 instructions
simultaneously then two microcode instruction pointers are required, which will access the
microcode ROM.
d. None of these
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2. Which of the following is a type of branch prediction?
a) static prediction
b) dynamic prediction
c) static and dynamic prediction
d) none
View Answer
Answer: c
Explanation: There are two types of branch prediction namely static prediction and dynamic
prediction.
3. The prediction that is based on a statistical assumption that the majority of backward branches
occur in repetitive loops is
a) static prediction
b) dynamic prediction
c) branch prediction
d) none
View Answer
Answer: a
Explanation: The static prediction is based on a statistical assumption that the majority of
backward branches occur in the context of repetitive loops.
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4. The advantage of static prediction is
a) simple and fast
b) does not require table lookups or calculations
c) performs without much degradation
d) all of the mentioned
View Answer
Answer: d
Explanation: The static prediction is simple and fast. It does not require table lookups or
calculations. In case if a program contains a number of loops, static prediction performs without
much degradation.
5. The dynamic branch prediction algorithms use
a) Branch History Table (BHT)
b) Branch Target Buffer (BTB)
c) Branch History Table and Branch Target Buffer
d) None
View Answer
Answer: c
Explanation: The dynamic branch prediction algorithms use two types of tables, namely Branch
History Table (BHT) and Branch Target Buffer (BTB).
6. The unit that preserves the history of each conditional branch is
a) Branch Target Buffer (BTB)
b) Branch History Table (BHT)
c) Static prediction
d) Dynamic prediction
View Answer
d. None of these
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Answer: b
Explanation: The Branch History Table (BHT) preserves the history of each conditional branch
that the speculative branch prediction unit encounters during the last several cycles.
7. The BHT keeps a record that indicates the likelihood of the branches grouped as
a) strongly taken
b) taken
c) not taken
d) all of the mentioned
View Answer
Answer: d
Explanation: The BHT keeps a record that indicates the likelihood that the branch will be taken
based on its past history. The branches may be grouped as ‘strongly taken’, ‘taken’, ‘not taken’
and ‘strongly not taken’.
8. Each logical processor has
a) one 64-byte streaming buffer
b) one 32-byte streaming buffer
c) two 64-byte streaming buffers
d) two 32-byte streaming buffers
View Answer
Answer: c
Explanation: Each logic processor has its own set of two 64-byte streaming buffers, which store
the instruction bytes and subsequently they are dispatched to the instruction decode stage.
9. If there is a trace cache miss, then the instruction bytes are required to be fetched from the
a) instruction decoder
b) Level2 cache
c) execution module
d) none of the mentioned
View Answer
Answer: b
Explanation: If there is a trace cache miss, then the instruction bytes are required to be fetched
from the Level2 cache.
10. The Instruction Translation Lookaside Buffer(ITLB) is present in
a) trace cache
b) instruction decoder
c) logical processors
d) all of the mentioned
View Answer
Answer: c
Explanation: Since there are two logical processors, there are two ITLBs. Thus each logical
processor has its own ITLB and its own instruction pointer to track the progress of instruction fetch
for each of them.
1. The units that are primarily used to resolve indirect mode of memory addressing is called
a) ALU
b) AGU
c) ALU and AGU
d. None of these
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d) NONE
View Answer
Answer: b
Explanation: The AGUs(Address Generation Units) are primarily used to resolve indirect mode of
memory addressing.
2. The AGUs work at a speed of
a) equal to that of processor
b) twice the processor
c) thrice the processor
d) none
View Answer
Answer: b
Explanation: The AGUs run at twice the processor speed.
3. Pentium 4 consists of
a) 4 ALUs
b) 4 AGUs
c) 2 ALUs and 2 AGUs
d) 4 ALUs and 4 AGUs
View Answer
Answer: c
Explanation: Pentium 4 consists of 2 ALUs and 2 AGUs.
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4. The number of instructions that can be executed per clock cycle by the ALU or AGU is
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: b
Explanation: As the speed of the units, ALU and AGU are doubled, which means that twice the
number of instructions being executed per clock cycle.
5. The paging mechanism of IA-32 architecture has an extension as
a) page memory extension
b) page size extension
c) page address extension and page size extension
d) page memory extension and page size extension
View Answer
Answer: c
Explanation: IA-32 architecture’s paging mechanism includes an extension that support
1. Page address extension to address space greater than 4GB.
2. Page size extension to map linear address to physical address in 4MB.
6. The linear address space is mapped into the processors physical address space either directly
or through paging by
a) flat memory model
b) segmented memory model
c) flat or segmented memory model
d. None of these
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d) none
View Answer
Answer: c
Explanation: With the flat or segmented memory model, linear address space is mapped into the
processors physical address space either directly or through paging.
7. The features of thread in threading process is
a) threads can be bunched together
b) threads are simple and light weight
c) threads are independent
d) all of the mentioned
View Answer
Answer: d
Explanation: Threads may be bunched together in a process. Threads are independent, simple in
structure and are lightweight in the sense that they may enhance the speed of operation of an
overall process.
8. The process in which multiple threads correspond to the tracking of each individual object is
known as
a) multiple thread system
b) multi thread parallelism
c) thread level parallelism
d) multi level parallelism
View Answer
Answer: c
Explanation: The mutiple threads correspond to the tracking of each individual object. This kind of
parallelism is known as thread level parallelism(TLP).
9. Which of the following is not a type of context switching?
a) time-slice multithreading
b) on chip multiprocessing
c) hyperthreading
d) none
View Answer
Answer: d
Explanation: A single processor can execute multiple threads by switching between them. The
scheme of context switching may be several types. They are
1. Time-slice multithreading
2. On chip multiprocessing
3. Hyperthreading.
10. The thread level parallelism is a process of
a) saving the context of currently executing process
b) flushing the CPU of the same process
c) loading the context of new next process
d) all of the mentioned
View Answer
Answer: d
Explanation: The thread level parallelism is a process of
1. Saving the context of currently executing process.
d. None of these
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2. Flushing the CPU of the same process.
3. Loading the context of new next process is called a context switch.
1. Which of the following is a resource sharing strategy that had been investigated by the
developers?
a) partitioned resources
b) threshold sharing
c) full sharing
d) all of the mentioned
View Answer
Answer: d
Explanation: Several resource sharing strategies have been investigated by the developers. Some
of these are
1. Partitioned resources
2. Threshold sharing
3. Full sharing.
2. The feature of hyperthreading is
a) simultaneous multithreading
b) switching is not required
c) effective use of processor resources
d) all of the mentioned
View Answer
Answer: d
Explanation: Hyperthreading used the concept of simultaneous multithreading, where multiple
threads can be executed on a single processor without switching.
3. Each logical processor maintains a set of architecture state which consists of
a) general purpose registers
b) machine state register
c) advanced programmed interrupt controller
d) all of the mentioned
View Answer
Answer: d
Explanation: Each logical processor maintains a set of architecture state which consists of
1. Registers including the general purpose registers
2. The control register
3. Advanced programmed interrupt controller
4. Machine state register.
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4. A logical processor may be temporarily stalled for
a) including servicing cache misses
b) handling branch mispredictions
c) waiting for results of previous instructions
d) all of the mentioned
View Answer
Answer: d
Explanation: A logical processor may be temporarily stalled for a variety of reasons like including
d. None of these
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servicing cache misses, handling branch mispredictions and waiting for results of previous
instructions.
5. The hyperthreading technology automatically involves the
a) decrease of die area
b) increase of die area
c) decrease of die area to half
d) none
View Answer
Answer: b
Explanation: The hyperthreading technology automatically involves the increase of die area.
6. The instruction that is used when either of the logical processors is idle is
a) HOLD
b) HLDA
c) HALT
d) NONE
View Answer
Answer: c
Explanation: An optimization may require the use of HALT instruction, when either of the two
logical processors is idle.
7. The mode that is available when there is only one software thread to execute is
a) single task mode
b) multi task mode
c) single task and multi task mode
d) dual task mode
View Answer
Answer: c
Explanation: When there is only one software thread to execute, there are two modes namely
single task mode and multi task mode.
8. The HALT instruction is a privileged instruction that can be only used by
a) execution unit
b) operating system
c) control unit
d) memory unit
View Answer
Answer: b
Explanation: The HALT instruction is a privileged instruction that can be only used by operating
system.
9. When the operating system uses HALT instruction on a processor which supports
multithreading, the operation moves from
a) Single task to multi task mode
b) ST1 to ST0
c) Multi task to single task mode
d) None
View Answer
d. None of these
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Answer: c
Explanation: When the operating system uses HALT instruction on a processor which supports
multithreading, the operation moves from multi tasking mode to single tasking mode.
10. The Xeon TM processor on which hyperthreading technology was first implemented consists
of
a) one logical processor per physical processor
b) two logical processor per physical processor
c) three logical processor per physical processor
d) zero logical processor per physical processor
View Answer
Answer: b
Explanation: The Xeon TM processor on which hyperthreading technology was first implemented
consists of two logical processor per physical processor.
1. The MMX instructions support only
a) character data type
b) float data type
c) integer data type
d) string data type
View Answer
Answer: c
Explanation: The MMX instructions support only integer data type.
2. For single precision floating point numbers, the SSE instructions are
a) MMX instructions
b) SIMD instructions
c) Floating point executions
d) None
View Answer
Answer: b
Explanation: The SSE instructions are SIMD(Single Instruction Multiple Data Stream) instructions
for single precision floating point numbers.
3. The feature of SSE among the following is
a) operate on four 32-bit floating points
b) register size is of 128 bits
c) no switching from one mode to other
d) all of the mentioned
View Answer
Answer: d
Explanation: The features of SSE(Streaming SIMD extensions) are
1. SSE instructions are SIMD instructions for single precision floating point numbers.
2. They operate on four 32-bit floating points.
3. The register size is of 128 bits
4. No necessity to switch from one mode to other.
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4. The new instructions that are added in SSE for floating point operations are of
a) 72
b) 50
d. None of these
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c) 25
d) 8
View Answer
Answer: b
Explanation: The new instructions that are added in SSE for floating point operations are 50.
5. The SSE instructions can operate on
a) packed data
b) unpacked data
c) dynamic data
d) all of the mentioned
View Answer
Answer: a
Explanation: The SSE instructions can operate on packed data or scalar data.
6. Which of the following group is not of SSE instructions?
a) jump or branch group of instruction
b) logic and comparison group of instruction
c) shuffle instructions
d) all of the mentioned
View Answer
Answer: d
Explanation: The SSE instructions can be grouped to many types. Some of them are
1. Data transfer instructions
2. Arithmetic, logic and comparison group of instruction
3. shuffle instructions
4. Cacheability instructions.
7. Which of the following is true about SSE2 instructions in Pentium III and Pentium 4?
a) SSE increases the accuracy of double precision floating point operations
b) SSE supports new formats of packed data
c) SSE increases the speed of manipulation of SIMD integer operations
d) All of the mentioned
View Answer
Answer: d
Explanation: The SSE new instruction set increases the accuracy of double precision floating point
operations, supports new formats of packed data.
8. The data type that the SSE2 instructions doesn’t support is
a) single precision floating points
b) double precision floating points
c) single and double precision floating points
d) none of the mentioned
View Answer
Answer: d
Explanation: The SSE2 instructions support new data types such as double precision floating
points along with single precision floating points.
9. The additional instructions of SSE3 over SSE2 contains
a) video encoding
b) complex arithmetic operation
d. None of these
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c) thread synchronization
d) all of the mentioned
View Answer
Answer: d
Explanation: The SSE3 contains 13 additional SIMD instructions over SSE2. These instructions
comprise five types.
i. floating point to integer conversion
ii. complex arithmetic operation
iii. video encoding
iv. SIMD floating point operations using array of structures format
v. thread synchronization.
10. The unit that may acts as an interface between the Front end and the Out of order execution
engine in the pipeline flow is
a) micro-op queue
b) micro-op stack
c) micro-ops
d) none
View Answer
Answer: a
Explanation: The micro-op queue acts as an interface between the Front end and the Out of order
execution engine in the pipeline flow.
11. The verification of the logic using formal mathematical tools is called
a) arithmetic verification
b) formal verification
c) mathematical verification
d) logical verification
View Answer
Answer: b
Explanation: The verification of the logic using formal mathematical tools is called formal
verification.
12. The formal verification is important for
a) developing the tools
b) developing the methodologies
c) to detect the bugs in design
d) all of the mentioned
View Answer
Answer: d
Explanation: The formal verification is important to develop the tools and methodologies to handle
a large number of proofs using which it will be possible to detect the bugs in the design.
13. By using the techniques of formal verification, one can detect the logical bugs of
a) more than 50
b) less than 50
c) more than 100
d) less than 100
View Answer
d. None of these
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Answer: c
Explanation: By using the techniques of formal verification, one can detect more than 100 logical
bugs.
14. The modern processors are designed to achieve
a) high speed
b) operate at low operating voltage
c) uses cooling technology
d) all of the mentioned
View Answer
Answer: d
Explanation: The modern processors are designed to operate at a very high speed and even with
the lower operating voltages, the power consumption is high enough to require expensive cooling
technology.
1. The disadvantage of CISC design processors is
a) low burden on compiler developers
b) wide availability of existing software
c) complex in nature
d) none
View Answer
Answer: c
Explanation: Some computers are used in preference to CISC design due to its low burden on
compiler developers and wide availability of existing software. But they are complex in nature.
2. The RISC architecture is preferred to CISC because RISC architecture has
a) simplicity
b) efficiency
c) high speed
d) all of the mentioned
View Answer
Answer: d
Explanation: The RISC architecture is preferred to CISC because RISC architecture is simple,
highly efficient and the processors using RISC architecture have high speed.
3. The feature of RISC that is not present in CISC is
a) branch prediction
b) pipelining
c) branch prediction and pipelining
d) none
View Answer
Answer: c
Explanation: A RISC core allows performance enhancing features, such as branch prediction and
pipelining. Traditionally, these have only been possible in RISC designs.
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4. The feature of hybrid CISC-RISC architecture is
a) consume a lot of power
b) not applicable to mobile applications
c) processed by RISC core
d. None of these
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d) all of the mentioned
View Answer
Answer: d
Explanation: The CISC-RISC hybrids continue to consume a lot of power and are not best
candidates for mobile and embedded applications.
5. Which of the following is an application of RISC architecture by adding more instructions?
a) multimedia applications
b) telecommunication encoding
c) image conversion
d) all of the mentioned
View Answer
Answer: d
Explanation: By adding more instructions to the RISC architecture, some applications can be run
much faster like multimedia applications, telecommunication encoding/decoding, image
conversion and video processing.
6. Which of the following processor belongs to hybrid RISC-CISC architecture?
a) Intel Pentium III
b) Intel Itanium 64
c) AMD’s X86-64
d) All of the mentioned
View Answer
Answer: d
Explanation: The processors, Intel Pentium III, Intel Itanium 64 and AMD’s X86-64 consists of
hybrid RISC-CISC architecture.
7. In order to implement complex instructions, CISC architectures use
a) macroprogramming
b) hardwire
c) microprogramming
d) none
View Answer
Answer: c
Explanation: In order to implement complex instructions, CISC architectures use
microprogramming.
8. The advantage of RISC processors is
a) can operate at high clock frequency
b) shorter design cycle
c) simple and fast
d) all of the mentioned
View Answer
Answer: d
Explanation: The advantages of RISC processors are that they can work at high clock frequency,
can be designed, developed and tested more quickly with a high speed.
9. The additional functionality that can be placed on the same chip of RISC is
a) Memory management units
b) Floating point units
c) Memory management and floating point arithmetic units
d. None of these
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d) RAM, ROM
View Answer
Answer: c
Explanation: Several extra functionalities, such as memory management units or floating point
arithmetic units, can also be placed on the same chip of RISC.
10. The number of clockcycles that take to wait until the length of the instruction is known in order
to start decoding is
a) 0
b) 1
c) 2
d) 3
View Answer
Answer: a
Explanation: The loading and decoding the instructions in a RISC processor is simple and fast. It
is not needed to wait until the length of the instruction is known in order to start the decoding.
1. The number of CPIs(Clock Per Instruction) for an instruction of RISC processors is
a) 0
b) 1
c) 2
d) 3
View Answer
Answer: b
Explanation: RISC processors have unity CPI(Clock Per Instruction), which is due to the
optimization of each instruction on the CPU and massive pipelining embedded in a RISC
processor.
2. Which of the following is not true about RISC processors?
a) addressing modes are less
b) pipelining is key for high speed
c) microcoding is required
d) single machine cycle instructions
View Answer
Answer: c
Explanation: Unlike the CISC, in RISC architecture, instruction microcoding is not required.
3. The RISC processors that support variable length instructions are from
a) Intel
b) Motorola
c) AMD
d) Intel and Motorola
View Answer
Answer: d
Explanation: In RISC, each instruction is of the same length, so that it may be fetched in a single
operation. The traditional microprocessors from Intel or Motorola support variable length
instructions.
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4. Which of the following is true about register windowing?
a) chips expose 32 registers to programmer
d. None of these
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b) puts demands on multiplexers
c) puts enormous demands on register ports
d) all of the mentioned
View Answer
Answer: d
Explanation: The register windowing involves a mechanism where the chips expose 32 registers
to the programmer at any one time. It puts enormous demands on multiplexers and register ports
to make any physical register appear to be any logical register.
5. The disadvantage of register windowing is
a) high speed
b) puts demands on multiplexers/register ports
c) consumes less cycles
d) doesn’t handle overflow/underflow
View Answer
Answer: d
Explanation: It is impossible to predict when the register file will overflow or underflow, so
performance is unpredictable. It generates a software fault, which the operating system has to
handle, consuming more cycles.
6. The register window is used to point the number of physical registers is
a) infinite
b) that are currently used
c) finite
d) that are unused
View Answer
Answer: c
Explanation: The register window only helps us to point the number of physical registers is finite.
7. Which of the following is not a stage of pipeline of a RISC processor?
a) read registers and decode the instructions
b) fetch instructions from registers
c) write result into a register
d) access an operand in data memory
View Answer
Answer: b
Explanation: There are 5 stages in pipelining. They are
1. Fetch instructions from memory
2. Read registers and decode the instructions
3. Execute the instructions or calculate an address
4. Access an operand in data memory
5. Write result into a register.
8. When an instruction depends on the results of the previous instructions then
a) error occurs
b) software fault occurs
c) data dependency occurs
d) hardware fault occurs
View Answer
d. None of these
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Answer: c
Explanation: A data dependency occurs when an instruction depends on the results of the previous
instructions.
9. The instructions that instruct the processor to make a decision about the next instruction to be
executed are
a) data dependency instructions
b) branch instructions
c) control transfer instructions
d) none
View Answer
Answer: b
Explanation: The branch instructions are those which instruct the processor to make a decision
about the next instruction to be executed, depending upon whether the condition is satisfied or
not.
10. The reason for which the RISC processor goes to idle state(or stall) is
a) delay in reading information from memory
b) poor instruction set design
c) dependencies between instructions
d) all of the mentioned
View Answer
Answer: d
Explanation: There are a variety of reasons, including delays in reading information from memory,
poor instruction set design, or dependencies between instructions for the RISC processor to
remain idle.
1. The register that may be used as an operand register is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
View Answer
Answer: d
Explanation: In some instructions, the Accumulator and B register are used to store the operands.
2. The register that can be used as a scratch pad is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
View Answer
3. The registers that contain the status information is
a) control registers
b) instruction registers
c) program status word
d) all of the mentioned
View Answer
Answer: c
Explanation: The set of flags of program status word contains the status information and is
considered as one of the special function registers.
d. None of these
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4. Which of the processor’s stack does not contain the top-down data structure?
a) 8086
b) 80286
c) 8051
d) 80386
View Answer
Answer: c
Explanation: The 8051 stack is not a top-down data structure, like other Intel processors.
5. The architecture of 8051 consists of
a) 4 latches
b) 2 timer registers
c) 4 on-chip I/O ports
d) all of the mentioned
View Answer
Answer: d
Explanation: The architecture of 8051 consists of 4 latches and driver pairs are allotted to each of
the four on-chip I/O ports. It contains two 16-bit timer registers.
6. The transmit buffer of serial data buffer is a
a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register
View Answer
Answer: b
Explanation: The transmit buffer of serial data buffer is a parallel-in serial-out register.
7. The receive buffer of serial data buffer is a
a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register
View Answer
Answer: a
Explanation: The serial data register has two buffers. The transmit buffer is a parallel-in serial-out
register and receive buffer is a parallel-in serial-out register.
8. The register that provides control and status information about counters is
a) IP
b) TMOD
c) TSCON
d) PCON
View Answer
Answer: b
Explanation: The registers, TMOD and TCON contain control and status information about
timers/counters.
9. The register that provides control and status information about serial port is
a) IP
d. None of these
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b) IE
c) TSCON
d) PCON and SCON
View Answer
Answer: d
Explanation: The registers, PCON and SCON contain control and status information about serial
port.
10. The device that generates the basic timing clock signal for the operation of the circuit using
crystal oscillator is
a) timing unit
b) timing and control unit
c) oscillator
d) clock generator
View Answer
Answer: c
Explanation: The oscillator circuit generates the basic timing clock signal for the operation of the
circuit using crystal oscillator.
11. The registers that are not accessible by the user are
a) Accumulator and B register
b) IP and IE
c) Instruction registers
d) TMP1 and TMP2
View Answer
Answer: d
Explanation: The arithmetic operations are performed over the operands held by the temporary
registers, TMP1 and TMP2. Users cannot access these temporary registers.
1. Which of the following is an 8-bit register?
a) PSW(Program Status Word)
b) TCON(Timer Control Register)
c) Accumulator
d) All of the mentioned
View Answer
Answer: d
Explanation: The registers, PSW, TCON and Accumulator are 8-bit registers.
2. Which of the following register can be addressed as a byte?
a) P1
b) SCON
c) TMOD
d) TCON
View Answer
Answer: c
Explanation: The registers, TMOD, SP, TH0, TH1, TL0, TL1 are to be addressed as bytes.
3. Which of the following is bit-addressable register?
a) SBUF
b) PCON
c) TMOD
d. None of these
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d) SCON
View Answer
Answer: d
Explanation: The registers, accumulator, PSW, B, P0, P1, P2, P3, IP, IE, TCON and SCON are
all bit-addressable registers.
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4. The higher and lower bytes of a 16-bit register DPTR are represented respectively as
a) LDPTR and HDPTR
b) DPTRL and DPTRH
c) DPH and DPL
d) HDP and LDP
View Answer
Answer: c
Explanation: The registers, DPH and DPL are the higher and lower bytes of a 16-bit register DPTR.
5. The register that is used for accessing external data memory is
a) DPH
b) DPL
c) DPTR
d) NONE
View Answer
Answer: c
Explanation: The Data Pointer(DPTR) is used for accessing external data memory which means
that it includes both DPH and DPL.
6. Among the four groups of register banks, the number of groups that can be accessed at a time
is
a) 1
b) 2
c) 3
d) all the four
View Answer
Answer: a
Explanation: At a time, only one of the four register banks can be accessed.
7. The number of 8-bit registers that a register bank contain is
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: d
Explanation: The 32, 8-bit registers are divided into four groups of 8 registers each, called register
banks.
8. If RS1=1, RS0=0, then the register bank selected is
a) register bank 0
b) register bank 1
c) register bank 2
d. None of these
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d) register bank 3
View Answer
Answer: c
Explanation: If RS1=1, RS0=0, then the register bank selected is register bank 2.
9. If RS1=1, RS0=1, then the register bank selected is
a) register bank 0
b) register bank 1
c) register bank 2
d) register bank 3
View Answer
Answer: d
Explanation: If RS1=1, RS0=1, then the register bank selected is register bank 3. If RS1=0,
RS0=0, then selected bank is register bank 0.
10. The PCON register consists of
a) power mode bit
b) power idle bit
c) power ideal bit
d) power down bit and idle bit
View Answer
Answer: d
Explanation: The power control register, PCON consists of power down bit and idle bit which
activate the power down mode and idle mode in 80C51BH.
11. The on-chip oscillator is stopped in
a) power mode
b) power down mode
c) idle mode
d) ideal mode
View Answer
Answer: b
Explanation: In power down mode, the on-chip oscillator is stopped.
12. In idle mode, the device that is disabled is
a) serial port
b) timer block
c) clock to CPU
d) all of the mentioned
View Answer
Answer: c
Explanation: In idle mode, the oscillator continues to run and the interrupt, serial port and timer
blocks are active but the clock to the CPU is disabled.
13. The only way to terminate the power down mode is to
a) CLEAR
b) RESET
c) HOLD
d) HLT
View Answer
d. None of these
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Answer: b
Explanation: The only way to terminate the power down mode is hardware reset. The reset
redefines all the SFRs but the RAM contents are left unchanged.
14. The idle mode can be terminated by
a) PRESET
b) CLEAR
c) Interrupt
d) Interrupt or reset
View Answer
Answer: d
Explanation: The idle mode can be terminated with a hardware interrupt or hardware reset signal.
on “Interrupt and Stack of 8051 -1”.
1. Which of the following is an external interrupt?
a) INT0(active low)
b) INT2(active low)
c) Timer0 interrupt
d) Timer1 interrupt
View Answer
Answer: a
Explanation: INT0(active low) and INT1(active low) are two external interrupt inputs provided by
8051.
2. The interrupts, INT0(active low) and INT1(active low) are processed internally by flags
a) IE0 and IE1
b) IE0 and IF1
c) IF0 and IE1
d) IF0 and IF1
View Answer
Answer: a
Explanation: The interrupts, INT0(active low) and INT1(active low) are processed internally by the
flags IE0 and IE1.
3. The flags IE0 and IE1, are automatically cleared after the control is transferred to respective
vector if the interrupt is
a) level-sensitive
b) edge-sensitive
c) in serial port
d) in parallel port
View Answer
Answer: b
Explanation: If the interrupts are programmed as edge sensitive, the flags IE0 and IE1 are
automatically cleared after the control is transferred to respective vector.
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4. If the external interrupt sources control the flags IE0 and IE1, then the interrupt programmed is
a) level-sensitive
b) edge-sensitive
d. None of these
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c) in serial port
d) in parallel port
View Answer
Answer: a
Explanation: If the interrupts are programmed as level sensitive, then the flags IE0 and IE1 are
controlled by external interrupt sources themselves.
5. The pulses at T0 or T1 pin are counted in
a) timer mode
b) counter mode
c) idle mode
d) power down mode
View Answer
Answer: b
Explanation: In counter mode, the pulses are counted at T0 or T1 pin.
6. In timer mode, the oscillator clock is divided by a prescalar
a) (1/8)
b) (1/4)
c) (1/16)
d) (1/32)
View Answer
Answer: d
Explanation: In timer mode, the oscillator clock is divided by a prescalar (1/32) and then given to
the timer.
7. The serial port interrupt is generated if
a) RI is set
b) RI and TI are set
c) Either RI or TI is set
d) RI and TI are reset
View Answer
Answer: c
Explanation: The serial port interrupt is generated if atleast one of the two bits, RI and TI is set.
8. In serial port interrupt, after the control is transferred to the interrupt service routine, the flag
that is cleared is
a) RI
b) TI
c) RI and TI
d) None
View Answer
Answer: d
Explanation: In serial port interrupt, after the control is transferred to the interrupt service routine,
neither of the flags are cleared.
9. The atleast number of machine cycles for which the external interrupts that are programmed
level-sensitive should remain high is
a) 1
b) 2
c) 3
d. None of these
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d) 0
View Answer
Answer: b
Explanation: The external interrupts, programmed level-sensitive should remain high for atleast 2
machine cycles.
10. If the external interrupts are programmed edge sensitive, then they should remain high for
atleast
a) 0 machine cycle
b) 2 machine cycles
c) 1 machine cycle
d) 3 machine cycles
View Answer
Answer: c
Explanation: If the external interrupts are programmed edge sensitive, then they should remain
high for atleast one machine cycle and low for atleast one machine cycle, for being sensed.
1. The timer generates an interrupt, if the count value reaches to
a) 00FFH
b) FF00H
c) 0FFFH
d) FFFFH
View Answer
Answer: d
Explanation: The timer is an up-counter and generates an interrupt when the count has reached
FFFFH.
2. The external interrupt that has the lowest priority among the following is
a) TF0
b) TF1
c) IE1
d) NONE
View Answer
Answer: c
Explanation: The order of given interrupts from high to low priority is TF0, IE1 and TF1.
3. Among the five interrupts generated by 8051, the lowest priority is given to the interrupt
a) IE0
b) TF1
c) TF0
d) RI
View Answer
Answer: d
Explanation: The interrupt, RI=TI (serial port) is given the lowest priority among all the interrupts.
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4. Among the five interrupts generated by 8051, the highest priority is given to the interrupt
a) IE0
b) TF1
c) TF0
d. None of these
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d) IE1
View Answer
Answer: a
Explanation: The interrupt, IE0(External INT0) is given the highest priority among all the interrupts.
5. All the interrupts are enabled using a special function register called
a) interrupt priority register
b) interrupt register
c) interrupt function register
d) interrupt enable register
View Answer
Answer: d
Explanation: All the interrupts are enabled using a special function register called interrupt enable
register (IE) and their priorities are programmed using another special function register called
interrupt priority register(IP).
6. The number of bytes stored on the stack during one operation of PUSH or POP is
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: a
Explanation: As 8051 stack operations are 8-bit wide i.e. in an operation using PUSH or POP
instruction, one byte of data is stored on a stack or retrieved from the stack. For implementing 16-
bit operations, two 8-bit operations are cascaded.
7. The step involved in PUSH operation is
a) increment stack by 2 and store 8-bit content to address pointed to by SP
b) decrement stack by 1 and store 16-bit content to address pointed to by SP
c) increment stack by 1 and store 8-bit content to address pointed to by SP
d) store 8-bit content to address pointed to by SP and then increment stack by 1
View Answer
Answer: c
Explanation: The PUSH instruction follows two steps.
1. Increment stack by 1
2. Store 8-bit content of the 8-bit address specified in the instruction to the address pointed to by
SP.
8. The step involved in POP operation is
a) decrement stack by 2 and store 8-bit content to address pointed to by SP
b) store 16-bit content to address pointed to by SP and decrement stack by 1
c) decrement stack by 1 and store content of top of stack to address pointed to by SP
d) store content of top of stack to address pointed to by SP and then decrement stack by 1
View Answer
Answer: d
Explanation: The POP instruction follows two steps.
1. Store the contents of top of stack pointed to by SP register to the 8-bit memory specified in the
instruction.
2. Decrement stack by 1.
d. None of these
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9. The 8051 stack is
a) auto-decrement during PUSH operations
b) auto-increment during POP operations
c) auto-decrement during POP operations
d) auto-increment during PUSH operations
View Answer
Answer: d
Explanation: The 8051 stack is opposite to that in 8085 or 8086 i.e. in 8085 it is auto-decrement
while in 8051 it is auto-increment during PUSH operations.
10. After reset, the stack pointer(SP) is initialized to the address of
a) internal ROM
b) internal RAM
c) external ROM
d) external RAM
View Answer
Answer: b
Explanation: The stack pointer(SP) is an 8-bit register and is initialized to internal RAM address
07H after reset.
1. Which of the following is not an addressing mode of 8051?
a) register instructions
b) register specific instructions
c) indexed addressing
d) none
View Answer
Answer: d
Explanation: The six addressing modes of 8051 are
1. Direct addressing
2. Indirect addressing
3. Register instructions
4. Register specific(Register Implicit) instructions
5. Immediate mode
6. Indexed addressing.
2. The symbol, ‘addr 16’ represents the 16-bit address which is used by the instructions to specify
the
a) destination address of CALL
b) source address of JUMP
c) destination address of call or jump
d) source address of call or jump
View Answer
Answer: c
Explanation: The symbol, ‘addr 16’ represents the 16-bit destination address which is used by the
LCALL or LJMP instruction to specify the call or jump destination address, within 64 Kbytes
program memory.
3. The storage of addresses that can be directly accessed is
a) external data RAM
b) internal data ROM
d. None of these
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c) internal data RAM and SFRS
d) external data ROM and SFRS
View Answer
Answer: c
Explanation: Only internal data RAM and SFRS can be directly addressed in direct addressing
mode.
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4. The address register for storing the 16-bit addresses can only be
a) stack pointer
b) data pointer
c) instruction register
d) accumulator
View Answer
Answer: b
Explanation: The address register for storing the 16-bit addresses can only be data pointer.
5. The address register for storing the 8-bit addresses can be
a) R0 of the selected bank of register
b) R1 of the selected bank of register
c) Stack pointer
d) All of the mentioned
View Answer
Answer: d
Explanation: The registers R0 and R1 of the selected bank of registers or stack pointer can be
used as address registers for storing the 8-bit addresses.
6. The instruction, ADD A, R7 is an example of
a) register instructions
b) register specific instructions
c) indexed addressing
d) none
View Answer
Answer: a
Explanation: In register instructions addressing mode, operands are stored in the registers R0-R7
of the selected register bank. One of these registers is specified in the instruction.
7. The addressing mode, in which the instructions has no source and destination operands is
a) register instructions
b) register specific instructions
c) direct addressing
d) indirect addressing
View Answer
Answer: b
Explanation: In register specific instructions addressing mode, the instructions don’t have source
and destination operands. Some of the instructions always operate only on a specific register.
8. The instruction, RLA performs
a) rotation of address register to left
b) rotation of accumulator to left
c) rotation of address register to right
d. None of these
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d) rotation of accumulator to right
View Answer
Answer: b
Explanation: The instruction, RLA rotates accumulator left.
9. The instruction, ADD A, #100 performs
a) 100(decimal) is added to contents of address register
b) 100(decimal) is subtracted from the accumulator
c) 100(decimal) is added to contents of an accumulator
d) none
View Answer
Answer: c
Explanation: Immediate data 100(decimal) is added to the contents of the accumulator.
10. In which of these addressing modes, a constant is specified in the instruction, after the opcode
byte?
a) register instructions
b) register specific instructions
c) direct addressing
d) immediate mode
View Answer
Answer: d
Explanation: In immediate mode, an immediate data, i.e. a constant is specified in the instruction,
after the opcode byte.
11. The only memory which can be accessed using indexed addressing mode is
a) RAM
b) ROM
c) Main memory
d) Program memory
View Answer
Answer: d
Explanation: Only program memory can be accessed using the indexed addressing mode.
12. The data address of look-up table is found by adding the contents of
a) accumulator with that of program counter
b) accumulator with that of program counter or data pointer
c) data register with that of program counter or accumulator
d) data register with that of program counter or data pointer
View Answer
Answer: b
Explanation: The look-up table data address is found out by adding the contents of register
accumulator with that of the program counter or data pointer.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “8051
Instruction Set -1”.
1. Which of the following is not an instruction of 8051 instructions?
a) arithmetic instructions
b) boolean instructions
c) logical instructions
d. None of these
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d) none
View Answer
Answer: d
Explanation: The 8051 instructions are categorized as
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Boolean instructions
5. Control transfer instructions.
2. The operations performed by data transfer instructions are on
a) bit data
b) byte data
c) 16-bit data
d) all of the mentioned
View Answer
Answer: d
Explanation: The data transfer instructions implement a bit, byte, 16-bit data transfer operations
between the SRC(source) and DST(destination) operands.
3. Which of the following is true while executing data transfer instructions?
a) program counter is not accessible
b) restricted bit-transfer operations are allowed
c) both operands can be direct/indirect register operands
d) all of the mentioned
View Answer
Answer: c
Explanation: In data transfer instructions,
1. Program counter is not accessible.
2. Restricted bit-transfer operations are allowed.
3. Both operands can be direct/indirect register operands.
4. BOth operands can be internal direct data memory operands.
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4. The logical instruction that affects the carry flag during its execution is
a) XRL A;
b) ANL A;
c) ORL A;
d) RLC A;
View Answer
Answer: d
Explanation: The logical instructions that doesn’t affect the carry flag are, ANL, ORL and XRL. The
logical instructions that affect the carry flag during its execution are RL, RLC, RRC and RR.
5. The instruction that is used to complement or invert the bit of a bit addressable SFR is
a) CLR C
b) CPL C
c) CPL Bit
d) ANL Bit
View Answer
d. None of these
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Answer: c
Explanation: The instruction, CPL Bit is used to complement or invert the bit of a bit addressable
SFR or RAM.
6. The instructions that change the sequence of execution are
a) conditional instructions
b) logical instructions
c) control transfer instructions
d) data transfer instructions
View Answer
Answer: c
Explanation: The control transfer instructions transfer the control of execution or change the
sequence of execution conditionally or unconditionally.
7. The control transfer instructions are divided into
a) explicit and implicit control transfer instructions
b) conditional and unconditional control transfer instructions
c) auto control and self control transfer instructions
d) all of the mentioned
View Answer
Answer: b
Explanation: The control transfer instructions are divided into conditional and unconditional control
transfer instructions.
8. The conditional control transfer instructions check a bit condition which includes any bit of
a) bit addressable RAM
b) bit addressable SFRs
c) content of accumulator
d) all of the mentioned
View Answer
Answer: d
Explanation: The conditional control transfer instructions check a bit condition which includes any
bit of bit addressable RAM or bit addressable SFRs or content of accumulator for transferring the
control to the specified jump location.
9. All conditional jumps are
a) absolute jumps
b) long jumps
c) short jumps
d) none
View Answer
Answer: c
Explanation: All conditional jumps are short jumps.
10. The first byte of a short jump instruction represents
a) opcode byte
b) relative address
c) opcode field
d) none
View Answer
d. None of these
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Answer: a
Explanation: The short jump instruction has two byte instruction. The first byte represents opcode
byte and second byte represents an 8-bit relative address.
11. In logical instructions, the immediate data can be an operand for
a) increment operation
b) decrement operation
c) single operand instruction
d) none
View Answer
Answer: d
Explanation: In logical instructions, the immediate data can’t be an operand for
increment/decrement or any other single operand instruction
1. If the most significant bit of relative address byte is 1, then the short jump instruction is
a) forward jump
b) back jump
c) either forward or back jump
d) none
View Answer
Answer: b
Explanation: If the most significant bit of relative address byte is 1, then the short jump instruction
is back jump, else it is considered as forward jump.
2. The first byte of an absolute jump instruction consists of
a) 3 LSBs of opcode and 5 MSBs of 11-bit address
b) 5 MSBs of opcode and 3 LSBs of 11-bit address
c) 6 MSBs of opcode and 1 LSB of 11-bit address
d) 5 LSBs of opcode and 3 MSBs of 11-bit address
View Answer
Answer: d
Explanation: The first byte of an absolute jump instruction consists of 5 LSBs of opcode and 3
MSBs of 11-bit address. The next byte carries the least significant 8 bits of the 11-bit address.
3. The third byte of the long jump instruction is
a) opcode
b) 5 LSBs of opcode
c) higher byte of jump location or subroutine
d) lower byte of jump location or subroutine
View Answer
Answer: c
Explanation: The third byte of the long jump instruction is a higher byte of jump location or
subroutine.
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4. The absolute jump instruction is intended mainly for a jump within a memory space of
a) 2 bytes
b) 2 Kbytes
c) 2 Mbytes
d) none
View Answer
d. None of these
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Answer: b
Explanation: The absolute jump instruction is intended mainly for a jump within a memory space
of 2 Kbytes.
5. The LJMP instruction is very useful in programming in the external code memory space of
a) 32 MB
b) 64 MB
c) 32 KB
d) 64 KB
View Answer
Answer: d
Explanation: The LJMP instruction is very useful in programming in the external code memory
space of 64 KB.
6. Which of the following is not an unconditional control transfer instruction?
a) JMP
b) RET
c) JNC
d) CALL
View Answer
Answer: c
Explanation: The instructions, JMP, RET, RETI, CALL are the unconditional control transfer
instructions.
7. The conditional control transfer instructions use
a) status flags
b) bits of bit addressable RAM
c) SFRs termed bit
d) all of the mentioned
View Answer
Answer: d
Explanation: The conditional control transfer instructions use status flags or bits of bit addressable
RAM or SFRs termed bit.
8. Which of the following is not a conditional control transfer instruction?
a) JC
b) JBC
c) JNC
d) NONE
View Answer
Answer: d
Explanation: The instructions, JC, JBC, JNC, JB and JNB are the conditional control transfer
instructions.
9. The mnemonic used to perform a subtraction of source with an 8-bit data and jumps to specified
relative address if subtraction is non-zero is
a) DJNZ
b) CJNE
c) JZ
d) JNC
View Answer
d. None of these
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Answer: b
Explanation: The CJNE instruction perform a subtraction of source with an 8-bit data and jumps
to specified relative address only if the result of the subtraction is non-zero, else continues to the
next instruction.
10. The mnemonic, JNB is used to jump to the specified relative address only if
a) specified bit=1
b) specified bit=0
c) specified bit is non-recursive
d) none
View Answer
Answer: a
Explanation: The mnemonic, JNB is used to jump to the specified relative address only if specified
bit=1, else continues to the next instruction.
11. The type of operand that is not allowed to use in boolean instructions of 8051 is
a) direct register operands
b) indirect register operands
c) immediate bit
d) none
View Answer
Answer: c
Explanation: In boolean instructions, the immediate bit is not allowed as an operand.
12. In boolean instructions, the flag that is the only allowed destination operand for two operand
instructions is
a) overflow flag
b) underflow flag
c) auxiliary flag
d) carry flag
View Answer
Answer: d
Explanation: Carry flag(C) is the only allowed destination operand for two operand instructions in
boolean instructions
1. Which of the following is not one of the SFR addresses of the ports of 8051?
a) 80H
b) 90H
c) A0H
d) NONE
View Answer
Answer: d
Explanation: The SFR addresses of the ports P0, P1, P2 and P3 are 80H, 90H, A0H and B0H
respectively.
2. Each port line of a port can individually source a current of upto
a) 0.2 mA
b) 0.25 mA
c) 0.5 mA
d. None of these
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d) 0.75 mA
View Answer
Answer: c
Explanation: Each port line of a port can individually source a current of upto 0.5 mA.
3. Each port line of a port can individually sink a current of upto
a) 2 mA
b) 8 mA
c) 5 mA
d) 1 mA
View Answer
Answer: b
Explanation: Each port line of a port can individually sink a current of upto 8 mA.
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4. The number of TTL inputs that can be sinked by the port 0 when a logic 0 is sent to a port line
as an output port is
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: d
Explanation: When a logic 0 is sent to a port line as an output port, it can sink 8 LS TTL inputs.
Port 0 is used as data bus during external interfacing whenever required.
5. The open drain bidirectional (input or output) port with internal pullups is
a) Port 0
b) Port 1
c) Port 2
d) Port 3
View Answer
Answer: a
Explanation: Port 0 is an open drain bidirectional (input or output) port with internal pullups. Port
1, Port 2, Port 3 are 8-bit bidirectional ports.
6. The port that can source or sink 4 LS TTL inputs when being used as an output port on each of
its line is
a) Port 1
b) Port 2
c) Port 3
d) all of the mentioned
View Answer
Answer: d
Explanation: The ports P1, P2 and P3 can source or sink 4 LS TTL inputs when being used as an
output port on each of its line.
7. The port that will source a current of 500 micro amperes when being used as input ports is
a) 0.5 mA
b) 0.25 mA
c) 250 micro amperes
d. None of these
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d) 500 micro amperes
View Answer
Answer: d
Explanation: Port 3 pins which are externally pulled low when being used as input pins will source
current of 500 micro amperes.
8. If the EA(active low) signal is grounded then the execution
a) directly start from main memory
b) directly start from 16 bit address in main memory
c) directly start from 16 bit address in program memory
d) directly start from RAM
View Answer
Answer: c
Explanation: For interfacing external program memory, EA(active low) pin must be grounded. If
the EA(active low) signal is grounded then the execution will start directly from the 16-bit address
0000H in external program memory.
9. When the port lines of a port are to be used as input lines then the value that must be written to
the port address is
a) F0H
b) 0FH
c) FFH
d) 00H
View Answer
Answer: c
Explanation: When the port lines of a port are to be used as input lines then ‘FF’H must be written
to the port address.
10. Port 1 lines are used during programming of
a) external EPROM and EEPROM
b) external ROM and RAM
c) internal ROM and RAM
d) internal EPROM and EEPROM
View Answer
Answer: d
Explanation: Port 1 lines are used as lower byte of 16-bit address bus during programming of
internal EPROM or EEPROM.
11. The configuration in which each LED receives operating current of 8 mA from power supply
while the port lines sink the current on each port line is
a) common port configuration
b) common anode configuration
c) common cathode configuration
d) none of the mentioned
View Answer
Answer: b
Explanation: The common anode configuration is preferred to that of other configurations as in
common anode configuration, each LED receives operating current of 8 mA from power supply
while the port lines sink the current on each port line.
d. None of these
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1. If EA(active low) signal =1, then the execution starts from
a) internal EPROM
b) flash RAM
c) internal EPROM or flash RAM
d) none
View Answer
Answer: c
Explanation: If EA(active low) signal =1, then the execution starts from an internal EPROM or flash
RAM address 000H, can continue upto FFFH address and then for higher addresses it will go into
external memory.
2. The pin that is grounded for interfacing external EPROM is
a) EA(active low)
b) PSEN(active low)
c) OE(active low)
d) All of the mentioned
View Answer
Answer: a
Explanation: The EA(active low) pin is grounded for interfacing external EPROM. The
PSEN(active low) is used for interfacing EPROM i.e. it acts as an OE(active low) input to EPROM.
3. The step that is involved in the procedure of memory interfacing with 8051 is
a) data bus is connected to data lines of memory chips
b) PSEN(active low) is connected to OE(active low) of EPROM chips
c) writing address map of memory chip in bit form
d) all of the mentioned
View Answer
Answer: d
Explanation: The procedure of memory interfacing with 8051 includes, data bus connection to data
lines of memory chips, PSEN(active low) connected to OE(active low) of EPROM chips and writing
address map of memory chip in bit form.
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4. The device that is used for deriving chip select signals is
a) Logic gates
b) Multiplexers
c) PLAs and EPROMs
d) All of the mentioned
View Answer
Answer: d
Explanation: The logic gates and multiplexers are most commonly used for deriving chip select
signals. The advanced circuits like PLAs and EPROMs are also used for deriving chip select
signals.
5. For deriving chip selects of isolated memory or IO devices, the gates that are traditionally used
are
a) NOR and NAND
b) NAND and NOT
c) NOT and NOR
d. None of these
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d) AND, OR and NOT
View Answer
Answer: b
Explanation: For deriving chip selects of isolated memory or IO devices, the NAND and NOT gates
are traditionally used.
6. The current that is required for a LED for an appropriate glow is
a) 6-8 mA
b) 4-6 mA
c) 8-10 mA
d) 10-12 mA
View Answer
Answer: c
Explanation: For appropriate glow, a LED typically requires 8-10 mA with around 1.6 Volts.
7. The maximum current that can be sinked totally by all the ports of 8051 is
a) 61 mA
b) 81 mA
c) 91 mA
d) 71 mA
View Answer
Answer: d
Explanation: All the ports together (4 ports) should not be made to sink more than 71 mA.
8. The number of LEDs that can be connected to a port of 8051, if all are expected to glow
simultaneously is
a) 6
b) 8
c) 10
d) 12
View Answer
Answer: b
Explanation: If 8 LEDs are connected to a port of 8051, and if all are expected to glow
simultaneously, the total current sinked by the 8051 port will be 8×8=64 mA (since min voltage for
an LED to glow=8 mA) which is less than the maximum 71 mA.
9. Which is true in interfacing 7 segment code display?
a) transmitted by second port
b) display is selected by third port
c) display is selected by second port
d) none of the mentioned
View Answer
Answer: c
Explanation: The 7-segment code of a digit is transmitted by the first port and the display is
selected by second port. As soon as the display is selected by the second port, the digit starts
glowing on that display position.
10. After the display is selected by second port, then the digit (LED) glows for a duration of
a) 5 msec
b) 10 msec
c) 2 msec
d. None of these
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d) 6 msec
View Answer
Answer: a
Explanation: The unit(LED) glows for a duration of 5 msec.
11. The number of scans of the complete 8-digit display that can be carried out in one second is
a) 15
b) 25
c) 35
d) 55
View Answer
Answer: b
Explanation: Starting from either right most or left most digit, every digit glows for 5 msec one by
one. Thus one scan of the 8 digit display requires 40 msec. Thus in one second, 25 scans of the
complete 8-digit display can be carried out.
12. To convert its current output into a voltage, the DAC 0808 is connected with
a) Transistor(BJT) externally
b) FET externally
c) OPAMP externally
d) OPAMP internally
View Answer
Answer: c
Explanation: the DAC 0808 is connected with OPAMP externally, to convert its current output into
voltage.
1. The external interrupts of 8051 can be enabled by
a) 4 LSBs of TCON register
b) Interrupt enable
c) priority register
d) all of the mentioned
View Answer
Answer: d
Explanation: The external interrupts namely INT0(active low) and INT1(active low) can be enabled
and programmed using the least significant four bits of TCON register and the Interrupt enable
and priority registers.
2. The bits that control the external interrupts are
a) ET0 and ET1
b) ET1 and ET2
c) EX0 and EX1
d) EX1 and EX2
View Answer
Answer: c
Explanation: The bits, EX0 and EX1 individually control the external interrupts, INT0(active low)
and INT1(active low). If INT0(active low) and INT1(active low) interrupts are to be enabled then
the bits EX0 and EX1 must be set respectively.
3. EA bit is used to
a) enable or disable external interrupts
b) enable or disable internal interrupts
d. None of these
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c) enable or disable all the interrupts
d) none of the mentioned
View Answer
Answer: c
Explanation: Using EA bit, all the interrupts can be enabled or disabled. Using the individual
respective bit, the respective interrupt can be enabled or disabled.
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4. The number of priority levels that each interrupt of 8051 have is
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: b
Explanation: Each interrupts level of 8051 can have two levels of priority namely level 0 and level
1. Level 1 is considered as a higher priority level compared to level 0.
5. The priority level of an interrupt of 8051 for which SI(serial interrupt) interrupt is programmed is
a) level 0
b) level 1
c) level 0 or level 1
d) none
View Answer
Answer: b
Explanation: SI interrupt is programmed for level 1 priority.
6. The interrupt bit that when set works at level 1, and otherwise at level 0 is
a) PT1
b) PT0
c) PX1
d) All of the mentioned
View Answer
Answer: d
Explanation: The bits, PT1, PT0, PX0 and PX1 when set, work at level 1, otherwise at level 0.
7. All the interrupts at level 1 are polled in the second clock cycle of the
a) forth T state
b) fifth T state
c) third T state
d) none
View Answer
Answer: b
Explanation: All the interrupts at level 1 are polled or sensed in the second clock cycle of the fifth
T state or 9th clock cycle out of 12 clock cycles. Then all the interrupts at level 0 are also polled in
the same cycle.
8. The minimum duration of the active low interrupt pulse for being sensed without being lost must
be
a) greater than one machine cycle
b) equal to one machine cycle
d. None of these
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c) greater than 2 machine cycles
d) equal to 2 machine cycles
View Answer
Answer: b
Explanation: The minimum duration of the active low interrupt pulse should be equal to the duration
of one machine cycle for being sensed, else it will be lost.
9. If two interrupts, of higher priority and lower priority occur simultaneously, then the service
provided is for
a) interrupt of lower priority
b) interrupt of higher priority
c) lower & higher priority interrupts
d) none of the mentioned
View Answer
Answer: b
Explanation: If two interrupts, occur simultaneously, then the one with higher priority level and
early polling sequence will receive service. The other one with lower priority may get lost there, as
there is no mechanism for storing the interrupt requests.
10. For an interrupt to be guaranteed served it should have duration of
a) one machine cycle
b) three machine cycles
c) two machine cycles
d) four machine cycles
View Answer
Answer: c
Explanation: For an interrupt to be guaranteed served it should have duration of two machine
cycles.
11. The service to an interrupt will be delayed if it appears during the execution of
a) RETI instruction
b) Instruction that writes to IE register
c) Instruction that writes to IP register
d) All of the mentioned
View Answer
Answer: d
Explanation: The service to an interrupt will be delayed if it appears during the execution of RETI
instruction or the instruction that writes to IE/IP registers.
1. The serial communication is
a) cheaper communication
b) requires less number of conductors
c) slow process of communication
d) all of the mentioned
View Answer
Answer: d
Explanation: The serial communication requires less number of conductors and thus it is cheaper.
It is slow as the bits are transmitted one by one along with start, stop and parity bits.
d. None of these
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2. The serial communication is used for
a) short distance communication
b) long distance communication
c) short and long distance communication
d) communication for a certain range of distance
View Answer
Answer: b
Explanation: Serial communication is more popular for communication over longer distances as it
requires less number of conductors.
3. The mcs 51 architecture supports
a) serial transmission and reception
b) simultaneous transmission and reception
c) transmission and reception of data using serial communication interface
d) all of the mentioned
View Answer
Answer: d
Explanation: The mcs 51 architecture supports simultaneous transmission and reception of binary
data byte by byte i.e. full duplex mode of communication. It supports serial transmission and
reception of data using standard serial communication interface and baud rates.
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4. The number of bits transmitted or received per second is defined as
a) transmission rate
b) reception rate
c) transceiver rate
d) baud rate
View Answer
Answer: d
Explanation: Here, baud rate can be defined as the number of bits transmitted or received per
second.
5. The task of converting the byte into serial form and transmitting it bit by bit along with start, stop
and parity bits is carried out by
a) reception unit
b) serial communication unit
c) transmission unit
d) all of the mentioned
View Answer
Answer: c
Explanation: the serial communication unit consists of transmission unit and reception unit. The
task of converting the byte into serial form and transmitting it bit by bit along with start, stop and
parity bits is carried out by transmission unit.
6. The transmission unit does not require assistance from processor if once a byte for transmission
is written to
a) SCON register
b) SBUF register
c) SFR address
d. None of these
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d) Any of the mentioned
View Answer
Answer: b
Explanation: once a byte for transmission is written to the serial buffer(SBUF) register, the
transmission unit does not require assistance from a processor.
7. The common unit shared by the receiver unit and transmission unit of serial communication unit
is
a) SCON(Serial Port Control) Register
b) SBUF(Serial Buffer) register
c) 8-bit serial data interface
d) All of the mentioned
View Answer
Answer: d
Explanation: The transmission unit and receiver unit both are controlled by using a common
SCON(Serial Port Control) Register. Also both units share a common serial buffer(SBUF) register
which is a common 8-bit serial data interface.
8. During serial reception, the buffer that receives serial bits and converts to a byte is
a) receive buffer 0
b) receive buffer 1
c) receive buffer 2
d) none
View Answer
Answer: b
Explanation: During serial reception, the receive buffer 1 receives serial bits and converts to a
byte, it then transfers the received parallel byte in receive buffer 2.
9. If SM0=1, SM1=0, then the transceiver selected is
a) 8-bit synchronous
b) 9-bit synchronous
c) 8-bit asynchronous
d) 9-bit asynchronous
View Answer
Answer: d
Explanation: If SM0=1, SM1=0, then the 9-bit asynchronous transceiver is selected.
10. If the microcontroller is expected to communicate in a multiprocessor system, then the required
condition is
a) SM0 is set
b) SM1 is set
c) SM2 is set
d) REN is set
View Answer
Answer: c
Explanation: The bit, SM2 is set if the microcontroller is expected to communicate in a
multiprocessor system.
11. In mode 2, the baud rate depends only on
a) SMOD bit
b) SCON bit
d. None of these
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c) Oscillator clock frequency
d) SMOD bit and oscillator clock frequency
View Answer
Answer: d
Explanation: In mode 2, the baud rate depends only on SMOD bit and oscillator clock frequency.
12. The mode that offers the most secured parity enabled data communication at lower baud rates
is
a) mode 2
b) mode 1
c) mode 0
d) all of the mentioned
View Answer
Answer: a
Explanation: The mode 3 offers the most secured parity enabled data communication at lower
baud rates of mode 1
1. The power control register is
a) used for power saving during idle state
b) used for eventual power off to 8051 chip
c) non-bit addressable register
d) all of the mentioned
View Answer
Answer: d
Explanation: The power control register is used for power saving during idle state of the
microcontroller and eventual power off to the microcontroller chip. It has SMOD bit which is used
to double the baud rate.
2. The state of signals in idle mode is
a) ALE is high
b) PSEN is high
c) PSEN(active low) is high
d) ALE and PSEN(active low) are high
View Answer
Answer: d
Explanation: ALE and PSEN(active low) remain high in Idle mode.
3. To come out of idle mode, the external interrupt that is enabled is
a) SI(serial)
b) INT0
c) INT1
d) All of the mentioned
View Answer
Answer: d
Explanation: To come out of idle mode, any external interrupt that is enabled like SI(Serial), INT0
and INT1.
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4. The microcontroller enters into power down mode when
a) SMOD bit of PCON is set
d. None of these
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b) GF1 bit of PCON is set
c) PD bit of PCON is set
d) GF2 bit of PCON is set
View Answer
Answer: c
Explanation: If the PD bit of PCON register is set, it enters power down mode.
5. The clock signal is disabled to all parts of 8051 in
a) normal mode
b) idle mode
c) power down mode
d) addressing mode
View Answer
Answer: c
Explanation: In power down mode, the clock signal to all parts of 8051 chip is disabled.
6. During power down to save battery, the supply voltage can be reduced to a value of
a) 4 volts
b) 2 volts
c) 8 volts
d) 1 volt
View Answer
Answer: b
Explanation: The supply voltage can be reduced to a value of around 2 volts, during power down
to save battery.
7. The signal that only pulls the microcontroller(8051) out of the power down mode is
a) CLEAR
b) LEAVE
c) RESET
d) EXIT
View Answer
Answer: c
Explanation: Only Reset signal can pull 8051 out of the power down mode.
8. The state of signals in power down mode is
a) ALE is high
b) PSEN is low
c) ALE and PSEN(active low) are high
d) ALE and PSEN(active low) are low
View Answer
Answer: d
Explanation: ALE and PSEN(active low) remain low in power down mode of 8051.
9. In power down mode,
a) Port pins maintain their logic levels
b) SFRs maintain their logic levels
c) Clock signal is disabled
d) All of the mentioned
View Answer
d. None of these
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10. The SMOD bit is used to
a) decrease the baud rate by 2
b) increase the baud rate by 4
c) increase the baud rate by 2
d) triple the baud rate
View Answer
Answer: c
Explanation: The SMOD bit is used to double the baud rate
Date-16/06/2021
Subject Name-KCS-403-Microprocessor_CSE-Semester 4
UNIT-1
d. None of these
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1. In 8085 microprocessor, the RST6 instruction transfer programme execution
to following location
a. 0030H
b. 0024H
c. 0048H
d. 0060H
Answer: (a).0030H
HLT opcode means
load data to accumulator
store result in memory
load accumulator with contents of register
end of program
Answer: (d).end of program
d. None of these
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Answer: (c).Set interrupt mask
The ROM programmed during manufacturing process itself is called
MROM
PROM
EPROM
EEPROM
Answer: (a).MROM
A field programmable ROM is called
MROM
PROM
FROM
FPROM
Answer: (b).PROM
Answer: (b).Macro-operations
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The operations executed by two or more control units are referred as
Micro-operations
Macro-operations
Multi-operations
Bi control-operations
Answer: (b).Macro-operations
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Program counter in a digital computer
Counts the numbers of programs run in the machine.
Counts the number of times a subroutine is called.
Counts the number of times the loops are executed.
Points the memory address of the next instruction to be fetched.
Answer: (c).EPROM, USART & PORTS
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Answer: (d).Points the memory address of the next instruction to be fetched.
At the beginning of a fetch cycle, the contents of the program
counter are
incremented by one.
transferred to address bus.
transferred to memory address register.
transferred to memory data register.
Answer: (c).transferred to memory address register.
Which components are NOT found on chip in a microprocessor but may be
found on chip in a micro-controller?
SRAM & USART
EPROM & PORTS
EPROM, USART & PORTS
SRAM, EPROM & PORTS
Answer: (c).EPROM, USART & PORTS
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10. For the purpose of data processing an efficient assembly language
programmer makes use of the general purpose registers rather than
memory. The reason is
a. the set of instructions for data processing with memory is limited
b. data processing becomes easier when register are used
c. more memory related instructions are required
d. data processing with registers takes fewer cycles than that with memory
Answer: (d).data processing with registers takes fewer cycles than that with memory
11. The first machine cycle of an instruction is always
a. A memory read cycle
b. A fetch cycle
c. An I/O read cycle
d. A memory write cycle
Answer: (b).A fetch cycle
12. The output data lines of microprocessor and memories are usually tristated
because
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a. More than one device can transmit information over the data bus by enabling
only one device at a time
b. More than one device can transmit over the data bus at the same time
c. The data line can be multiplexed for both input and output
d. It increases the speed of data transfer over the data bus
Answer: (a).More than one device can transmit information over the data bus by
enabling only one device at a time
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The correct sequence of steps in the instruction cycle of a basic computer is
Fetch, Execute, Decode and Read effective address.
Read effective address,Decode,Fetch and Execute.
Fetch, Decode, Read effective address and ,Execute.
Fetch, Read effective address, Decode and Execute.
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Answer: (c).Fetch, Decode, Read effective address and ,Execute.
The register which holds the information about the nature of results of
arithmetic and logic operations is called as
Accumulator
Condition code register
Flag register
Process status register
Answer: (c).Flag register
15. Consider the following statements:
Arithmetic Logic Unit (ALU)
1.Performs arithmetic operations
2.Performs comparisons.
3.Communicates with I/O devices
4.Keeps watch on the system
Which of these statements are correct?
a. 1, 2, 3 and 4
1, 2 and 3
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d. 3 and 4 only
Answer: (c).1 and 2 only
Ready pin of microprocessor is used
to indicate that microprocessor is ready to receive inputs
to indicate that microprocessor is ready to receive outputs
to introduce wait state
to provide direct memory access
Answer: (c).to introduce wait state
Both the ALU and control section of CPU employ which special purpose
storage location?
Buffers
Decoders
Accumulators
Registers
Answer: (c).Accumulators
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A high on RESET OUT signifies that
all the registers of the CPU are being reset
all the registers and counters are being reset
all the registers and counters are being reset and this signal can be used to
reset external support chip
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d. processing can begin when this signal goes high
Answer: (c).all the registers and counters are being reset and this signal can be
used to reset external support chip
In a vector interrupt
the branch address is assigned to a fixed location in memory
the interrupting source supplies the branch information to the processor
through an interrupt vector
the branch address is obtained from a register in the processor
none of the above
Answer: (a).the branch address is assigned to a fixed location in memory
The content of the A15-A8 (higher order address lines) while executing “IN
8-bit port address” instruction are
same as the content of A7-A0
irrelevant
all bits reset (i.e. 00H)
all bits set (i.e. FFH)
Answer: (a).same as the content of A7-A0
21. Which one of the following interrupt is only level triggering?
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a. TRAP
b. RST 7.5
c. RST 6.5 and RST 5.5
d. RST 6.5
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Answer: (c).RST 6.5 and RST 5.5
Which one of the following instruction may be used to clear the
accumulator content irrespective of its initial value?
CLR A
ORA A
SUB A
MOV A, 00H
Answer: (c).SUB A
23. signal prevent the microprocessor from reading the same data
more than one.
pipelining
handshaking
controlling
signaling
Answer: (b).handshaking
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Data transfer between the microprocessor for peripheral takes place
through .
I/O port
input port
output port
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d. multi port
Answer: (a).I/O port
25. 8255A operates with power supply.
a. +5V
-5V
-10V
d. +10V
Answer: (a).+5V
The allow data transfer between memory and peripherals.
DMA technique
Microprocessor
Register
Decoder
Answer: (a).DMA technique
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Expansion of SPGA is .
Staggered Pin Grid-Array package
Staggered Point Grid-Array package
Staggered Plus Grid-Array package
Staggered per grid-Array package
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Answer: (a).Staggered Pin Grid-Array package
Pentium-pro processor design implements_ micro architecture.
P2
P4
P6
P8
Answer: (c).P6
The number of hardware chips needed for multiple digit display can be
minimized by using the technique called .
interfacing
multiplexing
demultiplexing
multiprocessing
Answer: (b).multiplexing
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An RS-232 interface is .
a parallel interface
a serial interface
printer interface
a modem interface
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Answer: (b).a serial interface
31. Expansion for DTE is .
a. data terminal equipment
b. data trap equipment
c. data text equipment
d. data terminal extension
Answer: (a).data terminal equipment
Compared with RS-232, USB is faster and uses_ .
medium voltage
higher voltage
lower voltage
None of the above
Answer: (c).lower voltage
Expansion for HMOS technology is .
high level mode oxygen semiconductor
high level metal oxygen semiconductor
high performance medium oxide semiconductor
high performance metal oxide semiconductor
Answer: (d).high performance metal oxide semiconductor
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RIM is used to check whether, the .
write operation is done or not
interrupt is Masked or not
interrupt is Masked
interrupt is not Masked
Answer: (b).interrupt is Masked or not
What does microprocessor speed depends on?
clock
data bus width
address bus width
signal bus
Answer: (c).address bus width
The advantage of memory mapped I/O over I/O mapped I/O is
faster operation
many instructions supporting memory mapped I/O
require a bigger address decoder
all the above
Answer: (d).all the above
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37. In 8279 Status Word, data is read when pins are low, and write to
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the display RAM with are low.
A0, CS, RD & A0, WR, CS
CS, WR, A0 & A0, CS, RD
A0, RD & WR, CS
CS, RD & A0, CS
Answer: (a).A0, CS, RD & A0, WR, CS
In 8279, the keyboard entries are de bounced and stored in an ,
that is further accessed by the CPU to read the key codes.
8-bit FIFO
8-byte FIFO
16 byte FIFO
16 bit FIFO
Answer: (b).8-byte FIFO
For the most Static RAM the write pulse width should be at least
10 ns
60 ns
300 ns
350 ns
Answer: (b).60 ns
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Pentium-I, Pentium-II, Pentium-III and Pentium-IV are recently
introduced microprocessor by .
Motorala
Intel
Stephen Mors
HCL
Answer: (b).Intel
The address bus flow in .
bidirection
unidirection
mulidirection
Answer: (b).unidirection
circular
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4 The 8085 microprocessor is based in a pin DIP.
2.
a. 40
b. 45
c. 20
d. 35
Answer: (a).40
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43. The 8085 Microprocessor uses_ power supply.
a. +5V
b. -5V
c. +12V
d. -12V
Answer: (a).+5V
Answer: (a).Pushing data
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Which is used to store critical pieces of data during subroutines and
interrupts ?
Stack
Queue
Accumulator
Data register
Answer: (a).Stack
The data in the stack is called
Pushing data
Pushed
Pulling
None of these
Answer: (a).Pushing data
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The external system bus architecture is created using from
architecture.
Pascal
Dennis Ritchie
Charles Babbage
Von Neumann
Answer: (c).Both A and B
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Answer: (d).Von Neumann
Secondary memory can store_ .
Program store code
Compiler
Operating system
All of these
Answer: (d).All of these
Secondary memory is also called .
Auxiliary
Backup store
Both A and B
None of these
Answer: (c).Both A and B
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The lower red curvy arrow show that CPU places the address extracted
from the memory location on the_ .
Address bus
System bus
Control bus
Data bus
Answer: (a).Address bus
50. The CPU sends out a signal to indicate that valid data is available on
the data bus.
a. Read
b. Write
c. Both a and b
d. None of these
Answer: (b).Write
UNIT-2
1. In 8085 microprocessor, how many interrupts are maskable.
a. Two
b. Three
c. Four
d. Five
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Answer. c
2. Which stack is used in 8085 microprocessors?
a. FIFO
b. FILO
c. LIFO
d. LILO
Answer. c
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3. In the instruction of the 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
4. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
5. Which one of the following register of 8085 microprocessor is not a part of the
programming model?
a. Instruction register
b. Memory address register
c. Status register
d. Temporary data register
Answer. c
6. The program counter in 8085 microprocessor is a 16-bit register, because
a. It counts 16 bits at a time
b. There are 16 address times
c. It facilitates the users storing 16-bit data temporarily
d. It has to fetch two 8-bit data at a time.
Answer. b
7. A direct memory access (DMA) transfer replies
a. Direct transfer of data between memory and accumulator
b. Direct transfer of data between memory and I/O devices without the use of
microprocessor
c. Transfer of data exclusively within microprocessor registers
d. A fast transfer of data between microprocessor and I/O devices
Answer. b
8. Handshaking mode of data transfer is
a. Synchronous data transfer
b. asynchronous data transfer
c. interrupt driven data transfer
d. level Mode of DMA data transfer
Answer. a
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9. In a Microprocessor, the address of the new next instruction to be executed is
stored in
a. Stack pointer
b. address latch
c. Program counter
d. General purpose register
Answer. c
10. In how many different modes a universal shift register operates?
a. 2
b. 3
c. 4
d. 5
Answer. c
11. The insruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
12. Which one of the following statements is correct regarding the instruction
CMP A ?
a. compare accumulator with register A
b. compare accumulator with memory
c. compare accumulator with register H
d. This instruction does not exist
Answer. a
13. The instruction JNC 16-bit refers to jump to 16-bit address if ?
a. sign flag is set
b. carry flag is reset
c. zero flag is set
d. parity flag is reset
Answer. b
14. Among the given instructions, the one which affects the maximum number of
flags is ?
a. RAL
b. POP PSW
c. XRA A
d. DCR A
Answer. c
15. XCHG instruction of 8085 exchanges the content of ?
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a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
16. Direction flag is used with
a. string instructions
b. stack instructions
c. arithmetic instructions
d. branch instructions
Answer. a
17. The number of output pins of a 8085 microprocessor are
a. 40
b. 27
c. 21
d. 19
Answer. b
18. Following is a 16-bit register for 8085 microprocessor
a. Stack pointer
b. Accumulator
c. Register B
d. Register C
Answer. a
19. The register which holds the information about the nature of results of
arithmetic of logic operations is called as
a. Accumulator
b. Condition code register
c. Flag register
d. Process status registers
Answer. c
20. When referring to instruction words, a mnemonic is
a. a short abbreviation for the operand address.
b. a short abbreviation for the operation to be performed.
c. a short abbreviation for the data word stored at the operand address.
d. Shorthand for machine language.
Answer. b
21. While using a frequency counter for measuring frequency, two modes of
measurement are possible.
1. Period mode
2. Frequency mode
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There is a ‘cross-over frequency’ below which the period mode is preferred.
Assuming the crystal oscillator frequency to be 4 MHz the crossover frequency is
given by
a. 8 MHz
b. 2 MHz
c. 2 kHz
d. 1 kHz
Answer. b
22. In a 8085 microprocessor system with memory-mapped I/O, which of the
following is true?
a. Devices have 8-bit‘address line
b. Devices are accessed using IN and OUT instructions
c. There can be maximum of 256 input devices and 256 output devices
d. Arithmetic and logic operations can be directly performed with the I/O data
Answer. d
23. Consider the following statements:
Arithmetic Logic Unit (ALU)
1 . Performs arithmetic operations.
2. Performs comparisons.
3. Communicates with I/O devices.
4. Keeps watch on the system.
Which of these statements are correct?
a. 1, 2, 3 and 4
b. 1,2 and 3 only
c. 1 and 2 only
d. 3 and 4 only
Answer. c
24. Ready pin 0f microprocessor is used
a. to indicate that the microprocessor is ready to receive inputs
b. to indicate that the microprocessor is ready to receive outputs
c. to introduce wait state
d. to provide direct memory access
Answer. c
25. A bus connected between the CPU and the main memory that permits transfer
of information between main memory and the CPU is known as
a. DMA bus
b. Memory bus
c. Address bus
d. Control bus
Answer. b
26. The operations executed by two or more control units are referred as
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a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer. c
27. Consider the following registers:
1. Accumulator and flag register
2. B and C registers
3. D and E registers
4. H and L registers
Which of these 8-bit registers of 8085 μP can be paired together to make a 16-bit
register?
a. (a) 1, 3 and 4
b. 2, 3 and 4
c. 1, 2 and 3
d. 1, 2 and 4
Answer. b
28. The first microprocessor to include virtual memory in the Intel
microprocessor family is
a. 80286
b. 80386
c. 80486
d. Pentium
Answer. a
29. Program counter in a digital computer
a. counts the numbers of programs run in the machine ,
b. counts the number of times a subroutine is called
c. counts the number of times the loops are executed
d. points the memory address of the current or the next instruction to be
executed
Answer
Answer. d
30. Assuming LSB is at position 0 and MSB at position 7, which bit positions are
not used (undefined) in Flag Register of an 8085 microprocessor?
a. 1, 3, 5
b. 2, 3, 5
c. 1, 2, 5
d. 1, 3, 4
Answer. a
31. At the beginning of a fetch cycle, the contents of the program counter are
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a. incremented by one
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b. transferred to address bus
c. transferred to memory address register
d. transferred to memory data register
Answer. c
32. Each instruction in an assembly language program has the following fields
1. Label field
2. Mnemonic field
3. Operand field
4. Comment field
What is the correct sequence of these fields?
a. 1, 2, 3 and 4
b. 2, 1, 4 and 3
c. 1,3, 2 and 4
d. 2, 4, 1 and 3
Answer. a
33. The relation among IC (lnstruction Cycle), FC (Fetch Cycle) and EC (Execute
Cycle) is
a. IC = FC − EC
b. IC = FC+ EC
c. IC= FC + 2EC
d. EC = IC+FC
Answer. b
34. When a peripheral is connected to the microprocessor in input/output mode,
the data transfer takes place between
a. any register and I/O device
b. memory and I/O device
c. accumulator and I/O device
d. HL registerand I/O device.
Answer. c
35. While execution of I/O instruction takes place, the 8-bit address of the port is
placed on
a. lower address bus
b. higher address bus
c. data bus
d. lower as well as higher-order address bus
Answer. d
36. The length of a bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and
an indeterminate number of wait state clock cycles denoted by TW. The wait
states are always inserted between
a. T1 and T2
b. T2 and T3
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c. T3 and T4
d. T4 and T1
Answer. c
37. Which one of the following circuits transmits two messages simultaneously in
one direction?
a. Duplex
b. Diplex
c. Simplex
d. Quadruplex
Answer. b
38. A microprocessor is ALU
a. and control unit on a single chip
b. and memory on a single chip
c. register unit and I/O device on a single chip
d. register unit and control unit on a single chip
Answer. d
39. In Intel 8085 microprocessor, ALE signal is made high to
a. Enable the data bus to be used as low order address bus
b. To latch data D0— D7 from the data bus
c. To disable data bus
d. To achieve all the functions listed above
Answer. a
40. Output of the assembler in machine codes is referred to as
a. Object program
b. Source program
c. Macro instruction
d. Symbolic addressing
Answer. a
41. Which one of the following statements for Intel 8085 is correct?
a. Program counter (PC) specifies the address of the instruction last executed
b. PC specifies the address of the instruction being executed
c. PC specifies the address of the instruction be executed
d. PC specifies the number of instruction executed so far
Answer. c
42. The instruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
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43. Which one of the following statements is correct regarding the instruction
CMP A?
a. Compare accumulator with register A
b. Compare accumulator with memory
c. Compare accumulator with register H
d. This instruction does not exist
Answer. a
44. The instruction JNC 16-bit refers to jump to 16-bit address if
a. Sign flag is set
b. Carry flag is reset
c. Zero flag is set
d. Parity flag is reset
Answer. b
45. Consider the following interrupts for 8085 microprocessor:
1. INTR
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. TRAP
If the interrupt is to be vectored to any memory location then which of the above
interrupt is/are correct?
a. 1 and 2 only
b. 1, 2, 3 and 4
c. 5 only
d. 1 only
Answer. d
46. Consider the following statements:
1. Auxiliary carry flag is used only by the DAA and DAS instruction.
2. Zero flag is set to 1 if the two operands compared are equal.
3. All conditional jumps are long type jumps.
Which of the above statements are correct?
a. 1, 2 and 3 only
b. 1 and 2 only
c. 1 and 3 only
d. 2 and 3 only
Answer. b
47. Among the given instructions, the one which affects maximum number of
flags is
a. RAL
b. POP PSW
c. XRA A
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d. DCR A
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Answer. c
48. XCHG instruction of 8085 exchanges the content of
a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
49. Direction flag is used with
a. String instructions
b. Stack instructions
c. Arithmetic instructions
d. Branch instructions
Answer. a
50. What will be the contents of DE and HL register pairs respectively after the
execution of the following instructions?
LXIH, 2500 H
LXID, 0200 H
DAD D
XCHG
a. 0200 H, 2500 H
b. 0200 H, 2700 H
c. 2500 H, 0200 H
d. 2700 H, 0200 H
Answer. d
UNIT-3
51. In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
52. A ‘DAD H” instruction is the same as shifting each bit by one position to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
53. When a program is being executed in an 8085 microprocessor, its program
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counter contains
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a.
the memory address as the instruction that is to be executed next.
b.
the memory address of the instruction that is being currently matched.
c.
the total number of instructions in the program being executed.
d.
the number of instructions in the current program that have already been
executed.
Answer. a
54. Which of the following data transfer is not possible in microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
55. LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
d. loads English like command and generates the binary code
Answer. b
56. Which of the following instructions is closest match to the instruction POP
PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
57. How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
58. Which of the following 8085 instruction will require maximum T-states for
execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
59. In 8085 microprocessor, which mode of addressing does the instruction CMP
M use?
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a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
60. With reference to 8085 microprocessor, which of the following statements
are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
61. Assume that the accumulator and the register C of 8085 microprocessor
contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution of
instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
62. It is desired to multiply the numbers 0A H by OB H and store the result in the
accumulator. The numbers are available in registers B and C respectively. A part
of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C
b. ADD B; JNZ LOOP; DCR C
c. DCR C; JNZ LOOP; ADD B
d. ADD B; DCR C; JNZ LOOP
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Answer. d
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63. Find the content of the accumulator after the execution of the following
program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
64. The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
65. The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
66. The content of accumulator are 70 H. Initially all flags are zero. What will be
values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
67. A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
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How many times DCR instruction will be executed?
a 255
. 510
b
c. 650
. 652
d 25
. 79d
Answer.
68. What is content of accumulator of 8085 microprocessor after the execution of
XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
69. The 8085 programming manual says that it takes seven T states to fetch and
execute the MOV instruction. If the system clock has a frequency of 2.5 MHz, how
long is an instruction Cycle?
a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
70. The instruction PCHL, in 8085 is used for
a. Load PC with contents of HL.
b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
71. The following instruction copies a byte of data from the accumulator into the
memory address given in the instruction
a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
72. The instruction that exchanges top of stack with HL pair is
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a. XTHL
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b. SPHL
c. PUSH H
d. POP H
Answer. a
73. In 8085 microprocessor, during PUSH PSW Operation, Stack pointer is
a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
74. While a program is being executed in an Intel 8085 microprocessor, the
program counter of the microprocessor contains:
a. The memory address of the instruction that is being currently executed.
b. The memory address of the instruction that is to be executed next.
c. The number of instructions that have already been executed.
d. The total number of instructions in the current program still to be
executed.
Answer. b
75. The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
76. If the status of the control lines SI and SO is LOW, then 8085 microprocessor
is performing
a. Reset operation
b. HOLD operation
c. Halt operation
d. Interrupt acknowledge
Answer. c
77. LXI SP, 7FFF H
MVI A, 25 H
XRI 02 H
PUSH PSW
POP H
MOV A,L
ORI 10 H
HLT
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What are the contents of A, H, L, SP and PSW registers after executing the above
set of instructions? Assume undefined flags always remain clear.
a. 10H, 25H, 00H, 7FFFH, 00H respectively
b. 14H, 27H, 04H, 7FFFH, 04H respectively
c. 14H, 25H, 00H. 7FFFH, 04H respectively
d. 10H, 27H, 04H, 7FFFH, 00H respectively
Answer. b
78. The content of the programme counter of an 8085 microprocessor is
a. the total number of instructions in the program already executed.
b. the total number of times a subroutine is called.
c. the memory address of the instruction that is being currently executed.
d. the memory address of the instruction that is to be executed next.
Answer. d
79. The opcode for the instruction “Add Immediately to Accumulator with carry”
in 8085 microprocessor is
a. ADI
b. ACI
c. ADC
d. ADD
Answer. b
80. MVI A, AA H
ORI FFH
RRC
RRC
CMC
INR A
What are the contents of A and PSW registers after executing the above set of
instructions in sequence?
a. AAH and 00H
b. FFH and 66H
c. 00H and 54H
d. 00H and 00H
Answer. c
81. For which one of the following, the instruction XRA A in 8085 microprocessor
can be used?
a. Set the carry flag
b. Set the zero flag
c. Reset the carry flag and clear the accumulator
d. Transfer FFH to the accumulator
Answer. b
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82. An 8085 microprocessor is executing the programme as follows:
MVI A, 20H
MVI B, 10H
BACK: NOP
ADD B
RLC
JNC BACK
HLT
How many times the instruction NOP will be executed?
a. 4
b. 3
c. 2
d. 1
Answer. b
83. The stack pointer of an 8085 microprocessor is ABCD H. At the end of
execution of the sequence of instructions, what will be the content of the stack
pointer?
PUSH PSW
XTHL
PUSH D
JMP FC70 H
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
84. What is the correct 8085 assembly language instruction that stores the
contents of H and L registers into the memory locations 1080 H and 1081 H
respectively?
a. SPHL 1080 H
b. SHLD 1080 H
c. STAX 1080 H
d. SPHL 1081 H
Answer. b
85. When the operand requires for instruction is stored inside the processor, then
What this addressing mode is called?
a. Direct
b. Register
c. Implicit
d. Immediate
Answer. b
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86. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
87. In an instruction of 8085 microprocessor, how many bytes are present?
One or two
One, two or three
One only
Two or three
Answer. b
Which one is the indirect addressing mode in the following instructions?
LXI H 2050 H
MOV A, B
LDAX B
LDA 2050 H
Answer. c
The addressing mode used in the instruction JMP F347 H in case of an Intel
8085A microprocessor is which one of the following?
Direct
Register—indirect
Implicit
Immediate
Answer. d
Carry flag is not affected after the execution of
a. ADD B
b. SBB B
c. INR B
d. ORA B
Answer. c
91. The contents of the Program Counter (PC), when the microprocessor is
reading from 2FFF H memory location, will be
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a. 2FFE H
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b. 2FFF H
c. 3000 H
d. 3001 H
Answer. c
92. If the HLT instruction of an Intel 8085A microprocessor is executed
a. the microprocessor is disconnected from the system bus till the RESET is
pressed.
b. the microprocessor halts the execution of the program and returns to the
monitor.
c. the microprocessor enters into a HALT state and the buses are tri-stated.
d. the microprocessor reloads the program counter from the locations 0024 H
and 0025 H.
Answer. c
93. The stack pointer of an 8085 A microprocessor contains ABCD H.
PUSH PSW
XTHL
PUSH D
JMP EC75 H
At the end of the execution of the above instructions, what would be the content
of the stack pointer?
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
94. In an Intel 8085 A, what is the content of the Instruction Register (IR)?
a. Op-code for the instruction being executed
b. Operand for the instruction being executed
c. Op-code for the instruction to be executed next
d. Operand for the instruction to be executed next
Answer. a
95. The content of the Program Counter of an intel 8085A microprocessor
specifies which one of the following?
a. The address of the instruction being executed
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b. The address of the instruction executed earlier
c. The address of the next instruction to be executed
d. The number of instructions executed so far
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Answer. c
96. Which one of the following statement does not describe
property/characteristic of a stack pointer register in 8085 microprocessor?
a. It points to the top of the stack.
b. It is UP/DOWN counter
c. It is automatically initialized to 0000 H on power-on
d. It is a 16-bit register
Answer. c
Which one of the following instructions is a 3-byte instruction?
MVI A
LDAX B
JMP 2050 H
MOV A,M
Answer. c
In 8085, the DAA instruction is used for
Direct Address Accumulator
Double Add Accumulator
Decimal Adjust Accumulator
Direct Access Accumulator
Answer. c
When an 8086 executes an INT type instruction, it?
Resets both IF and TF flags
Resets all flags
Sets both IF and TF
Resets the CF and TF
Answer. a an 8086 executes an INT type instruction, it?
100. When
a. Resets both IF and TF flags
b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
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UNIT-4
ASSEMBLY LANGUAGE PROGRAMMING Multiple Choice Questions :-
1) Assembly language programs are written using
A) Hex code
B) Mnenonics
C) ASCII code
D) None of these View
ANS: B
2) For execution of an interrupt applied at INTR, number of states required by
8085 Microprocessor are
A) 4
B) 6
C) 12
D) 18
ANS: C
3) In 8085 which is/are the 16 bit registers?
A) Program Counter
B) Stack Pointer
C) Both A) & B)
D) None of the above
ANS: C
4) How many memory locations are required to store the instruction LXIH,
0800H in an 8085 assembly language program?
A) 1
B) 2
C) 3
D) 4
ANS: B
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5) The instruction DEC N inform the assembler to....
A) Decrement the content of N
B) Decrement the data addressed by N
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C) Convert signed decimal number to binary
D) None of the above
ANS: A
6) In 8085 microprocessor, the value of the most significant bit of the result
following the execution of any arithmetic or Boolean instruction is stored in
the
A) carry status flag
B) auxiliary carry status flag
C) sign status flag
D) zero status flag
ANS: C
7) Instructions performing actions in assembly language are called
A) imperative statements
B) declarative statements
C) directive statements
D) none of the above
ANS: A
8) What is the content of Stack Pointer ?
A) Address of the current instruction
B) Address of the next instruction
C) Address of the top element of the stack
D) None of the above
ANS: C
9) Which of the following interrupt has highest Priority?
A) INTR
B) TRAP
C) RST 7.5
D) RST 6.5
ANS: B
10) Number of machine cycles required for RET instruction in 8085
microprocessor is
A) 1
B) 2
C) 3
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D) 5
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ANS: C
11) converts the programs written in assembly language into
machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
Answer: c
Clarification: An assembler is a software used to convert the programs into
machine instructions.
12) The instructions like MOV or ADD are called as _
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned
Answer: a
Clarification: This OP – codes tell the system what operation to perform on the
operands.
13) The alternate way of writing the instruction, ADD #5,R1 is
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way
Answer: b
Clarification: The ADDI instruction, means the addition is in immediate
addressing mode.
14) Instructions which won’t appear in the object program are called as
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
Answer: d
Clarification: The directives help the program in getting compiled and hence
won’t be there in the object code.
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15) The assembler directive EQU, when used in the instruction: Sum EQU
200 does
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
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c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
Answer: b
Clarification: This basically is used to replace the variable with a constant value.
16) The purpose of the ORIGIN directive is
a) To indicate the starting position in memory, where the program block is
to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used
Answer: a
Clarification: This does the function similar to the main statement.
17) The directive used to perform initialization before the execution of
the code is
a) Reserve
b) Store
c) Dataword
d) EQU
Answer: c
Clarification: None.
18) directive is used to specify and assign the memory required for
the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve
Answer: d
Clarification: This instruction is used to allocate a block of memory and to store
the object code of the program there.
19) directive specifies the end of execution of a program.
a) End
b) Return
c) Stop
d) Terminate
Answer: b
Clarification: This instruction directive is used to terminate the program
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execution.
20) The last statement of the source program should be
a) Stop
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b) Return
c) OP
d) End
Answer: d
Clarification: This enables the processor to load some other process.
21) When dealing with the branching code the assembler
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive
Answer: c
Clarification: When the assembler comes across the branch code, it immediately
finds the branch offset and replaces it with it.
22) The assembler stores all the names and their corresponding values in
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned
Answer: b
Clarification: The table where the assembler stores the variable names along with
their corresponding memory locations and values.
23) The assembler stores the object code in
a) Main memory
b) Cache
c) RAM
d) Magnetic disk
Answer: d
Clarification: After compiling the object code, the assembler stores it in the
magnetic disk and waits for further execution.
24) The utility program used to bring the object code into memory for
execution is
a) Loader
b) Fetcher
c) Extractor
d) Linker
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Answer: a
Clarification: The program is used to load the program into memory.
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25) To overcome the problems of the assembler in dealing with
branching code we use
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
Answer: d
Clarification: This creates entries into the symbol table first and then creates the
object code.
26) In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
27) A ‘DAD H” instruction is the same as shifting each bit by one position
to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
28) When a program is being executed in an 8085 microprocessor, its
program counter contains
a. the memory address as the instruction that is to be executed next.
b. the memory address of the instruction that is being currently matched.
c. the total number of instructions in the program being executed.
d. the number of instructions in the current program that have already been
executed.
Answer. a
29) Which of the following data transfer is not possible in
microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
30) LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
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c. loads the COM file and generates the binary code
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d. loads English like command and generates the binary code
Answer. b
31) Which of the following instructions is closest match to the
instruction POP PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
32) How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
33) Which of the following 8085 instruction will require maximum T-
states for execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
34) In 8085 microprocessor, which mode of addressing does the
instruction CMP M use?
a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
35) With reference to 8085 microprocessor, which of the following
statements are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
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36) Assume that the accumulator and the register C of 8085
microprocessor contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution
of instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
37) It is desired to multiply the numbers 0A H by OB H and store the
result in the accumulator. The numbers are available in registers B and C
respectively. A part of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C
b. ADD B; JNZ LOOP; DCR C
c. DCR C; JNZ LOOP; ADD B
d. ADD B; DCR C; JNZ LOOP
Answer. d
38) Find the content of the accumulator after the execution of the
following program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
39) The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
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The content of accumulator when the program counter reaches 0107 H is
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a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
40) The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
41) The content of accumulator are 70 H. Initially all flags are zero. What
will be values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
42) A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR instruction will be executed?
a. 255
b. 510
c. 65025
d. 65279
Answer. d
43) What is content of accumulator of 8085 microprocessor after the
execution of XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
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44) The 8085 programming manual says that it takes seven T states to
fetch and execute the MOV instruction. If the system clock has a frequency
of 2.5 MHz, how long is an instruction Cycle?
a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
45) The instruction PCHL, in 8085 is used for
a. Load PC with contents of HL.
b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
46) The following instruction copies a byte of data from the accumulator
into the memory address given in the instruction
a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
47) The instruction that exchanges top of stack with HL pair is
a. XTHL
b. SPHL
c. PUSH H
d. POP H
Answer. a
48) In 8085 microprocessor, during PUSH PSW Operation, Stack pointer
is
a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
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49) While a program is being executed in an Intel 8085 microprocessor,
the program counter of the microprocessor contains:
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a.The memory address of the instruction that is being currently executed.
b.The memory address of the instruction that is to be executed next.
c.The number of instructions that have already been executed.
d.The total number of instructions in the current program still to be
executed.
Answer. b
50) The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
UNIT-5
Microprocessors Questions and Answers – Programmable DMA Interface
8237 (Part-1)
1. The block of 8237 that decodes the various commands given to the 8237 by the
CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: b
Explanation: The program control block decodes various commands given to the
8237 by the CPU before servicing a DMA request.
2. The priority between the DMA channels requesting the services can be
resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
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Answer: c
Explanation: The priority encoder block resolves the priority between the DMA
channels requesting the services.
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3. The register that holds the current memory address is
a) current word register
b) current address register
c) base address register
d) command register
Answer: b
Explanation: The current address register holds the current memory address. The
current address register is accessed during the DMA transfer.
4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register
Answer: a
Explanation: The current word register is a 16-bit register that holds the data
transfers. The word count is decremented after each transfer, and the new value
is stored again in the register.
5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated
Answer: c
Explanation: When the count becomes zero, the EOP signal is generated. This can
be written in successive bytes by the CPU, in program mode.
6. The current address register is programmed by the CPU as
a) bit-wise
b) byte-wise
c) bit-wise and byte-wise
d) none of the mentioned
View Answer
Explanation: The current address register is byte-wise programmed by the CPU,
i.e. lower byte first and the higher byte later.
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7. Which of these register’s contents is used for auto-initialization (internally)?
a) current word register
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b) current address register
c) base address register
d) command register
Answer: c
Explanation: The contents of base address register cannot be read by the CPU.
These contents are used internally for auto-initialization.
8. The register that maintains an original copy of the respective initial current
address register and current word register is
a) mode register
b) base address register
c) command register
d) mask register
Answer: b
Explanation: The base address register maintains an original copy of the current
address register and current word register, before incrementing or
decrementing.
9. The register that can be automatically incremented or decremented, after each
DMA transfer is
a) mask register
b) mode register
c) command register
d) current address register
Answer: d
Explanation: The address is automatically incremented or decremented after
each DMA transfer, and the resulting address value is again stored in the current
address register.
10. Which of the following is a type of DMA transfer?
a) memory read
b) memory write
c) verify transfer
d) all of the mentioned
Answer: d
Explanation: Memory read, memory write and verify transfer are the three types
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of DMA transfer.
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Microprocessors Questions and Answers – 8255 programmable peripheral interface-
(Part-2)
Question 1: How many pins does the 8255 PPI IC contains?
a. 24
b. 20
c. 32
d. 40
Answer: d. 40
Question 2: In which mode do all the Ports of the 8255 PPI work as Input-Output
units for data transfer?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: b. Mode 0 of I/O mode
Question 3: Which of the following pins are responsible for handling the on the
Read Write control logic unit of the 8255 PPI?
a. CS'
b. RD'
c. WR'
d. ALL of the above
Answer: d. All of the above
Question 4: In which of the following modes is the 8255 PPI capable of
transferring data while handshaking with the interfaced device?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
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d. Mode 2 of I/O mode
Answer: c. Mode 1 of I/O mode
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Question 5: How many bits of data can be transferred between the 8255 PPI and
the interfaced device at a time? or What is the size of internal bus of the 8255
PPI?
a. 16 bits
b. 12 bits
c. 8 bits
d. None of the above
Answer: c. 8 bits
Question 6: Which port of the 8255 PPI is capable of performing the handshaking
function with the interfaced devices?
a. Port A
b. Port B
c. Port C
d. All of the above
Answer: c. Port C
Question 7: In which of the following modes of the 8255 PPI, only port C is taken
into consideration?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: a. BSR mode
Question 8: In mode 2 of I/O mode, which of the following ports are capable of
transferring the data in both the directions?
a. Port A
b. Port B
c. Port C
d. All of the above
Answer: a. Port A
Question 9: In which of the following modes we do not consider the D6, D5 and
D4 bits of the control word?
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a. BSR mode
b. Mode 0 of I/O mode
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c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: a. BSR mode
Question 10: How many data lines in total are there in the 8255 PPI IC?
a. 8 data lines
b. 32 data lines
c. 24 data lines
d. None of the above
Answer: c. 24 data lines
Microprocessors Questions and Answers – 8253/8254programmable
timer/counter-(Part-3)
1. The number of counters that are present in the programmable timer device
8254 is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: There are three counters that can be used as either counters or
delay generators.
2. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
Answer: b
Explanation: The control word register can only be written and cannot be read.
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3. The mode that is used to interrupt the processor by setting a suitable terminal
count is
a) mode 0
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b) mode 1
c) mode 2
d) mode 3
Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.
4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output
becomes low for
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If
the count N is reloaded and again the output becomes high and remains so for (N-
1) clock pulses.
5. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Answer: c
Explanation: When the count N loaded is even, then for half of the count, the
output remains high and for the remaining half it remains low. If the count loaded
is odd, the first clock pulse decrements it by 1 resulting in an even count value.
6. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
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Answer: b
Explanation: SC denotes select counter.
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7. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.
8. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is
BCD count.
9. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.
10. The control word register contents are used for
a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
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ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.
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Rooma, Kanpur – 208 008
Microprocessors Questions and Answers – 8259 programmable interrupt controller-
(Part-4)
1. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7
View Answer
Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these
five, four pins were alloted fixed vector addresses but the pin INTR was not
alloted by vector address, rather an external device was supposed to hand over
the type of the interrupt to the microprocessor.
2. The register that stores all the interrupt requests in it in order to serve them
one by one on a priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request
Register internally.
3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
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Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request
Register) at the direction of the Priority Resolver.
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4. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
Answer: d
Explanation: The interrupt control logic performs all the operations that are
involved within the interrupts like accepting and managing interrupt
acknowledge signals, interrupts.
5. In a cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64
vectored interrupts can be provided.
6. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode,
then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a
buffer enable to control buffer transreceivers. If it is not used in buffered mode,
then the pin is used as input to designate whether the chip is used as a master or
a slave.
7. Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
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Answer: d
Explanation: The initialization procedure involves
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i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.
8. When non-specific EOI command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will
automatically reset the highest ISR.
9. In the application where all the interrupting devices are of equal priority, the
mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
Answer: a
Explanation: The automatic rotation is used in the applications where all the
interrupting devices are of equal priority.
Microprocessors Questions and Answers – 8251 USART and
RS232C- (Part-5)
1. Which of the following is not a mode of data transmission?
a) simplex
b) duplex
c) semi duplex
d) half duplex
Answer: c
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Explanation: Basically, there are three modes of data transmission. simplex,
duplex and half duplex.
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2. If the data is transmitted only in one direction over a single communication
channel, then it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: a
Explanation: In simplex mode, the data transmission is unidirectional. For
example, a CPU may transmit data for a CRT display unit in this mode.
3. If the data transmission takes place in either direction, but at a time data may
be transmitted only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: d
Explanation: In half duplex mode, data transmission is bidirectional but not at a
time. For example, Walkie-Talkie.
4. In 8251A, the pin that controls the rate at which the character is to be
transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)
Answer: a
Explanation: Transmitter Clock Input (TXC(active low)) is a pin that controls the
rate at which the character is to be transmitted.
5. TXD(Transmitted Data Output) pin carries serial stream of the transmitted
data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned
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Answer: d
Explanation: Transmitted Data Output pin carries a serial stream of the
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transmitted data bits along with other information like start bits, stop bits and
parity bits etc.
6. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY(Transmitter ready)
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)
Answer: b
Explanation: RXRDY(Receiver ready output) may be used either to interrupt the
CPU or polled by the CPU.
7. The disadvantage of RS-232C is
a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned
Answer: d
Explanation: RS232C has been used for long and has a few disadvantages like
limited speed of communication, high-voltage level signaling and big-size
communication adapters.
8. The USB supports the signaling rate of
a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned
Answer: d
Explanation: The USB standards support the signaling rates. Also, USB signaling is
implemented in a differential in low- and full-speed options.
9. The bit packet that commands the device either to receive data or transmit
data in transmission of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
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Answer: b
Explanation: The token packet is the second type of packet which commands the device
either to receive data or transmit data.
10. High speed USB devices neglect
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
Answer: c
Explanation: PRE packets are only of importance to low-speed USB devices
Microprocessors MCQs Set-1
A+
A
A-
This section contains more frequently asked Microprocessors MCQs (Multiple Choice
Questions Answers) in the various University Level and Competitive Examinations.
Practice it now to sharpen your concepts and knowledge
1
. Which is the microprocessor comprises:
A. Register section
B. One or more ALU
C. Control unit
D. All of these
D. All of these
2
. What is the store by register?
A. data
B. operands
C. memory
D. None of these
A. data
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3
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. Accumulator based microprocessor example are:
A. Intel 8085
B. Motorola 6809
C. A and B
D. None of these
C. A and B
4
. A set of register which contain are:
A. data
B. memory addresses
C. result
D. all of these
D. all of these
5
. There are primarily two types of register:
A. general purpose register
B. dedicated register
C. A and B
D. none of these
C. A and B
6
. Name of typical dedicated register is:
A. PC
B. IR
C. SP
D. All of these
D. All of these
7
. BCD stands for:
A. Binary coded decimal
B. Binary coded decoded
C. Both a & b
D. none of these
A. Binary coded decimal
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8
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. Which is used to store critical pieces of data during subroutines and interrupts:
A. Stack
B. Queue
C. Accumulator
D. Data register
A. Stack
9
. The data in the stack is called:
A. Pushing data
B. Pushed
C. Pulling
D. None of these
A. Pushing data
10
. The external system bus architecture is created using from ______ architecture:
A. Pascal
B. Dennis Ritchie
C. Charles Babbage
D. Von Neumann
D. Von Neumann
This section contains more frequently asked Microprocessors 8085 Multiple Choice Questions
and Answers in the various University Level and Competitive Examinations.
1
. The processor 80386/80486 and the Pentium processor uses _____ bits address bus:
A. 16
B. 32
C. 36
D. 64
B. 32
2
. Which is not the control bus signal:
A. READ
B. WRITE
C. RESET
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D. None of these
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C. RESET
3
. PROM stands for:
A. Programmable read‐only memory
B. Programmable read write memory
C. Programmer read and write memory
D. None of these
A. Programmable read‐only memory
4
. EPROM stands for:
A. Erasable Programmable read‐only memory
B. Electrically Programmable read write memory
C. Electrically Programmable read‐only memory
D. None of these
A. Erasable Programmable read‐only memory
5
. Which is the type of microcomputer memory:
A. Address
B. Contents
C. Both A and B
D. None of these
C. Both A and B
6
. Secondary memory can store____:
A. Program store code
B. Compiler
C. Operating system
D. All of these
D. All of these
7
. Secondary memory is also called____:
A. Auxiliary
B. Backup store
C. Both A and B
D. None of these
C. Both A and B
8
. Customized ROMS are called:
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A. Mask ROM
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B. Flash ROM
C. EPROM
D. None of these
A. Mask ROM
9
. The RAM which is created using bipolar transistors is called:
A. Dynamic RAM
B. Static RAM
C. Permanent RAM
D. DDR RAM
B. Static RAM
10
. Each memory location has:
A. Address
B. Contents
C. Both A and B
D. None of these
C. Both A and B
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QUE AND ANS
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Microprocessors MCQs Set-3
A+
A
A-
This section contains more frequently asked Microprocessors 8085 Questions and
Answers in the various University Level and Competitive Examinations.
1
. Which type of RAM needs regular referred:
A. Dynamic RAM
B. Static RAM
C. Permanent RAM
D. SD RAM
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A. Dynamic RAM
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2
. Which RAM is created using MOS transistors:
A. Dynamic RAM
B. Static RAM
C. Permanent RAM
D. SD RAM
A. Dynamic RAM
3
. A microprocessor retries instructions from :
A. Control memory
B. Cache memory
C. Main memory
D. Virtual memory
C. Main memory
4
. The lower red curvy arrow show that CPU places the address extracted from the memory
location on the_____:
A. Address bus
B. System bus
C. Control bus
D. Data bus
A. Address bus
5
. The CPU sends out a ____ signal to indicate that valid data is available on the data bus:
A. Read
B. Write
C. Both A and B
D. None of these
B. Write
6
. The CPU removes the ___ signal to complete the memory write operation:
A. Read
B. Write
C. Both A and B
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D. None of these
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A. Read
7
. BIU STAND FOR:
A. Bus interface unit
B. Bess interface unit
C. A and B
D. None of these
A. Bus interface unit
8
. EU STAND FOR:
A. Execution unit
B. Execute unit
C. Exchange unit
D. None of these
A. Execution unit
9
. Which are the four categories of registers:
A. General‐ purpose register
B. Pointer or index registers
C. Segment registers
D. Other register
E. All of these
E. All of these
10
. Eight of the register are known as:
A. General‐ purpose register
B. Pointer or index registers
C. Segment registers
D. Other register
A. General‐ purpose register
1
. The four index register can be used for:
A. Arithmetic operation
B. Multipulation operation
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C. Subtraction operation
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D. All of these
A. Arithmetic operation
2
. IP Stand for:
A. Instruction pointer
B. Instruction purpose
C. Instruction paints
D. None of these
A. Instruction pointer
3
. CS Stand for:
A. Code segment
B. Coot segment
C. Cost segment
D. Counter segment
A. Code segment
4
. DS Stand for:
A. Data segment
B. Direct segment
C. Declare segment
D. Divide segment
A. Data segment
5
. Which are the segment:
A. CS: Code segment
B. DS: data segment
C. SS: Stack segment
D. ES:extra segment
E. All of these
E. All of these
6
. The acculatator is 16 bit wide and is called:
A. AX
B. AH
C. AL
D. DL
A. AX
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7
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. How many bits the instruction pointer is wide:
A. 16 bit
B. 32 bit
C. 64 bit
D. 128 bit
A. 16 bit
8
. How many type of addressing in memory:
A. Logical address
B. Physical address
C. Both A and B
D. None of these
C. Both A and B
9
. The size of each segment in 8086 is:
A. 64 kb
B. 24 kb
C. 50 kb
D. 16kb
A. 64 kb
10
. The _______ address of a memory is a 20 bit address for the 8086 microprocessor:
A. Physical
B. Logical
C. Both
D. None of these
A. Physical
. EA stand for:
A. Effective address
B. Electrical address
C. Effect address
D. None of these
A. Effective address
2
. BP stand for:
A. Bit pointer
B. Base pointer
C. Bus pointer
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D. Byte pointer
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B. Base pointer
3
. DI stand for:
A. Destination index
B. Defect index
C. Definition index
D. Delete index
A. Destination index
4
. SI stand for:
A. Stand index
B. Source index
C. Segment index
D. Simple index
B. Source index
5
. ALE stand for:
A. Address latch enable
B. Address light enable
C. Address lower enable
D. Address last enable
A. Address latch enable
6
. NMI stand for:
A. Non mask able interrupt
B. Non mistake interrupt
C. Both
D. None of these
A. Non mask able interrupt
7
. ________ is the most important segment and it contains the actual assembly language instruction
to be executed by the microprocessor:
A. Data segment
B. Code segment
C. Stack segment
D. Extra segment
B. Code segment
8
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. The offset of a particular segment varies from _________:
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A. 000H to FFFH
B. 0000H to FFFFH
C. 00H to FFH
D. 00000H to FFFFFH
B. 0000H to FFFFH
9
. The pin configuration of 8086 is available in the________:
A. 40 pin
B. 50 pin
C. 30 pin
D. 20 pin
A. 40 pin
10
. DIP stand for:
A. Deal inline package
B. Dual inline package
C. Direct inline package
D. Digital inline package
B. Dual inline package
This section contains more frequently asked Microprocessors Questions and Answers in the
various University Level and Competitive Examinations.
1
. Which are the factor of cache memory:
A. Architecture of the microprocessor
B. Properties of the programs being executed
C. ize organization of the cache
D. All of these
D. All of these
2
. ________ is usually the first level of memory access by the microprocessor:
A. Cache memory
B. Data memory
C. Main memory
D. All of these
A. Cache memory
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3
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. Which is the small amount of high‐ speed memory used to work directly with the microprocessor:
A. Cache
B. Case
C. Cost
D. Coos
A. Cache
4
. The cache usually gets its data from the_________ whenever the instruction or data is required
by the CPU:
A. Main memory
B. Case memory
C. Cache memory
D. All of these
A. Main memory
5
. Microprocessor reference that are available in the cache are called______:
A. Cache hits
B. Cache line
C. Cache memory
D. All of these
A. Cache hits
6
. Microprocessor reference that are not available in the cache are called_________:
A. Cache hits
B. Cache line
C. Cache misses
D. Cache memory
C. Cache misses
7
. Which causes the microprocessor to immediately terminate its present activity:
A. RESET signal
B. INTERUPT signal
C. Both
D. None of these
A. RESET signal
8
. Which is responsible for all the outside world communication by the microprocessor:
A. BIU
B. PIU
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C. TIU
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D. LIU
A. BIU
9
. INTR: it implies the__________ signal:
A. INTRRUPT REQUEST
B. INTRRUPT RIGHT
C. INTRRUPT RONGH
D. INTRRUPT RESET
A. INTRRUPT REQUEST
10
. Which of the following are the two main components of the CPU?
A. Control Unit and Registers
B. Registers and Main Memory
C. Control unit and ALU
D. ALU and bus
C. Control unit and ALU
1
. Different components n the motherboard of a PC unit are linked together by sets of parallel
electrical conducting lines. What are these lines called?
A. Conductors
B. Buses
C. Connectors
D. Consecutives
B. Buses
2
. The language that the computer can understand and execute is called
A. Machine language
B. Application software
C. System program
D. All of the above
A. Machine language
3
. Which of the following is used as a primary storage device?
A. Magnetic drum
B. PROM
C. Floppy disk
D. All of these
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B. PROM
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4
. Which of the following memories needs refresh?
A. SRAM
B. DRAM
C. ROM
D. All of above
B. DRAM
5
. The memory which is programmed at the time it is manufactured
A. PROM
B. RAM
C. PROM
D. EPROM
A. PROM
6
. Which of the following memory medium is not used as main memory system?
A. Magnetic core
B. Semiconductor
C. Magnetic tape
D. Both a and b
C. Magnetic tape
7
. Registers, which are partially visible to users and used to hold conditional, are known as
A. PC
B. Memory address registers
C. General purpose register
D. Flags
C. General purpose register
8
. One of the main feature that distinguish microprocessors from micro‐computers is
A. Words are usually larger in microprocessors
B. Words are shorter in microprocessors
C. Microprocessor does not contain I/O devices
D. Exactly the same as the machine cycle time
C. Microprocessor does not contain I/O devices
9
. The first microprocessor built by the Intel Corporation was called
A. 8008
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B. 8080
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C. 4004
D. 8800
C. 4004
10
. An integrated circuit is
A. A complicated circuit
B. An integrating device
C. Much costlier than a single transistor
D. Fabricated on a tiny silicon chip
D. Fabricated on a tiny silicon chip
1
. Most important advantage of an IC is its
A. Easy replacement in case of circuit failure
B. Extremely high reliability
C. Reduced cost
D. Low powers consumption
B. Extremely high reliability
2
. Which of the following items are examples of storage devices?
A. Floppy / hard disks
B. CD‐ROMs
C. Tape devices
D. All of the above
D. All of the above
3
. The Width of a processor’s data path is measured in bits. Which of the following are common
data paths?
A. 8 bits
B. 12 bits
C. 16 bits
D. 32 bits
A. 8 bits
4
. Which is the type of memory for information that does not change on your computer?
A. RAM
B. ROM
C. ERAM
D. RW / RAM
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B. ROM
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5
. What type of memory is not directly addressable by the CPU and requires special softw3are
called EMS (expanded memory specification)?
A. Extended
B. Expanded
C. Base
D. Conventional
B. Expanded
6
. Before a disk can be used to store data. It must be…….
A. Formatted
B. Reformatted
C. Addressed
D. None of the above
A. Formatted
7
. Which company is the biggest player in the microprocessor industry?
A. Motorola
B. IBM
C. Intel
D. AMD
C. Intel
8
. A typical personal computer used for business purposes would have… of RAM.
A. 4 KB
B. 16 K
C. 64 K
D. 256 K
D. 256 K
9
. The word length of a computer is measured in
A. Bytes
B. Millimeters
C. Meters
D. Bits
D. Bits
10
. What are the three decisions making operations performed by the ALU of a computer?
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A. Grater than
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B. Less than
C. Equal to
D. All of the above
D. All of the above
1
. Can you tell what passes into and out from the computer via its ports?
A. Data
B. Bytes
C. Graphics
D. Pictures
A. Data
2
. What is the responsibility of the logical unit in the CPU of a computer?
A. To produce result
B. To compare numbers
C. To control flow of information
D. To do math’s works
B. To compare numbers
3
. The secondary storage devices can only store data but they cannot perform
A. Arithmetic Operation
B. Logic operation
C. Fetch operations
D. Either of the above
D. Either of the above
4
. Which of the following memories allows simultaneous read and write operations?
A. ROM
B. RAM
C. EPROM
D. None of above
B. RAM
5
. Which of the following memories has the shortest access times?
A. Cache memory
B. Magnetic bubble memory
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C. Magnetic core memory
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D. RAM
A. Cache memory
6
. A 32 bit microprocessor has the word length equal to
A. 2 byte
B. 32 byte
C. 4 byte
D. 8 byte
C. 4 byte
7
. An error in computer data is called
A. Chip
B. Bug
C. CPU
D. Storage device
B. Bug
8
. The silicon chips used for data processing are called
A. RAM chips
B. ROM chips
C. Micro processors
D. PROM chips
D. PROM chips
9
. The metal disks, which are permanently housed in, sealed and contamination free containers are
called
A. Hard disks
B. Floppy disk
C. Winchester disk
D. Flexible disk
C. Winchester disk
10
. A computer consists of
A. A central processing unit
B. A memory
C. Input and output unit
D. All of the above
D. All of the above
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This section contains more frequently asked Microprocessors Fundamental Multiple Choice
Questions and Answers in the various University Level and Competitive Examinations.
1
. The instructions for starting the computer are house on
A. Random access memory
B. CD‐Rom
C. Read only memory chip
D. All of above
C. Read only memory chip
2
. The ALU of a computer normally contains a number of high speed storage element called
A. Semiconductor memory
B. Registers
C. Hard disks
D. Magnetic disk
B. Registers
3
. The first digital computer built with IC chips was known as
A. IBM 7090
B. Apple – 1
C. IBM System / 360
D. VAX‐10
C. IBM System / 360
4
. Which of the following terms is the most closely related to main memory?
A. Non volatile
B. Permanent
C. Control unit
D. Temporary
D. Temporary
5
. Which of the following is used for manufacturing chips?
A. Control bus
B. Control unit
C. Parity unit
D. Semiconductor
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D. Semiconductor
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6
. To locate a data item for storage is
A. Field
B. Feed
C. Database
D. Fetch
D. Fetch
7
. A directly accessible appointment calendar is feature of a … resident package
A. CPU
B. Memory
C. Buffer
D. ALU
B. Memory
8
. The term gigabyte refers to
A. 1024 bytes
B. 1024 kilobytes
C. 1024 megabytes
D. 1024 gigabyte
C. 1024 megabytes
9
. A/n …. Device is any device that provides information, which is sent to the CPU
A. Input
B. Output
C. CPU
D. Memory
A. Input
10
. Current SIMMs have either … or … connectors (pins)
A. 9 or 32
B. 30 or 70
C. 28 or 72
D. 30 or 72
D. 30 or 72
1
. Which is the brain of computer:
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A. ALU
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B. CPU
C. MU
D. None of these
B. CPU
2
. Which technology using the microprocessor is fabricated on a single chip:
A. POS
B. MOS
C. ALU
D. ABM
B. MOS
3
. MOS stands for:
A. Metal oxide semiconductor
B. Memory oxide semiconductor
C. Metal oxide select
D. None of these
A. Metal oxide semiconductor
4
. In which form CPU provide output:
A. Computer signals
B. Digital signals
C. Metal signals
D. None of these
B. Digital signals
5
. The register section is related to______ of the computer:
A. Processing
B. ALU
C. Main memory
D. None of these
C. Main memory
6
. In Microprocessor one of the operands holds a special register called:
A. Calculator
B. Dedicated
C. Accumulator
D. None of these
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C. Accumulator
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7
. Which register is a temporary storage location:
A. general purpose register
B. dedicated register
C. A and B
D. none of these
C. A and B
8
. PC stands for:
A. Program counter
B. Points counter
C. Paragraph counter
D. Paint counter
A. Program counter
9
. IR stands for:
A. Intel register
B. In counter register
C. Index register
D. Instruction register
D. Instruction register
10
. SP stands for:
A. Status pointer
B. Stack pointer
C. a and b
D. None of these
B. Stack pointer
1
. The act of acquiring an instruction is referred as the____ the instruction:
A. Fetching
B. Fetch cycle
C. Both a and b
D. None of these
A. Fetching
2
. How many bit of instruction on our simple computer consist of one____:
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A. 2‐bit
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B. 6‐bit
C. 12‐bit
D. None of these
C. 12‐bit
3
. How many parts of single address computer instruction :
A. 1
B. 2
C. 3
D. 4
B. 2
4
. Single address computer instruction has two parts:
A. The operation code
B. The operand
C. A and B
D. None of these
C. A and B
5
. LA stands for:
A. Load accumulator
B. Least accumulator
C. Last accumulator
D. None of these
A. Load accumulator
6
. Which are the flags of status register:
A. Over flow flag
B. Carry flag
C. Half carry flag
D. Zero flag
E. All of these
E. All of these
7
. The carry is operand by:
A. C
B. D
C. S
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D. O
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A. C
8
. The sign is operand by:
A. S
B. D
C. C
D. O
A. S
9
. The zero is operand by:
A. Z
B. D
C. S
D. O
A. Z
10
. The overflow is operand by:
A. O
B. D
C. S
D. C
A. O
1
. _________ Stores the instruction currently being executed:
A. Instruction register
B. Current register
C. Both a and b
D. None of these
A. Instruction register
2
. In which register instruction is decoded prepared and ultimately executed:
A. Instruction register
B. Current register
C. Both a and b
D. None of these
A. Instruction register
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3
Rooma, Kanpur – 208 008
. The status register is also called the____:
A. Condition code register
B. Flag register
C. A and B
D. None of these
C. A and B
4
. The area of memory with addresses near zero are called:
A. High memory
B. Mid memory
C. Memory
D. Low memory
D. Low memory
5
. The processor uses the stack to keep track of where the items are stored on it this by using the:
A. Stack pointer register
B. Queue pointer register
C. Both a & b
D. None of these
A. Stack pointer register
6
. Stack words on:
A. LILO
B. LIFO
C. FIFO
D. None of these
B. LIFO
7
. Which is the basic stack operation:
A. PUSH
B. POP
C. BOTH A and B
D. None of these
C. BOTH A and B
8
. SP stand for:
A. Stack pointer
B. Stack pop
C. Stack push
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D. None of these
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A. Stack pointer
9
. How many bit stored by status register:
A. 1 bit
B. 4 bit
C. 6 bit
D. 8 bit
A. 1 bit
10
. The 16 bit register is separated into groups of 4 bit where each groups is called:
A. BCD
B. Nibble
C. Half byte
D. None of these
B. Nibble
Microprocessors MCQs Set-14
A+
A
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This section contains more frequently asked Microprocessors Fundamental MCQs in
the various University Level and Competitive Examinations.
1
. A nibble can be represented in the from of:
A. Octal digit
B. Decimal
C. Hexadecimal
D. None of these
C. Hexadecimal
2
. The left side of any binary number is called:
A. Least significant digit
B. Most significant digit
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C. Medium significant digit
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D. low significant digit
B. Most significant digit
3
. MSD stands for:
A. Least significant digit
B. Most significant digit
C. Medium significant digit
D. low significant digit
B. Most significant digit
4
. _____ a subsystem that transfer data between computer components inside a computer or
between computer:
A. Chip
B. Register
C. Processor
D. Bus
D. Bus
5
. The external system bus architecture is created using from ______ architecture:
A. Pascal
B. Dennis Ritchie
C. Charles Babbage
D. Von Neumann
D. Von Neumann
6
. Which bus carry addresses:
A. System bus
B. Address bus
C. Control bus
D. Data bus
B. Address bus
7
. A 16 bit address bus can generate___ addresses:
A. 32767
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B. 25652
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C. 65536
D. none of these
C. 65536
8
. CPU can read & write data by using :
A. Control bus
B. Data bus
C. Address bus
D. None of these
B. Data bus
9
. Which bus transfer singles from the CPU to external device and others that carry singles from
external device to the CPU:
A. Control bus
B. Data bus
C. Address bus
D. None of these
A. Control bus
10
. When memory read or I/O read are active data is to the processor :
A. Input
B. Output
C. Processor
D. None of these
A. Input
This section contains more frequently asked Microprocessors Basics Multiple Choice Questions
and Answers in the various University Level and Competitive Examinations.
1
. When memory write or I/O read are active data is from the processor:
A. Input
B. Output
C. Processor
D. None of these
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B. Output
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2
. CS stands for:
A. Cable select
B. Chip select
C. Control select
D. Cable system
B. Chip select
3
. WE stands for
A. Write enable
B. Wrote enable
C. Write envy
D. None of these
A. Write enable
4
. MAR stands for
A. Memory address register
B. Memory address recode
C. Micro address register
D. None of these
A. Memory address register
5
. MDR stands for
A. Memory data register
B. Memory data recode
C. Micro data register
D. None of these
A. Memory data register
6
. Which are the READ operation can in simple steps
A. Address
B. Data
C. Control
D. All of these
D. All of these
7
. DMA stands for
A. Direct memory access
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B. Direct memory allocation
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C. Data memory access
D. Data memory allocation
A. Direct memory access
8
. The ____ place the data from a register onto the data bus
A. CPU
B. ALU
C. Both A and B
D. None of these
A. CPU
9
. The microcomputer system by using the ____device interface
A. Input
B. Output
C. Both A and B
D. None of these
C. Both A and B
10
. The standard I/O is also called
A. Isolated I/O
B. Parallel I/O
C. both a and b
D. none of these
A. Isolated I/O
1
. The external device is connected to a pin called the ______ pin on the processor chip
A. Interrupt
B. Transfer
C. Both
D. None of these
A. Interrupt
2
. Which interrupt has the highest priority?
A. INTR
B. TRAP
C. RST6.5
D. none of these
B. TRAP
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3
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. In 8085 name the 16 bit registers?
A. Stack pointer
B. Program counter
C. a & b
D. none of these
C. a & b
4
. What are level Triggering interrupts?
A. INTR&TRAP
B. RST6.5&RST5.5
C. RST7.5&RST6.5
D. none of these
B. RST6.5&RST5.5
5
. Which stack is used in 8085?
A. FIFO
B. LIFO
C. FILO
D. none of these
B. LIFO
6
. What is SIM?
A. Select Interrupt Mask
B. Sorting Interrupt Mask
C. Set Interrupt Mask.
D. none of these
C. Set Interrupt Mask.
7
. RIM is used to check whether, ______
A. The write operation is done or not
B. The interrupt is Masked or not
C. a & b
D. none of these
B. The interrupt is Masked or not
8
. In 8086, Example for Non maskable interrupts are
A. Trap
B. RST6.5
C. INTR
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D. none of these
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A. Trap
9
. In 8086 microprocessor the following has the highest priority among all type interrupts.
A. NMI
B. DIV 0
C. TYPE 255
D. OVER FLOW
A. NMI
10
. BIU STAND FOR:
A. Bus interface unit
B. Bess interface unit
C. A and B
D. None of these
A. Bus interface unit
1
. EU STAND FOR
A. Execution unit
B. Execute unit
C. Exchange unit
D. None of these
A. Execution unit
2
. Which are the part of architecture of 8086
A. The bus interface unit
B. The execution unit
C. Both A and B
D. None of these
C. Both A and B
3
. Which are the four categories of registers:
A. General‐ purpose register
B. Pointer or index registers
C. Segment registers
D. Other register
E. All of these
E. All of these
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4
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. IP Stand for
A. Instruction pointer
B. Instruction purpose
C. Instruction paints
D. None of these
A. Instruction pointer
5
. CS Stand for
A. Code segment
B. Coot segment
C. Cost segment
D. Counter segment
A. Code segment
6
. DS Stand for
A. Data segment
B. Direct segment
C. Declare segment
D. Divide segment
A. Data segment
7
. Which are the segment
A. CS: Code segment
B. DS: data segment
C. SS: Stack segment
D. ES:extra segment
E. All of these
E. All of these
8
. The acculatator is 16 bit wide and is called
A. AX
B. AH
C. AL
D. DL
A. AX
9
. The upper 8 bit are called______
A. BH
B. BL
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C. AH
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D. CH
C. AH
10
. The lower 8 bit are called_______
A. AL
B. CL
C. BL
D. DL
A. AL
1
. IP stand for
A. Industry pointer
B. Instruction pointer
C. Index pointer
D. None of these
B. Instruction pointer
2
. Which has great important in modular programming
A. Stack segment
B. Queue segment
C. Array segment
D. All of these
A. Stack segment
3
. Which register containing the 8086/8088 flag
A. Status register
B. Stack register
C. Flag register
D. Stand register
A. Status register
4
. How many bits the instruction pointer is wide
A. 16 bit
B. 32 bit
C. 64 bit
D. 128 bit
A. 16 bit
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5
Rooma, Kanpur – 208 008
. How many type of addressing in memory
A. Logical address
B. Physical address
C. Both A and B
D. None of these
C. Both A and B
6
. The size of each segment in 8086 is
A. 64 kb
B. 24 kb
C. 50 kb
D. 16kb
A. 64 kb
7
. The physical address of memory is
A. 20 bit
B. 16 bit
C. 32 bit
D. 64 bit
A. 20 bit
8
. The _______ address of a memory is a 20 bit address for the 8086 microprocessor
A. Physical
B. Logical
C. Both
D. None of these
A. Physical
9
. The pin configuration of 8086 is available in the________
A. 40 pin
B. 50 pin
C. 30 pin
D. 20 pin
A. 40 pin
10
. DIP stand for
A. Deal inline package
B. Dual inline package
C. Direct inline package
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D. Digital inline package
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B. Dual inline package
This section contains more frequently asked Microprocessor and Microcontroller Multiple
Choice Questions and Answers in the various University Level and Competitive Examinations.
1
. PA stand for
A. Project address
B. Physical address
C. Pin address
D. Pointer address
B. Physical address
2
. SBA stand for
A. Segment bus address
B. Segment bit address
C. Segment base address
D. Segment byte address
C. Segment base address
3
. EA stand for
A. Effective address
B. Electrical address
C. Effect address
D. None of these
A. Effective address
4
. BP stand for
A. Bit pointer
B. Base pointer
C. Bus pointer
D. Byte pointer
B. Base pointer
5
. DI stand for
A. Destination index
B. Defect index
C. Definition index
D. Delete index
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A. Destination index
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6
. SI stand for
A. Stand index
B. Source index
C. Segment index
D. Simple index
B. Source index
7
. DS stand for
A. Default segment
B. Defect segment
C. Delete segment
D. Definition segment
A. Default segment
8
. ALE stand for
A. Address latch enable
B. Address light enable
C. Address lower enable
D. Address last enable
A. Address latch enable
9
. AD stand for
A. Address data
B. Address delete
C. Address date
D. Address deal
A. Address data
10
. NMI stand for
A. Non mask able interrupt
B. Non mistake interrupt
C. Both
D. None of these
A. Non mask able interrupt
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Microprocessors MCQs Set-20
Rooma, Kanpur – 208 008
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A
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This section contains more frequently asked Microprocessor and Micro-controller MCQs
in the various University Level and Competitive Examinations.
1
. PC stand for
A. program counter
B. project counter
C. protect counter
D. planning counter
A. program counter
2
. AH stand for
A. Accumulator high
B. Address high
C. Appropriate high
D. Application high
A. Accumulator high
3
. AL stand for
A. Accumulator low
B. Address low
C. Appropriate low
D. Application low
A. Accumulator low
4
. The offset of a particular segment varies from _________
A. 000H to FFFH
B. 0000H to FFFFH
C. 00H to FFH
D. 00000H to FFFFFH
B. 0000H to FFFFH
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5
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. ________ is usually the first level of memory access by the microprocessor
A. Cache memory
B. Data memory
C. Main memory
D. All of these
A. Cache memory
6
. which is the small amount of high‐ speed memory used to work directly with the
microprocessor
A. Cache
B. Case
C. Cost
D. Coos
A. Cache
7
. The cache usually gets its data from the_________ whenever the instruction or data is
required by the CPU
A. Main memory
B. Case memory
C. Cache memory
D. All of these
A. Main memory
8
. How many type of cache memory
A. 1
B. 2
C. 3
D. 4
C. 3
9
. Which is the type of cache memory
A. Fully associative cache
B. Direct‐mapped cache
C. Set‐associative cache
D. All of these
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D. All of these
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10
. Which memory is used to holds the address of the data stored in the cache
A. Associative memory
B. Case memory
C. Ordinary memory
D. None of these
A. Associative memory
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Microprocessors MCQs Set-21
A+
A
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This section contains more frequently asked Microprocessors 8085 Questions Bank
with Answers in the various University Level and Competitive Examinations.
1
. If the crystal oscillator is operating at 15 MHz, the PCLK output of 8284 is
A. 2.5 MHz.
B. 5 MHz.
C. 7.5 MHz.
D. 10 MHz.
A. 2.5 MHz.
2
. In which T-state does the CPU sends the address to memory or I/O and the ALE signal for
demultiplexing
A. T1.
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B. T2.
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C. T3.
D. T4.
A. T1.
3
. If a 1M ×1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more than
__________ of time must pass before another row is refreshed.
A. 64 ms.
B. 4 ns.
C. 0.5 ns.
D. 15.625 µs .
B. 4 ns.
4
. In a DMA write operation the data is transferred
A. from I/O to memory.
B. from memory to I/O.
C. from memory to memory.
D. from I/O to I/O.
A. from I/O to memory.
5
. Which type of JMP instruction assembles if the distance is 0020 h bytes
A. near.
B. far
C. short
D. none of the above.
A. near.
6
. A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following modes this
SRAM is operating
A. Read
B. Write
C. Stand by
D. None of the above
B. Write
7
. Which of the following is true with respect to EEPROM?
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A. contents can be erased byte wise only.
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B. contents of full memory can be erased together
C. contents can be erased using ultra violet rays
D. contents can not be erased
C. contents can be erased using ultra violet rays
8
. Pseudo instructions are basically
A. false instructions.
B. instructions that are ignored by the microprocessor
C. assembler directives
D. instructions that are treated like comments
C. assembler directives
9
. Number of the times the instruction sequence below will loop before coming out of loop is
MOV AL, 00h A1: INC AL JNZ A1
A. 0
B. 1
C. 255
D. 256
D. 256
10
. What will be the contents of register AL after the following has been executed MOV BL, 8C
MOV AL, 7E ADD AL, BL
A. 0A and carry flag is set
B. 0A and carry flag is reset
C. 6A and carry flag is set
D. 6A and carry flag is reset
A. 0A and carry flag is set
1
. Direction flag is used with
A. String instructions.
B. Stack instructions
C. Arithmetic instructions
D. Branch instructions
A. String instructions.
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2
Rooma, Kanpur – 208 008
. Ready pin of a microprocessor is used
A. to indicate that the microprocessor is ready to receive inputs
B. to indicate that the microprocessor is ready to receive outputs
C. to introduce wait states
D. to provide direct memory access
C. to introduce wait states
3
. These are two ways in which a microprocessor can come out of Halt state.
A. When hold line is a logical 1
B. When interrupt occurs and the interrupt system has been enabled
C. When both (A) and (B) are true
D. When either (A) or (B) are true
A. When hold line is a logical 1
4
. In the instruction FADD, F stands for
A. Far
B. Floppy
C. Floating
D. File
C. Floating
5
. SD RAM refers to
A. Synchronous DRAM
B. Static DRAM
C. Semi DRAM
D. Second DRAM
A. Synchronous DRAM
6
. In case of DVD, the speed is referred in terms of n X (for example 32 X). Here, X refers to
A. 150 KB/s
B. 300 KB/s
C. 1.38 MB/s
D. 2.4 MB/s
C. 1.38 MB/s
7
. Itanium processor of Intel is a
A. 32 bit microprocessor.
B. 64 bit microprocessor.
C. 128 bit microprocessor.
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D. 256 bit microprocessor
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B. 64 bit microprocessor.
8
. LOCK prefix is used most often
A. during normal execution.
B. during DMA accesses
C. during interrupt servicing
D. during memory accesses
C. during interrupt servicing
9
. The Pentium microprocessor has______execution units.
A. 1
B. 2
C. 3
D. 4
C. 3
10
. EPROM is generally erased by using
A. Ultraviolet rays
B. infrared rays
C. 12 V electrical pulse
D. 24 V electrical pulse
A. Ultraviolet ray
1
. Signal voltage ranges for a logic high and for a logic low in RS-232C standard are
A. Low = 0 volt to 1.8 volt, high = 2.0 volt to 5 volt
B. Low =-15 volt to –3 vol, high = +3 volt to +15 volt
C. Low = +3 volt to +15 volt, high = -3 volt to -15 volt
D. Low = 2 volt to 5.0 volt, high = 0 volt to 1.8 volt
B. Low =-15 volt to –3 vol, high = +3 volt to +15 volt
2
. The PCI bus is the important bus found in all the new Pentium systems because
A. It has plug and play characteristics
B. It has ability to function with a 64 bit data bus
C. Any Microprocessor can be interfaced to it with PCI controller or bridge
D. All of the above
D. All of the above
3
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. Which of the following statement is true?
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A. The group of machine cycle is called a state.
B. A machine cycle consists of one or more instruction cycle.
C. An instruction cycle is made up of machine cycles and a machine cycle is made up of
number of states.
D. None of the above
B. A machine cycle consists of one or more instruction cycle.
4
. 8251 is a
A. UART
B. USART
C. Programmable Interrupt controller
D. Programmable interval timer/counter
B. USART
5
. 8088 microprocessor has
A. 16 bit data bus
B. 4 byte pre-fetch queue
C. 6 byte pre-fetch queue
D. 16 bit address bus
D. 16 bit address bus
6
. By what factor does the 8284A clock generator divide the crystal oscillator’s output frequency?
A. One
B. Two
C. Three
D. Four
C. Three
7
. The memory data bus width in Pentium is
A. 16 bit
B. 32 bit
C. 64 bit
D. None of these
C. 64 bit
8
. When the 82C55 is reset, its I/O ports are all initializes as
A. output port using mode 0
B. Input port using mode 1
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C. output port using mode 1
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D. Input port using mode 0
D. Input port using mode 0
9
. Which microprocessor pins are used to request and acknowledge a DMA transfer?
A. reset and ready
B. ready and wait
C. HOLD and HLDA
D. None o these
C. HOLD and HLDA
10
. Which of the following statement is false?
A. RTOS performs tasks in predictable amount of time
B. Windows 98 is RTOS
C. Interrupts are used to develop RTOS
D. Kernel is the one of component of any OS
B. Windows 98 is RTOS
1
. The VESA local bus operates at
A. 8 MHz
B. 33 MHz
C. 16 MHz
D. None of these
B. 33 MHz
2
. The first modern computer was called_____________
A. FLOW-MATIC
B. UNIVAC-I
C. ENIAC
D. INTEL
C. ENIAC
3
. Software command CLEAR MASK REGISTER in DMA
A. Disables all channels.
B. Enables all channels.
C. None
D. Clears first/last flip-flop within 8237.
B. Enables all channels.
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4
. The first task of DOS operating system afterRooma, Kanpur – 208 008
loading into the memory is to use the file
called___________
A. HIMEM.SYS
B. CONFIG.SYS
C. AUTOEXEC.BAT
D. SYSTEM.INI
B. CONFIG.SYS
5
. If the programmable counter timer 8254 is set in mode 1 and is to be used to count six events, the
output will remain at logic 0 for _____ number of counts
A. 5
B. 6
C. All of the above
B. 6
6
. The flash memory is programmed in the system by 12 V programming pulse
A. TRUE
B. FALSE
A. TRUE
7
. A plug and play (PnP) interface is one that contains a memory that holds configuration
information of the system
A. 1
A. 1
8
. The accelerated graphics port (AGP) allows virtually any microprocessor to be interfaced with
PCI bus via the use of bridge interface
A. 1
A. 1
9
. A Bus cycle is equal to how many clocking periods
A. Two
B. Three
C. Four
D. Six
C. Four
10
. The time required to refresh a typical DRAM is
A. 2 – 4 us
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B. 2 – 4 ns
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C. 2 – 4 ms
D. 2 – 4 ps
C. 2 – 4 ms
This section contains more frequently asked Microprocessors 8085 Basics MCQs in the various
University Level and Competitive Examinations.
1
. The no. of address lines required to address a memory of size 32 K is
A. 15 lines
B. 16 lines
C. 18 lines
D. 14 lines
A. 15 lines
2
. The no. of wait states required to interface 8279 to 8086 with 8MHz clock are
A. Two
B. Three
C. One
D. None
A. Two
3
. NMI input is
A. Edge sensitive
B. Level sensitive
C. Both edge and level triggered
D. edge triggered and level sensitive
D. edge triggered and level sensitive
4
. Data rate available for use on USB is
A. 12 Mbits per second
B. 1.5 Mbits per second
C. Both (A) and (B)
D. No restriction
C. Both (A) and (B)
5
. In 80186, the timer which connects to the system clock is
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A. timer 0
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B. timer 1
C. timer 2
D. Any one can be connected
C. timer 2
6
. Conversion of the +1000 decimal number into signed binary word results
A. 0000 0011 1110 1000
B. 1111 1100 0001 1000
C. 1000 0011 1110 1000
D. 0111 1100 0001 1000
C. 1000 0011 1110 1000
7
. What do the symbols [ ] indicate?
A. Direct addressing
B. Register Addressing
C. Indirect addressing
D. None of the above
C. Indirect addressing
8
. SDRAM refers to
A. static DRAM
B. synchronous DRAM
C. sequential DRAM
D. semi DRAM
B. synchronous DRAM
9
. Which pins are general purpose I/O pins during mode-2 operation of the 82C55?
A. PA0 – PA7
B. PB0-PB7
C. PC3-PC7
D. PC0-PC2
A. PA0 – PA7
1. A microprocessor is a chip integrating all the functions of a CPU of a computer. A. multiple B. single C. double D. triple
ANSWER: B
2. Microprocessor is a/an circuit that functions as the CPU of the compute A. electronic B. mechanic C. integrating D.
processing ANSWER: A
3. Microprocessor is the of the computer and it perform all the computational tasks A. main B. heart C. important D.
simple ANSWER: B
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4. The purpose of the microprocessor is to control A. memory B. switches C. processing D. tasks ANSWER: A
5. The first digital electronic computer was built in the Rooma,
year A.Kanpur
1950 B.– 208
1960008C. 1940 D. 1930 ANSWER: C 6. In 1960's texas
institute invented A. integrated circuits B. microprocessor C. vacuum tubes D. transistors ANSWER: A
7. The intel 8086 microprocessor is a processor A. 8 bit B. 16 bit C. 32 bit D. 4 bit ANSWER: B
8. The microprocessor can read/write 16 bit data from or to A. memory B. I /O device C. processor D. register ANSWER:
A
9. In 8086 microprocessor , the address bus is bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit ANSWER: D 10. The work of
EU is A. encoding B. decoding C. processing D. calculations ANSWER: B 11. The 16 bit flag of 8086 microprocessor is
responsible to indicate A. the condition of result of ALU operation B. the condition of memory C. the result of addition D.
the result of subtraction ANSWER: A
12. The CF is known as A. carry flag B. condition flag C. common flag D. single flag .ANSWER: A
13. The SF is called as A. service flag B. sign flag C. single flag D. condition flag ANSWER: B
14. The OF is called as A. overflow flag B. overdue flag C. one flag D. over flag ANSWER: A
15. The IF is called as A. initial flag B. indicate flag C. interrupt flag D. inter flag ANSWER: C
16. The register AX is formed by grouping A. AH & AL B. BH & BL C. CH & CL D. DH & DL ANSWER: A
17. The SP is indicated by A. single pointer B. stack pointer C. source pointer D. destination pointer ANSWER: B
18. The BP is indicated by A. base pointer B. binary pointer C. bit pointer D. digital pointer ANSWER: A
19. The SS is called as A. single stack B. stack segment C. sequence stack .D. random stack ANSWER: B
20. The index register are used to hold A. memory register B. offset address C. segment memory D. offset memory
ANSWER: A
21. The BIU contains FIFO register of size bytes A. 8 B. 6 C. 4 D. 12 ANSWER: B
22. The BIU prefetches the instruction from memory and store them in A. queue B. register C. memory D. stack ANSWER:
A
23. The 1 MB byte of memory can be divided into segment A. 1 Kbyte B. 64 Kbyte C. 33 Kbyte D. 34 Kbyte ANSWER: B
24. The DS is called as A. data segment B. digital segment C. divide segment D. decode segment ANSWER: A
25. The CS register stores instruction in code segment A. stream B. path C. codes D. stream line ANSWER: C
26. The IP is bits in length A. 8 bits B. 4 bits C. 16 bits D. 32 bits ANSWER: C
27. The push source copies a word from source to A. stack B. memory C. register D. destination ANSWER: A
28. LDs copies to consecutive words from memory to register and A. ES B. DS C. SS D. CS ANSWER: B
29. INC destination increments the content of destination by A. 1 B. 2 C. 30 D. 41
30. IMUL source is a signed A. multiplication B. addition C. subtraction D. division ANSWER: A
31. destination inverts each bit of destination A. NOT B. NOR C. AND D. OR ANSWER: A
32. The JS is called as A. jump the signed bit B. jump single bit C. jump simple bit D. jump signal it ANSWER: A
33. Instruction providing both segment base and offset address are called A. below type .B. far type C. low type D. high
type ANSWER: B
34. The conditional branch instruction specify for branching A. conditions B. instruction C. address D. memory ANSWER:
A
35. The microprocessor determines whether the specified condition exists or not by testing the A. carry flag B. conditional
flag C. common flag D. sign flag ANSWER: B
36. The LES copies to words from memory to register and A. DS B. CS C. ES D. DS ANSWER: C
37. The translates a byte from one code to another code A. XLAT B. XCHNG C. POP D. PUSH ANSWER: A 38. The contains
an offset instead of actual address A. SP B. IP C. ES D. SS ANSWER: B
39. The 8086 fetches instruction one after another from of memory A. code segment B. IP C. ES D. SS ANSWER: A
40. The BIU contains FIFO register of size 6 bytes called . A. queue B. stack C. segment D. register ANSWER: A
41. The is required to synchronize the internal operands in the processor CLK Signal A. UR Signal B. Vcc C. AIE D. Ground
ANSWER: A
42. The pin of minimum mode AD0-AD15 has address A. 16 bit B. 20 bit C. 32 bit D. 4 bit ANSWER: B
43. The pin of minimum mode AD0- AD15 has _ data bus A. 4 bit B. 20 bit C. 16 bit D. 32 bit ANSWER: C
44. The address bits are sent out on lines through ANSWER: B A. A16-19 B. A0-17 C. D0-D17 D. C0-C17 ANSWER: A
45. is used to write into memory A. RD B. WR C. RD / WR D. CLK ANSWER: B 46. The functions of Pins from 24 to 31
depend on the mode in which is operating A. 8085 B. 8086 C. 80835 D. 80845 ANSWER: B
47. The RD, WR, M/IO is the heart of control for a mode A. minimum B. maximum C. compatibility mode D. control mode
ANSWER: A
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48. In a minimum mode there is a on the system bus A. single B. double C. multiple D. triple ANSWER: A 49. If MN/MX is
low the 8086 operates in mode A. Minimum B. Maximum Rooma, Kanpur
C. both (A)– and
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(B) D. medium ANSWER: B
50. In max mode, control bus signal So,S1 and S2 are sent out in form A. decoded B. encoded C. shared D. unshared
ANSWER: B
51. The bus controller device decodes the signals to produce the control bus signal A. internal B. data C. external D.
address ANSWER: C
52. A Instruction at the end of interrupt service program takes the execution back to the interrupted program A. forward
B. return C. data D. line ANSWER: B
53. The main concerns of the are to define a flexible set of commands A. memory interface B. peripheral interface C.
both (A) and (B) D. control interface .ANSWER: A
54. Primary function of memory interfacing is that the should be able to read from and write into register A.
multiprocessor B. microprocessor C. dual Processor D. coprocessor ANSWER: B
55. To perform any operations, the Mp should identify the A. register B. memory C. interface D. system ANSWER: A
56. The Microprocessor places address on the address bus A. 4 bit B. 8 bit C. 16 bit D. 32 bit ANSWER: C
57. The Microprocessor places 16 bit address on the add lines from that address by register should be selected A. address
B. one C. two D. three ANSWER: B
58. The of the memory chip will identify and select the register for the EPROM A. internal decoder B. external decoder
C. address decoder D. data decoder ANSWER: A
59. Microprocessor provides signal like to indicate the read operatio A. LOW B. MCMW C. MCMR D. MCMWR ANSWER:
C
60. To interface memory with the microprocessor, connect register the lines of the address bus must be added to address
lines of the chip. A. single B. memory C. multiple D. triple ANSWER: B
61. The remaining address line of bus is decoded to generate chip select signal A. data B. address C. control bus D. both
(a) and (b) ANSWER: B
62. signal is generated by combining RD and WR signals with IO/M A. control B. memory C. register D. system ANSWER:
A
63. Memory is an integral part of a system A. supercomputer B. microcomputer C. mini computer D. mainframe computer
ANSWER: B
64. has certain signal requirements write into and read from its registers A. memory B. register C. both (a) and (b) D.
control ANSWER: A
65. An is used to fetch one address A. internal decoder B. external decoder C. encoder D. register ANSWER: A
66. The primary function of the is to accept data from I/P devices A. multiprocessor B. microprocessor C. peripherals D.
interfaces ANSWER: B
67. signal prevent the microprocessor from reading the same data more than one A. pipelining B. handshaking C.
controlling D. signaling ANSWER: B
68. Bits in IRR interrupt are A. reset B. set C. stop D. start ANSWER: B
69. generate interrupt signal to microprocessor and receive acknowledge A. priority resolver B. control logic C. interrupt
request register D. interrupt register ANSWER: B
70. The pin is used to select direct command word A. A0 B. D7-D6 C. A12 D. AD7-AD6 ANSWER: A
71. The is used to connect more microprocessor A. peripheral device B. cascade C. I/O devices D. control unit
72. CS connect the output of A. encoder B. decoder C. slave program D. buffer ANSWER: B
73. In which year, 8086 was introduced? A. 1978 B. 1979 C. 1977 D. 1981 ANSWER: A
74. Expansion for HMOS technology_ A. high level mode oxygen semiconductor B. high level metal oxygen semiconductor
C. high performance medium oxide semiconductor D. high performance metal oxide semiconductor ANSWER: D
75. 8086 and 8088 contains transistors A. 29000 B. 24000 C. 34000 D. 54000 ANSWER: A
76. ALE stands for A. address latch enable B. address level enable C. address leak enable D. address leak extension
ANSWER: A
77. What is DEN? A. direct enable B. data entered C. data enable D. data encoding ANSWER: C
78. In 8086, Example for Non maskable interrupts are . A. TRAP B. RST6.5 C. INTR D. RST6.6 ANSWER: A 79. In 8086 the
overflow flag is set when . A. the sum is more than 16 bits. B. signed numbers go out of their range after an arithmetic
operation. C. carry and sign flags are set. D. subtraction ANSWER: B
80. In 8086 microprocessor the following has the highest priority among all type interrupts? A. NMI B. DIV 0 C. TYPE 255
D. OVER FLOW ANSWER: A
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81. In 8086 microprocessor one of the following statements is not true? A. coprocessor is interfaced in max mode. B.
coprocessor is interfaced in min mode. C. I /O can be Rooma, Kanpur
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in max min mode. D. supports pipelining ANSWER: B
82. Address line for TRAP is? A. 0023H B. 0024H C. 0033H D. 0099H ANSWER: B
83. Access time is faster for . A. ROM B. SRAM C. DRAM D. ERAM ANSWER: B
84. The First Microprocessor was . A. Intel 4004 B. 8080 C. 8085 D. 4008 ANSWER: A
85. Status register is also called as . A. accumulator B. stack C. counter D. flags ANSWER: D
86. Which of the following is not a basic element within the microprocessor? A. Microcontroller B. Arithmetic logic unit
(ALU) C. Register array D. Control unit Ans.: A
87. Which method bypasses the CPU for certain types of data transfer? A. Software interrupts B. Interrupt-driven I/O C.
Polled I/O D. Direct memory access (DMA) Ans.: D
88. Which bus is bidirectional? A. Address bus B. Control bus C. Data bus D. None of the above Ans.: C
89. The first microprocessor had a(n) . A. 1 – bit data bus B. 2 – bit data bus C. 4 – bit data bus D. 8 – bit data bus Ans.: C
90. Which microprocessor has multiplexed data and address lines? A. 8086 B. 80286 C. 80386 D. Pentium Ans.: A
91. Which is not an operand? A. Variable B. Register C. Memory location D. Assembler Ans.: D
92. Which is not part of the execution unit (EU)? A. Arithmetic logic unit (ALU) B. Clock C. General registers D. Flags Ans.:
B
93. A 20-bit address bus can locate . A. 1,048,576 locations B. 2,097,152 locations C. 4,194,304 locations D. 8,388,608
locations Ans.: A
94. Which of the following is not an arithmetic instruction? A. INC (increment) B. CMP (compare) C. DEC (decrement) D.
ROL (rotate left) Ans.: D
95. During a read operation the CPU fetches _. A. a program instruction B. another address C. data itself D. all of the
above Ans.: D
96. Which of the following is not an 8086/8088 general-purpose register? A. Code segment (CS) B. Data segment (DS) C.
Stack segment (SS) D. Address segment (AS) Ans.: D
97. A 20-bit address bus allows access to a memory of capacity A. 1 MB B. 2 MB C. 4 MB D. 8 MB Ans.: A
98. Which microprocessor accepts the program written for 8086 without any changes? A. 8085 B. 8086 C. 8087 D. 8088
Ans.: D
99. Which group of instructions do not affect the flags? A. Arithmetic operations B. Logic operations C. Data transfer
operations D. Branch operations Ans.: C
100. The result of MOV AL, 65 is to store A. store 0100 0010 in AL B. store 42H in AL C. store 40H in AL D. store 0100 0001
in AL Ans.: D
Important Theory
1.
In one’s complement 8 bit representation 11111111 represents
A. +0
B. -0
C. +1
D. -1
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Answer & Solution
Answer: Option B
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2.
Circuit A is a 1-bit adder; circuit B is a 1 bit multiplier.
[Hint: Construct the truth table for the adder and the multiplier]
A. Circuit A has more gates than circuit B
B. Circuit B has more gates than circuit A
C. Circuit A has the same number of gates as circuit B
D. None of the above
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Answer & Solution
Answer: Option A
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3.
An e-mail message can be sent to many recipients.
A. True
B. False
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Answer & Solution
Answer: Option A
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For the number A[15:0] = 0110110010001111, A[14:13] is ______ A[3:2].
A. Less than
B. Greater than
C. The same as
D. Cannot be determined
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Answer & Solution
Answer: Option C
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5.
The five flags in 8085 are designated as
A. Z, CY, S, P and AC
B. D, Z, S, P, AC
C. Z, C, S, P, AC
D. Z, CY, S, D, AC
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Answer & Solution
Answer: Option A
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A 37 bit mantissa has an accuracy of
A. 6 decimal places
B. 8 decimal places
C. 10 decimal places
D. 11 decimal places
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Answer & Solution
Answer: Option D
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7.
DS directive in 8085
A. Forces the assembler to reserve one byte of memory
B. Forces the assembler to reserve a specified number of bytes in the memory
C. Forces the assembler to reserve a specified number of consecutive bytes in the memory
D. None of the above
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Answer & Solution
Answer: Option C
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Because we wish to allow each ASCII code to occupy one location in
memory, most memories are __________ addressable.
A. BYTE
B. NIBBLE
C. WORD (16 bits)
D. DOUBLEWORD (32 bits)
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Answer & Solution
Answer: Option A
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9.
We say that a set of gates is logically complete if we can build any circuit
without using any other kind of gates. Which of the following sets are
logically complete
A. Set of {AND,OR}
B. Set of {EXOR, NOT}
C. Set of {AND,OR,NOT}
D. None of the above
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Answer & Solution
Answer: Option C
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10. Rooma, Kanpur – 208 008
In a C expression using assignment operators, relational operators and
arithmetic operators, the hierarchy of operations (in the absence of
parenthesis) is
A. Assignment, relational, arithmetic
B. Relational, assignment, arithmetic
C. Arithmetic, assignment, relational
D. Arithmetic, relational, assignment
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Answer & Solution
Answer: Option D
Important Theory
11.
In 8086 the number of bytes which can be addressed directly is about
A. 1000
B. 10000
C. 100000
D. one million
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Answer & Solution
Answer: Option D
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12.
In a computer the data transfer between hard disk and CPU is nearly the same as that
between diskette and CPU.
A. True
B. False
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Answer & Solution
Answer: Option B
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13.
Which of the following pair of gates can form a latch?
A. A pair of cross coupled OR
B. A pair of cross copled AND
C. A pair of cross coupled NAND
D. A cross coupled NAND/OR
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Answer & Solution
Answer: Option C
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14.
Assertion (A): Each memory chip has its own address latch.
Reason (R): ALE signal comes out of microprocessor 8085 and goes to memory chip.
A. Both A and R are correct and R is correct explanation of A
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B. Both A and R are correct but R is not correct explanation
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C. A is correct R is wrong
D. A is wrong R is correct
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Answer & Solution
Answer: Option D
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15.
When the write enable input is not asserted, the gated D latch _________ its output.
A. Can not change
B. Clears
C. Sets
D. Complements
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Answer & Solution
Answer: Option A
For a memory with a 16-bit address space, the addressability is
A. 16 bits
B. 8 bits
C. 2^16 bits
D. Cannot be determined
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Answer & Solution
Answer: Option D
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17.
Which of the following is a valid integer constant?
A. 127
B. 127.0
C. 127
D. 125 + 3
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Answer & Solution
Answer: Option A
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18.
In 8085
A. P flag is set when the result has even parity
B. P flag is set when the result has odd parity
C. P flag is reset when the result has odd parity
D. P flag is reset when the result has even parity
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Answer & Solution Rooma, Kanpur – 208 008
Answer: Option A
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19.
In 8085 which addressing mode is also called inherent addressing?
A. Direct
B. Register
C. Implicit
D. Immediate
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Answer & Solution
Answer: Option C
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20.
Internet is a worldwide network of computers where most of the information
is freely available.
A. True
B. False
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Answer & Solution
Answer: Option A
Important Theory
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21. Rooma, Kanpur – 208 008
A real number consists of
A. Integer part
B. Integer part and fraction part
C. Integer part, fraction part along with positive or negative sign
D. None of the above
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Answer & Solution
Answer: Option C
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22.
Using DeMorgan’s Theorem we can convert any AND-OR structure into
A. NAND-NAND
B. OR-NAND
C. NAND-NOR
D. NOR-NAND
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Answer & Solution
Answer: Option A
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If the sign bit of mantissa is 0 and the exponent is increased from a positive
to a more negative number the result is
A. A larger floating point number
B. A smaller floating point number
C. Either A or B depending on the actual number
D. A negative floating point number
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Answer & Solution
Answer: Option A
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24.
The operating modes of 8255 A are called
A. Mode 0 and mode 1
B. Mode 0, mode 1 and mode 2
C. Mode 0 and mode 2
D. Mode 0, mode 2 and mode 3
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Answer & Solution
Answer: Option B
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In C the keywords are also called
A. Special words
B. Reserved words
C. Class words
D. Character words
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Answer & Solution
Answer: Option B
Important Theory
26.
The forms of IF statements in FORTRAN 77 are called
A. Logical IF and Block IF
B. Logical IF, block IF and arithmetic IF
C. Logic IF, block IF, arithmetic IF and negate IF
D. Logical IF and arithmetic IF
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Answer & Solution
Answer: Option B
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Which of the following conditions is not allowed in an RS latch?
A. R is asserted, S is asserted
B. R is asserted, S is negated
C. R is negated, S is asserted
D. R is negated, S is negated
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Answer & Solution
Answer: Option A
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28.
If m is a power of 2, the number of select lines required for an m-input mux is:
A. m
B. 2^m
C. log2 (m)
D. 2*m
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Answer & Solution
Answer: Option C
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The timing difference between a slow memory and fast processor can be resolved if
A. Processor is capable of waiting
B. External buffer is used
C. Either A or B
D. Neither A nor B
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Answer & Solution
Answer: Option C
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30.
Which memory has read operation, byte erase, byte write and chip erase?
A. RAM
B. UVEPROM
C. EEPROM
D. Both B and C
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Answer & Solution
Answer: Option C
31.
The character set of Fortran 77 includes lower case alphabets a to z.
A. True
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Answer & Solution
Answer: Option B
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32.
A structure that stores a number of bits taken “together as a unit” is a
A. Gate
B. Mux
C. Decoder
D. Register
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Answer & Solution
Answer: Option D
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33.
Each instruction in assembly language program has the following fields:
Lable field
Mnemonic field
Operand field
Comment field
The correct sequence of these fields is?
A. 1, 2, 3, 4
B. 1, 2, 4, 3
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D. 2, 1, 4, 3
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Answer & Solution
Answer: Option A
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34.
Which of the following is type declaration statement in C?
A. int bar
B. s=s+1
C. king = horse + 1
D. prin = prin * prin
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Answer & Solution
Answer: Option A
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35.
If the number of address bits in a memory is reduced by 2 and the
addressability is doubled, the size of the memory (i.e., the number of bits
stored in the memory)
A. Doubles
B. Remains unchanged
C. Halves
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Answer & Solution
Answer: Option C
36.
The number of interrupt lines in 8085 is
A. 2
B. 3
C. 4
D. 5
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Answer & Solution
Answer: Option D
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37.
Assertion (A): Negative values of incremental operator in DO loop are
allowed in Fortran 77 but not in earlier versions of Fortran.
Reason (R): Fortran 77 has better array facilities than earlier versions of
Fortran.
A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is correct R is wrong
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Answer & Solution
Answer: Option B
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38.
The minimum number of transistors required to implement a two input AND
gate is
A. 2
B. 4
C. 6
D. 8
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Answer & Solution
Answer: Option C
No explanation is given for this question Let's Discuss on Board
39.
Which of the following is not treated as hexadecimal constant by assembler
in 8085?
A. 45 H
B. 6 AFH
C. 234
D. 64 H
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Answer & Solution
Answer: Option C
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40.
IC 7485 cannot be cascadeD.
A. True
B. False
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Answer & Solution
Answer: Option B
41.
‘Burst refresh’ in DRAM is also called
A. Concentrated refresh
B. Distributed refresh
C. Hidden refresh
D. None of the above
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Answer & Solution
Answer: Option A
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42. Rooma, Kanpur – 208 008
When .9432 E – 4 is subtracted from .5452 E – 3 in normalized floating
point mode
A. None of the numbers is changed
B. .9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed
C. .5452 E – 3 is changed to 5.452 E – 4 but .9432 E – 4 is not changed
D. Both Ihe numbers are changed and their exponents are, made equal to -5
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Answer & Solution
Answer: Option B
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43.
In 8085, the pins for SID and SOD are
A. 4 and 5 respectively
B. 5 and 4 respectively
C. 3 and 4 respectively
D. 4 and 3 respectively
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Answer & Solution
Answer: Option B
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An I/O processor controls the flow of information between
A. Cache memory and I/O devices
B. Main memory and I/O devices
C. Two I/O devices
D. Cache and main memory
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Answer & Solution
Answer: Option B
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45.
Of the following circuits, the one which involves storage is
A. RS Latch
B. Mux
C. Nand
D. Decoder
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Answer & Solution
Answer: Option A
Important Theory
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MS Access is a DBMS software.
A. True
B. False
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Answer & Solution
Answer: Option A
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47.
Which of the following is not a general purpose peripheral?
A. I/O port
B. Programmable interrupt controller
C. Programmable CRT controller
D. Programmable interval timer
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Answer & Solution
Answer: Option C
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48.
In Fortran 77 a variable name can contain special characters.
A. True
B. False
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Answer: Option B
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49.
It is possible to copy a file in the same directory.
A. True
B. False
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Answer & Solution
Answer: Option A
01․ FPGA means
Field Programmable Gate Array
Forward Programmable Gate Array
Forward Parallel Gate Array
Field Parallel Gate Array
Field Programmable Gate Array (FPGA) is the re-configurable hardware, which consists
of millions of logic gates which could be arranged according to the user's demand. They
also have much higher frequency compared to micro controllers.
02․ Which language could be used for programming an FPGA.
Verilog
VHDL
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Both A and B Rooma, Kanpur – 208 008
None
Verilog and VHDL are the hardware description languages that are used for the
programming of FPGAs. Both of these languages are case-insensitive in nature.
03․ What is mean by ALU
Arithmetic logic upgrade
Arithmetic logic unsigned
Arithmetic local unsigned
Arithmetic logic unit
It is used for arithmetic operations...
04․ Which one of the following is not a vectored interrupt?
TRAP.
INTR.
RST 7.5.
RST 3.
Here TRAP, INTR, RST 7.5 are vectored interrupts. But RST 3 is not a vectored interrupt.
05․ 8085 microprocessor has how many pins
30.
39.
40.
41.
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Intel 8085 NMOS microprocessor is a 8 bit, 40 pins IC. It is a 40 pin I.C. package
fabricated on a single LSI chip. The Intel 8085 uses a single + 5 V DC supply for its
operation.Its clock speed is about 3 MHz. The clock cycle is 320 ns. It has 80 basic
instructions and 246 opcodes.
06․ In 8085 microprocessor, the RST6 instruction transfer programme execution to
following location
0030H.
0024H.
0048H.
0060H.
07․ HLT opcode means
load data to accumulator.
store result in memory.
load accumulator with contents of register.
end of program.
HLT opcode in 8085 microprocessor means end of program.
08․ In 8085 name/names of the 16 bit registers is/are
stack pointer.
program counter.
both A and B.
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Program counter (PC) and Stack pointer (SP) are basically used to hold 16 - bit memory
addresses. PC stores the 16-bit memory address of the next instruction to be fetched. SP
can be used to temporarily store the 16 - bit memory address as well as data. So PC and
SP are 16-bit registers.
09․ What is SIM?
Select interrupt mask.
Sorting interrupt mask.
Set interrupt mask.
None of these.
SIM stands for set interrupt mask which is handling the interrupts in 8085
microprocessor.
10․ The ROM programmed during manufacturing process itself is called
MROM
PROM
EPROM
EEPROM
ROM’s are two types.
1. Permanent ROMs
MROM
PROM
2. Erasable ROMs
EPROM
EEPROM
The ROM programmed during manufacturing process itself is called MROM. Data is
stored by the manufacturer during fabrication and user can not alter this data.
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01․ A field programmable ROM is called
MROM
PROM
FROM
FPROM
ROM’s are two types.
1. Permanent ROM’s a) MROM b) PROM
2. Erasable ROM’s a) EPROM b) EEPROM
In PROM data is stored by user. Only one time programmable and reprogramming is not
possible.
02․ A combinational PLD with a fixed AND array and a programmable OR array is called
a
PLD
PROM
PAL
PLA
ROM – Fixed AND array and fixed OR array PROM – Fixed AND array and
Programmable OR array PAL – Programmable AND array and fixed OR array PLA –
Programmable AND array and programmable OR array
03․ A combinational PLD with a programmable AND array and a fixed OR array is called
a
PLD
PROM
PAL
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PLA Rooma, Kanpur – 208 008
ROM – Fixed AND array and fixed OR array PROM – Fixed AND array and
Programmable OR array PAL – Programmable AND array and fixed OR array PLA –
Programmable AND array and programmable OR array
04․ A combinational PLD with a programmable AND array and a programmable OR
array is called a
PLD
PROM
PAL
PLA
ROM – Fixed AND array and fixed OR array PROM – Fixed AND array and
Programmable OR array PAL – Programmable AND array and fixed OR array PLA –
Programmable AND array and programmable OR array
05․ A mask programmed ROM is
programmed at the time of fabrication
programmed by the user
erasable and programmable
erasable electrically
The ROM programmed during manufacturing process itself is called MROM. Data is
stored by the manufacturer during fabrication and user can not alter the data. In PROM
data is stored by user. Only one time programmable and reprogramming is not possible.
In EPROM erasing is done using UV light and programming is through electrical.
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06․ The length of bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an
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indeterminate number of wait state clock cycles denoted by Tw. The wait states are always
inserted between
T1 & T2
T2 & T3
T3 & T4
T4 & T1
The wait states are always inserted between T3 & T4
07․ Which one of the following circuits transmits two messages simultaneously in one
direction
Duplex
Diplex
Simplex
Quadruplex
Diplex circuits transmits two messages simultaneously.
08․ The number of output pins in 8085 microprocessors are
27.
40.
21.
19.
In 8085 microprocessor there are 40 pins out of which 27 are output pins and rest 13 are
including clock input, power supply and other input pins.
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09․ The program counter in a 8085 micro-processor is a 16-bit register, because
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It counts 16-bits at a time
There are 16 address lines
It facilitates the user storing 16-bit data temporarily
It has to fetch two 8-bit data at a time
Program counter stores the address of next instruction to be fetched. AS 8085 address is
of 16-bit so program counter has to be of 16-bit.
10․ A microprocessor is ALU
and control unit on a single chip.
and memory on a single chip.
register unit and I/O device on a single chip.
register unit and control unit on a single chip.
A microprocessor is a semiconductor component designed by using VLSI technology and
it contains ALU, Control unit (CU) and registers of a CPU in a single package
03․ Which of the following statements for intel 8085 is correct?
Program Counter (PC) specifies the address of the instruction last executed
PC specifies the address of the instruction being executed
PC specifies the address of the instruction to be executed
PC specifies the number of instructions executed so far
Program counter contains the address of the instruction to be fetched.
04․ A good assembly language programmer should use general purpose registers rather
than memory in maximum possible ways for data processing. This is because:
Data processing with registers is easier than with memory
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Data processing with memory requires more
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with registers
Of limited set of instructions for data processing with memory
Data processing with registers takes fewer cycles than that with memory
Data processing with registers takes fewer cycle than with memory which require extra
memory read or write signal.
05․ Which one of the following is not correct?
Bus is a group of wires
Bootstrap is a technique or device for loading first instruction
An instruction is a set of bits that defines a computer operation
An interrupt signal is required at the start of every program
Interrupt is required for interruption of main program to perform a subroutine. It may be
used at the start of some program as per requirement but it is not mandatory at start of
every program.
06․ I)A total of about one million bytes can be directly addressed by the 8086
microprocessor II)8086 has thirteen 16-bit registers III)8086 has eight flags IV)Compared
to 8086, the 80286 provides a higher degree of memory protection Which one of the
statements given above are correct?
2,3&4
1,3 &4
1,2 & 4
1,2 & 3
→ 8086 has 9 flags i.e. CF, PF, AF, ZF, SF, TF, IF, DF, OF → 8086 has 20 address lines so it
can address 220 = 1Mbyte memory location. → 8086 has thirteen 16-bit registers.
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07․ The processor status word of 8085 microprocessor has five flags namely:
S, Z, AC, P, CY
S, OV, AC, P, CY
S, Z, OV, P, CY
S, Z, AC, P, OV
8085 microprocessor has 5 status flag S → Sign flag Z → Zero flag AC → Auxiliary carry
flag P → Parity flag CY → Carry flag
08․ What are the sets of commands in a program which are not translated into machine
instructions during assembly process, called?
Mnemonics
Directives
Identifiers
Operands
Directives are not translated into machine instruction during assembly process.
09․ The cycle required to fetch and execute an instruction in a 8085 microprocessor is
which one of the following?
Clock cycle
Memory cycle
Machine cycle
Instruction cycle
One machine cycle is equivalent to one memory access. Clock cycle implies one clock
period. Instruction cycle includes fetching and execution of a given instruction.
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10․ In an intel 8085A, which is the first machine cycle of an instruction?
An op-code fetch cycle
A memory read cycle
A memory write cycle
An I/O read cycle
In execution of any instruction first cycle is op-code fetch the memory read or write or I/O
read or write cycle occur as per instruction given.
01․ Inintel 8085A microprocessor ALE signal is made high to
Enable the data bus to be used as low order address bus
To latch data D0-D7 from data bus
To disable data bus
To achieve all the functions listed above
When ALE signal is high all the buses are used as address bus and when it is low lower
byte of address bus is used as data bus.
02․ Output of the assembler in machine codes is referred to as
Object program
Source program
Macroinstruction
Symbolic addressing
Input to a assembler is the source program and assembler converts it into object program
01․ Both the ALU and control section of CPU employ which special purpose storage
location?
Buffers
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Accumulators
Registers
Accumulator is a special purpose 8-bit register which is used as a storage for almost all
arithmetic and logic operations.
02․ IN an intel 8085A microprocessor, why is READY signal used?
To indicate to user that the microprocessor is working and is ready for use.
To provide proper WAIT states when the microprocessor is communicating with a
slow peripheral device.
To slow down a fast peripheral device so as to communicate at the microprocessor’s
device.
None of the above.
Ready signal is used in microprocessor to communicate with slow peripheral device. It
provides proper synchronization between processor and slow devices.
03․ Assertion(A): Monostablemultivibrators (IC74121) are used in a microprocessor based
system for frequency measurement. Reason(R): Microprocessor counts the number of
interrupt signals/second or within a specified interval through ISR.
Both A & R are true and R is the correct explanation of A.
Both A & R are true but R is not the correct explanation of A.
A is true but R is false.
A is false but R is true.
IC74121 is used for frequency measurement in microprocessor and microprocessor
counts the number of interrupt signals/second or within a specified interval through ISR.
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04․ Consider the following I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag.
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Which one of the above flags is/are present in 8085 microprocessor?
(I) only
(I) & (II)
(II) & (III)
(I) ,(III) & (IV)
Trap flag is not present in 8085 microprocessor.
05․ Consider the following statements: In 8085 microprocessor, data-bus and address bus
are multiplexed in order to I)Increase the speed of microprocessor. II)Reduce the number
of pins. III)Connect more peripheral chips. Which of these statements is/are correct?
(I) only
(II) only
(II) & (III)
(I), (II) & (III)
Lower byte of address bus (A0 - A7) are multiplexed with data bus (AD0 - AD7) to reduce
the number of pins of microprocessor. This multiplexed address is controlled by ALE
signal.
06․ Assertion(A): Address bus is unidirectional. Reason(R): Data bus is bidirectional
Both A & R are true and R is the correct explanation of A
Both A & R are true but R is not the correct explanation of A
A is true but R is false
A is false but R is true
Address bus is unidirectional and data bus is bidirectional.
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07․ Assertion(A): The frequency of 8085 system is ½ of the crystal frequency. Reason(R):
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Microprocessor (8085) requires a two phase clock.
Both A & R are true and R is the correct explanation of A
Both A & R are true but R is not the correct explanation of A
A is true but R is false
A is false but R is true
Microprocessor clock frequency = (Crystal frequency/2)
08․ ALU (Arithmetic and Logic Unit ) of 8085 microprocessor consists of
Accumulator, temporary register, arithmetic and logic circuits
Accumulator, arithmetic, logic circuits and five flags
Accumulator, arithmetic and logic circuits
Accumulator, temporary register, arithmetic, logic circuits and five flags
ALU consists of Accumulator, temporary register, arithmetic, logic circuits and five flags.
09․ Which components are NOT found on chip in a microprocessor but may be found on
chip in a microcontroller?
SRAM & USART
EPROM & PORTS
EPROM, USART & PORTS
SRAM, EPROM & PORTS
EPROM, USART & PORTS are found on chip in microcontroller but not in
microprocessor chip.
10․ The clock speed of 8085 is
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1KHz.
3.2KHz.
3.2MHz.
8085 requires a signal +5V power supply and operates at 3.2 MHZ single phase clock
01․ The first machine cycle of an instruction is always
A memory read cycle
A fetch cycle
An I/O read cycle
A memory write cycle
The first machine cycle of an instruction is always fetch cycle.
02․ The output data lines of microprocessor and memories are usually tristated because
More than one device can transmit information over the data bus by enabling only
one device at a time
More than one device can transmit over the data bus at the same time
The data line can be multiplexed for both input and output
It increases the speed of data transfer over the data bus
Using tristate buffer, more than one device can transmit information over the data bus by
enabling only one device at a time.
03․ The correct sequence of steps in the instruction cycle of a basic computer is
Fetch, Execute, Decode and Read effective address.
Read effective address, Decode, Fetch and Execute.
Fetch, Decode, Read effective address and, Execute.
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At first instruction is fetched then decoded and then read effective address and executed.
04․ Following is a 16-bit register for 8085 microprocessor
Stack pointer
Accumulator
Register
Register C
In a 8085 microprocessor Accumulator, register B & C are of 8-bit whereas stack pointer is
a 16-bit register.
05․ The register which holds the information about the nature of results of arithmetic and
logic operations is called as
Accumulator
Condition code register
Flag register
Process status register
In a microprocessor flag registers indicate status of an arithmetic and logic operation.
06․ When referring to instruction words, a mnemonic is
a short abbreviation for the operand address.
a short abbreviation for the operation to be performed.
a short abbreviation for the data word stored at the operand address.
shorthand for machine language.
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All instructions consist of opcode and operand where opcode indicates operation to be
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performed and operand is on which operation to be done. Opcode is always expressed as
a short abbreviation which is nothing but mnemonic.
07․ While using a frequency counter for measuring frequency, two modes of
measurement are possible:
1. Period time
2. Frequency mode
There is a ‘cross-over frequency’ below which the period mode is preferred. Assuming
the crystal oscillator frequency to be 4MHz, the crossover frequency is given by
8 Mhz.
2 Mhz.
2 Khz.
1Khz.
As we know crossover frequency is the half of oscillator frequency. i.e.
08․ In 8085 microprocessor system with memory mapped I/O, which of the following is
true?
Devices have 8-bit address line
Devices are accessed using IN and OUT instructions
There can be maximum of 256 input devices and 256 output devices
Arithmetic and logic operations can be directly performed with the I/O data
With the memory mapped I/O arithmetic and logic operations can be directly performed
whereas with I/O mapped I/O it is not possible. Options A, B, C are valid for I/O mapped
I/O.
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09․ Consider the following statements: Arithmetic Logic Unit (ALU) 1.Performs
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arithmetic operations 2.Performs comparisons. 3.Communicates with I/O devices 4.Keeps
watch on the system Which of these statements are correct?
1, 2, 3 and 4
1, 2 and 3
1 and 2 only
3 and 4 only
ALU performs arithmetic and logical operations. Note: Comparison is a logical operation.
10․ Ready pin of microprocessor is used
to indicate that microprocessor is ready to receive inputs
to indicate that microprocessor is ready to receive outputs
to introduce wait state
to provide direct memory access
Ready signal is used to provide proper wait state when processor is communicating with
a slow peripheral device.
01․ A bus connected between the CPU and main memory that permits transfer of
information between main memory and the CPU is known as
DMA bus
Memory bus
Address bus
Control bus
We know data bus (Also known as Memory bus) allows transfer of information between
main memory and the CPU.
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02․ The operations executed by two or more control units are referred as
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Micro-operations
Macro-operations
Multi-operations
Bi control-operations
The operations executed by two or more control units are referred as Macro-operations.
03․ Consider the following registers: 1. Accumulator and flag register 2. B and C register
3. D and E register 4. H and L register Which of these 8-bit registers of 8085
microprocessor can be paired together to make a 16-bit register?
1, 3 and 4
2, 3 and 4
1, 2 and 3
1, 2 and 4
We can not combine accumulator and flag register to form 16-bit register whereas B & C,
D & E, H & L can be combined to form a 16-bit register.
04․ In a microcomputer , the address of memory locations are binary numbers that
identify each memory circuit where a byte is stored. If a microcomputer uses 20-bit
address, then numbers of different memory locations are
20
220
220-1
220 - 1
A 20-bit address can allow 220 different memory locations.
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05․ Number of Hex digits needed to represent the 20-bit address of a memory location are
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20
16
5
4
Since one hex digit can represent 4 binary bits, it will take 5 hex digits to represent the 20-
bit address of a memory location.
06․ HLDA signal in 8085 performs the following operation:
Indicates that another master is requesting the use of the address and data buses.
Indicates that the CPU has received the HOLD request and that it will relinquish the
bus in the next clock cycle.
Indicates that the CPU has not received the HOLD request.
Hold the data in the accumulator until the microprocessor is turned OFF.
07․ The field, which is never present in an assembly language statement, is
Opcode
Operand
Continue
Comment
There is nothing called “continue” in assembly language statement.
08․ Bus Interface Unit (BIU) in 8086 performs the following functions:
Instruction decoding.
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Arithmatic and Logic operations.
All the above.
BIU has the following functions: Instruction fetching, Instruction queuing, Operand
fetching and storage, Address relocation and Bus control.
09․ In 8086, _______ uses a mechanism known as an instruction stream queue to
implement a pipeline architecture.
Both ‘b’ and ‘c’
Execution Unit (EU)
Bus Interface Unit (BIU)
None of these
The BIU uses a mechanism known as an instruction stream queue to implement a
pipeline architecture. This queue permits prefetch of up to six bytes of instruction code.
Whenever the queue of the BIU is not full, it has room for at least two more bytes and at
the same time the EU is not requesting it to read or write operands from memory, the BIU
is free to look ahead in the program by prefetching the next sequential instruction.
10․ During the execution of the instruction, the ________tests the status and control flags
and updates them based on the results of executing the instruction.
None of these
Both ‘c’ and ‘d’
Bus Interface Unit (BIU)
Execution Unit (EU)
EU tests the status and control flags and updates them based on the results of executing
the instruction, during the execution of the instruction.
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01․ How many bytes in a zero memory page should be reserved for vectors used by RST
instructions?
16.
32.
64.
128.
First 64 bytes in a zero memory page should be reserved for vectors used by RST
instructions.
02․ CALL instruction is a ______ instruction.
4 bytes
2 bytes
1 bytes
3 bytes
CALL instruction is a 3 bytes instruction. The processor calls the subroutine, address of
which is specified in the second and third bytes of the instruction.
03․ The characteristics of RESET OUT signal is/are
indicates that µp is being reset.
all.
this signal can be used to reset other devices.
the signal is synchronized to the processor clock.
RESET OUT signal indicates that microprocessor is being reset. This signal can be used to
reset other devices. The signal is synchronized to the processor clock and lasts an integral
number of clock periods.
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04․ DMA signal/signals in 8085 is/are
All.
HOLD.
HLDA.
READY.
HOLD, HLDA and READY all are Direct Memory Access signals of 8085.
05․ Which general register or general register pair is incremented/decremented by 2
during PUSH and POP instructions?
H-L.
D-E.
Stack Pointer.
Program Counter.
PUSH: This instruction pushes the register pair onto stack. The contents of the register
pair designated in the operand are copied onto the stack in the following sequence. The
stack pointer register is decremented and the contents of the highorder register (B, D, H,
A) are copied into that location. The stack pointer register is decremented again and the
contents of the low-order register (C, E, L, flags) are copied to that location. Eg: - PUSH B
PUSH A POP: This instruction pop off stack to register pair. The contents of the memory
location pointed out by the stack pointer register are copied to the low-order register (C,
E, L, status flags) of the operand. The stack pointer is incremented by 1 and the contents
of that memory location are copied to the high-order register (B, D, H, A) of the operand.
The stack pointer register is again incremented by 1. Eg: - POP H POP A
06․ XCHG instruction exchanges the content of H-L with ______ register pair.
B-C
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D-E
Stack Pointer
Exchange H and L with D and E. The contents of register H are exchanged with the
contents of register D, and the contents of register L are exchanged with the contents of
register E.
07․ SPHL instruction copies the content of H-L register pair to the _________.
D-E
B-C
Stack Pointer
PSW
SPHL: - This instruction copies H and L register to the stack pointer. The instruction
loads the contents of the H and L registers into the stack pointer register, the contents of
the H register provide the high-order address and the contents of the L register provide
the low-order address. The contents of the H and L registers are not altered.
08․ The control flags in 8086 are:
the Trap flag(TF).
the interrupt flag(IF).
the direction flag(DF).
All of the above.
The three control flags of 8086 are:
1. The Trap flag(TF)
2. The interrupt flag(IF)
3. The direction flag(DF)
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The Trap Flag: Setting TF puts the processor into single step mode for debugging. If TF=1,
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the CPU automatically generates an internal interrupt after each instruction, allowing a
program to be inspected as it executes instruction by instruction. The Interrupt Flag: If
IF=1, the CPU will recognize external interrupt request (Interrupt Disabled). If IF=0, then
interrupt is disabled. The Direction Flag: This bit is especially for string instructions. If
DF=1, the string instruction will automatically decrement the pointer. If DF = 0, the string
instruction will automatically increment the pointer.
09․ RST0 - RST7 are the __________ in 8085.
hardware interrupts
logical interrupts
software interrupts
conditional interrupts
Software Interrupts are those which are inserted in between the program which means
these are mnemonics of microprocessor. There are 8 software interrupts in 8085
microprocessor. They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.
10․ ________is the only non-vectored interrupt in 8085 microprocessor.
TRAP
RST 5.5
INTR
RST 7
Non-Vectored Interrupts are those in which vector address is not predefined. The
interrupting device gives the address of sub-routine for these interrupts. INTR is the only
non-vectored interrupt in 8085 microprocessor.
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roprocessor Rooma, Kanpur – 208 008
8
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01․ ________used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by
setting various bits to form masks or generate output data via the Serial Output Data
(SOD) line.
RIM
SIM
EI
DI
Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts (RST 7.5, RST
6.5, RST 5.5) by setting various bits to form masks or generate output data via the Serial
Output Data (SOD) line. First the required value is loaded in accumulator then SIM will
take the bit pattern from it.
02․ _____________is used to read the status of the hardware interrupts (RST 7.5, RST 6.5,
RST 5.5) by loading into the A register a byte which defines the condition of the mask bits
for the interrupts.
SIM
RIM
DI
EI
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Read Interrupt Mask (RIM) – This instruction is used to read the status of the hardware
interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the A register a byte which defines
the condition of the mask bits for the interrupts. It also reads the condition of SID (Serial
Input Data) bit on the microprocessor.
03․ How many segments are there in 8086?
6.
4.
3.
2.
There are four segments in 8086: Code, Stack, Data and Extra.
04․ The first microprocessor to include virtual memory in the intel microprocessor family
is
80286
80386
80486
Pentium
80286 is a 16 bit microprocessor consisting of virtual memory.
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05․ Assertion(A): Segment override prefix (SOP) is used when a default offset register is
not used with its default base segment register but with a different base register.
Reason(R): The offset registers IP and SP can never be associated with any other segment
registers apart from their respective default segments.
Both A & R are true and R is the correct explanation of A.
Both A & R are true but R is not the correct explanation of A.
A is true but R is false.
A is false but R is true.
Both A & R are true but R is not the correct explanation of A.
06․ Assertion(A): Ready signal of microprocessor is used to detect whether a peripheral is
ready for the data transfer or not. Reason(R): In the microprocessor during data transfer
operations, the wait states are added by forcing the ready signal low.
Both A & R are true and R is the correct explanation of A.
Both A & R are true but R is not the correct explanation of A .
A is true but R is false.
A is false but R is true.
Both are correct and (R) is the correct explanation of (A)
07․ Program counter in a digital computer
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Counts the numbers of programs runRooma,
in the machine.
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Counts the number of times a subroutine is called.
Counts the number of times the loops are executed.
Points the memory address of the next instruction to be fetched.
Program counter is a 16-bit register which points the address of next instruction to be
fetched.
08․ During which T-state, contents of OP code from memory are loaded into IR
(Instruction Register)?
T1 OP code fetch
T2 OP code fetch
T3 OP code fetch
T4 OP code fetch
During T3 time period opcode from memory are loaded into instruction register (IR).
09․ Assuming LSB is at position 0 and MSB at position 7, which bit positions are not used
(Undefined) in flag register of an 8085 microprocessor?
1, 3, 5
2, 3, 5
1, 2, 5
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1, 3, 4 Rooma, Kanpur – 208 008
Among eight bit (0 to 7) 1st, 3rd and 5th bits are undefined in a flag register.
10․ At the beginning of a fetch cycle, the contents of the program counter are
incremented by one.
transferred to address bus.
transferred to memory address register .
transferred to memory data register.
Memory Address Register (MAR) is used to hold the address of memory before it is
placed on address bus.
9
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01․ The relation among IC (Instruction Cycle), FC (Fetch cycle) and EC (Execute Cycle) is
IC = FC - EC
IC = FC + EC
IC = FC + 2EC
EC = IC + FC
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Instruction cycle consists of fetch cycle and execute cycle.
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02․ Each instruction in an assembly language program has the following fields 1. Label
field 2. Mnemonic field 3. Operand field 4. Comment field What are the correct sequence
of these fields?
1, 2, 3 and 4
2, 1, 4 and 3
1, 3, 2 and 4
2, 4, 1 and 3
The correct sequence of any Instruction in an assembly language program is Label field,
Mnemonic field, Operand field and Comment field.
03․ Total number of instructions in 8085 microprocessor assembly language is
244
245
246
247
8085 microprocessor assembly language consists of 246 instructions.
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04․ An 8-bit microprocessor signifies that
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8-bit address bus
8-bit controller
8-interrupt lines
8-bit data bus
An 8-bit microprocessor signifies that it has 8-bit data bus.
05․ Which one of the following microprocessor is not an 8-bit microprocessor
8085
Z-80
68000
6502
8085, Z-80 and 6502 are 8-bit microprocessors whereas 68000 is a 16-bit microprocessor.
06․ Which one of the following microprocessor has 16-bit data bus?
8085
Z-80
68000
6502
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68000 is a 16-bit microprocessor. So it hasRooma,
16 data lines.
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07․ A microcomputer consists of
a microprocessor
memory
I/O device
All of the above
A microcomputer consists of a microprocessor, memory and I/O devices.
08․ The address bus of any microprocessor is always
Unidirectional
Bi-directional
Either unidirectional or bi-directional
None
Address bus of any microprocessor is always Unidirectional. Address bus points only
memory location so it is unidirectional.
09․ The data bus of any microprocessor is always
Unidirectional
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Bi-directional Rooma, Kanpur – 208 008
Either unidirectional or bi-directional
None
A data can be moved from microprocessor to memory and also from memory to
microprocessor. So Data bus of any microprocessor is always Bi-directional.
10․ The multiplexing of address bus and data buses is used in
all the microprocessors.
depends on the internal architecture.
never multiplexed.
none of these.
Multiplexing of address bus and data buses depends upon internal architecture of any
microprocessor.
9
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01․ The relation among IC (Instruction Cycle), FC (Fetch cycle) and EC (Execute Cycle) is
IC = FC - EC
IC = FC + EC
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IC = FC + 2EC Rooma, Kanpur – 208 008
EC = IC + FC
Instruction cycle consists of fetch cycle and execute cycle.
02․ Each instruction in an assembly language program has the following fields 1. Label
field 2. Mnemonic field 3. Operand field 4. Comment field What are the correct sequence
of these fields?
1, 2, 3 and 4
2, 1, 4 and 3
1, 3, 2 and 4
2, 4, 1 and 3
The correct sequence of any Instruction in an assembly language program is Label field,
Mnemonic field, Operand field and Comment field.
03․ Total number of instructions in 8085 microprocessor assembly language is
244
245
246
247
8085 microprocessor assembly language consists of 246 instructions.
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04․ An 8-bit microprocessor signifies that
8-bit address bus
8-bit controller
8-interrupt lines
8-bit data bus
An 8-bit microprocessor signifies that it has 8-bit data bus.
05․ Which one of the following microprocessor is not an 8-bit microprocessor
8085
Z-80
68000
6502
8085, Z-80 and 6502 are 8-bit microprocessors whereas 68000 is a 16-bit microprocessor.
06․ Which one of the following microprocessor has 16-bit data bus?
8085
Z-80
68000
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6502 Rooma, Kanpur – 208 008
68000 is a 16-bit microprocessor. So it has 16 data lines.
07․ A microcomputer consists of
a microprocessor
memory
I/O device
All of the above
A microcomputer consists of a microprocessor, memory and I/O devices.
08․ The address bus of any microprocessor is always
Unidirectional
Bi-directional
Either unidirectional or bi-directional
None
Address bus of any microprocessor is always Unidirectional. Address bus points only
memory location so it is unidirectional.
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09․ The data bus of any microprocessor is always
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Unidirectional
Bi-directional
Either unidirectional or bi-directional
None
A data can be moved from microprocessor to memory and also from memory to
microprocessor. So Data bus of any microprocessor is always Bi-directional.
10․ The multiplexing of address bus and data buses is used in
all the microprocessors.
depends on the internal architecture.
never multiplexed.
none of these.
Multiplexing of address bus and data buses depends upon internal architecture of any
microprocessor.
01․ Which one of the following statement is false?
A microprocessor has bi-directional address bus
A microprocessor has unidirectional address bus
A microprocessor has bi-directional data bus
A microprocessor has an ALU
A microprocessor has unidirectional address bus.
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02․ Identify the non-maskable interrupt from the following
RST 7.5
RST 6.5
RST 5.5
RST 4.5
One and only non-maskable interrupt in 8085 microprocessor is TRAP which is also
known as RST 4.5
03․ In microprocessor based system DMA refers to
direct memory access for microprocessor
direct memory access for the user
direct memory access for the I/O device
none of the above
When more data is to be transferred between memory and I/O device DMA operation is
used with the help of DMA controller.
04․ The interrupt facility is provided in microprocessor to
change the sequence of the instructions being executed
stop the microprocessor when desired
stop the microprocessor when it starts malfunctioning
keep a control on the working of the microprocessor
Interrupt facility is provided in the microprocessor to change the sequence of the
instructions being executed.
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05․ A microprocessor differentiates between op code, data/address at any time by
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the sequence in which memory contents are fetched by it
its internal registers
the stack pointer
the program counter
A microprocessor differentiates between op code, data/address at any time by the
sequence in which memory contents are fetched by it.
06․ A microprocessor without the interrupt facility
is best suited for process control system
is not useful for process control system
cannot be used for DMA operation
cannot be interfaced with any I/O devices
Interrupt facility is mandatory for any process control system to have proper control on
the system.
07․ In microprocessor based system I/O ports are used to interface
the I/O devices and memory chips
the I/P device only
the O/P devices only
all the I/O devices
In microprocessor based system I/O ports are used to interface all the I/O devices.
08․ The stack pointer
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resides in RAM Rooma, Kanpur – 208 008
resides in ROM
resides in microprocessor
may be in RAM or ROM
Stack pointer is nothing but the register which holds the address of the top of the stack,
resides within the microprocessor.
09․ In a microprocessor based system the stack is always in
microprocessor
RAM
ROM
EPROM
In a microprocessor based system the stack is always in Random Access Memory (RAM).
10․ The instruction set of a microprocessor
is specified by the manufacturers
is specified by the user
cannot be changed by the user
is stored inside the microprocessor
The instruction set of a microprocessor is specified by the manufacturers.
01․ The 8085 microprocessor uses a crystal of frequency 6.25 Mhz. The T-state value is
320ns
640ns
960ns
1280ns
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We know Now,
02․ When an 8085 microprocessor is reset, the address bus contains
0000H
002CH
0043H
003CH
When an 8085 microprocessor is reset, the address bus contains 0000H.
03․ In an 8085 microprocessor based system, the contents of SP are 1000H, PUSH B
instruction will transfer the contents of registers B & C respectively for memory locations
0FFF H and 0FFE H
0FFE H and 0FFF H
1000 H and 0FFF H
1000 H and 1001 H
Stack pointer indicates the top of the stack memory. If data are to be moved in stack
memory then those will start to be stored from above the address contained by stack
pointer. In this problem stack pointer contains 1000 H. So when PUSH B instruction is
given data will start to be stored from 0FFF H, 0FFE H, 0FFD H onwards.
04․ In an 8085 microprocessor based system, the contents of SP are 2000H. POP H
instruction will transfer the contents of memory location
2001H and 2002H to H and L registers respectively
2001H and 2000H to H and L registers respectively
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2000H and 1FFFH to H and L registers respectively
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2000H and 1999H to H and L registers respectively
The content of 2001 H will be stored into H and content of 2000 H will be stored in L.
05․ PUSH B instruction in 8085 microprocessor causes
the contents of register B only to be copied in the stack
the contents of register B & C to be copied in the stack
the contents of registers B & C to be transferred in the stack and and the registers get
cleared
registers B & C to be cleared
PUSH B instruction allows to copy the contents of register pairs B & C to the stack
06․ SUB A instruction in 8085
reset carry and sign flags
reset zero and parity flags
sets zero and sign flags
sets zero and carry flags
SUB R instruction allows to subtract the content of register R from Accumulator (A).
Likewise, SUB A instruction will allow to subtract the content of Accumulator form
Accumulator. Hence, carry and sign flags will be reset.
07․ In 8085 microprocessor , let the accumulator contains the value 0AH and register C
contains the value 05H. After CMP C instruction is executed, the
zero and carry flags will be set
zero and carry flags will be reset
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zero flag will be set and carry flag will be reset
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zero flag will be reset and carry flag will be set
CMP C instruction allows to subtract the content of Register C from Accumulator. So, in
the given problem 05 H will be subtracted from 0AH and results 05 H whose binary form
is (0000 0101)2. As content of Accumulator is greater than register C then both the carry
and zero flag are reset.
08․ Which of the data transfer is not possible in microprocessor
memory to accumulator
accumulator to memory
memory to memory
I/O device to accumulator
In 8085 microprocessor memory to memory data transfer is not possible.
09․ In 8085 microprocessor, in response to RST 7.5 interrupts the execution is transferred
to memory location
0000H
002CH
0034H
003CH
The vector address of RST 7.5 is hexadecimal equivalent of . So, in response to RST
7.5 interrupts the execution is transferred to memory location 003CH.
10․ In 8085 microprocessor which one of the following statement is wrong
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there is a pin available for serial input
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there is a pin available for serial output
serial I/O is possible through SIM and RIM instruction
serial I/O is not possible
8085 microprocessor has two signals to implement serial data transmission SID(Serial
Input Data) and SOD(Serial Output Data).Serial I/O is also possible through SIM (Serial
output data) and RIM (Serial input data) instruction in 8085 microprocessor.
01․ EPROMs are preferred for storing programs while developing new microprocessor
based system. Because of their
non-volatile characteristic
erasable and programmable characteristic
random access characteristic
all the above characteristic
EPROM(Erasable Programmable Read Only Memory) has non-volatile, erasable and
programmable characteristics.
02․ When any data transfer instruction, to transfer the data from memory to
microprocessor, is executed the condition flags are
not affected
always set
always reset
affected indicating specific conditions
Data transfer operation does not affect any of the flags in 8085 microprocessor.
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03․ Let the content of accumulator and register B be 0000 0100 and 0100 0000 respectively
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before execution of instruction SUB B. The content of accumulator after the execution of
this instruction will be
00000100
01000000
11000100
010001000
SUB B allows subtraction of content B from A and the result is stored in the accumulator.
In the given problem we have to subtract 0100 0000 from 0000 0100. Hence the
content of the accumulator after execution the given instruction will be 11000100.
04․ Let the content of register C be 00000000 before the instruction DCR C is executed.
The content of register C after the after the execution of this instruction will be
00000000
11111111
00000001
None
DCR C instruction allows C to decrement the content of register C by 1. Binary of 1 is
00000001. We have to subtract 00000001 from 00000000.
05․ In 8085 microprocessor based system maximum possible number of input/output
devices can be connected using I/O mapped I/O technique is
64
256
512
65536
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Using I/O mapped I/O technique 256 input device and 256 output device i.e. total 512
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input/output devices can be connected to the microprocessor.
06․ Cycle stealing mode of DMA operation involves
DMA controller taking over the address, data and control buses while a block of data
is transferred between memory and I/O device
While the microprocessor is executing a program an interface circuit takes over
control of address, data, control buses when not in use by microprocessor
Data transfer takes place between the I/O device and memory during every alternate
clock cycle
The DMA control waiting for the microprocessor to finish execution of the program
and then takes over the buses
Cycle stealing mode of DMA operation takes place while the microprocessor is executing
a program and an interface circuit takes over control of address, data and control buses
when not in use by microprocessor.
07․ Which of the following is not true during the execution of an interrupt service routine,
which does not contain any EI instructions
the microprocessor can be interrupted by a non-mask able interrupt
the microprocessor cannot be interrupted by any interrupt
the microprocessor cannot be interrupted by any mask able interrupt
all interrupts except non-maskable interrupt are disabled
EI (Enable Interrupt) instruction should be provided at the beginning of any program so
that it can respond to any interrupts. If EI is not provided in the program then
microprocessor cannot be interrupted by any interrupt.
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08․ The reason for the presence of ALE pin in 8085, but not in 6800 is that
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8085 uses I/O mapped I/O, whereas 6800 uses memory mapped I/O
8085 has 5 interrupts lines, whereas 6800 has only two
8085 has multiplexed bus, whereas 6800 does not have
None
8085 has multiplexed bus which acts as address bus as well as data bus(AD0-AD7). So
ALE is required to indicate status of the buses.
09․ Which of the following interrupt is both level and edge sensitive?
RST 5.5
INTR
RST 7.5
TRAP
TRAP is one and only interrupt having both level and edge sensitive triggering.
10․ The addressing mode in instruction PUSH B is
direct
register
register indirect
immediate
The addressing mode in instruction PUSH B is register indirect. The contents of the
source registers are not altred after the PUSH instruction
01․ Which of the following interrupt is only edge sensitive?
RST 7.5
TRAP
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RST6.5 Rooma, Kanpur – 208 008
RST 5.5
Among all interrupts RST 7.5 is only positive edge sensitive.RST 6.5 and RST 5.5 are level
sensitive triggered.TRAP is both level and edge sensitive triggered.
02․ What is the vector address of INTR?
0024H
003CH
0034H
No address is available
INTR is the one and only non-vectored interrupt in 8085 microprocessor so it has no
addressing available in 8085 microprocessor. For INTR, external hardware is used to
transfer program to specific CALL location.
03․ On receiving an interrupt from an I/O device, the CPU
halts for a predetermined times
hands over the control of address bus and data bus to the interrupting device
branches off to the interrupt service routine immediately
branches off to the interrupt serviceroutine after completion of the current instruction
After receiving an interrupt signal at first microprocessor will complete the current
instruction and then it will branch off to the interrupt service routine.
04․ The ALE line of 8085 microprocessor is used to
latch the output of an I/O instruction into an external latch
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deactivate the chip-select signal fromRooma,
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latch the 8-bit of address lines AD0-AD7 into an external latch
find the interrupt enable status of the TRAP interrupt
The ALE (Address Latch Enable) line of 8085 microprocessor is used to latch the 8-bit of
address lines AD0-AD7 into an external latch.
05․ The first operation performed in INTEL 8085 microprocessor after RESET is
instruction fetch from 0000H
memory read from the location 0000H
instruction fetch from location 8000H
stack initialization
After RESET instruction the processor execution will initialize from 0000H.
06․ After the execution of CMP A instruction
ZF is set and CY is reset
ZF is set and CY is unchanged
ZF is reset and CY is set
ZF is reset and CY is unchanged
CMP R instruction compares the content of register R to accumulator and accordingly
Zero and Carry flag will be affected. By CMP A instruction content of the accumulator is
compared with the accumulator itself.The condition is that if A is same as comparing
register zero flag will be set and carry flag will reset.
07․ The 8085 microprocessor will enter into INA cycle after recognition of
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any interrupt Rooma, Kanpur – 208 008
TRAP only
INTR only
RST 7.5,RST 6.5 & RST 5.5 only
The 8085 microprocessor will enter into INA cycle after recognition of INTR only.
08․ Which of the following lists the interrupt in decreasing order of priority?
TRAP, RST 5.5, RST 6.5, RST 7.5, INTR
INTR, TRAP, RST 7.5, RST 6.5, RST 5.5
TRAP, RST 7.5, RST 6.5, RST 5.5, INTR
RST 7.5, RST 6.5, RST 5.5, TRAP, INTR
Priority wise decreasing order of interrupts is TRAP, RST 7.5, RST 6.5, RST 5.5, INTR. The
first four interrupt are vectored interrupt. TRAP is highest priority interrupt but has a
lower priority than HOLD signal.
09․ The interrupt vector address for TRAP is
0000H
0024H
0018H
002CH
For vectored interrupt the microprocessor assigns a specified memory location. The
interrupt vector address for TRAP is 0024H.
10․ In order to reset the carry without affecting the accumulator content one has to use,
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SUB A Rooma, Kanpur – 208 008
XRA A
ORA A
CMC
After OR operation CY (carry flag) & AC (auxiliary carry flag) is reset by default. So this
is the most suitable instruction to reset carry
01․ Maximum number of I/O that can be addressed by the INTEL 8085 is
65536
285
512
256
I/O has 8 bit port address so maximum number of I/O that can be addressed by the
INTEL 8085 is 28=256
02․ The microprocessor may be made to exit from HALT state by asserting
RESTART
any of the five interrupt lines
READY line
A or B or HOLD line
The microprocessor may be made to exit from HALT state by asserting RESTART or any
of the five interrupt lines or HOLD line.
03․ In order to complement the lower nibble of accumulator one can use
ANI 0FH
XRI 0FH
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ORI 0FH Rooma, Kanpur – 208 008
CMA
By XRI operation the 8 bit data are exclusive ORed with the contents of the accumulator
and results are placed in the accumulator.Let the content of accumulator is 0101 1010.
Now EXORing it with 0FH = (0000 1111)2. We will get the answer 0101 0101 which will be
stored in the accumulator. Hence we can see XRI 0FH instruction can be used to
complement the content of lower nibble of accumulator.
04․ The 8085 microprocessor enters into bus idle machine cycle whenever
INTR interrupt is recognized
RST 7.5 is recognized
DAD RP instruction is executed
none of the above
When RST 7.5 is recognized the 8085 microprocessor enters into bus idle machine cycle.
05․ During OPCODE fetch the state of S0 and S1 is
00
01
10
11
S0 and S1 are status signal for different operation like HALT,WRITE,READ,and
FETCH.During OPCODE fetch S0 = 1 and S1 = 1.
06․ After RESET 8255 will be in
mode 0; all ports are input
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mode 0; all ports are output Rooma, Kanpur – 208 008
mode 2
unchanged condition
In INTEL 8255, RESET is a active high signal which clears the control register and sets all
the ports in the input mode or mode 0.
07․ The microprocessor issues ALE during first T-state of
fetch cycle only
memory READ cycle only
memory WRITE cycle only
every machine cycle
ALE is address latch enable signal.The microprocessor issues ALE or it goes high during
first clock cycle of every machine cycle.
08․ The data lines of 8085 microprocessor are multiplexed with
higher order address lines
lower order address lines
status lines
none of the above
AD0 to AD7 can be used for both transmit data or address at different moments.Thus
these bus operate in time sharing mode which is called multiplexing.The data lines of
8085 microprocessor are multiplexed with lower order address lines to increase the
effective width of address bus.
09․ RST 3 instruction will cause the processor to branch to the location
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0000H Rooma, Kanpur – 208 008
0018H
0024H
0028H
For every vectored interrupt irrespective of software and hardware 8-bytes are
allocated.Generally the allocated memory address will be 8*interrupt and its equivalent
hexadecimal value. Example for RST 3 the memory address location would be
8*3=(24)10=(18)H.So the correct ans will be (0018)H.
10․ Which of the following instruction will never affect the zero flag?
DCR R
ORA R
DCX Rp
XRA R
By DCR B, the contents of the register is decreased by 1.The zero flag is affected but the
carry flag is not affected. Due to ORA R the contents of the accumulator is ORed with the
contents of register R.Zero and carry flag both are affected. Due to DCX Rp instruction
register pair is decremented by1, no flags will be affected i.e. zero flag also will be
unaffected. Due to XRA R the content of accumulator is Ex-ORed with register R, both
zero and carry flag is affected.
01․ The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port
address” instruction are
same as the content of A7-A0
irrelevant
all bits reset (i.e. 00H)
all bits set (i.e. FFH)
“IN 8-bit port address” is an 8 bit port address. The maximum port range is up to (FF)H.
For executing this instruction the high order (A15-A8) port address is duplicated to low
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order (A7 -A0) port address. So high order address bus has same content as low order
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address bus.
01․ In a vector interrupt
the branch address is assigned to a fixed location in memory.
the interrupting source supplies the branch information to the processor through an
interrupt vector.
the branch address is obtained from a register in the processor.
none.
TRAP, RST 7.5, RST 6.5 and RST 6.5 are the vector interrupts in 8085. In a vector interrupt
the branch address is assigned to a specific location in memory page without any external
hardware.
02․ A sequence of two registers that multiplies the content of DE register pair by two and
stores the result in HL register pair (in 8085 assembly language) is
XCHG & DAD B
XTHL & DAD H
PCHL & DAD D
XCHG & DAD H
XCHG → exchange the content of DE register pair with HL pair. DAD H → add the
content of HL pair with HL pair. So, after following these two sequences of instructions
the content of DE register pair will be multiplied by two and saved to the HL register
pair.
03․ Identify the programmable interval timer from the following
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8252 Rooma, Kanpur – 208 008
8253
8279
8275
8253 and 8254 are the programmable interval timer. It can generate accurate time delays
by using software instruction.It can be used as accurate time delays,square wave
generator etc.
04․ Identify the communication interfacing device from the following
8155
8255
8251
8257
Programmable communication interface is used for the serial data transmission.Intel 8251
is a programmable communication interface.It is Universal Synchronous /Asynchronous
Receiver/ Transmitter (USART).
05․ Identify the programmable DMA controller from the following
8257
8253
8251
8279
In DMA data transfer data is directly transferred between I/O to the RAM or from the
RAM to the I/O. 8257 and the 8237 are used as a programmable DMA controller. In this
question the correct answer would be 8257.
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06․ Pick up the programmable interrupt controller from the following
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8279
8259
8257
8275
8259 is a programmable interrupt controller which is designed to work with
microprocessor like 8085,8086 and 8088.It can manage eight interrupts according to the
instruction written into its control registers.
07․ Identify the non-programmable interfacing device from the following
8295.
8257.
8212.
8255.
8212 has a non-programmable 8-Bit I/O Port.
08․ The maximum number of seven segment displays that can be connected to 8279 is
12
16
18
8
The maximum number of seven segment displays that can be connected to 8279 is 18.
09․ Using one 8259 IC is equivalent to providing …………. INTR pins on 8085
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16 Rooma, Kanpur – 208 008
12
8
18
8259 is a programmable interrupt controller designed to work with microprocessor like
8085,8086 and 8088. It can manage eight interrupts according to the instructions written
to its control registers.This is equivalent to providing eight interrupt pins in place of one
INTR pin in 8085 microprocessor.
10․ Total number of modes the 8253 can work
4
6
8
12
The 8253 is a 24 pin IC which can be programmed in any of the following 6 operating
modes e.g. Interrupt on terminal count,programmable one shot,Rate generator, Square
wave generator, software triggered strobe and hardware triggered strobe
03․ Which of the following instruction is not possible in 8085?
POP PSW
POP B
POP D
POP 30 H
POP 30 H instruction is not possible in 8085 because POP instruction is used with register
pair or PSW. By using this instruction the content of the memory location pointed out by
the stack pointer register are copied to the low order register. 30 H is not a valid register
pair or memory address so this instruction is invalid
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04․ How many T-states are required for execution of OUT 80H instruction?
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10
13
16
7
OUT operation means Output data from Accumulator to a port with 8 bit address.The
contents of the accumulator are copied into the output port.It is a two byte operation with
3 machine cycles and 10 T states.10T states 4 for Opcode fetch, 3 for Memory read and 3
for I/O write operation.
05․ How many machine cycles are required for execution of IN 30H instruction
3
4
5
6
IN instruction means Input data to Accumulator from a port with 8-bit address.IN 30H is
a 2 byte instruction which requires 3 machine cycles i.e. Opcode fetch, read, read(operand
read from the 8 bit port address).
06․ Length of the instruction POP D is
1 byte
2 byte
3 byte
4 byte
By POP instruction the contents of the memory location pointed out by the stack pointer
register are copied to the low order register of the operand.POP D is an 1 byte instruction.
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Rooma, Kanpur – 208 008
07․ While INX B instruction execute,
only carry flag will be affected
all flags will be affected
only carry and zero flags will be affected
no flags will be affected
The flags (flip flop) are affected by the arithmetical and logical operations in the ALU.
Flags generally reflects the data conditions in the accumulator with some exception. INX
B is a instruction which increment the content of the register pair BC by 1 and it does not
affect any of the flags.
08․ While STC instruction executes,
only carry flag will be affected.
all flags will be affected.
only carry and zero flags will be affected.
no flags will be affected.
While STC instruction executes, microprocessor sets the carry flag to 1. So this instruction
affects the carry flag only.
09․ While CMP B instruction executes,
only carry flag will be affected.
all flags will be affected.
only carry and zero flags will be affected.
no flags will be affected.
While CMP B instruction executes, microprocessor compares the contents of register B
with the contents of the accumulator. The comparison is shown by setting all the flags.
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The flags S, P, AC are modified and flag Z and CY reflects the result of the operation. So,
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all flags will be affected.
10․ Which instruction is required to rotate the content of accumulator one bit right along
with carry?
RLC
RAL
RRC
RAR
RAR instruction means rotate accumulator right through carry. By this instruction each
bit of the accumulator is rotated right by one position through the carry flag. The carry
flag is set by the least significant digit and content of the carry flag is placed in the most
significant position. Example : accumulator contents before instruction is 10100111 and
the flag is set by 0. After the instruction executes the accumulator content is 01010011 and
the flag is set by 1.
01․ How can we make any bit of a register “1”?
AND that bit with “0” and remaining bits with “1”.
AND that bit with “1” and remaining bits with “0”.
OR that bit with “0” and remaining bits with “1”.
OR that bit with “1” and remaining bits with “0”.
If we want to make any bit “1”, then we have to OR that bit with “1” so that the bit
becomes “1”. We also have to OR the remaining bits of the register with “0” so that they
remain unaltered.
02․ When RET instruction is executed by any subroutine then
the top of the stack will be popped out and assigned to the PC.
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without any operation, the calling program would
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– 208 008
immediately following the call instruction.
the PC will be incremented after the execution of the instruction.
without any operation, the calling program would resume from instruction
immediately following the call instruction and also the PC will be incremented after the
execution of the instruction.
When RET instruction is executed by any subroutine then two bytes from the top of the
stack will be popped out and assigned to the Program counter and the program execution
begins at the new address.
01․ In a vector interrupt
the branch address is assigned to a fixed location in memory.
the interrupting source supplies the branch information to the processor through an
interrupt vector.
the branch address is obtained from a register in the processor.
none.
TRAP, RST 7.5, RST 6.5 and RST 6.5 are the vector interrupts in 8085. In a vector interrupt
the branch address is assigned to a specific location in memory page without any external
hardware.
02․ A sequence of two registers that multiplies the content of DE register pair by two and
stores the result in HL register pair (in 8085 assembly language) is
XCHG & DAD B
XTHL & DAD H
PCHL & DAD D
XCHG & DAD H
XCHG → exchange the content of DE register pair with HL pair. DAD H → add the
content of HL pair with HL pair. So, after following these two sequences of instructions
the content of DE register pair will be multiplied by two and saved to the HL register
pair.
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Rooma, Kanpur – 208 008
03․ Identify the programmable interval timer from the following
8252
8253
8279
8275
8253 and 8254 are the programmable interval timer. It can generate accurate time delays
by using software instruction.It can be used as accurate time delays,square wave
generator etc.
04․ Identify the communication interfacing device from the following
8155
8255
8251
8257
Programmable communication interface is used for the serial data transmission.Intel 8251
is a programmable communication interface.It is Universal Synchronous /Asynchronous
Receiver/ Transmitter (USART).
05․ Identify the programmable DMA controller from the following
8257
8253
8251
8279
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In DMA data transfer data is directly transferred between I/O to the RAM or from the
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RAM to the I/O. 8257 and the 8237 are used as a programmable DMA controller. In this
question the correct answer would be 8257.
06․ Pick up the programmable interrupt controller from the following
8279
8259
8257
8275
8259 is a programmable interrupt controller which is designed to work with
microprocessor like 8085,8086 and 8088.It can manage eight interrupts according to the
instruction written into its control registers.
07․ Identify the non-programmable interfacing device from the following
8295.
8257.
8212.
8255.
8212 has a non-programmable 8-Bit I/O Port.
08․ The maximum number of seven segment displays that can be connected to 8279 is
12
16
18
8
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
The maximum number of seven segment displays that can be connected to 8279 is 18.
09․ Using one 8259 IC is equivalent to providing …………. INTR pins on 8085
16
12
8
18
8259 is a programmable interrupt controller designed to work with microprocessor like
8085,8086 and 8088. It can manage eight interrupts according to the instructions written
to its control registers.This is equivalent to providing eight interrupt pins in place of one
INTR pin in 8085 microprocessor.
10․ Total number of modes the 8253 can work
4
6
8
12
The 8253 is a 24 pin IC which can be programmed in any of the following 6 operating
modes e.g. Interrupt on terminal count,programmable one shot,Rate generator, Square
wave generator, software triggered strobe and hardware triggered strobe
1. In 8085 microprocessor, how many interrupts are maskable.
a. Two
b. Three
c. Four
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d. Five Rooma, Kanpur – 208 008
Answer
Answer. c
2. Which stack is used in 8085 microprocessors?
a. FIFO
b. FILO
c. LIFO
d. LILO
Answer
Answer. c
3. In the instruction of the 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer
Answer. b
4. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer
Answer. d
5. Which one of the following register of 8085 microprocessor is not a part of the
programming model?
a. Instruction register
b. Memory address register
c. Status register
d. Temporary data register
Answer
Answer. c
6. The program counter in 8085 microprocessor is a 16-bit register, because
a. It counts 16 bits at a time
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b. There are 16 address times Rooma, Kanpur – 208 008
c. It facilitates the users storing 16-bit data temporarily
d. It has to fetch two 8-bit data at a time.
Answer
Answer. b
7. A direct memory access (DMA) transfer replies
a. Direct transfer of data between memory and accumulator
b. Direct transfer of data between memory and I/O devices without the use of
microprocessor
c. Transfer of data exclusively within microprocessor registers
d. A fast transfer of data between microprocessor and I/O devices
Answer
Answer. b
8. Handshaking mode of data transfer is
a. Synchronous data transfer
b. asynchronous data transfer
c. interrupt driven data transfer
d. level Mode of DMA data transfer
Answer
Answer. a
9. In a Microprocessor, the address of the new next instruction to be executed is
stored in
a. Stack pointer
b. address latch
c. Program counter
d. General purpose register
Answer
Answer. c
10. In how many different modes a universal shift register operates?
a. 2
b. 3
c. 4
d. 5
Answer
Answer. c
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11. The insruction RET executes with the following series of machine cycle
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a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer
Answer. c
12. Which one of the following statements is correct regarding the instruction CMP
A?
a. compare accumulator with register A
b. compare accumulator with memory
c. compare accumulator with register H
d. This instruction does not exist
Answer
Answer. a
13. The instruction JNC 16-bit refers to jump to 16-bit address if ?
a. sign flag is set
b. carry flag is reset
c. zero flag is set
d. parity flag is reset
Answer
Answer. b
14. Among the given instructions, the one which affects the maximum number of
flags is ?
a. RAL
b. POP PSW
c. XRA A
d. DCR A
Answer
Answer. c
15. XCHG instruction of 8085 exchanges the content of ?
a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
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Answer
Rooma, Kanpur – 208 008
Answer. c
16. Direction flag is used with
a. string instructions
b. stack instructions
c. arithmetic instructions
d. branch instructions
Answer
Answer. a
17. The number of output pins of a 8085 microprocessor are
a. 40
b. 27
c. 21
d. 19
Answer
Answer. b
18. Following is a 16-bit register for 8085 microprocessor
a. Stack pointer
b. Accumulator
c. Register B
d. Register C
Answer
Answer. a
19. The register which holds the information about the nature of results of
arithmetic of logic operations is called as
a. Accumulator
b. Condition code register
c. Flag register
d. Process status registers
Answer
Answer. c
20. When referring to instruction words, a mnemonic is
a. a short abbreviation for the operand address.
b. a short abbreviation for the operation to be performed.
c. a short abbreviation for the data word stored at the operand address.
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d. Shorthand for machine language.Rooma, Kanpur – 208 008
Answer
Answer. b
21. While using a frequency counter for measuring frequency, two modes of
measurement are possible.
1. Period mode
2. Frequency mode
There is a ‘cross-over frequency’ below which the period mode is preferred.
Assuming the crystal oscillator frequency to be 4 MHz the crossover frequency is
given by
a. 8 MHz
b. 2 MHz
c. 2 kHz
d. 1 kHz
Answer
Answer. b
22. In a 8085 microprocessor system with memory-mapped I/O, which of the
following is true?
a. Devices have 8-bit‘address line
b. Devices are accessed using IN and OUT instructions
c. There can be maximum of 256 input devices and 256 output devices
d. Arithmetic and logic operations can be directly performed with the I/O data
Answer
Answer. d
23. Consider the following statements:
Arithmetic Logic Unit (ALU)
1 . Performs arithmetic operations.
2. Performs comparisons.
3. Communicates with I/O devices.
4. Keeps watch on the system.
Which of these statements are correct?
a. 1, 2, 3 and 4
b. 1,2 and 3 only
c. 1 and 2 only
d. 3 and 4 only
Answer
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Answer. c Rooma, Kanpur – 208 008
24. Ready pin 0f microprocessor is used
a. to indicate that the microprocessor is ready to receive inputs
b. to indicate that the microprocessor is ready to receive outputs
c. to introduce wait state
d. to provide direct memory access
Answer
Answer. c
25. A bus connected between the CPU and the main memory that permits transfer
of information between main memory and the CPU is known as
a. DMA bus
b. Memory bus
c. Address bus
d. Control bus
Answer
Answer. b
26. The operations executed by two or more control units are referred as
a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer
Answer. c
27. Consider the following registers:
1. Accumulator and flag register
2. B and C registers
3. D and E registers
4. H and L registers
Which of these 8-bit registers of 8085 μP can be paired together to make a 16-bit
register?
a. (a) 1, 3 and 4
b. 2, 3 and 4
c. 1, 2 and 3
d. 1, 2 and 4
Answer
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Answer. b Rooma, Kanpur – 208 008
28. The first microprocessor to include virtual memory in the Intel microprocessor
family is
a. 80286
b. 80386
c. 80486
d. Pentium
Answer
Answer. a
29. Program counter in a digital computer
a. counts the numbers of programs run in the machine ,
b. counts the number of times a subroutine is called
c. counts the number of times the loops are executed
d. points the memory address of the current or the next instruction to be
executed
Answer
Answer. d
30. Assuming LSB is at position 0 and MSB at position 7, which bit positions are not
used (undefined) in Flag Register of an 8085 microprocessor?
a. 1, 3, 5
b. 2, 3, 5
c. 1, 2, 5
d. 1, 3, 4
Answer
Answer. a
31. At the beginning of a fetch cycle, the contents of the program counter are
a. incremented by one
b. transferred to address bus
c. transferred to memory address register
d. transferred to memory data register
Answer
Answer. c
32. Each instruction in an assembly language program has the following fields
1. Label field
2. Mnemonic field
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3. Operand field Rooma, Kanpur – 208 008
4. Comment field
What is the correct sequence of these fields?
a. 1, 2, 3 and 4
b. 2, 1, 4 and 3
c. 1,3, 2 and 4
d. 2, 4, 1 and 3
Answer
Answer. a
33. The relation among IC (lnstruction Cycle), FC (Fetch Cycle) and EC (Execute
Cycle) is
a. IC = FC − EC
b. IC = FC+ EC
c. IC= FC + 2EC
d. EC = IC+FC
Answer
Answer. b
34. When a peripheral is connected to the microprocessor in input/output mode,
the data transfer takes place between
a. any register and I/O device
b. memory and I/O device
c. accumulator and I/O device
d. HL registerand I/O device
Answer
Answer. c
35. While execution of I/O instruction takes place, the 8-bit address of the port is
placed on
a. lower address bus
b. higher address bus
c. data bus
d. lower as well as higher-order address bus
Answer
Answer. d
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36. The length of a bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an
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indeterminate number of wait state clock cycles denoted by TW. The wait states are
always inserted between
a. T1 and T2
b. T2 and T3
c. T3 and T4
d. T4 and T1
Answer
Answer. c
37. Which one of the following circuits transmits two messages simultaneously in
one direction?
a. Duplex
b. Diplex
c. Simplex
d. Quadruplex
Answer
Answer. b
38. A microprocessor is ALU
a. and control unit on a single chip
b. and memory on a single chip
c. register unit and I/O device on a single chip
d. register unit and control unit on a single chip
Answer
Answer. d
39. In Intel 8085 microprocessor, ALE signal is made high to
a. Enable the data bus to be used as low order address bus
b. To latch data D0— D7 from the data bus
c. To disable data bus
d. To achieve all the functions listed above
Answer
Answer. a
40. Output of the assembler in machine codes is referred to as
a. Object program
b. Source program
c. Macro instruction
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d. Symbolic addressing Rooma, Kanpur – 208 008
Answer
Answer. a
41. Which one of the following statements for Intel 8085 is correct?
a. Program counter (PC) specifies the address of the instruction last executed
b. PC specifies the address of the instruction being executed
c. PC specifies the address of the instruction be executed
d. PC specifies the number of instruction executed so far
Answer
Answer. c
42. The instruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer
Answer. c
43. Which one of the following statements is correct regarding the instruction CMP
A?
a. Compare accumulator with register A
b. Compare accumulator with memory
c. Compare accumulator with register H
d. This instruction does not exist
Answer
Answer. a
44. The instruction JNC 16-bit refers to jump to 16-bit address if
a. Sign flag is set
b. Carry flag is reset
c. Zero flag is set
d. Parity flag is reset
Answer
Answer. b
45. Consider the following interrupts for 8085 microprocessor:
1. INTR
2. RST 5.5
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3. RST 6.5
4. RST 7.5 Rooma, Kanpur – 208 008
5. TRAP
If the interrupt is to be vectored to any memory location then which of the above
interrupt is/are correct?
a. 1 and 2 only
b. 1, 2, 3 and 4
c. 5 only
d. 1 only
Answer
Answer. d
46. Consider the following statements:
1. Auxiliary carry flag is used only by the DAA and DAS instruction.
2. Zero flag is set to 1 if the two operands compared are equal.
3. All conditional jumps are long type jumps.
Which of the above statements are correct?
a. 1, 2 and 3 only
b. 1 and 2 only
c. 1 and 3 only
d. 2 and 3 only
Answer
Answer. b
47. Among the given instructions, the one which affects maximum number of flags
is
a. RAL
b. POP PSW
c. XRA A
d. DCR A
Answer
Answer. c
48. XCHG instruction of 8085 exchanges the content of
a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer
Answer. c
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49. Direction flag is used with Rooma, Kanpur – 208 008
a. String instructions
b. Stack instructions
c. Arithmetic instructions
d. Branch instructions
Answer
Answer. a
50. What will be the contents of DE and HL register pairs respectively after the
execution of the following instructions?
LXIH, 2500 H
LXID, 0200 H
DAD D
XCHG
a. 0200 H, 2500 H
b. 0200 H, 2700 H
c. 2500 H, 0200 H
d. 2700 H, 0200 H
Answer
Answer. d
51. In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer
Answer. a
52. A ‘DAD H” instruction is the same as shifting each bit by one position to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer
Answer. c
53. When a program is being executed in an 8085 microprocessor, its program
counter contains
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a. the memory address as the instruction that is to be executed next.
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b. the memory address of the instruction that is being currently matched.
c. the total number of instructions in the program being executed.
d. the number of instructions in the current program that have already been
executed.
Answer
Answer. a
54. Which of the following data transfer is not possible in microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer
Answer. c
55. LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
d. loads English like command and generates the binary code
Answer
Answer. b
56. Which of the following instructions is closest match to the instruction POP PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer
Answer. a
57. How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer
Answer. c
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58. Which of the following 8085 instruction will require maximum T-states for
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execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer
Answer. c
59. In 8085 microprocessor, which mode of addressing does the instruction CMP M
use?
a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer
Answer. c
60. With reference to 8085 microprocessor, which of the following statements are
correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer
Answer. d
61. Assume that the accumulator and the register C of 8085 microprocessor contain
respectively F0 H
and OF H initially. What will be the content of accumulator after execution of
instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
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Answer
Rooma, Kanpur – 208 008
Answer. b
62. It is desired to multiply the numbers 0A H by OB H and store the result in the
accumulator. The numbers are available in registers B and C respectively. A part of
the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C
b. ADD B; JNZ LOOP; DCR C
c. DCR C; JNZ LOOP; ADD B
d. ADD B; DCR C; JNZ LOOP
Answer
Answer. d
63. Find the content of the accumulator after the execution of the following
program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer
Answer. c
64. The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
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The content of accumulator when the Rooma,
program counter reaches 0107 H is
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a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer
Answer. c
65. The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer
Answer. a
66. The content of accumulator are 70 H. Initially all flags are zero. What will be
values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer
Answer. d
67. A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR instruction will be executed?
a. 255
b. 510
c. 65025
d. 65279
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Answer
Rooma, Kanpur – 208 008
Answer. d
68. What is content of accumulator of 8085 microprocessor after the execution of
XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer
Answer. a
69. The 8085 programming manual says that it takes seven T states to fetch and
execute the MOV instruction. If the system clock has a frequency of 2.5 MHz, how
long is an instruction Cycle?
a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer
Answer. d
70. The instruction PCHL, in 8085 is used for
a. Load PC with contents of HL.
b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer
Answer. a
71. The following instruction copies a byte of data from the accumulator into the
memory address given in the instruction
a. STA address
b. LDAX B
c. LHLD address
d. LDA address
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Answer
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Answer. a
72. The instruction that exchanges top of stack with HL pair is
a. XTHL
b. SPHL
c. PUSH H
d. POP H
Answer
Answer. a
73. In 8085 microprocessor, during PUSH PSW Operation, Stack pointer is
a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer
Answer. b
74. While a program is being executed in an Intel 8085 microprocessor, the
program counter of the microprocessor contains:
a. The memory address of the instruction that is being currently executed.
b. The memory address of the instruction that is to be executed next.
c. The number of instructions that have already been executed.
d. The total number of instructions in the current program still to be executed.
Answer
Answer. b
75. The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer
Answer. c
76. If the status of the control lines SI and SO is LOW, then 8085 microprocessor is
performing
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a. Reset operation Rooma, Kanpur – 208 008
b. HOLD operation
c. Halt operation
d. Interrupt acknowledge
Answer
Answer. c
77. LXI SP, 7FFF H
MVI A, 25 H
XRI 02 H
PUSH PSW
POP H
MOV A,L
ORI 10 H
HLT
What are the contents of A, H, L, SP and PSW registers after executing the above set
of instructions? Assume undefined flags always remain clear.
a. 10H, 25H, 00H, 7FFFH, 00H respectively
b. 14H, 27H, 04H, 7FFFH, 04H respectively
c. 14H, 25H, 00H. 7FFFH, 04H respectively
d. 10H, 27H, 04H, 7FFFH, 00H respectively
Answer
Answer. b
78. The content of the programme counter of an 8085 microprocessor is
a. the total number of instructions in the program already executed.
b. the total number of times a subroutine is called.
c. the memory address of the instruction that is being currently executed.
d. the memory address of the instruction that is to be executed next.
Answer
Answer. d
79. The opcode for the instruction “Add Immediately to Accumulator with carry” in
8085 microprocessor is
a. ADI
b. ACI
c. ADC
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d. ADD Rooma, Kanpur – 208 008
Answer
Answer. b
80. MVI A, AA H
ORI FFH
RRC
RRC
CMC
INR A
What are the contents of A and PSW registers after executing the above set of
instructions in sequence?
a. AAH and 00H
b. FFH and 66H
c. 00H and 54H
d. 00H and 00H
Answer
Answer. c
81. For which one of the following, the instruction XRA A in 8085 microprocessor
can be used?
a. Set the carry flag
b. Set the zero flag
c. Reset the carry flag and clear the accumulator
d. Transfer FFH to the accumulator
Answer
Answer. b
82. An 8085 microprocessor is executing the programme as follows:
MVI A, 20H
MVI B, 10H
BACK: NOP
ADD B
RLC
JNC BACK
HLT
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How many times the instruction NOP will be executed?
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a. 4
b. 3
c. 2
d. 1
Answer
Answer. b
83. The stack pointer of an 8085 microprocessor is ABCD H. At the end of execution
of the sequence of instructions, what will be the content of the stack pointer?
PUSH PSW
XTHL
PUSH D
JMP FC70 H
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer
Answer. c
84. What is the correct 8085 assembly language instruction that stores the contents
of H and L registers into the memory locations 1080 H and 1081 H respectively?
a. SPHL 1080 H
b. SHLD 1080 H
c. STAX 1080 H
d. SPHL 1081 H
Answer
Answer. b
85. When the operand requires for instruction is stored inside the processor, then
What this addressing mode is called?
a. Direct
b. Register
c. Implicit
d. Immediate
Answer
Answer. b
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86. Which one of the following addressing technique is not used in 8085
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microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer
Answer. d
87. In an instruction of 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer
Answer. b
88. Which one is the indirect addressing mode in the following instructions?
a. LXI H 2050 H
b. MOV A, B
c. LDAX B
d. LDA 2050 H
Answer
Answer. c
89. The addressing mode used in the instruction JMP F347 H in case of an Intel
8085A microprocessor is which one of the following?
a. Direct
b. Register—indirect
c. Implicit
d. Immediate
Answer
Answer. d
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90. Carry flag is not affected after the execution of
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a. ADD B
b. SBB B
c. INR B
d. ORA B
Answer
Answer. c
91. The contents of the Program Counter (PC), when the microprocessor is reading
from 2FFF H memory location, will be
a. 2FFE H
b. 2FFF H
c. 3000 H
d. 3001 H
Answer
Answer. c
92. If the HLT instruction of an Intel 8085A microprocessor is executed
a. the microprocessor is disconnected from the system bus till the RESET is
pressed.
b. the microprocessor halts the execution of the program and returns to the
monitor.
c. the microprocessor enters into a HALT state and the buses are tri-stated.
d. the microprocessor reloads the program counter from the locations 0024 H
and 0025 H.
Answer
Answer. c
93. The stack pointer of an 8085 A microprocessor contains ABCD H.
PUSH PSW
XTHL
PUSH D
JMP EC75 H
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At the end of the execution of the above instructions, what would be the content of
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the stack pointer?
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer
Answer. c
94. In an Intel 8085 A, what is the content of the Instruction Register (IR)?
a. Op-code for the instruction being executed
b. Operand for the instruction being executed
c. Op-code for the instruction to be executed next
d. Operand for the instruction to be executed next
Answer
Answer. a
95. The content of the Program Counter of an intel 8085A microprocessor specifies
which one of the following?
a. The address of the instruction being executed
b. The address of the instruction executed earlier
c. The address of the next instruction to be executed
d. The number of instructions executed so far
Answer
Answer. c
96. Which one of the following statement does not describe property/characteristic
of a stack pointer register in 8085 microprocessor?
a. It points to the top of the stack.
b. It is UP/DOWN counter
c. It is automatically initialized to 0000 H on power-on
d. It is a 16-bit register
Answer
Answer. c
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97. Which one of the following instructions is a 3-byte instruction?
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a. MVI A
b. LDAX B
c. JMP 2050 H
d. MOV A,M
Answer
Answer. c
98. In 8085, the DAA instruction is used for
a. Direct Address Accumulator
b. Double Add Accumulator
c. Decimal Adjust Accumulator
d. Direct Access Accumulator
Answer
Answer. c
99. When an 8086 executes an INT type instruction, it?
a. Resets both IF and TF flags
b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer
Answer. a
100. When an 8086 executes an INT type instruction, it?
a. Resets both IF and TF flags
b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer
Answer. a
101. How many times will the following loop be executed?
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LXI B, 0010 H Rooma, Kanpur – 208 008
LOOP: DCX B
MOV A, B
ORA C
JNZ LOOP
Select the correct answer using the code given below:
a. 10
b. 100
c. 16
d. 15
Answer
Answer. c
102. Read the following assembly language program segment of the 8085
microprocessor:
LXIH, 2501 H
MOV A, L
ORI F0 H
MOV L, A
MOV A, H
ANI F0 H
MOV H, A
HLT
What are the contents of A, H and L registers after executing the above set of
instructions in sequence?
a. Contents of A, H and L registers are 25, 20 and F1, respectively
b. Contents of A, H and L registers are 05, 25 and 01, respectively
c. Contents of A, H and L registers are 20, 20 and F1, respectively
d. Contents of A, H and L registers are 25, 05 and 01, respectively
Answer
Answer. c
103. On execution of the following segment 0f instructions in sequence
MVI A, 91H
XRI 91 H
Which one of the following is correct?
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a. Content of accumulator is 00 H. Carry, Auxiliary Carry and Zero flag set to 0, 1
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and 0, respectively.
b. Content of accumulator is 91 H. Carry, Auxiliary Carry and Zero flag set to 0, 0
and 1, respectively.
c. Content of accumulator is 00 H. Carry, Auxiliary Carry and Zero flag set to 0, 0
and 1, respectively.
d. Content of accumulator is 91 H. Carry, Auxiliary Carry and Zero flag set to 0, 1
and 0, respectively.
Answer
Answer. c
104. Consider the following statements:
1. Indirect addressing is not possible for mapped I/O port addresses
2. Pointers can not be used to access memory-mapped I/O addresses
3. Fewer machine instructions can be used with I/O mapped I/O addressing as
compared to memory mapped I/O addressing
4. With an 8085 microprocessor, one can access at the most 512 devices with
unique addresses using I/O mapped I/O addressing
Which of these statements are correct?
a. 1, 2 and 3
b. 2 and 4
c. 3 and 4
d. 1 and 3
Answer
Answer. d
105. The contents of memory locations 2000 H, 2001 H and 2002 H are AAH, BBH
and CCH respectively. What are the contents of H and L registers after executing
the following instructions in sequence?
LXI H, 2001 H
LHLD 2001 H
Select the correct answer using the codes given below:
a. Contents of H and L registers are 20 H and 01 H, respectively
b. Contents of H and L registers are AAH and BBH, respectively
c. Contents of H and L registers are BBH and CCH, respectively
d. Contents of H and L registers are CCH and BBH, respectively
Answer
Answer. d
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106. The following sequences of instructions are executed by an 8085
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microprocessor:
1000 LXI SP, 27FF
1003 CALL 1006
1006 POPH
What are the contents of the stack pointer (SP) and the HL register pair on
completion of execution of these instructions?
a. SP = 27 FF, HL = 1003
b. SP = 27 FD, HL = 1003
c. SP = 27 FF, HL = 1006
d. SP = 27 FD, HL = 1006
Answer
Answer. c
107. INR instruction of 8085 does not affect carry flag. Which of the following is
correct about INR instruction?
a. Overflow cannot be detected
b. Overflow can be detected
c. If a programme requires overflow to be detected, ADD instruction should be
used instead of INR
d. It can be used to increase the contents of the BC register pair
Answer
Answer. c
108. Consider the following 8085 instructions:
ANA A, ORA A, XRA A, SUB A, CMP A.
Now, consider the following statements:
1. All are arithmetic and logic instructions
2. All cause the accumulator to be cleared irrespective of its original contents
3. All reset the carry flag
4. All of them are 1-byte instructions
Which of these statements is/are correct?
a. 1, 2, 3 and 4
b. 2 only
c. 1, 2 and 4
d. 1,3 and 4
Answer
Answer. d
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109. Consider the program given below, which transfer a block of data from one
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place in memory to another:
MVI C, 0B H
LXI H, 2400 H
LXI D, 3400 H
L1: MOV A, M
STAX D
INR L
INR E
DCR C
JNZ L1
What is the total number of memory accesses (including instruction fetches) carried
out?
a. 118
b. 140
c. 98
d. 108
Answer
Answer. a
110. Consider the following statements about register indirect addressing:
1. It helps in writing code that executes faster
2. It helps in writing compact code
3. It allows reuse of memory CPU data transfer instruction
4. It is essential for stack operations
Which of these statements are correct?
a. 1, 3 and 4
b. 1, 2 and 4
c. 2,3 and 4
d. 1,2 and 3
Answer
Answer. b
111. Which one of the following 8085 assembly language instructions does not
affect the contents of the accumulator?
a. CMA
b. CMP B
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c. DAA Rooma, Kanpur – 208 008
d. ADD B
Answer
Answer. b
112. If the accumulator of an Intel 8085A microprocessor contains 37 H and the
previous operation has set the carry flag, the instruction ACI 56 H will result in
a. 8E H
b. 94H
c. 7E H
d. 84 H
Answer
Answer. a
113. Examine the following instruction to be executed by a 8085 microprocessor.
The input port has an address of 01 h and has a data 05 h to input:
IN 01 H
ANI 80 H
After the execution of the two instructions the following flag portions may occur:
1. Zero flag is set
2. Zero flag is reset
3. Carry flag is cleared
4. Auxiliary carry flag is set
Select the correct answer using the codes given below:
a. 1 and 3
b. 2, 3 and 4
c. 1, 3 and 4
d. 1, 2 and 4
Answer
Answer. c
114. For 8085 microprocessor, the instruction RST 6 restarts subroutine at address
a. 00 H
b. 03 H
c. 30 H
d. 33 H
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Answer
Rooma, Kanpur – 208 008
Answer. c
115. Which one of the following function is performed by the 8085 instruction MOV
H, C?
a. Moves the contents of H register to C register
b. Moves the contents of C register to H register
c. Moves the contents of C register to HL pair
d. Moves the contents of HL pair to C register
Answer
Answer. b
116. Consider the execution of the following instructions by an 8085
microprocessor:
LXI H, 01FF H
SHLD 2050H
After execution, the contents of memory locations 2050H and 2051 H and the
registers H and L, will be
a. 2050 H→ FF; 2051 H→ 01 ; H→ FF; L→ 01
b. 2050 H→ 01; 2051 H→ FF ; H→ FF; L→ 01
c. 2050 H→ FF; 2051 H→ 01 ; H→ 01; L→ FF
d. 2050 H→ FF; 2051 H→ 01 ; H→ 00; L→ 00
Answer
Answer. c
117. In 8085 microprocessor, a number of the form 000XXXX0 stored in the
accumulator is processed by the programme (Assume CY = 0) as follows
ANI FF H
RAL
MOV B, A
ANI FF H
RAL
ANI FF H
RAL
ADD B
The operation carried out by the programme is
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a. multiplication of accumulator content by 10
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b. complement of accumulator content
c. multiplication of accumulator content by 9
d. rotation of accumulator content three times
Answer
Answer. a
118. When RET instruction is executed by any Subroutine then
a. the top of the stack will be popped out and assigned to the PC
b. without any operation, the calling program would resume from instruction
immediately following the call instruction
c. the PC will be incremented after the execution of the instruction
d. without any operation, the calling program would resume from instruction
immediately following the call instruction, and also the PC will be incremented
after the execution of the instruction
Answer
Answer. a
119. An 8085 microprocessor-based system uses a 4 K x 8-bit RAM whose starting
address is AA00 H. The address of the last byte in this RAM is
a. 0FFF H
b. 1000 H
c. B9FF H
d. BA00 H
Answer
Answer. c
120. The address bus of Intel 8085 is 16-bit wide and hence the memory which can
be accessed by this address bus is
a. 2 k bytes
b. 4 k bytes
c. 16 k bytes
d. 64 k bytes
Answer
Answer. d
121. To address the full memory space of an Intel 8085 microprocessor four RAMS
of different sizes are available:
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1. 8K x 8 Rooma, Kanpur – 208 008
2. 16K x 4
3. 32K x 4
4. 32K x 16
What minimal combination of chip(s) will serve the purpose?
a. 1, 2, 3 and 4
b. 2
c. 3
d. 4
Answer
Answer. d
122. An example of 8085 instruction that uses direct addressing is
a. RLC
b. STA
c. RRC
d. CMA
Answer
Answer. b
123. A 16 bit memory address register can address memory locations of
a. 16 k
b. 32 k
c. 64 k
d. 128 k
Answer
Answer. c
124. What are the number of memories required of size 16 x 4 to design a memory
of size 64 x 8?
a. 2
b. 4
c. 6
d. 8
Answer
Answer. d
125. Which stack is used in 8085 microprocessors?
a. FIFO
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b. FILO Rooma, Kanpur – 208 008
c. LIFO
d. LILO
Answer
Answer. c
126. Memory chips of four different sizes as below are available:
1. 32 K x 4
2. 32 K x 16
3. 8 K x 8
4. 16 K x 4
All the memory chips as mentioned in the above list are Read/Write memory. What
minimal combination of chips or chip alone can map full address space of 8085
microprocessor?
a. 1 and 2
b. 1 only
c. 2 only
d. 4 only
Answer
Answer. b
127. A memory system of 64 Kbytes needs to be designed with RAM chips of 1
Kbyte each, and a decoder tree constructed with 2 : 4 decoder chips with “Enable”
input. What is the total number of decoder chips?
a. 21
b. 64
c. 32
d. 25
Answer
Answer. a
128. Which one of the following statements is correct?
a. ROM is 3 Read/Write Memory
b. PC points to the last instruction that was executed
c. Stack works on the principle of LIFO
d. All instructions affect the flags
Answer
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Answer. c Rooma, Kanpur – 208 008
129. How many and which types of machine cycles are needed to execute PUSH
PSW by an Intel 8085 A microprocessor?
a. 2; Fetch and Memory write
b. 3; Fetch and 2 Memory write
c. 3; Fetch and 2 Memory read
d. 3; Fetch, Memory read and Memory write
Answer
Answer. b
130. Memory-mapped I/O-scheme for the allocation of address to memories and
I/O devices, is used
for
a. small systems
b. large systems
c. both large and small systems
d. very large systems
Answer
Answer. A
Introduction to Microcomputer System
Module 01
1. A microprocessor is a_________ chip integrating all the functions of a CPU of a computer.
A. multiple
B. single
C. double
D. triple
ANSWER: B
2. Microprocessor is a/an_________circuit that functions as the CPU of the compute
A. electronic
B. mechanic
C. integrating
D. processing
ANSWER: A
3. Microprocessor is the ________ of the computer and it perform all the computational tasks
A. main
B. heart
C. important
D. simple
ANSWER: B
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4. The purpose of the microprocessor is to control
A. memory Rooma, Kanpur – 208 008
B. switches
C. processing
D. tasks
ANSWER: A
5. The first digital electronic computer was built in the year
A. 1950
B. 1960
C. 1940
D. 1930
ANSWER: C
6. In 1960’s texas institute invented
A. integrated circuits
B. microprocessor
C. vacuum tubes
D. transistors
ANSWER: A
7. The intel 8086 microprocessor is a processor
A. 8 bit
B. 16 bit
C. 32 bit
D. 4 bit
ANSWER: B
8. The microprocessor can read/write 16 bit data from or to
A. memory
B. I /O device
C. processor
D. register
ANSWER: A
9. In 8086 microprocessor , the address bus is bit wide
A. 12 bit
B. 10 bit
C. 16 bit
D. 20 bit
ANSWER: D
10. The work of EU is
A. encoding
B. decoding
C. processing
D. calculations
ANSWER: B
11. The 16 bit flag of 8086 microprocessor is responsible to indicate
A. the condition of result of ALU operation
B. the condition of memory
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C. the result of addition
D. the result of subtraction Rooma, Kanpur – 208 008
ANSWER: A
12. The CF is known as
A. carry flag
B. condition flag
C. common flag
D. single flag
.ANSWER: A
13. The SF is called as
A. service flag
B. sign flag
C. single flag
D. condition flag
ANSWER: B
14. The OF is called as
A. overflow flag
B. overdue flag
C. one flag
D. over flag
ANSWER: A
15. The IF is called as
A. initial flag
B. indicate flag
C. interrupt flag
ANSWER: C
16. The register AX is formed by grouping
A. AH & AL
B. BH & BL
C. CH & CL
ANSWER: A
17. The SP is indicated by
A. single pointer
B. stack pointer
C. source pointer
ANSWER: B
18. The BP is indicated by
A. base pointer
B. binary pointer
C. bit pointer
ANSWER: A
19. The SS is called as
A. single stack
B. stack segment
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C. sequence stack
ANSWER: B Rooma, Kanpur – 208 008
20. The index register are used to hold
A. memory register B. offset address
C. segment memory
ANSWER: A
21. The BIU contains FIFO register of size
bytes
A. 8
B. 6
C. 4
ANSWER: B
22. The BIU prefetches the instruction from memory and store them in
A. queue
B. register
C. memory
ANSWER: A
23. The 1 MB byte of memory can be divided into segment
A. 1 Kbyte
B. 64 Kbyte
C. 33 Kbyte
ANSWER: B
24. The DS is called as
A. data segment
B. digital segment
C. divide segment
ANSWER: A
25. The CS register stores instruction in code segment
A. stream
B. path
C. codes
ANSWER: C
26. The IP is bits in length
A. 8 bits
B. 4 bits
C. 16 bits
ANSWER: C
27. The push source copies a word from source to
A. stack
B. memory
C. register
ANSWER: A
28. LDs copies to consecutive words from memory to register and
A. ES
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B. DS
C. SS Rooma, Kanpur – 208 008
ANSWER: B
29. INC destination increments the content of destination by
A. 1
B. 2
C. 30
ANSWER: A
30. IMUL source is a signed
A. multiplication
B. addition
C. subtraction
D. division
ANSWER: A
31._________destination inverts each bit of destination
A. NOT
B. NOR
C. AND
D. OR
ANSWER: A
32. The JS is called as
A. jump the signed bit
B. jump single bit
C. jump simple bit
D. jump signal it
ANSWER: A
33. Instruction providing both segment base and offset address are called
A. below type
.B. far type
C. low type
D. high type
ANSWER: B
34. The conditional branch instruction specify
for branching
A. conditions
B. instruction
C. address
D. memory
ANSWER: A
35. The microprocessor determines whether the specified condition exists or not by testing the
A. carry flag
B. conditional flag
C. common flag
D. sign flag
ANSWER: B
Allenhouse Institute of Technology (UPTU Code : 505)
36. The LES copies to words from memory to register and
A. DS Rooma, Kanpur – 208 008
B. CS
C. ES
D. DS
ANSWER: C
37. The________translates a byte from one code to another code
A. XLAT
B. XCHNG
C. POP
D. PUSH
ANSWER: A
38. The________contains an offset instead of actual address
A. SP
B. IP
C. ES
D. SS
ANSWER: B
39. The 8086 fetches instruction one after another from________of memory
A. code segment
B. IP
C. ES
D. SS
ANSWER: A
40. The BIU contains FIFO register of size 6 bytes called
A. queue
B. stack
C. segment
D. register
ANSWER: A
41. The_________is required to synchronize the internal operands in the processor CLK Signal
A. UR Signal
B. Vcc
C. AIE
D. Ground
ANSWER: A
42. The pin of minimum mode AD0-AD15 has_______address
A. 16 bit
B. 20 bit
C. 32 bit
D. 4 bit
ANSWER: B
43. The pin of minimum mode AD0- AD15 has _________data bus
A. 4 bit
B. 20 bit
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C. 16 bit
D. 32 bit Rooma, Kanpur – 208 008
ANSWER: C
44. The address bits are sent out on lines throughA. A16-19
B. A0-17
C. D0-D17
D. C0-C17
ANSWER: A
45.________is used to write into memory
A. RD
B. WR
C. RD / WR
D. CLK
ANSWER: B
46. The functions of Pins from 24 to 31 depend on the mode in which________is operating
A. 8085
B. 8086
C. 80835
D. 80845
ANSWER: B
47. The RD, WR, M/IO is the heart of control for a_______mode
A. minimum
B. maximum
C. compatibility mode
D. control mode
ANSWER: A
48. In a minimum mode there is a________on the system bus
A. single
B. double
C. multiple
D. triple
ANSWER: A
49. If MN/MX is low the 8086 operates in______mode
A. Minimum
B. Maximum
C. both (A) and (B) D. medium
ANSWER: B
50. In max mode, control bus signal So,S1 and S2 are sent out in _______form
A. decoded
B. encoded
C. shared
D. unshared
ANSWER: B
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51.What type of circuit is used at the interface point of an input port?
A. decoder Rooma, Kanpur – 208 008
B. latch
C. tristate buffer
D. none of the above
ANSWER: C
52.Because microprocessor CPUs do not understand mnemonics as they are, they have to be converted to ________.
A. hexadecimal machine code
B. binary machine code
C. assembly language
D. all of the above
ANSWER:B
53.A register in the microprocessor that keeps track of the answer or results of any arithmetic or logic operation is the:
A. stack pointer
B. program counter
C. instruction pointer
D. accumulator
ANSWER:D
54.What is the difference between a mnemonic code and machine code?
A. There is no difference.
B. Machine codes are in binary, mnemonic codes are in shorthand English.
C. Machine codes are in shorthand English, mnemonic codes are in binary.
D. None of the above
ANSWER:B
55. Which bus is a bidirectional bus?
A. address bus
B. data bus
C. address bus and data bus
D. none of the above
ANSWER : B
56. Which of the following buses is primarily used to carry signals that direct other ICs to find out what type of
operation is being performed?
A. data bus
B. control bus
C. address bus
D. address decoder bus
ANSWER: B
57.What kind of computer program is used to convert mnemonic code to machine code?
A. debug
B. assembler
C. C++
D. Fortran
ANSWER: B
58. Which of the following are the three basic sections of a microprocessor unit?
A. operand, register, and arithmetic/logic unit (ALU)
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B. control and timing, register, and arithmetic/logic unit (ALU)
C. control and timing, register, and memory Rooma, Kanpur – 208 008
D. arithmetic/logic unit (ALU), memory, and input/output
ANSWER:B
59.Which one of the following is not a vectored interrupt?
A. TRAP
B. INTR
C. RST 7.5
D. RST 3
ANSWER: D
60. 8085 microprocessor has how many pins
A. 30
B. 39
C. 40
D. 41
ANSWER: C
61.The first micro-processor had a (n) ______.
A. 1-bit data bus
B. 2- bit data bus
C.3-bit data bus
D.4-bit data bus
ANWER: D
Explanation: Intel introduced its first 4-bit microprocessor in 1971.
62.__________ processor is first introduced by the Intel in 1971.
A. 8080
B.4004
C. 8008
D 8085
ANSWER: B
Explanation: Intel introduced its first 4-bit microprocessor 4004 in 1971.
63.Which of the following is/are 8-bit micro processor?
A.8008
B. 8080
C. 8085
D. All of the mentioned
ANSWER: D
Explanation: The microprocessor 8008 in 1972, 8080 in 1974 and 8085 all are 8-bit microprocessors.
64.The limitations of the 8-bit microprocessors was/were is ________.
A. Low speed of execution
B. Low memory addressing capability
C. Less powerful instruction set
D. All of the mentioned
ANSWER: D
Explanation: The main limitations of 8-bit microprocessor were their low speed of execution, low memory addressing
capability, limited number of general purpose registers and a less powerful instruction set.
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65.The number of address and data lines of 8085 are____.
A. 8 and 8 Rooma, Kanpur – 208 008
B. 16 and 8
C. 8 and 16
D. 16 and 16
ANSWER: B
Explanation: The 8085 microprocessor is a 8-bit microprocessor having 16 address lines and 8 data lines.
66.Intel’s 8086 were launched in the year_____.
A. 1971
B. 1972
C. 1974
D. 1978
ANSWER: d
Explanation: Intel’s 8086 is the first 16-bit microprocessor launched in 1978.
67.Which is the microprocessor comprises?
A. Register section
B. One or more ALU
C. Control unit
D. All of the mentioned
ANSWER : D
Explanation: The major modules of a microprocessor are registers, CPU (A.L.U+ control unit).
68.A 16-bits address bus can generate _____addresses.
A. 32767
B. 25652
C. 65536
D. None of the mentioned
Answer: c
Explanation: By using n-address lines 2^n addresses can be generated. Therefore by using 16- address lines 2^16 =
65,536 addresses can be generated.
69.The register of 8086 are_____ bits in size.
a) 8
b) 12
c) 16
d) 20
ANSWER: C
Explanation: 8086 microprocessor is a 16-bit microprocessor and all the registers of 8086 are 16-bit registers.
70.Which of the following registers are not available in 8086 microprocessor?
A. General data register
B. Segment registers
C. Pointer and Index register
D. All of the mentioned
ANSWER: D
Explanation: 8086 containing powerful set of registers containing general purpose and special purpose registers. The
special purpose registers are used as segment registers, pointers, index registers. It has a 16-bit Flag register.
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71. The disadvantage of machine level programming is
A. time consuming Rooma, Kanpur – 208 008
B. chances of error are more
C. debugging is difficult
D. all of the mentioned
ANSWER: D
Explanation: The machine level programming is complicated.
72. The coded object modules of the program to be assembled are present in
A .ASM file
B .OBJ file
C .EXE file
D.OBJECT file
ANSWER: B
Explanation: .OBJ file is created with same name as source file and extension .OBJ. It contains the coded object modules
of the program to be assembled.
73. The advantages of assembly level programming are
A. flexibility of programming is more
B. chances of error are less
C. debugging is easy
D. all of the mentioned
ANSWER: D
Explanation: The assembly level programming is more advantageous than the machine level programming.
74. The extension that is essential for every assembly level program is
A. .ASP
B. .ALP
C. .ASM
D. .PGM
ANSWER:C
Explanation: All the files should have the extension, .ASM
75. The directory that is under work must have the files that are related to
A. Norton’s editor
B. Assembler
C. Linker
D. All of the mentioned
ANSWER: D
Explanation: Before starting the process of entering a small program on PC, ensure that all the files namely Norton’s
editor, assembler, linker and debugger are available in the same directory in which work is been done.
Architecture of 8086 Microprocessor
Module 02
1. 8086 Microprocessor supports _______ modes of operation.
A. 2
B. 3
C. 4
D. 5
Answer : A
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Explanation: It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable
for system having multiple processors and Minimum modeRooma,
is Kanpur – 208
suitable for 008
system having a single processor.
2. Which of the following is not a Features of 8086?
A. It uses two stages of pipelining
B. It is available in 3 versions based on the frequency of operation
C. Fetch stage can prefetch up to 6 bytes of instructions
D. It has 512 vectored interrupts.
Answer : D
Explanation: It has 256 vectored interrupts is true Features of 8086.
3. 8086 can access up to?
A. 512KB
B. 1Mb
C. 2Mb
D. 256KB
Answer: B
Explanation: 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.
4. 8086 has ___ address bus.
A. 16-bit
B. 18-bit
C. 20-bit
D. 24-bit
Answer : C
Explanation: Address Bus : 8085 has 16-bit address bus while 8086 has 20-bit address bus.
5. Which flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0?
A. Binary bit
B. Zero flag
C. Sign flag
D. Overflow flag
Answer : B
Explanation: Zero flag : This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0.
6. Which flag represents the result when the system capacity is exceeded?
A. Carry flag
B. Auxiliary flag
C. Trap flag
D. Overflow flag
Answer : D
Explanation: Overflow flag : This flag represents the result when the system capacity is exceeded.
7. It is an edge triggered input, which causes an interrupt request to the microprocessor.
A. NMA
B. INTR
C. INTA
D. ALE
Answer : A
Explanation: NMI : It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which
causes an interrupt request to the microprocessor.
Allenhouse Institute of Technology (UPTU Code : 505)
8. It is used to write the data into the memory or the output device depending on the status of M/IO signal.
A. IR Rooma, Kanpur – 208 008
B. HLDA
C. HR
D. WR
Answer : D
Explanation: WR : It stands for write signal and is available at pin 29. It is used to write the data into the memory or the
output device depending on the status of M/IO signal.
9. Which instruction is Used to load the address of operand into the provided register?
A. LEA
B. LDS
C. LES
D. LAHF
Answer : A
Explanation: LEA : Used to load the address of operand into the provided register.
10. The different ways in which a source operand is denoted in an instruction is known as
A. Instruction Set
B. Interrupts
C. 8086 Configuration
D. Addressing Modes
Answer : D
Explanation: The different ways in which a source operand is denoted in an instruction is known as addressing modes.
There are 8 different addressing modes in 8086 programming
11. The remaining address line of ______ bus is decoded to generate chip select signal
A. Data
B. Address
C. Control bus
D. Both (a) and (b)
Answer : B
12. _______ signal is generated by combining RD and WR signals with IO/M
A. Control
B. Memory
C. Register
D. System
Answer : A
13. Memory is an integral part of a _______ system
A. Supercomputer
B. Microcomputer
C. Mini computer
D. Mainframe computer
Answer : B
14. _____ has certain signal requirements write into and read from its registers
A. Memory
B. Register
C. Both (a) and (b)
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D. Control
Answer : A Rooma, Kanpur – 208 008
15. An _________ is used to fetch one address
A. Internal decoder
B. External decoder
C. Encoder
D. Register
Answer : A
16. The primary function of the _____________ is to accept data from I/P devices
A. Multiprocessor
B. microprocessor
C. Peripherals
D. Interfaces
Answer : B
17. ___________ signal prevent the microprocessor from reading the same data more than one
A. pipelining
B. Handshaking
C. Controlling
D. Signaling
Answer : B
18. Bits in IRR interrupt are ______
A. Reset
B. Set
C. Stop
D. Start
Answer : B
19. __________ generate interrupt signal to microprocessor and receive acknowledge
A. Priority resolver
B. Control logic
C. Interrupt request register
D. Interrupt register
Answer : B
20. The _______ pin is used to select direct command word
A. A0
B. D7-D6
C. A12
D. AD7-AD6
Answer : A
21. 8086 Microprocessor supports _______ modes of operation.
A. 2
B. 3
C. 4
D. 5
Answer : A
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Explanation: It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable
for system having multiple processors and Minimum modeRooma,
is Kanpur – 208
suitable for 008
system having a single processor.
22. Which of the following is not a Features of 8086?
A. It uses two stages of pipelining
B. It is available in 3 versions based on the frequency of operation
C. Fetch stage can prefetch up to 6 bytes of instructions
D. It has 512 vectored interrupts.
Answer: D
Explanation: It has 256 vectored interrupts is true Features of 8086.
23. 8086 can access up to?
A. 512KB
B. 1Mb
C. 2Mb
D. 256KB
Answer: B
Explanation: 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.
24. 8086 has ___ address bus.
A. 16-bit
B. 18-bit
C. 20-bit
D. 24-bit
Answer: C
Explanation: Address Bus : 8085 has 16-bit address bus while 8086 has 20-bit address bus.
25. Which flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0?
A. Binary bit
B. Zero flag
C. Sign flag
D. Overflow flag
Answer: B
Explanation: Zero flag : This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0.
26. Which flag represents the result when the system capacity is exceeded?
A. Carry flag
B. Auxiliary flag
C. Trap flag
D. Overflow flag
Answer : D
Explanation: Overflow flag : This flag represents the result when the system capacity is exceeded.
27. It is an edge triggered input, which causes an interrupt request to the microprocessor.
A. NMA
B. INTR
C. INTA
D. ALE
Answer : A
Explanation: NMI : It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which
causes an interrupt request to the microprocessor.
Allenhouse Institute of Technology (UPTU Code : 505)
28. It is used to write the data into the memory or the output device depending on the status of M/IO signal.
A. IR Rooma, Kanpur – 208 008
B. HLDA
C. HR
D. WR
Answer: D
Explanation: WR : It stands for write signal and is available at pin 29. It is used to write the data into the memory or the
output device depending on the status of M/IO signal.
29. Which instruction is Used to load the address of operand into the provided register?
A. LEA
B. LDS
C. LES
D. LAHF
Answer: A
Explanation: LEA : Used to load the address of operand into the provided register.
30. The different ways in which a source operand is denoted in an instruction is known as
A. Instruction Set
B. Interrupts
C. 8086 Configuration
D. Addressing Modes
Answer: D
Explanation: The different ways in which a source operand is denoted in an instruction is known as addressing modes.
There are 8 different addressing modes in 8086 programming
31. IP stand for
A. Industry pointer
B. Instruction pointer
C. Index pointer
D. None of these
Answer : B
32. Which has great important in modular programming
A. Stack segment
B. Queue segment
C. Array segment
D. All of these
Answer : A
33. Which register containing the 8086/8088 flag
A. Status register
B. Stack register
C. Flag register
D. Stand register
Answer :A
34. How many bits the instruction pointer is wide
A. 16 bit
B. 32 bit
C. 64 bit
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D. 128 bit
Answer :A Rooma, Kanpur – 208 008
35. How many type of addressing in memory
A. Logical address
B. Physical address
C. Both A and B
D. None of these
Answer : C
36. The size of each segment in 8086 is
A. 64 kb
B. 24 kb
C. 50 kb
D. 16kb
Answer :A
37. The physical address of memory is
A.20 bit
B. 16 bit
C. 32 bit
D. 64 bit
Answer :A
38. The _______ address of a memory is a 20 bit address for the 8086 microprocessor
A. Physical
B. Logical
C. Both
D. None of these
Answer :A
39. The pin configuration of 8086 is available in the________
A. 40 pin
B. 50 pin
C. 30 pin
D. 20 pin
Answer : A
40. DIP stand for
A. Deal inline package
B. Dual inline package
C. Direct inline package
D. Digital inline package
Answer :B
41.If MN/MX is low, the 8086 operates in _____ mode.
A. Minimum mode
B. Maximum mode
C. Both A and B
D. Control mode
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Answer: B
Rooma,in
Explanation: If MN/MX’ is tied to Ground, the 8086 operates Kanpur – 208 008
maximum mode and MN/MX’ is tied
to Vcc, the processor 8086 operates in minimum mode
42Which of the following processor supports pipelined architecture?
A. 8080
B. 8085
C. 8086
D. 8008
Answer: C
Explanation: 8086 microprocessor supports pipelined architecture because of its
predecoded instruction byte queue; it can fetch the next instruction while executing the
current instruction.
Instruction set and programming of 8086
Module 03
1. The instruction, MOV AX, 0005H belongs to the address mode
a) register
b) direct
c) immediate
d) register relative
Answer: c
Explanation: In Immediate addressing mode, immediate data is a part of instruction and appears in the form of
successive byte or bytes.
2. The instruction, MOV AX, 1234H is an example of
a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
Answer: c
Explanation: Since immediate data is present in the instruction.
3. The instruction, MOV AX, [2500H] is an example of
a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
Answer: b
Explanation: Since the address is directly specified in the instruction as a part of it.
4. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
Answer: b
Explanation: Since register is used to refer the address.
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5. The instruction, MOV AX,[BX] is an example of
a) direct addressing mode Rooma, Kanpur – 208 008
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
Answer: d
Explanation: Since the register used to refer to the address is accessed indirectly.
6. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned
Answer: c
Explanation: In the indexed addressing mode, the offset of an operand is stored and in the rest of them, address is
stored.
7. The addressing mode that is used in unconditional branch instructions is
a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
Answer: b
Explanation: In intrasegment indirect mode, the branch address is found as the content of a register or a memory
location.
8. If the location to which the control is to be transferred lies in a different segment other than the current one, then
the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode
Answer: d
Explanation: In intersegment mode, the control to be transferred lies in a different segment.
9. The instruction, JMP 5000H:2000H;
is an example of
a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode
Answer: c
Explanation: Since in intersegment direct mode, the address to which the control is to be transferred is in a different
segment.
10. The contents of a base register are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode
Answer: d
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Explanation: The effective address is formed by adding the contents of both base and index registers to a default
segment. Rooma, Kanpur – 208 008
11. Operation code field is present in :
a) programming language instruction
b) assembly language instruction
c) machine language instruction
d) none of the mentioned
Answer: c
Explanation: Machine language instruction format has one or more fields. The first one is the operation code field.
22. A machine language instruction format consists of
a) Operand field
b) Operation code field
c) Operation code field & operand field
d) none of the mentioned
Answer: c
Explanation: Machine language instruction format has both the fields.
23. The length of the one-byte instruction is
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
Answer: b
Explanation: This format is only one byte long.
24. The instruction format ‘register to register’ has a length of
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
Answer: a
Explanation: This format is 2 bytes long.
25. The R/M field in a machine instruction format specifies
a) another register
b) another memory location
c) other operands
d) all of the mentioned
Answer: d
Explanation: The LSBs(least significant bits) from 0 to 3 represent R/M field that specifies another register or memory
location i.e. the other operand.
26. In a machine instruction format, S-bit is the
a) status bit
b) sign bit
c) sign extension bit
d) none of the mentioned
Answer: c
Explanation: The S-bit known as sign extension bit is used along with W-bit to show the type of operation.
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27. The bit which is used by the ‘REP’ instruction is
a) W-bit Rooma, Kanpur – 208 008
b) S-bit
c) V-bit
d) Z-bit
Answer: d
Explanation: The Z-bit is used by the REP instruction to control the loop.
28. If a W-bit value is ‘1’ then the operand is of
a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits
Answer: c
Explanation: If W-bit is ‘1’ then the operand is of 16-bits, and if it is ‘0’ then the operand is of 8-bits.
29. The instructions which after execution transfer control to the next instruction in the sequence are called
a) Sequential control flow instructions
b) control transfer instructions
c) Sequential control flow & control transfer instructions
d) none of the mentioned
Answer: a
Explanation: The sequential control flow instructions follow sequence order in their execution.
30. The instructions that transfer the control to some predefined address or the address specified in the instruction are
called as
a) sequential control flow instructions
b) control transfer instructions
c) sequential control flow & control transfer instructions
d) none of the mentioned
Answer: b
Explanation: The control transfer instructions transfer control to the specified address.
31. The instruction “JUMP” belongs to
a) sequential control flow instructions
b) control transfer instructions
c) branch instructions
d) control transfer & branch instructions
Answer: d
Explanation: The JUMP instruction transfers the control to the address located in the instruction.
32. The instruction, “INC” increases the contents of the specified register or memory location by
a) 2
b) 0
c) 1
d) 3
Answer: c
Explanation: This instruction adds 1 to the contents of the operand and so increments by 1.
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33. The instruction that subtracts 1 from the contents of the specified register/memory location is
a) INC Rooma, Kanpur – 208 008
b) SUBB
c) SUB
d) DEC
Answer: d
Explanation: The DEC instruction decrements the contents of a specified register/memory location by 1.
34. The instruction that enables subtraction with borrow is
a) DEC
b) SUB
c) SBB
d) None of the mentioned
Answer: c
Explanation: The SBB instruction subtracts the source operand and the borrow flag from the destination operand.
35. The flag that acts as Borrow flag in the instruction, SBB is
a) direction flag
b) carry flag
c) parity flag
d) trap flag
Answer: b
Explanation: If borrow exists in the subtraction operation performed then carry flag is set.
36. In general, the source operand of an instruction can be
a) memory location
b) register
c) immediate data
d) all of the mentioned
Answer: d
Explanation: The source operand is the element which is data or data stored memory location on which operation is
performed.
37. In general, the destination operand of an instruction can be
a) memory location
b) register
c) immediate data
d) memory location and register
Answer: d
Explanation: Since the destination should be able to store the data, immediate data cannot be considered as a
destination operand.
38. The instruction, CMP to compare source and destination operands it performs
a) addition
b) subtraction
c) division
d) multiplication
Answer: b
Explanation: For comparison, the instruction CMP subtracts source operand from destination operand.
39. During comparison operation, the result of comparing or subtraction is stored in
a) memory
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b) registers
c) stack Rooma, Kanpur – 208 008
d) no where
Answer: d
Explanation: The result of subtraction operation is not stored anywhere during a comparison.
40. The instruction that converts the result in an unpacked decimal digits is
a) AAA
b) AAS
c) AAM
d) All of the mentioned
Answer: d
Explanation: All the ASCII adjust instructions give result in unpacked decimal form and so are called as “Unpacked BCD
arithmetic instructions”.
41. Which of the following is a mnemonic?
a) ADD
b) ADC
c) AAA
d) ADD & ADC
Answer: c
Explanation: AAA is a mnemonic. It doesn’t have either a source or destination operand.
42. The instruction in which adjustment is made before performing the operation is
a) AAA
b) AAS
c) AAM
d) AAD
Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL.
This adjustment must be made before dividing the two unpacked BCD digits.
43. The expansion of DAA is
a) decimal adjust after addition
b) decimal adjust before addition
c) decimal adjust accumulator
d) decimal adjust auxiliary
Answer: c
Explanation: This instruction performs conversion operation.
44. The instruction that is used to convert the result of the addition of two packed BCD numbers to a valid BCD number
is
a) DAA
b) DAS
c) AAA
d) AAS
Answer: a
Explanation: In this conversion, the result has to be only in AL.
45. The ROR instruction rotates the contents of the destination operand to
a) left
b) right
Allenhouse Institute of Technology (UPTU Code : 505)
c) left and then right
d) right and then left Rooma, Kanpur – 208 008
Answer: b
Explanation: ROR stands for Rotate Right without carry. so, the instruction rotates right.
46. The mnemonic that is placed before the arithmetic operation is performed is
a) AAA
b) AAS
c) AAM
d) AAD
Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL.
47. The Carry flag is undefined after performing the operation
a) AAA
b) ADC
c) AAM
d) AAD
Answer: d
Explanation: Since the operation, AAD is performed before division operation is performed, the carry flag, auxiliary flag
and overflow flag are undefined.
48. The instruction that performs logical AND operation and the result of the operation is not available is
a) AAA
b) AND
c) TEST
d) XOR
Answer: c
Explanation: In the TEST instruction, the logical AND operation is performed and the result is not stored but flags are
affected.
49. In the RCL instruction, the contents of the destination operand undergo function as
a) carry flag is pushed into LSB & MSB is pushed into the carry flag
b) carry flag is pushed into MSB & LSB is pushed into the carry flag
c) auxiliary flag is pushed into LSB & MSB is pushed into the carry flag
d) parity flag is pushed into MSB & LSB is pushed into the carry flag
Answer: a
Explanation: In RCL(Rotate right through carry), for each operation, the carry flag is pushed into LSB and the MSB of the
operand is pushed into carry flag.
50. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX register becomes zero is
a) SCAS
b) REP
c) CMPS
d) STOS
Answer: b
Explanation: The instruction to which the REP is prefix, is executed repeatedly until CX register becomes zero. When CX
becomes zero, the execution proceeds to the next instruction in sequence.
51. Match the following
A) MOvSB/SW 1) loads AL/AX register by content of a string
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B) CMPS 2) moves a string of bytes stored in source to destination
Rooma, Kanpur – 208 008
C) SCAS 3) compares two strings of bytes or words whose length is stored in CX register
D) LODS 4) scans a string of bytes or words
a) A-3,B-4,C-2,D-1
b) A-2,B-1,C-4,D-3
c) A-2,B-3,C-1,D-4
d) A-2,B-3,C-4,D-1
Answer: d
Explanation: By using the string instructions, the operations on strings can be performed.
52. The instructions that are used to call a subroutine from the main program and return to the main program after
execution of called function are
a) CALL, JMP
b) JMP, IRET
c) CALL, RET
d) JMP, RET
Answer: c
Explanation: At each CALL instruction, the IP and CS of the next instruction are pushed onto the stack, before the
control is transferred to the procedure. At the end of the procedure, the RET instruction must be executed to retrieve
the stored contents of IP & CS registers from a stack.
53. The instruction that unconditionally transfers the control of execution to the specified address is
a) CALL
b) JMP
c) RET
d) IRET
Answer: b
Explanation: In this the control transfers to the address specified in the instruction and flags are not affected by this
instruction.
54. Which instruction cannot force the 8086 processor out of ‘halt’ state?
a) Interrupt request
b) Reset
c) Both interrupt request and reset
d) Hold
Answer: d
Explanation: Only an interrupt request or Reset will force the 8086 processor to come out of the ‘halt’ state.
55. NOP instruction introduces
a) Address
b) Delay
c) Memory location
d) None of the mentioned
Answer: b
Explanation: NOP is the No operation. It means that the processor performs no operation for the clock cycle and thus
there exists a delay.
56. Which of the following is not a machine controlled instruction?
a) HLT
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b) CLC
c) LOCK Rooma, Kanpur – 208 008
d) ESC
Answer: b
Explanation: Since CLC is a flag manipulation instruction where CLC stands for Clear Carry Flag.
57. The disadvantage of machine level programming is
a) time consuming
b) chances of error are more
c) debugging is difficult
d) all of the mentioned
Answer: d
Explanation: The machine level programming is complicated.
58. The coded object modules of the program to be assembled are present in
a) .ASM file
b) .OBJ file
c) .EXE file
d) .OBJECT file
Answer: b
Explanation: .OBJ file is created with same name as source file and extension .OBJ. It contains the coded object modules
of the program to be assembled.
59. The advantages of assembly level programming are
a) flexibility of programming is more
b) chances of error are less
c) debugging is easy
d) all of the mentioned
Answer: d
Explanation: The assembly level programming is more advantageous than the machine level programming.
60. The extension that is essential for every assembly level program is
a) .ASP
b) .ALP
c) .ASM
d) .PGM
Answer: c
Explanation: All the files should have the extension, .ASM.
61. The directory that is under work must have the files that are related to
a) Norton’s editor
b) Assembler
c) Linker
d) All of the mentioned
Answer: d
Explanation: Before starting the process of entering a small program on PC, ensure that all the files namely Norton’s
editor, assembler, linker and debugger are available in the same directory in which work is been done.
62. The listing file is identified by
a) source file name
b) extension .LSF
c) source file name and an extension .LSF
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d) source file name and an extension .LST
Answer: d Rooma, Kanpur – 208 008
Explanation: The listing file is automatically generated in the assembly process and is identified by the entered or
source file name and an extension .LST.
63. The extension file that is must for a file to be accepted by the LINK as a valid object file is
a) .OBJ file
b) .EXE file
c) .MASM file
d) DEBUG file
Answer: a
Explanation: The .OBJ extension is a must for a file to be accepted by the LINK as a valid object file.
64. The listing file contains
a) total offset map of a source file
b) offset address and labels
c) memory allotments for different labels
d) all of the mentioned
Answer: d
Explanation: The listing file contains total offset map of source file including labels, offset addresses, opcodes, memory
allotments for different directives and labels and relocation information.
65. DEBUG.COM facilitates the
a) debugging
b) trouble shooting
c) debugging and trouble shooting
d) debugging and assembling
Answer: c
Explanation: DEBUG.COM is a DOS utility that facilitates the debugging and trouble shooting.
66. DEBUG is able to troubleshoot only
a) .EXE files
b) .OBJ files
c) .EXE file and .OBJ file
d) .EXE flie and .LST file
Answer: a
Explanation: The DEBUG may be used either to debug a source program or to observe the results of execution of an
.EXE file.
Peripherals interfacing with 8086 and applications
Module 04
1. The stack pointer register contains
a) address of the stack segment
b) pointer address of the stack segment
c) offset of address of stack segment
d) data present in the stack segment
Answer: c
Explanation: The stack pointer register contains the offset of the address of the stack segment.
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2. The stack segment register contains
a) address of the stack segment Rooma, Kanpur – 208 008
b) base address of the stack segment
c) pointer address of the stack segment
d) data in the stack segment
Answer: b
Explanation: The stack segment register contains base address of the stack segment in the memory. The stack pointer
register (sP) and stack segment register (SS) together address the stack-top.
3. PUSH operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
Answer: a
Explanation: Each PUSH operation decrements the SP ( Stack Pointer) register.
4. POP operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
Answer: b
Explanation: Each POP operation increments the SP ( Stack Pointer) register.
5. The register or memory location that is pushed into the stack at the end must be
a) popped off last
b) pushed off first
c) popped off first
d) pushed off last
Answer: c
Explanation: The data can be retrieved by POP operation and as in stack, the data that is pushed at the end must be
popped off first.
6. In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK
the ASSUME directive directs to the assembler the
a) address of the stack segment
b) pointer address of the stack segment
c) name of the stack segment
d) name of the stack, code and data segments
Answer: d
Explanation: The directive ASSUME facilitates to name the segments with the desired name that is not a mnemonic or
keyword.
7. When a stack segment is initialised then
a) SS and SP are initialised
b) only SS is initialised
c) only SP is initialised
d) SS and SP need not be initialised
Answer: a
Explanation: Though the Stack segment is initialised, the SS and SP pointers must be initialised.
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8. The number of PUSH instructions and POP instructions in a subroutine must be
Rooma, Kanpur – 208 008
a) PUSH instructions must be greater than POP instructions
b) POP instructions must be greater than PUSH instructions
c) Both must be equal
d) Instructions may be any kind
Answer: c
Explanation: The number of PUSH instructions must be equal to the number of POP instructions.
9. 8086 does not support
a) Arithmetic operations
b) logical operations
c) BCD operations
d) Direct BCD packed multiplication
Answer: d
Explanation: The 8086 microprocessor does not support direct BCD packed operations.
10. For 8086 microprocessor, the stack segment may have a memory block of a maximum of
a) 32K bytes
b) 64K bytes
c) 16K bytes
d) NONE
Answer: b
Explanation: In 8086 microprocessor, the memory segments each have a memory of 64K bytes.
11. While CPU is executing a program, an interrupt exists then it
a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
Answer: c
Explanation: An interrupt function is to break the sequence of operation.
12. An interrupt breaks the execution of instructions and diverts its execution to
a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit
Answer: a
Explanation: An interrupt transfers the control to interrupt service routine (ISR). After executing ISR, the control is
transferred back again to the main program.
13. While executing the main program, if two or more interrupts occur, then the sequence of appearance of interrupts
is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt
Answer: d
Explanation: If an interrupt occurs while executing a program, and the processor is executing the interrupt, if one more
interrupt occurs again, then it is called a nested interrupt.
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14. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to handle them properly, it is
said to have Rooma, Kanpur – 208 008
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability
Answer: c
Explanation: The processor if handles more devices as interrupts then it has multiple interrupt processing ability.
15. NMI stands for
a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none of the mentioned
Answer: a
Explanation: NMI is the acronym for nonmaskable interrupt.
16. If any interrupt request given to an input pin cannot be disabled by any means then the input pin is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
d) none of the mentioned
Answer: b
Explanation: A nonmaskable interrupt input pin is one which means that any interrupt request at NMI (nonmaskable
interrupt) input cannot be masked or disabled by any means.
17. The INTR interrupt may be
a) maskable
b) nonmaskable
c) maskable and nonmaskable
d) none of the mentioned
Answer: a
Explanation: the INTR (interrupt request) is maskable or can be disabled.
18. The Programmable interrupt controller is required to
a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request
Answer: b
Explanation: If more than one interrupt request (INTR) occurs at a time, then an external chip called programmable
interrupt controller is required to handle them.
19. The INTR interrupt may be masked using the flag
a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag
Answer: c
Explanation: If a microprocessor wants to serve any interrupt then interrupt flag, IF=1. If interrupt flag, IF=0, then the
processor ignores the service.
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20. The interrupt for which the processor has the highest priority among all the external interrupts is
a) keyboard interrupt Rooma, Kanpur – 208 008
b) TRAP
c) NMI
d) INT
Answer: c
Explanation: The Non-Maskable Interrupt input pin has the highest priority among all the external interrupts.
21. The interrupt for which the processor has highest priority among all the internal interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
Answer: b
Explanation: TRAP is the internal interrupt that has highest priority among all the interrupts except the Divide By Zero
(Type 0) exception.
22. In case of string instructions, the NMI interrupt will be served only after
a) initialisation of string
b) execution of some part of the string
c) complete string is manipulated
d) the occurrence of the interrupt
Answer: c
Explanation: When NMI is activated, the current instruction being executed is completed and then NMI is served. In the
case of string instructions, it is served after the complete string is manipulated.
23. The NMI pin should remain high for atleast
a) 4 clock cycles
b) 3 clock cycles
c) 1 clock cycle
d) 2 clock cycles
Answer: d
Explanation: The NMI pin should remain high for atleast 2 clock cycles and need not be synchronized with the clock for
being sensed.
24. The INTR signal can be masked by resetting the
a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag
Answer: b
Explanation: The INTR signal can be masked by resetting the interrupt flag.
25. For the INTR signal, to be responded to in the next instruction cycle, it must go ________ in the last clock cycle of
the current instruction
a) high
b) low
c) high or low
d) unchanged
Answer: a
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Explanation: The INTR signal must go high in the clock cycle of the current instruction in order to respond in the next
instruction cycle. Rooma, Kanpur – 208 008
26. The status of the pending interrupts is checked at
a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle
Answer: d
Explanation: At the end of each instruction, the status of the pending interrupts is checked.
27. Once the processor responds to an INTR signal, the IF is automatically
a) set
b) reset
c) high
d) low
Answer: b
Explanation: The IF is automatically reset when the processor responds to an INTR signal. If the processor wants to
respond to any type of INTR signal further then, the IF should again be set.
28. If the pin LOCK (active low based) is low at the trailing edge of the first ALE pulse, then till the start of the next
machine cycle, the pin LOCK (active low) is
a) low
b) high
c) low or high
d) none of the mentioned
Answer: a
Explanation: The pin LOCK (active low) remains low till the start of the next machine cycle.
29. With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in it for
a) 0 clock cycle
b) 1 clock cycle
c) 2 clock cycles
d) 3 clock cycles
Answer: c
Explanation: The INTA (active low) goes low and remains low for two clock cycles before returning back to the high
state.
30. If a number of instructions are repeating through the main program, then to reduce the length of the program,
__________ is used.
a) procedure
b) subroutine
c) macro
d) none of the mentioned
Answer: c
Explanation: For a certain number of instructions that are repeated in the main program, when macro is defined then
the code of a program is reduced by placing the name of the macro at which the set of instructions are needed to be
repeated.
31. The process of assigning a label or macroname to the string is called
a) initialising macro
b) initialising string macro
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c) defining a string macro
d) defining a macro Rooma, Kanpur – 208 008
Answer: d
Explanation: The process of assigning a label to the string is called defining a macro.
32. A macro within a macro is called
a) macro-within-macro
b) nested macro
c) macro-in-macro
d) none of the mentioned
Answer: b
Explanation: A macro may be called from inside a macro. This type of macro is called nested macro.
33. A macro can be defined as
a) beginning of a program
b) end of a program
c) after initialisation of program
d) anywhere in a program
Answer: d
Explanation: A macro can be defined anywhere in a program.
34. A macro can be used as ________
a) in data segment
b) to represent directives
c) to represent statements
d) all of the mentioned
Answer: d
Explanation: A macro may be used in data segment and can also be used to represent statements and directives.
35. The end of a macro can be represented by the directive.
a) END
b) ENDS
c) ENDM
d) ENDD
Answer: c
Explanation: The ENDM directive marks the end of the instructions or statements sequence assigned with the macro
name.
36. Inserting the statements and instructions represented by macro, directly at the place of the macroname, in the
program, is known as
a) calling a macro
b) inserting a macro
c) initializing a macro
d) none of the mentioned
Answer: a
Explanation: Inserting the statements and instructions at the place of macroname, in the program, is known as calling a
macro.
37. The time required for execution of a macro is ________ that of the procedure.
a) greater than
b) less than
c) equal to
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d) none of the mentioned
Answer: b Rooma, Kanpur – 208 008
Explanation: The time required for execution of a macro is less than that of procedure as it does not contain CALL and
RET instructions as the procedures do.
38. Which of the following statements is incorrect?
a) complete code of instruction string is inserted at each place, wherever the macroname appears
b) macro requires less time of execution than that of procedure
c) macro uses stack memory
d) macroname can be anything except registers and mnemonics
Answer: c
Explanation: Macro does not require stack memory and hence has less time for execution.
39. The beginning of the macro can be represented as
a) START
b) BEGIN
c) MACRO
d) None of the mentioned
Answer: c
Explanation: The beginning of the macro is represented as macroname followed by the directive MACRO.
SYNTAX: macroname MACRO
EXAMPLE: STRINGS MACRO.
40. If ‘n’ denotes the number of clock cycles and ‘T’ denotes period of the clock at which the microprocessor is running,
then the duration of execution of loop once can be denoted by
a) n+T
b) n-T
c) n*T
d) n/T
Answer: c
Explanation: The duration of execution of the loop is the product of number of clock cycles and the period of the clock
cycle at which microprocessor is running.
41. The number of instructions actually executed by the microprocessor depends on the
a) stack
b) loop count
c) program counter
d) time duration
Answer: b
Explanation: As the microprocessor executes each instruction corresponding loop counter value decreases and the
microprocessor executes the instructions till the loop counter becomes zero.
42. In case of subroutines, the actual number of instructions executed by the processor depends on
a) loop count
b) length of interrupt service routine
c) length of procedure
d) none
Answer: c
Explanation: In case of subroutines or interrupt service routines, the number of instructions executed by the processor
depends on the length of procedure (or subroutine) or length of interrupt service routine along with the main calling
program.
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43. The step included in generating delays is
a) determining exact required delay Rooma, Kanpur – 208 008
b) selecting instructions for delay loop
c) finding period of clock frequency
d) all of the mentioned
Answer: d
Explanation: The delays can be generated step wise.
44. The Count, N can be defined as
a) required delay/duration for execution
b) duration of execution/required delay
c) required delay/number of clock cycles
d) required delay/period of clock frequency
Answer: a
Explanation: The count N can be defined as the required time delay by the duration for execution of the loop once.
Count, N = required delay (Td)/duration for execution of the loop once (n*T).
45. In the instruction set,
MOV CX, BA03H
WAIT: DEC CX
NOP
JNZ WAIT
RET
if the zeroth condition is satisfied then, for execution, the JNZ instruction takes
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
Answer: d
Explanation: The JNZ instruction takes only 4 clock cycles if the zeroth condition is satisfied.
46. In the instruction set,
MOV CX, BA03H
WAIT: DEC CX
NOP
JNZ WAIT
RET
if the zeroth condition is not satisfied, then the JNZ instruction takes
a) 2 clock cycles
b) 8 clock cycles
c) 16 clock cycles
d) 64 clock cycles
Answer: c
Explanation: The JNZ instruction takes 16 clock cycles if the zeroth condition is not satisfied.
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47. The maximum count value of 16-bit count register puts a limitation on
a) memory usage Rooma, Kanpur – 208 008
b) storage of address of registers
c) to generate clock pulse
d) to generate maximum delay
Answer: d
Explanation: The maximum count value of 16-bit count register is FFFFH. This may put the limitation on the maximum
delay that can be generated using the instructions.
48. When large delays are required, then to serve the purpose
a) one or more count registers can be used
b) one or more shift registers can be used
c) one or more pointer registers can be used
d) one or more index registers can be used
Answer: a
Explanation: One or more count registers can be used to serve large delays.
49. The device that enables the microprocessor to read data from the external devices is
a) printer
b) joystick
c) display
d) reader
Answer: b
Explanation: Since joystick is an input device, it reads data from the external devices.
50. The example of output device is
a) CRT display
b) 7-segment display
c) Printer
d) All of the mentioned
Answer: d
Explanation: The output device transfers data from the microprocessor to the external devices.
51. The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read
Answer: c
Explanation: The input activity is similar to read operation and the output activity is similar to write operation.
52. The operation, IOWR (active low) performs
a) write operation on input data
b) write operation on output data
c) read operation on input data
d) read operation on output data
Answer: b
Explanation: IOWR (active low) operation means writing data to an output device and not an input device.
53. The latch or IC 74LS373 acts as
a) good input port
b) bad input port
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c) good output port
d) bad output port Rooma, Kanpur – 208 008
Answer: c
Explanation: If the output port is to source large currents, the port lines must be buffered. So, the latch is used as it acts
as a good output port.
54. While performing read operation, one must take care that much current should not be
a) sourced from data lines
b) sinked from data lines
c) sourced or sinked from data lines
d) sinked from address lines
Answer: c
Explanation: More current should not be sourced or sinked from data lines while reading to avoid loading.
55. To avoid loading during read operation, the device used is
a) latch
b) flipflop
c) buffer
d) tristate buffer
Answer: d
Explanation: A tristate buffer is used as an input device to overcome loading.
56. The chip 74LS245 is
a) bidirectional buffer
b) 8-bit input port
c) one that has 8 buffers
d) all of the mentioned
Answer: d
Explanation: The chip 74LS245 is a bidirectional buffer that contains 8 buffers and may be used as an 8-bit input port.
But while using as an input device, only one direction is useful.
57. In 74LS245, if DIR is 1, then the direction is from
a) inputs to outputs
b) outputs to inputs
c) source to sink
d) sink to source
Answer: a
Explanation: If DIR is 1, then the direction is from A(inputs) to B(outputs).
58. In memory-mapped scheme, the devices are viewed as
a) distinct I/O devices
b) memory locations
c) only input devices
d) only output devices
Answer: b
Explanation: In memory-mapped scheme, the devices are viewed as memory locations and are addressed likewise.
59. Programmable peripheral input-output port is another name for
a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port
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Answer: b
Explanation: The parallel input-output port chip 8255 isRooma, Kanpur as
also known – 208 008
programmable peripheral input-output port.
60. Port C of 8255 can function independently as
a) input port
b) output port
c) either input or output ports
d) both input and output ports
Answer: c
Explanation: Port C can function independently either as input or as output ports.
61. All the functions of the ports of 8255 are achieved by programming the bits of an internal register called
a) data bus control
b) read logic control
c) control word register
d) none of the mentioned
Answer: c
Explanation: By programming the bits of control word register, the operations of the ports are specified.
62. The data bus buffer is controlled by
a) control word register
b) read/write control logic
c) data bus
d) none of the mentioned
Answer: b
Explanation: The data bus buffer is controlled by read/write control logic.
63. The input provided by the microprocessor to the read/write control logic is
a) RESET
b) A1
c) WR(ACTIVE LOW)
d) All of the mentioned
Answer: d
Explanation: RD(ACTIVE LOW), WR(ACTIVE LOW), A1, A0, RESET are the inputs provided by the microprocessor to the
read/write control logic of 8255.
64. The device that receives or transmits data upon the execution of input or output instructions by the microprocessor
is
a) control word register
b) read/write control logic
c) 3-state bidirectional buffer
d) none of the mentioned
Answer: c
Explanation: 3-state bidirectional buffer is used to receives or transmits data upon the execution of input or output
instructions by the microprocessor.
65. The port that is used for the generation of handshake lines in mode 1 or mode 2 is
a) port A
b) port B
c) port C Lower
d) port C Upper
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Answer: d
Explanation: Port C upper is used for the generation ofRooma, Kanpurlines
handshake – 208in008
mode 1 or mode 2.
66.. If A1=0, A0=1 then the input read cycle is performed from
a) port A to data bus
b) port B to data bus
c) port C to data bus
d) CWR to data bus
Answer: b
Explanation: If A1=0, A0=1 then the input read cycle is performed from port B to data bus.
67. The function, ‘data bus tristated’ is performed when
a) CS(active low) = 1
b) CS(active low) = 0
c) CS(active low) = 0, RD(active low) = 1, WR(active low) = 1
d) CS(active low) = 1 OR CS(active low) = 0, RD(active low) = 1, WR(active low) = 1
Answer: d
Explanation: The data bus is tristated when chip select pin=1 or chip select pin=0 and read and write signals are high i.e
1.
68. The pin that clears the control word register of 8255 when enabled is
a) CLEAR
b) SET
c) RESET
d) CLK
Answer: c
Explanation: If reset pin is enabled then the control word register is cleared.
69. In the I/O mode, the 8255 ports work as
a) reset pins
b) set pins
c) programmable I/O ports
d) only output ports
View Answer
Answer: c
Explanation: In the I/O mode, the 8255 ports work as programmable I/O ports.
70. In BSR mode, only port C can be used to
a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports
Answer: c
Explanation: In BSR (Bit Set-Reset) Mode, port C can be used to set and reset its individual port bits.
71. The feature of mode 0 is
a) any port can be used as input or output
b) output ports are latched
c) maximum of 4 ports are available
d) all of the mentioned
Answer: d
Explanation: In mode 0, any port can be used as input or output and output ports are latched.
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72. The strobed input/output mode is another name of
a) mode 0 Rooma, Kanpur – 208 008
b) mode 1
c) mode 2
d) none
Answer: b
Explanation: In this mode, the handshaking signals control the input or output action of the specified port.
73. If the value of the pin STB (Strobe Input) falls to low level, then
a) input port is loaded into input latches
b) input port is loaded into output latches
c) output port is loaded into input latches
d) output port is loaded into output latches
Answer: a
Explanation: If the value of the pin STB (Strobe Input) falls to low level, the input port is loaded into input latches.
74. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of
a) Control word register
b) CPU
c) Printer
d) Ports
Answer: c
Explanation: This signal indicates that the printer is selected.
75. The pulse width of the signal INIT at the receiving terminal must be more than
a) 10 microseconds
b) 20 microseconds
c) 40 microseconds
d) 50 microseconds
Answer: d
Explanation: The pulse width of the signal must be more than 50microseconds at the receiving terminal.
76. The level of the signal ERROR(active low) becomes ‘low’ when the printer is in
a) Paper end state
b) Offline state
c) Error state
d) All of the mentioned
Answer: d
Explanation: The level of the signal ERROR(active low) becomes ‘low’ when the printer is in the Paper end state, Offline
state and Error state.
77. The signals that are provided to maintain proper data flow and synchronization between the data transmitter and
receiver are
a) handshaking signals
b) control signals
c) input signals
d) none
Answer: a
Explanation: Handshaking signals maintain proper data flow and synchronization.
78. The feature of mode 2 of 8255 is
a) single 8-bit port is available
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b) both inputs and outputs are latched
c) port C is used for generating handshake signals Rooma, Kanpur – 208 008
d) all of the mentioned
Answer: d
Explanation: In mode 2 of 8255, a single 8-bit port is available i.e group A.
79. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: There are three counters that can be used as either counters or delay generators.
80. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
Answer: b
Explanation: The control word register can only be written and cannot be read.
81. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3
Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.
82. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low for
a) 1 clockcycle
b) 2 clockcycles
c) 3 clockcycles
d) 4 clockcycles
Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If the count N is reloaded and again the
output becomes high and remains so for (N-1) clock pulses.
83. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Answer: c
Explanation: When the count N loaded is even, then for half of the count, the output remains high and for the
remaining half it remains low. If the count loaded is odd, the first clock pulse decrements it by 1 resulting in an even
count value.
84. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
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c) counter 2
d) none Rooma, Kanpur – 208 008
Answer: b
Explanation: SC denotes select counter.
85. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.
86. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is BCD count.
87. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.
80. The control word register contents are used for
a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
89.. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7
Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these five, four pins were alloted fixed vector
addresses but the pin INTR was not alloted by vector address, rather an external device was supposed to hand over the
type of the interrupt to the microprocessor.
90. The register that stores all the interrupt requests in it in order to serve them one by one on a priority basis is
a) Interrupt Request Register
b) In-Service Register
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c) Priority resolver
d) Interrupt Mask Register Rooma, Kanpur – 208 008
Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request Register internally.
91. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request Register) at the direction of the Priority
Resolver.
92. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
Answer: d
Explanation: The interrupt control logic performs all the operations that are involved within the interrupts like
accepting and managing interrupt acknowledge signals, interrupts.
93. In a cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64 vectored interrupts can be provided.
94. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a buffer enable to control buffer
transreceivers. If it is not used in buffered mode, then the pin is used as input to designate whether the chip is used as a
master or a slave.
95. Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
Answer: d
Explanation: The initialization procedure involves
i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
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iv) slave mode address is set to 7
Rooma,
v) special mask mode is cleared and the status read is set Kanpur – 208 008
to IRR.
96. When non-specific EOI command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will automatically reset the highest ISR.
97. In the application where all the interrupting devices are of equal priority, the mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
Answer: a
Explanation: The automatic rotation is used in the applications where all the interrupting devices are of equal priority.
iii) choosing binary or BCD counters
iv) loading of the counter registers.
ADC, DAC interfacing with 8086 and its application
Module 05
1. The time taken by the ADC from the active edge of SOC(start of conversion) pulse till the active edge of EOC(end of
conversion) signal is called
a) edge time
b) conversion time
c) conversion delay
d) time delay
Answer: c
Explanation: Broadly speaking, the time taken by the converter to calculate the equivalent digital data output from the
moment of the start of conversion is called conversion delay.
2. The popular technique that is used in the integration of ADC chips is
a) successive approximation
b) dual slope integration
c) successive approximation and dual slope integration
d) none
Answer: c
Explanation: Successive approximation and dual slope integration are the most popular techniques that are used in the
integrated ADC chips.
3. The procedure of algorithm for interfacing ADC contain
a) ensuring stability of analog input
b) issuing start of conversion pulse to ADC
c) reading digital data output of ADC as equivalent digital output
d) all of the mentioned
Answer: d
Explanation: The general algorithm for interfacing ADC contains ensuring the stability of analog input, issuing start of
Allenhouse Institute of Technology (UPTU Code : 505)
conversion pulse to ADC, reading end of conversion signal to mark the end of a conversion process, reading digital data
output of ADC as equivalent digital output. Rooma, Kanpur – 208 008
4. Which is the ADC among the following?
a) AD 7523
b) 74373
c) 74245
d) ICL7109
Answer: d
Explanation: AD 7523 is a DAC(Digital to analog converter), 74373 is a latch, 74245 is transceiver and ICL7109 is an ADC.
5. The conversion delay in a successive approximation of an ADC 0808/0809 is
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 milliseconds
Answer: b
Explanation: The conversion delay is 100microseconds which is low as compared to other converters.
6. The number of inputs that can be connected at a time to an ADC that is integrated with successive approximation is
a) 4
b) 2
c) 8
d) 16
Answer: c
Explanation: As these converters internally have 3:8 analog multiplexer, at a time 8 different analog inputs can be
connected to the chip.
7. ADC 7109 integrated by Dual slope integration technique is used for
a) low cost option
b) slow practical applications
c) low complexity
d) all of the mentioned
Answer: d
Explanation: Compared to other 12-bit ADCs, it is of very low cost and useful for slow practical applications.
8. Which of the following is not one of the phases of the total conversion cycle?
a) autozero phase
b) conversion phase
c) signal integrate phase
d) disintegrate phase
Answer: b
Explanation: Autozero phase, signal integrate phase and disintegrate phase are the three phases of total conversion
cycle.
9. Which of the following phase contain feedback loop in it?
a) autozero phase
b) signal integrate phase
c) disintegrate phase
d) none
Answer: a
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Explanation: A feedback loop is closed around the system to charge the autozero capacitor to compensate for the offset
Rooma, Kanpur – 208 008
voltages in the buffer amplifier, integrator and comparator.
10. In the signal integrate phase, the differential input voltage between IN LO(input low) and IN HI(input high) pins is
integrated by the internal integrator for a fixed period of
a) 256 clock cycles
b) 1024 clock cycles
c) 2048 clock cycles
d) 4096 clock cycles
Answer: c
Explanation: The internal integrator needs 2048 clock cycles to integrate voltage difference between input low and
input high.
11. Programmable peripheral input-output port is other name for
a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port
Answer: b
Explanation: The parallel input-output port chip 8255 is also known as programmable peripheral
input-output port.
12. Port C of 8255 can function independently as
a) input port
b) output port
c) either input or output ports
d) both input and output ports
Answer: c
Explanation: Port C can function independently either as input or as output ports.
13. All the functions of the ports of 8255 are achieved by programming the bits of an internal
register called
a) data bus control
b) read logic control
c) control word register
d) none
Answer: c
Explanation: By programming the bits of control word register, the operations of the ports are
specified.
14. The data bus buffer is controlled by
a) control word register
b) read/write control logic
c) data bus
d) none
Answer: b
Explanation: The data bus buffer is controlled by read/write control logic.
15. The input provided by the microprocessor to the read/write control logic is
a) RESET
b) A1
c) WR(ACTIVE LOW)
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d) all of the mentioned
Answer: d Rooma, Kanpur – 208 008
Explanation: RD(ACTIVE LOW), WR(ACTIVE LOW), A1, A0, RESET are the inputs
provided by the microprocessor to the read/write control logic of 8255.
16. The device that receives or transmits data upon the execution of input or output instructions by the microprocessor
is
a) control word register
b) read/write control logic
c) 3-state bidirectional buffer
d) none
Answer: c
Explanation: 3-state bidirectional buffer is used to receives or transmits data upon the execution
of input or output instructions by the microprocessor.
17. The port that is used for the generation of handshake lines in mode 1 or mode 2 is
a) port A
b) port B
c) port C Lower
d) port C Upper
Answer: d
Explanation: Port C upper is used for the generation of handshake lines in mode 1 or mode 2.
18. If A1=0, A0=1 then the input read cycle is performed from
a) port A to data bus
b) port B to data bus
c) port C to data bus
d) CWR to data bus
Answer: b
Explanation: If A1=0, A0=1 then the input read cycle is performed from port B to data bus.
19. The function, „data bus tristated‟ is performed when
a) CS(active low) =1
b) CS(active low) =0
c) CS(active low) =0, RD(active low) =1, WR(active low) =1
d) CS(active low) =1 OR CS(active low) =0, RD(active low) =1, WR(active low) =1
Answer: d
Explanation: the data bus is tristated when chip select pin=1 or chip select pin=0 and read and
write signals are high i.e 1.
20. The pin that clears the control word register of 8255 when enabled is
a) CLEAR
b) SET
c) RESET
d) CLK
Answer: c
Explanation: If reset pin is enabled then the control word register is cleared.
21. The device that enables the microprocessor to read data from the external devices is
a) printer
b) joystick
c) display
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d) reader
Answer: b Rooma, Kanpur – 208 008
Explanation: Since joystick is an input device, it reads data from the external devices.
22. The example of output device is
a) CRT display
b) 7-segment display
c) printer
d) all of the mentioned
Answer: d
Explanation: The output device transfers data from microprocessor to the external devices.
23. The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read
Answer: c
Explanation: The input activity is similar to read operation and the output activity is similar to
write operation.
24. The operation, IOWR (active low) performs
a) write operation on input data
b) write operation on output data
c) read operation on input data
d) read operation on output data
Answer: b
Explanation: IOWR (active low) operation means writing data to an output device and not an
input device.
25. The latch or IC 74LS373 acts as
a) good input port
b) bad input port
c) good output port
d) bad output port
Answer: c
Explanation: If the output port is to source large currents, the port lines must be buffered. So, the
latch is used as it acts as good output port.
26. While performing read operation, one must take care that much current should not be
a) sourced from data lines
b) sinked from data lines
c) sourced or sinked from data lines
d) sinked from address lines
Answer: c
Explanation: More current should not be sourced or sinked from data lines while reading to
avoid loading.
27. To avoid loading during read operation, the device used is
a) latch
b) flipflop
c) buffer
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d) tristate buffer
Answer: d Rooma, Kanpur – 208 008
Explanation: A tristate buffer is used as an input device to overcome loading.
28. The chip 74LS245 is
a) bidirectional buffer
b) 8-bit input port
c) one that has 8 buffers
d) all of the mentioned
Answer: d
Explanation: The chip 74LS245 is a bidirectional buffer that contains 8 buffers and may be used
as an 8-bit input port. But while using as an input device, only one direction is useful.
29. In 74LS245, if DIR is 1, then the direction is from
a) inputs to outputs
b) outputs to inputs
c) source to sink
d) sink to source
Answer: a
Explanation: If DIR is 1, then the direction is from A(inputs) to B(outputs).
30. In memory-mapped scheme, the devices are viewed as
a) distinct I/O devices
b) memory locations
c) only input devices
d) only output devices
Answer: b
Explanation: In memory-mapped scheme, the devices are viewed as memory locations and are
addressed likewise.
31. In the I/O mode, the 8255 ports work as
a) reset pins
b) set pins
c) programmable I/O ports
d) only output ports
Answer: c
Explanation: In the I/O mode, the 8255 ports work as programmable I/O ports.
32. In BSR mode, only port C can be used to
a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports
Answer: c
Explanation: In BSR (Bit Set-Reset) Mode, port C can be used to set and reset its individual port
bits.
33. The feature of mode 0 is
a) any port can be used as input or output
b) output ports are latched
c) maximum of 4 ports are available
d) all of the mentioned
Allenhouse Institute of Technology (UPTU Code : 505)
Answer: d
Rooma,
Explanation: In mode 0, any port can be used as input or Kanpur
output and–output
208 008ports are latched.
34. The strobed input/output mode is another name of
a) mode 0
b) mode 1
c) mode 2
d) none
Answer: b
Explanation: In this mode, the handshaking signals control the input or output action of the
specified port.
35. If the value of the pin STB (Strobe Input) falls to low level, then
a) input port is loaded into input latches
b) input port is loaded into output latches
c) output port is loaded into input latches
d) output port is loaded into output latches
Answer: a
Explanation: If the value of the pin STB (Strobe Input) falls to low level, then input port is
loaded into input latches.
36. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of
a) control word register
b) CPU
c) Printer
d) ports
Answer: c
Explanation: This signal indicates that the printer is selected.
37. The pulse width of the signal INIT at the receiving terminal must be more than
a) 10 microseconds
b) 20 microseconds
c) 40 microseconds
d) 50 microseconds
Answer: d
Explanation: The pulse width of the signal must be more than 50microseconds at the receiving
terminal.
38. The level of the signal ERROR(active low) becomes „low‟ when the printer is in
a) Paper end state
b) Offline state
c) Error state
d) all of the mentioned
Answer: d
Explanation: The level of the signal ERROR(active low) becomes „low‟ when the printer is in
Paper end state, Offline state and Error state.
39. The signals that are provided to maintain proper data flow and synchronisation between the
data transmitter and receiver are
a) handshaking signals
b) control signals
c) input signals
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d) none
Answer: a Rooma, Kanpur – 208 008
Explanation: Handshaking signals maintain proper data flow and synchronisation.
40. The feature of mode 2 of 8255 is
a) single 8-bit port is available
b) both inputs and outputs are latched
c) port C is used for generating handshake signals
d) all of the mentioned
Answer: d
Explanation: In mode 2 of 8255, single 8-bit port is available i.e group A.
ADC
41. The time taken by the ADC from the active edge of SOC(start of conversion) pulse till the
active edge of EOC(end of conversion) signal is called
a) edge time
b) conversion time
c) conversion delay
d) time delay
Answer: c
Explanation: Broadly speaking, the time taken by the converter to calculate the equivalent digital
data output from the moment of the start of conversion is called conversion delay.
42. The popular technique that is used in the integration of ADC chips is
a) successive approximation
b) dual slope integration
c) successive approximation and dual slope integration
d) none
Answer: c
Explanation: Successive approximation and dual slope integration are the most popular
techniques that are used in the integrated ADC chips.
43. The procedure of algorithm for interfacing ADC contain
a) ensuring stability of analog input
b) issuing start of conversion pulse to ADC
c) reading digital data output of ADC as equivalent digital output
d) all of the mentioned
Answer: d
Explanation: The general algorithm for interfacing ADC contains ensuring stability of analog
input, issuing start of conversion pulse to ADC, reading end of conversion signal to mark the end
of conversion process, reading digital data output of ADC as equivalent digital output.
44. Which is the ADC among the following?
a) AD 7523
b) 74373
c) 74245
d) ICL7109
Answer: d
Explanation: AD 7523 is a DAC(Digital to analog converter), 74373 is a latch, 74245 is
transreceiver and ICL7109 is an ADC.
Allenhouse Institute of Technology (UPTU Code : 505)
45. The conversion delay in successive approximation of an ADC 0808/0809 is
a) 100 milliseconds Rooma, Kanpur – 208 008
b) 100 microseconds
c) 50 milliseconds
d) 50 milliseconds
Answer: b
Explanation: The conversion delay is 100microseconds which is low as compared to other
converters.
46. The number of inputs that can be connected at a time to an ADC that is integrated with
successive approximation is
a) 4
b) 2
c) 8
d) 16
Answer: c
Explanation: As these converters internally have 3:8 analog multiplexer, at a time 8 different
analog inputs can be connected to the chip.
47. ADC 7109 integrated by Dual slope integration technique is used for
a) low cost option
b) slow practical applications
c) low complexity
d) all of the mentioned
Answer: d
Explanation: Compared to other 12-bit ADCs, it is of very low cost and useful for slow practical
applications.
48. Which of the following is not one of the phase of total conversion cycle?
a) autozero phase
b) conversion phase
c) signal integrate phase
d) deintegrate phase
Answer: b
Explanation: autozero phase, signal integrate phase and deintegrate phase are the three phases of
total conversion cycle.
49. Which of the following phase contain feedback loop in it?
a) autozero phase
b) signal integrate phase
c) deintegrate phase
d) none
Answer: a
Explanation: A feedback loop is closed around the system to charge the autozero capacitor to
compensate for the offset voltages in the buffer amplifier, integrator and comparator.
50. In the signal integrate phase, the differential input voltage between IN LO(input low) and IN
HI(input high) pins is integrated by the internal integrator for a fixed period of
a) 256 clock cycles
b) 1024 clock cycles
c) 2048 clock cycles
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d) 4096 clock cycles
Answer: c Rooma, Kanpur – 208 008
Explanation: The internal integrator needs 2048 clock cycles to integrate voltage difference
between input low and input high.
51. DAC (Digital to Analog Converter) finds application in
a) digitally controlled gains
b) motor speed controls
c) programmable gain amplifiers
d) all of the mentioned
Answer: d
Explanation: DAC is used in digitally controlled gains, motor speed controls and programmable
gain amplifiers.
52. To save the DAC from negative transients the device connected between OUT1 and OUT2 of
AD 7523 is
a) p-n junction diode
b) Zener
c) FET
d) BJT (Bipolar Junction transistor)
Answer: b
Explanation: Zener is connected between OUT1 and OUT2 pins of AD7523 to save from
negative transients.
53. An operational amplifier connected to the output of AD 7523 is used
a) to convert current output to output voltage
b) to provide additional driving capability
c) as current-to-voltage converter
d) all of the mentioned
Answer: d
Explanation: An operational amplifier is used as a current-to-voltage converter to convert current
output to output voltage and also provides additional driving capability to the DAC.
54. The DAC 0800 has a settling time of
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 microseconds
Answer: a
Explanation: DAC 0800 has a settling time of 100 milliseconds.
55. The device that is used to obtain an accurate position control of rotating shafts in terms of
steps is
a) DC motor
b) AC motor
c) Stepper motor
d) Servo motor
Answer: c
Explanation: Stepper motor employs rotation of its shaft in terms of steps, rather than continuous
rotation as in case of AC or DC motors.
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56. The internal schematic of a typical stepper motor has
a) 1 winding Rooma, Kanpur – 208 008
b) 2 windings
c) 3 windings
d) 4 windings
Answer: d
Explanation: the internal schematic of a typical stepper motor has 4 windings.
57. The number of pulses required for one complete rotation of the shaft of the stepper motor is
equal to the
a) number of internal teeth on a rotor
b) number of internal teeth on a stator
c) number of internal teeth on a rotor and stator
d) number of external teeth on a stator
Answer: a
Explanation: The number of pulses required for one complete rotation of the shaft of the stepper
motor is equal to the number of internal teeth on its rotor.
58. A simple scheme for rotating the shaft of a stepper motor is called
a) rotating scheme
b) shaft scheme
c) wave scheme
d) none
Answer: c
Explanation: In this scheme, the windings are applied with the required voltage pulses, in a
cyclic fashion.
59. The firing angles of thyristors are controlled by
a) pulse generating circuits
b) relaxation oscillators
c) microprocessor
d) all of the mentioned
Answer: d
Explanation: In early days, the firing angles were controlled by pulse generating circuits like
relaxation oscillators and now, they are accurately fired using a microprocessor.
60. The Isolation transformers are generally used for
a) protecting low power circuit
b) isolation
c) protecting low power circuit and isolation
d) none
Answer: c
Explanation: Any switching component of a high power circuit may be sufficient to damage the
microprocessor system. So, to protect the low power circuit isolation transformers are used. They
are also used if isolation is necessary.
61. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
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Answer: c
Explanation: There are three counters that can be usedRooma, Kanpur
as either – 208 008
counters or delay generators.
62. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
Answer: b
Explanation: The control word register can only be written and cannot be read.
63. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3
Answer: a
Explanation: Mode 0 is also called as interrupt on terminal count.
64. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low
for
a) 1 clockcycle
b) 2 clockcycles
c) 3 clockcycles
d) 4 clockcycles
Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If the count N is
reloaded and again the output becomes high and remains so for (N-1) clock pulses.
65. The generation of square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Answer: c
Explanation: When the count N loaded is even, then for half of the count, the output remains
high and for the remaining half it remains low. If the count loaded is odd, the first clock pulse
decrements it by 1 resulting in an even count value.
66. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
Answer: b
Explanation: SC denotes select counter.
67. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
Allenhouse Institute of Technology (UPTU Code : 505)
Answer: c
Rooma,
Explanation: To access 16 bit, first LSB is loaded first, and thenKanpur
MSB. – 208 008
68. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is BCD count.
69. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.
70. The control word register contents are used for
a) initialising the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Answer: d
Explanation: The control word register contents are used for
i) initialising the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.
71. The registers that store the keyboard and display modes and operations programmed by CPU
are
a) I/O control and data buffers
b) control and timing registers
c) return buffers
d) display address registers
Answer: b
Explanation: The control and timing registers store the keyboard and display modes and other
operations programmed by CPU.
72. The sensor RAM acts as 8-byte first-in-first-out RAM in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
Answer: c
Explanation: In this mode, each key code of the pressed key is entered in the order of the entry,
and in the meantime, read by the CPU, till the RAM becomes empty.
73. The registers that holds the address of the word currently being written by the CPU from the
display RAM are
Allenhouse Institute of Technology (UPTU Code : 505)
a) control and timing register
b) control and timing register and timing control Rooma, Kanpur – 208 008
c) display RAM
d) display address registers
Answer: d
Explanation: The display address registers holds the address of the word currently being written
or read by the CPU to or from the display RAM.
74. When a key is pressed, a debounce logic comes into operation in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Answer: c
Explanation: In scanned keyboard mode with 2 key lockout mode of operation, when a key is
pressed, a debounce logic comes into operation. During the next two scans, other keys are
checked for closure and if no other key is pressed then the first pressed key is identified.
75. The mode that is programmed using “end interrupt/error mode set command” is
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Answer: a
Explanation: The scanned keyboard special error mode is programmed using end interrupt/error
mode set command. This mode is valid only under the N-key rollover mode.
76. When a key is pressed, the debounce circuit waits for 2 keyboard scans and then checks
whether the key is still depressed in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Answer: b
Explanation: In this mode, When a key is pressed, the debounce circuit waits for 2 keyboard
scans and then checks whether the key is still depressed. If it is still depressed, the code is
entered in FIFO RAM.
77. The data that is entered from the left side of the display unit is of
a) left entry mode
b) right entry mode
c) left and right entry modes
d) none
Answer: a
Explanation: The data that is entered from the left side of the display unit is of left entry mode, as
in a type-writer the first character typed appears at the left-most position, while the subsequent
characters appear successively to the right of the first one.
78. The FIFO status word is used to indicate the error in
a) keyboard mode
b) strobed input mode
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c) keyboard and strobed input mode
d) scanned sensor matrix mode Rooma, Kanpur – 208 008
Answer: c
Explanation: Overrun error occurs, when an already full FIFO is attempted an entry. Underrun
error occurs when an empty FIFO read is attempted.
79. The flag that increments automatically after each read or write operation to the display RAM is
a) IF
b) RF
c) AI
d) WF
Answer: c
Explanation: AI refers to auto increment flag.
80. If any change in sensor value is detected at the end of a sensor matrix scan, then the IRQ line
a) goes low
b) goes high
c) remains unchanged
d) none
Answer: b
Explanation: In sensor matrix mode, the IRQ line goes high, if any change in sensor value is
detected at the end of a sensor matrix scan or the sensor RAM has a previous entry to be read by
the CPU.
81. A/D converter is used for __________
a) converting analog to digital
b) converting digital to analog
c) converting digital to mixed signal mode
d) converting analog to mixed signal mode
Answer: a
Explanation: In a digital data acquisition system, an A/D converter is used for the purpose of converting analog signals
to digital.
82. Output of A/D converter is _________
a) given to an analog display
b) given to a digital display
c) given to a CRO
d) given to a voltmeter
Answer: b
Explanation: Output from the analog to digital converter is given to a digital display device or to a digital recorder for
the purpose of displaying or recording.
83. What are auxiliary equipments?
a) equipment
b) guard rings
c) devices
d) voltage source
Answer: c
Explanation: Auxiliary equipments are basically devices used for system programming functions and digital data
processing applications.
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84. What is the main function of auxiliary equipment?
a) unit step response Rooma, Kanpur – 208 008
b) ramp response
c) non-linear response
d) linear response
Answer: d
Explanation: The typical functions of auxiliary equipments include linearization and limit compression for the input
signals. Individual instruments or a digital computer is used to perform these functions.
85. What is a digital recorder?
a) records digital data
b) records analog data
c) does not record data
d) records both analog and digital data
Answer: a
Explanation: A digital recorder is used for the purpose of recording the digital data. Punched cards, magnetic tape
recorders, type written pages, etc make use of digital recorders.
86. Data acquisition systems are not widely used.
a) True
b) False
Answer: b
Explanation: In digital recorders, data acquisition systems are used widely in industries, space applications, medical and
telephony.
87. For lower accuracies _________
a) digital acquisition system is used
b) both digital and analog acquisition systems are used
c) analog acquisition system is used
d) mechanical data acquisition system is used
Answer: c
Explanation: When low values of accuracy is required, analog data acquisition system is used. This includes a wide
frequency bandwidth as well.
88. Digital acquisition systems are used when _________
a) bandwidth is high
b) bandwidth is medium
c) bandwidth is zero
d) bandwidth is low
Answer: d
Explanation: When the bandwidth required is low, usually digital acquisition systems are made use of. For higher
accuracy and lower per channel cost, digital data acquisition systems are used.
8086 Microprocessor interfacing
Module 06
1. The unit that executes all the numeric processor instructions in 8087 is
a) Control unit
b) ALU
c) Numeric extension unit
d) None of the mentioned
Allenhouse Institute of Technology (UPTU Code : 505)
Answer: c
Rooma,
Explanation: The 8087 is divided into two sections namely Kanpur
control – 208
unit and008
numeric extension unit in which the numeric
extension unit executes all the numeric processor instructions.
2. The unit that receives and decodes the instructions in 8087 is
a) Control unit
b) ALU
c) Numeric extension unit
d) None of the mentioned
Answer: a
Explanation: The control unit receives, decodes the instructions, and executes the 8087 control instructions.
3. The control unit functions in
a) establishing communication between CPU and memory
b) coordinating the internal coprocessor execution
c) reads and writes memory operands
d) all of the mentioned
Answer: d
Explanation: The control unit is used for establishing communication between CPU and memory and coordinating the
internal coprocessor execution.
4. When the numeric extension unit (NEU) begins its execution, then the signal that is active is
a) BUSY (active high)
b) BUSY (active low)
c) READY (active low)
d) RESET (active high)
Answer: a
Explanation: When NEU begins its execution, the BUSY signal is pulled up. Also, this output signal when high, indicates
to the CPU that it is busy with the execution of an allotted instruction.
5. The register that allows the register programmer to select the required processing options is
a) significant
b) exponent
c) control word register
d) none of the mentioned
Answer: c
Explanation: The control word register allows the register programmer to select the required processing options out of
available ones. It is used to control the operation of 8087.
6. Invalid operation is the exception generated due to
a) stack overflow
b) stack underflow
c) indeterminate form as result
d) all of the mentioned
Answer: d
Explanation: Invalid operation is generated due to stack overflow, stack underflow, indeterminate form as result, or
non-number (NAN) as operand.
7. The exception generated for a too big result to fit in the format is
a) invalid operation
b) overflow
c) denormalized operand
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d) result overflow
Answer: b Rooma, Kanpur – 208 008
Explanation: A too big result to fit in the format generates this exception. The condition code bits indicate that the
result is prohibitively large.
8. If the result is infinity, then the exception generated is
a) overflow
b) invalid operation
c) denormalized operand
d) zero divide
Answer: d
Explanation: If any non-zero finite operand is divided by zero, the zero divide exception is generated. The resulting
condition code bits indicate that the result is infinity, even if the exception is masked.
9. To operate 8087 in maximum mode, the pin MN/MX (active low) is
a) connected to Vcc or power supply
b) connected to ground
c) left unconnected
d) none of the mentioned
Answer: b
Explanation: The 8087 can operate in a maximum mode, only when the MN/MX (active low) pin of the CPU is
grounded. In maximum mode, all the control signals are derived using a sequence chip known as a bus controller.
10. If the result is rounded according to the rounding control bits, then the exception generated is
a) denormalized operand
b) underflow
c) inexact result
d) invalid operation
Answer: c
Explanation: If it is impossible to fit the actual result in the specified format, the result is rounded according to the
rounding control bits, and an exception is generated. This sets the precision exception flag.
11. The instruction that stores a copy of top of the stack into the memory, and pops the top of the stack is
a) FST
b) FSTP
c) FIST
d) FLD
Answer: b
Explanation: FSTP (store floating point number and pop) stores a copy of top of the stack into memory or any
coprocessor register, and then pops the top of the stack.
12. The instruction that multiplies the content of the stack top by 2n is
a) FMUL
b) FPREM
c) FSCAL
d) FCSH
Answer: c
Explanation: FSCAL instruction multiplies the content of the stack top by 2n, where n is an integral part of stack and
stores the result in stack.
13. If the opcode bit is D=1, then the source and destination operands are
a) incremented
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b) decremented
c) cleared Rooma, Kanpur – 208 008
d) interchanged
Answer: d
Explanation: If D=1, then it interchanges the source and destination operands.
14. Which of the following is not a block of an architecture of 80287?
a) bus control logic
b) data interface and control unit
c) floating point unit
d) none of the mentioned
Answer: d
Explanation: The three blocks of an internal architecture of 80287 are:
1. bus control logic
2. data interface and control unit
3. floating point unit.
15. The unit that provides and controls the interface, between the internal 80287 bus and 80286 bus via data buffer is
a) bus control logic
b) data interface and control unit
c) floating point unit
d) none of the mentioned
Answer: a
Explanation: The bus control logic provides and controls the interface, between the internal 80287 bus and 80286 bus
via data buffer.
16. The data interface and control unit consists of
a) status and control words
b) tag words and error pointers
c) instruction decoders
d) all of the mentioned
Answer: d
Explanation: The data interface and control unit contains status and controls words, TAG words and error pointers.
17. The word that optimizes the NDP performance, by maintaining a record of empty and non-empty register locations
is
a) Status and control words
b) TAG words
c) Error pointers
d) All of the mentioned
Answer: b
Explanation: The TAG word optimizes the NDP performance by maintaining a record of empty and non-empty register
locations. It helps the exception handler to identify special values in the contents of the stack locations.
18. The part of the data interface and control unit, that points to the source of exception generated is
a) Status and control words
b) TAG words
c) Error pointers
d) None of the mentioned
Answer: c
Allenhouse Institute of Technology (UPTU Code : 505)
Explanation: The error pointers point to the source of exception (address of the instruction that generated the
exception) generated. Rooma, Kanpur – 208 008
19. The data bus in a floating point unit is of
a) 16 bits
b) 32 bits
c) 64 bits
d) 84 bits
Answer: d
Explanation: The data bus in a floating point unit is of 84-bits. Out of this 84-bits, the lower 68 bits are significant
(mantissa) data bit, the next 16 bits are used for the exponent.
20. The arrangement of data that is to be shifted successively, whenever required for the execution, is done by
a) error pointer
b) data buffer
c) barrel shifter
d) none of the mentioned
Answer: c
Explanation: The barrel shifter arranges and presents the data to be shifted successively, whenever required for the
execution.
21. The word that is used to select one of the processing options, among the provided ones is
a) status word
b) control word
c) status and control words
d) none of the mentioned
Answer: b
Explanation: The control word is used to select one of the processing options, among the ones provided by 80287.
22. After reset of 80287, the control bit that is initialized to zero is
a) masking bits
b) precision control bits
c) rounding control bits
d) infinity control bits
Answer: d
Explanation: The infinity control bit is initialized to zero after reset.
23. The bits that are modified depending upon the result of the execution of arithmetic instructions are
a) masking bits
b) rounding control bits
c) condition code bits
d) error summary bits
Answer: c
Explanation: The condition code bits are similar to the flags of a CPU. These are modified depending upon the result of
the execution of arithmetic instructions.
24. If the stack flag is set, and condition code bit C1=1, then the stack is
a) full
b) overflown
c) underflown
d) empty
Allenhouse Institute of Technology (UPTU Code : 505)
Answer: b
Explanation: If the stack flag is set, and condition codeRooma, Kanpur
bit C1=1, then– the
208 008
stack has overflown.
25. If the stack flag is set, and condition code bit C1=0, then the stack is
a) full
b) overflown
c) underflown
d) empty
Answer: c
Explanation: If the stack flag is set, and condition code bit C1=0, then the stack has underflown.
26. The bits that affect the result of arithmetic operations like ADD, SUB, MUL, DIV are
a) condition code bits
b) rounding control bits
c) masking bits
d) precision control bits
Answer: d
Explanation: The precision control bits affect ADD, SUB, MUL, DIV and SQRT results.
27. The precision is decided by the
a) opcode
b) extended precision format
c) opcode or extended precision format
d) none of the mentioned
Answer: c
Explanation: For other than the arithmetic instructions (like ADD, SUB, MUL, DIV and SQRT), the precision is decided by
opcode or extended precision format.
28. If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
Answer: c
Explanation: If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables a data transfer from
80286 to 80287.
29. If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
Answer: b
Explanation: If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables a data transfer from
80287 to 80286.
30. Which of the input line(s) indicate that the CPU is performing an escape operation, and enables 80287 to execute
the next instruction?
a) NPWR (active low) and NPRD (active low)
b) NPS1 and NPS2 (active low)
c) NPS1 (active low) and NPS2
d) CMD0 and CMD1
Allenhouse Institute of Technology (UPTU Code : 505)
Answer: c
Explanation: The Numeric Processor select input lines, Rooma, Kanpur low)
NPS1 (active – 208and
008 NPS2, indicate that the CPU is performing
an escape operation, and enables 80287 to execute the next instruction.
31. For which pin of 80286 is the active low pin, BUSY of 80287, connected?
a) ERROR (active low)
b) BUSY (active low)
c) HLDA
d) TEST (active low)
Answer: d
Explanation: The BUSY (active low) is connected to the TEST (active low) pin of 80286.
32. If Clock Mode (CM) input pin is held low, then the CLK input is divided by
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: If Clock Mode (CM) input pin is held high, then the CLK input is directly used for deriving the internal
timings. Else, it is divided by 2.
33. Which of the following pin is not involved in the interface of 80287 with 80286?
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answer: c
Explanation: The 10 pins, PEREQ, PEACK#, BUSY#, ERROR#, NPRD(active low)#, NPWR(active low)#, NPS1(active low)#,
NPS2#, CMD0 and CMD1.
34. The PEACK (active low) when activated, the pin that goes into deactivation is
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answer: a
Explanation: When the data transfer is over, the CPU activates PEACK (active low)# pin, which results in deactivating the
PEREQ pin by 80287.
35. If the stack flag is set, and condition code bit C1=1, then the stack is
a) full
b) overflown
c) underflown
d) empty
Answer: b
Explanation: If the stack flag is set, and condition code bit C1=1, then the stack has overflown.
36. If the stack flag is set, and condition code bit C1=0, then the stack is
a) full
b) overflown
c) underflown
d) empty
Allenhouse Institute of Technology (UPTU Code : 505)
Answer: c
Explanation: If the stack flag is set, and condition codeRooma, Kanpur
bit C1=0, then– the
208 008
stack has underflown.
37. The bits that affect the result of arithmetic operations like ADD, SUB, MUL, DIV are
a) condition code bits
b) rounding control bits
c) masking bits
d) precision control bits
Answer: d
Explanation: The precision control bits affect ADD, SUB, MUL, DIV and SQRT results.
38. The precision is decided by the
a) opcode
b) extended precision format
c) opcode or extended precision format
d) none of the mentioned
Answer: c
Explanation: For other than the arithmetic instructions (like ADD, SUB, MUL, DIV and SQRT), the precision is decided by
opcode or extended precision format.
39. If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
Answer: c
Explanation: If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables a data transfer from
80286 to 80287.
40. If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
Answer: b
Explanation: If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables a data transfer from
80287 to 80286.
41. Which of the input line(s) indicate that the CPU is performing an escape operation, and enables 80287 to execute
the next instruction?
a) NPWR (active low) and NPRD (active low)
b) NPS1 and NPS2 (active low)
c) NPS1 (active low) and NPS2
d) CMD0 and CMD1
Answer: c
Explanation: The Numeric Processor select input lines, NPS1 (active low) and NPS2, indicate that the CPU is performing
an escape operation, and enables 80287 to execute the next instruction.
42. For which pin of 80286 is the active low pin, BUSY of 80287, connected?
a) ERROR (active low)
b) BUSY (active low)
c) HLDA
Allenhouse Institute of Technology (UPTU Code : 505)
d) TEST (active low)
Answer: d Rooma, Kanpur – 208 008
Explanation: The BUSY (active low) is connected to the TEST (active low) pin of 80286.
43. If Clock Mode (CM) input pin is held low, then the CLK input is divided by
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: If Clock Mode (CM) input pin is held high, then the CLK input is directly used for deriving the internal
timings. Else, it is divided by 2.
44. Which of the following pin is not involved in the interface of 80287 with 80286?
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answer: c
Explanation: The 10 pins, PEREQ, PEACK#, BUSY#, ERROR#, NPRD(active low)#, NPWR(active low)#, NPS1(active low)#,
NPS2#, CMD0 and CMD1.
45. The PEACK (active low) when activated, the pin that goes into deactivation is
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answer: a
Explanation: When the data transfer is over, the CPU activates PEACK (active low)# pin, which results in deactivating the
PEREQ pin by 80287.
46. The semiconductor memories are organised as __________ dimension(s) of array of memory locations.
a) one dimensional
b) two dimensional
c) three dimensional
d) none
Answer: b
Explanation: The semiconductor memories are organised as two dimensions of an array which consists of rows and
columns.
47. If a location is selected, then all the bits in it are accessible using a group of conductors called
a) control bus
b) address bus
c) data bus
d) either address bus or data bus
Answer: c
Explanation: The bits in a selected location are accessible using data bus.
48. To address a memory location out of N memory locations, the number of address lines required is
a) log N (to the base 2)
b) log N (to the base 10)
c) log N (to the base e)
Allenhouse Institute of Technology (UPTU Code : 505)
d) log (2N) (to the base e)
Answer: a Rooma, Kanpur – 208 008
Explanation: For n memory locations, log n(to the base of 2) address lines are required. For addressing 4K bytes of
memory, 12 address lines are required since log(4KB) =log(4*1024)=log(212)=12.
49. If the microprocessor has 10 address lines, then the number of memory locations it is able to address is
a) 512
b) 1024
c) 2048
d) none
Answer: b
Explanation: Since for n address lines, the number of memory locations able to address is 2^n.
50. In static memory, the upper 8-bit bank of an available 16-bit memory chip is called
a) upper address memory bank
b) even address memory bank
c) static upper memory
d) odd address memory bank
Answer: d
Explanation: In static memory, the upper 8-bit bank is called odd address memory bank.
51. In static memory, the lower 8-bit bank of an available 16-bit memory chip is called
a) lower address memory bank
b) even address memory bank
c) static lower memory bank
d) odd address memory bank
Answer: b
Explanation: In static memory, the lower 8-bit bank is called even address memory bank.
52. In most of the cases, the method used for decoding that may be used to minimise the required hardware is
a) absolute decoding
b) non-linear decoding
c) linear decoding
d) none
Answer: c
Explanation: In general, linear decoding is used to minimise the required hardware.
53. To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
a) parallel
b) serial
c) both serial and parallel
d) neither serial nor parallel
Answer: a
Explanation: The two 4K*8 chips of RAM and ROM are arranged in parallel.
54. If (address line) Ao=0 then, the status of address and memory are
a) address is even and memory is in ROM
b) address is odd and memory is in ROM
c) address is even and memory is in RAM
d) address is odd and memory is in RAM
Answer: c
Explanation: If Ao=0 then address is even and is in RAM. If Ao=1 then, address is odd and is in RAM.
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55. If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be
a) RAM Rooma, Kanpur – 208 008
b) ROM
c) RAM and ROM
d) ONLY RAM
Answer: c
Explanation: If at a time Ao and BHE(active low) both are zero, then both RAM and ROM are selected
nd other competitive examinations.
1. What is true about microprocessor?
A. Microprocessor is a controlling unit of a micro-computer
B. It is fabricated on a small chip capable of performing ALU (Arithmetic Logical Unit)
operations
C. It also communicate with the other devices connected to it.
D. All of the above
View Answer
Ans : D
Explanation: Microprocessor is a controlling unit of a micro-computer, fabricated on a small chip capable
of performing ALU (Arithmetic Logical Unit) operations and communicating with the other devices
connected to it.
2. Microprocessor consists of?
A. ALU
B. register array
C. control unit
D. All of the above
View Answer
Ans : D
Explanation: Microprocessor consists of an ALU, register array, and a control unit.
3. The __________ controls the flow of data and instructions within the computer.
A. control unit
B. register array
C. accumulator
D. ALU
View Answer
Ans : A
Explanation: The control unit controls the flow of data and instructions within the computer.
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
4. Which of the following is not a features of a Microprocessor?
A. Versatility
B. Reliability
C. Low Bandwidth
D. Low Power Consumption
View Answer
Ans : C
Explanation: low bandwidth is not a features of a Microprocessor
5. The microprocessor ___________ those instructions from the memory
A. Fetch
B. Decode
C. Execute
D. None of the above
View Answer
Ans : A
Explanation: The microprocessor fetches those instructions from the memory, then decodes it
6. It determines the number of operations per second?
A. Bandwidth
B. Word Length
C. Clock Speed
D. Operations Speed
View Answer
Ans : C
Explanation: Clock Speed : It determines the number of operations per second the processor can
perform. It is expressed in megahertz (MHz) or gigahertz (GHz).
7. Clock Speed is also known as?
A. Clock Rate.
B. Clock Length.
C. Clock Set.
D. Clock Type.
View Answer
Ans : A
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Explanation: Clock Speed : It determines the number of operations per second the processor can
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perform. It is expressed in megahertz (MHz) or gigahertz – 208 008
(GHz).It is also known as Clock Rate.
8. An 8-bit microprocessor can process _____ data at a time.
A. 4-bit
B. 8-bit
C. 16-bit
D. All of the above
View Answer
Ans : B
Explanation: An 8-bit microprocessor can process 8-bit data at a time.
9. The number of bits processed in a single instruction is known as ?
A. Instruction Set
B. Bandwidth
C. Bandspeed
D. Instruction Speed
View Answer
Ans : B
Explanation: Bandwidth : It is the number of bits processed in a single instruction.
10. What is false about microprocessor?
A. The microprocessor is of small size chip, hence is not portable.
B. microprocessor chips are available at low prices
C. microprocessors are versatile
D. failure rate of an IC in microprocessors is very low
View Answer
Ans : A
Explanation: The microprocessor is of small size chip, hence is portable
1. A microprocessor can be classified into?
A. 2
B. 3
C. 4
D. 5
View Answer
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Ans : B
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Explanation: A microprocessor can be classified into three categories: RISC, CISC and special
processors
2. Which of the following is not a RISC processors?
A. Power PC: 501
B. DEC Alpha: 210642
C. MIPS: TS (R10000) RISC Processor
D. PA-RISC: HP 7100LC
View Answer
Ans : A
Explanation: Power PC: 501 is not a RISC processors, instead of that Power PC: 601, 604, 615, 620 are
RISC processors.
3. Which of the following are correct characteristics of RISC?
A. It consists of simple instructions.
B. It supports various data-type formats.
C. It supports register to use in any context.
D. All of the above
View Answer
Ans : D
Explanation: All of the above are correct characteristics of RISC.
4. Which of the following is not a CISC processors?
A. IBM 370/168
B. Dell 5435
C. Intel 80486
D. VAX 11/780
View Answer
Ans : B
Explanation: Dell 5435 is not a CISC processors.
5. Which Processors includes multi-clocks?
A. RISC
B. CISC
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C. DSP
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D. Transputer
View Answer
Ans : B
Explanation: CISC includes multi-clocks.
6. Which of the following are incorrect Characteristics of CISC?
A. Variety of addressing modes.
B. Variable length of instruction format
C. Instruction-decoding logic is complex.
D. Small number of instructions.
View Answer
Ans : D
Explanation: Larger number of instructions is correct Characteristics of CISC.
7. A _______________ is a specially designed microprocessor, which can handle its
particular function many times faster than the ordinary microprocessor.
A. Input/Output Processor
B. Transputer
C. Coprocessor
D. DSP
View Answer
Ans : C
Explanation: A coprocessor is a specially designed microprocessor, which can handle its particular
function many times faster than the ordinary microprocessor.
8. DSP stands for?
A. Digital Signal Processor
B. Digital Signal Preprocessor
C. Digital Signal Program
D. Data Signal Processor
View Answer
Ans : A
Explanation: DSP: This processor is specially designed to process the analog signals into a digital form.
9. What is true about Transputer?
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A. It is a specially designed microprocessor having a local memory of its own
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B. A transputer is a specially designed microprocessor with its own local memory
C. It can handle its particular function many times faster than the ordinary microprocessor.
D. This processor is specially designed to process the analog signals into a digital form.
View Answer
Ans : B
Explanation: A transputer is a specially designed microprocessor with its own local memory and having
links to connect one transputer to another transputer for inter-processor communications
10. Graphic display controller is an example of?
A. Input/Output Processor
B. Transputer
C. Coprocessor
D. DSP
View Answer
Ans : A
Explanation: Graphic display controller is an example of Input/Output Processor
1. 8085 microprocessor is an 8-bit microprocessor designed by?
A. IBM
B. Dell
C. Intel
D. VAX
View Answer
Ans : C
Explanation: 8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor
designed by Intel in 1977.
2. In 8085, 16-bit address bus, which can address upto?
A. 16KB
B. 32KB
C. 64KB
D. 128KB
View Answer
Ans : C
Explanation: In 8085, 16-bit address bus, which can address upto 64KB.
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3. There are _______ general purpose registers in 8085 processor
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A. 5
B. 6
C. 7
D. 8
View Answer
Ans : B
Explanation: There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each
register can hold 8-bit data.
4. It is also a 16-bit register works like stack, which is always
incremented/decremented by 2 during push & pop operations.
A. Stack pointer
B. Temporary register
C. Flag register
D. Program counter
View Answer
Ans : A
Explanation: Stack pointer : It is also a 16-bit register works like stack, which is always
incremented/decremented by 2 during push & pop operations.
5. Flag register is an 8-bit register having __________ 1-bit flip-flops.
A. 3
B. 4
C. 5
D. 6
View Answer
Ans : C
Explanation: These are the set of 5 flip-flops : Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P) and
Carry (C)
6. What is true about Program counter?
A. It is an 8-bit register, which holds the temporary data of arithmetic and logical
operations.
B. When an instruction is fetched from memory then it is stored in the program counter
C. It provides timing and control signal to the microprocessor
D. It is a 16-bit register used to store the memory address location of the next instruction to
be executed.
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View Answer
Ans : D Rooma, Kanpur – 208 008
Explanation: Program counter : It is a 16-bit register used to store the memory address location of the
next instruction to be executed.
7. This signal indicates that another master is requesting the use of the address and
data buses.
A. READY
B. HOLD
C. HLDA
D. INTA
View Answer
Ans : B
Explanation: HOLD : This signal indicates that another master is requesting the use of the address and
data buses.
8. This signal is used as the system clock for devices connected with the
microprocessor.
A. X1, X2
B. CLK OUT
C. CLK IN
D. IO/M
View Answer
Ans : B
Explanation: CLK OUT : This signal is used as the system clock for devices connected with the
microprocessor.
9. Which of the following is true about Control and status signals?
A. These signals are used to identify the nature of operation.
B. There are 3 control signal and 3 status signals.
C. Three status signals are IO/M, S0 & S1.
D. All of the above
View Answer
Ans : D
Explanation: All of the above are correct about Control and status signals.
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10. MVI K, 20F is an example of? Rooma, Kanpur – 208 008
A. Immediate addressing mode
B. Register addressing mode
C. Direct addressing mode
D. Indirect addressing mode
View Answer
Ans : A
Explanation: Immediate addressing mode : In this mode, the 8/16-bit data is specified in the instruction
itself as one of its operand. For example: MVI K, 20F: means 20F is copied into register K
8086 Microprocessor supports _______ modes of operation.
A. 2
B. 3
C. 4
D. 5
View Answer
Ans : A
Explanation: It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum
mode is suitable for system having multiple processors and Minimum mode is suitable for system having
a single processor.
2. Which of the following is not a Features of 8086?
A. It uses two stages of pipelining
B. It is available in 3 versions based on the frequency of operation
C. Fetch stage can prefetch up to 6 bytes of instructions
D. It has 512 vectored interrupts.
View Answer
Ans : D
Explanation: It has 256 vectored interrupts is true Features of 8086.
3. 8086 can access up to?
A. 512KB
B. 1Mb
C. 2Mb
D. 256KB
View Answer
Ans : B
Explanation: 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.
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4. 8086 has ___ address bus.
A. 16-bit
B. 18-bit
C. 20-bit
D. 24-bit
View Answer
Ans : C
Explanation: Address Bus : 8085 has 16-bit address bus while 8086 has 20-bit address bus.
5. Which flag is set to 1 when the result of arithmetic or logical operation is zero
else it is set to 0?
A. Binary bit
B. Zero flag
C. Sign flag
D. Overflow flag
View Answer
Ans : B
Explanation: Zero flag : This flag is set to 1 when the result of arithmetic or logical operation is zero else it
is set to 0.
6. Which flag represents the result when the system capacity is exceeded?
A. Carry flag
B. Auxiliary flag
C. Trap flag
D. Overflow flag
View Answer
Ans : D
Explanation: Overflow flag : This flag represents the result when the system capacity is exceeded.
7. It is an edge triggered input, which causes an interrupt request to the
microprocessor.
A. NMA
B. INTR
C. INTA
D. ALE
View Answer
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Ans : A
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Explanation: NMI : It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered
input, which causes an interrupt request to the microprocessor.
8. It is used to write the data into the memory or the output device depending on
the status of M/IO signal.
A. IR
B. HLDA
C. HR
D. WR
View Answer
Ans : D
Explanation: WR : It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.
9. Which intruction is Used to load the address of operand into the provided
register?
A. LEA
B. LDS
C. LES
D. LAHF
View Answer
Ans : A
Explanation: LEA : Used to load the address of operand into the provided register.
10. The different ways in which a source operand is denoted in an instruction is
known as
A. Instruction Set
B. Interrupts
C. 8086 Configuration
D. Addressing Modes
View Answer
Ans : D
Explanation: The different ways in which a source operand is denoted in an instruction is known as
addressing modes. There are 8 different addressing modes in 8086 programming
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1. How many types of basic multiprocessor configurations?
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A. 2
B. 3
C. 4
D. 5
View Answer
Ans : B
Explanation: Multiprocessor means a multiple set of processors that executes instructions
simultaneously. There are three basic multiprocessor configurations : Coprocessor configuration, Closely
coupled configuration and Loosely coupled configuration.
2. A _____________ is a specially designed circuit on microprocessor chip which can
perform the same task very quickly, which the microprocessor performs
A. Coprocessor configuration
B. Closely coupled configuration
C. Loosely coupled configuration
D. None of the above
View Answer
Ans : A
Explanation: A Coprocessor is a specially designed circuit on microprocessor chip which can perform the
same task very quickly, which the microprocessor performs.
3. The coprocessor and the processor is connected via?
A. TEST
B. QS0
C. QS1
D. All of the above
View Answer
Ans : D
Explanation: The coprocessor and the processor is connected via TEST, RQ-/GT- and QS0 & QS1
signals.
4. _________signal takes care of the coprocessor's activity, i.e. the coprocessor is busy
or idle.
A. TEST
B. QS0
C. QS1
D. None of the above
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View Answer
Ans : A Rooma, Kanpur – 208 008
Explanation: TEST signal takes care of the coprocessor's activity, i.e. the coprocessor is busy or idle.
5. Which of the following are advantage of Loosely Coupled Configuration?
A. Having more than one processor results in increased efficiency.
B. easy to achieve parallel processing.
C. system structure is flexible
D. All of the above
View Answer
Ans : D
Explanation: All of the above are advantage of Loosely Coupled Configuration
6. 8087 numeric data processor is also known as?
A. Math co-processor
B. Numeric processor extension
C. Floating point unit
D. All of the above
View Answer
Ans : D
Explanation: 8087 numeric data processor is also known as Math co-processor, Numeric processor
extension and Floating point unit.
7. 8087 Architecture is divided into?
A. 2
B. 3
C. 4
D. 5
View Answer
Ans : B
Explanation: 8087 Architecture is divided into two groups, i.e., Control Unit (CU) and Numeric Extension
Unit (NEU).
8. It is a power supply signal, which requires +5V supply for the operation of the
circuit.
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A. VCA
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B. VDD
C. VCC
D. INTA
View Answer
Ans : C
Explanation: VCC : It is a power supply signal, which requires +5V supply for the operation of the circuit.
9. The _________ handles all the communication between the processor and the
memory
A. numeric extension unit
B. Packed Unit
C. control unit
D. Binary Unit
View Answer
Ans : C
Explanation: The control unit handles all the communication between the processor and the memory
10. 8087 Numeric Data Processor designed by?
A. Intel
B. IBM
C. Microsoft
D. VAX
View Answer
Ans : A
Explanation: It was the first math coprocessor designed by Intel to pair with 8086/8088 resulting in easier
and faster calculation
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other competitive examinations.
1. How many types of Interfacing?
A. 2
B. 3
C. 4
D. 5
View Answer
Ans : A
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Explanation: Interface is the path for communication between two components. Interfacing is of two
types, memory interfacing and I/O interfacing. Rooma, Kanpur – 208 008
2. In which type of communication, the interface gets a single byte of data from the
microprocessor and sends it bit by bit to the other system serially and vice-a-versa?
A. Parallel Communication Interface
B. Serial Communication Interface
C. Both A and B
D. None of the above
View Answer
Ans : B
Explanation: Serial Communication Interface : In this type of communication, the interface gets a single
byte of data from the microprocessor and sends it bit by bit to the other system serially and vice-a-versa.
3. Which of the following are known as Higher Address Bus?
A. A15 - A8
B. AD7 - AD0
C. READY
D. WR
View Answer
Ans : A
Explanation: A15 - A8 (Higher Address Bus)
4. In which mode, the CPU periodically reads an internal flag of 8279 to check
whether any key is pressed or not with key pressure?
A. Interrupt mode
B. Polled mode
C. Decoded Mode
D. Encoded Mode
View Answer
Ans : B
Explanation: In the Polled mode, the CPU periodically reads an internal flag of 8279 to check whether
any key is pressed or not with key pressure.
5. What is true about Encoded Mode?
A. the unit contains registers to store the keyboard, display modes
B. the counter internally decodes the least significant 2 bits and provides a decoded 1 out
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of 4 scan on SL0-SL3.
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C. the processor is requested service only if any key is pressed, otherwise the CPU will
continue with its main task.
D. the counter provides the binary count that is to be externally decoded to provide the
scan lines for the keyboard and display.
View Answer
Ans : D
Explanation: In the encoded mode, the counter provides the binary count that is to be externally decoded
to provide the scan lines for the keyboard and display.
6. Which pin is used to blank the display during digit switching?
A. WR
B. IR
C. BD
D. DB
View Answer
Ans : C
Explanation: BD : It stands for blank display. It is used to blank the display during digit switching.
7. Which mode allows 8/16 character multiplexed displays to be organized as dual
4-bit/single 8-bit display units?
A. Display Entry
B. Display Scan
C. Strobed Input
D. Scanned Keyboard Mode
View Answer
Ans : B
Explanation: Display Scan : This mode allows 8/16 character multiplexed displays to be organized as
dual 4-bit/single 8-bit display units.
8. DMA stands for?
A. Display Memory Access
B. Directly Memory Access
C. Device Memory Access
D. Direct Memory Access
View Answer
Ans : D
Explanation: DMA stands for Direct Memory Access
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9. Which of the following is not true features of 8257?
A. It has three channels which can be used over three I/O devices.
B. Each channel has 16-bit address and 14-bit counter.
C. Each channel can transfer data up to 64kb.
D. Each channel can be programmed independently.
View Answer
Ans : A
Explanation: It has four channels which can be used over four I/O devices is true.
10. What is correct range of frequency for 8257?
A. 500Hz to 3MHz.
B. 250Hz to 2MHz.
C. 250Hz to 3MHz.
D. 500Hz to 2MHz.
View Answer
Ans : C
Explanation: Its frequency ranges from 250Hz to 3MH
1. What is true about microcontroller?
A. A microcontroller is a small and low-cost microcomputer
B. It is designed to perform the specific tasks of embedded systems
C. microcontroller consists of the processor, the memory, Serial ports, peripherals.
D. All of the above
View Answer
Ans : D
Explanation: All of the above statement are true.
2. Which is false about microcontroller?
A. Microcontrollers are used to execute a single task within an application.
B. It consists of CPU, RAM, ROM, I/O ports.
C. Its power consumption is high because it has to control the entire system.
D. It is built with CMOS technology
View Answer
Ans : C
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Explanation: It is built with CMOS technology, which requires less power to operate.
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3. This type of microcontroller is generally used in automatically controlled
appliances like automatic operational machines.
A. 8-bit microcontroller
B. 16-bit microcontroller
C. 32-bit microcontroller
D. 64-bit microcontroller
View Answer
Ans : C
Explanation: 32-bit microcontroller : This type of microcontroller is generally used in automatically
controlled appliances like automatic operational machines.
4. This type of microcontroller is designed in such a way that they do not have a
program memory on the chip.
A. External memory microcontroller
B. Embedded memory microcontroller
C. CISC
D. RISC
View Answer
Ans : A
Explanation: External memory microcontroller : This type of microcontroller is designed in such a way
that they do not have a program memory on the chip. Hence, it is named as external memory
microcontroller.
5. Which of the following is an example of Embedded memory microcontroller?
A. Intel 8031 microcontroller
B. Intel 8051 microcontroller.
C. Intel 8081 microcontroller.
D. Intel 8085 microcontroller.
View Answer
Ans : B
Explanation: Intel 8051 microcontroller is an example of Embedded memory microcontroller.
6. 8051 microcontroller is designed by Intel in?
A. 1980
B. 1981
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C. 1982
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D. 1983
View Answer
Ans : B
Explanation: 8051 microcontroller is designed by Intel in 1981. It is an 8-bit microcontroller
7. At what PIN number, there is a RESET pin, which is used to reset the
microcontroller to its initial values?
A. PIN 9
B. PIN 20
C. PIN 30
D. PIN 35
View Answer
Ans : A
Explanation: Pin 9 : It is a RESET pin, which is used to reset the microcontroller to its initial values.
8. At what PIN number, there is EA pin which stands for External Access input?
A. PIN 28
B. PIN 29
C. PIN 30
D. PIN 31
View Answer
Ans : C
Explanation: Pin 30 : This is EA pin which stands for External Access input. It is used to enable/disable
the external memory interfacing.
9. When pins are configured as an output (i.e. logic 0), then the single port pins can
receive a current of?
A. 5mA
B. 8mA
C. 15mA
D. 10mA
View Answer
Ans : D
Explanation: When pins are configured as an output (i.e. logic 0), then the single port pins can receive a
current of 10mA.
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10. Which IO Port can be used for higher address byte with addresses A8-A15?
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A. PORT1
B. PORT0
C. PORT3
D. PORT2
View Answer
Ans : D
Explanation: PORT2 : This port can be used for higher address byte with addresses A8-A15. When no
memory is added then this port can be used as a general input/output port similar to Port 1
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1. The ______ is a general purpose programmable I/O device designed to transfer the
data from I/O to interrupt I/O.
A. 8285A
B. 8241A
C. 8255A
D. 8251A
View Answer
Ans : C
Explanation: The 8255A is a general purpose programmable I/O device designed to transfer the data
from I/O to interrupt I/O
2. How many ports 8255A has?
A. 2
B. 3
C. 4
D. 5
View Answer
Ans : B
Explanation: 8255A has three ports, i.e., PORT A, PORT B, and PORT C.
3. Which port can be split into two parts?
A. PORT A
B. PORT B
C. PORT C
D. PORT D
View Answer
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Ans : C
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Explanation: Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-
PC4) by the control word.
4. Which of the following are Features of 8255A?
A. It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
B. Address/data bus must be externally demux'd.
C. It is TTL compatible.
D. All of the above
View Answer
Ans : D
Explanation: All of the above are Features of 8255A.
5. Which of the following is responsible for controlling the internal/external
transfer of data/control/status word?
A. Data Bus Buffer
B. Read/Write Control Logic
C. CS
D. WR
View Answer
Ans : B
Explanation: Read/Write Control Logic : This block is responsible for controlling the internal/external
transfer of data/control/status word.
6. Which of the following uses N-MOS technology?
A. 8253
B. 8254
C. 8255
D. 8256
View Answer
Ans : A
Explanation: 8253 : It uses N-MOS technology.
7. It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54
to the system data bus.
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A. Read/Write Logic
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B. Data Bus Buffer
C. system data bus
D. System Buffer
View Answer
Ans : B
Explanation: Data Bus Buffer : It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the
8253/54 to the system data bus.
8. 8253/54 can be operated in _________ Modes?
A. 3
B. 4
C. 5
D. 6
View Answer
Ans : D
Explanation: 8253/54 can be operated in 6 different modes
9. Which mode can be used as a mono stable multi-vibrator?
A. Mode 0
B. Mode 1
C. Mode 2
D. Mode 3
View Answer
Ans : B
Explanation: Mode 1 : Programmable One Shot can be used as a mono stable multi-vibrator.
10. Which mode generates a strobe in response to an externally generated signal?
A. Mode 3
B. Mode 4
C. Mode 5
D. Mode 6
View Answer
Ans : C
Explanation: Mode 5 : Hardware Triggered Mode generates a strobe in response to an externally
generated signal.
Allenhouse Institute of Technology (UPTU Code : 505)
Which one of the following is not correct?
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Bus is a group of wires
Bootstrap is a technique or device for loading first instruction
An instruction is a set of bits that defines a computer operation
An interrupt signal is required at the start of every program
Correct
Interrupt is required for interruption of main program to perform a subroutine. It may be used at the start of
some program as per requirement but it is not mandatory at start of every program.
Which one of the following circuits transmits two messages simultaneously in one direction
Diplex
Duplex
Quadruplex
Simplex
Incorrect
Diplex circuits transmits two messages simultaneously
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
8085 microprocessor has how many pins
41
40
30
39
Incorrect
Intel 8085 NMOS microprocessor is a 8 bit, 40 pins IC. It is a 40 pin I.C. package fabricated on a single LSI chip. The
Intel 8085 uses a single + 5 V DC supply for its operation.Its clock speed is about 3 MHz. The clock cycle is 320 ns. It
has 80 basic instructions and 246 opcodes.
What is SIM?
Set interrupt mask
Sorting interrupt mask
Select interrupt mask
None of the answers
Incorrect
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SIM stands for set interrupt mask which is handling the interrupts in 8085 microprocessor.
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A field programmable ROM is called
MROM
FROM
PROM
FPROM
Correct
In PROM data is stored by user. Only one time programmable and reprogramming is not possible
In 8085 microprocessor, the RST6 instruction transfer programme execution to following location
0060H
0024H
0030H
0048H
Incorrect
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6 X 8 = ( 48)10= 0030H.
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HLT opcode means
load data to accumulator.
store result in memory.
load accumulator with contents of register.
end of program.
Correct
HLT opcode in 8085 microprocessor means end of program
A microprocessor is ALU
register unit and I/O device on a single chip.
register unit and control unit on a single chip.
and control unit on a single chip.
and memory on a single chip.
Incorrect
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A microprocessor is a semiconductor component designed by using VLSI technology and it contains ALU, Control unit
(CU) and registers of a CPU in a single package Rooma, Kanpur – 208 008
The length of bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate
number of wait state clock cycles denoted by Tw. The wait states are always inserted between
𝑇4&𝑇1
𝑇2&𝑇3
𝑇3&𝑇4
𝑇1&𝑇2
Correct
The wait states are always inserted between T3 & T4
A combinational PLD with a programmable AND array and a programmable OR array is called a
PAL
PLA
PROM
PLD
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ROM – Fixed AND array and fixed OR array PROM – Fixed AND array and Programmable OR array PAL –
Programmable AND array and fixed OR array PLA – Programmable AND array and programmable OR array
Which language could be used for programming an FPGA.
None of the answers
Both Verilog & VHDL
VHDL
Verilog
Incorrect
Verilog and VHDL are the hardware description languages that are used for the programming of FPGAs. Both
of these languages are case-insensitive in nature.
In 8085 name of the 16 bit registers is
none of the answers
program counter
stack pointer
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both stack pointer & program counter
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Correct
Program counter (PC) and Stack pointer (SP) are basically used to hold 16 - bit memory addresses. PC stores
the 16-bit memory address of the next instruction to be fetched. SP can be used to temporarily store the 16 - bit
memory address as well as data. So PC and SP are 16-bit registers.
Inintel 8085A microprocessor ALE signal is made high to
To disable data bus
To achieve all the functions listed above
Enable the data bus to be used as low order address bus
To latch data D0-D7 from data bus
Incorrect
When ALE signal is high all the buses are used as address bus and when it is low lower byte of address bus is
used as data bus.
The program counter in a 8085 micro-processor is a 16-bit register, because
It facilitates the user storing 16-bit data temporarily
It has to fetch two 8-bit data at a time
There are 16 address lines
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It counts 16-bits at a time
Incorrect
Program counter stores the address of next instruction to be fetched. AS 8085 address is of 16-bit so program
counter has to be of 16-bit
Which of the following statements for intel 8085 is correct?
PC specifies the number of instructions executed so far
Program Counter (PC) specifies the address of the instruction last executed
PC specifies the address of the instruction being executed
PC specifies the address of the instruction to be executed
Correct
Program counter contains the address of the instruction to be fetched.
The number of output pins in 8085 microprocessors are
21
40
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19
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27
Incorrect
In 8085 microprocessor there are 40 pins out of which 27 are output pins and rest 13 are including clock input,
power supply and other input pins
I)A total of about one million bytes can be directly addressed by the 8086 microprocessor II)8086
has thirteen 16-bit registers III)8086 has eight flags IV)Compared to 8086, the 80286 provides a
higher degree of memory protection Which one of the statements given above are correct?
2,3&4
1,3 &4
1,2 & 4
1,2 & 3
Correct
→ 8086 has 9 flags i.e. CF, PF, AF, ZF, SF, TF, IF, DF, OF → 8086 has 20 address lines so it can address
220 = 1Mbyte memory location. → 8086 has thirteen 16-bit registers
What is mean by ALU
Arithmetic logic unit
Arithmetic logic upgrade
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Arithmetic local unsigned
Arithmetic logic unsigned
Correct
It is used for arithmetic operations...
What are the sets of commands in a program which are not translated into machine instructions
during assembly process, called?
Mnemonics
Directives
Identifiers
Operands
Incorrect
Directives are not translated into machine instruction during assembly process.
The ROM programmed during manufacturing process itself is called
EEPROM
MROM
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PROM
EPROM
Incorrect
The ROM programmed during manufacturing process itself is called MROM. Data is stored by the manufacturer during
fabrication. User can not alter
Processor status word of 8085 microprocessor has five flags?
S, Z, AC, P, CY
S, Z, OV, P, CY
S, Z, AC, P, OV
S, OV, AC, P, CY
Incorrect
8085 microprocessor has 5 status flag S → Sign flag Z → Zero flag AC → Auxiliary carry flag P → Parity flag
CY → Carry flag
A combinational PLD with a fixed AND array and a programmable OR array is called a
PLA
PAL
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PROM
PLD
Correct
ROM – Fixed AND array and fixed OR array PROM – Fixed AND array and Programmable OR array PAL –
Programmable AND array and fixed OR array PLA – Programmable AND array and programmable OR array
A combinational PLD with a fixed AND array and a programmable OR array is called a
PLA
PAL
PROM
PLD
Correct
ROM – Fixed AND array and fixed OR array PROM – Fixed AND array and Programmable OR array PAL –
Programmable AND array and fixed OR array PLA – Programmable AND array and programmable OR array
FPGA means
Forward Programmable Gate Array
Forward Parallel Gate Array
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Field Parallel Gate Array
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Field Programmable Gate Array
Correct
Field Programmable Gate Array (FPGA) are the re-configurable hardware. Which consists of millions of logic
gate which could be arranged according to the user's demand. Also having much higher frequency than in
micro controllers.
Output of the assembler in machine codes is referred to as
Object program
Macroinstruction
Source program
Symbolic addressing
Incorrect
Input to a assembler is the source program and assembler converts it into object program.
A combinational PLD with a programmable AND array and a fixed OR array is called a
PAL
PLD
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PROM
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PLA
Incorrect
ROM – Fixed AND array and fixed OR array PROM – Fixed AND array and Programmable OR array PAL –
Programmable AND array and fixed OR array PLA – Programmable AND array and programmable OR array
Which one of the following is not a vectored interrupt?
TRAP
RST 3
RST 7.5.
INTR
Incorrect
Here TRAP, INTR, RST 7.5 are vectored interrupt. But RST 3 is not a non vectored interrupt.
The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one of
the following?
Clock cycle
Memory cycle
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Instruction cycle
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Machine cycle
Incorrect
One machine cycle is equivalent to one memory access. Clock cycle implies one clock period. Instruction cycle
includes fetching and execution of a given instruction.
A good assembly language programmer should use general purpose registers rather than memory
in maximum possible ways for data processing. This is because:
Data processing with memory requires more instructions in the program than that with registers
Data processing with registers takes fewer cycles than that with memory
Data processing with registers is easier than with memory
Of limited set of instructions for data processing with memory
Incorrect
Data processing with registers takes fewer cycle than with memory which require extra memory read or write
signal.
A mask programmed ROM is
programmed by the user
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erasable electrically
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programmed at the time of fabrication
erasable and programmable
Incorrect
The ROM programmed during manufacturing process itself is called MROM. Data is stored by the
manufacturer during fabrication. User can not alter. In PROM data is stored by user. Only one time
programmable and reprogramming is not possible. EPROM erasing is done using UV light and programming is
through electrical.
Consider the following registers:
1. Accumulator and flag register
2. B and C register
3. D and E register
4. H and L register
Which of these 8-bit registers of 8085 microprocessor can be paired together to make a 16-bit
register?
1, 2 and 4
2, 3 and 4
1, 2 and 3
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1, 3 and 4
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We can not combine accumulator and flag register to form 16-bit register whereas B & C, D & E, H & L can
be combined to form a 16-bit register.
Consider the following statements: Arithmetic Logic Unit (ALU)
1.Performs arithmetic operations
2.Performs comparisons.
3.Communicates with I/O devices
4.Keeps watch on the system
Which of these statements are correct?
1 and 2 only
3 and 4 only
1, 2 and 3
1, 2, 3 and 4
Incorrect
ALU performs arithmetic and logical operations. Note: Comparison is a logical operation.
Assertion(A): Address bus is unidirectional.
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Reason(R): Data bus is bidirectional
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Both A & R are true and R is the correct explanation of A
A is true but R is false
A is false but R is true
Both A & R are true but R is not the correct explanation of A
Correct
Address bus is unidirectional and data bus is bidirectional.
While using a frequency counter for measuring frequency, two modes of measurement are
possible.
1. Period time
2. Frequency mode
There is a ‘cross-over frequency’ below which the period mode is preferred. Assuming the crystal
oscillator frequency to be 4Mhz the crossover frequency is given by
2 Mhz
8 Mhz
1Khz
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2 Khz
Incorrect
As we know crossover frequency is the half of oscillator frequency. i.e.fcross-over = fcrystal/2 = 2Mhz
Number of Hex digits needed to represent the 20-bit address of a memory location are
20
16
Incorrect
Since a hex digit requires 4 bits to represent, it will take 5 hex digits to represent the 20-bit address of a
memory location.
Assertion(A): The frequency of 8085 system is ½ of the crystal frequency.
Reason(R): Microprocessor (8085) requires a two phase clock.
Both A & R are true but R is not the correct explanation of A
Both A &R are true and R is the correct explanation of A
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A is true but R is false
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A is false but R is true
Incorrect
Microprocessor clock frequency = (Crystal frequency/2)
ALU (Arithmetic and Logic Unit ) of 8085 microprocessor consists of
Accumulator, temporary register, arithmetic , logic circuits and five flags
Accumulator, arithmetic, logic circuits and five flags
Accumulator, temporary register, arithmetic and logic circuits
Accumulator, arithmetic and logic circuits
Incorrect
ALU consists of Accumulator, temporary register, arithmetic, logic circuits and five flags.
The field, which is never present in an assembly language statement, is
Opcode
Operand
Continue
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Comment
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Correct
There is nothing called “continue” in assembly language statement.
The correct sequence of steps in the instruction cycle of a basic computer is
Fetch, Read effective address, Decode and Execute.
Fetch, Execute, Decode and Read effective address.
Fetch, Decode, Read effective address and, Execute.
Read effective address, Decode, Fetch and Execute.
Incorrect
At first instruction is fetched then decoded and then read effective address and executed.
A bus connected between the CPU and main memory that permits transfer of information between
main memory and the CPU is known as
Address bus
Memory bus
Control bus
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DMA bus
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Correct
We know data bus (Also known as Memory bus) allows transfer of information between main memory and the
CPU.
consider the following
I) Sign flag
II) Trap flag
III) Parity flag
IV) Auxiliary carry flag
Which one of the above flags is/are present in 8085 microprocessor?
(I) only
(I) & (II)
(I) ,(III) & (IV)
(II) & (III)
Correct
Trap flag is not present in 8085 microprocessor.
The operations executed by two or more control units are referred as
Multi-operations
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Macro-operations
Micro-operations
Bi control-operations
Incorrect
The operations executed by two or more control units are referred as Macro-operations.
Assertion(A): Address bus is unidirectional.
Reason(R): Data bus is bidirectional
A is false but R is true
Both A &R are true and R is the correct explanation of A
Both A & R are true but R is not the correct explanation of A
A is true but R is false
Incorrect
Address bus is unidirectional and data bus is bidirectional.
IN an intel 8085A microprocessor, why is READY signal used?
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To slow down a fast peripheral device so as to communicate at the microprocessor’s device
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To provide proper WAIT states when the microprocessor is communicating with a slow peripheral device.
None of the answers
To indicate to user that the microprocessor is working and is ready for use.
Incorrect
Ready signal is used in microprocessor to communicate with slow peripheral device. It provides proper
synchronization between processor and slow devices.
Following is a 16-bit register for 8085 microprocessor
Accumulator
Register
Stack pointer
Register C
Incorrect
In a 8085 microprocessor Accumulator, register B & C are of 8-bit whereas stack pointer is a 16-bit register.
Consider the following statements: In 8085 microprocessor, data-bus and address bus are
multiplexed in order to
I)Increase the speed of microprocessor.
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II)Reduce the number of pins.
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III)Connect more peripheral chips.
Which of these statements is/are correct?
II) only
(I), (II) & (III)
(II) & (III)
(I) only
Incorrect
Lower byte of address bus (𝐴0-𝐴7 ) are multiplexed with data bus (𝐴𝐷0-𝐴𝐷7 ) to reduce the number of pins of
microprocessor. This multiplexed address is controlled by ALE signal.
Assertion(A): Monostable multivibrators (IC74121) are used in a microprocessor based system for
frequency measurement.
Reason(R): Microprocessor counts the number of interrupt signals/second or within a specified
interval through ISR.
A is false but R is true.
A is true but R is false.
Both A & R are true but R is not the correct explanation of A.
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Both A & R are true and R is the correct explanation of A.
Incorrect
IC74121 is used for frequency measurement in microprocessor and microprocessor counts the number of
interrupt signals/second or within a specified interval through ISR.
Both the ALU and control section of CPU employ which special purpose storage location?
Buffers
Decoders
Accumulators
Registers
Correct
Accumulator is a special purpose 8-bit register which is used as a storage for almost all arithmetic and logic
operations.
Both the ALU and control section of CPU employ which special purpose storage location?
Buffers
Decoders
Accumulators
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Registers
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Correct
Accumulator is a special purpose 8-bit register which is used as a storage for almost all arithmetic and logic
operations.
Ready pin of microprocessor is used
to indicate that microprocessor is ready to receive inputs
to indicate that microprocessor is ready to receive outputs
to introduce wait state
to provide direct memory access
Incorrect
Ready signal is used to provide proper wait state when processor is communicating with a slow peripheral
device.
The register which holds the information about the nature of results of arithmetic and logic
operations is called as
Flag register
Accumulator
Process status register
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Condition code register
Incorrect
In a microprocessor flag registers indicate status of an arithmetic and logic operation.
8085 microprocessor has how many pins
39
30
41
40
Correct
Intel 8085 NMOS microprocessor is a 8 bit, 40 pins IC. It is a 40 pin I.C. package fabricated on a single LSI
chip. The Intel 8085 uses a single + 5 V DC supply for its operation.Its clock speed is about 3 MHz. The clock
cycle is 320 ns. It has 80 basic instructions and 246 opcodes.
Which components are NOT found on chip in a microprocessor but may be found on chip in a
microcontroller?
SRAM & USART
SRAM, EPROM & PORTS
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EPROM & PORTS
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EPROM, USART & PORTS
Correct
EPROM, USART & PORTS are found on chip in microcontroller but not in microprocessor chip.
In 8085 microprocessor system with memory mapped I/O, which of the following is true?
Devices have 8-bit address line
There can be maximum of 256 input devices and 256 output devices
Arithmetic and logic operations can be directly performed with the I/O data
Devices are accessed using IN and OUT instructions
Incorrect
With the memory mapped I/O arithmetic and logic operations can be directly performed whereas with I/O
mapped I/O it is not possible. Options A, B, C are valid for I/O mapped I/O.
The output data lines of microprocessor and memories are usually tristated because
The data line can be multiplexed for both input and output
It increases the speed of data transfer over the data bus
More than one device can transmit over the data bus at the same time
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More than one device can transmit information over the data bus by enabling only one device at a time
Correct
Using tristate buffer, more than one device can transmit information over the data bus by enabling only one
device at a time.
When referring to instruction words, a mnemonic is
a short abbreviation for the operation to be performed.
a short abbreviation for the operand address.
shorthand for machine language.
a short abbreviation for the data word stored at the operand address
Assertion(A): The frequency of 8085 system is ½ of the crystal frequency.
Reason(R): Microprocessor (8085) requires a two phase clock.
Both A & R are true and R is the correct explanation of A
A is true but R is false
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A is false but R is true
Both A & R are true but R is not the correct explanation of A
Microprocessor clock frequency =(Crystal frequency/2)
Question 28 of 30
Your Score: 9 of 30
The first machine cycle of an instruction is always
A memory write cycle
A memory read cycle
A fetch cycle
An I/O read cycle
Incorrect
The first machine cycle of an instruction is always fetch cycle.
Question 29 of 30
Your Score: 9 of 30
ALU (Arithmetic and Logic Unit ) of 8085 microprocessor consists of
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Accumulator, temporary register, arithmetic, logic circuits and five flags
Accumulator, temporary register, arithmetic and logic circuits
Accumulator, arithmetic, logic circuits and five flags
Accumulator, arithmetic and logic circuits
Incorrect
ALU consists of Accumulator, temporary register, arithmetic, logic circuits and five flags.
Q. Match the items given in List I and those in List II. Select your answers using the
codes given in the question.
List I List II
Instruction Operation
1. Exchange the top of the stack with
A. PCHL
the contents of HL pair
2. Exchange the contents of HL with
B. SPHL
those of DE pair
3. Transfer the contents of HL to the
C. XTHL
stack pointer
4. Transfer the contents of HL to the
D. XCHG
programme counter
Codes: A B C D
(a) 3 4 1 2
(b) 3 4 2 1
(c) 4 3 2 1
(d) 4 3 1 2
Answer
(d)
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Q. Match the items given in List I and those in List II. Select your answers using the
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codes given in the question.
List I List II
Addressing mode Instruction
A. Implicit addressing 1. JMP 3FAO H
B. Register-indirect 2. MOV A,M
C. Immediate 3. LDA 03FC H
D. Direct addressing 4. RAL
Codes: A B C D
(a) 4 1 2 3
(b) 4 2 1 3
(c) 3 2 1 4
(d) 3 1 2 4
Answer
(b)
Q. Match the items given in List I and those in List II. Select your answers using the
codes given in the question.
List I List II
Instruction Type of addressing
A. MOV A,M 1. Direct addressing
B. LXIH, E400 H 2. Register addressing
C. LDA F1CD H 3. Implicit addressing
D. CMC 4. Register Indirect addressing
5. Immediate addressing
Codes: A B C D
(a) 5 4 1 3
(b) 4 5 3 1
(c) 5 4 2 3
(d) 4 5 1 3
Answer
(d)
stems, and mobile phones.
1). Microprocessor is a unit that controls ___________.
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Microcomputer - Rooma, Kanpur – 208 008
Marco computer
Input-output devices
System on chip
Hint
Read more about Microprocessor.
2). ALU stands for ________.
Arithmetic logical unit -
Addition logic unit
Adders logic unit
None of the above
Hint
3). What is the function of ALU?
Used to perform arithmetic operations
Used to perform arithmetic operations
Both a and b -
None of the above
Hint
4). Which of the following are the components of a microprocessor?
ALU
Register array
Control unit
All the above -
Hint
5). Which of the following statement is related to the register array?
It consist of registers like B, C, D, E, H, L
It consists of an accumulator
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Both a and b - Rooma, Kanpur – 208 008
None of the above
Hint
6). Which of the following statement is related to Accumulator?
It is a storage element
It performs complementing operations
It performs decimal operations
All the above -
Hint
7). The function of the control unit is _________.
It controls data flow
It controls instructions in a computer
It decides how computer memory, ALU unit, the input-output device should respond to the processor's
instructions
All the above -
Hint
Read more about Control Unit.
8). Which of the following sequence that a microprocessor follows?
Fetch, decode, execute -
Fetch, execute, decode
Decode, fetch, execute
Execute, decode, fetch
Hint
9). Initially the microprocessors stores instructions in ______ order in a memory.
Sequential manner -
Concurrent manner
Both a and b
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Hint
10). Instructions in a microprocessor, are fetched from _________.
Memory -
ALU
CPU
All the above
Hint
11). Microprocessor continues to execute the instruction until it reaches _______ instruction.
Start
Stop -
Continue
None of the above
Hint
12). When a microprocessor reaches a stop instruction it responds back in _______ format to the
ports output.
Decimal
Binary
0’s and 1’s -
Both b and c
Hint
13). Microprocessor understands a set of instructions called ________.
Instruction set -
Software
Code
All the above
Hint
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14). A single instruction processes number of bits in a processor it is called ______.
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Instruction processor
Bandwidth -
Clock speed
Frequency
Hint
15). A number of operations processes per second by a processor is called ______.
Instruction processor
Bandwidth
Clock speed -
Frequency
Hint
16). Word length depends on _______.
Internal bus width
Registers
ALU
All the above -
Hint
17). A microprocessor with 8-bit can process ______ bits of data at a time.
8-
12
16
Hint
18). Word length in a microcomputer ranges from ______.
4 bits to 64 bits -
4 bits to 128bits
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16 bits to 64 bits Rooma, Kanpur – 208 008
4 bits to 64 bytes
Hint
19). Which of the following are the data types used in a microprocessor?
Binary
BCD
ASCII
All the above -
Hint
20). Binary numbers are represented in which of the following.
0’s and 1’s -
A to Z
+1 and -1
Both a and b
Hint
21). BCD number is represented in which of the following.
0’s and 1’s
4 bits -
+1 and -1
Both a and b
Hint
22). ASCII stands for _______.
American standard code for information interchange-
Alphabet standard code for information interchange
American standard code for interchange information
None of the above
Hint
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Read more about ASCII.
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23). ASCII code can represent the text of which of the following data.
Computers
Telecommunication
Other electronic devices
All the above -
Hint
24). Signed number is represented in which of the following.
0’s and 1’s
4 bits
+1 and -1 -
Both a and b
Hint
25). Un-Signed number is represented in which of the following?
0’s and 1’s
4 bits
+1 and -1
0-
Hint
26). Which of the following are the features of a microprocessor?
Small chip size
Cost-effective
Is more versatile
All the above -
Hint
27). A microprocessor is made up of _________.
Silicon
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Metals
All the above -
Hint
28). How many months does it take for a microprocessor to build?
1 month
2 months -
3 months
4 months
Hint
29). A microprocessor is classified based on which of the following factors.
Size of a data bus
Size of an address bus
RISC and CISC
All the above -
Hint
30). RISC type processor stands for _________.
Reduced instruction set computer processor -
React instruction set computer processor
Reduced information set computer processor
None of the above
Hint
Microprocessor MCQs with Answers
31). CISC type Processor stands for _______.
Complex instruction set computer processor -
Computer instruction set computer processor
Complex information set computer processor
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Hint
32). Microprocessors are of how many types?
3-
5
Hint
Read more about RISC and CISC Processors.
33). What is the main purpose of the RISC type processor?
Reduces execution time
It consumes only single clock cycle
Both a and b -
None of the above
Hint
34). Does the RISC type processor consumes more RAM memory to store instruction?
Yes -
No
Maybe
Hint
35). Choose the examples of RISC type processors.
MIPS:TS(R10000) RISC type Processor
Power PC: 601
DEC Alpha: 210642
All the above -
Hint
36). RISC type processor uses _______ set of instruction set.
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Low optimized
Optimized
None of the above
Hint
37). RISC type processor architecture consists of which of the following components.
Hardwired control unit
Instruction cache
Main memory
All the above -
Hint
38). RISC type processor consists of _______ instruction set.
Simple -
Tough
Equal
None of the above
Hint
39). Does the RISC type processor supports different data types?
Yes -
No
Maybe
Hint
40). RISC type processor uses _____ types of addressing modes?
Simple -
Complex
Common
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Both a and b Rooma, Kanpur – 208 008
Hint
41). RISC type processor uses _____ length instruction for pipelining.
Fixed -
Variable
Common
Both a and b
Hint
42). RISC type processor uses ______ cycle execution time.
One -
Two
Three
Four
Hint
43). Which of the following instruction in the RISC type processor access memory location?
LOAD instruction
STORE instruction
Transfer instruction
Both a and b -
Hint
44). RISC type processor contains ______ number of processors.
Many -
Few
Hint
45). RISC type processor contains _______ number of transistors.
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Large
Few -
Hint
46). CISC type processor is designed` to _______ number of instruction per program.
Maximize
Minimize -
Zero
None of the above
Hint
47). What is the function of a compiler?
It translates high-level language into machine code
It translates high-level language into assembly-level language
Both a and b -
It translates low-level language into a high-level language
Hint
48). CISC type processor uses _____ amount of RAM.
Large
Small -
Equal
None of the above
Hint
49). Which of the following is the CISC type processor?
IBM 370/168
VAX 11/780
Allenhouse Institute of Technology (UPTU Code : 505)
Intel 80486 Rooma, Kanpur – 208 008
All the above -
Hint
50). Which of the following are the components of a CISC type processor?
Control unit
Cache
Main memory
All the above -
Hint
51). CISC type processor has ______ type of addressing modes.
Few
One
Various -
Zero
Hint
52). CISC type processor uses _______ number of instructions.
Less
Large -
Zero
None of the above
Hint
53). In a CISC type processor, instruction decoding logic is _______.
Simple
Complex -
Fragile
None of the above
Hint
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54). How many instructions are required to support multiple addressing modes?
Rooma, Kanpur – 208 008
1-
4
Hint
55). What is the purpose of designing a special processor?
It is designed for special purpose -
It is designed for dual purpose
It is designed to simplify complexity
None of the above
Hint
56). Which of the following are types of special processors?
Math processor
Input-output processor
Transputer
All the above -
Hint
57). Which of the following are the examples of math coprocessor?
8087- used with 8086
80287 used with 80286
80387 used with 80386
All the above -
Hint
58). A coprocessor handles a particular function ____ than a microprocessor.
Slower
Faster -
Allenhouse Institute of Technology (UPTU Code : 505)
Moderate Rooma, Kanpur – 208 008
Any of the above
Hint
59). Which of the following are the examples of input/output processors?
DMA processor
Keyboard/ mouse controller
Graphic display controller
All the above -
Hint
60). DMA stands for?
Direct memory access -
Direction memory access
Dictate memory accumulator
None of the above
Hint
Microprocessor Interview Questions & Answers
61). Which of the following is the special feature of the IO processor?
It has its own local memory
It controls I/O devices with min CPU involvement
Both a and b -
None of the above
Hint
62). The word transputer is also called _______.
Transistor computer -
Transact computer
Transistor component
None of the above
Allenhouse Institute of Technology (UPTU Code : 505)
Hint
Rooma, Kanpur – 208 008
63). A transputer has ________ memory.
Own local -
External
Both a and b
Any of the above
Hint
64). A transputer was designed in ________ year.
1980 -
1979
1890
1888
Hint
65). Which of the following statement matches the transputer?
It is used as a single processor
It connects to external links
It improves performance
All the above -
Hint
66). Which of the following are the examples of transputers?
16bit T212
32 bit T425
T800
All the above -
Hint
67). DSP in DSP processor stands for ________.
Digital signal processor -
Allenhouse Institute of Technology (UPTU Code : 505)
Digital sign processor Rooma, Kanpur – 208 008
Digital signal pin
None of the above
Hint
68). DSP processor processes _________.
Analog signal to digital signal -
Digital signal to analog signal
Analog signal to analog signal
Digital signal to digital signal
Hint
69). ADC process in a DSP processor is done by _______.
Voltage level sampling at periodic intervals of time and converting this voltage level at that instant into
digital form -
Voltage level sampling at aperiodic intervals of time and converting this voltage level at that instant into
digital form
Voltage level sampling at periodic intervals of time and converting current level at that instant into digital
form
None of the above
Hint
70). Which of the following are the components of the DSP processor?
Program memory
Data memory
Compute engine
All the above -
Hint
71). What is the purpose of program memory in a DSP processor?
It records the programs
It will use stored programs to process data
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Both a and b - Rooma, Kanpur – 208 008
None of the above
Hint
72). What is the purpose of data memory in a DSP processor?
It stores information to be processed -
It will use stored programs to process data
Both a and b
None of the above
Hint
73). What is the purpose of compute engine in a DSP processor?
It performs math operation -
It will use stored programs to process data
Both a and b
None of the above
Hint
74). What is the purpose of input/output in a DSP processor?
It communicates with the external world -
It will use stored programs to process data
Both a and b
None of the above
Hint
75). Which of the following are the applications of DSP processors?
AV compression
2D / 3D graphics acceleration
Music synthesis
All the above -
Hint
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76). Which of the following are the examples of DSP processor?
Rooma, Kanpur – 208 008
TMS 320C40
TMS320C50
Both a and b -
None of the above
Hint
77). Which of the following is a microprocessor?
8085
8086
8051
Both a and b -
Hint
78). 8085 is a ______ bit microprocessor.
8 bit -
16 bit
32 bit
All the above
Hint
Read more about 8085 Microprocessor.
79). 8085 is designed by ________.
Intel -
ADM
Microsoft
None of the above
Hint
80). 8085 microprocessor has ________ bits of data bus.
8 bits -
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16 bits Rooma, Kanpur – 208 008
32 bits
48 bits
Hint
81). 8085 microprocessor has _____ bits of address bus?
8 bits
16 bits -
32 bits
48 bits
Hint
82). 8085 microprocessor has ________ bits of program counter.
8 bits
16 bits -
32 bits
48 bits
Hint
83). 8085 microprocessor has ______ bits of stack pointer.
8 bits
16 bits -
32 bits
48 bits
Hint
84). 8085 microprocessor has six _______ bits of registers.
8 bits-
16 bits
32 bits
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48 bits Rooma, Kanpur – 208 008
Hint
85). Which of the following are the register pair in the 8085 microprocessor?
BC
DE
HL
All the above -
Hint
86). Which of the following are the applications of the 8085 processor?
Washing machine
Ovens
Mobiles
All the above -
Hint
87). Which of the following are the functional units of the 8085 processor?
Accumulator
ALU
General purpose register
All the above -
Hint
88). What is the purpose of temporary registers in 8085?
It holds the data
It retrieves the data
It captures the data
It holds data on a temporary basis -
Hint
89). How many flipflops are there in a flag register of 8085.
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4 Rooma, Kanpur – 208 008
5-
7
Hint
Read more about Flip-Flops.
90). Which of the following are control signals of the 8085 processor?
READY, RD, WR, ALE -
S0, S1, IO/M
HOLD, HLDA
RESET
Hint
Microprocessor Exam Questions & Answers
91). Which of the following are status signals of the 8085 processor?
READY, RD, WR, ALE
S0, S1, IO/M -
HOLD, HLDA
RESET
Hint
92). Which of the following are DMA signals of the 8085 processor?
READY, RD, WR, ALE
S0, S1, IO/M
HOLD, HLDA -
RESET
Hint
93). Which of the following are RESET signals of the 8085 processor?
READY, RD, WR, ALE
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S0, S1, IO/M Rooma, Kanpur – 208 008
HOLD, HLDA
RESET IN, RESET OUT -
Hint
94). What is the function of the RESET IN signal?
It resets input function -
It resets output function
It resets both input and output function
None of the above
Hint
95). What is the function of the RESET OUT signal?
It resets input function
It resets output function -
It resets both input and output function
None of the above
Hint
96). Which of the following are interrupt signals in the 8085 processor?
INTR
RST 7.5
RST 6.5
All the above -
Hint
97). What is the purpose of serial input/output control?
It controls serial data communication -
It controls parallel data communication
Both a and b
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None of the above Rooma, Kanpur – 208 008
Hint
98). Data bus in 8085 is _______ directional.
Unidirectional
Bi-directional -
Tri directional
Multi-directional
Hint
99). Data bus in 8085 is used for ______.
Storing data -
Carrying data
Manipulating data
None of the above
Hint
100). Address bus in 8085 is used for _________.
Storing data
Holds the location of data address -
Manipulating data
None of the above
Hint
101). 8086 microprocessor supports _____ bits of ALU.
4 bit ALU
8 bit ALU
16 bit ALU
32 bit ALU -
Hint
102). Which of the following are the types of registers in the 8086 microprocessor?
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General-purpose registers Rooma, Kanpur – 208 008
Segment registers
All of the above -
None
Hint
103). 8086 can operate in ______ modes.
2-
4
Hint
104). Name the modes in which 8086 performs operations.
Minimum mode and maximum mode -
Maximum mode
Minimum mode
Operating mode
Hint
105). How much power supply does 8086 need to perform operations?
4v
3v
2v
+ 5v -
Hint
106). What is the full form of HMOS?
High-Speed Metal Oxide Semiconductor -
High speed metal
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High speed oxides Rooma, Kanpur – 208 008
None
Hint
107). 8086 uses ______ channel HMOS microprocessor.
P-channel
N- Channel -
Both a and b
None
Hint
108). What are the different types of flags in 8086?
Status flag and control flag
Directional flag, interrupt flag, trap flag
Auxiliary carry flag, overflow flag, Parity flag, Sign flag Zero flag,
All of the above -
Hint
109). What is a bidirectional data bus?
Data flow in both directions -
Data flow in one direction
Data flow in multiple directions
None
Hint
110). What is the size of the address bus and data bus in the 8086 processor?
16bits
20bits
Both a and b -
None
Hint
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111). What is the use of addressing mode in 8086 microprocessor?
Rooma, Kanpur – 208 008
To calculate the operands effective memory address -
To calculate the address of an operand
To calculate the direct address of an operand
None
Hint
112 ). Which type of package of 8086 microprocessor?
Dual inline package -
Single line package
Multithreaded package
All of the above
Hint
113). What is the use of zero flags in the 8086 microprocessor?
The function of zero flags in the 8086 microprocessor is to check the result of the bitwise logical operation
Use to check the result of arithmetic operation
Use to check the result of bitwise logical operation
Both a and b
None
Hint
114). Does the 8086 processor has multiplication and division instructions?
8086 have both multiplication and division instructions
No
Only multiplication
Both multiplication and division instructions
Only Division
Hint
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115). What are the operating frequencies of the 8086 microprocessor?
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8086 microprocessor operates 5 MHz, 8MHZ, 10MHZ
5 MHz
8 MHz
10 MHz
All of the above
Hint
116). Which type of technology used in the manufacturing of the 8086 microprocessor?
HMOS technology is used in the manufacturing of 8086 microprocessors
HMOS technology
NMOS technology
PMOS technology
Semiconductor technology
Hint
117). What are the characteristics of the flag register in 8086?
A flag register used in 8086 is a special purpose register, with 16 bits, it is changed to 0/ 1 after arithmetic and
logic operation
Special purpose register
16 bit flag register
Flag bit changed to 0/ 1 after arithmetic and logic operation
All the above
Hint
118). Zero flag is a ______ bit flag of 8086 processor.
1 bit
3 bit Zero flag is a 1-bit flag of 8086 processo
6 bit
16bit
Hint
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119). What is the purpose of zero flags in the 8086 processor?
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Checks the arithmetic operation
Checks the logical operation The purpose of zero flags in the 8086 processor is to check
arithmetic operations and include bitwise logical instruction
Includes bitwise logical instructions
Both a and c
Hint
120). 8086 is a _________.
Microprocessor
Microcontroller 8086 is a microprocessor
Both a and b
None
Hint
121). 8051 is a ________.
Microprocessor Hint8051 is a microcontroller.
Microcontroller
Both a and b
None
Hint
Marks : 0/20
Total number of questions : 20
Number of answered questions : 1
Number of unanswered questions : 19
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Test Review : View answers and explanation for this test.
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1. Which of the following is not a key word in C?
A. pop
B. for
C. if
D. union
Your Answer: Option D
Correct Answer: Option A
Explanation:
pop is not a keyword in C.
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2. A computer program is used to read M and print the sum 2 + 4 + 6 + 8 +.........+ 2M. If M = 9 , the print out will
show the number
A. 9
B. 18
C. 90
D. 100
Your Answer: Option (Not Answered)
Correct Answer: Option C
Explanation:
SUM = 2 + 4 + 6 + 8 + 10 + 12 + 14 + 16 + 18 = 90.
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3. Consider the following statements about an array in Pascal
1. An array has a fixed predetermined number of components.
2. Any component of an array can be accessed using an index.
3. An array variable name refers to a group of quantities by a single name.
4. When array variables are used an appropriate declaration is required.
Which of the above are correct?
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A. All Rooma, Kanpur – 208 008
B. 1, 2, 3 only
C. 2, 3, 4 only
D. 1, 2 and 4 only
Your Answer: Option (Not Answered)
Correct Answer: Option A
Explanation:
All are true.
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4. If F = 95.0 what will be the result of following FORTRAN 77 program?
REAL F , C
READ * , F
C = (5. / 9.) * (F - 32.)
A. 35.0
B. 35
C. 25.0
D. 25
Your Answer: Option (Not Answered)
Correct Answer: Option A
Explanation:
(95 - 32) and decimal must be added.
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5. Consider the following expressions in Java
int a, b, c,
a = 40;
b = a++ ;
c = ++a ;
Now the values of a, b, c are
A. 42, 40, 42 respectively
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B. 42, 42, 42 respectively Rooma, Kanpur – 208 008
C. 40, 42, 42 respectively
D. 40, 40, 42 respectively
Your Answer: Option (Not Answered)
Correct Answer: Option A
Explanation:
The steps are : a is given the value 40, b is given the value of a before it is incremented (i.e., 40) and a is
incremented to 41, a is incremented to 42 and c is given this value. Thus the result is 42, 40, 42.
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6. The number of primitive string operations in 8086 is
A. 3
B. 4
C. 5
D. 6
Your Answer: Option (Not Answered)
Correct Answer: Option C
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7. The standard FORTRAN exponential form of decimal number - 0.000000023 is
A. 2.3 E - 8
B. -2.3 E - 8
C. 2.3 E - 7
D. -2.3 E - 7
Your Answer: Option (Not Answered)
Correct Answer: Option B
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Which of the following methods does not cause any reduction in instruction length?
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A. Using program counter Rooma, Kanpur – 208 008
B. Common source and destination address
C. Implicit source and destination address
8.
D. Machine language programming
Your Answer: Option (Not Answered)
Correct Answer: Option D
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9. Assertion (A): In C arithmetic operations are pemiissible on ints, floats and chars.
Reason (R): In C every arithmetic operator must be written explicitly.
A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is correct R is wrong
D. A is wrong R is correct
Your Answer: Option (Not Answered)
Correct Answer: Option B
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10. Assertion (A): In microprocessor 8085 instruction LXIB, 90 FF H means register B and C are loaded with
upper and lower bytes to get B = 90 H and C = FFH.
Reason (R): In 8085 the stack pointer indicates which memory location is to accessed.
A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is correct R is wrong
D. A is wrong R is correct
Your Answer: Option (Not Answered)
Correct Answer: Option B
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11. The initial contents of ACC and CY in 8085 are
1. CY = 1
2. ACC = 10000001
After instruction RAL is executed once the contents of CY and ACC respectively will be
A. 1 and 00000011
B. 0 and 00000011
C. 1 and 00000001
D. 0 and 00000001
Your Answer: Option (Not Answered)
Correct Answer: Option A
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12. The word size accessible at a time from the memory subsystem depends on
A. width of data bus
B. width of address bus
C. width of control bus
D. both (b) and (c)
Your Answer: Option (Not Answered)
Correct Answer: Option A
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13. 8085 data bus has 8 lines and is bidirectional.
A. True
B. False
Your Answer: Option (Not Answered)
Correct Answer: Option A
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A PC has typically
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A. 5 to 10 KB of main memory Rooma, Kanpur – 208 008
B. 10 to 100 KB of main memory
C. 100 to 256 KB of main memory
14.
D. 256 KB to 1 MB of main memory
Your Answer: Option (Not Answered)
Correct Answer: Option D
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15. RAM is a volatile memory device.
A. True
B. False
Your Answer: Option (Not Answered)
Correct Answer: Option A
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16. Read the following statement
1. Multi-processing operation permits highly efficient parallel processing at several levels.
2. Multi processing involves use of several processing units jointly on a common program and severally on
different programs.
3. In multi-processing the assignment of facilities to tasks, loading of programs and monitoring of I/O activity is
taken care of by operating system.
Which of the above are correct?
A. All
B. 1 and 2 only
C. 1 and 3 only
D. 2 and 3 only
Your Answer: Option (Not Answered)
Correct Answer: Option A
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17. Which memory has read operation, byte erase, byte write and chip erase?
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A. RAM
B. UVEPROM
C. EEPROM
D. both (b) and (c)
Your Answer: Option (Not Answered)
Correct Answer: Option C
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18. Assertion (A): Structures are useful in DBMS.
Reason (R): Structures are very large numbers of applications besides DBMS.
A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is correct R is wrong
D. A is wrong R is correct
Your Answer: Option (Not Answered)
Correct Answer: Option B
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19. The use of microprocessor control in automobiles results in
A. improved fuel economy
B. improved car control
C. advanced information system for driver
D. all of the above
Your Answer: Option (Not Answered)
Correct Answer: Option D
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20. In a typical microcomputer data transfer takes place between
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A. μP and memory
B. μP and I/O devices
C. memory and I/O devices
D. all of the above
Your Answer: Option (Not Answered)
Correct Answer: Option D
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Microprocessor: 8085
Multiple Choice Questions and Answers:-
1) Which is the microprocessor comprises:
a.Register section
b.One or more ALU
c.Control unit
d.All of these
Answer:D
2) What is the store by register?
a.data
b.operands
c.memory
d.None of these
Answer:A
3) Accumulator based microprocessor example are:
a.Intel 8085
b.Motorola 6809
c.A and B
d.None of these
Answer:C
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4) A set of register which contain are:
a.data Rooma, Kanpur – 208 008
b.memory addresses
c.result
d.all of these
Answer:D
5) There are primarily two types of register:
a.general purpose register
b.dedicated register
c.A and B
d.none of these
Answer:C
6) Name of typical dedicated register is:
a.PC
b.IR
c.SP
d.All of these
Answer:D
7) BCD stands for:
a.Binary coded decimal
b.Binary coded decoded
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c.Both a & b
d.none of these Rooma, Kanpur – 208 008
Answer:A
8) Which is used to store critical pieces of data during subroutines and interrupts:
a.Stack
b.Queue
c.Accumulator
d.Data register
Answer:A
9) The data in the stack is called:
a.Pushing data
b.Pushed
c.Pulling
d.None of these
Answer:A
10) The external system bus architecture is created using from ______ architecture:
a.Pascal
b.Dennis Ritchie
c.Charles Babbage
d.Von Neumann
Answer:D
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11) The processor 80386/80486 and the Pentium processor uses _____ bits address bus:
a.16 Rooma, Kanpur – 208 008
b.32
c.36
d.64
Answer:B
12) Which is not the control bus signal:
a.READ
b.WRITE
c.RESET
d.None of these
Answer:C
13) PROM stands for:
a.Programmable read-only memory
b.Programmable read write memory
c.Programmer read and write memory
d.None of these
Answer:A
14) EPROM stands for:
a.Erasable Programmable read-only memory
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b.ectrically Programmable read write memory
c.Electrically Programmable read-only memory Rooma, Kanpur – 208 008
d.None of these
Answer:A
15) Each memory location has:
a.Address
b.Contents
c.Both A and B
d.None of these
Answer:C
16) Which is the type of microcomputer memory:
a.Processor memory
b.Primary memory
c.Secondary memory
d.All of these
Answer:D
17) Secondary memory can store____:
a.Program store code
b.Compiler
c.Operating system
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d.All of these
Answer:D Rooma, Kanpur – 208 008
18) Secondary memory is also called____:
a.Auxiliary
b.Backup store
c.Both A and B
d.None of these
Answer:C
19 Customized ROMS are called:
a.Mask ROM
b.Flash ROM
c.EPROM
d.None of these
Answer:A
20) The RAM which is created using bipolar transistors is called:
a.Dynamic RAM
b.Static RAM
c.Permanent RAM
d.DDR RAM
Answer:B
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21) Which type of RAM needs regular referred:
a.Dynamic RAM Rooma, Kanpur – 208 008
b.Static RAM
c.Permanent RAM
d.SD RAM
Answer:A
22) Which RAM is created using MOS transistors:
a.Dynamic RAM
b.Static RAM
c.Permanent RAM
d.SD RAM
Answer:A
23) A microprocessor retries instructions from :
a.Control memory
b.Cache memory
c.Main memory
d.Virtual memory
Answer:C
24) The lower red curvy arrow show that CPU places the address extracted from the memory
location on the_____:
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a.Address bus
b.System bus Rooma, Kanpur – 208 008
c.Control bus
d.Data bus
Answer:A
25) The CPU sends out a ____ signal to indicate that valid data is available on the data bus:
a.Read
b.Write
c.Both A and B
d.None of these
Answer:B
26) The CPU removes the ___ signal to complete the memory write operation:
a.Read
b.Write
c.Both A and B
d.None of these
Answer:A
27) BIU STAND FOR:
a.Bus interface unit
b.Bess interface unit
c.A and B
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d.None of these
Answer:A Rooma, Kanpur – 208 008
28) EU STAND FOR:
a.Execution unit
b.Execute unit
c.Exchange unit
d.None of these
Answer:A
29) Which are the four categories of registers:
a.General- purpose register
b.Pointer or index registers
c.Segment registers
d.Other register
e.All of these
Answer:E
30) Eight of the register are known as:
a.General- purpose register
b.Pointer or index registers
c.Segment registers
d.Other register
Answer:A
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31) The four index register can be used for:
a.Arithmetic operation Rooma, Kanpur – 208 008
b.Multipulation operation
c.Subtraction operation
d.All of these
Answer:A
32) IP Stand for:
a.Instruction pointer
b.Instruction purpose
c.Instruction paints
d.None of these
Answer:A
33) CS Stand for:
a.Code segment
b.Coot segment
c.Cost segment
d.Counter segment
Answer:A
34) DS Stand for:
a.Data segment
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b.Direct segment
c.Declare segment Rooma, Kanpur – 208 008
d.Divide segment
Answer:A
35) Which are the segment:
a.CS: Code segment
b.DS: data segment
c.SS: Stack segment
d.ES:extra segment
e.All of these
Answer:D
36) The acculatator is 16 bit wide and is called:
a.AX
b.AH
c.AL
d.DL
Answer:A
37) How many bits the instruction pointer is wide:
a.16 bit
b.32 bit
c.64 bit
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d.128 bit
Answer:A Rooma, Kanpur – 208 008
38) How many type of addressing in memory:
a.Logical address
b.Physical address
c.Both A and B
d.None of these
Answer:C
39) The size of each segment in 8086 is:
a.64 kb
b.24 kb
c.50 kb
d.16kb
Answer:A
40) The _______ address of a memory is a 20 bit address for the 8086 microprocessor:
a.Physical
b.Logical
c.Both
d.None of these
Answer:A
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41) The pin configuration of 8086 is available in the________:
a.40 pin Rooma, Kanpur – 208 008
b.50 pin
c.30 pin
d.20 pin
Answer:A
42) DIP stand for:
a.Deal inline package
b.Dual inline package
c.Direct inline package
d.Digital inline package
Answer:B
43) EA stand for:
a.Effective address
b.Electrical address
c.Effect address
d.None of these
Answer:A
44) BP stand for:
a.Bit pointer
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b.Base pointer
c.Bus pointer Rooma, Kanpur – 208 008
d.Byte pointer
Answer:B
45) DI stand for:
a.Destination index
b.Defect index
c.Definition index
d.Delete index
Answer:A
46) SI stand for:
a.Stand index
b.Source index
c.Segment index
d.Simple index
Answer:B
47) ALE stand for:
a.Address latch enable
b.Address light enable
c.Address lower enable
d.Address last enable
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Answer:A
48) NMI stand for: Rooma, Kanpur – 208 008
a.Non mask able interrupt
b.Non mistake interrupt
c.Both
d.None of these
Answer:A
49) ________ is the most important segment and it contains the actual assembly language
instruction to be executed by the microprocessor:
a.Data segment
b.Code segment
c.Stack segment
d.Extra segment
Answer:B
50) The offset of a particular segment varies from _________:
a.000H to FFFH
b.0000H to FFFFH
c.00H to FFH
d.00000H to FFFFFH
Answer:B
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51) Which are the factor of cache memory:
a.Architecture of the microprocessor Rooma, Kanpur – 208 008
b.Properties of the programs being executed
c.Size organization of the cache
d.All of these
Answer:D
52) ________ is usually the first level of memory access by the microprocessor:
a.Cache memory
b.Data memory
c.Main memory
d.All of these
Answer:A
53) Which is the small amount of high- speed memory used to work directly with the
microprocessor:
a.Cache
b.Case
c.Cost
d.Coos
Answer:A
54) The cache usually gets its data from the_________ whenever the instruction or data is
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required by the CPU:
a.Main memory Rooma, Kanpur – 208 008
b.Case memory
c.Cache memory
d.All of these
Answer:A
55) Microprocessor reference that are available in the cache are called______:
a.Cache hits
b.Cache line
c.Cache memory
d.All of these
Answer:A
56) Microprocessor reference that are not available in the cache are called_________:
a.Cache hits
b.Cache line
c.Cache misses
d.Cache memory
Answer:C
57) Which causes the microprocessor to immediately terminate its present activity:
a.RESET signal
b.INTERUPT signal
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c.Both
d.None of these Rooma, Kanpur – 208 008
Answer:A
58) Which is responsible for all the outside world communication by the microprocessor:
a.BIU
b.PIU
c.TIU
d.LIU
Answer:A
59) INTR: it implies the__________ signal:
a.INTRRUPT REQUEST
b.INTRRUPT RIGHT
c.INTRRUPT RONGH
d.INTRRUPT RESET
Answer:A
60) Which of the following are the two main components of the CPU?
a.Control Unit and Registers
b.Registers and Main Memory
c.Control unit and ALU
d.ALU and bus
Answer:C
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61) Different components n the motherboard of a PC unit are linked together by sets of parallel
Rooma, Kanpur – 208 008
electrical conducting lines. What are these lines called?
a.Conductors
b.Buses
c.Connectors
d.Consecutives
Answer:B
62) The language that the computer can understand and execute is called
a.Machine language
b.Application software
c.System program
d.All of the above
Answer:A
63) Which of the following is used as a primary storage device?
a.Magnetic drum
b.PROM
c.Floppy disk
d.All of these
Answer:B
64) Which of the following memories needs refresh?
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a.SRAM
b.DRAM Rooma, Kanpur – 208 008
c.ROM
d.All of above
Answer:B
65) The memory which is programmed at the time it is manufactured
a.PROM
b.RAM
c.PROM
d.EPROM
Answer:A
66) Which of the following memory medium is not used as main memory system?
a.Magnetic core
b.Semiconductor
c.Magnetic tape
d.Both a and b
Answer:C
67) Registers, which are partially visible to users and used to hold conditional, are known as
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a.PC
b.Memory address registers Rooma, Kanpur – 208 008
c.General purpose register
d.Flags
Answer:C
68) One of the main feature that distinguish microprocessors from micro-computers is
a.Words are usually larger in microprocessors
b.Words are shorter in microprocessors
c.Microprocessor does not contain I/O devices
d.Exactly the same as the machine cycle time
Answer:C
69) The first microprocessor built by the Intel Corporation was called
a.8008
b.8080
c.4004
d.8800
Answer:C
70) An integrated circuit is
a.A complicated circuit
b.An integrating device
c.Much costlier than a single transistor
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d.Fabricated on a tiny silicon chip
Answer:D Rooma, Kanpur – 208 008
71) Most important advantage of an IC is its
a.Easy replacement in case of circuit failure
b.Extremely high reliability
c.Reduced cost
d.Low powers consumption
Answer:B
72) Which of the following items are examples of storage devices?
a.Floppy / hard disks
b.CD-ROMs
c.Tape devices
d.All of the above
Answer:D
73) The Width of a processor’s data path is measured in bits. Which of the following are common
data paths?
a.8 bits
b.12 bits
c.16 bits
d.32 bits
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Answer:A
74) Which is the type of memory for information that Rooma,
doesKanpur – 208 008
not change on your computer?
a.RAM
b.ROM
c.ERAM
d.RW / RAM
Answer:B
75) What type of memory is not directly addressable by the CPU and requires special softw3are
called EMS (expanded memory specification)?
a.Extended
b.Expanded
c.Base
d.Conventional
Answer:B
76) Before a disk can be used to store data. It must be…….
a.Formatted
b.Reformatted
c.Addressed
d.None of the above
Answer:A
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77) Which company is the biggest player in the microprocessor industry?
a.Motorola Rooma, Kanpur – 208 008
b.IBM
c.Intel
d.AMD
Answer:C
78) A typical personal computer used for business purposes would have… of RAM.
a.4 KB
b.16 K
c.64 K
d.256 K
Answer:D
78) The word length of a computer is measured in
a.Bytes
b.Millimeters
c.Meters
d.Bits
Answer:D
79) What are the three decisions making operations performed by the ALU of a computer?
a.Grater than
b.Less than
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c.Equal to
d.All of the above Rooma, Kanpur – 208 008
Answer:D
80) Which part of the computer is used for calculating and comparing?
a.Disk unit
b.Control unit
c.ALU
d.Modem
Answer:C
81) Can you tell what passes into and out from the computer via its ports?
a.Data
b.Bytes
c.Graphics
d.Pictures
Answer:A
82) What is the responsibility of the logical unit in the CPU of a computer?
a.To produce result
b.To compare numbers
c.To control flow of information
d.To do math’s works
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Answer:B
Rooma,
83) The secondary storage devices can only store data Kanpurcannot
but they – 208 008
perform
a.Arithmetic Operation
b.Logic operation
c.Fetch operations
d.Either of the above
Answer:D
84) Which of the following memories allows simultaneous read and write operations?
a.ROM
b.RAM
c.EPROM
d.None of above
Answer:B
85) Which of the following memories has the shortest access times?
a.Cache memory
b.Magnetic bubble memory
c.Magnetic core memory
d.RAM
Answer:A
86) A 32 bit microprocessor has the word length equal to
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a.2 byte
b.32 byte Rooma, Kanpur – 208 008
c.4 byte
d.8 byte
Answer:C
87) An error in computer data is called
a.Chip
b.Bug
c.CPU
d.Storage device
Answer:B
88) The silicon chips used for data processing are called
a.RAM chips
b.ROM chips
c.Micro processors
d.PROM chips
Answer:D
89) The metal disks, which are permanently housed in, sealed and contamination free containers
are called
a.Hard disks
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b.Floppy disk
c.Winchester disk Rooma, Kanpur – 208 008
d.Flexible disk
Answer:C
90) A computer consists of
a.A central processing unit
b.A memory
c.Input and output unit
d.All of the above
Answer:D
91) The instructions for starting the computer are house on
a.Random access memory
b.CD-Rom
c.Read only memory chip
d.All of above
Answer:C
92) The ALU of a computer normally contains a number of high speed storage element called
a.Semiconductor memory
b.Registers
c.Hard disks
d.Magnetic disk
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Answer:B
93) The first digital computer built with IC chips wasRooma,
knownKanpur
as – 208 008
a.IBM 7090
b.Apple – 1
c.IBM System / 360
d.VAX-10
Answer:C
94) Which of the following terms is the most closely related to main memory?
a.Non volatile
b.Permanent
c.Control unit
d.Temporary
Answer:D
95) Which of the following is used for manufacturing chips?
a.Control bus
b.Control unit
c.Parity unit
d.Semiconductor
Answer:D
96) To locate a data item for storage is
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a.Field
b.Feed Rooma, Kanpur – 208 008
c.Database
d.Fetch
Answer:D
97) A directly accessible appointment calendar is feature of a … resident package
a.CPU
b.Memory
c.Buffer
d.ALU
Answer:B
98) The term gigabyte refers to
a.1024 bytes
b.1024 kilobytes
c.1024 megabytes
d.1024 gigabyte
Answer:C
99) A/n …. Device is any device that provides information, which is sent to the CPU
a.Input
b.Output
c.CPU
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d.Memory
Answer:A Rooma, Kanpur – 208 008
100) Current SIMMs have either … or … connectors (pins)
a.9 or 32
b.30 or 70
c.28 or 72
d.30 or 72
Answer:D
Microprocessor 8085 MCQ Questions and Answers for preparation of MCA, BCA and other IT
examinations of various Institutions.
Microprocessor 8085 MCQ Questions and Answers
1) A microprocessor is the heart of the microcomputer.
a) Receiving input
b) Performing computations.
c) Storing data & instructions
d) All of the above.
2) A device, which enables a microcomputer to perform the first of the above-mentioned tasks is
known as the input device.
a) Keyboard
b) Mouse
c) Toggle
d) All of the above.
3) The task of displaying the result computed by the microprocessor is performed by an output
device, some of the commonly used output device.
a) Cathode Ray Tube(CRT)
b) Light-Emitting diodes(LED’S)
c) Laser printer
d) All of the above.
4) n instruction essentially consists of an
a) Operation code
b) Address of the data
c) Instruction operates
d) None of the above.
5) The 8085A has interrupt pins:-
a) TRAP, RST7.5
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b) RST6.5, RST5.5
Rooma, Kanpur – 208 008
c) TNTR(pin 10)
d) All of the above.
6) 8085A has 8 unidirectional signal lines:-
a) MSB
b) HOLD,HALT
c) RESET mode
d) None of the above.
7) Every microprocessor is provided with a set of registers :
a) Temporary storage
b) Instruction Execution
c) All of these
d) None of the above.
8) Registers available for the temporary storage of operands or address affects the following:-
a) Memory space occupied by the program.
b) Time of execution of the program.
c) Ease of programming.
d) All of the above.
9) The registers available to the user can be further classified into:-
a) General purpose register
b) Special-purpose register
c) None of these
d) All of the above.
10) In the 8085A microprocessor, the data size is 8-bit and the address size is 16-bit.
a) B-C pair
b) D-E pair
c) H-L pair
d) All of the above.
11) Set of registers provided for some special applications.
a) Accumulator
b) Memory space
c) All of the above
d) None of the above.
12) A microprocessor to execute a program, the CPU has to do the following operations:
a) Fetch the opcode
b) Read a memory location for the data.
c) Perform the required operation
d) All of the above.
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13) An instruction cycle can be defined as the sum of an instruction fetch time and the instruction
Rooma, Kanpur – 208 008
execution time.
a) Instruction cycle=Instruction fetch + Instruction execute.
b) Memory location and deposited in the CPU’s
c) Both of these
d) None of the above.
14) 8085 has 5 addressing mode and are:-
a) Immediate, inherent
b) Direct
c) Register and register indirect
d) All of the above.
30) The part of 8255 can be programmed for any other mode by writing a single control word into
the
a) Port
b) Control Logic
c) Set/Reset
d) Register.
16) One of the following addressing modes is not possible in 8085.
a) Indexed addressing
b) Indirect addressing
c) Direct addressing
d) Indirect register address.
17) 8085 has
a) One 16-bit register
b) Two 16-bit register
c) Three 16-bit register
d) Four 16-bit register.
18) The speed of a microprocessor is usually measured by the
a) Microprocessor’s throughput.
b) Speed with which it performs I/P and O/P operations.
c) Time required to execute basic instruction.
d) Time required to process a small operation.
19) Interrupts can be generally classified :
a) Hardware interrupts
b) Software interrupts
c) Both of above
d) All of the above.
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20) 8085 microprocessor has 5 hardware interrupts :
Rooma, Kanpur – 208 008
a) TRAP, RST6.5
b) RST7.5, RST5.5
c) INTR
d) None of the above.
21) The data which a microprocessor needs to process, comes from devices such as a keyboard.
a) Switch
b) Analog-to-digital
c) Digital-to-analog
d) All of the above.
22) The 8085 can respond to four externally initiated operation.
a) Reset, Interrupt b) Ready hold c) Memory-mapped I/O d) Memory chip
a) c, d, both
b) a, b, both
c) None of the above.
d) All of the above
23) To interconnect peripherals with the 8085 MPU, additional logic circuit, called interfacing devices.
These circuits include a device such as
a) buffer
b) Decoder
c) Encoder, latches
d) All of the above.
24) The 8085 flag register has five flags.
1) Carry flag, Sign flag 2) Zero flag, Parity flag 3) Auxilliary Carry
a) 1, 2 both
b) 1, 3 both
c) 2, 3 both
d) All of the above.
25) Counters and time delays can be designed using.
a) Software
b) CPI
c) Instruction
d) All of the above.
26) The 8085 code can be assembled by using a program called a :
a) Cross-assembler
b) Cross-compiler
c) Cross-interpret
d) All of the above.
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27) The 8085 microprocessor has two pins available for I/O communication.
Rooma, Kanpur – 208 008
(1) HOLD, HOLDA (2) HOLDAB, HOLDB
a) 1, 2 both
b) 1 only
c) 2 only.
d) All of these
28) The ___ is a program that allows then used to test and debug the object file.
a) Assembler
b) Loader
c) Debugger
d) None of the above.
29) It is a program that takes the object file generated by the assembler program.
a) Loading
b) Loader
c) Debugger
d) All of the above.
30) Intel’s 8086 and 80286, Motorola’s M 68000 and Zilog’s Z8000 are some of the most powerful-
16-bit microprocessor are not available today. (T/F)
Ans. False
31) A microprocessor is a multipurpose, programmable, clock driven, register-based electronic
device. (T/F)
Ans. True
32) Read instructions from a storage device called memory. (T/F)
Ans. False
33) A typical programmable machine can be represented with 4 component: microprocessor,
memory, Input/Output device, application. (T/F)
Ans. False
34) The physical components of this system are called the hardware. (T/F)
Ans. True
35) A set of instructions written for the microprocessor to perform a task is called an application.
(T/F)
Ans. False
37) The microprocessor applications are classified primarily into 3 categories: re-programmable
system and embedded system. (T/F)
Ans. True
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38) The first microprocessor was introduced by Intel Corporation in 1971. (T/F)
Rooma, Kanpur – 208 008
Ans. True
39) 4-bit microprocessor (Intel) introduced were ROCKWELL International‘s (PPS4). (T/F)
Ans. True
40) In 8087 ___ executes all the instructions including arithmetic, logical, transcendental, and data
transfer instructions.
A) Arithmetic and logical unit
B) Control Unit
C) Numeric Execution Unit
D) None of the above
41) A group of ___ bits is called byte.
A) 2
B) 4
C) 6
D) 8
42) The single IC which consists of ALU, control section, and register section is called___.
A) Microprocessor
B) Microcontroller
C) Register
D) Computer
43) A system bus which carries, only the control and timing signals then it is called as ____
A) Address bus
B) Data bus
C) Control bus
D) None of the above
44) Physical devices and circuitry of the computer are also known as ___ .
A) Hardware
B) Software
C) System Software
D) Application Software
45) Intel developed first processor 4004 in 1974 which was a ___ bit processor.
A) 1
B) 2
C) 3
D) 4
46) Intel introduced the ___ 16 bit microprocessor in 1978.
A) 8085
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B) 8086
Rooma, Kanpur – 208 008
C) 8080
D) 80386
47) The ____ family was introduced as a part of Intel Centrino Technology.
A) Pentium M
B) Pentium I
C) Pentium II
D) Dual core
48) AMD stand for___
A) Advanced Macro Devices
B) Advanced Micro Devices
C) Analog Macro Devices
D) Analog Micro Devices
49) 16 bit microprocessor has ___ bit data bus and ___ bit address bus.
A) 16, 20
B) 8,16
C) 4, 16
D) 8,20
50) 8086 operates in ___ modes.
A) Four
B) Three
C) Two
D) One
51) BIU Stands for___.
A) Binary Interactive Unit
B) Bus Interactive Unit
C) Bus Interface Unit
D) Binary Interface Unit
52) Assembler is a type of translator that translates ___ language into machine
level language.
A) High Level
B) Assembly level
C) Both A and B
D) None of the above
53) The addressing modes of 8086 can be categorized into ___ categories.
A) One
B) Two
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C) Three
Rooma, Kanpur – 208 008
D) Four
54) In ___ addressing mode the operands are specified in the instruction itself.
A) Immediate
B) Register
C) Direct
D) Indirect
55) ___ instructions are used in such cases when some instructions are needed to be executed
number of times to perform certain tasks.
A) Jump
B) Loop
C) Shift
D) Rotate
56) ___ instruction stops the execution of microprocessor and force microprocessor to enter into wait
state
A) WAIT
B) LOCK
C) ESC(Escape)
D) HALT
57) A series of data byte available in memory at consecutive locations is called as___.
A) Bit String
B) Byte String
C) Word
D) None of these
58) ___loads a byte from a string in memory into AL.
A) LOD SB
B) LOD SW
C) STO SB
D) STO SW
59) CMPS stands for___.
A) Compare string byte
B) Compare string bit
C) Concatenate string byte
D) Concatenate string bit
60) ___ is a Prgrammable Interrupt Controller.
A) 8259A
B) 8086
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C) 8085
Rooma, Kanpur – 208 008
D) 8255
61) ___ is used by 8259 A to Decipher various Commnad Words the CPU writes.
A) INT
B) INTA
C) A0
D) RD
62) The length of a bus cycle in 8086 system is of ___ clock cycles.
A) One
B) Two
C) Three
D) Four
63) PIC stands for___
A) Process Interface Controller
B) Process Interrupt Controller
C) Programmable Interface Controller
D) Pragrammable Interrupt Controller
64) Data bus buffer is a ___ state bidirectional ___ bit buffer that is used to interface 8259A to the
system Data Bus.
A) 3,8
B) 2,8
C) 3,16
D) 2,16
65) RAM is ___ memory.
A) read only
B) Write only
C) Read/write
D) None of the above
66) In ___ cell the capacitor is used to store the charge as a representation of data.
A) Static RAM
B) ROM
C) Dynamic RAM
D) None of the above
67) In context of 8255 BSR stands for___.
A) Bit Set Register
B) Bit-Set Reset
C) Binary Set Register
D) Binary Set-Reset
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68) In 8255-PPI ___ mode is used as two simple 8 bit I/O ports and port C as two 4-bit I/O ports.
Rooma, Kanpur – 208 008
A) Mode 0
B) Mode 1
C) Mode 2
D) Mode 3
69) In displays when small information or data has to be displayed then we can use ___.
A) LED
B) LCD
C) CRT
D) Both A and B
70) There are ___ types of seven segment displays
A) 4
B) 3
C) 2
D) 1
71) IC 7447 is used as BCD to 7 segment decoder.
A) True
B) False
72) ___ is an Intel’s general purpose keyboard display controller.
A) 8255
B) 8279
C) 8085
D) 8088
73) ___ is a programmable interval timer/counter designed for use with Intel Microprocessor system.
A) 8255
B) 8279
C) 8251
D) 8254
74) 8254 has powerful READ BACK command which allows the user to check the count value,
programmed mode, current mode and current status of counter
A) True
B) False
75) USART stands for ___
A) Universal Synchronous Asynchronous Receiver Transmitter
B) Universal Standard Analog Receiver Transmitter
C) Universal Synchronous Analog Radiator Transmitter
D) Universal Standard Asynchronous Radiator Transmitter
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Rooma, Kanpur – 208 008
Microprocessor and Microcontroller multiple choice questions with answers for IT student who are
preparing for academic and competitive exam
Microprocessor and Microcontroller multiple choice questions with answers
1. A computer accepts data from the user processes the data according to the instructions given and
produces the desired output result. (True /False)
Ans. True
2. RAM stands for ___.
Ans. Random Access Memory
3. A single IC which consists of ALU, control section and Register section is called ___.
Ans. Microprocessor
4. What is the name of the system which carries only the control and timing signals?
Ans. Control bus
5. The physical components of the computer are called ___.
Ans. Hardware
6. System Software is suited for specific applications. (True/False)
Ans. False
7. Machine language can be directly understood and executed by a machine and it is the language of
0s and 1s. (True/False)
Ans. True
8. The various ways of specifying the data is called ___.
Ans. Addressing mode
9. An operating system is a software component that acts as the ___ of a computer system.
Ans. Core
10. ___ performs parallel processing.
Ans. Supercomputer
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11. The ___ computers are specially used as servers on the World Wide Web.
Rooma, Kanpur – 208 008
Ans. Mainframe
12. PDA stands for ___.
Ans. Personal Digital Assistant
13. SSI stands for ___.
Ans. Small-Scale Integration
14. The 4004 was a ___ bit processor introduced by Intel in the year 1971.
Ans. 4
15. Intel introduced the 16-bit microprocessor 8086 in 1988. (True/False)
Ans. False
16. The ___ processor is the first in a family of the 64-bit microprocessor by Intel introduced in 2001.
Ans. Itanium
17. The original Core brand refers to Intel’s 32-bit mobile dual-core x86 CPUs that derived from the
___ branded processors.
Ans. Pentium M
18. 80286 was introduced in the year ___.
Ans. 1982
19. 80486 is a ___ bit processor.
Ans. 32
20. Intel is considered as the founder of X86 processors. (True/False)
Ans. True
21. MIPS stands for ___.
Ans. Millions of Instructions Per Second
22. AMD stands for ___.
Ans. Advanced Micro Devices
23. 8086 microprocessor has ___ bit data bus and ___ bit address bus.
Ans. 16 bit, 20 bit
24. The prefetched instruction bytes are stored in a first in first out (FIFO) group of registers called an
___ for the Execution Unit.
Ans. Instruction Queue
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25. The ___ input provides the basic timing for processor operation and bus control activity.
Rooma, Kanpur – 208 008
Ans. Clock
26. ___ are the time-multiplexed address and data lines.
Ans. AD0-AD15
27. WR is an active high output signal. (True or False).
Ans. False
28. ___ language can be defined as a pattern of bits.
Ans. Machine
29. An instruction has two fields one is ___ and another is ___.
Ans. Opcode, Operand
30. In 8086 microprocessor we use ___ to give instructions and to write the programs for 8086.
Ans. Assembly level Language
31. Interpreter translates ___ language into machine level language and the translation is done line by
line.
Ans. High level
32. Complier translates high-level language into ___.
Ans. Machine level language
33. ___ enables the programmers to run the program step by step so that the programmer can find
out the exact location of the error.
Ans. Debugger
34. ___ instruction is used to exit debugger.
Ans. QUIT
34. In 8086 microprocessor address and control bus are multiplexed. (True/False)
Ans. False
36. How many processor cycles are there for all the bus cycles?
Ans. Four
37. During which cycle the address is transmitted?
Ans. T1 Cycle
38. In which mode the processor derives the status signals S2, S1 and S0?
Ans. Maximum mode
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39. The addressing modes of 8086 can be categorized into four categories. (True/False)
Rooma, Kanpur – 208 008
Ans. True
40. In ___ addressing mode the operand is specified in the instruction itself.
Ans. Immediate
41. Memory addressing mode can be divide into two groups. They are ___ and ___.
Ans. Direct, indirect
42. In ___ mode the address of the required data is calculated by adding signed or unsigned
displacement to the base registers BX or BP.
Ans. Based addressing with displacement mode
43. In ___ the port address can’t be changed throughout the execution of the program.
Ans. Fixed port addressing mode
44. ___ are the abbreviations used to write assembly language programs.
Ans. Mnemonics
45. The four fields in which the assembly level instruction is divided into are ___, ___, ___ and ___.
Ans. Label, opcode, operand, comments
46. ___ instruction interchanges the contents of two registers.
Ans. XCGH
47. ___ instruction adds the source, destination and also carry to the result.
Ans. ADC
48. ___ instruction performs complement.
Ans. NOT
49. ___ instruction suspends the execution of the microprocessor and it enters into the wait state.
Ans. Wait
50. CALL instruction transfers the control of execution of the program to the subroutine or
procedure. (True/False)
Ans. True
51. The ___ is used to reserve byte or bytes of memory locations in the available memory.
Ans. DB(Define Byte)
52. ___ directive marks the end of an assembly language program.
Ans. END
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53. The string instructions can operate on only a single byte or word unless they are used with the ___
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prefix.
Ans. REP
54. Regardless of the form of the primitive the actual ___ are determined solely by the contents of the
SI, DI, DS, and ES registers.
Ans. Operands
55. LODS instruction affects flags. (True/False).
Ans. False
56. In assembly language the prefix is invoked by placing the appropriate repeat (REP) mnemonic
before the primitive. (True/False)
Ans. True
57. A terminal may communicate with the computer using the EBCDIC alphanumeric code even
though the computer’s software is designed to work with the ASCII code or vice versa. (True/False)
Ans. True
58. The XLAT instruction assumes the base address of the byte array is in the ___ register.
Ans. BX
59. Arithmetic using the ___ format is acceptable if only addition and subtraction are involved.
Ans. packed BCD
60. Branch to a procedure is referred to as the ____, and the corresponding branch back is known as
the ___.
Ans. Call, Return
61. If the attribute is NEAR, the RET instruction will only pop a word into the ___ register.
Ans. IP
62. A macro is unlike a ____ in that the machine instructions are repeated each time the macro is
referenced.
Ans. Procedure
63. ___ requires that each dummy-parameter appearing in the prototype code be preceded by a %
character.
Ans. ASM-86
64. The meaning of ‘interrupts’ is to break the sequence of operation. (True or False)
Ans. True
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65. The process of interrupting the normal program execution to carry out a specific task/work is
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referred to as ___.
Ans. Interrupt
66. The interrupts generated by special instructions are called ___ interrupts.
Ans. software
67. The interrupts initiated by external hardware by sending an appropriate signal to the interrupt pin
of the processor is called ___.
Ans. hardware interrupt
68. In ___ interrupts the interrupting device should supply the address of the ISR to be executed in
response to the interrupt.
Ans. Non-vectored
69. ___ a maskable hardware interrupt.
Ans. INTR
70. NMI stands for___,
Ans. Non maskable interrupt
71. PIC stands for ____.
Ans. Programmable Interrupt Controller
72. Whenever a command is issued with A0=0 and D4=1, this is interpreted as ___.
Ans. Initialization Command Word1
73. OCWs stands for ___.
Ans. Operation Command Words
74. ___ Mode is the default mode of operation of 8259A.
Ans. Fully Nested
75. The 8259A is polled by using software execution by microprocessor instead of the requests on
INT input. (True/False).
Ans. True
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PAPERS RRB-JE Classroom Online & Postal Coaching Call : 9990657855 Multiple choice Questions : RRB-JE Sample Practice
Test Microprocessor and Microcontroller Introduction to microprocessor, 8085 microprocessor working ; Assembly
Language programming ; Peripherals & other Microprocessors ; Microcontrollers Introduction to microprocessor
8085(Working, Hardware, Address) Part-1 1) Which is the microprocessor comprises: a.Register section b.One or more
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ALU c.Control unit d.All of these Ans: D 2) What is the store by register? a.data b.operands c.memory d.None of these
Ans: a 3) Accumulator based microprocessor example Rooma, Kanpur
are: a.Intel – 208
8085 008
b.Motorola 6809 c.A and B d.None of these Ans:
c 4) A set of register which contain are: a.data b.memory addresses c.result d.all of these Ans: D 5) There are primarily
two types of register: a.general purpose register b.dedicated register c.A and B d.none of these Ans: c 6) Name of typical
dedicated register is: a.PC b.IR c.SP d.All of these Ans: D 7) BCD stands for: a.Binary coded decimal b.Binary coded decoded
c.Both a & b d.none of these Ans: a 8) Which is used to store critical pieces of data during subroutines and interrupts:
a.Stack b.Queue c.Accumulator d.Data register Ans: a SAMPLE QUESTION PAPERS RRB-JE Classroom Online & Postal
Coaching Call : 9990657855 9) The data in the stack is called: a.Pushing data b.Pushed c.Pulling d.None of these Ans: a
10) The external system bus architecture is created using from ______ architecture: a.Pascal b.Dennis Ritchie c.Charles
Babbage d.Von Neumann Ans: D 11) The processor 80386/80486 and the Pentium processor uses _____ bits address bus:
a.16 b.32 c.36 d.64 Ans: b 12) Which is not the control bus signal: a.READ b.WRITE c.RESET d.None of these Ans: c 13)
PROM stands for: a.Programmable read-only memory b.Programmable read write memory c.Programmer read and write
memory d.None of these Ans: a 14) EPROM stands for: a.Erasable Programmable read-only memory b.ectrically
Programmable read write memory c.Electrically Programmable read-only memory d.None of these Ans: a 15) Each
memory location has: a.Address b.Contents c.Both A and B d.None of these Ans: c 16) Which is the type of microcomputer
memory: a.Processor memory b.Primary memory c.Secondary memory d.All of these Ans: D 17) Secondary memory can
store____: a.Program store code b.Compiler c.Operating system d.All of these Ans: D 18) Secondary memory is also
called____: a.Auxiliary b.Backup store c.Both A and B d.None of these Ans: c 19 Customized ROMS are called: a.Mask
ROM b.Flash ROM SAMPLE QUESTION PAPERS RRB-JE Classroom Online & Postal Coaching Call : 9990657855 c.EPROM
d.None of these Ans: a 20) The RAM which is created using bipolar transistors is called: a.Dynamic RAM b.Static RAM
c.Permanent RAM d.DDR RAM Ans: b 21) Which type of RAM needs regular referred: a.Dynamic RAM b.Static RAM
c.Permanent RAM d.SD RAM Ans: a 22) Which RAM is created using MOS transistors: a.Dynamic RAM b.Static RAM
c.Permanent RAM d.SD RAM Ans: a 23) A microprocessor retries instructions from : a.Control memory b.Cache memory
c.Main memory d.Virtual memory Ans: c 24) The lower red curvy arrow show that CPU places the address extracted from
the memory location on the_____: a.Address bus b.System bus c.Control bus d.Data bus Ans: a 25) The CPU sends out a
____ signal to indicate that valid data is available on the data bus: a.Read b.Write c.Both A and B d.None of these Ans: b
26) The CPU removes the ___ signal to complete the memory write operation: a.Read b.Write c.Both A and B d.None of
these Ans: a 27) BIU STAND FOR: a.Bus interface unit b.Bess interface unit c.A and B d.None of these Ans: a 28) EU STAND
FOR: a.Execution unit b.Execute unit c.Exchange unit d.None of these Ans: a 29) Which are the four categories of registers:
a.General- purpose register b.Pointer or index registers c.Segment registers d.Other register e.All of these SAMPLE
QUESTION PAPERS RRB-JE Classroom Online & Postal Coaching Call : 9990657855 Answer:E 30) Eight of the register are
known as: a.General- purpose register b.Pointer or index registers c.Segment registers d.Other register Ans: a 31) The
four index register can be used for: a.Arithmetic operation b.Multipulation operation c.Subtraction operation d.All of
these Ans: a 32) IP Stand for: a.Instruction pointer b.Instruction purpose c.Instruction paints d.None of these Ans: a 33)
CS Stand for: a.Code segment b.Coot segment c.Cost segment d.Counter segment Ans: a 34) DS Stand for: a.Data segment
b.Direct segment c.Declare segment d.Divide segment Ans: a 35) Which are the segment: a.CS: Code segment b.DS: data
segment c.SS: Stack segment d.ES:extra segment e.All of these Ans: D Part-2 1. Which interrupt has the highest priority?
a) INTR b) TRAP c) RST6.5 2. In 8085 name the 16 bit registers? a) Stack pointer b) Program counter c) a & b 3. Which of
the following is hardware interrupts? a) RST5.5, RST6.5, RST7.5 b) INTR, TRAP c) a & b 4. What is the RST for the TRAP? a)
RST5.5 b) RST4.5 c) RST4 5. What are level Triggering interrupts? a) INTR&TRAP b)RST6.5&RST5.5 c)RST7.5&RST6.5 6.
Which interrupt is not level sensitive in 8085? a) RST6.5 is a raising edge-trigging interrupt. b) RST7.5 is a raising edge-
trigging interrupt. c) a & b. 7. What are software interrupts? a) RST 0 - 7 b) RST 5.5 - 7.5 c) INTR, TRAP 8. Which stack is
used in 8085? a) FIFO b) LIFO c) FILO 9. Why 8085 processor is called an 8 bit processor? SAMPLE QUESTION PAPERS RRB-
JE Classroom Online & Postal Coaching Call : 9990657855 a) Because 8085 processor has 8 bit ALU. b) Because 8085
processor has 8 bit data bus. c) a & b. 10. What is SIM? a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt
Mask. 11. RIM is used to check whether, ______ a) The write operation is done or not b) The interrupt is Masked or not
c) a & b 12. What is meant by Maskable interrupts? a) An interrupt which can never be turned off. b) An interrupt that
can be turned off by the programmer. c) none 13. In 8086, Example for Non maskable interrupts are a) Trapb) RST6.5 c)
INTR 14. What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width 15. Can ROM be
used as stack? a) Yes b) No c) sometimes yes, sometimes no 16. Which processor structure is pipelined? a) all x80
processors b) all x85 processors c) all x86 processors 17. Address line for RST3 is? a) 0020H b) 0028H c) 0018H 18. In 8086
the overflow flag is set when a) The sum is more than 16 bits b) Signed numbers go out of their range after an arithmetic
operation c) Carry and sign flags are set d) During subtraction 19. The advantage of memory mapped I/O over I/O mapped
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I/O is, a) Faster b) Many instructions supporting memory mapped I/O c) Require a bigger address decoder d) All the above
Rooma,
20. BHE of 8086 microprocessor signal is used to interface theKanpur – 208
a) Even 008memory b) Odd bank memory c) I/O d) DMA
bank
21. In 8086 microprocessor the following has the highest priority among all type interrupts. a) NMI b) DIV 0 c) TYPE 255
d) OVER FLOW 22. In 8086 microprocessor one of the following statements is not true. a) Coprocessor is interfaced in
MAX mode b) Coprocessor is interfaced in MIN mode c) I/O can be interfaced in MAX / MIN mode d) Supports pipelining
23. 8088 microprocessor differs with 8086 microprocessor in SAMPLE QUESTION PAPERS RRB-JE Classroom Online &
Postal Coaching Call : 9990657855 a) Data width on the output b) Address capability c) Support of coprocessor d) Support
of MAX / MIN mode Answer Key: 1 C 2 C 3 C 4 B 5 B 6 B 7 A 8 B 9 A 10 C 11 B 12 B 13 A 14 C 15 B 16 C 17 C 18 B 19 D 20
B 21 A 22 B 23 A
1. Consider the following registers:
1. Accumulator and flag register
2. B and C register
3. D and E register
4. H and L register
Which of these 8-bit registers of 8085 microprocessor can be paired together to make a 16-bit register?
a. 1 ,3 and 4
b. 2 ,3 and 4
c. 1, 2 and 3
d. 1, 2 and 4
View Answer Report Discuss Too Difficult!
Answer: (b).2 ,3 and 4
2. In 8085 microprocessor system with memory mapped I/O, which of the following is true?
a. Devices have 8-bit address line
b. Devices are accessed using IN and OUT instructions
c. There can be maximum of 256 input devices and 256 output devices
d. Arithmetic and logic operations can be directly performed with the I/O data
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Answer: (d).Arithmetic and logic operations can be directly performed with the I/O data
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Rooma, Kanpur – 208 008
3. In an intel 8085A microprocessor, why is READY signal used?
a. To indicate to user that the microprocessor is working and is ready for use.
b. To provide proper WAIT states when the microprocessor is communicating with a slow peripheral device.
c. To slow down a fast peripheral device so as to communicate at the microprocessor’s device.
d. None of the above.
View Answer Report Discuss Too Difficult!
Answer: (b).To provide proper WAIT states when the microprocessor is communicating with a slow peripheral
device.
4. consider the following
I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag
Which one of the above flags is/are present in 8085 microprocessor?
a. (I) only
b. (I) & (II)
c. (II) & (III)
d. (I) ,(III) & (IV)
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Answer: (d).(I) ,(III) & (IV)
5. Consider the following statements:
In 8085 microprocessor, data-bus and address bus are multiplexed in order to
I)Increase the speed of microprocessor.
II)Reduce the number of pins.
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III)Connect more peripheral chips. Rooma, Kanpur – 208 008
Which of these statements is/are correct?
a. (I) only
b. (II) only
c. (II) & (III)
d. (I), (II) & (III)
View Answer Report Discuss Too Difficult!
Answer: (b).(II) only
6. ALU (Arithmetic and Logic Unit ) of 8085 microprocessor consists of
a. Accumulator, temporary register, arithmetic and logic circuits
b. Accumulator, arithmetic, logic circuits and five flags
c. Accumulator, arithmetic and logic circuits
d. Accumulator, temporary register, arithmetic, logic circuits and five flags
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Answer: (d).Accumulator, temporary register, arithmetic, logic circuits and five flags
7. In intel 8085A microprocessor ALE signal is made high to
a. Enable the data bus to be used as low order address bus
b. To latch data D0-D7 from data bus
c. To disable data bus
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d. To achieve all the functions listed above Rooma, Kanpur – 208 008
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Answer: (a).Enable the data bus to be used as low order address bus
8. Which of the following statements for Intel 8085 is correct?
a. Program Counter (PC) specifies the address of the instruction last executed
b. PC specifies the address of the instruction being executed
c. PC specifies the address of the instruction to be executed
d. PC specifies the number of instructions executed so far
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Answer: (c).PC specifies the address of the instruction to be executed
9. Processor status word of 8085 microprocessor has five flags. They are
a. S, Z, AC, P, CY
b. S, OV, AC, P, CY
c. S, Z, OV, P, CY
d. S, Z, AC, P, OV
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Answer: (a).S, Z, AC, P, CY
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10. The cycle required to fetch and execute an instruction in a –8085
Rooma, Kanpur microprocessor is which one of the following?
208 008
a. Clock cycle
b. Memory cycle
c. Machine cycle
d. Instruction cycle
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Answer: (d).Instruction cycle
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11. In an Intel 8085A, which is the first machine cycle of an instruction?
a. An op-code fetch cycle
b. A memory read cycle
c. A memory write cycle
d. An I/O read cycle
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Answer: (a).An op-code fetch cycle
12. The number of output pins in 8085 microprocessors are
a. 40
b. 27
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c. 21 Rooma, Kanpur – 208 008
d. 19
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Answer: (a).40
13. In 8085 name of the 16 bit registers is
a. stack pointer
b. program counter
c. both A and B
d. none of these
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Answer: (c).both A and B
14. Which of the following instruction is not possible in 8085?
a. POP PSW
b. POP B
c. POP D
d. POP 30 H
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Answer: (d).POP 30 H
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15. How many T-states are required for executionRooma,
of OUT 80H–instruction?
Kanpur 208 008
a. 10
b. 13
c. 16
d. 7
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Answer: (a).10
16. Which instruction is required to rotate the content of accumulator one bit right along with carry?
a. RLC
b. RAL
c. RRC
d. RAR
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Answer: (d).RAR
17. The frequency of the driving network connected between pins 1 and 2 of 8085 microprocessor is
a. twice the desired frequency
b. equal to the desired frequency
c. four times the desired frequency
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d. none of the above Rooma, Kanpur – 208 008
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Answer: (a).twice the desired frequency
18. READY signal in 8085 is useful when the CPU communicates with
a. a slow peripheral device
b. a fast peripheral device
c. a DMA chip
d. a PPI
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Answer: (a).a slow peripheral device
19. Temporary registers in 8085 are
a. B and C
b. D and E
c. H and L
d. W and Z
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Answer: (d).W and Z
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20. Register pair used to indicate memory Rooma, Kanpur – 208 008
a. B and C
b. D and E
c. H and L
d. W and Z
View Answer Report Discuss Too Difficult!
Answer: (c).H and
21. A sequence of two registers that multiplies the content of DE register pair
by two and stores the result in HL register pair (in 8085 assembly
language) is
a. XCHG & DAD B
b. XTHL & DAD H
c. PCHL & DAD D
d. XCHG & DAD H
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Answer: (d).XCHG & DAD H
22. The Intel 8086 microprocessor is a _______ processor.
a. 8 bit
b. 16 bit
c. 32 bit
d. 4 bit
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View Answer Report Discuss Too Difficult!
Rooma, Kanpur – 208 008
Answer: (b).16 bit
23. The 16 bit flag of 8086 microprocessor is responsible to indicate ___________.
a. the condition of result of ALU operation
b. the condition of memory
c. the result of addition
d. the result of subtraction
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Answer: (a).the condition of result of ALU operation
24. The register AX is formed by grouping ________.
a. AH & AL
b. BH & BL
c. CH & CL
d. DH & DL
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Answer: (a).AH & AL
25. In which year, 8086 microprocessor was introduced?
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a. 1978 Rooma, Kanpur – 208 008
b. 1979
c. 1977
d. 1981
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Answer: (a).1978
26. In which year, 8088 microprocessor was announced?
a. 1979
b. 1988
c. 1999
d. 2000
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Answer: (a).1979
27. Which interrupt has the highest priority?
a. INTR
b. TRAP
c. RST6.5
d. RST6.6
View Answer Report Discuss Too Difficult!
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Answer: (c).RST6.5
Rooma, Kanpur – 208 008
28. What is the RST for the TRAP?
a. RST5.5
b. RST4.5
c. RST4
d. RST3
View Answer Report Discuss Too Difficult!
Answer: (b).RST4.5
29. What are level Triggering interrupts?
a. INTR & TRAP
b. RST6.5 & RST5.5
c. RST7.5 & RST6.5
d. RST2.5 & RST6.2
View Answer Report Discuss Too Difficult!
Answer: (b).RST6.5 & RST5.5
30. Which interrupt is not level sensitive in 8085?
a. RST 6.5
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b. RST 7.5 Rooma, Kanpur – 208 008
c. RST 5.5
d. RST 4.5
View Answer Report Discuss Too Difficult!
Answer: (b).RST 7.5
31. What are software interrupts?
a. RST 0-7
b. RST 5.5 - 7.5
c. INTR, TRAP
d. RST 4.4 - 6.4
View Answer Report Discuss Too Difficult!
Answer: (a).RST 0-7
32. Which stack is used in 8085 ?
a. FIFO
b. LIFO
c. FILO
d. LILO
View Answer Report Discuss Too Difficult!
Answer: (b).LIFO
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33. Why 8085 processor is called an 8 bit processor?
Rooma, Kanpur – 208 008
a. because 8085 processor has 8 bit ALU
b. because 8085 processor has 8 bit data bus
c. because 8085 processor has 16 bit data bus
d. because 8085 processor has 16 bit address bus
View Answer Report Discuss Too Difficult!
Answer: (a).because 8085 processor has 8 bit ALU
34. What is SIM in context of microprocessor ?
a. Select Interrupt Mask
b. Sorting Interrupt Mask
c. Set Interrupt Mask
d. Set Integer Mask
View Answer Report Discuss Too Difficult!
Answer: (c).Set Interrupt Mask
35. What is meant by maskable interrupts?
a. an interrupt which can never be turned off
b. an interrupt that can be turned off by the programmer
c. an interrupt which can never be turned on
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d. an interrupt which can never be turned on or off
Rooma, Kanpur – 208 008
View Answer Report Discuss Too Difficult!
Answer: (b).an interrupt that can be turned off by the programmer
36. In 8086, Example for Non maskable interrupts are ________.
a. trap
b. rst6.5
c. intr
d. rst6.6
View Answer Report Discuss Too Difficult!
Answer: (a).trap
37. In 8085 microprocessor address line for RST3 is ?
a. 0020H
b. 0028H
c. 0018H
d. 0019H
View Answer Report Discuss Too Difficult!
Answer: (c).0018H
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38. In 8086 the overflow flag is set when _____________.
Rooma, Kanpur – 208 008
a. the sum is more than 16 bits
b. signed numbers go out of their range after an arithmetic operation
c. carry and sign flags are set
d. subtraction
View Answer Report Discuss Too Difficult!
Answer: (b).signed numbers go out of their range after an arithmetic operation
39. In 8086 microprocessor the following has the highest priority among all type interrupts?
a. NMI
b. DIV 0
c. TYPE 255
d. OVER FLOW
View Answer Report Discuss Too Difficult!
Answer: (a).NMI
40. In 8086 microprocessor one of the following statements is not true?
a. coprocessor is interfaced in max mode
b. coprocessor is interfaced in min mode
c. i/o can be interfaced in max / min mode
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d. supports pipelining Rooma, Kanpur – 208 008
View Answer Report Discuss Too Difficult!
Answer: (b).coprocessor is interfaced in min mode
41. 8088 microprocessor differs with 8086 microprocessor in
_______.
a. data width on the output
b. address capability
c. support of coprocessor
d. support of MAX / MIN mode
View Answer Report Discuss Too Difficult!
Answer: (a).data width on the output
42. Address line for TRAP is ?
a. 0023H
b. 0024H
c. 0033H
d. 0099H
View Answer Report Discuss Too Difficult!
Answer: (b).0024H
43. 8085 microprocessor was introduced in __________.
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a. 1971 Rooma, Kanpur – 208 008
b. 1976
c. 1972
d. 1978
View Answer Report Discuss Too Difficult!
Answer: (b).1976
44. The address / data bus in 8085 is __________.
a. multiplexed
b. demultiplexed
c. decoded
d. encoded
View Answer Report Discuss Too Difficult!
Answer: (a).multiplexed
45. In 8085 name the 16 bit registers?
a. Stack pointer
b. Program counter
c. Both a and b
d. None of these
View Answer Report Discuss Too Difficult!
Allenhouse Institute of Technology (UPTU Code : 505)
Answer: (c).Both a and b
Rooma, Kanpur – 208 008
46. Which stack is used in 8085?
a. FIFO
b. LIFO
c. FILO
d. None of these
View Answer Report Discuss Too Difficult!
Answer: (b).LIFO
47. RIM is used to check whether, ______
a. The write operation is done or not
b. The interrupt is Masked or not
c. a&b
d. None of these
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Answer: (b).The interrupt is Masked or not
48. 8088 microprocessor has
a. 16 bit data bus
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c. 6 byte pre-fetch queue
d. 16 bit address bus
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Answer: (d).16 bit address bus
49. By what factor does the 8284A clock generator divide the crystal oscillator’s output
frequency?
a. One
b. Two
c. Three
d. Four
View Answer Report Discuss Too Difficult!
Answer: (c).Three
Multiple Choice Questions and Answers:-
1) Which is the microprocessor comprises:
a.Register section
b.One or more ALU
c.Control unit
d.All of these
Answer:D
2) What is the store by register?
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a.data
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b.operands
c.memory
d.None of
these
Answer:A
3) Accumulator based microprocessor example are:
a.Intel 8085
b.Motorola 6809
c.A and B d.None
of these
Answer:C
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4) A set of register which contain are:
a.data
b.memory addresses
c.result
d.all of these
Answer:D
5) There are primarily two types of register:
a.general purpose register
b.dedicated register
c.A and B d.none
of these
Answer:C
6) Name of typical dedicated register is:
a.PC
b.IR
c.S
d.All of these
Answer:D
7) BCD stands for:
a.Binary coded decimal
b.Binary coded decoded
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c.Both a&b
d.none of
these
Answer:A
8) Which is used to store critical pieces of data during subroutines and interrupts:a.Stack
b.Queue
c.Accumulat
ord.Data
register
Answer:A
9) The data in the stack is called:
a.Pushing data
b.Pushed
c.Pulling
d.None of
these
Answer:A
10) The external system bus architecture is created using from architecture:
a.Pascal
b.Dennis Ritchie
c.Charles
Babbaged.Von
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Neumann
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Answer:D
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11) The processor 80386/80486 and the Pentium processor uses bits address bus:
a.16
b.32
c.3
d.6
Answer:B
12) Which is not the control bus signal:
a.READ
b.WRITE
c.RESE
d.None of these
Answer:C
13) PROM stands for: a.Programmable
read-only memory b.Programmable read
write memory c.Programmer read and
write memoryd.None of these
Answer:A
14) EPROM stands for:
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a.Erasable Programmable read-only memory
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b.ectrically Programmable read write
memory c.Electrically Programmable
read-only memoryd.None of these
Answer:A
15) Each memory location has:
a.Address
b.Contents
c.Both A and
B d.None of
these
Answer:C
16) Which is the type of microcomputer memory:
a.Processor memory
b.Primary memory
c.Secondary
memoryd.All of
these Answer:D
17) Secondary memory can store :
a.Program store code
b.Compiler
c.Operating
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system
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d.All of these
Answer:D
18) Secondary memory is also called :
a.Auxiliary
b.Backup
store c.Both A
and B d.None
of these
Answer:C
19 Customized ROMS are called:
a.Mask ROM
b.Flash
ROM
c.EPROM
d.None of these
Answer:A
20) The RAM which is created using bipolar transistors is called:
a.Dynamic RAM
b.Static RAM
c.Permanent
RAMd.DDR
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RAM
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Answer:B
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21) Which type of RAM needs regular referred:
a.Dynamic RAM
b.Static RAM
c.Permanent
RAMd.SD RAM
Answer:A
22) Which RAM is created using MOS transistors:
a.Dynamic RAM
b.Static RAM
c.Permanent
RAMd.SD RAM
Answer:A
23) A microprocessor retries instructions from :
a.Control memory
b.Cache
memory c.Main
memory
d.Virtual
memory
Answer:C
24) The lower red curvy arrow show that CPU places the address extracted from the
memory
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location on the :
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a.Address bus
b.System
bus
c.Control
bus d.Data
bus
Answer:A
25) The CPU sends out a signal to indicate that valid data is available on the data bus:
a.Read
b.Write
c.Both A and B
d.None of
these
Answer:B
26) The CPU removes the signal to complete the memory write operation:
a.Read
b.Write
c.Both A and B
d.None of
these
Answer:A
27) BIU STAND FOR:
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a.Bus interface unit
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b.Bess interface unit
c.A and B
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d.None of these
Answer:A
28) EU STAND FOR:
a.Execution unit
b.Execute unit
c.Exchange unit
d.None of
these
Answer:A
29) Which are the four categories of registers:
a.General- purpose register
b.Pointer or index
registersc.Segment
registers d.Other
register
e.All of these
Answer:E
30) Eight of the register are known as:
a.General- purpose register
b.Pointer or index
registersc.Segment
registers d.Other
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register
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Answer:A
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31) The four index register can be used for:
a.Arithmetic operation
b.Multipulation operation
c.Subtraction
operation d.All of
these
Answer:A
32) IP Stand for:
a.Instruction pointer
b.Instruction purpose
c.Instruction paints
d.None of these
Answer:A
33) CS Stand for:
a.Code segment
b.Coot segment
c.Cost segment
d.Counter segment
Answer:A
34) DS Stand for:
a.Data segment
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b.Direct segment
c.Declare
segment
d.Divide
segment
Answer:A
35) Which are the segment:
a. CS: Code segment
b. DS: data segment
c. SS: Stack segment
d. ES:extra segment
e.All of these
Answer:D
36) The acculatator is 16 bit wide and is called:
a.AX
b.AH
c.AL
d.D
Answer:A
37) How many bits the instruction pointer is wide:
a.16 bit
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b.32 bit
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c.64 bit
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d.128 bit
Answer:A
38) How many type of addressing in memory:
a.Logical address
b.Physical
addressc.Both A
and B d.None of
these Answer:C
39) The size of each segment in 8086 is:
a.64 kb
b.24 kb
c.50 kb
d.16kb
Answer:
40) The address of a memory is a 20 bit address for the 8086 microprocessor:
a.Physical
b.Logical
c.Both
d.None of these
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Answer:A
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41) The pin configuration of 8086 is available in the :
a.40 pin
b.50 pin
c.30 pin
d.20 pin
Answer:
42) DIP stand for:
a.Deal inline package
b.Dual inline package
c.Direct inline package
d.Digital inline package
Answer:B
43) EA stand for:
a.Effective address
b.Electrical address
c.Effect address
d.None of these
Answer:A
44) BP stand for:
a.Bit pointer
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b.Base pointer
c.Bus
pointer
d.Byte
pointer
Answer:B
45) DI stand for:
a.Destination index
b.Defect index
c.Definition index
d.Delete index
Answer:A
46) SI stand for:
a.Stand index
b.Source index
c.Segment index
d.Simple index
Answer:B
47) ALE stand for:
a.Address latch enable
b.Address light enable
c.Address lower enable
d.Address last enable
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Answer:A
48) NMI stand for:
a.Non mask able interrupt
b.Non mistake
interrupt c.Both
d.None of these
Answer:A
49) is the most important segment and it contains the actual assembly language
instruction to be executed by the microprocessor:
a.Data segment
b.Code
segment
c.Stack
segment
d.Extra
segment
Answer:B
50) The offset of a particular segment varies from :
a.000H to FFFH
b.0000H to FFFFH
c.00H to FFH
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d.00000H to
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FFFFFH
Answer:B
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51) Which are the factor of cache memory:
a.Architecture of the microprocessor
b.Properties of the programs being
executed c.Size organization of the cache
d.All of these
Answer:D
52) is usually the first level of memory access by the microprocessor:
a.Cache memory
b.Data memory
c.Main
memoryd.All
of these
Answer:A
53) Which is the small amount of high- speed memory used to work directly with the
microprocessor:
a.Cache
b.Case
c.Cost
d.Coos
Answer:
A
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54) The cache usually gets its data from the whenever the instruction or data is
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required by the CPU:
a.Main memory
b.Case
memory
c.Cache
memoryd.All
of these
Answer:A
55) Microprocessor reference that are available in the cache are called :
a.Cache hits
b.Cache line
c.Cache
memoryd.All
of these
Answer:A
56) Microprocessor reference that are not available in the cache are called :
a.Cache hits
b.Cache line
c.Cache misses
d.Cache
memory
Answer:C
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57) Which causes the microprocessor toRooma, Kanpur –terminate
immediately 208 008 its present activity:
a.RESET signal
b.INTERUPT signal
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c.Both
d.None of these
Answer:A
58) Which is responsible for all the outside world communication by the microprocessor:a.BIU
b.PIU
c.TI
d.LI
Answer:A
59) INTR: it implies the signal:
a. INTRRUPT REQUEST
b. INTRRUPT RIGHT
c. INTRRUPT RONGH
d. INTRRUPT RESET
Answer:A
60) Which of the following are the two main components of the CPU?
a.Control Unit and Registers
b.Registers and Main
Memoryc.Control unit and
ALU
d.ALU and bus
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Answer:C
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61) Different components n the motherboard of a PC unit are linked together by sets of parallel
electrical conducting lines. What are these lines called?
a.Conductors
b.Buses
c.Connectors
d.Consecutiv
esAnswer:B
62) The language that the computer can understand and execute is called
a.Machine language
b.Application software
c.System program
d.All of the above
Answer:A
63) Which of the following is used as a primary storage device?
a.Magnetic drum
b.PROM
c.Floppy disk
d.All of
these
Answer:B
64) Which of the following memories needs refresh?
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a.SRAM
b.DRAM
c.ROM
d.All of above
Answer:B
65) The memory which is programmed at the time it is manufactured
a.PROM
b.RAM
c.PROM
d.EPRO
Answer:A
66) Which of the following memory medium is not used as main memory system?
a.Magnetic core
b.Semiconductor
c.Magnetic
tape d.Both a
and b
Answer:C
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67) Registers, which are partially visibleRooma, Kanpur
to users – 208 to
and used 008hold conditional, are known as
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a.PC
b.Memory address
registersc.General
purpose register d.Flags
Answer:C
68) One of the main feature that distinguish microprocessors from micro-computers is
a.Words are usually larger in microprocessors
b.Words are shorter in microprocessors
c.Microprocessor does not contain I/O
devicesd.Exactly the same as the
machine cycle time Answer:C
69) The first microprocessor built by the Intel Corporation was calleda.8008
b.8080
c.400
d.880
Answer:C
70) An integrated circuit is
a.A complicated circuit
b.An integrating
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device
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c.Much costlier than a single transistor
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d.Fabricated on a tiny silicon
chipAnswer:D
71) Most important advantage of an IC is its
a.Easy replacement in case of circuit failure
b.Extremely high reliability
c.Reduced cost
d.Low powers
consumptionAnswer:B
72) Which of the following items are examples of storage devices?
a.Floppy / hard disks
b.CD-ROMs
c.Tape devices
d.All of the
above
Answer:D
73) The Width of a processor’s data path is measured in bits. Which of the following are
common
data paths?
a.8 bits
b.12 bits
c.16 bits
d.32 bits
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Answer:A
74) Which is the type of memory for information that does not change on your computer?a.RAM
b.ROM
c.ERAM
d.RW /
RAM
Answer:B
75) What type of memory is not directly addressable by the CPU and requires special softw3arecalled
EMS (expanded memory specification)?
a. Extended
b.Expanded
c.Base
d.Conventional
Answer:B
76) Before a disk can be used to store data. It must be…….
a.Formatted
b.Reformatted
c.Addressed
d.None of the above
Answer:A
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77) Which company is the biggest player in the microprocessor industry?
a.Motorola
b. IBM
c. Intel
d.AMD
Answer:C
78) A typical personal computer used for business purposes would have… of RAM.
a.4 KB
b.16 K
c.64 K
d.256 K
Answer:
78) The word length of a computer is measured in
a.Bytes
b.Millimeters
c.Meters
d.Bits
Answer:D
79) What are the three decisions making operations performed by the ALU of a computer?
a.Grater than
b.Less than
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c.Equal to
d.All of the above
Answer:D
80) Which part of the computer is used for calculating and comparing?a.Disk
unit
b.Control unit
c.ALU
d.Modem
Answer:
81) Can you tell what passes into and out from the computer via its ports?a.Data
b.Bytes
c.Graphi
cs
d.Picture
Answer:
82) What is the responsibility of the logical unit in the CPU of a computer?a.To
produce result
b.To compare numbers
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c.To control flow of Rooma, Kanpur – 208 008
informationd.To do math’s
works
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Answer:B
83) The secondary storage devices can only store data but they cannot perform
a.Arithmetic Operation
b.Logic operation
c.Fetch operations
d.Either of the
above Answer:D
84) Which of the following memories allows simultaneous read and write operations?a.ROM
b.RAM
c.EPRO
d.None of above
Answer:B
85) Which of the following memories has the shortest access times?
a.Cache memory
b.Magnetic bubble memory
c.Magnetic core
memory d.RAM
Answer:A
86) A 32 bit microprocessor has the word length equal to
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a.2 byte
b.32 byte
c.4 byte
d.8 byte
Answer:
87) An error in computer data is called
a.Chip
b.Bug
c.CP
d.Storage device
Answer:B
88) The silicon chips used for data processing are called
a.RAM chips
b. ROM chips
c. Micro processors
d. PROM chips
Answer:D
89) The metal disks, which are permanently housed in, sealed and contamination free
containers
are called
a.Hard
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disks
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b.Floppy disk
c.Winchester
diskd.Flexible
disk Answer:C
90) A computer consists of
a.A central processing unit
b.A memory
c.Input and output unit
d.All of the above
Answer:D
91) The instructions for starting the computer are house on
a.Random access memory
b.CD-Rom
c.Read only memory chip
d.All of above
Answer:C
92) The ALU of a computer normally contains a number of high speed storage element called
a.Semiconductor memory
b.Registers
c.Hard disks
d.Magnetic
disk
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Answer:B
93) The first digital computer built with IC chips was known as
a.IBM 7090
b.Apple – 1
c.IBM System / 360
d.VAX-10
Answer:C
94) Which of the following terms is the most closely related to main memory?a.Non
volatile
b.Permanent
c.Control
unit
d.Temporar
y Answer:D
95) Which of the following is used for manufacturing chips?
a.Control bus
b.Control unit
c.Parity unit
d.Semiconduct
orAnswer:D
96) To locate a data item for storage is
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a.Field
b.Feed
c.Databas
ed.Fetch
Answer:
97) A directly accessible appointment calendar is feature of a … resident packagea.CPU
b.Memory
c.Buffer
d.ALU
Answer:B
98) The term gigabyte refers to
a.1024 bytes
b.1024 kilobytes
c.1024
megabytes
d.1024 gigabyte
Answer:C
99) A/n …. Device is any device that provides information, which is sent to the CPUa.Input
b.Output
c.CPU
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d.Memory
Answer:
100) Current SIMMs have either … or … connectors (pins)
a.9 or 32
b.30 or 70
c.28 or 72
d.30 or 72
Answer:
D
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8086 Microprocessor
1. A microprocessor is a chip integrating all the functions of a CPU of a computer.
A. multiple B. single C. double D. triple
ANSWER: B
2. Microprocessor is a/an circuit that functions as the CPU of the compute
A. electronic B. mechanic C. integrating D. processing
ANSWER: A
3. Microprocessor is the of the computer and it perform all the computational tasks
A. main B. heart C. important D. simple
ANSWER: B
4. The purpose of the microprocessor is to control
A. memory B. switches C. processing D. tasks
ANSWER: A
5. The first digital electronic computer was built in the year
A. 1950 B. 1960 C. 1940 D. 1930
ANSWER: C
6. In 1960's texas institute invented
A. integrated circuits B. microprocessor C. vacuum tubes D. transistors
ANSWER: A
7. The intel 8086 microprocessor is a processor
A. 8 bit B. 16 bit C. 32 bit D. 4 bit
ANSWER: B
8. The microprocessor can read/write 16 bit data from or to
A. memory B. I /O device C. processor D. register
ANSWER: A
9. In 8086 microprocessor , the address bus is bit wide
A. 12 bit B. 10 bit C. 16 bit D. 20 bit
ANSWER: D
10. The work of EU is
A. encoding B. decoding C. processing D. calculations
ANSWER: B
11. The 16 bit flag of 8086 microprocessor is responsible to indicate
A. the condition of result of ALU operation B. the condition of memory
C. the result of addition D. the result of subtraction
ANSWER: A
12. The CF is known as
A. carry flag B. condition flag C. common flag D. single flag
.ANSWER: A
13. The SF is called as
A. service flag B. sign flag C. single flag D. condition flag
ANSWER: B
14. The OF is called as
A. overflow flag B. overdue flag C. one flag D. over flag
ANSWER: A
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15. The IF is called as
A. initial flag B. indicate flag C. interrupt flag D. inter flag
ANSWER: C
16. The register AX is formed by grouping
A. AH & AL B. BH & BL C. CH & CL D. DH & DL
ANSWER: A
17. The SP is indicated by
A. single pointer B. stack pointer C. source pointer D. destination
pointerANSWER: B
18. The BP is indicated by
A. base pointer B. binary pointer C. bit pointer D. digital pointer
ANSWER: A
19. The SS is called as
A. single stack B. stack segment C. sequence stack .D. random stack
ANSWER: B
20. The index register are used to hold
A. memory register B. offset address C. segment memory D. offset memory
ANSWER: A
21. The BIU contains FIFO register of size bytes
A. 8 B. 6 C. 4 D. 12
ANSWER: B
22. The BIU prefetches the instruction from memory and store them in
A. queue B. register C. memory D. stack
ANSWER: A
23. The 1 MB byte of memory can be divided into segment
A. 1 Kbyte B. 64 Kbyte C. 33 Kbyte D. 34 Kbyte
ANSWER: B
24. The DS is called as
A. data segment B. digital segment C. divide segment D. decode
segmentANSWER: A
25. The CS register stores instruction in code segment
A. stream B. path C. codes D. stream line
ANSWER: C
26. The IP is bits in length
A. 8 bits B. 4 bits C. 16 bits D. 32 bits
ANSWER: C
27. The push source copies a word from source to
A. stack B. memory C. register D. destination
ANSWER: A
28. LDs copies to consecutive words from memory to register and
A. ES B. DS C. SS D. CS
ANSWER: B
29. INC destination increments the content of destination by
A. 1 B. 2 C. 30 D. 41
ANSWER: A
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30. IMUL source is a signed
A. multiplication B. addition C. subtraction D. division
ANSWER: A
31. destination inverts each bit of destination
A. NOT B. NOR C. AND D. OR
ANSWER: A
32. The JS is called as
A. jump the signed bit B. jump single bit
C. jump simple bit D. jump signal it
ANSWER: A
33. Instruction providing both segment base and offset address are called
A. below type .B. far type C. low type D. high type
ANSWER: B
34. The conditional branch instruction specify for branching
A. conditions B. instruction C. address D. memory
ANSWER: A
35. The microprocessor determines whether the specified condition exists or not by testing the
A. carry flag B. conditional flag C. common flag D. sign flag
ANSWER: B
36. The LES copies to words from memory to register and
A. DS B. CS C. ES D. DS
ANSWER: C
37. The translates a byte from one code to another code
A. XLAT B. XCHNG C. POP D. PUSH
ANSWER: A
38. The contains an offset instead of actual address
A. SP B. IP C. ES D. SS
ANSWER: B
39. The 8086 fetches instruction one after another from of memory
A. code segment B. IP C. ES D. SS
ANSWER: A
40. The BIU contains FIFO register of size 6 bytes called .
A. queue B. stack C. segment D. register
ANSWER: A
41. The is required to synchronize the internal operands in the processor CLK
Signal
A. UR Signal B. Vcc C. AIE D. Ground
ANSWER: A
42. The pin of minimum mode AD0-AD15 has address
A. 16 bit B. 20 bit C. 32 bit D. 4 bit
ANSWER: B
43. The pin of minimum mode AD0- AD15 has _ data bus
A. 4 bit B. 20 bit C. 16 bit D. 32 bit
ANSWER: C
44. The address bits are sent out on lines through
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A. A16-19 B. A0-17 C. D0-D17 D. C0-C17
ANSWER: A
45. is used to write into memory
A. RD B. WR C. RD / WR D. CLK
ANSWER: B
46. The functions of Pins from 24 to 31 depend on the mode in which is
operatingA. 8085 B. 8086 C. 80835 D. 80845
ANSWER: B
47. The RD, WR, M/IO is the heart of control for a mode
A. minimum B. maximum C. compatibility mode D. control mode
ANSWER: A
48. In a minimum mode there is a on the system bus
A. single B. double C. multiple D. triple
ANSWER: A
49. If MN/MX is low the 8086 operates in mode
A. Minimum B. Maximum C. both (A) and (B) D. medium
ANSWER: B
50. In max mode, control bus signal So,S1 and S2 are sent out in form
A. decoded B. encoded C. shared D. unshared
ANSWER: B
51. The bus controller device decodes the signals to produce the control bus signal
A. internal B. data C. external D. address
ANSWER: C
52. A Instruction at the end of interrupt service program takes the execution back to
theinterrupted program
A. forward B. return C. data D. line
ANSWER: B
53. The main concerns of the are to define a flexible set of commands
A. memory interface B. peripheral interface
C. both (A) and (B) D. control interface
.ANSWER: A
54. Primary function of memory interfacing is that the should be able to read
fromand write into register
A. multiprocessor B. microprocessor C. dual Processor D. coprocessor
ANSWER: B
55. To perform any operations, the Mp should identify the
A. register B. memory C. interface D. system
ANSWER: A
56. The Microprocessor places address on the address bus
A. 4 bit B. 8 bit C. 16 bit D. 32 bit
ANSWER: C
57. The Microprocessor places 16 bit address on the add lines from that address by
register should be selected
A. address B. one C. two D.
threeANSWER: B
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
58. The of the memory chip will identify and select the register for the EPROM
A. internal decoder B. external decoder C. address decoder D. data
decoderANSWER: A
59. Microprocessor provides signal like to indicate the read operatio
A. LOW B. MCMW C. MCMR D. MCMWR
ANSWER: C
60. To interface memory with the microprocessor, connect register the lines of the address
busmust be added to address lines of the chip.
A. single B. memory C. multiple D. triple
ANSWER: B
61. The remaining address line of bus is decoded to generate chip select signal
A. data B. address C. control bus D. both (a) and (b)
ANSWER: B
62. signal is generated by combining RD and WR signals with IO/M
A. control B. memory C. register D. system
ANSWER: A
63. Memory is an integral part of a system
A. supercomputer B. microcomputer
C. mini computer D. mainframe computer
ANSWER: B
64. has certain signal requirements write into and read from its registers
A. memory B. register C. both (a) and (b) D. control
ANSWER: A
65. An is used to fetch one address
A. internal decoder B. external decoder C. encoder D. register
ANSWER: A
66. The primary function of the is to accept data from I/P devices
A. multiprocessor B. microprocessor C. peripherals D. interfaces
ANSWER: B
67. signal prevent the microprocessor from reading the same data more than one
A. pipelining B. handshaking C. controlling D. signaling
ANSWER: B
68. Bits in IRR interrupt are
A. reset B. set C. stop D. start
ANSWER: B
69. generate interrupt signal to microprocessor and receive acknowledge
A. priority resolver B. control logic
C. interrupt request register D. interrupt register
ANSWER: B
70. The pin is used to select direct command word
A. A0 B. D7-D6 C. A12 D. AD7-AD6
ANSWER: A
71. The is used to connect more microprocessor
A. peripheral device B. cascade C. I/O devices D. control unit
ANSWER: B
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
72. CS connect the output of
A. encoder B. decoder C. slave program D. buffer
ANSWER: B
73. In which year, 8086 was introduced?
A. 1978 B. 1979 C. 1977 D. 1981
ANSWER: A
74. Expansion for HMOS technology_
A. high level mode oxygen semiconductor
B. high level metal oxygen semiconductor
C. high performance medium oxide semiconductor
D. high performance metal oxide
semiconductorANSWER: D
75. 8086 and 8088 contains transistors
A. 29000 B. 24000 C. 34000 D. 54000
ANSWER: A
76. ALE stands for
A. address latch enable B. address level enable
C. address leak enable D. address leak extension
ANSWER: A
77. What is DEN?
A. direct enable B. data entered C. data enable D. data
encodingANSWER: C
78. In 8086, Example for Non maskable interrupts are .
A. TRAP B. RST6.5 C. INTR D. RST6.6
ANSWER: A
79. In 8086 the overflow flag is set when .
A. the sum is more than 16 bits.
B. signed numbers go out of their range after an arithmetic operation.
C. carry and sign flags are set.
D. subtractio
nANSWER: B
80. In 8086 microprocessor the following has the highest priority among all type interrupts?
A. NMI B. DIV 0 C. TYPE 255 D. OVER FLOW
ANSWER: A
81. In 8086 microprocessor one of the following statements is not true?
A. coprocessor is interfaced in max mode. B. coprocessor is interfaced in min mode.
C. I /O can be interfaced in max / min mode. D. supports pipelining
ANSWER: B
82. Address line for TRAP is?
A. 0023H B. 0024H C. 0033H D. 0099H
ANSWER: B
83. Access time is faster for .
A. ROM B. SRAM C. DRAM D. ERAM
ANSWER: B
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
84. The First Microprocessor was .
A. Intel 4004 B. 8080 C. 8085 D. 4008
ANSWER: A
85. Status register is also called as .
A. accumulator B. stack C. counter D. flags
ANSWER: D
86. Which of the following is not a basic element within the microprocessor?
A. Microcontroller B. Arithmetic logic unit (ALU)
C. Register array D. Control unit
Ans.: A
87. Which method bypasses the CPU for certain types of data transfer?
A. Software interrupts B. Interrupt-driven I/O
C. Polled I/O D. Direct memory access (DMA)
Ans.: D
88. Which bus is bidirectional?
A. Address bus B. Control bus
C. Data bus D. None of the above
Ans.: C
89. The first microprocessor had a(n) .
A. 1 – bit data bus B. 2 – bit data bus
C. 4 – bit data bus D. 8 – bit data bus
Ans.: C
90. Which microprocessor has multiplexed data and address lines?
A. 8086 B. 80286 C. 80386 D. Pentium
Ans.: A
91. Which is not an operand?
A. Variable B. Register C. Memory location D. Assembler
Ans.: D
92. Which is not part of the execution unit (EU)?
A. Arithmetic logic unit (ALU) B. Clock
C. General registers D. Flags
Ans.: B
93. A 20-bit address bus can locate .
A. 1,048,576 locations B. 2,097,152 locations
C. 4,194,304 locations D. 8,388,608 locations
Ans.: A
94. Which of the following is not an arithmetic instruction?
A. INC (increment) B. CMP (compare)
C. DEC (decrement) D. ROL (rotate left)
Ans.: D
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
95. During a read operation the CPU fetches _.
A. a program instruction B. another address
C. data itself D. all of the above
Ans.: D
96. Which of the following is not an 8086/8088 general-purpose register?
A. Code segment (CS) B. Data segment (DS)
C. Stack segment (SS) D. Address segment (AS)
Ans.: D
97. A 20-bit address bus allows access to a memory of capacity
A. 1 MB B. 2 MB C. 4 MB D. 8 MB
Ans.: A
98. Which microprocessor accepts the program written for 8086 without any
changes?A. 8085 B. 8086 C. 8087 D. 8088
Ans.: D
99. Which group of instructions do not affect the flags?
A. Arithmetic operations B. Logic operations
C. Data transfer operations D. Branch operations
Ans.: C
100. The result of MOV AL, 65 is to store
A. store 0100 0010 in AL B. store 42H in AL
C. store 40H in AL D. store 0100 0001 in AL
Ans.: D
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
8255
Question 1: How many pins does the 8255 PPI IC contains?
a. 24
b. 20
c. 32
d. 40
Answer: d. 40
Question 2: In which mode do all the Ports of the 8255 PPI work as Input-Output
units for data transfer?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: b. Mode 0 of I/O mode
Question 3: Which of the following pins are responsible for handling the on the
Read Write control logic unit of the 8255 PPI?
a. CS'
b. RD'
c. WR'
d. ALL of the above
Answer: d. All of the above
Question 4: In which of the following modes is the 8255 PPI capable of transferring
data while handshaking with the interfaced device?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: c. Mode 1 of I/O mode
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma,
Question 5: How many bits of data can beKanpur – 208 008 between the 8255 PPI and the
transferred
interfaced device at a time? or What is the size of internal bus of the 8255 PPI?
a. 16 bits
b. 12 bits
c. 8 bits
d. None of the above
Answer: c. 8 bits
Question 6: Which port of the 8255 PPI is capable of performing the handshaking
function with the interfaced devices?
a. Port A
b. Port B
c. Port C
d. All of the above
Answer: c. Port C
Question 7: In which of the following modes of the 8255 PPI, only port C is taken
into consideration?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: a. BSR mode
Question 8: In mode 2 of I/O mode, which of the following ports are capable of
transferring the data in both the directions?
a. Port A
b. Port B
c. Port C
d. All of the above
Answer: a. Port A
Question 9: In which of the following modes we do not consider the D6, D5 and D4
bits of the control word?
a. BSR mode
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Question 10: How many data lines in total are there in the 8255 PPI IC?
a. 8 data lines
b. 32 data lines
c. 24 data lines
d. None of the above
Answer: c. 24 data lines
Question 11: PPI 8255 is a general purpose programmable I/O device designed to
interface the CPU with its outside world such as ADC, DAC, keyboard etc.
a. True
b. False
Answer: a. True
Explanation:
PPI 8255 is a general purpose programmable I/O device which is specifically designed to
interface the CPU with its outside world such as ADC, DAC, keyboard etc.
Question 12: During process a data bus buffer has controlled using,
a. Control word register
b. Data bus
c. R/W control logic
d. None of these
Answer: b. Data bus
Explanation:
During process a data bus buffer has controlled using read/write control logic.
Question 13: The 8255 ports works in the I/O mode,
a. Programmable I/O ports
b. Set pins
c. Reset pins
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
The 8255 ports work in the I/O mode as programmable I/O ports.
Question 14: PPI 8255 consists of three 8-bit bidirectional I/O ports,
a. PORT A,
b. PORT B
c. PORT C
d. All of these
Answer: d. All of these
Explanation:
PPI 8255 consists of three 8-bit bidirectional I/O ports as PORT A, PORT B, and PORT C.
Question 15: PPI 8255 consists of 40 pins and operates in ... regulated power
supply,
a. +5V
b. +15V
c. +5V
d. None of these
Answer: a. +5V
Explanation:
PPI 8255 consists of 40 pins and operates in +5V regulated power supply.
Question 16: Strobed input/output mode is also known as -
a. Mode 0
b. Mode 1
c. Mode 2
d. None of these
Answer: b. Mode 1
Explanation:
In this mode, the input or output operation of the specified port is controlled by
handshaking signals.
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
c. Mode 2
d. None of these
Answer: b. Mode 1
Explanation:
In this mode, the handshaking signals control the input or output action of the specified
port.
Question 18: The pulse width of the INIT signal at the receiving terminal must be
greater than ... that of the receiving terminal –
a. 10 microseconds
b. 50 microseconds
c. 40 microseconds
d. 20 microseconds
Answer: b. 50 microseconds
Explanation:
The pulse width of a signal at the receiving terminal must be more than 50
microseconds.
Question 19: The feature of mode 2 of 8255 is,
a. Both inputs and outputs are latched
b. Port C is used for generating handshake signals
c. Single 8-bit port is available
d. All of these
Answer: d. All of these
Explanation:
A single 8-bit port is available in mode 2 of 8255, i.e., group A.
Question 20: The port which is used in mode 1 or mode 2 for the generation of
handshake lines is,
a. Port A
b. Port B
c. Port C Upper
Allenhouse Institute of Technology (UPTU Code : 505)
d. Port C Lower Rooma, Kanpur – 208 008
Answer: d. Port C Lower
Explanation:
The upper Port C is used for the generation of mode 1 or mode 2 handshake lines.
Question 21: The pin that clears the control word register of 8255 when enabled is,
a. RESET
b. SET
c. CLEAR
d. CLK
Answer: a. RESET
Explanation:
If the reset pin is allowed, then the register of control words is cleared.
Question 22: The signals that are provided to maintain proper data flow and
synchronization between the data transmitter and receiver are –
a. Handshaking signals
b. Control signals
c. Input signals
d. None of these
Answer: a. Handshaking signals
Explanation:
Handshaking signals preserve proper flow and synchronization of information. In orderto
create a valid link between two stations, signals are transmitted back and forth via a
communications network. In an RS-232 serial transmission, a "hardware handshake"
utilizes dedicated wires such as request-to-send (RTS) and clear-to-send (CTS) lines.
Question 23: From pin PA0 – PA7 are the part of -
a. Pins of port A
b. Pins of port B
c. Pins of port C
d. None of these
Answer: a. Pins of port A
Explanation:
Allenhouse Institute of Technology (UPTU Code : 505)
There are 24 input/output pins for the Rooma,
8255. Kanpur
These–are
208 008
split into three ports that are 8-bit(A,
B, C). It is possible to use Port A and Port B as 8-bit input/output ports. Pins of port A
consist pins from pin PA0 – PA7.Port C can be used either as an 8-bit input/output port
or as two 4-bit input/output ports or for ports A and B to create handshake signals.
Question 24: In the pin diagram of PIP 8255, CS stands for Chip select,
a. True
b. False
Answer: a. True
Explanation:
In the pin diagram of PIP 8255, CS stands for Chip select. Chip selection (CS) or slave
selection (SS) is the name of a digital electronics control line used to select one (or a set)
of integrated circuits (commonly referred to as 'chips') out of many connected to the
same device bus, typically using three-state logic.
Question 25: If MSB of control word (D7) is 0, PPI works in BSR mode.
a. True
b. False
Answer: a. True
Explanation:
If MSB of control word (D7) is 0, PPI works in BSR mode.
Allenhouse Institute of Technology (UPTU Code : 505)
8253
Rooma, Kanpur – 208 008
1.Intel’s programmable device (8253) facilitates the
generation of accurate time delays.
a) counter
b) timer
c) both a & b
d) none of these
ANSWER: c
2. The programmable timer device (8253) contains three independent bit
counters.
a) 8
b) 16
c) 20
d) 32
ANSWER: b
3. The 8-bit data buffer interfaces internal circuit of 8253 to microprocessor
systems bus.
a) Unidirectional
b) Single
c) Bidirectional
d) None of these
ANSWER: c
4. The three counters available in 8253 are independent of each other in operation,but
they are to each other in organisation.
a) Similar
b) Opposite
c) Identical
d) Common
ANSWER: c
5. The speciality of the 8253 counters is that they can be easily read on line
without disturbing the _ input to the counter.
a) GATE
b) CLK
c) OUT
d) WR
ANSWER: b
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
6. The GATE signal is and should be for normal counting.
a) Active Low, Low
b) Normal, Normal
c) Active High, High
d) None of the Above
ANSWER: c
7. When GATE goes low counting is terminated and the current count is
till the GATE again goes high.
a) Disturb
b) Latched
c) Decrease
d) Increase
ANSWER: b
8. If N is loaded as the count value, then, after N pulses, the output becomes lowonly
for clock cycle.
a) One
b) Zero
c) N
d) (N-1)
ANSWER: a
9. In this mode, the 8253 can be used as a wave rate generator.
a) Sine wave
b) Cosine wave
c) Square wave
d) All of these
e) ANSWER: c
10. When count is N loaded in , then for half of the count, the output remains
high and for remaining half it remain low.
a) Odd
b) Even
c) Even-even
d) Odd-odd
ANSWER: b
11. If the count loaded is odd the first clock cycle pulse decrement by
resulting in an even count value.
a) 0
b) 1
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
c) -1
d) None of these
ANSWER: b
12. The processor 8085 had hardware interrupt pins.
a) 4
b) 5
c) 6
d) 8
ANSWER: b
13. The predecessor 8259 was designed to operate only with bit processors
like 8085.
a) 4
b) 8
c) 16
d) 20
ANSWER: b
14. A modified version, was later introduced that is compatible with 8-bit aswell
as 16-bit.
a) 8259
b) 8359
c) 8259A
d) 8359A
ANSWER: c
15. stores all the interrupt requests in it in order to serve them one by one onthe
priority basis.
a) IRR
b) ISR
c) IMR
d) NMI
ANSWER: a
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
16. keeps a track of the requests being served.
a) IRR
b) ISR
c) IMR
d) NMI
ANSWER: b
17. stores the bits required to mask the interrupt input.
a) IRR
b) ISR
c) IMR
d) NMI
ANSWER: c
18. pin is an active low write enable input to 8259A
a) WR
b) WR‾‾
c) Both a & b
d) None of these
ANSWER: b
19. In Cascade Buffer/Comparator the same pins act as inputs when the 8259A is in
a) Master
b) Slave
c) Master-Slave
d) All of these
ANSWER: b
20. goes high whenever a valid interrupt request is asserted.
a) INT pin
b) NMI pin
c) IRR pin
d) ISR pin
ANSWER: a
21. as inputs to accept interrupt requests to the CPU.
a) IR₀-IR₇
b) CR₀-CR₇
c) DR₀-DR₇
d) TS₀-TS₇
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
ANSWER: a
22. In an based system , A₁₅-A₈ of the interrupt vector address are the
respective bits of ICW₂.
a) 8008
b) 8080
c) 8085
d) 8086
ANSWER: c
23. In an 8086/88 based system of the interrupt vector address are insertedin
place of T₇ -T₃ respectively.
a) A₁₅-A₁₁
b) A₁₅-A₈
c) A₁₅-A₁₃
d) A₁₅-A₅
ANSWER: a
24. Special fully nested mode is selected, if SFNM= .
a) 0
b) -1
c) 1
d) None
ANSWER: c
25. If AEOI= , the automatic end of interrupt mode is selected.
a) 1
b) 0
c) -1
d) None
ANSWER: a
26. is the default mode of operation of 8259A.
a) Real mode
b) AEOI (automatic end of interrupt mode)
c) EOI(end of interrupt mode)
d) Fully Nested mode
ANSWER: d
27. If bit LTIM of ICW₁=0 , they are triggered
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
a) Edge
b) Level
c) Both a & b
d) None of these
ANSWER: a
28. The I/O section is enabled only if CS‾‾Is
a) High
b) Low
c) Very high
d) Very low
ANSWER: b
29. RD‾‾/WR‾‾ input pins enable the data buffers to receive or send data over the
bus.
a) Address
b) Data
c) Both a & b
d) None of these
ANSWER: b
30. are used to scan the key board matrix and display digits.
a) SL₀-SL₃
b) RL₀-RL₃
c) CL₀-CL₃
d) All of these
ANSWER: a
31. O/P pin is used to blank the display during digit switching or by a
blanking command.
a) BD
b) BS
c) BD‾‾
d) BS‾‾
ANSWER: c
32. Scanned Keyboard Mode in encoded scan keyboard or in decode scana
Keyboard can be interfaced.
a) 8*8,4*8
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
b) 4*8,8*8
c) 4*4,8*8
d) 8*4,4*8
ANSWER: a
33. Scanned Keyboard Special Error Mode is valid only under the key rollover
Mode.
a) 1
b) 50
c) N-1
d) N
ANSWER: d
34. The 8-byte FIFO RAM now acts as bit memory matrix.
a) 4*4
b) 4*8
c) 8*8
d) 8*4
ANSWER: c
35. In the left entry mode, the data is entered from the side of display unit.
a) Left
b) Right
c) Front
d) Back
ANSWER: a
36. In the right entry mode, the data is entered from the side of display unit.
a) Left
b) Right
c) Front
d) Back
ANSWER: b
37. In mode, data is transmitted only in one direction over a single
communication channel.
a) Simplex
b) Duplex
c) Half duplex
d) Half simplex
ANSWER: a
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
38. input pins, together with RD‾‾ and WR‾‾ inputs, informs the 8251Athat
the word on the data bus is either a data or control word/status information.
a) C/D-control Word/Data
b) C/D‾-control Word/Data
c) C‾/D-control Word
d) C‾/D‾-control Word/Data
ANSWER: b
39. A high on RESET input forces the 8251A into an state
a) Wait
b) Ready‾‾‾‾‾
c) Idle
d) Hold
ANSWER: c
40. input controls the rate at which the character is to be transmitted.
a) System clock
b) Transmitter clock
c) Bus system clock
d) Receiver clock
ANSWER: b
41. input controls the rate at which the character is to be received.
a) System clock
b) Transmitter clock
c) Bus system clock
d) Receiver clock
ANSWER: d
42. may be used as a general purpose one bit inverting input port.
a) DSR‾‾‾
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
b) DTR‾‾‾
c) RTS‾‾‾
d) CTS‾‾‾
ANSWER: a
43. may be used as a general purpose one bit inverting output port.
a) DSR‾‾‾
b) DTR‾‾‾
c) RTS‾‾‾
d) CTS‾‾‾
ANSWER: b
44. pin of 8251A receives a composite stream of the data to be received by
8251A
a) RXD
b) RXC
c) RXRDY
d) RD
ANSWER: a
45. When a data character is sent to 8251A by the CPU, it adds start bits prior to the serial
data bits , followed by optional parity bit and stop bits using the
mode instruction control word format.
a) Synchronous
b) Asynchronous
c) Both a & b
d) None of the above
ANSWER: b
46. In the character synchronization can be achieved internally or
externally.
a) Synchronous
b) Asynchronous
c) Both a & b
d) None of the above
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
ANSWER: a
47. Once the mode instruction has been written into 8251A and SYNC characters are
inserted internally by 8251A, all the further control words written with
will load command instruction.
a) C/D=0
b) C/D=1
c) C‾/D=1
d) C/D‾=1
ANSWER: d
48. O/P also may be used as a general purpose one bit inverting O/P portthat
can be programmed low to indicate the modem.
a) RTS‾‾‾
b) DTR‾‾‾
c) CTS‾‾‾
d) All of the above
ANSWER: a
49. is used to generate internal device timings and normally connected toclock
generator.
a) CLK
b) CLK reset
c) CLK set
d) None
ANSWER: a
50. is active low input to 8251A is used to inform it that the CPU is readingeither
data or status information from its internal register.
a) RD
b) BD
c) CS
d) WR
ANSWER: a
Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008
Allenhouse Institute of Technology (UPTU Code : 505)
https://www.youtube.com/playlist?list=PLqisrLSFbMDIToRo6KCX2RARjofFGJ4B
P
Rooma, Kanpur – 208 008
1. Intel’s programmable device (8253) facilitates
thegeneration of accurate time delays.
a) counter
b) timer
c) both a & b
d) none of
theseANSWER:
c
2. The programmable timer device (8253) contains three independent
bit counters.
a) 8
b) 16
c) 20
d) 32
ANSWER: b
3. The 8-bit data buffer interfaces internal circuit of 8253
tomicroprocessor systems bus.
a) Unidirectional
b) Single
c) Bidirectional
d) None of
theseANSWER: c
4. The three counters available in 8253 are independent of each other
inoperation, but they are to each other in organisation.
a) Similar
b) Opposite
c) Identical
d) Common
ANSWER: c
5. The speciality of the 8253 counters is that they can be easily read on
line without disturbing the input to the counter.
a) GATE
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b) CLK Institute of Technology (UPTU Code : 505)
c) OUT Rooma, Kanpur – 208 008
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d) WR
ANSWER: b
6. The GATE signal is and should be for
normal counting.
a) Active Low, Low
b) Normal, Normal
c) Active High, High
d) None of the Above
ANSWER: c
7. When GATE goes low counting is terminated and the current count is
till the GATE again goes high.
a) Disturb
b) Latched
c) Decrease
d) Increase
ANSWER: b
8. If N is loaded as the count value, then, after N pulses, the output
becomeslow only for clock cycle.
a) One
b) Zero
c) N
d) (N-1)
ANSWER: a
9. In this mode, the 8253 can be used as a wave rate generator.
a) Sine wave
b) Cosine wave
c) Square wave
d) All of these
e) ANSWER: c
10.When count is N loaded in , then for half of the count,
theoutput remains high and for remaining half it remain low.
a) Odd
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c) Even-even
d) Odd-odd
ANSWER: b
11. If the count loaded is odd the first clock cycle pulse decrement by
resulting in an even count value.
a) 0
b) 1
c) -1
d) None of
theseANSWER:
12. The processor 8085 had hardware interrupt pins.
a) 4
b) 5
c) 6
d) 8
ANSWER: b
13.The predecessor 8259 was designed to operate only with bit
processors like 8085.
a) 4
b) 8
c) 16
d) 20
ANSWER: b
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14.A Institute ofwas
modified version, Technology
later introduced(UPTU
that isCode
compatible
: 505)
with 8-bit as well as 16-bit.
Rooma, Kanpur – 208 008
a) 8259
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b) 8359
c) 8259A
d) 8359A
ANSWER: c
15. stores all the interrupt requests in it in order to serve them
oneby one on the priority basis.
a) IRR
b) ISR
c) IMR
d) NMI
ANSWER: a
16. keeps a track of the requests being served.
a) IRR
b) ISR
c) IMR
d) NMI
ANSWER: b
17. stores the bits required to mask the interrupt input.
a) IRR
b) ISR
c) IMR
d) NMI
ANSWER: c
18. pin is an active low write enable input to 8259A
a) WR
b) WR‾‾
c) Both a & b
d) None of
theseANSWER:
b
19.Allenhouse Institute ofthe
In Cascade Buffer/Comparator Technology
same pins act as inputs
(UPTU when
Code : 505)
the8259A is in Rooma, Kanpur – 208 008
a) Master
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b) Slave
c) Master-Slave
d) All of these
ANSWER: b
20. goes high whenever a valid interrupt request is asserted.
a) INT pin
b) NMI pin
c) IRR pin
d) ISR pin
ANSWER: a
21. as inputs to accept interrupt requests to the CPU.
a) IR₀-IR₇
b) CR₀-CR₇
c) DR₀-DR₇
d) TS₀-TS₇
ANSWER: a
22. In an based system , A₁₅-A₈ of the interrupt vector address
arethe respective bits of ICW₂.
a) 8008
b) 8080
c) 8085
d) 8086
ANSWER: c
23. In an 8086/88 based system of the interrupt vector address
areinserted in place of T₇ -T₃ respectively.
a) A₁₅-A₁₁
b) A₁₅-A₈
c) A₁₅-A₁₃
d) A₁₅-A₅
ANSWER: a
24. Special fully nested mode is selected, if SFNM= .
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a) 0
b) -1
c) 1
d) None
ANSWER: c
25. If AEOI= , the automatic end of interrupt mode is selected.
a) 1
b) 0
c) -1
d) None
ANSWER: a
26. is the default mode of operation of 8259A.
a) Real mode
b) AEOI (automatic end of interrupt mode)
c) EOI(end of interrupt mode)
d) Fully Nested mode
ANSWER: d
27. If bit LTIM of ICW₁=0 , they are triggered
a) Edge
b) Level
c) Both a & b
d) None of
theseANSWER: a
28. The I/O section is enabled only if CS‾‾
Is
a) High
b) Low
c) Very high
d) Very low
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ANSWER: b
29. RD‾‾/WR‾‾ input pins enable the data buffers to receive or send data
overthe bus.
a) Address
b) Data
c) Both a & b
d) None of
these
ANSWER: b
30. are used to scan the key board matrix and display digits.
a) SL₀-SL₃
b) RL₀-RL₃
c) CL₀-CL₃
d) All of these
ANSWER: a
31. O/P pin is used to blank the display during digit switching or
by a blanking command.
a) BD
b) BS
c) BD‾‾
d) BS‾‾
ANSWER: c
32. Scanned Keyboard Mode in encoded scan keyboard or
indecode scan a
Keyboard can be interfaced.a)
8*8,4*8
b) 4*8,8*8
c) 4*4,8*8
d) 8*4,4*8
ANSWER: a
33. Scanned Keyboard Special Error Mode is valid only under the
key rollover Mode.
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a) 1
b) 50
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c) N-1
d) N
ANSWER: d
34. The 8-byte FIFO RAM now acts as bit memory matrix.
a) 4*4
b) 4*8
c) 8*8
d) 8*4
ANSWER: c
35. In the left entry mode, the data is entered from the side of display
unit.
a) Left
b) Right
c) Front
d) Back
ANSWER: a
36. In the right entry mode, the data is entered from the side of
display unit.
a) Left
b) Right
c) Front
d) Back
ANSWER: b
37. In mode, data is transmitted only in one direction over a
singlecommunication channel.
a) Simplex
b) Duplex
c) Half duplex
d) Half simplex
ANSWER: a
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38. input pins, together with RD‾‾ and WR‾‾ inputs,
informs the 8251A that the word on the data bus is either a data or
controlword/status information.
a) C/D-control Word/Data
b) C/D‾-control Word/Data
c) C‾/D-control Word
d) C‾/D‾-control
Word/DataANSWER: b
39.A high on RESET input forces the 8251A into an state
a) Wait
b) Ready‾‾‾‾‾
c) Idle
d) Hold
ANSWER: c
40. input controls the rate at which the character is to
betransmitted.
a) System clock
b) Transmitter clock
c) Bus system clock
d) Receiver clock
ANSWER: b
41. input controls the rate at which the character is to be
received.
a) System clock
b) Transmitter clock
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c) Bus system clock of Technology (UPTU Code : 505)
d) Receiver clock Rooma, Kanpur – 208 008
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ANSWER: d
42. may be used as a general purpose one bit inverting input
port.
a) DSR‾‾‾
b) DTR‾‾‾
c) RTS‾‾‾
d) CTS‾‾‾
ANSWER: a
43. may be used as a general purpose one bit inverting output
port.
a) DSR‾‾‾
b) DTR‾‾‾
c) RTS‾‾‾
d) CTS‾‾‾
ANSWER: b
44. pin of 8251A receives a composite stream of the data to
bereceived by 8251A
a) RXD
b) RXC
c) RXRDY
d) RD
ANSWER: a
45. When a data character is sent to 8251A by the CPU, it adds start bits
priorto the serial data bits , followed by optional parity bit and stop bits
using the mode instruction control word format.
a) Synchronous
b) Asynchronous
c) Both a & b
d) None of the
aboveANSWER: b
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46. In the character synchronization can be
achievedinternally or externally.
a) Synchronous
b) Asynchronous
c) Both a & b
d) None of the
aboveANSWER: a
47. Once the mode instruction has been written into 8251A and SYNC
characters are inserted internally by 8251A, all the further control
wordswritten with will load command instruction.
a) C/D=0
b) C/D=1
c) C‾/D=1
d) C/D‾=1
ANSWER: d
48. O/P also may be used as a general purpose one bit
invertingO/P port that can be programmed low to indicate the
modem.
a) RTS‾‾‾
b) DTR‾‾‾
c) CTS‾‾‾
d) All of the above
ANSWER: a
49. is used to generate internal device timings and
normallyconnected to clock generator.
a) CLK
b) CLK reset
c) CLK set
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ANSWER: a Rooma, Kanpur – 208 008
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50. is active low input to 8251A is used to inform it that the CPU is
reading either data or status information from its internal register.
a) RD
b) BD
c) CS
d) WR
ANSWER: a
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8237
Rooma, Kanpur – 208 008
1. 8237 contains three basic blocks of its operational logic.
a. Timing block
b. Control block
c. Program command control block
d. All of d above”
2. Which block generates the internal timings and external control signals.
a. Bus interface unit
b. Execution unit
c. Timing and control block”
d. None of the above
3. Each of 4 DMA channels of 8237 has bit current address register.a.
16”
b. 32
c. 64
d. 124
4. register holds the current memory address
a. Current address register”
b. Current word register
c. Both
d. None of the above
5. register holds the no of data byte transfers to be carried out
a. Current word register”
b. Count segment
c. Only a
d. Both
6. These maintain an original copy of respective initial current register and current word registerbefore
incrementing or decrementing
a. Mode register
b. Base address and base word count registers”
c. Only b
d. Both
7. register controls the complete operation of 8237
a. Code register
b. Count register
c. Command register”
d. None of the above
8. Command register is bit
a. 16
b. 32
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c. 8”
d. 64
9. Command register is programmed by and cleared by .
a. CPU , reset”
b. ALU
c. BIU
d. None of the above
10. In mode register bits and determine which of the 4 channels mode register are to be written
a. 0 and 1”
b. 2 and 3
c. 1 and 0
d. None of the above
11. Bits and indicate the type of DMA transfer
a. 0 and 1
b. 2 and 3”
c. 1 and 0
d. None of the above
12. Bit indicates whether address incremented or address decremented mode is selected
a. 0
b. 5”
c. 3
d. 2
13. register is nonmaskable and subject to prioritization by the priority resolving network of 8237
a. Request register”
b. Command register
c. Mode register
d. Both b and c
14. register holds data during memory –memory data transfer
a. Temporary register”
b. Command register
c. Mode register
d. None of the above
15. register keeps the track of all DMA channel pending requests and the status of terminal counts
a. Temporary register
b. Command register
c. Mode register
d. Status register”
16. bits are set if channels request services
a. D4-D7”
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b. D0-D3
c. None of the above
17. signal is required for deriving the internal timings requiredfpr circuit operations
a. GND
b. CLK”
c. READY
d. RESET
18. High on this input line clears the command, status, request and temporary register
a. RESET”
b. CLK
c. READY
d. none
19. this active- high input is used to match the read or write speed of 8237 with slow memories or i/odevices
a. READY”
b. RESET
c. CLK
d. None
20. Signal used to indicate that cpu has relinquished the control of the bus, as a response to bus request
a. HLDA”
b. READY
c. RESET
d. CLK
21. DREQo has priority
a. Highest”
b. Lowest
c. None of these
22. DREQ3 has priority
a. Lowest”
b. Highest
c. None
23. Data bus is lines used to transfer data to /from I/O or memory
a. Unidirectional
b. Bidirectional”
c. None
24. An output pin used to request te control of the system bus from cpu
a. HRQ”
b. HOLD
c. HLDA
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d. CLK
25. An active low bidirectional pin used to indicate the completion of DMA operation
a. HRQ
b. HOLD
c. EOP”
d. CLK
26. 8237 operates in 2 cycles
a. Idle, passive
b. Idle, active
c. Passive, active
d. Both b and c”
27. are actual working states of DMA operation in which the actual data transfer is carried outa.
S0,S1,S2,S3
b. S1,S2,S3,S4”
c. S0,S1
d. S2,S3
28. pin is used to disable other bus drivers during DMA transfer
a. AEN”
b. HRQ
c. HLDA
d. HOLD
29. This output line is used to strobe the upper address byte generated by 8237, in master mode into ,an
external latch
a. ADSTB”
b. AEN
c. READY
d. HLDA
30. In single transfer mode the device transfers only byte per second
a. 1”
b. 2
c. 4
d. 8
31. In this mode, 8237 is activated by DEREQ to continue the transfer until a block of data istransferred
a. Demand mode
b. Block transfer mode”
c. Cascade mode
d. None
32. In this mode more than one 8237 can be connected together.
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a. Block transfer mode
b. Cascade mode”
c. Demand mode
d. All of the above
33. The transfer of a block of data from one set of memory address to another one is done using mode
a. Memory to Memory transfer”
b. Demand mode
c. Block transfer mode
d. Cascade mode
34. 8237 can be connected together to provide more than four DMA channels
a. 1
b. More than 1”
c. Both
d. None
35. Channel 0 current address register acts as a pointer
a. Source”
b. Destination
c. Both
d. None of these
36. Channel 1 current address register acts as a pointer
a. Source
b. Destination”
c. None of these
37. 8237 carries out three basic transfers namely-
a. Write transfer
b. Read transfer
c. Verify transfer
d. All of the above”
38. There exists an flip-flop in 8237 also which is called first/last flip flop
a. External
b. Internal”
c. Slave
d. None
39. Output of these flip flop decides whether the byte of selected 16-bit register will be read or written
a. First/last flip-flop”
b. Internal
c. External
d. None
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40. Selected register means register
a. Current address register
b. Current word count register
c. Both
d. None
41. By clearing the first/last flip-flop the will address the higher or lower byte in appropriate
sequence
a. BIU
b. Execution unit
c. CPU”
d. Control unit
42. Mask set register when set, may the DMA cannels so that DMA requests are not entertained
a. Enabled
b. Disabled”
c. Reset
d. None
43. command will clear the bits of mask register individually or collectively
a. Mask set register
b. Clear mask register”
c. Clear register
d. None
44. To enable the DMA channels register clears the bits of mask register
a. Mask register
b. Clear register
c. Clear mask register”
d. None
45. All internal registers of 8237 are cleared using this command
a. Clear mask register
b. Mask register
c. Clear first/last flip-flop
d. Master clear command”
46. Master clear command clears integral register , while all the bits of mask register are
a. Reset
b. Set”
c. Enabled
d. None
47. DMA controller disables all the DMA channels and enters an cycle
a. Idle”
b. Wait
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c. Ready
d. None
48. In transfers, the 8237 works in the same way as read or write transfer but does not
generateany control signal
a. Read transfer
b. Write transfer
c. Both
d. Verify”
49. In transfer the 8237 reads from an I/O device and writes to the memory
a. Read transfer
b. Write transfer”
c. Both
d. Verify
50. In transfer the 8237 reads from the memory and writes to an I/O device
a. Read transfer”
b. Write transfer
c. Both
d. Verify
e.
Multiple Choice Questions and Answers:-
1) Which is the microprocessor comprises: a.Register section
b.One or more ALU c.Control unit
d.All of these Answer:D
2) What is the store by register? a.data
b.operands c.memory d.None of these Answer:A
3) Accumulator based microprocessor example are: a.Intel 8085
b.Motorola 6809
c.A and B d.None of these Answer:C
4) A set of register which contain are: a.data
b.memory addresses c.result
d.all of these Answer:D
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5) There are primarily two types of register: a.general purpose register
b.dedicated register
c.A and B d.none of these Answer:C
6) Name of typical dedicated register is: a.PC
b.IR c.SP
d.All of these Answer:D
7) BCD stands for: a.Binary coded decimal
b.Binary coded decoded
a & b d.none of these Answer:A
8) Which is used to store critical pieces of data during subroutines and interrupts: a.Stack
b.Queue c.Accumulator d.Data register Answer:A
9) The data in the stack is called:
a.Pushing data b.Pushed c.Pulling d.None of these Answer:A
10) The external system bus architecture is created using from architecture:
a.Pascal
b.Dennis Ritchie c.Charles Babbage d.Von Neumann Answer:D
11) The processor 80386/80486 and the Pentium processor uses bits address bus:
a.16
b.32 c.36 d.64
Answer:B
12) Which is not the control bus signal: a.READ
b.WRITE c.RESET
d.None of these Answer:C
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13) PROM stands for: a.Programmable read-only memory b.Programmable read write
memory c.Programmer read and write memory d.None of these
Answer:A
14) EPROM stands for:
a.Erasable Programmable read-only memory
b.ectrically Programmable read write memory c.Electrically Programmable read-only memory
d.None of these
Answer:A
15) Each memory location has: a.Address
b.Contents c.Both A and B d.None of these Answer:C
16) Which is the type of microcomputer memory: a.Processor memory
b.Primary memory c.Secondary memory d.All of these Answer:D
17) Secondary memory can store : a.Program store code
b.Compiler c.Operating system
d.All of these Answer:D
18) Secondary memory is also called :
a.Auxiliary b.Backup store c.Both A and B d.None of these Answer:C
19 Customized ROMS are called:
a.Mask ROM b.Flash ROM c.EPROM
d.None of these Answer:A
20) The RAM which is created using bipolar transistors is called: a.Dynamic RAM
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b.Static RAM c.Permanent RAM d.DDR RAM
Answer:B
21) Which type of RAM needs regular referred:
a.Dynamic RAM b.Static RAM c.Permanent RAM d.SD RAM
Answer:A
22) Which RAM is created using MOS transistors:
a.Dynamic RAM b.Static RAM c.Permanent RAM d.SD RAM
Answer:A
23) A microprocessor retries instructions from :
a.Control memory b.Cache memory c.Main memory d.Virtual memory Answer:C
24) The lower red curvy arrow show that CPU places the address extracted from the
memory
location on the :
a.Address bus b.System bus c.Control bus d.Data bus Answer:A
25) The CPU sends out a signal to indicate that valid data is available on the data
bus: a.Read
b.Write
c.Both A and B d.None of these Answer:B
26) The CPU removes the signal to complete the memory write operation: a.Read
b.Write
c.Both A and B d.None of these Answer:A
27) BIU STAND FOR: a.Bus interface unit b.Bess interface unit
c.A and B
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d.None of these Answer:A
28) EU STAND FOR:
a.Execution unit b.Execute unit
c.Exchange unit d.None of these Answer:A
29) Which are the four categories of registers: a.General- purpose register
b.Pointer or index registers c.Segment registers d.Other register
e.All of these Answer:E
30) Eight of the register are known as: a.General- purpose register
b.Pointer or index registers c.Segment registers d.Other register
Answer:A
31) The four index register can be used for: a.Arithmetic operation
b.Multipulation operation c.Subtraction operation d.All of these
Answer:A
32) IP Stand for: a.Instruction pointer b.Instruction purpose c.Instruction paints d.None of
these Answer:A
33) CS Stand for: a.Code segment b.Coot segment c.Cost segment d.Counter segment
Answer:A
34) DS Stand for: a.Data segment
b.Direct segment c.Declare segment d.Divide segment Answer:A
35) Which are the segment:
a. CS: Code segment
b. DS: data segment
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c. SS: Stack segment
d. ES:extra segment e.All of these Answer:D
36) The acculatator is 16 bit wide and is called: a.AX
b.AH c.AL d.DL
Answer:A
37) How many bits the instruction pointer is wide:
a.16 bit
b.32 bit
c.64 bit
Answer:A
38) How many type of addressing in memory:
a.Logical address b.Physical address c.Both A and B d.None of these Answer:C
39) The size of each segment in 8086 is:
a.64 kb
b.24 kb
c.50 kb d.16kb Answer:A
40) The address of a memory is a 20 bit address for the 8086 microprocessor:
a.Physical
b.Logical c.Both
d.None of these Answer:A
41) The pin configuration of 8086 is available in the :
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a.40 pin
b.50 pin
c.30 pin
d.20 pin Answer:A
42) DIP stand for: a.Deal inline package b.Dual inline package c.Direct inline package
d.Digital inline package Answer:B
43) EA stand for: a.Effective address b.Electrical address c.Effect address d.None of
these Answer:A
44) BP stand for: a.Bit pointer
b.Base pointer c.Bus pointer d.Byte pointer Answer:B
45) DI stand for: a.Destination index b.Defect index c.Definition index d.Delete index
Answer:A
46) SI stand for: a.Stand index b.Source index c.Segment index d.Simple index Answer:B
47) ALE stand for: a.Address latch enable b.Address light enable c.Address lower enable
d.Address last enable
48) NMI stand for:
a.Non mask able interrupt b.Non mistake interrupt c.Both
d.None of these Answer:A
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49) is the most important segment and it contains the actual assembly language
instruction to be executed by the microprocessor:
a.Data segment b.Code segment c.Stack segment d.Extra segment Answer:B
50) The offset of a particular segment varies from : a.000H to FFFH
b.0000H to FFFFH c.00H to FFH d.00000H to FFFFFH
Answer:B
51) Which are the factor of cache memory:
a.Architecture of the microprocessor b.Properties of the programs being executed c.Size
organization of the cache
d.All of these Answer:D
52) is usually the first level of memory access by the microprocessor: a.Cache
memory
b.Data memory c.Main memory d.All of these Answer:A
53) Which is the small amount of high- speed memory used to work directly with the
microprocessor:
a.Cache b.Case c.Cost d.Coos Answer:A
54) The cache usually gets its data from the whenever the instruction or data is
required by the CPU:
a.Main memory b.Case memory c.Cache memory d.All of these Answer:A
55) Microprocessor reference that are available in the cache are called : a.Cache hits
b.Cache line c.Cache memory d.All of these Answer:A
56) Microprocessor reference that are not available in the cache are called : a.Cache hits
b.Cache line c.Cache misses d.Cache memory Answer:C
57) Which causes the microprocessor to immediately terminate its present activity:
a.RESET signal
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b.INTERUPT signal
d.None of these Answer:A
58) Which is responsible for all the outside world communication by the microprocessor:
a.BIU
b.PIU c.TIU d.LIU
Answer:A
59) INTR: it implies the signal:
a. INTRRUPT REQUEST
b. INTRRUPT RIGHT
c. INTRRUPT RONGH
d. INTRRUPT RESET
Answer:A
60) Which of the following are the two main components of the CPU? a.Control Unit and
Registers
b.Registers and Main Memory c.Control unit and ALU
d.ALU and bus Answer:C
61) Different components n the motherboard of a PC unit are linked together by sets of
parallel electrical conducting lines. What are these lines called?
a.Conductors b.Buses c.Connectors d.Consecutives Answer:B
62) The language that the computer can understand and execute is called a.Machine
language
b.Application software c.System program d.All of the above Answer:A
63) Which of the following is used as a primary storage device? a.Magnetic drum
b.PROM
c.Floppy disk d.All of these Answer:B
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64) Which of the following memories needs refresh?
b.DRAM c.ROM
d.All of above Answer:B
65) The memory which is programmed at the time it is manufactured a.PROM
b.RAM c.PROM d.EPROM
Answer:A
66) Which of the following memory medium is not used as main memory system?
a.Magnetic core
b.Semiconductor c.Magnetic tape d.Both a and b Answer:C
67) Registers, which are partially visible to users and used to hold conditional, are known
as
b.Memory address registers c.General purpose register d.Flags
Answer:C
68) One of the main feature that distinguish microprocessors from micro-computers is
a.Words are usually larger in microprocessors
b.Words are shorter in microprocessors c.Microprocessor does not contain I/O devices
d.Exactly the same as the machine cycle time Answer:C
69) The first microprocessor built by the Intel Corporation was called a.8008
b.8080 c.4004 d.8800
Answer:C
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70) An integrated circuit is
a.A complicated circuit b.An integrating device
c.Much costlier than a single transistor
d.Fabricated on a tiny silicon chip Answer:D
71) Most important advantage of an IC is its a.Easy replacement in case of circuit failure
b.Extremely high reliability
c.Reduced cost
d.Low powers consumption Answer:B
72) Which of the following items are examples of storage devices? a.Floppy / hard disks
b.CD-ROMs
c.Tape devices d.All of the above Answer:D
73) The Width of a processor’s data path is measured in bits. Which of the following are
common
data paths?
a.8 bits
b.12 bits
c.16 bits
d.32 bits
74) Which is the type of memory for information that does not change on your computer?
a.RAM
b.ROM c.ERAM d.RW / RAM
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Answer:B
75) What type of memory is not directly addressable by the CPU and requires special
softw3are called EMS (expanded memory specification)?
a. Extended b.Expanded c.Base d.Conventional Answer:B
76) Before a disk can be used to store data. It must be……. a.Formatted
b.Reformatted c.Addressed
d.None of the above Answer:A
77) Which company is the biggest player in the microprocessor industry? a.Motorola
b. IBM
c. Intel d.AMD
Answer:C
78) A typical personal computer used for business purposes would have… of RAM.
a.4 KB
b.16 K
c.64 K
d.256 K Answer:D
78) The word length of a computer is measured in a.Bytes
b.Millimeters c.Meters d.Bits Answer:D
79) What are the three decisions making operations performed by the ALU of a computer?
a.Grater than
b.Less than
d.All of the above Answer:D
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80) Which part of the computer is used for calculating and comparing? a.Disk unit
b.Control unit c.ALU
d.Modem Answer:C
81) Can you tell what passes into and out from the computer via its ports? a.Data
b.Bytes c.Graphics d.Pictures Answer:A
82) What is the responsibility of the logical unit in the CPU of a computer? a.To produce
result
b.To compare numbers
c.To control flow of information d.To do math’s works
83) The secondary storage devices can only store data but they cannot perform
a.Arithmetic Operation
b.Logic operation c.Fetch operations d.Either of the above Answer:D
84) Which of the following memories allows simultaneous read and write operations?
a.ROM
b.RAM c.EPROM
d.None of above Answer:B
85) Which of the following memories has the shortest access times? a.Cache memory
b.Magnetic bubble memory c.Magnetic core memory d.RAM
Answer:A
86) A 32 bit microprocessor has the word length equal to
b.32 byte
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c.4 byte
d.8 byte Answer:C
87) An error in computer data is called a.Chip
b.Bug c.CPU
d.Storage device Answer:B
88) The silicon chips used for data processing are called a.RAM chips
b. ROM chips
c. Micro processors
d. PROM chips Answer:D
89) The metal disks, which are permanently housed in, sealed and contamination free
containers
are called a.Hard disks
b.Floppy disk c.Winchester disk d.Flexible disk Answer:C
90) A computer consists of
a.A central processing unit
b.A memory
c.Input and output unit d.All of the above Answer:D
91) The instructions for starting the computer are house on a.Random access memory
b.CD-Rom
c.Read only memory chip d.All of above
Answer:C
92) The ALU of a computer normally contains a number of high speed storage element
called a.Semiconductor memory
b.Registers c.Hard disks d.Magnetic disk
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93) The first digital computer built with IC chips was known as a.IBM 7090
b.Apple – 1
c.IBM System / 360 d.VAX-10
Answer:C
94) Which of the following terms is the most closely related to main memory? a.Non
volatile
b.Permanent c.Control unit d.Temporary Answer:D
95) Which of the following is used for manufacturing chips? a.Control bus
b.Control unit c.Parity unit d.Semiconductor Answer:D
96) To locate a data item for storage is
b.Feed c.Database d.Fetch Answer:D
97) A directly accessible appointment calendar is feature of a … resident package a.CPU
b.Memory c.Buffer d.ALU
Answer:B
98) The term gigabyte refers to a.1024 bytes
b.1024 kilobytes c.1024 megabytes d.1024 gigabyte Answer:C
99) A/n …. Device is any device that provides information, which is sent to the CPU a.Input
b.Output c.CPU
d.Memory Answer:A
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100) Current SIMMs have either … or … connectors (pins)
a.9 or 32
b.30 or 70
c.28 or 72
d.30 or 72 Answer:D
8086 Microprocessor
1. A microprocessor is a chip integrating all the functions of a CPU of a computer.
A. multiple B. single C. double D. triple ANSWER: B
2. Microprocessor is a/an circuit that functions as the CPU of the compute
A. electronic B. mechanic C. integrating D. processing ANSWER: A
3. Microprocessor is the of the computer and it perform all the computational tasks
A. main B. heart C. important D. simple ANSWER: B
4. The purpose of the microprocessor is to control
A. memory B. switches C. processing D. tasks ANSWER: A
5. The first digital electronic computer was built in the year
A. 1950 B. 1960 C. 1940 D. 1930 ANSWER: C
6. In 1960's texas institute invented
A. integrated circuits B. microprocessor C. vacuum tubes D. transistors
ANSWER: A
7. The intel 8086 microprocessor is a processor
A. 8 bit B. 16 bit C. 32 bit D. 4 bit ANSWER: B
8. The microprocessor can read/write 16 bit data from or to
A. memory B. I /O device C. processor D. register ANSWER: A
9. In 8086 microprocessor , the address bus is bit wide
A. 12 bit B. 10 bit C. 16 bit D. 20 bit ANSWER: D
10. The work of EU is
A. encoding B. decoding C. processing D. calculations ANSWER: B
11. The 16 bit flag of 8086 microprocessor is responsible to indicate
A. the condition of result of ALU operation B. the condition of memory
C. the result of addition D. the result of subtraction ANSWER: A
12. The CF is known as
A. carry flag B. condition flag C. common flag D. single flag
.ANSWER: A
13. The SF is called as
A. service flag B. sign flag C. single flag D. condition flag ANSWER: B
14. The OF is called as
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A. overflow flag B. overdue flag C. one flag D. over flag ANSWER: A
15. The IF is called as
A. initial flag B. indicate flag C. interrupt flag D. inter flag ANSWER: C
16. The register AX is formed by grouping
A. AH & AL B. BH & BL C. CH & CL D. DH & DL ANSWER: A
17. The SP is indicated by
A. single pointer B. stack pointer C. source pointer D. destination pointer
ANSWER: B
18. The BP is indicated by
A. base pointer B. binary pointer C. bit pointer D. digital pointer ANSWER: A
19. The SS is called as
A. single stack B. stack segment C. sequence stack .D. random stack ANSWER:
B
20. The index register are used to hold
A. memory register B. offset address C. segment memory D. offset memory
ANSWER: A
21. The BIU contains FIFO register of size bytes
A. 8 B. 6 C. 4 D. 12 ANSWER: B
22. The BIU prefetches the instruction from memory and store them in
A. queue B. register C. memory D. stack ANSWER: A
23. The 1 MB byte of memory can be divided into segment
A. 1 Kbyte B. 64 Kbyte C. 33 Kbyte D. 34 Kbyte ANSWER: B
24. The DS is called as
A. data segment B. digital segment C. divide segment D. decode segment
ANSWER: A
25. The CS register stores instruction in code segment
A. stream B. path C. codes D. stream line ANSWER: C
26. The IP is bits in length
A. 8 bits B. 4 bits C. 16 bits D. 32 bits ANSWER: C
27. The push source copies a word from source to
A. stack B. memory C. register D. destination ANSWER: A
28. LDs copies to consecutive words from memory to register and
A. ES B. DS C. SS D. CS ANSWER: B
29. INC destination increments the content of destination by
A. 1 B. 2 C. 30 D. 41 ANSWER: A
30. IMUL source is a signed
A. multiplication B. addition C. subtraction D. division ANSWER: A
31. destination inverts each bit of destination
A. NOT B. NOR C. AND D. OR ANSWER: A
32. The JS is called as
A. jump the signed bit B. jump single bit
C. jump simple bit D. jump signal it ANSWER: A
33. Instruction providing both segment base and offset address are called
A. below type .B. far type C. low type D. high type ANSWER: B
34. The conditional branch instruction specify for branching
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A. conditions B. instruction C. address D. memory ANSWER: A
35. The microprocessor determines whether the specified condition exists or not by testing
the
A. carry flag B. conditional flag C. common flag D. sign flag ANSWER: B
36. The LES copies to words from memory to register and
A. DS B. CS C. ES D. DS ANSWER: C
37. The translates a byte from one code to another code
A. XLAT B. XCHNG C. POP D. PUSH ANSWER: A
38. The contains an offset instead of actual address
A. SP B. IP C. ES D. SS ANSWER: B
39. The 8086 fetches instruction one after another from of memory
A. code segment B. IP C. ES D. SS ANSWER: A
40. The BIU contains FIFO register of size 6 bytes called .
A. queue B. stack C. segment D. register ANSWER: A
41. The is required to synchronize the internal operands in the processor CLK Signal
A. UR Signal B. Vcc C. AIE D. Ground ANSWER: A
42. The pin of minimum mode AD0-AD15 has address
A. 16 bit B. 20 bit C. 32 bit D. 4 bit ANSWER: B
43. The pin of minimum mode AD0- AD15 has _ data bus
A. 4 bit B. 20 bit C. 16 bit D. 32 bit ANSWER: C
44. The address bits are sent out on lines through
A. A16-19 B. A0-17 C. D0-D17 D. C0-C17 ANSWER: A
45. is used to write into memory
A. RD B. WR C. RD / WR D. CLK ANSWER: B
46. The functions of Pins from 24 to 31 depend on the mode in which is
operating A. 8085 B. 8086 C. 80835 D. 80845
ANSWER: B
47. The RD, WR, M/IO is the heart of control for a mode
A. minimum B. maximum C. compatibility mode D. control mode ANSWER:
A
48. In a minimum mode there is a on the system bus
A. single B. double C. multiple D. triple ANSWER: A
49. If MN/MX is low the 8086 operates in mode
A. Minimum B. Maximum C. both (A) and (B) D. medium ANSWER: B
50. In max mode, control bus signal So,S1 and S2 are sent out in form
A. decoded B. encoded C. shared D. unshared ANSWER: B
51. The bus controller device decodes the signals to produce the control bus signal
A. internal B. data C. external D. address ANSWER: C
52. A Instruction at the end of interrupt service program takes the execution back to
the interrupted program
A. forward B. return C. data D. line ANSWER: B
53. The main concerns of the are to define a flexible set of commands
A. memory interface B. peripheral interface
C. both (A) and (B) D. control interface
.ANSWER: A
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54. Primary function of memory interfacing is that the should be able to read from and
write into register
A. multiprocessor B. microprocessor C. dual Processor D. coprocessor
ANSWER: B
55. To perform any operations, the Mp should identify the
A. register B. memory C. interface D. system ANSWER: A
56. The Microprocessor places address on the address bus
A. 4 bit B. 8 bitC. 16 bit D. 32 bit ANSWER: C
57. The Microprocessor places 16 bit address on the add lines from that address by
register should be selected
A. address B. one C. two D. three ANSWER: B
58. The of the memory chip will identify and select the register for the EPROM
A. internal decoder B. external decoder C. address decoder D. data decoder
ANSWER: A
59. Microprocessor provides signal like to indicate the read operatio
A. LOW B. MCMW C. MCMR D. MCMWR ANSWER: C
60. To interface memory with the microprocessor, connect register the lines of the address
bus must be added to address lines of the chip.
A. single B. memory C. multiple D. triple ANSWER: B
61. The remaining address line of bus is decoded to generate chip select signal
A. data B. address C. control bus D. both (a) and (b) ANSWER: B
62. signal is generated by combining RD and WR signals with IO/M
A. control B. memory C. register D. system ANSWER: A
63. Memory is an integral part of a system
A. supercomputer B. microcomputer
C. mini computer D. mainframe computer ANSWER: B
64. has certain signal requirements write into and read from its registers
A. memory B. register C. both (a) and (b) D. control ANSWER: A
65. An is used to fetch one address
A. internal decoder B. external decoder C. encoder D. register ANSWER: A
66. The primary function of the is to accept data from I/P devices
A. multiprocessor B. microprocessor C. peripherals D. interfaces ANSWER: B
67. signal prevent the microprocessor from reading the same data more than one
A. pipelining B. handshaking C. controlling D. signaling ANSWER: B
68. Bits in IRR interrupt are
A. reset B. set C. stop D. start ANSWER: B
69. generate interrupt signal to microprocessor and receive acknowledge
A. priority resolver B. control logic
C. interrupt request register D. interrupt register ANSWER: B
70. The pin is used to select direct command word
A. A0 B. D7-D6 C. A12 D. AD7-AD6 ANSWER: A
71. The is used to connect more microprocessor
A. peripheral device B. cascade C. I/O devices D. control unit ANSWER: B
72. CS connect the output of
A. encoder B. decoder C. slave program D. buffer ANSWER: B
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73. In which year, 8086 was introduced?
A. 1978 B. 1979 C. 1977 D. 1981 ANSWER: A
74. Expansion for HMOS technology_
A. high level mode oxygen semiconductor
B. high level metal oxygen semiconductor
C. high performance medium oxide semiconductor
D. high performance metal oxide semiconductor ANSWER: D
75. 8086 and 8088 contains transistors
A. 29000 B. 24000 C. 34000 D. 54000 ANSWER: A
76. ALE stands for
A. address latch enable B. address level enable
C. address leak enable D. address leak extension ANSWER: A
77. What is DEN?
A. direct enable B. data entered C. data enable D. data encoding ANSWER:
C
78. In 8086, Example for Non maskable interrupts are .
A. TRAP B. RST6.5 C. INTR D. RST6.6 ANSWER: A
79. In 8086 the overflow flag is set when .
A. the sum is more than 16 bits.
B. signed numbers go out of their range after an arithmetic operation.
C. carry and sign flags are set.
D. subtraction ANSWER: B
80. In 8086 microprocessor the following has the highest priority among all type
interrupts?
A. NMI B. DIV 0 C. TYPE 255 D. OVER FLOW ANSWER: A
81. In 8086 microprocessor one of the following statements is not true?
A. coprocessor is interfaced in max mode. B. coprocessor is interfaced in min mode.
C. I /O can be interfaced in max / min mode. D. supports pipelining ANSWER: B
82. Address line for TRAP is?
A. 0023H B. 0024H C. 0033H D. 0099H ANSWER: B
83. Access time is faster for .
A. ROM B. SRAM C. DRAM D. ERAM ANSWER: B
84. The First Microprocessor was .
A. Intel 4004 B. 8080 C. 8085 D. 4008 ANSWER: A
85. Status register is also called as .
A. accumulator B. stack C. counter D. flags ANSWER: D
86. Which of the following is not a basic element within the microprocessor?
A. Microcontroller B. Arithmetic logic unit (ALU)
C. Register array D. Control unit Ans.: A
87. Which method bypasses the CPU for certain types of data transfer?
A. Software interrupts B. Interrupt-driven I/O
C. Polled I/O D. Direct memory access (DMA) Ans.: D
88. Which bus is bidirectional?
A. Address bus B. Control bus
C. Data bus D. None of the above Ans.: C
89. The first microprocessor had a(n) .
A. 1 – bit data bus B. 2 – bit data bus
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C. 4 – bit data bus D. 8 – bit data bus Ans.: C
90. Which microprocessor has multiplexed data and address lines?
A. 8086 B. 80286 C. 80386 D. Pentium
Ans.: A
91. Which is not an operand?
A. Variable B. Register C. Memory location D. Assembler Ans.: D
92. Which is not part of the execution unit (EU)?
A. Arithmetic logic unit (ALU) B. Clock
C. General registers D. Flags Ans.: B
93. A 20-bit address bus can locate .
A. 1,048,576 locations B. 2,097,152 locations
C. 4,194,304 locations D. 8,388,608 locations Ans.: A
94. Which of the following is not an arithmetic instruction?
A. INC (increment) B. CMP (compare)
C. DEC (decrement) D. ROL (rotate left) Ans.: D
95. During a read operation the CPU fetches _.
A. a program instruction B. another address
C. data itself D. all of the above
Ans.: D
96. Which of the following is not an 8086/8088 general-purpose register?
A. Code segment (CS) B. Data segment (DS)
C. Stack segment (SS) D. Address segment (AS) Ans.: D
97. A 20-bit address bus allows access to a memory of capacity
A. 1 MB B. 2 MB C. 4 MB D. 8 MB Ans.: A
98. Which microprocessor accepts the program written for 8086 without any changes? A.
8085 B. 8086 C. 8087 D. 8088
Ans.: D
99. Which group of instructions do not affect the flags?
A. Arithmetic operations B. Logic operations
C. Data transfer operations D. Branch operations Ans.: C
100. The result of MOV AL, 65 is to store
A. store 0100 0010 in AL B. store 42H in AL
C. store 40H in AL D. store 0100 0001 in AL Ans.: D
8255
Question 1: How many pins does the 8255 PPI IC contains?
a. 24
b. 20
c. 32
d. 40
Answer: d. 40
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Question 2: In which mode do all the Ports of the 8255 PPI work as Input-Output units for
data transfer?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: b. Mode 0 of I/O mode
Question 3: Which of the following pins are responsible for handling the on the Read Write
control logic unit of the 8255 PPI?
a. CS'
b. RD'
c. WR'
d. ALL of the above
Answer: d. All of the above
Question 4: In which of the following modes is the 8255 PPI capable of transferring data while
handshaking with the interfaced device?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: c. Mode 1 of I/O mode
Question 5: How many bits of data can be transferred between the 8255 PPI and the
interfaced device at a time? or What is the size of internal bus of the 8255 PPI?
a. 16 bits
b. 12 bits
c. 8 bits
d. None of the above
Answer: c. 8 bits
Question 6: Which port of the 8255 PPI is capable of performing the handshaking function
with the interfaced devices?
a. Port A
b. Port B
c. Port C
d. All of the above
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Answer: c. Port C
Question 7: In which of the following modes of the 8255 PPI, only port C is taken into
consideration?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: a. BSR mode
Question 8: In mode 2 of I/O mode, which of the following ports are capable of transferring
the data in both the directions?
a. Port A
b. Port B
c. Port C
d. All of the above
Answer: a. Port A
Question 9: In which of the following modes we do not consider the D6, D5 and D4 bits of the
control word?
a. BSR mode
Question 10: How many data lines in total are there in the 8255 PPI IC?
a. 8 data lines
b. 32 data lines
c. 24 data lines
d. None of the above
Answer: c. 24 data lines
Question 11: PPI 8255 is a general purpose programmable I/O device designed to interface
the CPU with its outside world such as ADC, DAC, keyboard etc.
a. True
b. False Answer: a. True Explanation:
PPI 8255 is a general purpose programmable I/O device which is specifically designed to
interface the CPU with its outside world such as ADC, DAC, keyboard etc.
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Question 12: During process a data bus buffer has controlled using,
a. Control word register
b. Data bus
c. R/W control logic
d. None of these Answer: b. Data bus Explanation:
During process a data bus buffer has controlled using read/write control logic.
Question 13: The 8255 ports works in the I/O mode,
a. Programmable I/O ports
b. Set pins
c. Reset pins
The 8255 ports work in the I/O mode as programmable I/O ports.
Question 14: PPI 8255 consists of three 8-bit bidirectional I/O ports,
a. PORT A,
b. PORT B
c. PORT C
d. All of these Answer: d. All of these Explanation:
PPI 8255 consists of three 8-bit bidirectional I/O ports as PORT A, PORT B, and PORT C.
Question 15: PPI 8255 consists of 40 pins and operates in ... regulated power supply,
a. +5V
b. +15V
c. +5V
d. None of these Answer: a. +5V Explanation:
PPI 8255 consists of 40 pins and operates in +5V regulated power supply.
Question 16: Strobed input/output mode is also known as -
a. Mode 0
b. Mode 1
c. Mode 2
d. None of these Answer: b. Mode 1 Explanation:
In this mode, the input or output operation of the specified port is controlled by handshaking
signals.
c. Mode 2
d. None of these Answer: b. Mode 1 Explanation:
In this mode, the handshaking signals control the input or output action of the specified port.
Question 18: The pulse width of the INIT signal at the receiving terminal must be greater than
... that of the receiving terminal –
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a. 10 microseconds
b. 50 microseconds
c. 40 microseconds
d. 20 microseconds Answer: b. 50 microseconds Explanation:
The pulse width of a signal at the receiving terminal must be more than 50 microseconds.
Question 19: The feature of mode 2 of 8255 is,
a. Both inputs and outputs are latched
b. Port C is used for generating handshake signals
c. Single 8-bit port is available
d. All of these Answer: d. All of these Explanation:
A single 8-bit port is available in mode 2 of 8255, i.e., group A.
Question 20: The port which is used in mode 1 or mode 2 for the generation of handshake
lines is,
a. Port A
b. Port B
c. Port C Upper
d. Port C Lower Answer: d. Port C Lower Explanation:
The upper Port C is used for the generation of mode 1 or mode 2 handshake lines.
Question 21: The pin that clears the control word register of 8255 when enabled is,
a. RESET
b. SET
c. CLEAR
d. CLK Answer: a. RESET Explanation:
If the reset pin is allowed, then the register of control words is cleared.
Question 22: The signals that are provided to maintain proper data flow and synchronization
between the data transmitter and receiver are –
a. Handshaking signals
b. Control signals
c. Input signals
d. None of these
Answer: a. Handshaking signals Explanation:
Handshaking signals preserve proper flow and synchronization of information. In order to
create a valid link between two stations, signals are transmitted back and forth via a
communications network. In an RS-232 serial transmission, a "hardware handshake" utilizes
dedicated wires such as request-to-send (RTS) and clear-to-send (CTS) lines.
Question 23: From pin PA0 – PA7 are the part of -
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a. Pins of port A
b. Pins of port B
c. Pins of port C
d. None of these Answer: a. Pins of port A Explanation:
There are 24 input/output pins for the 8255. These are split into three ports that are 8-bit (A,
B, C). It is possible to use Port A and Port B as 8-bit input/output ports. Pins of port A consist
pins from pin PA0 – PA7.Port C can be used either as an 8-bit input/output port or as two 4-
bit input/output ports or for ports A and B to create handshake signals.
Question 24: In the pin diagram of PIP 8255, CS stands for Chip select,
a. True
b. False Answer: a. True Explanation:
In the pin diagram of PIP 8255, CS stands for Chip select. Chip selection (CS) or slave
selection (SS) is the name of a digital electronics control line used to select one (or a set) of
integrated circuits (commonly referred to as 'chips') out of many connected to the same device
bus, typically using three-state logic.
Question 25: If MSB of control word (D7) is 0, PPI works in BSR mode.
a. True
b. False Answer: a. True Explanation:
If MSB of control word (D7) is 0, PPI works in BSR mode.
Intel’s programmable device (8253) facilitates the generation of accurate time delays.
a) counter
b) timer
c) both a & b
d) none of these
ANSWER: c
2. The programmable timer device (8253) contains three independent bit counters.
a) 8
b) 16
c) 20
d) 32
ANSWER: b
3. The 8-bit data buffer interfaces internal circuit of 8253 to microprocessor systems
bus.
a) Unidirectional
b) Single
c) Bidirectional
d) None of these
ANSWER: c
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4. The three counters available in 8253 are independent of each other in operation, but
they are to each other in organisation.
a) Similar
b) Opposite
c) Identical
d) Common
ANSWER: c
5. The speciality of the 8253 counters is that they can be easily read on line
without disturbing the _ input to the counter.
a) GATE
b) CLK
c) OUT
d) WR
ANSWER: b
6. The GATE signal is and should be for normal counting.
a) Active Low, Low
b) Normal, Normal
c) Active High, High
d) None of the Above
ANSWER: c
7. When GATE goes low counting is terminated and the current count is till the GATE
again goes high.
a) Disturb
b) Latched
c) Decrease
d) Increase
ANSWER: b
8. If N is loaded as the count value, then, after N pulses, the output becomes low only
for clock cycle.
a) One
b) Zero
c) N
d) (N-1)
ANSWER: a
9. In this mode, the 8253 can be used as a wave rate generator.
a) Sine wave
b) Cosine wave
c) Square wave
d) All of these
e) ANSWER: c
10. When count is N loaded in , then for half of the count, the output remains high and
for remaining half it remain low.
a) Odd
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b) Even
c) Even-even
d) Odd-odd
ANSWER: b
11. If the count loaded is odd the first clock cycle pulse decrement by resulting in
an even count value.
a) 0
b) 1
c) -1
d) None of these
ANSWER: b
12. The processor 8085 had hardware interrupt pins.
a) 4
b) 5
c) 6
d) 8
ANSWER: b
13. The predecessor 8259 was designed to operate only with bit processors like
8085.
a) 4
b) 8
c) 16
d) 20
ANSWER: b
14. A modified version, was later introduced that is compatible with 8-bit as well as 16-
bit.
a) 8259
b) 8359
c) 8259A
d) 8359A
ANSWER: c
15. stores all the interrupt requests in it in order to serve them one by one on the
priority basis.
a) IRR
b) ISR
c) IMR
d) NMI
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ANSWER: a
16. keeps a track of the requests being served.
a) IRR
b) ISR
c) IMR
d) NMI
ANSWER: b
17. stores the bits required to mask the interrupt input.
a) IRR
b) ISR
c) IMR
d) NMI
ANSWER: c
18. pin is an active low write enable input to 8259A
a) WR
b) WR‾‾
c) Both a & b
d) None of these
ANSWER: b
19. In Cascade Buffer/Comparator the same pins act as inputs when the 8259A is in
a) Master
b) Slave
c) Master-Slave
d) All of these
ANSWER: b
20. goes high whenever a valid interrupt request is asserted.
a) INT pin
b) NMI pin
c) IRR pin
d) ISR pin
ANSWER: a
21. as inputs to accept interrupt requests to the CPU.
a) IR₀-IR₇
b) CR₀-CR₇
c) DR₀-DR₇
d) TS₀-TS₇
ANSWER: a
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22. In an based system , A₁₅-A₈ of the interrupt vector address are the respective bits of
ICW₂.
a) 8008
b) 8080
c) 8085
d) 8086
ANSWER: c
23. In an 8086/88 based system of the interrupt vector address are inserted in
place of T₇ -T₃ respectively.
a) A₁₅-A₁₁
b) A₁₅-A₈
c) A₁₅-A₁₃
d) A₁₅-A₅
ANSWER: a
24. Special fully nested mode is selected, if SFNM= .
a) 0
b) -1
c) 1
d) None
ANSWER: c
25. If AEOI= , the automatic end of interrupt mode is selected.
a) 1
b) 0
c) -1
d) None
ANSWER: a
26. is the default mode of operation of 8259A.
a) Real mode
b) AEOI (automatic end of interrupt mode)
c) EOI(end of interrupt mode)
d) Fully Nested mode
ANSWER: d
27. If bit LTIM of ICW₁=0 , they are triggered
a) Edge
b) Level
c) Both a & b
d) None of these
ANSWER: a
28. The I/O section is enabled only if CS‾‾ Is
a) High
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b) Low
c) Very high
d) Very low
ANSWER: b
29. RD‾‾/WR‾‾ input pins enable the data buffers to receive or send data over the
bus.
a) Address
b) Data
c) Both a & b
d) None of these
ANSWER: b
30. are used to scan the key board matrix and display digits.
a) SL₀-SL₃
b) RL₀-RL₃
c) CL₀-CL₃
d) All of these
ANSWER: a
31. O/P pin is used to blank the display during digit switching or by a
blanking command.
a) BD
b) BS
c) BD‾‾
d) BS‾‾
ANSWER: c
32. Scanned Keyboard Mode in encoded scan keyboard or in decode scan a
Keyboard can be interfaced. a) 8*8,4*8
b) 4*8,8*8
c) 4*4,8*8
d) 8*4,4*8
ANSWER: a
33. Scanned Keyboard Special Error Mode is valid only under the key rollover Mode.
a) 1
b) 50
c) N-1
d) N
ANSWER: d
34. The 8-byte FIFO RAM now acts as bit memory matrix.
a) 4*4
b) 4*8
c) 8*8
d) 8*4
ANSWER: c
35. In the left entry mode, the data is entered from the side of display unit.
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a) Left
b) Right
c) Front
d) Back
ANSWER: a
36. In the right entry mode, the data is entered from the side of display unit.
a) Left
b) Right
c) Front
d) Back
ANSWER: b
37. In mode, data is transmitted only in one direction over a single communication
channel.
a) Simplex
b) Duplex
c) Half duplex
d) Half simplex
ANSWER: a
38. input pins, together with RD‾‾ and WR‾‾ inputs, informs the 8251A that the word
on the data bus is either a data or control word/status information.
a) C/D-control Word/Data
b) C/D‾-control Word/Data
c) C‾/D-control Word
d) C‾/D‾-control Word/Data
ANSWER: b
39. A high on RESET input forces the 8251A into an state
a) Wait
b) Ready‾‾‾‾‾
c) Idle
d) Hold
ANSWER: c
40. input controls the rate at which the character is to be transmitted.
a) System clock
b) Transmitter clock
c) Bus system clock
d) Receiver clock
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ANSWER: b
41. input controls the rate at which the character is to be received.
a) System clock
b) Transmitter clock
c) Bus system clock
d) Receiver clock
ANSWER: d
42. may be used as a general purpose one bit inverting input port.
a) DSR‾‾‾
b) DTR‾‾‾
c) RTS‾‾‾
d) CTS‾‾‾
ANSWER: a
43. may be used as a general purpose one bit inverting output port.
a) DSR‾‾‾
b) DTR‾‾‾
c) RTS‾‾‾
d) CTS‾‾‾
ANSWER: b
44. pin of 8251A receives a composite stream of the data to be received by 8251A
a) RXD
b) RXC
c) RXRDY
d) RD
ANSWER: a
45. When a data character is sent to 8251A by the CPU, it adds start bits prior to the serial
data bits , followed by optional parity bit and stop bits using the mode instruction
control word format.
a) Synchronous
b) Asynchronous
c) Both a & b
d) None of the above
ANSWER: b
46. In the character synchronization can be achieved internally or externally.
a) Synchronous
b) Asynchronous
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c) Both a & b
d) None of the above
ANSWER: a
47. Once the mode instruction has been written into 8251A and SYNC characters are
inserted internally by 8251A, all the further control words written with
will load command instruction.
a) C/D=0
b) C/D=1
c) C‾/D=1
d) C/D‾=1
ANSWER: d
48. O/P also may be used as a general purpose one bit inverting O/P port that can
be programmed low to indicate the modem.
a) RTS‾‾‾
b) DTR‾‾‾
c) CTS‾‾‾
d) All of the above
ANSWER: a
49. is used to generate internal device timings and normally connected to clock
generator.
a) CLK
b) CLK reset
c) CLK set
d) None
ANSWER: a
50. is active low input to 8251A is used to inform it that the CPU is reading either
data or status information from its internal register.
a) RD
b) BD
c) CS
d) WR
ANSWER: a
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1. Intel’s programmable device (8253) facilitates the generation of accurate time delays.
a) counter
b) timer
c) both a & b
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d) none of these ANSWER: c
2. The programmable timer device (8253) contains three independent
bit counters.
a) 8
b) 16
c) 20
d) 32
ANSWER: b
3. The 8-bit data buffer interfaces internal circuit of 8253 to microprocessor systems
bus.
a) Unidirectional
b) Single
c) Bidirectional
d) None of these ANSWER: c
4. The three counters available in 8253 are independent of each other in operation, but
they are to each other in organisation.
a) Similar
b) Opposite
c) Identical
d) Common ANSWER: c
5. The speciality of the 8253 counters is that they can be easily read on line
without disturbing the input to the counter.
a) GATE
b) CLK
c) OUT
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d) WR ANSWER: b
6. The GATE signal is and should be for normal counting.
a) Active Low, Low
b) Normal, Normal
c) Active High, High
d) None of the Above ANSWER: c
7. When GATE goes low counting is terminated and the current count is
till the GATE again goes high.
a) Disturb
b) Latched
c) Decrease
d) Increase ANSWER: b
8. If N is loaded as the count value, then, after N pulses, the output becomes low only
for clock cycle.
a) One
b) Zero
c) N
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d) (N-1) ANSWER: a
9. In this mode, the 8253 can be used as a wave rate generator.
a) Sine wave
b) Cosine wave
c) Square wave
d) All of these
e) ANSWER: c
10. When count is N loaded in , then for half of the count, the output remains high and
for remaining half it remain low.
a) Odd
b) Even
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c) Even-even
d) Odd-odd ANSWER: b
11. If the count loaded is odd the first clock cycle pulse decrement by
resulting in an even count value.
a) 0
b) 1
c) -1
d) None of these ANSWER: b
12. The processor 8085 had hardware interrupt pins.
a) 4
b) 5
c) 6
d) 8 ANSWER: b
13. The predecessor 8259 was designed to operate only with bit processors like
8085.
a) 4
b) 8
c) 16
d) 20 ANSWER: b
14.A modified version, was later introduced that is compatible with 8-bit as well as 16-
bit.
a) 8259
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b) 8359
c) 8259A
d) 8359A ANSWER: c
15. stores all the interrupt requests in it in order to serve them one by one on the
priority basis.
a) IRR
b) ISR
c) IMR
d) NMI ANSWER: a
16. keeps a track of the requests being served.
a) IRR
b) ISR
c) IMR
d) NMI ANSWER: b
17. stores the bits required to mask the interrupt input.
a) IRR
b) ISR
c) IMR
d) NMI ANSWER: c
18. pin is an active low write enable input to 8259A
a) WR
b) WR‾‾
c) Both a & b
d) None of these ANSWER: b
19. In Cascade Buffer/Comparator the same pins act as inputs when the 8259A is in
a) Master
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b) Slave
c) Master-Slave
d) All of these ANSWER: b
20. goes high whenever a valid interrupt request is asserted.
a) INT pin
b) NMI pin
c) IRR pin
d) ISR pin ANSWER: a
21. as inputs to accept interrupt requests to the CPU.
a) IR₀-IR₇
b) CR₀-CR₇
c) DR₀-DR₇
d) TS₀-TS₇ ANSWER: a
22. In an based system , A₁₅-A₈ of the interrupt vector address are the respective bits of
ICW₂.
a) 8008
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b) 8080
c) 8085
d) 8086 ANSWER: c
23. In an 8086/88 based system of the interrupt vector address are inserted in
place of T₇ -T₃ respectively.
a) A₁₅-A₁₁
b) A₁₅-A₈
c) A₁₅-A₁₃
d) A₁₅-A₅ ANSWER: a
24. Special fully nested mode is selected, if SFNM= .
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a) 0
b) -1
c) 1
d) None ANSWER: c
25. If AEOI= , the automatic end of interrupt mode is selected.
a) 1
b) 0
c) -1
d) None ANSWER: a
26. is the default mode of operation of 8259A.
a) Real mode
b) AEOI (automatic end of interrupt mode)
c) EOI(end of interrupt mode)
d) Fully Nested mode ANSWER: d
27. If bit LTIM of ICW₁=0 , they are triggered
a) Edge
b) Level
c) Both a & b
d) None of these ANSWER: a
28. The I/O section is enabled only if CS‾‾ Is
a) High
b) Low
c) Very high
d) Very low
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ANSWER: b
29. RD‾‾/WR‾‾ input pins enable the data buffers to receive or send data over the bus.
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a) Address
b) Data
c) Both a & b
d) None of these ANSWER: b
30.
a) SL₀-SL₃
are used to scan the key board matrix and display digits.
b) RL₀-RL₃
c) CL₀-CL₃
d) All of these ANSWER: a
31. O/P pin is used to blank the display during digit switching or
by a blanking command.
a) BD
b) BS
c) BD‾‾
d) BS‾‾ ANSWER: c
32. Scanned Keyboard Mode in encoded scan keyboard or in decode scan a
Keyboard can be interfaced. a) 8*8,4*8
b) 4*8,8*8
c) 4*4,8*8
d) 8*4,4*8 ANSWER: a
33. Scanned Keyboard Special Error Mode is valid only under the key rollover
Mode.
a) 1
b) 50
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c) N-1
d) N ANSWER: d
34. The 8-byte FIFO RAM now acts as bit memory matrix.
a) 4*4
b) 4*8
c) 8*8
d) 8*4 ANSWER: c
35. In the left entry mode, the data is entered from the side of display unit.
a) Left
b) Right
c) Front
d) Back ANSWER: a
36. In the right entry mode, the data is entered from the side of display unit.
a) Left
b) Right
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c) Front
d) Back ANSWER: b
37. In mode, data is transmitted only in one direction over a single communication
channel.
a) Simplex
b) Duplex
c) Half duplex
d) Half simplex ANSWER: a
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38. input pins, together with RD‾‾ and WR‾‾ inputs, informs the 8251A that the
word on the data bus is either a data or control word/status information.
a) C/D-control Word/Data
b) C/D‾-control Word/Data
c) C‾/D-control Word
d) C‾/D‾-control Word/Data ANSWER: b
39.A high on RESET input forces the 8251A into an state
a) Wait
b) Ready‾‾‾‾‾
c) Idle
d) Hold ANSWER: c
40. input controls the rate at which the character is to be transmitted.
a) System clock
b) Transmitter clock
c) Bus system clock
d) Receiver clock ANSWER: b
41. input controls the rate at which the character is to be received.
a) System clock
b) Transmitter clock
c) Bus system clock
d) Receiver clock
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ANSWER: d
42.
port.
a) DSR‾‾‾
b) DTR‾‾‾
c) RTS‾‾‾
d) CTS‾‾‾ ANSWER: a
43.
port.
may be used as a general purpose one bit inverting input
may be used as a general purpose one bit inverting output
a) DSR‾‾‾
b) DTR‾‾‾
c) RTS‾‾‾
d) CTS‾‾‾ ANSWER: b
44. pin of 8251A receives a composite stream of the data to be received by 8251A
a) RXD
b) RXC
c) RXRDY
d) RD ANSWER: a
45. When a data character is sent to 8251A by the CPU, it adds start bits prior to the serial
data bits , followed by optional parity bit and stop bits using the mode instruction control
word format.
a) Synchronous
b) Asynchronous
c) Both a & b
d) None of the above ANSWER: b
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46. In the character synchronization can be achieved internally or externally.
a) Synchronous
b) Asynchronous
c) Both a & b
d) None of the above ANSWER: a
47. Once the mode instruction has been written into 8251A and SYNC characters are
inserted internally by 8251A, all the further control words written with will load command
instruction.
a) C/D=0
b) C/D=1
c) C‾/D=1
d) C/D‾=1 ANSWER: d
48. O/P also may be used as a general purpose one bit inverting O/P port that can
be programmed low to indicate the modem.
a) RTS‾‾‾
b) DTR‾‾‾
c) CTS‾‾‾
d) All of the above ANSWER: a
49. is used to generate internal device timings and normally connected to clock
generator.
a) CLK
b) CLK reset
c) CLK set
d) None ANSWER: a
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50. is active low input to 8251A is used to inform it that the CPU is reading either
data or status information from its internal register.
a) RD
b) BD
c) CS
d) WR ANSWER: a
1. 8237 contains three basic blocks of its operational logic.
a. Timing block
b. Control block
c. Program command control block
d. All of d above”
2. Which block generates the internal timings and external control signals.
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a. Bus interface unit
b. Execution unit
c. Timing and control block”
d. None of the above
3. Each of 4 DMA channels of 8237 has bit current address register. a. 16”
b. 32
c. 64
d. 124
4. register holds the current memory address
a. Current address register”
b. Current word register
c. Both
d. None of the above
5. register holds the no of data byte transfers to be carried out
a. Current word register”
b. Count segment
c. Only a
d. Both
6. These maintain an original copy of respective initial current register and current word
register before incrementing or decrementing
a. Mode register
b. Base address and base word count registers”
c. Only b
d. Both
7. register controls the complete operation of 8237
a. Code register
b. Count register
c. Command register”
d. None of the above
8. Command register is bit
a. 16
b. 32
c. 8”
d. 64
9. Command register is programmed by and cleared by .
a. CPU , reset”
b. ALU
c. BIU
d. None of the above
10. In mode register bits and determine which of the 4 channels mode register are to
be written
a. 0 and 1”
b. 2 and 3
c. 1 and 0
d. None of the above
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11. Bits and indicate the type of DMA transfer
a. 0 and 1
b. 2 and 3”
c. 1 and 0
d. None of the above
12. Bit indicates whether address incremented or address decremented mode is
selected
a. 0
b. 5”
c. 3
d. 2
13. register is nonmaskable and subject to prioritization by the priority resolving
network of 8237
a. Request register”
b. Command register
c. Mode register
d. Both b and c
14. register holds data during memory –memory data transfer
a. Temporary register”
b. Command register
c. Mode register
d. None of the above
15. register keeps the track of all DMA channel pending requests and the status of
terminal counts
a. Temporary register
b. Command register
c. Mode register
d. Status register”
16. bits are set if channels request services
a. D4-D7”
b. D0-D3
c. None of the above
17. signal is required for deriving the internal timings requiredfpr circuit operations
a. GND
b. CLK”
c. READY
d. RESET
18. High on this input line clears the command, status, request and temporary register
a. RESET”
b. CLK
c. READY
d. none
19. this active- high input is used to match the read or write speed of 8237 with slow
memories or i/o devices
a. READY”
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b. RESET
c. CLK
d. None
20. Signal used to indicate that cpu has relinquished the control of the bus, as a response
to bus request
a. HLDA”
b. READY
c. RESET
d. CLK
21. DREQo has priority
a. Highest”
b. Lowest
c. None of these
22. DREQ3 has priority
a. Lowest”
b. Highest
c. None
23. Data bus is lines used to transfer data to /from I/O or memory
a. Unidirectional
b. Bidirectional”
c. None
24. An output pin used to request te control of the system bus from cpu
a. HRQ”
b. HOLD
c. HLDA
d. CLK
25. An active low bidirectional pin used to indicate the completion of DMA operation
a. HRQ
b. HOLD
c. EOP”
d. CLK
26. 8237 operates in 2 cycles
a. Idle, passive
b. Idle, active
c. Passive, active
d. Both b and c”
27. are actual working states of DMA operation in which the actual data transfer is
carried out a. S0,S1,S2,S3
b. S1,S2,S3,S4”
c. S0,S1
d. S2,S3
28. pin is used to disable other bus drivers during DMA transfer
a. AEN”
b. HRQ
c. HLDA
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d. HOLD
29. This output line is used to strobe the upper address byte generated by 8237, in master
mode into , an external latch
a. ADSTB”
b. AEN
c. READY
d. HLDA
30. In single transfer mode the device transfers only byte per second
a. 1”
b. 2
c. 4
d. 8
31. In this mode, 8237 is activated by DEREQ to continue the transfer until a block of data
is transferred
a. Demand mode
b. Block transfer mode”
c. Cascade mode
d. None
32. In this mode more than one 8237 can be connected together.
a. Block transfer mode
b. Cascade mode”
c. Demand mode
d. All of the above
33. The transfer of a block of data from one set of memory address to another one is done
using mode
a. Memory to Memory transfer”
b. Demand mode
c. Block transfer mode
d. Cascade mode
34. 8237 can be connected together to provide more than four DMA channels
a. 1
b. More than 1”
c. Both
d. None
35. Channel 0 current address register acts as a pointer
a. Source”
b. Destination
c. Both
d. None of these
36. Channel 1 current address register acts as a pointer
a. Source
b. Destination”
c. None of these
37. 8237 carries out three basic transfers namely-
a. Write transfer
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b. Read transfer
c. Verify transfer
d. All of the above”
38. There exists an flip-flop in 8237 also which is called first/last flip flop
a. External
b. Internal”
c. Slave
d. None
39. Output of these flip flop decides whether the byte of selected 16-bit register will be
read or written
a. First/last flip-flop”
b. Internal
c. External
d. None
40. Selected register means register
a. Current address register
b. Current word count register
c. Both
d. None
41. By clearing the first/last flip-flop the will address the higher or lower byte in
appropriate sequence
a. BIU
b. Execution unit
c. CPU”
d. Control unit
42. Mask set register when set, may the DMA cannels so that DMA requests are not
entertained
a. Enabled
b. Disabled”
c. Reset
d. None
43. command will clear the bits of mask register individually or collectively
a. Mask set register
b. Clear mask register”
c. Clear register
d. None
44. To enable the DMA channels register clears the bits of mask register
a. Mask register
b. Clear register
c. Clear mask register”
d. None
45. All internal registers of 8237 are cleared using this command
a. Clear mask register
b. Mask register
c. Clear first/last flip-flop
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d. Master clear command”
46. Master clear command clears integral register , while all the bits of mask register are
a. Reset
b. Set”
c. Enabled
d. None
47. DMA controller disables all the DMA channels and enters an cycle
a. Idle”
b. Wait
c. Ready
d. None
48. In transfers, the 8237 works in the same way as read or write transfer but
does not generate any control signal
a. Read transfer
b. Write transfer
c. Both
d. Verify”
49. In transfer the 8237 reads from an I/O device and writes to the memory
a. Read transfer
b. Write transfer”
c. Both
d. Verify
50. In transfer the 8237 reads from the memory and writes to an I/O device
a. Read transfer”
b. Write transfer
c. Both
d. Verify
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8085 Microprocessor MCQ | Quiz | Interview Questions
Published March 7, 2020 | Updated April 23, 2020
Contents
Quiz result
Attempt again:
Detailed solutions of the questions
Quiz result
Total Questions: 40
Attempted Questions: 0
Unattempted Questions: 40
Correct Answers: 0
Incorrect Answers: 0
Time spent: 00:03:24
Final Score: 0 / 43
Detailed performance analysis and comparison with other test takers are only available to signed-
up users. Please sign up. It’s free.
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Attempt again:
Detailed solutions of the questions
1. A nibble corresponds to
2 bits
4 bitscorrect
8 bits
16 bits
Question was not answered
2. The 8085 has five sign flags
True
Falsecorrect
Question was not answered
The 8085 has 5 flags, the sign flag is one of them. Read more about 8085’s flag register here.
3. The Z flag is set when an ALU operation results in a 0 output
Truecorrect
False
Question was not answered
The zero flag will be set (1/HIGH) when the answer of an ALU operation is 0.
4. Assertion (A): Microprocessor 8085 has an on-chip oscillator with an inbuilt crystal.
Reason (R): For frequency stability crystal oscillator is preferred.
Both A and R are correct and R is the correct explanation of A
Both A and R are correct but R is not the correct explanation of A
A is correct R is wrong
A is wrong R is correctcorrect
Question was not answered
The 8085 doesn’t have an inbuilt crystal. We’ve to connect one externally.
5. If the source and destination addresses are made implicit the length of instruction is reduced.
Truecorrect
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False
Question was not answered
6. Which of the following has volatile memory?
Magnetic Tape
RAMcorrect
Hard Disk
Diskette
Question was not answered
RAM loses all it’s contents when the device is powered down.
7. If a microprocessor uses a 5 MHz oscillator. The duration of one T state is
1 μs
0.333 μs
0.2 μs correct
2 μs
Question was not answered
1/(5 x 106 s) = 0.2 x 10-6 s.
8. What type of instructions can potentially change the sequence of operations in a program?
Logical instructions
Data transfer instructions
Branch instructionscorrect
Arithmetic instructions
Question was not answered
9. Seven address and data buses are multiplexed in 8085
True
Falsecorrect
Question was not answered
Eight address and data buses are multiplexed in 8085. AD0-AD7.
10. The Sign flag is set when the contents of the accumulator become negative after an ALU
operation.
Truecorrect
False
Question was not answered
11. Consider the following mnemonics
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1. MOV
2. ADD
3. LXI
4. ADI
1 and 2 only
2 and 3 only
1, 2 and 3 only
1, 2, 3 and 4correct
Question was not answered
1. MOV
– Moves data between registers
2. ADD
– Adds data of register or memory to Accumulator
3. LXI
– Loads 16-bit data to register pair
4. ADI
– Adds data to Accumulator
12. Handshaking programmed data transfer is also known as
Asynchronous transfercorrect
Synchronous transfer
Interrupt driver transfer
Both (a) and (c)
Question was not answered
13. The addressing mode shown in the given figure is
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Immediate addressing mode
Direct addressing mode
Register indirect addressing modecorrect
Register addressing mode
Question was not answered
14. Which of the following 8085 instructions affect all flags except the CY flag?
ADC r
INR r
correct
SEE M
ACI data
Question was not answered
15. The issue of a timing difference between a fast processor and slow memory is resolved by
using a processor that’s capable of waitingcorrect
using an external buffercorrect
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using a coprocessor
none of these
Question was not answered
16. In 8085, the RST instruction will cause an interrupt _______.
only if interrupts have been enabled by the EI (Enable interrupt) instruction
only if the interrupt mask bit is set to 0
only if an ISR is not actively executing
every time it’s executedcorrect
Question was not answered
17. Which of the following are buses present in 8085?
Address Buscorrect
DMA bus
Memory Buscorrect
Control Buscorrect
Question was not answered
Memory Bus is another name for Data Bus. There is no separate bus for DMA, it uses the data bus
to transfer data.
18. The values of odd and even parity flags are ___ and ___ respectively
0, 1correct
1, 0
0, 0
1, 1
Question was not answered
19. Which mode of Data Transfer Schemes (DTS) has the highest efficiency?
Cycle stealing modecorrect
Burst mode
None
Both
Question was not answered
In cycle stealing mode a long block of data is transferred in multiple sequences of DMA cycles.
After the transfer of one/several bytes, the I/O device withdraws the DMA request. In fact, this
method is capable of working exactly when there are free cycles left when the CPU is not using the
system bus. Hence, it is the most efficient.
20. The content of the HL pair after the execution of the following instructions is ___.
XRA A
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MOV L, A
MOV H, L
INX H
DAD H
0000H
0001H
0011H
0002Hcorrect
Question was not answered
XRA resets the accumulator. Move the contents of accumulator to L (00). Move that to H.
Increment H by 1. DAD adds H to HL and gives 0002H.
21. A stack pointer stores the ____.
Address of bottom of stack
Address of instruction being executed
Address of instruction to be executed
Address of top of stackcorrect
Question was not answered
22. The register which holds the information about the nature of results of arithmetic and logic
operations is called as
Condition code register
Accumulator
Flag registercorrect
Process status register
Question was not answered
23. An 8-bit microprocessor signifies that the processor has an
8-bit data buscorrect
8-interrupt lines
8-bit controller
8-bit address bus
Question was not answered
24. What is the purpose of the READY signal in 8085
It’s used to provide WAIT states when the 8085 is communicating with a slow peripheral
devicecorrect
It indicates that the 8085 is ready to receive inputs
It indicates that the 8085 is ready to provide Direct Memory Access
It indicates that the 8085 is ready to send outputs
Question was not answered
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25. For memory mapped I/O, which of the following is true?
Devices are accessed using IN and OUT instructions
Devices have 8-bit address line
There can be maximum of 256 input devices and 256 output devices
Arithmetic and logic operations can be directly performed with the I/O datacorrect
Question was not answered
26. RST0 – RST7 are the __________ in 8085.
hardware interrupts
logical interrupts
software interrupts
correct
conditional interrupts
Question was not answered
27. The Program Counter (PC) in a microprocessor is used to
specify the address of the instruction to be executedcorrect
specify the address of the instruction currently executing
specify the number of instructions executed
none of these
Question was not answered
28. Upon the execution of the RET instruction:
PC gets incremented
control goes directly to the next instruction after the calling instruction without any
operation
control goes directly to the next instruction after the calling instruction without any
operation and also PC will get incremented
top of the stack will get popped and get assigned to the PCcorrect
Question was not answered
29. POP B is a
1 byte instructioncorrect
2 byte instruction
3 byte instruction
4 byte instruction
Question was not answered
30. If you wish to save the value of the accumulator on the stack, which of the following instruction
will you use?
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PUSH PSWcorrect
PUSH A
POP PSW
PUSH SP
Question was not answered
PUSH PSW adds the contents of the accumulator and the flag register to the stack.
31. All jump/branch instructions in 8085 use ___________ addressing
Absolutecorrect
Immediate
Indirect
Implicit
Question was not answered
Absolute addressing mode is also known as Direct addressing mode.
32. Stack pointer is stored in
RAM
ROM
either RAM/ROM
Microprocessorcorrect
Question was not answered
33.
Which of the following is not true during the execution of an interrupt service routine, which does
not contain any EI instructions
the microprocessor can be interrupted by a non-mask able interrupt
the microprocessor cannot be interrupted by any interruptcorrect
the microprocessor cannot be interrupted by any maskable interrupt
all interrupts except non-maskable interrupt are disabled
Question was not answered
EI (Enable Interrupt) instruction should be provided at the beginning of any program so that it can
respond to any interrupts.
34.
After the execution of CMP A instruction
ZF is set and CY is unchanged
ZF is reset and CY is set
ZF is set and CY is resetcorrect
ZF is reset and CY is unchanged
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Question was not answered
35.
The 8085 microprocessor enters into bus idle machine cycle whenever
RST 7.5 is recognizedcorrect
INTR interrupt is recognized
DAD RP instruction is executed
none of the above
Question was not answered
36.
The content of the A15-A8 (higher-order address lines) while executing “IN 8-bit port address”
instruction are
irrelevant
all bits reset (i.e. 00H)
all bits set (i.e. FFH)
same as the content of A7-A0correct
Question was not answered
“IN 8-bit port address” is an 8-bit port address. The maximum port range is up to (FF)H. For
executing this instruction the high order (A15-A8) port address is duplicated to low order (A7 -A0)
port address. So high order address bus has the same content as low order address bus.
37. Select the correct statement(s). In 8085, the data bus and the address bus are multiplexed in
order to:
Increase the speed of the microprocessor
Reduce the number of pinscorrect
Connect more peripheral chips
Reduce power consumption
Question was not answered
For the 8085, multiplexing of pins actually slows down the processor. However, this might not be
the case for every microprocessor. In fact, modern microprocessor latch speeds are high enough to
remove the effect on speed due to multiplexing.
38. Both, the ALU and the control section of 8085 employs which special-purpose storage location?
Registers
Decoders
Buffers
Accumulatorcorrect
Question was not answered
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39. What will be the value in the memory location 7101H after the execution of the following code?
The data at memory location 7100 is A7H.
LXI H,7100H
MOV A, M
CMA
INR A
STA 7101H
HLT
59Hcorrect
58H
5AH
none of these
Question was not answered
CMA takes 1’s complement. INR makes it a 2’s complement.
40. A programmer’s model is ____.
list of all I/O devices that can be connected
diagrams of the internal bus architecture
part of the block diagram that a programmer can affect using the instruction setcorrect
the entire block diagram
Question was not answered
91. If the accumulator of an Intel 8085A microprocessor contains 37 H and the previous operation
has set the carry flag, the instruction ACI 56 H will result in
a.8E H
b.94H
c.7E H
d.84 H
Answer. a
92. Examine the following instruction to be executed by a 8085 microprocessor. The input port has
an address of 01 h and has a data 05 h to input:
IN 01 H
ANI 80 H
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After the execution of the two instructions the following flag portions may occur:
1. Zero flag is set
2. Zero flag is reset
3. Carry flag is cleared
4. Auxiliary carry flag is set
Select the correct answer using the codes given below:
a.1 and 3
b.2, 3 and 4
c.1, 3 and 4
d.1, 2 and 4
Answer. c
93. For 8085 microprocessor, the instruction RST 6 restarts subroutine at address
a. 00 H
b. 03 H
c. 30 H
d. 33 H
Answer. c
94. Which one of the following function is performed by the 8085 instruction MOV H, C?
a.Moves the contents of H register to C register
b.Moves the contents of C register to H register
c.Moves the contents of C register to HL pair
d.Moves the contents of HL pair to C register
Answer. b
95. Consider the execution of the following instructions by an 8085 microprocessor:
LXI H, 01FF H
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SHLD 2050H
After execution, the contents of memory locations 2050H and 2051 H and the registers H and L, will
be
a.2050 H→ FF; 2051 H→ 01 ; H→ FF; L→ 01
b.2050 H→ 01; 2051 H→ FF ; H→ FF; L→ 01
c.2050 H→ FF; 2051 H→ 01 ; H→ 01; L→ FF
d.2050 H→ FF; 2051 H→ 01 ; H→ 00; L→ 00
Answer. c
96. When RET instruction is executed by any Subroutine then
a. the top of the stack will be popped out and assigned to the PC
b. without any operation, the calling program would resume from instruction immediately
following the call instruction
c. the PC will be incremented after the execution of the instruction
d. without any operation, the calling program would resume from instruction immediately following
t the call instruction, and also the PC will be incremented after the execution of the instruction
Answer. a
97. An 8085 microprocessor-based system uses a 4 K x 8-bit RAM whose starting address is AA00
H. The address of the last byte in this RAM is
a. 0FFF H
b. 1000 H
c. B9FF H
d. BA00 H
Answer. c
98. The address bus of Intel 8085 is 16-bit wide and hence the memory which can be accessed by
this address bus is
a. 2 k bytes
b. 4 k bytes
c. 16 k bytes
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d. 64 k bytes
Answer. d
99. An example of 8085 instruction that uses direct addressing is
a. RLC
b. STA
c. RRC
d. CMA
Answer. b
100. A 16 bit memory address register can address memory locations of
a. 16 k
b. 32 k
c. 64 k
d. 128 k
Answer. c
71. Carry flag is not affected after the execution of
a.ADD B
b.SBB B
c.INR B
d.ORA B
Answer. c
72. The contents of the Program Counter (PC), when the microprocessor is reading from 2FFF H
memory location, will be
a.2FFE H
b.2FFF H
c.3000 H
d.3001 H
Answer. c
73. If the HLT instruction of an Intel 8085A microprocessor is executed
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a.the microprocessor is disconnected from the system bus till the RESET is pressed.
b.the microprocessor halts the execution of the program and returns to the monitor.
c.the microprocessor enters into a HALT state and the buses are tri-stated.
d.the microprocessor reloads the program counter from the locations 0024 H and 0025 H.
Answer. c
74. The stack pointer of an 8085 A microprocessor contains ABCD H.
1.PUSH PSW
2.XTHL
3.PUSH D
4.JMP EC75 H
At the end of the execution of the above instructions, what would be the content of the stack pointer?
a.ABCB H
b.ABCA H
c.ABC9 H
d.ABC8 H
Answer. c
75. In an Intel 8085 A, what is the content of the Instruction Register (IR)?
a.Op-code for the instruction being executed
b.Operand for the instruction being executed
c.Op-code for the instruction to be executed next
d.Operand for the instruction to be executed next
Answer. a
76. The content of the Program Counter of an intel 8085A microprocessor specifies which one of the
following?
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a.The address of the instruction being executed
b.The address of the instruction executed earlier
c.The address of the next instruction to be executed
d.The number of instructions executed so far
Answer. c
77. Which one of the following statement does not describe property/characteristic of a stack pointer
register in 8085 microprocessor?
a.It points to the top of the stack.
b.It is UP/DOWN counter
c.It is automatically initialized to 0000 H on power-on
d.It is a 16-bit register
Answer. c
78. Which one of the following instructions is a 3-byte instruction?
a.MVI A
b.LDAX B
c.JMP 2050 H
d.MOV A,M
Answer. c
79. In 8085, the DAA instruction is used for
a.Direct Address Accumulator
b.Double Add Accumulator
c.Decimal Adjust Accumulator
d.Direct Access Accumulator
Answer. c
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80. When an 8086 executes an INT type instruction, it?
a.Resets both IF and TF flags
b.Resets all flags
c.Sets both IF and TF
d.Resets the CF and TF
Answer. a
81. How many times will the following loop be executed?
LXI B, 0010 H
LOOP: DCX B
MOV A, B
ORA C
JNZ LOOP
Select the correct answer using the code given below:
a.10
b.100
c.16
d.15
Answer. c
82. On execution of the following segment 0f instructions in sequence
MVI A, 91H
XRI 91 H
Which one of the following is correct?
a.Content of accumulator is 00 H. Carry, Auxiliary Carry and Zero flag set to 0, 1 and 0, respectively.
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b.Content of accumulator is 91 H. Carry, Auxiliary Carry and Zero flag set to 0, 0 and 1, respectively.
c.Content of accumulator is 00 H. Carry, Auxiliary Carry and Zero flag set to 0, 0 and 1, respectively.
d.Content of accumulator is 91 H. Carry, Auxiliary Carry and Zero flag set to 0, 1 and 0, respectively.
Answer. c
83. Consider the following statements:
1. Indirect addressing is not possible for mapped I/O port addresses
2. Pointers can not be used to access memory-mapped I/O addresses
3. Fewer machine instructions can be used with I/O mapped I/O addressing as compared to memory
mapped I/O addressing
4. With an 8085 microprocessor, one can access at the most 512 devices with unique addresses
using I/O mapped I/O addressing
Which of these statements are correct?
a.1, 2 and 3
b.2 and 4
c.3 and 4
d.1 and 3
Answer. d
84. The contents of memory locations 2000 H, 2001 H and 2002 H are AAH, BBH and CCH
respectively. What are the contents of H and L registers after executing the following instructions in
sequence?
LXI H, 2001 H
LHLD 2001 H
Select the correct answer using the codes given below:
a.Contents of H and L registers are 20 H and 01 H, respectively
b.Contents of H and L registers are AAH and BBH, respectively
c.Contents of H and L registers are BBH and CCH, respectively
d.Contents of H and L registers are CCH and BBH, respectively
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Answer. d
85. The following sequences of instructions are executed by an 8085 microprocessor:
1000 LXI SP, 27FF
1003 CALL 1006
1006 POPH
What are the contents of the stack pointer (SP) and the HL register pair on completion of execution
of these instructions?
a.SP = 27 FF, HL = 1003
b.SP = 27 FD, HL = 1003
c.SP = 27 FF, HL = 1006
d.SP = 27 FD, HL = 1006
Answer. c
86. INR instruction of 8085 does not affect carry flag. Which of the following is correct about INR
instruction?
a.Overflow cannot be detected
b.Overflow can be detected
c.If a programme requires overflow to be detected, ADD instruction should be used instead of INR
d.It can be used to increase the contents of the BC register pair
Answer. c
87. Consider the following 8085 instructions:
ANA A, ORA A, XRA A, SUB A, CMP A.
Now, consider the following statements:
1. All are arithmetic and logic instructions
2. All cause the accumulator to be cleared irrespective of its original contents
3. All reset the carry flag
4. All of them are 1-byte instructions
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Which of these statements is/are correct?
a.1, 2, 3 and 4
b.2 only
c.1, 2 and 4
d.1,3 and 4
Answer. d
88. Consider the program given below, which transfer a block of data from one place in memory to
another:
MVI C, 0B H
LXI H, 2400 H
LXI D, 3400 H
L1: MOV A, M
STAX D
INR L
INR E
DCR C
JNZ L1
What is the total number of memory accesses (including instruction fetches) carried out?
a.118
b.140
c.98
d.108
Answer. a
89. Consider the following statements about register indirect addressing:
1. It helps in writing code that executes faster
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2. It helps in writing compact code
3. It allows reuse of memory CPU data transfer instruction
4. It is essential for stack operations
Which of these statements are correct?
a.1, 3 and 4
b.1, 2 and 4
c.2,3 and 4
d.1,2 and 3
Answer. b
90. Which one of the following 8085 assembly language instructions does not affect the contents of
the accumulator?
a.CMA
b.CMP B
c.DAA
d.ADD B
Answer. b
********************************************************************************
51. The instruction PCHL, in 8085 is used for
a.Load PC with contents of HL.
b.Load HL with contents of memory location pointed by PC.
c.Load HL with contents of PC
d.Load PC with the contents of memory location pointed by HL pair.
Answer. a
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52. Find the content of the accumulator after the execution of the following
program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer.c
53. The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
a.20 H
b.02 H
c.00 H
d. FF H
Answer. c
54. The difference between 8085 instructions RST n and PCHL is
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a.RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b.RST n uses direct addressing while PCHL uses register indirect addressing.
c.RST n is a software interrupt while PCHL simulates a hardware interrupt
d.RST n resets the processor while PCHL restarts the processor.
Answer. a
55. The content of accumulator are 70 H. Initially all flags are zero. What will
be values of CY and S after executing instruction RLC?
a.CY = 0 and S = 0
b.CY = 1 and S = 1
c.CY = 1 and S = 0
d.CY = 0 and S = 1
Answer.d
56. The instruction that exchanges top of stack with HL pair is
a.XTHL
b.SPHL
c.PUSH H
d.POP H
Answer. d
57. The following instruction copies a byte of data from the accumulator into
the memory address given in the instruction
a.STA address
b.LDAX B
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c.LHLD address
d.LDA address
Answer. a
58. In 8085 microprocessor, during PUSH PSW Operation, Stack pointer is
a.Decremented by one
b.Decremented by two
c.Incremented by one
d.Incremented by two
Answer. b
59. The description of a program counter (PC) in 8085 microprocessor is
a.An up/down counter
b.An 8-bit register
c.Initialized automatically by microprocessor
d.Used to point to stack memory area
Answer. c
60. If the status of the control lines SI and SO is LOW, then 8085
microprocessor is performing
a.Reset operation
b.HOLD operation
c.Halt operation
d.Interrupt acknowledge
Answer. c
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61. The opcode for the instruction “Add Immediately to Accumulator with
carry” in 8085 microprocessor is
a.ADI
b.ACI
c.ADC
d.ADD
Answer. b
62. If the status of the control lines SI and SO is LOW, then 8085
microprocessor is performing
a.Reset operation
b.HOLD operation
c.Halt operation
d.Interrupt acknowledge
Answer: c
63. The description of a program counter (PC) in 8085 microprocessor is
a.An up/down counter
b.An 8-bit register
c.Initialized automatically by microprocessor
d.Used to point to stack memory area
Answer: c
64. For which one of the following, the instruction XRA A in 8085
microprocessor can be used?
a.Set the carry flag
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b.Set the zero flag
c.Reset the carry flag and clear the accumulator
d.Transfer FFH to the accumulator
Answer. b
65. What is the correct 8085 assembly language instruction that stores
the contents of H and L registers into the memory locations 1080 H and
1081 H respectively?
a.SPHL 1080 H
b.SHLD 1080 H
c.STAX 1080 H
d.SPHL 1081 H
Answer. b
66. When the operand requires for instruction is stored inside the
processor, then What this addressing mode is called?
a.Direct
b.Register
c.Implicit
d.Immediate
Answer. b
67. Which one of the following addressing technique is not used in 8085
microprocessor?
a.Register
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b.Immediate
c.Register indirect
d.Relative
Answer. d
68. In an instruction of 8085 microprocessor, how many bytes are
present?
a.One or two
b.One, two or three
c.One only
d.Two or three
Answer. b
69. Which one is the indirect addressing mode in the following
instructions?
a.LXI H 2050 H
b.MOV A, B
c.LDAX B
d.LDA 2050 H
Answer. c
70. The addressing mode used in the instruction JMP F347 H in case of
an Intel 8085A microprocessor is which one of the following?
a.Direct
b.Register—indirect
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c.Implicit
d.Immediate
Answer. D
11. Which one of the following statements is correct regarding the instruction CMP A ?
a .compare accumulator with register A
b .compare accumulator with memory
c .compare accumulator with register H
d .This instruction does not exist
Answer. a
12. The instruction JNC 16-bit refers to jump to 16-bit address if ?
a .sign flag is set
b .carry flag is reset
c .zero flag is set
d .sparity flag is reset
Answer. b
13. Among the given instructions, the one which affects the maximum number of flags is ?
a.RAL
b.POP PSW
c.XRA A
d.DCR A
Answer. c
14. XCHG instruction of 8085 exchanges the content of ?
a.top of stack with contents of register pair
b.BC and DE register pairs
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c.HL and DE register pairs
d.None of the above
Answer. c
15. The number of output pins of a 8085 microprocessor are
a.40
b.27
c.21
d.19
Answer. b
16. Following is a 16-bit register for 8085 microprocessor
a.Stack pointer
b.Accumulator
c.Register B
d.Register C
Answer. a
17. The register which holds the information about the nature of results of arithmetic of logic
operations is called as
a.Accumulator
b.Condition code register
c.Flag register
d.Process status registers
Answer. c
18. When referring to instruction words, a mnemonic is
a.a short abbreviation for the operand address.
b.a short abbreviation for the operation to be performed.
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c.a short abbreviation for the data word stored at the operand address.
d.Shorthand for machine language.
Answer. b
19. In a 8085 microprocessor system with memory-mapped I/O, which of the following is true?
a.Devices have 8-bit‘address line
b.Devices are accessed using IN and OUT instructions
c.There can be maximum of 256 input devices and 256 output devices
d.Arithmetic and logic operations can be directly performed with the I/O data
Answer. d
20. Consider the following statements:
Arithmetic Logic Unit (ALU)
1 . Performs arithmetic operations.
2. Performs comparisons.
3. Communicates with I/O devices.
4. Keeps watch on the system.
Which of these statements are correct?
a.1, 2, 3 and 4
b.1,2 and 3 only
c.1 and 2 only
d.3 and 4 only
Answer. c
21. Ready pin 0f microprocessor is used
a.to indicate that the microprocessor is ready to receive inputs
b.to indicate that the microprocessor is ready to receive outputs
c.to introduce wait state
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d.to provide direct memory access
Answer. c
22. A bus connected between the CPU and the main memory that permits transfer of information
between main memory and the CPU is known as
a.DMA bus
b.Memory bus
c.Address bus
d.Control bus
Answer. b
23. The operations executed by two or more control units are referred as
a.Micro-operations
b.Macro-operations
c.Multi-operations
d.Bi control-operations
Answer. c
24. Consider the following registers:
1. Accumulator and flag register
2. B and C registers
3. D and E registers
4. H and L registers
Which of these 8-bit registers of 8085 μP can be paired together to make a 16-bit register?
a.1, 3 and 4
b.2, 3 and 4
c.1, 2 and 3
d.1, 2 and 4
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Answer. b
25. The first microprocessor to include virtual memory in the Intel microprocessor family is
a.80286
b.80386
c.80486
d.Pentium
Answer. a
26. Program counter in a digital computer
a.counts the numbers of programs run in the machine ,
b.counts the number of times a subroutine is called
c.counts the number of times the loops are executed
d.points the memory address of the current or the next instruction to be executed
Answer. d
27. Assuming LSB is at position 0 and MSB at position 7, which bit positions are not used
(undefined) in Flag Register of an 8085 microprocessor?
a.1, 3, 5
b.2, 3, 5
c.1, 2, 5
d.1, 3, 4
Answer. a
28. At the beginning of a fetch cycle, the contents of the program counter are
a.incremented by one
b.transferred to address bus
c.transferred to memory address register
d.transferred to memory data register
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Answer. c
29. Each instruction in an assembly language program has the following fields
1.Label field
2.Mnemonic field
3.Operand field
4.Comment field
What is the correct sequence of these fields?
a.1, 2, 3 and 4
b.2, 1, 4 and 3
c.1,3, 2 and 4
d.2, 4, 1 and 3
Answer. a
30. The relation among IC (instruction Cycle), FC (Fetch Cycle) and EC (Execute Cycle) is
a.IC = FC − EC
b.IC = FC+ EC
c.IC= FC + 2EC
d.EC = IC+FC
Answer. B
1. In 8085 microprocessor, how many interrupts are maskable.
a. Two
b. Three
c. Four
d. Five
Answer. c
2. Which stack is used in 8085 microprocessors?
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a. FIFO
b. FILO
c. LIFO
d. LILO
Answer. c
3. In the instruction of the 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
4. Which one of the following addressing technique is not used in 8085 microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
5. Which one of the following register of 8085 microprocessor is not a part of the programming
model?
a. Instruction register
b .Memory address register
c. Status register
d. Temporary data register
Answer. c
6. The program counter in 8085 microprocessor is a 16-bit register, because
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a. It counts 16 bits at a time
b. There are 16 address times
c. It facilitates the users storing 16-bit data temporarily
d. It has to fetch two 8-bit data at a time.
Answer. b
7. A direct memory access (DMA) transfer replies
a .Direct transfer of data between memory and accumulator
b .Direct transfer of data between memory and I/O devices without the use of microprocessor
c .Transfer of data exclusively within microprocessor registers
d .A fast transfer of data between microprocessor and I/O devices
Answer. b
8. Handshaking mode of data transfer is
a. Synchronous data transfer
b. asynchronous data transfer
c. interrupt driven data transfer
d. level Mode of DMA data transfer
Answer. a
9. In a Microprocessor, the address of the new next instruction to be executed is stored in
a. Stack pointer
b. address latch
c. Program counter
d. General purpose register
Answer. c
10. The instruction RET executes with the following series of machine cycle
a. Fetch, read, write
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b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
31. When a peripheral is connected to the microprocessor in input/output mode, the data transfer
takes place between
a.any register and I/O device
b.memory and I/O device
c.accumulator and I/O device
d.HL registerand I/O device
Answer. c
32. While execution of I/O instruction takes place, the 8-bit address of the port is placed on
a.lower address bus
b.higher address bus
c.data bus
d.lower as well as higher-order address bus
Answer. d
33. The length of a bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an
indeterminate number of wait state clock cycles denoted by TW. The wait states are always
inserted between
a.T1 and T2
b.T2 and T3
c.T3 and T4
d.T4 and T1
Answer. c
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34. Which one of the following circuits transmits two messages simultaneously in one direction?
a.Duplex
b.Diplex
c.Simplex
d.Quadruplex
Answer. b
35. A microprocessor is ALU
a.and control unit on a single chip
b.and memory on a single chip
c.register unit and I/O device on a single chip
d.register unit and control unit on a single chip
Answer. d
36. In Intel 8085 microprocessor, ALE signal is made high to
a.Enable the data bus to be used as low order address bus
b.To latch data D0— D7 from the data bus
c.To disable data bus
d.To achieve all the functions listed above
Answer. a
37. Which one of the following statements for Intel 8085 is correct?
a.Program counter (PC) specifies the address of the instruction last executed
b.PC specifies the address of the instruction being executed
c.PC specifies the address of the instruction be executed
d.PC specifies the number of instruction executed so far
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Answer.c
38. What will be the contents of DE and HL register pairs respectively after the execution of the
following ir:cnstructions?
a.LXIH, 2500 H
b.LXID, 0200 H
c.DAD D
d.XCHG
0200 H, 2500 H
0200 H, 2700 H
2500 H, 0200 H
2700 H, 0200 H
Answer. d
39. In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a.0024 H
b.002C H
c.0034 H
d.003C H
Answer. a
40. A ‘DAD H” instruction is the same as shifting each bit by one position to the
a.left
b.right
c.left with a zero inserted in LSB position
d.right with a zero inserted in LSB position
Answer. c
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41. When a program is being executed in an 8085 microprocessor, its program counter contains
a.the memory address as the instruction that is to be executed next
b.the memory address of the instruction that is being currently matched.
c.the total number of instructions in the program being executed.
d.the number of instructions in the current program that have already been executed.
Answer. a
42. Which of the following data transfer is not possible in microprocessor?
a.Memory to accumulator
b.Accumulator to memory
c.Memory to memory
d.I/O device to accumulator
Answer. c
43. LOADER is a program that
a.loads the memories and generates a hex file
b.loads the hex file and converts to the executable file
c.loads the COM file and generates the binary code
d.loads English like command and generates the binary code
Answer. b
44. Which of the following instructions is closest match to the instruction POP PC?
a.RET
b.PCHL
c.POP PSW
d.DAD SP
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Answer. a
45. How many machine cycles are required by STA instruction?
a.2
b.3
c.4
d.5
Answer. c
46. Which of the following 8085 instruction will require maximum T-states for execution?
a.XRI byte
b.STA address
c.CALL address
d.JMP address
Answer. c
47. In 8085 microprocessor, which mode of addressing does the instruction CMP M use?
a.Direct addressing
b.Register addressing
c.Indirect addressing
d.Immediate addressing
Answer. c
48. With reference to 8085 microprocessor, which of the following statements are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
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1 and 2 only
2 and 3 only
1 and 3 only
1, 2 and 3
Answer. d
Explanation:- STA 4050H has 3 byte.
49. What is content of accumulator of 8085 microprocessor after the execution of XRI F0 H
instruction?
a.Only the upper nibble of accumulator is complemented
b.Only the lower nibble is complemented
c.Only the upper nibble is reset to zero
d.Only the lower nibble is reset to zero
Answer. a
50. The 8085 programming manual says that it takes seven T states to fetch and execute the
MOV instruction. If the system clock has a frequency of 2.5 MHz, how long is an instruction
Cycle?
a.2.8 s
b.2.5ns
c.2.8 ns
d.2.8 μs
Answer. d
1. The fetch and execute instruction, one at a time,
in the order of address increment is identified as
1. The Instruction execution technique
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2. The Straight line sequencing technique
3. The Instruction fetching technique
4. The Random sequencing technique
Answer – (2)
2. The control signal employed to differentiate
amongst an input or output operation and memory
operations is
1. ALE
2. IO/ M͞
3. SID
4. SOD
Answer – (2)
3. The instruction register hold
1. The Flag condition
2. An Instruction address
3. An Opcode
4. None
Answer – (3)
4. A microprocessor is termed to be a 8-bit or 16-bit
or more considering the
1. Size of data bus
2. Size of Address bus
3. Size of Arithmetic Logic Unit
4. Size of Control bus
Answer – (3)
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5. The number of pair register found in 8085
microprocessor
1. Three
2. Four
3. two
4. Zero
Answer – (1)
6. The number of programmable 8-bit registers
of microprocessor 8085 is
1. five
2. Six
3. Seven
4. Eight
Answer – (3)
7. The stack and SP in microprocessor
1. Belong to the memory
2. Both reside in CPU
3. Both reside in memory and later in CPU
4. Former reside in CPU and the later in memory
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Answer – (3)
8. An 8kX8 ROM, having the monitor program of
microprocessor trainer-kit with end-address of
1. 600FH
2. 500FH
3. 1 FFF H
4. 4 FFF H
Answer – (3)
9. The overall I/O space existing in a 8085 if used as
a peripheral mapped mode
1. Sixty four only
2. One hundred twenty eight
3. Two hundred fifty six
4. Five hundred twelve
Answer – (3)
10. The interfacing device utilized with an O/P port
be there
1. Buffer circuit
2. Priority encoder circuit
3. Latch circuit
4. None
Answer – (1)
11. Address lines necessitate for the 64kB memory is
1. 24
2. 36
3. 12
4. 16
Answer – (4)
12. Which one is hardware type interrupt?
1. INTA
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2. TRAP
3. RST
4. INT
Answer – (2)
13. In 8085 microprocessor, which one is the non-
maskable interrupt?
1. RST 7.5
2. TRAP
3. HOLD
4. INTR
Answer – (2)
14. Machine cycles in the “CALL” instruction of
microprocessor 8085 CPU are
1. six
2. five
3. four
4. two
Answer – (2)
15. In 8085 Microprocessor, the interrupt TRAP is
1. Every time maskable
2. not interrupted by a service subroutine
3. Used for short-term power failure
4. Lowermost priority interrupt
Answer – (3)
16. RST 7.5 interrupt act as
1. Vectored and Maskable type
2. Vectored and non-maskable type
3. Direct and maskable type
4. Direct and non-maskable type
Answer – (1)
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17. No of hardware interrupt request, a solitary
interrupt- controller namely IC8259A could
process?
1. Eight
2. Nine
3. Sixteen
4. Sixty four
Answer – (1)
18. The interrupt mask in the 8085 microprocessor
is set or reset by the software instruction
1. By the EI interrupt
2. By the DI interrupt
3. By the RIM interrupt
4. By the SIM interrupt
Answer – (4)
19. For 8085, The vector address corresponding to
software interrupt RST 7.0 is
1. 0017 Hex
2. 0027 Hex
3. 0038 Hex
4. 0700 Hex
Answer – (3)
20. Which one has the highest priority out of these
1. TRAP
2. RST 7.5
3. RST 6.5
4. HOLD
Answer – (4)
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21. Which one of the following is the software
interrupt of 8085 ?
1. RST 7.5
2. EI
3. RST 1.0
4. TRAP
Answer – (3)
22. Let the accumulator content 4F after execution
the RAL instruction, contain of accumulator will be
1. 9E
2. 8B
3. 8C
Answer – (1)
23. The clock’s interrupt-handler of a certain
computational machine needs 2 m/sec per clock
tick. The clock’s frequency is 60 Hz. What percent of
the CPU is dedicated to the clk?
1. 1.2
2. 7.5
3. 12
4. 18.5
Answer – (3)
24. For “JZ NEXT” instruction, which of the following
register’s memory is checked to verify if it is ‘0’ or
not ?
1. A
2. B
3. R1
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4. R2
Answer – (1)
25. At any time POP H instruction is performed
1. Data bytes in the HL pairs will be put in storage of the stack’s registers
2. Two data bytes are transferred to the HL pair’s register
3. Two data bytes at the top of the stack are moved to the CPU
Answer – (2)
26. In microprocessor instruction STA 9000H is
1. A data transfer instruction
2. A Logical instruction
3. A I/O and MPU will execute
4. Not an option
Answer – (1)
27. The addressing method in microprocessor used
in the STAX B is
1. A Direct addressing method
2. A Resister addressing method
3. An Immediate addressing method
4. Register indirect addressing method
Answer – (4)
28. When a subroutine is called the address of the
instruction next to CALL is kept in
1. The Stack
2. The Program counter
3. The Stack pointer register
4. Not an option
Answer – (1)
29. Machine cycles for IN instructions in
microprocessor are
1. Eight
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2. five
3. four
4. three
Answer – (4)
30. The instruction MOV A, B is kind of
1. the Immediate addressing mode
2. Directing addressing mode
3. Implied addressing mode
4. Register addressing mode
Answer – (4)
31. How many T-states would be required for the
execution of CALL 2000 H instruction?
1. 10
2. 13
3. 18
4. None of these
Answer – (3)
32. The number of I/O lines for 8255 chip is
1. 256
2. 512
3. 1024
4. 2K
Answer – (1)
33. How many flag registers are available in the
8051 chip?
1. 9
2. 8
3. 6
4. 5
5. None
Answer – (5)
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Rooma, Kanpur – 208 008
34. The “programmable interval timer” is
1. 8253 chip
2. 8251 chip
3. 8250 chip
4. 8275 chip
Answer – (1)
35. The 8086 microprocessor addressing capacity is
1. 64 KB
2. 1 MB
3. 2 MB
4. 1 GB
Answer – (2)
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