ISSN (O): 2348-4098

RAJESH C et al. Citation: 10.2348/ijset06150601 ISSN (P): 2395-4752

DESIGN AND DEVELOPMENT OF VERIFICATION ENVIRONMENT TO VERIFY SPI

MASTER CORE USING UVM

1RAJESH C, 2SHIVANANDA, 3MRS. SHANTHI V A

M.Tech, Dept. of ECE, B.N.M Institute of Technology, Bengaluru, India, E‐mail: rajesh.cgowda@gmail.com

Assoc. Professor, Dept. of ECE, B.N.M Institute of Technology, Bengaluru, India, E‐mail: cshivananda@gmail.com

Senior Technical Staff, Maven Silicon Softech Pvt Ltd, Bengaluru, India, Email: shanthi@maven‐silicon.com

ABSTRACT

The main objective of the work is to design an SPI Master Core using Verilog HDL and Verify the designed SPI Master Core
using Universal Verification Methodology. SPI (Serial Peripheral Interface) facilitates the transfer of synchronous serial data,
which is now a day’s engineer’s favorite choice for its convenience and saving system resource. SPI (Serial Peripheral
Interface) operates in full duplex mode. It communicates in master/slave mode where the master device initiates the data
frame. Multiple slave devices are allowed with individual slave select line .Serial Peripheral Interface of symmetrical structure
can be designed using Verilog HDL and Synthesized using Xilinx 13.2, and then can be simulated using Questasim 10.0b. SPI is
a very popular interface used for connecting peripherals to each other and to microprocessors.

Key Words: SPI, WISHBONE, QUESTASIM, XILINX ISE, Verilog, UVM, Coverage

1. INTRODUCTION slave devices as it controls multiple slave devices. That

will not meet the standard SPI protocol. The standard SPI
In these days almost every system includes some communication is a single‐master communication, which
intelligent control, commonly a Microcontroller Core. is all the communications have only one master device.
General‐purpose circuits like remote I/O ports, data Thus the devices which are based on SPI protocol are
converters, LCD drivers, EEPROM or RAM. Application limited by both the aspects. The design is fully composed
oriented circuits for data communication interfaces with the four interfaces of standard SPI protocol.
and/or intensive computation task. So the
communications between these modules are important. 2. SPI DESIGN PRINCIPLES

In many applications the interface between these modules SPI is a synchronous serial bus protocol developed by
is still a bottleneck of system performance. In such Motorola and integrated in many of their
prospect the reuse of IP (intellectual property) macro microcontrollers. Normally SPI is used for short distance
cells is becoming the centre of gravity for design communication,
productivity and the key for being able to produce chips
that work efficiently. Every integrated components should 2.1 ARCHITECTURE OF SPI
be connected each other and every SoC should be linked
with each other in an efficient manner that allows an
error‐free and fast communication. Communication
among SoC is the key to yield higher performances: the
most widely used solution used for interconnecting SoC is
a serial bus, as it gives a great advantage in terms of cost.
With the development of the IC manufacturing, the
communication between hardware devices became very
important. Presently widely used protocols such as I2C
bus protocol, ARM bus protocol, WISHBONE bus protocol,
etc., allows the hardware devices to communicate through
the appointment of the rules and match the timing for
achieving the purpose of data communication. Compared
to other protocols, SPI has is simple to use, has higher
transmission speed, and little pins advantages. SPI
standard protocol requires at least four interfaces.
Normally, the devices which are based on SPI protocol are
divided into slave‐device and master‐device for Fig.1: Architecture of SPI
transmitting the data. The clock signal and slave select
signal have to be generated by the master‐device during SPI Master Core consists of three main building blocks:
the data exchange processing. Therefore, the master
device should have multiple slave select interfaces for • Clock generator

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 ISSN (O): 2348-4098
RAJESH C et al. Citation: 10.2348/ijset06150601 ISSN (P): 2395-4752
• Serial interface

• WISHBONE Interface

SPI bus consists of four signals: serial clock (SCK), master

in slave out (MISO), master out slave in (MOSI), master in
slave out (MISO), and active‐low chip select (SS). As a
multi‐master/slave protocol, communication between the
selected slave and master uses the unidirectional MOSI
and MISO lines, to achieve higher data rates in full duplex
mode. SPI requires separate Slave select lines for each
slave. With SPI we can connect as many devices as many
pins we have on the main microcontroller. The
communication speed between ICs is much faster due to
the Full Duplex communication.

2.2 MODULE DESIGN

Fig.3 Serial Interface Circuit Module
1) Clock Generator design
3) Top‐level module –TOP
The clock signal spi_clgen is root from the external clock
wb_clk, the module produces the output signal s_clk Based on the specifications of the SPI protocol, we get the
according to the different frequency factor of the clock basic structure SPI bus by including the clock generation
register. Divider is the basic and efficient part of the module and serial interface module. An important aspect
digital circuits and FPGA design; It is also a very of the top‐level module is to ensure that the sub‐modules
important component of the communication system. The work smoothly. The SPI top module needs the control
frequency of the serial clock s_clk of the master core word, the efficient operation of sub‐modules: clock
system is changed by changing the value of the DIVIDER generation module and serial interface module. SPI top
value in the Divider register. Relation between DIVIDER module is synthesized by ISE. Synthesized module is
value, s_clk and wb_clk is given by the following equation: shown in Fig. 4.

Clock generation module is synthesized by ISE. Module
synthesized shown below shown in Fig 2.

Fig.4 Top Level Circuit Module

3. SIMULATION AND VERIFICATION

Fig.2 Clock Generator Circuit Module Verilog HDL is one of the hardware description languages.
Verilog can be used for different levels of logic design, it
2) Serial Interface module design‐‐ spi‐shift
can be used for digital system logic simulation, timing
Serial interface module is the core module of the SPI. analysis and logic synthesis. In this work, a SPI Master
Serial interface module is responsible for serial data into core Interface Module is designed using Verilog HDL.
parallel out and data parallel into serial out. In this work According to the standard SPI bus principle, we can
the design of serial interface is different from the usual achieve the bidirectional data transmission between the
serial interface; It increases the overall data transmission slave devices and microcontroller. Using Verilog HDL we
rate. SPI Master at the host side acts as a slave device to had designed the SPI Master Core interface circuit,
receive data and acts as the master device to send data. synthesised with ISE, and then used Questasim to
Serial interface module is synthesized by ISE. Verilog code simulate. In order to establish the test platform, first setup
for this module is synthesised module shown in Fig. 3. the master module to simulate the Wishbone protocol,
and then setup the slave module to simulate SPI protocol
at the same time. Then to compare and check the

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 ISSN (O): 2348-4098
RAJESH C et al. Citation: 10.2348/ijset06150601 ISSN (P): 2395-4752
receive/send data and addresses. The test bench is
designed using universal verification methodology.
Verification is also the major part of this work as many
modules are designed and having many inputs univrsal
verification methodology helps to makes easy to stimulate
according to our wish, constraint the unwanted stimulus.
Here the SPI Master Core Design is considered as design
under test (DUT). Components of Verification
Environment are as follows : RTL module, Master and
Slave agent tops which consists of master and slave
agents which contains sequencer, driver and monitor,
virtual sequencer, Scoreboard, TOP level module which
encapsulates the above all with RTL and Test Cases.

UVM testbench architecture is as shown in Fig. 5. Fig.7: Coverage report

4. CONCLUSION

In this work, we have designed the SPI Master core Using

Verilog HDL language based upon design‐reuse
methodology. SPI Transmission timing is very strict, so
this paper designs a reliable and stable clock generation
module, considering both the odd‐even frequency cases.
Data transmission module is very simple and the transfer
speed is faster. We have verified the data in slave device
same as the data in the master device. Further, we have
also done functional verification. The code coverage is
obtained for the RTL design and 100% code coverage and
functional coverage is extracted. The complete function of
the registers is verified in this paper. The innovation of
this article: Universal verification methodology is used in
order to cover all the functions of the code and to reuse
the class instead of writing the code again. The advantage
of using universal methodology is making the things easy
Fig.5: UVM testbench Architecture by calling the inbuilt classes.
The simulation results are as shown below in Fig. 6 REFERENCES

[1] www.opencore.org Simon Srot.SPIMasterCore

Specification, Rev.0.6. May 16, 2007.

[2] Prophet, Graham. Communications IP adds SPI

interface to FP‐GA. EDN, v 48, n 27, Dec 11, 2003.

[3] Motorola, "MC68HC II manual".

[4] Smart Computing Dictionary, Serial Peripheral

Interface (SPI)
(online)http://www.smartcomputing.com/editorial/dicti
onary/detail.asp?guid=&searchtype=1&DicID=12820&Re
fType=Dictionary (access date 28May 2006)

Fig.6: Simulation results [5] Frédéric Leens，An Introduction to I2C and SPI
Protocols,IEEE Xplore.
Coverage Report is shown below in Fig. 7
[6] Zhang Yan‐wei, Verilog HDL detailed design
procedure, Posts & Telecom Press.

[7] Wikipedia, the free encyclopedia, “Serial Peripheral

Interface Bus”,

Available
http://en.wikipedia.org/wiki/Serial_Peripheral_Interface
_Bus.

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