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spi 设计

The document describes the design and implementation of a SPI interface controller for communication between a SoC chip and peripheral devices. It analyzes the SPI protocol sequence, describes the design of the SPI logic function, and discusses how the design is compatible with the SPI protocol while also expanding its functions. The SPI interface controller was tested and verified on FPGA and the SoC chip using it was successfully processed, with test results showing the design meets specifications.

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34 views4 pages

spi 设计

The document describes the design and implementation of a SPI interface controller for communication between a SoC chip and peripheral devices. It analyzes the SPI protocol sequence, describes the design of the SPI logic function, and discusses how the design is compatible with the SPI protocol while also expanding its functions. The SPI interface controller was tested and verified on FPGA and the SoC chip using it was successfully processed, with test results showing the design meets specifications.

Uploaded by

zy798408818
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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The design and realization of a comprehensive SPI

interface controller
Jianlong Zhang1,2, Chunyu Wu1,a, Wenjing Zhang2, Jiwei Wang1
1 College of physics, Liaoning university, Shengyang, China
2 Design department, Beijing hongsi electronic tech. co., ltd. Beijing, China
a
E-mail: wucnyu@sina.com

Abstract—This paper describes a design and implementation of ᳔催ԡӴ䕧៪㗙ᰃ‫ܜ‬᳔ԢԡӴ䕧ˈ᠔ҹৃҹֱ䆕Ϣ SD


SPI interface model which is used for a SoC chip. The objective वˈFLASHˈ⎆᱊ᰒ⼎఼䖯㸠䗮ֵˈՓࡳ㛑᳈ࡴܼ䴶DŽ㗠
of this design is to realize expediently communicate between SoC
Ϩ೼থ䗕᭄᥂ᯊᓩܹњϔ㑻 FIFOˈ䖭ḋህ䖯ϔℹᦤ催њ
chip and peripheral equipment. The paper analyses the sequence
of SPI protocol, describes the design project of implement SPI ᭄᥂ⱘӴ䕧䗳ᑺDŽ
logical function. Besides, the design is compatible with the SPI
protocal and the function is also expanded, finally achieves III. SPI ᥹ষⱘ䆒䅵
powerful in function. After testbench and FPGA verification, the
SoC chip that used this SPI model had been successfully
A. SPI ᥹ষ῵ഫ㋏㒳㒧ᵘ䆒䅵
processed. The test results indicate that the SPI interface
controller’s function and performance are all achieve design ᥹ষֵোᦣ䗄ⱘᰃ῵ഫϢ݊Ҫ῵ഫП䯈ⱘ᥹ষᅮНˈ
target, many communication tests indicate the design is reliable Ϣ63,ࡳ㛑῵ഫ䖲᥹ⱘ῵ഫ᳝བϟ޴Ͼˈ䖲᥹݇㋏೒བ೒
in performance. ᠔⼎DŽ
Keywords-SPI; Synchronous;Ttransfer; Sequential;

I. ᓩ㿔
䖥ᑈᴹ䱣ⴔ⬉ᄤᡔᴃⱘথሩˈSoC ⱘথሩᏆ㒣៤Ўњ
ϔ⾡䍟࢓ˈᑓ⊯ᑨ⫼Ѣ⦄ҷ⼒Ӯⱘ৘Ͼ乚ඳˈ⫼᠋Ꮰᳯѻ
ક ৃ ҹ ੠᳈ ໮ ⱘ 䆒໛ Ѹ ᤶ᭄ ᥂ ˈ ᠔ҹ ᕜ ໮ 㢃⠛ 䛑 ᬃᣕ
SPIˈUSBˈSDˈISO7816 ㄝ໮⾡᥹ষˈ݊Ё SPI ҹ݊⡍
᳝ⱘӬ䍞ᗻ㹿䍞ᴹ䍞ᑓ⊯ⱘᑨ⫼DŽ
೒1 SPI᥹ষ῵ഫϢ਼ೈ῵ഫ䖲᥹݇㋏೒
ᴀ῵ഫ䞛⫼ϔϾ 9 Ͼ⢊ᗕⱘ FSM 㾷‫އ‬ᮍḜᴹ᥻ࠊӴ䕧
ᯊᑣˈ㗠Ϩ䖬‫݋‬᳝ᇍ㋏㒳ᯊ䩳䖯㸠ߚ乥ⱘࡳ㛑ˈҹ⒵䎇ϡ
ৠⱘӴ䕧乥⥛DŽЎњᅲ⦄ϔϾЏ῵ഫϢϸϾҢ῵ഫ೼ϡ䳔
㽕⹀ӊ໡ԡⱘࠡᦤϟѸ᳓Ꮉ԰ˈ೼ॳ᳝ϔᴵ⠛䗝ֵোⱘ෎
⸔Ϟজ๲ࡴϔᴵ⠛䗝ֵো㒓DŽৠᯊЎњ㛑䖯ϔℹᦤ催᭄᥂
ⱘӴ䕧䗳⥛ˈ೼᭄᥂থ䗕ᯊ๲ࡴϔ㑻 FIFO˄㓧ᄬ˅DŽϞ
䗄ϸ乍ᬍ䖯೼Ꮖᶹ䯙ⱘ᭛⤂Ё䖬᳾㾕ࠄDŽᅠ៤ৢⱘ IP 䆒
䅵ˈᇍ RTL 㑻ҷⷕ䖯㸠њ໻䞣ⱘᑇৄ偠䆕ǃFPGA 偠䆕੠
㢃⠛⌕∈偠䆕DŽ偠䆕㒧ᵰ㸼ᯢˈ䆹䆒䅵೼Ꮖⶹⱘ৘⾡ᚙ‫މ‬
ϟ䛑㛑ℷ⹂ⱘᅠ៤᭄᥂ⱘӴ䕧DŽ

II. SPI ᥹ষὖ䗄


SPI˄Serial peripheral interface˅ᰃϔ⾡催䗳催ᬜ⥛ⱘІ
㸠᥹ষᡔᴃˈ⬅ Motorola ݀ৌᦤߎDŽ೼ SPI ᷛ‫ޚ‬ЁӴ㒳ⱘ
SPI ᥹ষ㒓݅ 4 ᴵˈࣙᣀᯊ䩳㒓 SCKˈЏᴎ䕧ܹ/Ңᴎ䕧ߎ
㒓 MISOˈЏᴎ䕧ߎ/Ңᴎ䕧ܹ㒓 MOSIˈԢ⬉ᑇ᳝ᬜⱘ⠛
䗝Փ㛑ֵো㒓 SS [1-2]DŽ
ᇍѢՓ⫼㗙ᴹ䇈ˈSPI Ӭ࢓ᰃᇍѢ໮⾡䆒໛ⱘ‫ݐ‬ᆍᗻDŽ
ᴀ᭛䆒䅵ⱘ SPI ῵ഫৃҹᬃᣕಯ⾡ϡৠⱘӴ䕧ᯊᑣ˄䗮䖛
ᬍব CPHA ҹঞ CPOL ⱘؐᴹᅲ⦄˅ˈ㗠Ϩ䖬ৃҹ䗝ᢽ‫ܜ‬
೒ 2 SPI ῵ഫ‫ݙ‬䚼㒧ᵘ೒

978-1-4244-9439-2/11/$26.00 ©2011 IEEE


4529
ᘏ㒓῵ഫ˖ᘏ㒓῵ഫᰃ SPI ᥹ষ῵ഫϢ CPU П䯈䗮ֵ Pin ᥻ࠊ䘏䕥῵ഫ˖䖭Ͼ῵ഫህᰃЏҢ SPI ᥹ষ῵ഫП
ⱘḹṕˈ䗮䖛ᘏ㒓ˈCPU ৃҹ᥻ࠊ SPI ᥹ষ῵ഫˈҢ㗠ᅲ 䯈䖯㸠᭄᥂Ѹᤶⱘഄᮍˈা᳝䗮䖛䖭Ͼ῵ഫⱘ᭄᥂ˈᠡⳳ
⦄ᇍ῵ഫᆘᄬ఼ⱘ䜡㕂ǃ᭄᥂ⱘথ䗕ҹঞ᭄᥂ⱘ᥹ᬊㄝࡳ ℷⱘᅲ⦄њ᭄᥂ⱘӴ䕧䖛⿟DŽ
㛑ˈҢ㗠ᅠ៤᭄᥂ⱘӴ䕧DŽ
B. ЏҢ SPI ῵ഫⱘ䖲᥹݇㋏
Ёᮁ῵ഫ˖೼೒ 1 ЁˈЁᮁ῵ഫЏ㽕⫼Ѣ໘⧚৘Ͼ῵
ഫѻ⫳ⱘЁᮁ䇋∖ֵোˈ⬅ѢЁᮁ῵ഫⱘᄬ೼ˈৃҹՓ Џ SPI Ёⱘ 8 ԡ⿏ԡᆘᄬ఼䗮䖛 MOSI ੠ MISO ᓩ㛮Ϣ
CPU ঞᯊⱘ໘⧚৘Ͼ῵ഫѻ⫳ⱘЁᮁ˗೼ᑨ⫼ᯊᎻ཭ⱘՓ Ң SPI Ёⱘ 8 ԡ⿏ԡᆘᄬ఼Ⳍ䖲᥹DŽ䖲᥹ৢⱘ⿏ԡᆘᄬ఼
⫼Ёᮁ䘏䕥ˈ䖬ৃҹ䰡Ԣ῵ഫⱘࡳ㗫DŽ 㒘៤њϔϾߚᏗᓣⱘ 16 ԡ⿏ԡᆘᄬ఼DŽ೼ SPI ⱘӴ䗕䖛
⿟ЁˈЏ⿏ԡᆘᄬ఼ⱘ SCK ᯊ䩳ᇚ᭄᥂⿏ࠄ 16 ԡᆘᄬ఼
PAD ῵ഫ˖৿᳝㢃⠛ᓩߎⱘㅵ㛮ֵোˈ⫼ѢϢ‫݋‬᳝ ⱘ 8 ԡˈϨЏҢ SPI Ѹᤶ᭄᥂DŽ‫ܹݭ‬Џ SPI Ё SPIDR˄᭄
SPI ᥹ষⱘ䆒໛䖯㸠᭄᥂ⱘѸᤶDŽ ᥂ᆘᄬ఼˅ᆘᄬ఼ⱘ᭄᥂৥Ң SPI 䕧ߎDŽᔧ᭄᥂Ѹᤶ㒧ᴳ
SPI ᥹ষ῵ഫⱘ‫ݙ‬䚼㒧ᵘ䆒䅵೒བ೒ 2 ᠔⼎DŽ ᯊˈЏҢ SPI ⱘ SPIDR ᆘᄬ఼䇏ߎⱘ᭄᥂⬅Ң SPI ‫ܹݭ‬DŽ
SPI ⱘѦ䖲ঞӴ䗕བ೒ 3 ᠔⼎DŽ
೒ 2 䆺㒚ⱘҟ㒡њ῵ഫ‫ݙ‬䚼৘Ͼᄤ῵ഫП䯈ⱘ䘏䕥݇
㋏ˈҹঞ SPI ῵ഫϢ݊Ҫ῵ഫП䯈䖲᥹݇㋏ⱘ᥹ষ[3-4]DŽ
ᘏ㒓᥻ࠊ䘏䕥῵ഫ˖Џ㽕ᅠ៤ᘏ㒓ֵোϢ SPI ᥹ষ῵
ഫ‫ݙ‬䚼ֵোⱘ䕀࣪ˈҢ㗠ᅲ⦄ᘏ㒓ᇍ᥹ষ῵ഫⱘ᥻ࠊDŽ
⊶⡍⥛ᆘᄬ఼῵ഫ੠ߚ乥᥻ࠊ䘏䕥῵ഫ˖䗮䖛ᇍ⊶⡍
⥛ᆘᄬ఼ⱘ䜡㕂ˈৃҹѻ⫳ SPI ᯊ䩳ߚ乥಴ᄤˈSPI ⱘ⊶
⡍⥛থ⫳఼⫼䖭Ͼߚ乥಴ᄤᇍ㋏㒳ᯊ䩳䖯㸠ߚ乥ˈህѻ⫳
њ SPI Ӵ䕧ᯊ䩳 SCKDŽ
(SPBR+1)
SPI ᯊ䩳ߚ乥಴ᄤ˙ SPBˇ1 h2 (1) 
⊶⡍⥛ᆘᄬ఼ᰃܿԡⱘᆘᄬ఼ˈԢϝԡ㸼⼎ SPBR,催 ೒ 3 SPI ⱘѦ䖲ঞӴ䗕⼎ᛣ೒
ϝԡ㸼⼎ SPBˈ⬅݀ᓣৃҹⳟߎߚ乥಴ᄤ᳔໻ؐЎ 2048ˈ
᳔ᇣؐЎ 2DŽ᠔ҹ SPI ᥹ষ῵ഫӴ䕧᭄᥂ⱘ᳔催乥⥛Ў㋏ C. Ӵ䕧Ḑᓣ੠ᯊᑣ
㒳ᯊ䩳ⱘ 2 ߚ乥DŽা᳝ᔧ SPI ໘ѢЏ䆒໛ᮍᓣᑊϨℷ೼থ
䗕ᯊˈSPI ῵ഫⱘ⊶⡍⥛থ⫳఼ᠡᰃ▔⌏ⱘˈ݊ԭᯊ䯈ߚ • CPHA=1 ⱘӴ䗕Ḑᓣ˖
乥఼ϡ▔⌏ˈҹ‫ޣ‬ᇥᎹ԰⬉⌕ˈҢ㗠᳔໻䰤ᑺⱘ䰡Ԣࡳ ೒ 4 㒭ߎњ SCK 䞛⫼ CPHA˙1 ᯊⱘ SPI ⱘᯊ䩳Ḑᓣ੠
㗫DŽ Ӵ䗕ᯊᑣ೒[5]DŽ
SPI ᥻ࠊᆘᄬ఼῵ഫ˖Џ㽕ᰃᇍϔѯᆘᄬ఼䖯㸠䜡㕂ˈ
䖯㗠ਃࡼ៪㗙᥻ࠊϔѯӴ䕧῵ᓣˈᅲ⦄ЏҢ῵ഫП䯈ℷ⹂
ⱘ᭄᥂Ӵ䕧DŽ
SPI ⢊ᗕᆘᄬ఼῵ഫ˖Џ㽕⫼Ѣᄬ‫ټ‬῵ഫ೼Ꮉ԰䖛⿟Ё
ѻ⫳ⱘϔѯ⢊ᗕˈCPU ৃҹ䗮䖛ᶹⳟ䖭ѯ⢊ᗕ䖯㸠ϟϔℹ
ⱘ᪡԰DŽ
SPI ᥻ࠊ῵ഫ˖䖭Ͼ῵ഫᰃ᳔䞡㽕ⱘ䚼ߚˈ䖭Ͼ῵ഫЁ
ѻ⫳ⱘ᥻ࠊֵো⫼ᴹ᥻ࠊ᭄᥂ⱘথ䗕ˈ᭄᥂ⱘ᥹ᬊㄝˈৃ
ҹ䇈ˈᭈϾ᥹ষ῵ഫП᠔ҹ㛑໳ℷᐌⱘᎹ԰ˈϢℸ῵ഫᆚ
ϡৃߚDŽ
⿏ԡ᥻ࠊ䘏䕥῵ഫ˖಴Ў᮴䆎ᰃ᭄᥂ⱘথ䗕䖬ᰃ᭄᥂ ೒ 4 SCK 䞛⫼ CPHA˙1 Ḑᓣᯊⱘ SPI Ӵ䗕ᯊᑣ೒
ⱘ᥹ᬊˈ䛑ᰃ䗮䖛⿏ԡᆘᄬ఼ϔԡϔԡⱘ䖯㸠Ӵ䕧ⱘˈ䖭
Ͼ䖛⿟ህᰃ೼䖭Ͼ῵ഫЁ䖯㸠ⱘDŽ ᔧЏ SPI ᠔೼ⱘ MCU ‫ ݭ‬SPIDRˈਃࡼ SPI Ӵ䗕ৢˈ SS
े᳝ᬜˈ㗠Џ SPI 㽕㒣 1/2 SCK ਼ᳳⱘৠℹᓊ䖳ˈ✊ৢᓔ
Ёᮁ᥻ࠊ䘏䕥῵ഫ˖SPI ᥹ষ῵ഫѻ⫳ⱘЁᮁֵোⱘ䖛
ྟӴ䗕DŽ೼Ӵ䗕ⱘ䍋ྟ⚍থߎ㄀ϔϾ SCK ⊓ˈ䖭Ͼ SCK
⿟ህথ⫳೼䖭Ͼ῵ഫЁˈѻ⫳ⱘЁᮁֵো䗮䖛䖭Ͼ῵ഫӴ
⊓԰⫼ѢЏ/Ң⿏ԡᆘᄬ఼ˈՓ⿏ԡᆘᄬ఼ⱘ᳔催ԡ⿏㟇
䕧㒭Ёᮁ῵ഫˈ㗠Ϩ䖬䍋ࠄњϔϾḹṕⱘ԰⫼DŽ
MOSI/MISO ᓩ㛮㒓Ϟˈ೼㄀ѠϾ SCK ⊓໘Џ/Ң SPI 䞛ḋ
ᯊ䩳᥻ࠊ䘏䕥῵ഫ˖Ϣ᥻ࠊ῵ഫϔ䍋԰⫼ѻ⫳Ӵ䕧ᯊ ৘㞾ⱘ䕧ܹ㒓DŽৢ㓁 SCK ⊓ⱘ԰⫼㉏ԐDŽ೼㄀ 17 Ͼ⊓П
䩳 SCKˈ԰Ў᭄᥂Ӵ䕧ⱘᯊ䩳DŽ ৢˈЏǃҢঠᮍⱘ᭄᥂ᆘᄬ఼䞠ⱘ᭄᥂ᕫҹѸᤶˈSCK ᯊ
䩳‫ذ‬ℶˈSPI ⢊ᗕᆘᄬ఼Ёⱘ TC ᷛᖫ㕂ԡˈ㸼ᯢӴ䗕㒧
ᴳDŽ

4530
• CPHA=0 ⱘӴ䗕Ḑᓣ˖ Ӵ䕧ҹৢˈৃҹ䖲㓁৥᭄᥂ᆘᄬ఼Ё‫ܹݭ‬ϸϾ᭄᥂ˈབ
೒˖0x66 ੠ 0x36,✊ৢˈ䗮䖛 pad ᓩ㛮থ䗕ߎএDŽ
೒ 5 㒭ߎњ䞛⫼ CPHA˙0 ᯊ SPI ⱘᯊ䩳Ḑᓣ੠Ӵ䗕ᯊ
ᑣ೒DŽ spi_padi_do ֵোЎ pad ᓩ㛮ⱘ䕧ߎ᭄᥂ˈ݅ 5 ԡˈ݊
Ё㄀ѠԡЎ䕧ߎⱘ᭄᥂㒓(㰮㒓)ˈ೼Ӵ䕧ᯊ䩳(ccg_sck)
ϟˈᅠ៤᭄᥂ⱘথ䗕DŽ䗮䖛ℸ೒ৃҹⳟߎথ䗕ߎⱘ᭄᥂Ў
01100110ˈेЎ 0x66DŽ᭄᥂᥹ᬊᯊᑣ೒ӓⳳ㒧ᵰབ೒ 7 ᠔
⼎DŽ

೒ 7 ᭄᥂᥹ᬊ䖛⿟ⱘ ModelSim ӓⳳ೒⼎

spi_padi_ind Ў padi ッষⱘ䕧᭄ܹ᥂ˈ݊Ё㄀ϔԡ(े


೒ 5 SCK 䞛⫼ CPHA˙0 Ḑᓣᯊⱘ SPI Ӵ䗕ᯊᑣ೒ spi_padi_ind[0])Ў䕧ܹⱘ᭄᥂ˈҢ೒ 7 Ёৃҹⳟߎ䕧ܹⱘ
᭄᥂Ў 10010101(㰮㒓)ˈे 0x95DŽ㗠䇏ߎⱘؐ shfr_spidr
ᔧЏ SPI ᠔೼ MCU ‫ ݭ‬SPIDRˈਃࡼ SPI Ӵ䗕ৢˈ SS ℷདЎ 0x95DŽ
े᳝ᬜˈৠᯊӴ䗕ᓔྟˈЏ SPI ᇚ݊⿏ԡᆘᄬ఼ⱘ᳔催ԡ
⿏㟇 MOSI ᓩ㛮㒓ϞˈԚЏ SPI ೼Ӵ䗕ᓔྟৢ᥼䖳 1/2 V. ៤ક⌟䆩
SCK ਼ᳳথߎ㄀ 1 Ͼ SCK ⊓DŽ⬅Ѣ CPHA˙0 ᯊˈা㽕Ң
ᑨ⫼ᴀ SPI ᥹ষ᥻ࠊ఼ⱘ SoC 㢃⠛Ꮖ㒣៤ࡳ⌕⠛ˈ៤
SPI ⱘ SS ЎԢˈҢ SPI ⿏ԡᆘᄬ఼ⱘ᳔催ԡህߎ⦄೼ ક⌟䆩䆕ᯢ䆹 IP ⱘࡳ㛑੠ᗻ㛑䛑䖒ࠄњ䆒䅵ᣛᷛˈ㢃⠛
MISO ᓩ㛮Ϟˈᬙ೼䖭㄀ϔϾ SCK ⊓໘ˈЏ/Ң SPI 䞛ḋ৘ ⱘ៤ક⌟䆩㒧ᵰབ೒ 8 ᠔⼎˖
㞾ⱘ䕧ܹ㒓ˈ㗠೼㄀ 2 Ͼ SCK ⊓໘ˈঠᮍ⿏ԡᆘᄬ఼ᡞ
ϟϔԡ⿏㟇䕧ߎ㒓ϞDŽৢ㓁 SCK ⊓ⱘ԰⫼㉏ԐDŽ೼㄀ 17
Ͼ⊓ПৢˈЏҢঠᮍ SPIDR ᆘᄬ఼䞠ⱘ᭄᥂ᕫҹѸᤶˈ
SCK ᯊ䩳‫ذ‬ℶˈ῵ഫЁ⢊ᗕᆘᄬ఼Ёⱘথ䗕ᅠ៤ᷛᖫ㕂
ԡˈ㸼ᯢӴ䗕㒧ᴳDŽ

IV. ᥹ষ῵ഫⱘӓⳳ
ᴀ᭛᠔⍝ঞⱘ SPI ῵ഫⱘӓⳳˈ໻䚼ߚᰃ೼ᭈϾ㢃⠛ ೒ 8 㢃⠛ⱘ៤ક⌟䆩䘏䕥ߚᵤҾ៾೒
ЁⱘᅠᭈᶊᵘЁ䖯㸠ⱘˈSPI Ⳉ᥹⬅ CPU ᪡԰DŽ೼໻䞣ⱘ
䘏䕥䆒䅵ЁˈCPU 䛑ৃҹ䗮䖛䆹᥹ষℷ⹂ⱘᅠ៤᭄᥂ⱘথ ೒ 8 Ўᑨ⫼ Tektronix TLA5201 䘏䕥ߚᵤҾ೼ SPI ῵ഫ
䗕Ϣ᥹ᬊ[6-7]DŽ Ꮉ԰೼ Master ῵ᓣϟⱘ PAD ᓩ㛮ᡧপⱘֵো⊶ᔶ೒ˈ೒
೼䱣ৢⱘ FPGA ᑇৄӓⳳЁˈ䆹䆒䅵гℷ⹂ⱘᅠ៤њ Ё SCK Ў᭄᥂Ӵ䕧ᯊ䩳ˈ SS ЎԢ⬉ᑇ᳝ᬜⱘ⠛䗝ֵোˈ
Ϣढ䙺 SPI FLASH П䯈ⱘ᭛ӊⱘ䇏‫ˈݭ‬೼᳔㒜ⱘᗻ㛑ᮍ MOSI Ў䕧ߎⱘ᭄᥂ˈMISO Ў䕧ܹⱘ᭄᥂ˈ⌟䆩㒧ᵰ㸼
䴶ˈ㢃⠛ⱘ㋏㒳Џ乥Ў 24MHz ᯊˈSPI ᳔໻Ꮉ԰乥⥛Ў ᯢ SPI ᥹ষ῵ഫᎹ԰ℷᐌˈᑊϨ䗮䖛䆹᥹ষӴ䕧ⱘ᭄᥂ℷ
12MHzˈӴ䕧䗳ᑺৃ䖒 1.14Mb/sDŽ᭄᥂থ䗕ᯊᑣ೒ӓⳳ㒧 ⹂DŽ
ᵰབ೒ 6 ᠔⼎DŽ
VI. 㒧䆎
ᴀ᭛ᅠ៤њϔϾ 63, ᥹ষ᥻ࠊ఼ ,3 ⱘᅠᭈ䆒䅵ˈ䆹䆒
䅵ᅠܼ‫ݐ‬ᆍ 63, ᷛ‫ޚ‬ण䆂㗠Ϩࡳ㛑唤ܼˈৃϢӫ໮‫݋‬᳝
63, ᥹ষⱘ䆒໛䖯㸠䗮ֵDŽ㒣䖛৘⾡⌟䆩ഛ䆕ᯢњ䆹᥹ষ
῵ഫ䆒䅵ⱘৃ䴴ᗻ催ˈ♉⌏ᗻདˈ㸼ᯢ 63, ᥹ষ᥻ࠊ఼ⱘ
䆒䅵ᰃ៤ࡳⱘDŽ

೒ 6 ᭄᥂থ䗕䖛⿟ⱘ ModelSim ӓⳳ೒⼎ 㟈䇶


೒ 6 Ёˈsfrwb_datao Ў䗮䖛 SPI ᥹ষ῵ഫথ䗕ⱘ᭄ ᛳ䇶೑ᆊ㞾✊⾥ᄺ෎䞥˄No.˅ⱘ䌘ࡽDŽ
᥂ˈ⬅Ѣᴀ῵ഫᄬ೼ϔ㑻 FIFO ⱘॳ಴ˈ᠔ҹϞ⬉ৢᓔྟ

4531
REFERENCES [4] B. Qu, D. W. Fan, “Design of remote data monitoring and recording
system based on ARM,” 2010 2nd International Conference on
[1] A. K. Oudjida, M. L. Berrandjia, A. Liacha, et al. “Design and test of Industrial and Information Systems (IIS), 2010, pp. 252-255.
general-purpose SPI master/slave IPs on OPB bus,ā 2010 7th
International Multi-Conference on Systems Signals and Devices (SSD). [5] J. M. Ma, L. H. Jiang, W. Du, et al. “The embedded systems based M.
2010, pp. 1-6. CORE microcontroller,” Beijing: National Defence Industry Press, 2003,
pp. 141-143. (in chinese)
[2] J. M. Xing, P. He, Z. C. Wang, et al. “Design of data acquisition system
based on AD7367 and TMS320F2812,” 2010 International Conference [6] M. Turner, J.Naber, “The design of a bi-directional, RFID-based ASIC
on Computational and Information Sciences (ICCIS), 2010, pp. 380-383. for interfacing with SPI bus peripherals,” 2010 53rd IEEE International
Midwest Symposium on Circuits and Systems (MWSCAS), 2010, pp.
[3] X. H. Chen, D. Y. Zhang, and H. Y. Yang, “Design and implementation 554-557.
of a single-chip ARM-based USB interface JTAG emulator,” Fifth IEEE
International Symposium on Embedded Computing, 2008, pp. 272-275. [7] A. K. Oudjida, M. L. Berrandjia, R. Tiar, et al. “FPGA implementation
of I2C & SPI protocols: A comparative study,” 2009 16th IEEE
International Conference on Electronics, Circuits, and Systems(ICECS),
2009, pp. 507-510.

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