Preset 

(PRE) and clear (CLR) are asynchronous control inputs, which

means output responds to these inputs immediately because they have
control over the output that is because they are not synchronized by an
external clock.
When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0)
regardless of any of the synchronous inputs or the clock. When the clear
input is activated, the flip-flop will be reset (Q=0, not-Q=1), regardless of
any of the synchronous inputs or the clock.

Race around condition can be eliminated using the master-slave flip-flop. Master-Slave
flip-flop is the cascaded combination of two flip-flops among which the first is designated as
master flip-flop while the next is called slave flip-flop

Race around condition in JK flip-flop:

1. In JK flip flop as long as clock is high for the input conditions
2. J&K equals to the output changes or complements its output from 1–>0 and 0–>1.
3. This is called toggling output or uncontrolled changing or racing condition. Consider
above J&K circuit diagram as long as clock is high and J&K=11 then two upper and
lower AND gates are only triggered by the complementary outputs Q and Q(bar). I.e.
in any condition according to the propagation delay one gate will be enabled and
another gate is disabled.
4. If upper gate is disabled then it sets the output and in the next lower gate will be
enabled which resets the flip flop output.
Steps to avoid racing condition in JK Flip flop:
1. If the Clock On or High time is less than the propagation delay of the flip flop then
racing can be avoided. This is done by using edge triggering rather than level
triggering.
2. If the flip flop is made to toggle over one clock period then racing can be avoided.
This introduced the concept of Master Slave JK flip flop

Race Around Condition In JK Flip-flop – For J-K flip-flop, if J=K=1, and if

clk=1 for a long period of time, then Q output will toggle as long as CLK is
high, which makes the output of the flip-flop unstable or uncertain. This
problem is called race around condition in J-K flip-flop. This problem (Race
Around Condition) can be avoided by ensuring that the clock input is at logic
“1” only for a very short time. This introduced the concept of Master Slave
JK flip flop.
Master Slave JK flip flop –
The Master-Slave Flip-Flop is basically a combination of two JK flip-flops
connected together in a series configuration. Out of these, one acts as
the “master” and the other as a “slave”. The output from the master flip
flop is connected to the two inputs of the slave flip flop whose output is fed
back to inputs of the master flip flop.
In addition to these two flip-flops, the circuit also includes an inverter. The
inverter is connected to clock pulse in such a way that the inverted clock
pulse is given to the slave flip-flop. In other words if CP=0 for a master flip-
flop, then CP=1 for a slave flip-flop and if CP=1 for master flip flop then it
becomes 0 for slave flip flop.

lip flops can be used to store a single bit of binary data (1or 0). However, in
order to store multiple bits of data, we need multiple flip flops. N flip flops are
to be connected in an order to store n bits of data. A Register is a device
which is used to store such information. It is a group of flip flops connected in
series used to store multiple bits of data.
The information stored within these registers can be transferred with the help
of shift registers. Shift Register is a group of flip flops used to store multiple
bits of data. The bits stored in such registers can be made to move within the
registers and in/out of the registers by applying clock pulses. An n-bit shift
register can be formed by connecting n flip-flops where each flip flop stores a
single bit of data.
The registers which will shift the bits to left are called “Shift left registers”.
The registers which will shift the bits to right are called “Shift right registers”.
Shift registers are basically of 4 types. These are:
1. Serial In Serial Out shift register
2. Serial In parallel Out shift register
 3. Parallel In Serial Out shift register
4. Parallel In parallel Out shift register

Serial-In Serial-Out Shift Register (SISO) –

The shift register, which allows serial input (one bit after the other through a
single data line) and produces a serial output is known as Serial-In Serial-
Out shift register. Since there is only one output, the data leaves the shift
register one bit at a time in a serial pattern, thus the name Serial-In Serial-
Out Shift Register.
The logic circuit given below shows a serial-in serial-out shift register. The
circuit consists of four D flip-flops which are connected in a serial manner. All
these flip-flops are synchronous with each other since the same clock signal
is applied to each flip flop.

The above circuit is an example of shift right register, taking the serial data
input from the left side of the flip flop. The main use of a SISO is to act as a
delay element.

e know that one flip-flop can store one-bit of information. In order to store multiple
bits of information, we require multiple flip-flops. The group of flip-flops, which are
used to hold storestore the binary data is known as register.
If the register is capable of shifting bits either towards right hand side or towards left
hand side is known as shift register. An ‘N’ bit shift register contains ‘N’ flip-flops.
Following are the four types of shift registers based on applying inputs and
accessing of outputs.
  Serial In − Serial Out shift register
 Serial In − Parallel Out shift register
 Parallel In − Serial Out shift register
 Parallel In − Parallel Out shift register

Serial In − Serial Out SISOSISO Shift Register

The shift register, which allows serial input and produces serial output is known as
Serial In – Serial Out SISOSISO shift register. The block diagram of 3-bit SISO
shift register is shown in the following figure.

This block diagram consists of three D flip-flops, which are cascaded. That means,
output of one D flip-flop is connected as the input of next D flip-flop. All these flip-
flops are synchronous with each other since, the same clock signal is applied to
each one.
In this shift register, we can send the bits serially from the input of left most D flip-
flop. Hence, this input is also called as serial input. For every positive edge
triggering of clock signal, the data shifts from one stage to the next. So, we can
receive the bits serially from the output of right most D flip-flop. Hence, this output is
also called as serial output.
https://www.tutorialspoint.com/digital_circuits/digital_circuits_shift_registers.htm

Example

Let us see the working of 3-bit SISO shift register by sending the binary
information “011” from LSB to MSB serially at the input.
Assume, initial status of the D flip-flops from leftmost to rightmost
is Q2Q1Q0=000Q2Q1Q0=000. We can understand the working of 3-bit SISO
shift register from the following table.
No of positive edge of Serial Input Q2 Q1 Q0
Clock

0 - 0 0 0
 1 1LSBLSB 1 0 0

2 1 1 1 0

3 0MSBMSB 0 1 1LSBLSB

4 - - 0 1

5 - - - 0MSBMSB

The initial status of the D flip-flops in the absence of clock signal

is Q2Q1Q0=000Q2Q1Q0=000. Here, the serial output is coming from Q0Q0. So,
the LSB 11 is received at 3rd positive edge of clock and the MSB 00 is received at
5th positive edge of clock.
Therefore, the 3-bit SISO shift register requires five clock pulses in order to produce
the valid output. Similarly, the N-bit SISO shift register requires 2N-1 clock pulses
in order to shift ‘N’ bit information.

Characteristics table for SR Nand flip-flop. Characteristics table is determined by

the truth table of any circuit, it basically takes Qn, S and R as its inputs and
Qn+1 as output. Qn+1 represents the next state while Qn represents the present state.

http://webpages.eng.wayne.edu/~ad5781/ECECourses/ECE2610/LectureNotes/Lec
ture11.pdf

https://www.vssut.ac.in/lecture_notes/lecture1430873727.pdf

https://www.cs.tau.ac.il/~nin/Courses/mivne98/counters/