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Lect 6 P Channel JFET

The document discusses the construction and working of a p-channel JFET. It describes: 1) How a p-channel JFET is constructed with a p-type semiconductor bar containing two diffused n-type regions to form the gate, with ohmic contacts on the ends to form the drain and source. 2) How it works, with the channel pinching off as VGS becomes more positive, reducing the drain current ID. 3) The key characteristics of a JFET - drain/output characteristics showing ID vs VDS and transfer characteristics showing ID vs VGS, which identify the different operating regions including ohmic, saturation and breakdown.

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H.M. Rai
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100% found this document useful (1 vote)
1K views9 pages

Lect 6 P Channel JFET

The document discusses the construction and working of a p-channel JFET. It describes: 1) How a p-channel JFET is constructed with a p-type semiconductor bar containing two diffused n-type regions to form the gate, with ohmic contacts on the ends to form the drain and source. 2) How it works, with the channel pinching off as VGS becomes more positive, reducing the drain current ID. 3) The key characteristics of a JFET - drain/output characteristics showing ID vs VDS and transfer characteristics showing ID vs VGS, which identify the different operating regions including ohmic, saturation and breakdown.

Uploaded by

H.M. Rai
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Emerging Domain in Electronics Engineering (KEC-

101T/201T)
P-Channel JFET
Hari Mohan Rai
Asst. Prof., (ECE), Krishna Engineering College, Ghaziabad
Email ID: hari.mohan@krishnacollege.ac.in
P-Channel JFET
Construction of P channel JFET
• A semiconductor bar of P type material is taken Drain (D)
and ohmic contacts are made at the two ends of
the bar (Upper and lower) which are the Drain
and Source terminals, respectively.
• Both sides of P-type material, heavily doped N-
type regions are formed and both the N- regions
are connected together called a Gate terminal. N P N
Gate (G)
• P-type material is lightly doped and both the

Channel
diffused N-type materials are heavily doped.
• The thin region between the two N-type material
is called Channel. Since this channel is in the n-
type bar, hence it is known as P-Channel JFET.
Source (S)
Working of N-Channel JFET
The working of JFET is explained in three main
steps.
I. VGS= 0, VDS Some Negative Value
II. VGS small Positive
III. VGS large Positive
(i) VGS = 0, VDS Some Negative Value
• In this case, the depletion region is wider near the
top of both p-type materials, It is because the upper
region of the p-type material will be reverse biased
and the lower region will be less reverse-biased
(approximately forward bias).
• The p-n junction is reverse-biased because of zero
VGS,results in zero gate current(IG = 0A).
• Due to the negative VDS, the holes in channel will
flow from source to drain and current ID will flow in
same direction.
• As we keep on increasing the negative
VDS, the depletion region keeps on
increasing and the channel becomes
narrow.
• At a certain voltage, called PINCHOFF
VOLTAGE (VP)the depletion regions
almost touch each other and current
becomes constant. This condition is
called as PINCH OFF CONDITION.
• The value of drain current is maximum
at VGS= 0V. It is denoted as IDSS.
• At the pinch-off point: Any further
increase in VDS does not produce any
increase in ID.
(ii) VGS small positive
I. Due to positive VGS , the reverse biasing will increase
and the width of the depletion layer will decrease
more rapidly.
II. Due to reduced channel width, less number of holes
can pass through the channel from source to drain.
Thus, drain current ID reduces with increase in
positive VGS.
(iii) VGS large positive
• As VGS is further increased, the depletion regions
spreads more inside N-type region.
• At certain value of positive VGS (VGS= VP), the depletion
regions touch each other and width is therefore zero,
and the drain current ID = 0.
• The gate to source voltage at which drain current
reduces to zero is called VGS(off). The value of
VGS(off)= -Vp (pinch-off voltage)
Characteristics of JFET
1. Drain or Output characteristics (ID vs VDS ) by keeping VGS fixed.
2. Transfer Characteristics (ID vs VGS ) for VDS fixed.
Drain or Output Characteristics
 Graph is plotted between the drain current (ID) and Gate or Transfer Characteristics Drain or Output Characteristics
drain to source voltage (VDS) for the different values ID(mA)

of VGS. Ohmic Breakdown


Saturation Region
Region Region
(i) Ohmic Region: IDSS
VGS = 0v
• The region to the left of the pinch-off locus is referred
to as the ohmic region. Locus of Pinch-off
• In this region, the drain current ID varies with the
increase of VDS as per the ohm’s law. VGS = +1v

VGS = +2v
VGS = +3v
VGS = +4v
+VGS +4v +3v +2v +1v 0 -5v -10v -15v -20v -25v -VDS
(ii) Saturation Region
In the saturation region, the drain current ID remains fairly constant and does not vary with VDS.
(iii) Breakdown Region
In this region, at the high value of VDS the gate current increases very rapidly, this is called
breakdown region.
Gate or Transfer Characteristics Drain or Output Characteristics
ID(mA)

Ohmic Breakdown
Saturation Region
Region Region
IDSS
VGS = 0v

Locus of Pinch-off

VGS = +1v

VGS = +2v
VGS = +3v
VGS = +4v
+VGS +4v +3v +2v +1v 0 -5v -10v -15v -20v -25v -VDS
Transfer or gate Characteristics:
 It is drawn between drain current (ID) and gate to source voltage (VGS)
 From this graph it is easy to determine the value of ID for a given value of VGS
 It is also possible to determine IDSS and VP by looking at the knee where VGS is 0
Gate or Transfer Characteristics Drain or Output Characteristics
ID(mA)

Ohmic Breakdown
Saturation Region
Region Region
IDSS
VGS = 0v

Locus of Pinch-off

VGS = +1v

VGS = +2v
VGS = +3v
VGS = +4v
+VGS +4v +3v +2v +1v 0 -5v -10v -15v -20v -25v -VDS
Thank you

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