PATEL TIMIR(U18EC038)

EXPERIMENT-3
AIM:
A CMOS inverter circuit is characterized by following parameters.

Design Specifications:
NML = 1.08V , NMH = 1.75V,
VDD = 3.3V,
VT0,n = 0.6V , VT0,p = -0.7V
μnCox = 200 μA/V2μpCox = 80 μA/V2
1 μm Technology
Design the inverter which satisfies the given noise margin constraints. Verify that the design
meets Noise Margin constraints by writing a suitable WINSPICE code.

Procedure:
Step 1:
From NMH and NML values, calculate VIH and VIL
Given, NML = 1.08V , NMH = 1.75HVOH = VDD = 3.3V , VOL = 0V
NMH = VOH - VIH
=> 1.75 = 3.3 - VIH
=> VIH = 1.55V
NML = VIL - VOL
=> 1.08 = VIL - 0
=>VIL = 1.08V

Step 2:
At VIH, equate NMOS linear current equation with PMOS saturation current equation. Arrive
at a value for Kr(=Kn/Kp) and VOUT at VIH.
Given, VDD = 3.3V , VT0,n = 0.6V and VT0,p = -0.7V
At VIH , Vin = VIH = 1.55V
( Kn/2) [2(Vin - VT0,n ).Vout – Vout2 ] = ( Kp/2).(Vin – VDD -VT0,p )2 ---------(1)
=> (Kn/2) [ 2(1.55 – 0.6).Vout – Vout2 ] = ( Kp/2).(1.55 – 3.3+ 0.7)2
=> Kr = 1.1025 /[1.9Vout – Vout2 ] ----------(2)
Differentiating (1) both sides w.r.t Vin and subtituing Vin = VIH and (dVout/dVin) = -1
Kn .[-VIH + VT0,n + 2Vout ] = Kp.(VIH - VDD -VT0,p )
 PATEL TIMIR(U18EC038)

=>Kn .[-1.55 + 0.6 + 2Vout ] = Kp.(1.55 - 3.3+ 0.7)

Vout = 0.2672V Kr = 2.53

Step 3:
At VIH, equate PMOS linear current equation with NMOS saturation current equation. Arrive
at another value for Kr(=Kn/Kp) and VOUT at VIL.
Given, VDD = 3.3V , VT0,n = 0.6V and VT0,p = -0.7V
At VIH , Vin = VIL = 1.08V
( Kn/2).(Vin - VT0,n )2 = ( Kp/2).[2.(Vin – VDD -VT0,p )(Vout - VDD) – (Vout - VDD)2 ] ---(4)
=> (Kn/2).(1.08 –0.6)2 = ( Kp/2).[2.(1.08 – 3.3+0.7)(Vout – 3.3) – (Vout – 3.3)2 ]
=> Kr = [– Vout2+3.56Vout– 0.858]/0.2304 ----------
(5)
Differentiating (4) both sides w.r.t Vin and subtituing Vin = VIL and (dVout/dVin) = -1
Kn.(VIL - VT0,n ) = Kp.[-(VIL – VDD -VT0,p )+(Vout - VDD) + (Vout - VDD) ]
=>Kn.(1.08 -0.6) = Kp.[-(1.08 – 3.3+ 0.7)+(Vout – 3.3) + (Vout – 3.3) ]
=> Kr = 4.167Vout – 10.58 ----
------(6)
Comparing Eq (5) and (6) we get

Vout = 3.108V Kr = 2.37

Step 4:
Take average value of Kr. Calculate W/L ratios of NMOS and PMOS using Kr.
At VIH , Kr = 2.53 At VIL , Kr = 2.37
Taking average, Kr = (2.53+2.37)/2 = 2.45 ≈ 2.5
[μnCox (W/L)n] / [μpCox (W/L)p] = 2.5
=>[200 . (W/L)n] / [80 .(W/L)p] = 2.5
Given L = 1μm , => Ln = Lp= 1μm
Assume Wn = 1μm thenWp = 1μm
 PATEL TIMIR(U18EC038)

Code:
*CMOS inverter with given specs

.modelnmos NMOS VTO=0.6 kp = 200u

M1 out in 1 1 pmos W=1u L=1u

.dc vin 0 4 0.01

Simulation Plot:
 PATEL TIMIR(U18EC038)

Calculation:
Vth = (VT0,n+( (1/Kr)^0.5) (VDD + VT0,p))/(1+(1/Kr)^0.5)
Vth = (0.6+( (1/2.5)^0.5) (3.3 – 0.7))/(1+(1/2.5)^0.5)
Vth = 1.375V

Observation:

Parameters Theoretical Practical

VIH 1.55V 1.52V

VIL 1.08V 1.1V

VTH 1.375V 1.375V

NMH 1.75 1.78

NML 1.08 1.1

CONCLUSION:
In this experiment we have designed CMOS inverter for the given specifications and
then implemented the CMOS in WINSPICE and compared both theoretical and practical
values.
 PATEL TIMIR(U18EC038)

ASSIGNMENT
AIM:
A CMOS inverter circuit is characterized by following parameters.

Design Specifications:
NML = 1.65V , NMH = 2.4H,
VDD = 5V,
VT0,n = 0.7V , VT0,p = -0.7V
μnCox = 40μA/V2μpCox = 20 μA/V2
Design the circuits and verify your design for 1 μm Technology using a suitable WINSPICE
code.

Procedure:
Step 1:
From NMH and NML values, calculate VIH and VIL
Given, NML = 1.65V , NMH = 2.4H VOH = VDD = 5V , VOL = 0V
NMH = VOH - VIH
=> 2.4 = 5 - VIH
=> VIH = 2.6V
NML = VIL - VOL
=> 1.65 = VIL - 0
=>VIL = 1.65V

Step 2:
At VIH, equate NMOS linear current equation with PMOS saturation current equation. Arrive
at a value for Kr(=Kn/Kp) and VOUT at VIH.
Given, VDD = 5V , VT0,n = 0.7V and VT0,p = -0.7V
At VIH , Vin = VIH = 2.6V
( Kn/2) [2(Vin - VT0,n ).Vout – Vout2 ] = ( Kp/2).(Vin – VDD -VT0,p )2 ---------(1)
=> (Kn/2) [ 2(2.6 – 0.7).Vout – Vout2 ] = ( Kp/2).(2.6 – 5+ 0.7)2
=> Kr = 2.89/[3.8Vout – Vout2 ] ----------(2)
 PATEL TIMIR(U18EC038)

Differentiating (1) both sides w.r.t Vin and subtituing Vin = VIH and (dVout/dVin) = -1
Kn .[-VIH + VT0,n + 2Vout ] = Kp.(VIH - VDD -VT0,p )
=>Kn .[-2.6 + 0.7 + 2Vout ] = Kp.(2.6 - 5 + 0.7)
=> Kr = -1.7/[-1.9 + 2Vout ] ----------(3)
Comparing Eq (2) and (3) we get
3.23- 7.2Vout +Vout2=0 =>Vout = 0.481V =>Kr = 1.812

Step 3:
At VIH, equate PMOS linear current equation with NMOS saturation current equation. Arrive
at another value for Kr(=Kn/Kp) and VOUT at VIL.
Given, VDD = 5V , VT0,n = 0.7V and VT0,p = -0.7V
At VIH , Vin = VIL = 1.65V
( Kn/2).(Vin - VT0,n )2 = ( Kp/2).[2.(Vin – VDD -VT0,p )(Vout - VDD) – (Vout - VDD)2 ] ---(4)
=> (Kn/2).(1.65 –0.7)2 = ( Kp/2).[2.(1.65 – 5+0.7)(Vout – 5) – (Vout – 5)2 ]
=> Kr = [– Vout2+4.7Vout+1.5]/0.9025 ----------(5)
Differentiating (4) both sides w.r.t Vin and subtituing Vin = VIL and (dVout/dVin) = -1
Kn.(VIL - VT0,n ) = Kp.[-(VIL – VDD -VT0,p )+(Vout - VDD) + (Vout - VDD) ]
=>Kn.(1.65 -0.7) = Kp.[-(1.65– 5 + 0.7)+(Vout – 5) + (Vout – 5) ]
=> Kr = 2.105Vout – 7.73 -----
-----(6)
Comparing Eq (5) and (6) we get
8.48+ 2.8Vout - Vout2=0 =>Vout = 4.63V =>Kr = 2.02

Step 4:
Take average value of Kr. Calculate W/L ratios of NMOS and PMOS using Kr.
At VIH , Kr = 1.812 At VIL , Kr = 2.02
Taking average, Kr = (1.812+2.02)/2 = 1.916≈ 2
[μnCox (W/L)n] / [μpCox (W/L)p] = 2
=>[40 . (W/L)n] / [20 .(W/L)p] = 2
Given L = 1μm , => Ln = Lp= 1μm
Assume Wn = 1μm thenWp = 1μm
 PATEL TIMIR(U18EC038)

Code:
*CMOS inverter with given specs

.modelnmos NMOS VTO=0.7 kp = 40u

M1 out in 1 1 pmos W=1u L=1u

.dc vin 0 5 0.01

Simulation Plot:
 PATEL TIMIR(U18EC038)

Calculation:
Vth = (VT0,n+( (1/Kr)^0.5) (VDD + VT0,p))/(1+(1/Kr)^0.5)
Vth = (0.7+( (1/2)^0.5) (5 – 0.7))/(1+(1/2)^0.5)
Vth = 2.19V

Observation:

Parameters Theoretical Practical

VIH 2.6V 2.53V

VIL 1.65V 1.7V

VTH 2.19V 2.19V

NMH 2.4 2.47

NML 1.65 1.7

CONCLUSION:
In this experiment we have designed CMOS inverter for the given specifications and
then implemented the CMOS in WINSPICE and compared both theoretical and practical
values.