M.Tech.

VLPE104
Class Test – I 2014
Full Marks: 100
Time: 1 hour
(Answer Question No. 1 and any five from the rest)
Q.1. Answer the following questions: (2×10)
25 22
(a) A pn junction has N A =10 holes/m3 and N D=10 electrons/m3. What is the built-in
16
junction potential? Assume that ni =1 .5×10 carriers/m3.
Answer:
Φ
We know that the junction potential, 0 , is given by the expression

( )
N A ND kT
Φ 0=V T ln 2 V =
ni T
q .
, where,
o
With T ( the room temperature in degree Kelvin )≃300 K ,
k ( the Boltzmann's constant ) = 1. 38×10−23 JK−1 , and q ( the charge of an electron ) = 1 . 602×10−19 C ,
kT 1. 38×10−23×300
VT= = ≃26
we have, q 1. 602×10−19 mV.

( )
25 22
10 ×10
Φ 0=0. 026×ln =0 .88
16 2
Therfore, ( 1 . 5×10 ) V.
(b) A MOS transistor in the active region is measured to have a drain current of 20 A
V =V eff . When V DS is increased by 0.5 V, I D increases to 23 A. Estimate the
when DS
output impedance
r ds and the output impedance constant λ .
I | =20 μA I | =23 μA
Answer: Given D V DS=V eff and D V DS=V eff +0 .5 V , we have to find λ :
I D|V =V eff +5V =I D|V DS=V eff ¿ ( 1+ λ×0.5 )
We know that DS

Therefore,
λ=2 (2320 −1)=0 . 3 V . –1

ΔV 0.5
r ds =
= =167
r
Now, we find ds as ΔI 3. 0×10−6 k.
(c) It is sometimes useful in analog circuits to use a transistor biased in triode region as a
voltage controlled resistor. Use the following parameters to design a p-channel
2
MOSFET with a resistance of 100 kΩ, μ p C ox =25 μ A/V , Th
V =−1 V , V GS =−1 .2 V
V =0 V
, and SB . What is the necessary width, if the length is 5 μm?
Answer: When the MOSFET is in the linear region, it behaves like a voltage controlled resistor.
The resistance of a PMOSFET in the linear region can be written as:
 1
R=
W
μ p C ox( V −V Th )
L SG
Now, we can solve for the width to achieve a resistance of 100 KΩ as below:
1
100×103 =
( )
( 25×10−6 ) W ( 1 .2−1 )
5

or,
( )
W
5
=
1
( 25×10 )( 100×103 ) ( 0 . 2 )
−6

5
W= =10
so, 0. 5 µm.
Thus, width of the transistor is found to be 10 µm for the given values.
(d) Consider the circuit shown in the Figure Q.1(d) below, where
V in is a dc signal of 1 V.
V
Taking into account only the channel charge storage, determine the final value of out ,
when the transistor is turned off, assuming half the channel charge goes to C L . Given:
V Th =0 . 8 V and C ox =1. 9×10−3 pF/ ( μm)2 .

Figure Q.1(d) Figure Q.1(e)

Qch =WLC ox ( V GS −V Th )
Answer: Channel charge is given by .
Therefore, Qch =10× (1 . 2−2×0. 2 )×0. 0019×[ ( 5−1 ) −0 .8 ]=48 . 6 fC
1
Qch
Assuming 2 is injected into the storage capacitor, we have,
1 1
Q ×48 .6 fC
2 ch 2
ΔV =− =− =−24
CL 1 pF mV.
Therfore,
V out =V in −ΔV =1−0 .024=0 . 976 V.

(e)
( W
)
Determine the value of L for the circuit shown in Figure Q.1(e) that places M 1at
the edge of saturation and calculate the drain voltage change for a 1-mV change at the
gate. Assume
V Th =0 . 4 V.
Answer:
V
With GS
=+ 1 V, the drain voltage must fall to
V GS −V Th =1−0 . 4=0 . 6 V for M 1 to enter
the triode region. That is,
V −V DS
I D = DD =240
RD μA

Since I D
( W
scales linearly with L ,
)
W 240×10−6 2 2. 4
|max= × =
L 200×10−6 0 .18 0 . 18
V
If GS increases by 1 mV, I D =248 .04 μA changing V X by ΔV X = ΔI D×R D=4 . 02 mV.
The voltage gain is thus equal to 4.02 in this case.
(f) A MOSFET is biased at a drain current of 0.5 mA. Draw the low-frequency small-
signal equivalent circuit. If μnCox = 100 μA/V2, W/L = 10 and λ = 0.1 V–1, calculate its
small-signal parameters gm and rO.
Answer: Figure below shows the low-frequency small-signal equivalent circuit of a MOSFET:

Here we have,

√
gm= 2 μn C ox
1
W
I =1
L D mmohs,
rO = =20
Also, λI D kΩ.
(g) For the circuit shown in Figure Q.1(g) below, V DD=3 V ,
μn C ox =2 .5 μ p C ox=20 μA /V 2 , |V Th|=1 V , λ=0 , γ =0 , L=10 μm , W =30 μm .
Find V REF and I D .

Figure Q.1(g) Figure Q.1 (h)

Answer: Both the transistors have
V D=V G , and therefore, they are operating in saturation.
Therefore, I D 1 =I D 2=I D . Now writing the current equations for both the transistors, we
get,
1 W 1 W
μn C ox ( V REF −V Th ) 2= μ p C ox ( V DD −V REF−V Th )2
2 L 2 L
2 .5 ( V REF −1 )2 =20 ( 3−V REF −1 )2 ⇒ ( V REF −1 )2 =8 ( 2−V REF ) 2

 ( V REF −1 )=2 . 828 ( 2−V REF ) ⇒ V REF =1 . 216
V
1 30
I D = ×20× ( 1 .216−1 )2 =1. 4
2 10 A.
(h) A student connects two MOS transistors as shown in Figure 1(h) above to form a current
mirror, thinking that the gate current is zero and hence leaving the gates floating. Explain
what happens.
Answer: This circuit is not a current mirror because only a diode-connected device can establish
the relation ship
(W / L)M
I copy= 1
I
( W / L ) M REF REF

and hence a copy current independent of device parameters and temperature. Since the gates of M REF
and M 1 are floating, they can assume any voltage, e.g., an initial condition created at node X when
I
the power supply is turned on. In other words, copy is very poorly defined.
(i) Compute the parasitic resistance of the metal1 wire shown in the Figure Q.1(i) below,
where the metal1 resistivity is 0.08Ω/□.

Figure Q.1(i) Figure Q.1(j)

Answer: We have from the Figure number of squares as
□’s = (12λ/2λ) + 0.5 (2λ/2λ) + (4λ/2λ) + 0.5 (2λ/2λ) + (3λ/2λ)
or □’s = 6 + 0.5 + 2 + 0.5 + 1.5
or □’s = 10.5
The resistance is given by
resistance = □’s  0.08 Ω/□
or resistance = 10.5  0.08 Ω/□
or resistance = 0.84 Ω.
(j) With the help of equivalent circuit derive the low-frequency output impedance of the
source follower shown in the Figure Q.1(j) above.
Answer: The small-signal low-frequency equivalent circuit of the source follower is given in the
Figure below:
Summing currents at node :
i X−g m 1 v X −g mb1 v X−v X GS 1 =0

1 i
Gout = = X =g m 1 + gmb 1 +G S1
Therefore, R out v X
1 1
GS 1 =gds 1 + g ds 2= +
where, r ds 1 r ds 2
1 1 1
Rout = = ≃
or, gm 1 + g mb1 +G S1 g m1 + gmb1 + g ds 1 + gds 2 gm 1 + g mb1
Q.2. (a) Given a polysilicon resistor like the one shown in the Figure Q.2(a) below with
W =0 .8 μm and L=20 μm , calculate ρ s (in /□), the number of squares of
resistance and the resistance value. Assume that for silicon the resistivity is
ρ=9×10−4 Ω-cm and the polysilicon is 3000 Å thick. Ignore any contact resistance.
(8)

Figure Q.2(a) Figure Q.2(b)

Answer: First let us calculate
ρs:
 ρ 9×10−4
ρ s= = =30
T 3000×10−8 /□.
The number of squares of resistance, N is
L 20×10−6
N= = =25
W 0 . 8×10−6
The total resistance is given by
R=ρs ×N=30×25=750 
(b) The NMOS transistors in the circuit shown in the Figure Q. 2(b) above have
μn C ox =120 µA/V2, V Th =1. 0 V, λ=0 , and L1 =L2=1 . 0 µm. Find the required
values of gate width for each of Q1 and Q2, and the value of R , to obtain the voltage
and current values indicated in the Figure. (8)
Answer: Referring to the Figure we have, VGS1 = 1.5 V, and from the current equation given by

( ) ( )
1 W 1 W
I D =120 μA= μn C ox 1 ( V GS 1−V THn )2 = 120 1 ( 1 .5−1 )2
2 L1 2 1
we get, W1 = 8 µm.
Again, we have, VGS2 = (3.5 – 1.5) V = 2 V, and from the current equation given by

( ) ( )
1 W 1 W
I D =120 μA= μn C ox 2 ( V GS 2−V THn )2 = 120 2 ( 2−1 )2
2 L2 2 1
we get, W2 = 2 µm.
The value of R, to obtain the voltage and current values indicated in Figure 23 is found to be
5−3 .5
R= =12. 5
120×10−6 kΩ.
Q.3. (a) Consider the circuit given in Figure Q.3(a) below. Determine IDQ, VSDQ and gm of the p-
MOSFET. Given that
V Thp=−2 V and K p =μ p C ox ( W / L )=1 mA /V 2 . (10)

Figure Q.3(a) Figure Q.3(b)

V dd −V SS ( 10 V )−(−10 V )
V G=V SS + R 2=− (10 V ) ×( 22 K ) =4 . 67 V
Answer: R1 +R 2 ( 8 K ) + ( 22 K )
V S =V dd −I D R D =( 10 V )−I D ( 0 .5 K Ω )
 V GS =V G−V S =( 4 .67 V )− [ ( 10 V )−I D ( 0. 5 KΩ ) ]=−( 5 . 33 V ) + I D ( 0 . 5 K Ω )
V >V +V
Assuming that the transistor is in saturation (i.e., SD GS Tp ), then the current ID is:
mA
( )
I D =K p ( V GS−V Tp ) = 1 2 [ −( 5. 33 V )+I D ( 0. 5 KΩ )−(−2 V ) ]
2
V
2

=( 11. 1 mA )−3 . 33 I D +0 .25 I 2D

We now have the equation
0 . 25 I 2D−3 . 33 I D + ( 11.1 mA )=0
The solution for this equation is
4 . 33± √( 4 .33 ) −4×0 .25×11.1 4 .33±2 .77 14 . 2 mA
{
2
I D= = =
0.5 0 .5 3 . 1 mA
which gives two values of VGS as below:
V GS =−( 5 .33 V ) +I D ( 0 .5 K Ω )=−( 5. 33 V )+ (14 .2 mA )( 0 . 5 K Ω ) =1. 77 V
and V GS =−( 5 .33 V ) +I D ( 0 .5 K Ω )=−( 5. 33 V )+ ( 3. 1 mA ) ( 0 .5 K Ω )=−3 . 78 V
So, we decide that the current ID should be 3.1 mA, since VGS has to be less than VTp for current
conduction. Thus, we get,
V SDQ=V dd −V SS −I D ( R D +R S )= (10 V )−(−10 V )−( 3 . 1 mA )×( 2 .5 k Ω )=12 .25 V

Now check whether the transistor is really in saturation region (i.e.,

V SD >V GS +V Tp ):
( 12 .25 V ) > ( 3 .78 V )−( 2 V )=1. 78 V
This verifies that the transistor operates in the saturation region. Now to find gm, we use the equation
∂I
gm= D =2 K p|V GS−V Tp|=2× 1
∂ V GS
mA
V (
2 )
×|( 3 .78 V )−(−2 V )|=3 . 56
mA
V
The results are: I D =3 .1 mA, V SDQ=12 .25 V, and gm=3. 56 mA/V2.

(b) Consider the current mirror shown in the Figure Q.3(b) above, where in
I =100 μA
2
and each transistor has ( W /L ) =( 100 μm ) / ( 1 . 6 μm ) . Given that μn C ox =92 μA / V ,
V Th =0 . 8 V and r ds= [ 8000 L ( μm ) ] / [ I D ( mA ) ] , find r out for the current mirror and
g I
the value of m 1 . Also, estimate the change in out for a 0.5 V change in the output
voltage. (6)
Answer: Since the ( W /L ) ratios of the MOSFETs M 1 and M 2 are the same, the nominal value of
I out =I in =100 μA . Thus, we have
8000 L 8000×1 . 6
r out =r ds 2= = =128 k Ω
ID 0.1
The value of
gm 1 is given by
gm 1 =√ μ n C ox ( W /L ) I D 1 =1 .07 mA /V
r
The change in output current can be estimated, using out , as
ΔV out 0 .5
ΔI out = = =3 . 9 μA
r out 128×103
 r
Note that this estimate does not account for second-order effects such as the fact that ds changes as
the output current changes.
Q.4. (a) Calculate the output resistance and the minimum output voltage, while maintaining all
devices in saturation, for the circuit shown in the Figure Q.4(a) below. Assume that
i OUT is actually 10 μA. Use the following device model information: V Th 0=0. 7 V ,
μn C ox =K n =110 μA/V 2 , γ=0.4 V 1/2 , λ=0 . 04 V−1 , 2|φ F|=0.7 V . The ( W /L )
'

values of each transistor are shown in the Figure below. (12)

Figure Q.4(a) Figure Q.4(b)

Answer: First calculate node voltages and currents. Assume a near perfect current mirror so that
the current in all devices is 10 μA. Calculate node voltages.

√ √ √
2i 2×10×10−6 20
V GS 3=V G 3 = ' D + V Th= −6
+0 .7= +0 . 7=0. 891 V
K n ( W / L )3 110×10 ×5 550
V SB2=V G 3 =0 .891 V , V DS1 =V G 3 +V GS 4 −V GS2
Because all devices are matched
gm 2 =gm 4 = √2 K 'n ( W / L ) I D =√ 2×110×10−6 × (5 /1 )×10×10−6 =104 . 9 μA /V
g m 2×γ 104 .9×10−6 ×0 . 4
gmb 2=g mb4 = = =16 . 63 μA /V
2 (√ 2|φ F|+V SB ) 2 ( √0 . 7+0 . 891 )
v out
i out ds 1 ds 2 [ ( m 2 mb 2 ) ds2 ] ds 1
r out = =r + r + g + g r r

1 1
r ds 1 =r ds 2 = = =2 .5 MΩ
λI D 0 .04×10×10−6
r out =2 .5×106 +2 .5×106 + [ ( 104 . 9×10−6 +16 . 63×10−6 )×2 .5×106 ]×2 . 5×106
=764 M Ω
The minimum voltage across drain and source while remaining in saturation is ON , which is given
V
by

√ √ √
2I D 2×10×10−6 20
V ON = '
+V Th = −6
+0 . 7= + 0. 7=0 .763 V
K n ( W /L ) 110×10 ×5 550
So,
VON 2 =0 .702 V . Therefore, the minimum output voltage to keep devices in saturation is
given by
V out ( min )=V DS1 +V ON 2 =V G 3 +V GS 4 −V GS 2 +V ON 2
=0 . 891+0 . 891−0 . 7+0 .762=1. 844 V
(b) Figure Q.4(b) above illustrates a reference circuit that provides an interesting reference
voltage output. Derive a symbolic expression for V REF . (4)
Answer: From the Figure above, we have,
V GS 1 +V GS 3−V GS 4 =V REF , V REF=V ON 1 +V Th1 +V ON 3 +V Th 3−V ON 4 +V Th4
V Th 3=V Th4 , V ON 1 =2V ON 3 ,
Therefore,
V REF=2 V ON 1 +V Th 1 +V Th 3 −2V ON 1 −V Th 3
or,
V REF=V Th 1
Q.5. (a) The cascode amplifier shown in the Figure Q.5(a) below incorporates the following
device parameters: ( W /L )1 , 2=30 , ( W /L )3 , 4 =40 and I D 1 =⋯=I D 4 =0. 5 mA . If
2 −1
μn C ox =100 μ A/V 2 , μ p C ox =50 μ A/V , λ n=0. 1 V −1 and λ p =0 .1 V , determine the
voltage gain. (8)

Figure Q.5(a) Figure Q.5(b)

Answer: With the particular choice of identical NMOS and identical PMOS devices we have,
gm 1 =gm 2 , r O 1 =r O 2 , gm 3 =gm 4 , and r O 3 =r O 4 . Thus, we can find

√ ( )
gm1 ,2= 2 μn C ox
W
L 1,2
I D 1,2 =√ 2×100×10−6 ×30×0. 5×10−3 =( 577 Ω )−1

gm1 , 2

r O 1 , 2=
√
= 2μ C ( )
W
L
1
p ox

=
3,4
1
I D 3, 4 =√2×50×10−6 ×40×0 .5×10−3 =( 707 Ω )−1

=20 Ω
Also,
λ n I D 1 , 2 0. 1×0. 5×10−3
1 1
r O3 , 4 = = =13 . 33 Ω
λ p I D 3 , 4 0. 15×0. 5×10−3
The output impedance components of the NMOS – PMOS cascade is given by
 Ron≈ gm2 r O2 r O1 and Rop≈ gm3 r O3 r O4
20×103 ×20×103
Ron≈ gm 2 r O 2 r O 1= =693 . 24 k Ω
Thus we have 577
13 . 33×10 3×13. 33×103
Rop≈ gm 3 r O 3 r O 4 = =252. 33 k Ω
and 707
1
A v=−g m 1 ( Ron||Rop ) =− ( 693 . 24×103||252 .33×103 )≈320
Thus 577
(b) Using small-signal analysis, find the output impedance of a MOS cascode current
mirror shown in Figure Q.5(b) above. Include in your analysis the voltage-dependent
current source that models the body effect. (8)
Answer: We know that
R1 =r DS2 which gives us the small-signal model as shown in Figure below:

Writing the KCL at the output, we get,

−( g m 4 + g s 4 ) v s 4 + g DS 4 v x −g DS 4 v s4 −i x=0

Therefore, ( g m 4 + g s 4 + g DS 4 ) v s 4 +i x=g DS 4 v x
i
v s 4= x
But g DS 2

Therefore,
[
i x ( gm 4 +g s4 +g DS 4 ) ×
1
gDS 2 ]
+1 =g DS 4 v x

[ ]
vx 1 1
g DS4 (
Rout Δ = 1+ g m 4 +gs 4 +g DS4 )
ix g DS 4
Hence,

or,
[ (
Rout =r DS 4 1+r Ds 2 gm 4 +g s 4 +
1
r DS 4 )]
Q.6. In the circuit shown in Figure below, a source follower using a wide transistor and a small
bias current is inserted in series with the gate of M3 so as to bias M2 at the edge of saturation.
Assuming M0 – M3 are identical and  ≠ 0, estimate the mismatch between Iout and IREF if (a)
γ = 0, (b) γ ≠ 0. (16)
 Figure Q.6
Answer: (a) For γ=0 we have
1
k 0= μC ox
2
W0 2
I REF =k 0 ( V GS1 −V Th ) ( 1+ λV DS1 )
L'0
W0 2
I out =k 0 ' ( V GS1 −V Th ) ( 1+ λV DS2 )
L0
where
V DS1 =V GS 1 and V DS2 =2V GS1 −V GS 4 −V GS 3
If we assume
I out≈ I REF , V GS 3≈V GS1 , we have V DS2 =V GS 1−V GS 4

V GS 1=V Th +
√
I REF L'0
V =V Th +
k 0 W 0 , GS 4
I 1 L'4
√
k 0 W 4 , where L'0 =L−2 LD

I out 1+ λV DS 2
= =
1+ λ (√ I REF L'0
k0 W 0 √ )
I L' 4
− 1
k0 W 4

( √ )
I REF 1+ λV DS 1
I REF L'0
1+ λ V Th +
k0 W 0
So,
(b) For γ≠0 we have
V Th=V Th 0+γ ( √ 2|φ f|+V SB −√2|φf |) φ f ≃0 . 45 V is the work function and V SB is the
, where
V V V V
voltage between Source to Substrate. We have to now find GS 1 , GS 0 , GS 3 and GS 4

V GS 1=V Th 0 +
√
I REF L'0
V =V Th0 +
k 0 W 0 , GS 0
I REF L'0
k0 W 0 ( √ f √
+γ 2|φ |+V GS 1 −√ 2|φf |)
,

V GS 3=V Th0 +
√ I out L'0
k0 W0 (√ f
+ γ 2|φ |+V DS2 −√ 2|φ f|)
,
If we assume
I out≈ I REF and
V DS2 ≈
√
I REF L'0
k0 W 0
I L
− 1 4
√
k 0 W 4 we can estimate V GS 3 as

V GS 3≈V Th0 +
√ I out L'0
k0 W 0
+γ
(√ (√
2|φ f|+
I REF L'0
k0 W 0
−
√ )√ )
I 1 L4
k0 W 4
− 2|φ f|
,

√
'
I out L0
k 0 W 0 (√
V GS 4 =V Th 0 + + γ 2|φ f|++ V GS 3 +V DS2 −√ 2|φ f|)
and
Now, we can substitute the values of all the voltages into the final equation
I out 1+ λ ( V GS 1 +V GS 0−V GS3 −V GS 4 )
=
I REF 1+λV GS 1 .

End of Answers