Scribd
Upload
35 views2 pages

2nd de QP 18-10-2019

Uploaded by

Deepa Jerin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
35 views2 pages

2nd de QP 18-10-2019

Uploaded by

Deepa Jerin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 2

USN 1 C E COURSE CODE:18EC34

CITY ENGINEERING COLLEGE


SECOND INTERNAL TEST
Programme: EC Date:22/10/2019
Course Name: Digital System Design Time:2:30pm-4:00
pm
Sem : III Max Marks: 50
Duration: 1 ½ hrs.
Note: Answer all Questions selecting any ONE FULL questions from each part.
Q Sub
No Q Questions Marks CO’s BT’S
. No.
PART-A
Explain Mealy and model and Moore model for clocked
1 synchronous sequential network. Explain Synchronous 10 CO3 L1,L2,L3
Sequential Circuit Analysis.
OR
Construct the transition table, state table and state diagram
for sequential circuit given.

J Q A
F

X K ~Q A

2 10 CO3 L1,L2,L3

J Q B

K ~Q B

CLK

PART-B
3 10 CO3 L1,L2,L3
Analyse the synchronous circuit of the figure below (and all
clock signals are implicit).
i. Write down the excitation and output function.
ii. Form the excitation and state tables.
iii. Give a word description of the circuit operation.
X J Q A J Q B

CLK CLK

X K ~Q A K ~Q B

Z
OR
Give output function, transition table and state diagram by
analyzing the sequential circuit shown.

B
Q A
SET
S Q S
SET

4 10 CO3 L1,L2,L3
CLK B
R CLR Q R CLR Q A

PART-C
With neat schematic diagram of Master salve SR flip flop,
5 discuss its operation with timing diagram. 10 CO3 L1,L2,L3

OR
L1,L2,L3
With neat schematic diagram of Master salve JK flip flop,
6 discuss its operation with timing diagram. 10 CO3

PART-D
L1,L2,L3
7 Design a mod 8 Asychronous down counter using JK flip flop. 10 CO3

OR
L1,L2,L3
8 Design4 bit binary ripple counter using JK flip flop. 10 CO3
PART-E
L1,L2,L3
Design a 3 bit synchronous binary up counter using D flip flop
9 10 CO3

OR

10
Design a mod 6 sychronous up counter using JK flip flop 10 CO3 L1,L2,L3

Bloom’s Taxonomy:L1: Remembering L2: Understanding L3: Applying


Course Outcomes:CO3: • Design the sequential circuits using SR, JK, D, T flip-flops and Mealy & Moore machines

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy