CSE 205: DIGITAL LOGIC DESIGN

Md. Hasan Al Kayem

Lecturer
CSE, UIU
TEXTBOOK
 Digital Design (5th Edition)
 M. Morris Mano
 Michael D. Ciletti
COMBINATIONAL LOGIC
 Combinational Logic:
 Output depends only on current input
 Has no memory
SEQUENTIAL LOGIC
 Sequential Logic:
 Output depends not only on current input but
also on past input values, e.g., design a counter
 Need some type of memory to remember the
past input values
ALARM CONTROL SYSTEM
 Suppose we wish to construct an alarm circuit such
that the output remains active (on) even after the
sensor output that triggered the alarm goes off
 The circuit requires a memory element to
remember that the alarm has to be active until a
reset signal arrives
SEQUENTIAL CIRCUITS
 Consist of a combinational circuit to which storage
elements are connected to form a feedback path
 State: –the state of the memory devices now, also
called current state
 Next states and outputs are functions of inputs
and present states of storage elements
TWO TYPES OF SEQUENTIAL CIRCUITS
 Synchronous sequential circuit
 circuit output changes only at some discrete
instants of time.
 Synchronized by a periodic train of clock pulses
 Much easier to design (preferred design style)

 Asynchronous sequential circuit

 circuit output can change at any time (clockless)
 May have better performance but hard to design
SYNCHRONOUS SEQUENTIAL CIRCUITS
MEMORY ELEMENTS
 A digital circuit that can maintain a binary state
indefinitely, until directed by an input signal to
switch states

 Differences among different types of storage

elements depends on
 The number of inputs they possess
 The manner in which the inputs affect the
binary state
MEMORY ELEMENTS
 Latch -—a level-sensitive memory element
 SR latches
 D latches
 Flip-Flop —
- an edge-triggered memory element
 Master-slave flip-flop
 Edge-triggered flip-flop
 RAM and ROM — a mass memory element
LATCHES
 A latch is binary storage element
 Can store a 0 or 1

 The most basic memory

 Easy to build

 Built with gates (NORs, NANDs, NOT)

LATCHES
S R Q0 Q Q’
 SR Latch 0 0 0 0 1 Q = Q0

R 0 0
Q

S Q
0 1

Initial Value
LATCHES
S R Q0 Q Q’
 SR Latch 0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R 0 1
Q

S Q
0 0
LATCHES
S R Q0 Q Q’
 SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 0
Q

S Q
0 1
LATCHES
S R Q0 Q Q’
 SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 1
Q
0 1 1 0 1 Q=0

S Q
0 0
LATCHES
S R Q0 Q Q’
 SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 0
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0 Q=1

S Q
1 1
LATCHES
S R Q0 Q Q’
 SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 0
Q=0
1 0 1 1 0 1
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

S Q
1 0
LATCHES
S R Q0 Q Q’
 SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10
LATCHES
S R Q0 Q Q’
 SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1
Q=0
10 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0
SR LATCH
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S R Q
Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
SR LATCH
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S’ R’ Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
Q 1 0 0 Reset
R Q0 No change
1 1
CONTROLLED LATCHES
 SR Latch with Control Input
R R S S
Q Q
C C
S Q R Q
S R

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid
CONTROLLED LATCHES
Timing Diagram
 D Latch (D = Data)
C
D S
Q
D
C
R Q Q

t
C D Q
Output may
0 x Q0 No change
change
1 0 0 Reset
1 1 1 Set
CONTROLLED LATCHES
Timing Diagram
 D Latch (D = Data)
D S C
Q
C D
R Q
Q

C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set
GRAPHIC SYMBOLS FOR LATCHES
LEVEL VERSUS EDGE SENSITIVITY
 Since the output of the D latch is controlled by the
level (0 or 1) of the clock input, the latch is said to
be level sensitive
 All of the latches we have seen have been level
sensitive

 It is possible to design a storage element for which

the output only changes at the point in time when
the clock changes from one value to another
 Such circuits are said to be edge triggered
FLIP-FLOPS
 Controlled latches are level-triggered

 Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

 FLIP-FLOPS
 Master-Slave D Flip-Flop

D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C
Master Slave

CLK CLK

D
Looks like it is negative
edge-triggered QMaster

QSlave
FLIP-FLOPS
 The circuit samples the D input and changes its
output at the negative edge of the clock, CLK.
 When the clock is 0, the output of the inverter is 1.
The slave latch is enabled and its output Q is equal
to the master output Y. The master latch is
disabled (CLK = 0).
 When the CLK changes to high, D input is
transferred to the master latch. The slave remains
disabled as long as CLK is low. Any change in the
input changes Y,but not Q.
 The output of the flip-flop can change when CLK
makes a transition 1 → 0
 FLIP-FLOPS
 Edge-Triggered D Flip-Flop

D Q

Q
Q
CLK Positive Edge

Q
D Q

D
Q
Negative Edge
FLIP-FLOPS:
EDGE-TRIGGERED D FLIP-FLOP
FLIP-FLOPS

Set-up time and hold time are times required before

and after the clock transition that data must be present
to be reliably clocked into the flip-flop.
D
Setup time is the minimum
time for the data to be present CLK
before the clock.
Set-up time, ts

D
Hold time is the minimum
time for the data to remain CLK
after the clock.

Hold time, tH
JK FLIP-FLOPS

 When J = 1 and K = 0, D = 1 → next clock edge sets

output to 1.
 When J = 0 and K = 1, D = 0 → next clock edge
resets output to 0.
 When J = 1 and K = 1, D= Q’ → next clock edge
complements output.
 When J = 0 and K = 0, D= Q → next clock edge
leaves output unchanged.

 JK Flip-Flop : D = JQ’ + K’Q

JK FLIP-FLOPS
 JK Flip-Flop

J
D Q Q
K
CLK Q Q

J Q
D = JQ’ + K’Q
K Q
T FLIP-FLOPS
 T Flip-Flop

T J Q T D Q

Q
K Q

T Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T  Q Q
FLIP-FLOP CHARACTERISTIC TABLES
D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q 1 Q’(t) Toggle
FLIP-FLOP CHARACTERISTIC EQUATIONS
D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q 1 Q’(t)
FLIP-FLOPS WITH ASYNCHRONOUS/DIRECT
INPUTS
 Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q 1 0 ↑ 0
R 1 1 ↑ 1
Reset
FLIP-FLOPS WITH DIRECT INPUTS
 Asynchronous Reset
FLIP-FLOPS WITH DIRECT INPUTS
 Asynchronous Preset and Clear
Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q 1 1 0 ↑ 0
CLR 1 1 1 ↑ 1
Reset
ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS: THE STATE
 State = Values of all Flip-Flops

Example
x
AB=00 D Q A

D Q B

CLK Q

y
ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS: TERMINOLOGY
 State Equation: A state equation (transition
equation) specifies the next state as a function of
the present state and inputs.
 State Table: A state table (transition table)
consists of: present state, input, next state and
output.
 State Diagram: The information in a state table
can be represented graphically in a state diagram.
The state is represented by a circle and the
transitions between states are indicated by
directed lines connecting the circles.
ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS: STATE/TRANSITION EQUATIONS

x
A(t+1) = DA D Q A

= A(t) x(t)+B(t) x(t)

Q
=Ax+Bx
B(t+1) = DB
= A’(t) x(t) D Q B

= A’ x CLK Q
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’ y
ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS: STATE /TRANSITION TABLE
x
Present Next D Q A
Input Output
State State
Q
A B x A B y
0 0 0 0 0 0
D Q B
0 0 1 0 1 0
0 1 0 0 0 1 CLK Q

0 1 1 1 1 0 y

1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1 A(t+1) = A x + B x
1 1 1 1 0 0 B(t+1) = A’ x
y(t) = (A + B) x’
t t+1 t
ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS: STATE/TRANSITION TABLE
x
Present Next State Output D Q A

State x=0 x=1 x=0 x=1 Q

A B A B A B y y
0 0 0 0 0 1 0 0 D Q B
0 1 0 0 1 1 1 0
CLK Q
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0 y

t t+1 t A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS: STATE DIAGRAM
Present Next State Output
State x=0 x=1 x=0 x=1
AB input/output A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
0/0 1/0
1 0 0 0 1 0 1 0
0/1 1 1 0 0 1 0 1 0
00 10
x
D Q A

0/1 Q
1/0 0/1 1/0
D Q B

CLK Q
01 11
y

1/0 46
ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS: D FLIP-FLOPS
Example:
x D Q A
Present Next y
Input
State State CLK Q
A x y A
0 0 0 0
0 0 1 1 A(t+1) = DA = A  x  y
0 1 0 1
0 1 1 0
1 0 0 1 01,10
1 0 1 0
00,11 0 1 00,11
1 1 0 0
1 1 1 1 01,10
ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS: JK FLIP-FLOPS
J Q A

Example: x K Q

Present Next Flip-Flop

I/P J Q B
State State Inputs
A B x A B JA KA JB KB K Q
0 0 0 0 1 0 0 1 0 CLK
0 0 0 0 0 1
0 0 1 JA = B KA = B x’
0 1 0 1 1 1 1 1 0
JB = x’ KB = A  x
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1 A(t+1) = JA Q’A + K’A QA
1 0 1 1 0 0 0 0 0 = A’B + AB’ + Ax
1 1 0 0 0 1 1 1 1 B(t+1) = JB Q’B + K’B QB
1 1 1 1 1 1 0 0 0 = B’x’ + ABx + A’Bx’
ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS: JK FLIP-FLOPS J Q A

Example: x K Q

Present Next Flip-Flop J Q B

I/P
State State Inputs
A B x A B JA KA JB KB K Q

0 0 0 0 1 0 0 1 0 CLK

0 0 1 0 0 0 0 0 1 1 0 1
0 1 0 1 1 1 1 1 0 00 11
0 1 1 1 0 1 0 0 1
0
1 0 0 1 1 0 0 1 1 0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 01 10
1 1 1 1 1 1 0 0 0 1
1
ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS: T FLIP-FLOPS x T Q
A
y

Example: R Q

Present Next F.F

I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0
TA = B x TB = x
0 1 1 1 0 1 1 0
y =AB
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
1 1 0 1 1 0 0 1
1 1
B(t+1) = TB Q’B + T’B QB
1 1 1 0 0 1
=xB
ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS: T FLIP-FLOPS x T Q
A
y

Example: R Q

Present Next F.F

I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0 0 0
0 1 1 1 0 1 1 0 0 0/0 1 0 1/0

1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0 1 1
1 1 0 1 1 0 0 1 1 1/1 1 0/0

1 1 1 0 0 1 1 1 0 0
1
MEALY AND MOORE MODELS
 The Mealy model: the outputs are functions of both
the present state and inputs
 The outputs may change if the inputs change
during the clock pulse period.
 The outputs may have momentary false values
unless the inputs are synchronized with the
clocks.
 The Moore model: the outputs are functions of the
present state only
 The outputs are synchronous with the clocks.
MEALY AND MOORE MODELS

Block diagram of Mealy and Moore state machine

 MEALY AND MOORE MODELS
Mealy Moore
Present Next Present Next
I/P O/P I/P O/P
State State State State
A B x A B y A B x A B y
0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 0 1 0
0 1 0 0 0 1 0 1 0 0 1 0
0 1 1 1 1 0 0 1 1 1 0 0
1 0 0 0 0 1 1 0 0 1 0 0
1 0 1 1 0 0 1 0 1 1 1 0
1 1 0 0 0 1 1 1 0 1 1 1
1 1 1 1 0 0 1 1 1 0 0 1

For the same state, For the same state,

the output changes with the input the output does not change with the input
MOORE STATE DIAGRAM

State / Output

0 0
1
00/0 01/0

1 1

11/1 10/0
1
0 0
STATE REDUCTION
 Sequential circuit analysis
Circuit diagram state table (or state diagram)
 Sequential circuit design

State diagram (state table) circuit diagram

 Redundant state may exist in a state diagram (or
table)
 By eliminating them reduce the # of logic
gates and flip-flops
STATE REDUCTION

State: a a b c d e f f g f g a
Input: 0 1 0 1 0 1 1 0 1 0 0

Eastern Mediterranean University

Output: 0 0 0 0 0 1 1 0 1 0 0

 Only the input-output

sequences are important.
 Two circuits are equivalent
 Have identical outputs for

all input sequences;

 The number of states is
not important.

State diagram
STATE REDUCTION
 Equivalent states
 Two states are said to be equivalent
 For each member of the set of inputs, they

give exactly the same output and send the

circuit to the same state or to an equivalent
state.
 One of them can be removed.
STATE REDUCTION
STATE REDUCTION
 Reducing the state table
 e = g (remove g);
 d = f (remove f);
STATE REDUCTION
 The reduced finite state machine

State: a a b c d e d d e d e a
Input: 0 1 0 1 0 1 1 0 1 0 0
Output: 0 0 0 0 0 1 1 0 1 0 0
STATE REDUCTION: IMPLICATION TABLE
 The state-reduction procedure for completely
specified state tables is based on the algorithm
that two states in a state table can be combined
into one if they can be shown to be equivalent.
 There are occasions when a pair of states do not
have the same next states, but, nonetheless, go to
equivalent next states

 The checking of each pair of states for possible

equivalence in a table with a large number of
states can be done systematically by means of an
implication table.
STATE REDUCTION: IMPLICATION TABLE

 (a, b) imply (c, d) and (c, d) imply (a, b). Both pairs
of states are equivalent; i.e., a and b are equivalent
as well as c and d.

63
STATE REDUCTION:IMPLICATION TABLE
STATE REDUCTION: IMPLICATION TABLE
 Finally, all the squares that have no crosses are
recorded with check marks. The equivalent states
are: (a, b), (d, e), (d, g), (e, g).

 We now combine pairs of states into larger

groups of equivalent states. The last three pairs
can be combined into a set of three equivalent
states (d, e, g) because each one of the states in
the group is equivalent to the other two.
STATE REDUCTION: IMPLICATION TABLE
 The final partition of these states consists of the
equivalent states found from the implication
table, together with all the remaining states in
the state table that are not equivalent to any
other state: (a, b) (c) (d, e, g) (f)
STATE ASSIGNMENT
 Assign coded binary values to the states for
physical implementation
 For a circuit with m states, the codes must
contain n bits where 2n >= m
 Unused states are treated as don’t care
conditions during the design
 Don’t cares can help to obtain a simpler circuit
 There are many possible state assignments

 Have large impacts on the final circuit size

POPULAR STATE ASSIGNMENT
STATE ASSIGNMENT
 Any binary number assignment is satisfactory as
long as each state is assigned a unique number
 Use binary assignment 1
DESIGN PROCEDURE
 Derive a state diagram for the circuit from
specifications
 Reduce the number of states if necessary

 Assign binary values to the states

 Obtain the binary-coded state table

 Choose the type of flip-flop to be used

 Derive the simplified flip-flop input equations

and output equations
 Draw the logic diagram
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS
Example:
Detect 3 or more consecutive 1’s
0 1
S0 / 0 S1 / 0 State A B
0 S0 0 0
0 1 S1 0 1
0
S2 1 0
S3 1 1
S3 / 1 S2 / 0
1 1
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS
Example:
Detect 3 or more consecutive 1’s
Present Next
Input Output 0 1
State State
A B x A B y S0 / 0 S1 / 0
0 0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0 0 0 1
0 1 1 1 0 0
1 0 0 0 0 0
S3 / 1 S2 / 0
1 0 1 1 1 0
1 1
1 1 0 0 0 1
1 1 1 1 1 1
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS
Example:
Detect 3 or more consecutive 1’s
Present Next
Input Output
State State
Synthesis using D Flip-Flops
A B x A B y
0 0 0 0 0 0 A(t+1) = DA (A, B, x)
0 0 1 0 1 0
= ∑ (3, 5, 7)
0 1 0 0 0 0
0 1 1 1 0 0 B(t+1) = DB (A, B, x)
1 0 0 0 0 0 = ∑ (1, 5, 7)
1 0 1 1 1 0 y (A, B, x) = ∑ (6, 7)
1 1 0 0 0 1
1 1 1 1 1 1
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS WITH D F.F.
Example:
Detect 3 or more consecutive 1’s
Synthesis using D Flip-Flops
B
DA (A, B, x) = ∑ (3, 5, 7) 0 0 1 0
A 0 1 1 0
=Ax+Bx
x B
DB (A, B, x) = ∑ (1, 5, 7) 0 1 0 0
= A x + B’ x A 0 1 1 0
y (A, B, x) = ∑ (6, 7) B
x
= AB 0 0 0 0
A 0 0 1 1
x
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS WITH D F.F.
Example:
Detect 3 or more consecutive 1’s
Synthesis using D Flip-Flops

DA = A x + B x D Q A
x
DB = A x + B’ x
y =AB Q
y

D Q B

CLK Q
FLIP-FLOP EXCITATION TABLES
Present Next F.F. Present Next F.F.
State State Input State State Input
Q(t) Q(t+1) D Q(t) Q(t+1) J K 0 0 (No change)
0 1 (Reset)
0 0 0 0 0 0 x 1 0 (Set)
0 1 1 0 1 1 x 1 1 (Toggle)
0 1 (Reset)
1 0 0 1 0 x 1 1 1 (Toggle)
1 1 1 1 1 x 0 0 0 (No change)
1 0 (Set)
Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS WITH JK F.F.
Example:
Detect 3 or more consecutive 1’s
Present Next Flip-Flop
Input
State State Inputs
Synthesis using JK F.F.
A B x A B JA KA JB KB
0 0 0 0 0 0 x 0 x JA (A, B, x) = ∑ (3)
0 0 1 0 1 0 x 1 x dJA (A, B, x) = ∑ (4,5,6,7)
0 1 0 0 0 0 x x 1 KA (A, B, x) = ∑ (4, 6)
0 1 1 1 0 1 x x 1 dKA (A, B, x) = ∑ (0,1,2,3)
0 x JB (A, B, x) = ∑ (1, 5)
1 0 0 0 0 x 1
dJB (A, B, x) = ∑ (2,3,6,7)
1 0 1 1 1 x 0 1 x
KB (A, B, x) = ∑ (2, 3, 6)
1 1 0 0 0 x 1 x 1
dKB (A, B, x) = ∑ (0,1,4,5)
1 1 1 1 1 x 0 x 0
 DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS WITH JK F.F.
Example:
Detect 3 or more consecutive 1’s
Synthesis using JK Flip-Flops
B B
JA = B x KA = x’ 0 0 1 0 x x x x
JB = x KB = A’ + x’ A x x x x A 1 0 0 1
x x
J Q A
B B
x K Q y 0 1 x x x x 1 1
A 0 1 x x A x x 0 1
J Q B x x

K Q

CLK
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS WITH T F.F.
Example:
Detect 3 or more consecutive 1’s
Present Next F.F.
Input
State State Input
Synthesis using T Flip-Flops
A B x A B TA TB
0 0 0 0 0 0 0 TA (A, B, x) = ∑ (3, 4, 6)
0 0 1 0 1 0 1 TB (A, B, x) = ∑ (1, 2, 3, 5, 6)
0 1 0 0 0 0 1
0 1 1 1 0 1 1
1 0 0 0 0 1 0
1 0 1 1 1 0 1
1 1 0 0 0 1 1
1 1 1 1 1 0 0
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS WITH T F.F.
Example:
Detect 3 or more consecutive 1’s
Synthesis using T Flip-Flops
TA = A x’ + A’ B x A
T Q
TB = A’ B + B  x x

Q y

B B
T Q B
0 0 1 0 0 1 1 1
Q
A 1 0 0 1 A 0 1 0 1
x x
CLK
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS WITH T F.F.
 Example:
3-bit binary counter
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS WITH T F.F.
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS WITH D F.F.
 Design a one-input, one-output serial 2's
complementer. The circuit accepts a string of bits
from the input and generates the 2's complement
at the output. The circuit can be reset
asynchronously to start and end the operation.
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS WITH D F.F.
DESIGN OF CLOCKED SEQUENTIAL
CIRCUITS WITH D F.F.
SYLLABUS
 Chapter 5 (Excluding Section 5.6)