EtherCAT on Sitara Processors

® ™

Maneesh Soni
Systems Manager
Arm® Microprocessor Group
Texas Instruments
EtherCAT® is among the leading communications
standards based on Ethernet that is used
increasingly for networking and communications
in the industrial or factory environment.
The EtherCAT communication technology was invented by Beckhoff Automation in
Germany and later standardized by the EtherCAT Technology Group (ETG).

Texas Instruments, Inc. (TI) is the first semiconductor company to license EtherCAT
technology. TI has integrated EtherCAT into all of the SitaraTM processors. To enable
EtherCAT, TI has built upon its programmable real-time unit (PRU) technology to
create a unified front-end for industrial communications and bring EtherCAT and other
industrial standards to its growing platform of Arm-based microprocessors.

TI has also brought the software, hardware and Introduction to EtherCAT

tools together to streamline the development of
EtherCAT (Ethernet for Control Automation
EtherCAT-based products with Sitara devices.
Technology) is a real-time industrial Ethernet
Additionally, the industrial grade temperature and
standard for industrial automation applications,
long life-cycle support make Sitara a compelling
such as input/output (I/O) devices, sensors and
choice for EtherCAT and other industrial networking
programmable logic controllers (PLCs). It was
applications.
originally developed by Beckhoff Automation GmbH
The integration of EtherCAT into Sitara processors but is now overseen by the EtherCAT Technology
enables best-in-class ­functionality at lower cost. Group that was set up to help with proliferation
For example, the Sitara AM335x processor-based of the EtherCAT standard. Today, there are over
integration of EtherCAT meets or exceeds all 1,900 member companies from 52 countries that
required features and ­performance benchmarks, create and deploy EtherCAT-compatible products.
including key EtherCAT features such as distributed Ethernet has seen unparalleled adoption in diverse
clocking and end-to-end latency of less than 700 applications, but in industrial environments it is
nanoseconds (ns). In addition to the capabilities of still not efficient enough for small amounts of data
Sitara processors, TI streamlines the development of exchange, it has low determinism for real-time
EtherCAT products by supporting design engineers operation, and it works with only star topology
with a wide range of related software, hardware and in which the network nodes must be connected
development tools. through switches. EtherCAT technology adds
certain features on Ethernet and enforces certain

EtherCAT® on Sitara™ Processors 2 April 2020

configurations to make it a very efficient network This helps eliminate the need for point-to-point
technology for automation while fully conforming exchange of small-sized frames between master
to the Ethernet specifications. The design of and individual slaves and drastically improves the
EtherCAT enables any standard PC to be used efficiency of communication. However, it also means
as an EtherCAT master and communicate with that each slave must have two Ethernet ports and
EtherCAT slaves, which are specialized devices be able to let the frame pass through while reading
compliant with the EtherCAT specification. Together, from or writing to the passing frame and therefore,
the master and slave EtherCAT devices can be used specialized hardware is required in the slave devices.
in all devices in the factory network – automation As a result of these improvements, the usable
controllers, operator interfaces, remote input/output bandwidth in a 100-Mbps network running EtherCAT
units, sensors, actuators, drives and others. is more than 90 percent as compared to less than
5 percent for networks where the master must
Technology separately communicate with each slave node.
EtherCAT improves upon traditional Ethernet by
implementing “on-the-fly” processing where the EtherCAT telegram
nodes in the EtherCAT network read the data from As illustrated in Figure 2, the EtherCAT telegram
a frame as it passes through. All ­EtherCAT frames is encapsulated in an Ethernet frame and includes
originate from the EtherCAT master which sends one or more EtherCAT datagrams destined to the
commands and data to the slaves. Any data to be EtherCAT slaves. Such Ethernet frames use the
sent back to master is written by the slave into the EtherCAT type in the header or they can be
frame as it passes through.

EtherCAT
Master

Drive Sensor Analog I/O Digital I/O

Figure 1. Example EtherCAT network.

Standard Ethernet Frame

48 Bit 48 Bit 16 Bit 16 Bit 48–1498 Byte 32 Bit

DA SA EtherType Header Datagram Datagram ... Datagram Pad CRC

EtherCAT Telegram

160 Bit 64 Bit 16 Bit

Ethernet Header IP UDP Header Datagram Datagram ... Datagram Pad CRC

Working
Length Res Type Header Data Counter

Figure 2. EtherCAT telegram.

EtherCAT® on Sitara™ Processors 3 April 2020

packed with the IP/UDP header. When the IP The FMMU units in each slave enable the EtherCAT
header is used, the EtherCAT protocol can also be protocol to treat various slave devices as part of
used across network routers. a 4-GB large memory space with slave spaces

Each EtherCAT datagram is a command that consists mapped in it. The EtherCAT master assembles a

of a header, data and a working counter. The header complete process image during the initialization

and data are used to specify the operation that the phase and then makes even bit-level accesses

slave must perform, and the working counter is to slave devices via a single EtherCAT command.

updated by the slave to let the master to know that This capability makes it possible to communicate

a slave has processed the command. practically with any number of input/output (I/O)
channels across large and small devices spanning
Protocol
the entire fieldbus network via a standard Ethernet
Each slave processes EtherCAT packets “on-the- controller and standard Ethernet cable.
fly” in that it receives the frame, parses it and takes
Performance
action if the address specified in an EtherCAT
datagram matches its own address, and forwards As a result of hardware-based FMMU and on-the-

the entire datagram from its second port while also fly processing, the EtherCAT network performs at

updating the contents and the CRC of the packet. very high levels of efficiency. It enables cycle times

Through the datagrams, the EtherCAT master of the order of microseconds to communicate from

addresses the entire address space of up to 4 GB controllers to field devices. The communication

in which up to 65,536 EtherCAT slaves, each with efficiency is no longer a bottleneck in industrial

65,536 addresses, can be located. The EtherCAT networks and brings it in line with the computation

datagrams do not have any restriction on the order speeds of contemporary industrial PCs. For

in which the slaves are addressed with respect to instance, the increased performance makes it

the actual position of slave nodes in the network. possible to run the current loop, in addition to the
position loop, for distributed drives over EtherCAT.
There are different types of EtherCAT data
transmissions – cyclic and acyclic. Cyclic data are Topology

the process data that are transferred at periodic The EtherCAT standard supports any topology –
intervals or cycle times. Acyclic data is usually non- line, star or tree – and the bus structures common
time-critical data that can be large in size and usually in fieldbus networks can also be realized with
exchanged in response to a controller command. EtherCAT. Since the EtherCAT interface is present
Some acyclic data, such as diagnostic data, can be on I/O devices, there is no requirement for any
critical and have demanding timing requirements. Ethernet switching hardware. With the 100-m range
EtherCAT handles these different data transmission of copper links and even longer with optical links,
requirements through optimized addressing EtherCAT can span over thousands of devices
schemes – physical addressing, logical addressing, spread across a large geographical area. For short
multiple addressing and broadcast addressing. distances, such as on back-plane, EtherCAT uses

To handle various addressing schemes, each slave E-bus, a differential signaling technology.

has a fieldbus memory management unit (FMMU).

EtherCAT® on Sitara™ Processors 4 April 2020

Distributed clocking
EtherCAT Slave Device
To realize simultaneous actions in industrial nodes
Ethernet Real-Time
installed away from each other, it is necessary Application Application
to synchronize their internal clocks. EtherCAT
TCP UDP Acyclic
accomplishes this by sampling the timestamps for
Data
the ingress and egress of an EtherCAT packet on IP
every slave node as it traverses the network. The
master uses the timestamp information provided by Mailbox Process Data
the slaves to accurately calculate the propagation EtherCAT MAC/DLL
delay for each individual slave. The clocks in each
slave node are adjusted based on this calculation Ethernet PHY Ethernet PHY
and thus, these clocks are synchronized to within
1 μs of each other. An additional advantage Figure 3. Components of an EtherCAT node.
of the accurately synchronized clocks is that
MAC is the industrial application that takes care of
any measurements taken can be linked to the
application-specific behavior and a standard TCP/
synchronized time and remove the uncertainty
IP and UDP/IP stack to support Ethernet-based
associated with the jitter in the communication
device profiles. Depending on the complexity of the
between devices.
device, the EtherCAT node can be implemented in
Device profiles hardware or it could be a combination of hardware
In industrial automation, use of device profiles is a and software running in an embedded CPU.
very common method to describe the functionality Compliance
and parameters of the devices. EtherCAT provides
To ensure broad interoperability among devices
interfaces to existing device profiles so that legacy
designed with EtherCAT interfaces, the EtherCAT
fieldbus devices can be easily upgraded to use
Technology Group (ETG) has several programs
EtherCAT. Some of such interfaces are CAN
for ensuring compliance with the technical
application layer over EtherCAT (CoE) and Servo
specifications. These programs include the
drive profile over EtherCAT (SoE) that enable use of
conformance test tool (CTT), which is a software
CANOpen® and SERCOS® by taking advantage of
program for testing compliance; the plug-fests
the mapping of their data structures to EtherCAT.
where members can meet and test against one
Components of an EtherCAT node another’s devices; and certification labs in Germany
Each EtherCAT node (Figure 3) has three and Japan where formal certification tests are
components – the physical layer, the data link layer performed. To meet minimum conformance
and an ­application layer. requirements a device has to pass the protocol
test using the conformance test tool at the time of
The physical layer is implemented using 100BASE-
its first release to the market. Optionally, vendors
TX copper, 100BASE-FX optical fiber or E-bus
can choose to get their products certified in any of
based on LVDS signaling. The MAC is implemented
the authorized certification labs. The ETG website
either in a specialized ASIC or an FPGA as per
provides detailed information on procedure and
the EtherCAT standard specifications. Beyond the
location of certification labs.

EtherCAT® on Sitara™ Processors 5 April 2020

Typical EtherCAT® node
PHY
Arm/Proprietary EtherCAT
A typical EtherCAT node that is in use today has Processor Peripheral
PHY
architecture similar to one of the illustrations below.
Many of the simple EtherCAT devices such as digital
I/O can be created using single FPGA or ASIC Figure 6. Integrated EtherCAT with processor.
solutions available today. A simplified version of such
In yet another approach, the EtherCAT
architecture is shown in Figure 4. Such architecture
implementation is one of the peripherals in the
is well suited for cost-sensitive simple I/O nodes
device that has an integrated CPU. Many FPGA
that do not require software and all functionality is
devices have the capability to configure a processor
implemented in hardware.
in the FPGA or already have an integrated processor.
Some vendors provide ASICs with both EtherCAT
and a suitable processor on the device. The FPGAs
PHY
Digital EtherCAT are flexible but depending on the CPU selection,
I/O ASIC/FPGA
PHY there is a risk that cost or operating frequency
targets are challenging to meet.

Figure 4. Basic Digital I/O EtherCAT device. EtherCAT solution from TI

TI has integrated EtherCAT functionality into the
In the EtherCAT nodes where additional processing Sitara processors. These devices integrate an Arm
power is needed, an external processor, often core with a cornucopia of other peripherals and
with on-chip Flash memory, is connected to the interfaces that make them attractive devices for
EtherCAT ASIC/FPGA for handling the application- building industrial automation equipment.
level processing. Such devices could be sensor
applications, for instance, where the processor is
Sitara processor
required to operate the sensor, implement the device
Arm MII ×2
driver and run the EtherCAT protocol stack. The cost Cortex-A PHY
CPU
of such architecture is higher than that for simple UART
digital I/O devices and it comes with the flexibility
Shared PRU ×2
that developers can select a processor that suits Memory PHY
PRU-ICSS
their needs and cost targets. with EtherCAT

Figure 7. EtherCAT slave on TI Sitara processors .

PHY
Host EtherCAT
Processor ASIC/FPGA
Interface
PHY
The Sitara processors integrate the programmable
real-time unit industrial communication subsystem
Figure 5. EtherCAT with ASIC and external processor. (PRU-ICSS), which supports very low-level
interaction with the MII interfaces. This capability
enables the PRU-ICSS to implement specialized
communication protocols such as EtherCAT.

EtherCAT® on Sitara™ Processors 6 April 2020

The entire EtherCAT MAC layer can be encapsulated PRUs also emulate EtherCAT register space in the
in the PRU-ICSS through firmware. The PRU-ICSS internal shared memory. With their deterministic
processes EtherCAT telegrams on-the-fly, parses realtime processing capability, the PRUs handle
them, decodes the address and executes EtherCAT datagrams with consistent and predictable
EtherCAT commands. Interrupts are used for any processing latency. The Sitara processor with TI’s
communication required with the Arm core where DP83822 Ethernet PHY device exhibits a low latency
the EtherCAT stack (Layer 7) and the industrial which makes TI’s implementation one of the leading
application is running. The PRU-ICSS also performs EtherCAT slave solutions.
frame forwarding in the reverse direction. Since
the PRU-ICSS can implement all EtherCAT
AM335x
functionality, the Arm core can be utilized for
Industrial Application
complex applications or a lower-speed Arm core Layer 7 - Application

can be deployed for simpler and cost-constrained

EtherCAT Slave Stack
applications, such as distributed I/O. ARM

To complete the EtherCAT solution with the Sitara Protocol Adaptation Layer

processors, Ethernet PHY devices such as TI’s

Customer PRU Subsystem Driver (API)
TLK105L, TLK106L, DP836X0 , DP83822 or
Third Party
DP8384x are required. PRU Firmware
TI PRU
Subsystem
EtherCAT software architecture PRU Subsystem with 2xMII
Layer 2 – Data Link
Three major software components comprise an Layer 1 - Physical
Ethernet PHY
EtherCAT slave implementation on one of TI’s TLK110
Sitara processors. The first is the micro-code that
implements Layer 2 functionality in the PRU; the Figure 8. Software architecture for EtherCAT slave.
second is the EtherCAT slave stack that runs on the
Arm core and the third is an industrial application
that is dependent on the end equipment in which this
solution is used. Additional supporting components,
such as the protocol adaptation layer and device
drivers are provided by TI in the Processor Software
Development Kit (SDK). Irrespective of whether a
TI-tested EtherCAT stack is used or another, the
architecture illustrated in Figure 8 on the following
page is designed to work without changes. This
EtherCAT solution is also independent of the OS
and any adaptations can be made by referring to the
PRU-ICSS firmware API guides.

In EtherCAT Layer 2, the PRU real-time cores share

the tasks of datagram processing, distributed
clocking, address mapping, error detection and
handling and host interface.

EtherCAT® on Sitara™ Processors 7 April 2020

 EtherCAT Slave Stack

PRU Subsystem Driver / Host API

PRU0 EtherCAT PRU1

Registers

RX1 / TX0 Events

RX0 / TX1
Host Interface Shared Distributed Clocking
Sync Managers Memory
Error Handling
FMMU
Digital I/O

RX1 TX0 RX0 TX1

Hardware Interfaces – MII, MDIO, Digital I/O

Figure 9. EtherCAT firmware architecture.

Sitara
DP83822 Arm-based DP83822
processor

700 ns
Figure 10. EtherCAT RX-TX latency.

Key EtherCAT parameters To facilitate the integration of the EtherCAT protocol

stack, TI has also closely collaborated with Beckhoff
The key attributes of an EtherCAT slave
Automation to validate EtherCAT Slave Stack Code on
implementation on the Sitara processors are
the Sitara processors. The Beckhoff code has been
provided in the EtherCAT firmware datasheet.
adapted to work on the Sitara processors and it has
Easy EtherCAT integration been tested to ensure that the integration is seamless
for customers. Customers are expected to become
TI has streamlined the process of integrating
ETG members (required to market EtherCAT products)
EtherCAT with the Sitara processors. All the tools and
and get entitled to obtain a free copy of the Beckhoff
software code required to integrate EtherCAT slaves
stack directly via the ETG website before taking their
are available as part of these processors’ software
product to market. A copy of the EtherCAT stack from
development kits (SDK). On each development
Beckhoff is also included in the Processor SDK for
platform, the SDK includes firmware for the Ether-
evaluation, development and test purposes.
CAT protocol, software drivers, hardware initialization
routines, adaptation layer for the stack API, EtherCAT For a typical use case, the EtherCAT firmware, the
protocol stack and the application itself. The stack, the drivers and the high-level operating system
supporting documentation with the SDK enables one (if needed) or a real-time OS kernel are all reused
to modify and build new features into the application. from the respective software development kit. There
is usually only one file to be modified by the user
when the user application is being developed.
EtherCAT® on Sitara™ Processors 8 April 2020
 Power consumption Customers can also use a slave stack from a different
vendor or develop their own. The customer should use
EtherCAT implementations on Sitara devices benefit
Conformance Test Tool to pass all tests. Optionally,
from a low-power Arm core and system architecture,
they can then get the product certified by EtherCAT
which eliminates the need for a fan or heat sink.
certification labs and may also perform broader
For instance, in most use cases, the peak power of
interoperability tests at the EtherCAT plug fests.
the AM335x processor is under 1 W. For EtherCAT
applications, the power consumption is less than
Development tools for EtherCAT
1 mW per MHz of Arm CPU speed.
implementation
TI provides Evaluation Module (EVM) development
platforms for its Sitara processors with
comprehensive design data to assist customers
with their implementations. All design data for these
EVMs such as schematics and layout is available for
accelerating development of customer designs. For
more information on the tools available for specific
processors, click here.
In addition, TI also collaborates with external vendors
Registers for an additional development platform targeted for
industrial applications.

Summary
TI offers integrated EtherCAT slave and master
capability on Sitara processors targeted for industrial
I/O, sensor, PLC and human machine interface (HMI)
Figure 11. EtherCAT software integration. systems. The integration of EtherCAT with a powerful
yet low-power Arm core results in lower-cost end
products without compromise on the functional or
Integrating EtherCAT on end products operational requirements. TI also offers the transceivers
with built-in isolation for the industrial communication
In order to integrate EtherCAT slave into industrial
interfaces such as EtherCAT, PROFIBUS, CAN,
equipment, customers can use TI’s EtherCAT slave
RS-485 and more. With comprehensive software and
implementation and complete their design process
hardware development tools, worldwide support and
using the evaluation copy of the EtherCAT Slave an active E2E™ developer community, customers can
Stack Code provided in the Processor SDK. The look forward to greatly simplified EtherCAT integration
Slave Stack Code is originally obtained from Beckhoff with the added benefit of significant cost savings – as
and it is available to all ETG members for no charge. much as 30 percent!

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