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SY - Synchronous Counter Using Flip Flops

The document describes the design and implementation of a 3-bit synchronous counter using flip-flops. The circuit uses IC 74LS76A dual J-K flip-flops and IC 7408 dual AND gates. An observation table shows the counter output states at each clock pulse from 0 to 7. The result is that the 3-bit synchronous counter is studied and its truth table is verified.

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Abhishek Parmar
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388 views2 pages

SY - Synchronous Counter Using Flip Flops

The document describes the design and implementation of a 3-bit synchronous counter using flip-flops. The circuit uses IC 74LS76A dual J-K flip-flops and IC 7408 dual AND gates. An observation table shows the counter output states at each clock pulse from 0 to 7. The result is that the 3-bit synchronous counter is studied and its truth table is verified.

Uploaded by

Abhishek Parmar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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S.Y.B.Sc. Practical.

Title: 3-bit Synchronous Counter using Flip-Flops.


Aim: To study 3 bit synchronous counter (Up-Counter) using flip flops.
Components: IC 74LS76A (-Ve edge triggered Dual J-K Flip-Flops), IC 7408 (Dual I/P Quad AND gates).
Equipment’s & Miscellaneous: Regulated DC power supply (0-25V), DMM, Breadboard, Connecting wires
etc.
Circuit Diagram:

Note: 1. Connect series combination of 220 resistor and LED between output and ground to see output.
2. IC 7473 (Dual JK flip-flop with reset; negative-edge trigger) can also use instead of IC 74LS76A.

Observation Table:

Clock Input Output


QC QB QA
Count
(22) (21) (20)
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Dr. Deepak R. Patil, Dept. of Electronics, KKHA Arts, SMGL Commerce & SPHJ Science Senior College, Chandwad. 1.
S.Y.B.Sc. Practical.

Timing Diagram:

Result:
3 bit synchronous counter is studied and verified its truth table.

(Do not write on Practical Sheet)


Precautions:
1. Always connect ground first and then connect Vcc.
2. The kit should be off before changing the connections.
3. Switch off the kit after the experiment.
Procedure:
1. Connect the circuit as shown in the diagram.
2. ̅̅̅̅̅̅ input to the logic 1 i.e. +5V.
Connect 𝑃𝑅𝐸
3. Connect ̅̅̅̅̅̅
𝐶𝐿𝑅 input to the logic 0 i.e. 0V or ground to reset counter.
4. Connect ̅̅̅̅̅̅
𝐶𝐿𝑅 input to the logic 1.
5. Apply the clock pulse to CLK input.
6. Observe the output and verify the observation table.

Dr. Deepak R. Patil, Dept. of Electronics, KKHA Arts, SMGL Commerce & SPHJ Science Senior College, Chandwad. 2.

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