A Fitting Approach to Generate Symbolic Expressions for Linear and

Nonlinear Analog Circuit Performance Characteristics

Walter Daems, Georges Gielen, Willy Sansen
Katholieke Universiteit Leuven, Department of Electrical Engineering, ESAT-MICAS
Kasteelpark Arenberg 10, B-3001 Leuven, Belgium

Abstract TRADITIONAL PROPOSED

Netlist Netlist
This paper presents a novel method to automatically generate symbolic
expressions for both linear and nonlinear circuit characteristics using a
AC expansion Operating Point
template-based fitting of numerical, simulated data. The aim of the method Single Hypercube
is to generate convex, interpretable expressions. The posynomiality of the Operating
Point AC−Netlist
generated expressions enables the use of efficient geometric programming
Numerical
techniques when using these expressions for circuit sizing and optimiza- Error Simulations Complexity
Reference
tion. Attention is paid to estimating the relative ‘goodness-of-fit’ of the Generation
Controlled Controlled

generated expressions. Experimental results illustrate the capabilities of Performance Data

the approach.
Expression Generation Template
(Matrix− or Graph−Based) Estimation
1 Introduction
Network Function Expression Template
The sizing of transistor-level analog integrated circuits is a time
consuming and thus expensive step in the design of analog and Symbolic Simulation−based
mixed-signal circuits. Automation of this process is currently an Postprocessing Template Fitting
important research target in the electronic design automation busi-
ness. Performance Parameter Performance Parameter
The sizing process can be decomposed into two subtasks [1]:
• one “investigates” the circuit’s behavior (knowledge acquisition), Figure 1. Comparison of the traditional symbolic analysis tech-
and nique with the proposed analysis technique
• one adjusts the design parameters according to the obtained knowl-
edge (knowledge use)
Symbolic analysis tries to automate the first subtask. Therefore, it followed by an expression generation step. This step first tries to
is an important research topic in the analog electronic design area. simplify the netlist, then generates a simplified network function
While symbolic analysis research started much earlier, the first re- containing only the dominant terms. Finally symbolic postprocess-
search boom is located in the 1980s [2], [3], [4], [5], [6], [7] mainly ing techniques are used to extract the performance characteristics
due to the wider availability of computing equipment. Soon it be- from the network function.
came obvious that the size of the circuits that could be analyzed However, so far, a number of problems remain unsolved:
was severely restricted by the exponential relationship between the 1. The mainstream symbolic analysis techniques are lim-
the length of the generated expressions and the size of the circuit. ited to linear (or linearized) analog circuits with some
Therefore, the research focus restricted itself more and more to- extensions to weakly nonlinear circuits.
wards enabling the analysis of larger linear circuits by employ-
2. The resulting expressions generated by the current linear
ing all sorts of approximation techniques [8], [9], [10], [11], [12],
and nonlinear techniques are lengthy and their complex-
[13], [14]. The developed approximation techniques are based on
ity is difficult to control, sometimes making their useful-
exploiting the numerical differences in order of magnitude of the
ness for interactive use questionable.
small-signal parameters. In most techniques reported in literature
these differences are obtained by numerically analyzing the circuit 3. The linear expressions that are generated are formulated
in a single design point. Another line of research investigated hi- in terms of (correlated) small-signal parameters (gm , cgs ,
erarchical techniques, i.e. splitting the symbolic analysis task up ro , . . .) instead of in terms of the true uncorrelated design
in several smaller tasks [15], [16], [17]. Linear hierarchical tech- parameters (Vbias , Ibias , w, l, . . .). This makes an ex-
niques typically generate a sequence of expressions relating a net- tra substitution necessary to reveal the true dependence
work function with the small-signal parameters involved and the on the design parameters. In addition, symbolic postpro-
Laplace variable s. Flat techniques generate network functions like cessing steps are needed to extract the performance char-
Pp acteristics (e.g. phase margin, pass-band ripple) from the
a i si generated network functions. E.g., for the gain-bandwidth
H(s) = Ppi=0 j
. (1) (GBW) of a circuit, this leads to the following substitu-
j=0 bj s
More recently, some promising extensions towards pole-zero anal- tion sequence:
ysis [18], [19], [20], [21], [22] and nonlinear analysis [23], [24] gm , cgs , ro , . . . = f (Vbias , Ibias , w, l, R, L, C) (2)
also emerged.
H(s) = g (s, gm, cgs, ro , . . .) (3)
The traditional approach used in symbolic analysis for linear (or
linearized) analog circuits has been depicted on the left-hand side GBW = h (H(s)) (4)
of Fig. 1. The approach starts with an AC expansion of the netlist, = h (g (f (Vbias , Ibias , w, l, R, L, C)))
(5)
 4. Simplified transistor models are needed, in order to limit E S Y X S P

the complexity of the results. (a) (b)

5. The simplification (or simplified generation) of the ex- Figure 2. Electronic system seen (a) as a system that relates an
pressions is only verified in a single design point, and input signal E to an output signal Y and (b) as a system that
therefore uncertainty arises concerning the reliability of relates a set of design parameters X the system’s performance
the generated expressions. P
6. The form of the expressions is not tuned towards the use
in an optimization engine used for automatic sizing. 2.2 Posynomial expressions
This paper describes an approach that attempts to overcome these
problems. The idea behind the proposed method can be seen on Let X = (x1 , x2 , x3 , . . . , xn )T be a vector of real, positive vari-
ables. An expression f is called signomial if it has the form
the right-hand side of Fig. 1. The core of the method consists of !
directly fitting well-chosen expression templates to the numerically Xm Y
n
αij

simulated performance characteristics of the circuit. Its strong points f (X) = ci xj (7)
i=1 j=1
are:
1. Expressions for linear and nonlinear characteristics can with ci ∈ R and αij ∈ R. If we restrict all ci to be positive (ci ∈
be generated. R+ ), then the expression f is called posynomial. Whereas the
former has better fitting properties, the latter allows to formulate
2. The complexity of the resulting expression is limited and
analog circuit sizing as a geometric program [26], [27].
imposed by the complexity of the fitting template. The
A (primal) geometric program is the constrained optimization prob-
designer is informed about the accuracy of the fit.
lem:
3. Performance parameters are expressed directly in terms
of the design parameters, avoiding additional postpro- minimize f0 (X)
cessing and substitutions. E.g., for the Gain-Bandwidth with the constraints: fi (X) ≤ 1, i = 1, . . . , p (8)
(GBW ) of a circuit, this corresponds to the following gj (X) = 1, j = 1, . . . , q
single expression:
xk ≥ 0, k = 1, . . . , n
GBW = u(Vbias , Ibias , w , l , R, L, C ) (6) with all fi (X) posynomial and all gj (X) monomial. By substitut-
ing all variables xi by zk = log (xk ) and taking the logarithm of
4. Well established and accepted device models, such as
the objective function f0 and every constraint fi , gj , it can read-
BSIM-3v3 or MM9 (used and trusted by designers to-
ily be seen that the transformed problem is a convex optimization
day), can be used without impairing the compactness of
problem. Because of this, it has only one global optimum. In ad-
the resulting expression.
dition, this optimum can be found very efficiently using interior
5. The fitting samples are chosen so that the part of the de- point methods [28], even for large problems. Notice that strictly
sign space in which the designer is interested is fully cov- speaking posynomial expressions are not convex: the above men-
ered. Therefore the expressions are suited to be used over tioned transformation makes them convex. However, in view of
a larger part of the design space during circuit design. that property, we conveniently denote them as convex expressions.
6. The technique generates posynomial expressions [25].
This allows to formulate the sizing problem as a geo- 3 Symbolic Performance expression genera-
metric program [26], [27]. tion
The paper is organized as follows. Section 2 will provide some Fig. 3 shows the outline of the proposed method to generate sym-
theoretical background. In section 3, we will discuss our approach bolic performance expressions. First we will determine a set of
in detail. The proposed approach has been implemented in a soft- experiments to perform, in order to obtain an optimal dataset for
ware prototype. The experimental results obtained with this proto- the expression template estimator. In a second step we will per-
type are described in section 4. Finally, section 5 summarizes both form these experiments using a numerical circuit-level simulator
strong and the weak points of the presented approach. Some ideas such as SPICE. The obtained samples are then used to estimate a
for future research also have been indicated. good posynomial template and afterwards reused to generate the
posynomial expression. In a final step, the model quality is veri-
2 Posynomial performance parameter expres- fied. In the next subsections we will treat the different steps of our
sions method in detail.
2.1 Performance parameters 3.1 Posynomial expression generation
Consider a system S transforming an input signal E into an output
Whereas traditional symbolic analysis methods compose their ex-
signal Y (Fig. 2-(a)). The mathematical modeling of this input-
pressions using network analysis intermixed with numerical ap-
output relationship is called behavioral modeling. Fig. 2-(b) de-
proximation techniques, our method is based on straight mathemat-
picts the same system seen from a designer’s point of view: a num-
ical fitting of a pre-estimated expression template using simulated
ber of design parameters (X) cause the system to exhibit a partic-
data. Standard mathematical fitting techniques like interpolation
ular performance (P ). The modeling of this relationship is called
or least-squares regression are well kown, but are rarely used in
performance modeling. Because our goal is to compose symbol-
symbolic analysis methods.
ical expressions that can be used for designing a circuit, we will
However, the advantages of using simulation-based fitting tech-
concentrate on the latter.
niques over traditional symbolic analysis techniques are multiple:
 Design of Experiments 1. start with an empty template
2. add ci,0,j,0
Simulation−based 3. if di > 0, then add ci,1,j,0 x1i
Performance Calculation else if di < 0, then add ci,−1,j,0 x−1 i
4. if di,i > 0, then add ci,1,i,1 x2i
Expression Template Estimation else if di < 0, then add ci,−1,j,0 x−1 i
5. if di,j |i6=j > 0, then add ci,1,j,1 xi xj
Posynomial else if di,j |i6=j < 0, then,
Expression Generation if (a0 ), then
if (∆xi /xi > ∆xj /xj ), then
Posynomial Expression add ci,−1,j,1 x−1
i xj and ci,0,j,−1 xj
−1

else
Expression Quality Verification
add ci,1,j,−1 x1i x−1
j and ci,−1,j,0 xi
−1

else
Figure 3. Outline of the expression-generation method if (∆xi /xi < ∆xj /xj ), then
add ci,−1,j,1 x−1
i xj and ci,0,j,−1 xj
−1

else
• any performance parameter (linear as well as nonlinear) add ci,1,j,−1 x1i x−1 −1
j and ci,−1,j,0 xi
can be fitted, 6. if (a1 ), then add ci,−1,j,0 , i = 1 . . . n
• full accuracy SPICE transistor models can be used, 7. if (a2 ), then add ci,1,j,0 , i = 1 . . . n
8. if (a3 ), then add ci,2,j,0 , i = 1 . . . n
• performance parameters (such as GBW or slew rate) are
directly fitted as a function of the design parameters, and Figure 4. The template estimation algorithm
• the complexity of the resulting expression is directly im-
posed by the fitting template that is chosen.
Of course, the selection of the expression template is crucial, in A set of template estimators is proposed based on a single algo-
order to obtain a good fit. A trade-off between the number of fit rithm that contains 4 binary choices. This leads to 16 alternatives.
parameters allowed and the resulting fit accuracy has to be made. For convenience, we represent the 4 binary choices by a 4-bit word
The designer’s experience and insight in the system may clearly (a3 a2 a1 a0 ). The algorithm can be found in Fig. 4.
help in selecting (or refining) a model template. However, to assist This algorithm keeps the terms of (11) that have positive coeffi-
the designer in this process, we propose the use of an expression cients and replaces the negative terms by appropriate approxima-
template estimator that allows to compose a template without rely- tions (see [29]). The number of terms of the estimated templates is
ing on human input. at most 1/2n2 + 5/2n + 1. In order to keep the template as sparse
Consider the generic n-dimensional posynomial template as possible, the estimation correlation between the coefficients of
n 
! (11) should be as close as possible to zero. Techniques from design
X X Xn X  of experiments can assist us to achieve this goal.
f (X) = k l
ci,k,j,l xi xj (9)
k=−1,0,1 l=−1,0,1 i=1 j=1
3.3 Design of experiments
with n the number of design parameters and all ci,k,j,l positive. The theory of Design Of Experiments (DOE) provides a mathemat-
The template of (9) allows to obtain good fitting results. However, ical basis to select an optimal sample set that allows an uncorre-
the number of independent parameters to fit equals lated estimation of the fit parameters, given a fit template [30]. The
3 2 5 number of sampling schemes described in literature is vast: start-
#ci,j,indep = n + n+1 (10)
2 2 ing from full- and fractional factorial design, over Placket-Burman
This number of fit parameters is too large for realistic sizing prob- and Taguchi schemes, to Latin hypercube and even random design.
lems (e.g., n > 10 leads to #ci,j,indep > 176). The expression A sampling scheme that allows an uncorrelated estimation of the
template estimator described in the next subsection allows to re- coefficients of (11) are level-3 orthogonal arrays of strength 3 [31].
duce this number. This scheme places the sampling points on the edges of a fitting hy-
percube of size ∆X around a center point X ∗ . Usually the center
3.2 Expression template estimation point is provided as well.
This sampling scheme has been chosen, in order to keep the coef-
To estimate which coefficients ci,k,j,l need to be retained in the
ficient leakage in (11) as small as possible.
posynomial fitting, we first fit the signomial function
The same samples are reused to fit the estimated posynomial tem-
X
n X
n

Xn X
n
plate. This avoids additional (costly) numerical simulations.
g(X) = d0 + (di xi ) + di,i x2i + (di,j xi xj )
i=1 i=1 i=1 j=i+1
(11)
3.4 Fit quality verification
to the experimental data. The number of independent parameters In order to assess the quality of fit, we use the quality-of-fit param-
to fit amounts to eter q, defined in [29]. The starting point for this parameter is the
1 3 root mean square of the deviation in the a sampling points. This pa-
#di,j,indep = n2 + n + 1, (12) rameter then is normalized by division with the performance range
2 2
of the sampling points:
which is about a third lower than (10). Because the fitting process qP
itself is O(d3i,j,indep ), this is a considerable gain.
j=1 (f (Xj ) − pj )
a
Then, a template estimation algorithm is applied to relate the ob- q= 
 . (13)
tained coefficients di,j to the ci,k,j,l that need to be present in (9). a c + maxaj=1 pj − minaj=1 pj
 VDD
In (13) c is a constant to avoid error overestimation when the per-
formance range approaches zero. If we reuse the sampling points M5a M6 M5b

used during the fitting process, then this figure is: n4a n5 n4b
1. computationally cheap (no extra simulations are needed), and
2. easy to assess: a quality larger than 1 suggests a bad fit. M4a M7 M4b

We will further denote the fit-quality parameter that reuses only the
iB3 n1
set of sampling points by q0 . In order to have a more realistic view iB2 nin_p M1a M1b nin_m nout
on the fit quality, additional samples located in the interior of the iB1
fitting hypercube may be selected. We will label this fit-quality pa-
rameter q1 . A drawback of the latter is the need for extra circuit M2a M2b

simulations. VSS VSS

n2a n2b

4 Experimental results M3a

n3
M3b

N VSS
4.1 S-PR I SM
N
The flow of Fig. 3 has been implemented in S-PR I SM, our Sym- Figure 6. Schematic of a high-speed CMOS OTA
bolic Posynomial Response Surface Modeling prototype. Fig. 5
N
shows the overall concept of S-PR I SM. Sixteen alternative tem-
the posynomial formulation). Note that transistor currents and volt-
ages are chosen as variables, rather than transistor widths, since we
Analysis Analysis Analysis
Server Server Server
use an operating-point driven formulation for analog circuit sizing
[32].
Analysis Analysis Analysis Analysis Analysis
Client Client Client Client Client

i xi nominal ∆xi,1 ∆xi,2 ∆xi,3 xi,ref

S
Design of Experiments Posynomial Modeling 1 vGS ,M1 -0.9V ± 0.2V ± 0.1V ±40mV -4.0V
Engine PRiSM Engine
2 vGS ,M2 0.8V ± 0.2V ± 0.1V ±40mV 4.0V
Quality Control
3 vDS ,M2 0.5V ± 0.2V ± 0.1V ±40mV 4.0V
Template Estimation
Engine Engine 4 vGS ,M3 2.5V ± 0.2V ± 0.1V ±40mV 4.0V
5 vGS ,M4 -1.2V ± 0.2V ± 0.1V ±40mV -4.0V
N 6 vGS ,M5 -1.2V ± 0.2V ± 0.1V ±40mV -4.0V
Figure 5. Overall concept of S-PR I SM 7 vDS ,M5 -1.4V ± 0.2V ± 0.1V ±40mV -4.0V
8 vDS ,M6 -0.85V ± 0.2V ± 0.1V ±40mV -4.0V
9 iD ,M1 1mA ± 0.5mA ± 0.25mA ±10mA 10mA
plate estimation schemes have been incorporated in the template 10 iD ,M2 0.8mA ± 0.5mA ± 0.25mA ±10mA 10mA
11 iB1 11uA ± 5uA ± 2.5uA ±10mA 100uA
estimation engine allowing to compare and to select the most ef- 12 iB2 13uA ± 5uA ± 2.5uA ± 1uA 100uA
fective ones. The core engines have been coded using C++, while 13 iB3 12uA ± 5uA ± 2.5uA ± 1uA 100uA
the analysis clients and servers have been coded in Perl. The total
N Table I. Design variables chosen as model inputs
amounts to about 42 000 lines of code. S-PR I SM’s TCP-based
client-server simulation system schedules simulation and extrac-
tion jobs on remote workstations over the intra-net or the Internet. For each of the characteristics to model, we will derive posyno-
SPICE simulations are performed using a standard simulation tool mial expressions using three different sampling hybercube widths
chosen according to the availability or preference. At this moment (∆X1 , ∆X2 , ∆X3 ). Their respective values can also be found in
interfaces to E LDO and Berkeley SPICE 3f4 are provided.1 Table I.
N
S-PR I SM was run on an Intel Celeron 466MHz running GNU/Linux.
4.2 Experiments The analysis servers ran on 16 UNIX workstations, ranging from a
SUN Ultra Sparc I (with a SPECfp95 of 9) to an HP B-1000 (with a
As test case we use the circuit of Fig. 6, a high-speed CMOS OTA SPECfp95 of 42) using their native OS. The simulations needed to
in a 0.7µm CMOS technology. The supply voltage is 5V. The nom- obtain a full orthogonal hypercube of sampling points took approx-
inal threshold voltages of this technology are 0.76V for NMOS- imately 3 minutes. Using these data the whole set of performance
devices and −0.75V for PMOS-devices. The circuit has to drive a characteristics (-Av,LF , -fu , -PM , -SR p , SR n ) can be fitted.
load capacitance of 10pF.
Comparison of the template estimators
Our goal is to derive expressions for the low frequency gain (Av,LF ),
We gathered the fit-quality parameters that can be obtained by each
the unity frequency (fu ), the phase margin (PM ), and the positive
of the template estimation variants in Table II. Hereto, we divided
and negative slew rate (SR p , SR n ). In order to comply with the
the quality range (difference between best and worst fit quality) for
geometric programming formulation (which in its direct form only
each parameter into five subranges (each representing 20% of the
supports minimization), we will fit the inverse of the characteristics
range). The subranges have been labeled from ‘best’ (++), over
that need to be maximized (i.e. −Av,LF , −fu , −PM and −SR p ).
good (+), average (o), and poor (-), to bad (--). Table II clearly
Thirteen independent design variables can be chosen for the high-
suggests the parallel use of multiple template estimators in order to
speed OTA of Fig. 6. In Table I an overview of the chosen vari-
obtain an acceptable fit in all cases. The template variants that we
ables and their nominal values around wich expressions are to be
have chosen are 0xE and 0xF (grey rows in table II).
generated is given. The variables are normalized by division with a
Fig. 7 shows the trade-off between the generation time (i.e. a di-
reference value, indicated in the rightmost column of the overview.
rect function of the template size) and the obtained accuracy (fit-
As a consequence all scaled variables are positive (as required for
quality) for the posymial fitting of an expression for SR n . In order
1
For this purpose we integrated the BSIM-3v3 model into Berkeley not to overload the picture, we omitted the fits based on template
SPICE 3f4. estimators 0x2 to 0xD. It can readily be seen that the speed advan-
 nr. Av ,LF fu PM SRp SR n
I II III I II III I II III I II III I II III Expression for −AV,LF
0x0 ++ o ++ ++ ++ + - o ++ -- + ++ -- -- ++
1e2
0x1 -- -- -- -- - o -- ++ -- ++ -- ++ -- ++ ++
0x2 ++ o ++ ++ ++ + - o ++ -- + ++ -- -- ++

Coefficient Values
0.75e2
0x3 -- -- -- -- o -- -- ++ -- -- ++ -- ++ ++ --
0x4 o + ++ ++ + ++ - -- ++ + + ++ ++ - ++ 0.5e2
0x5 -- o ++ -- - ++ -- o -- ++ -- ++ -- ++ ++
0x6 o + ++ ++ + ++ - -- ++ + + ++ ++ - ++ 0.25e2
0x7 -- o ++ ++ - -- -- o -- ++ ++ ++ ++ ++ --
0x8 ++ ++ ++ ++ ++ -- ++ - ++ -- ++ ++ -- -- ++ 0
0x9 -- -- ++ -- -- -- o + -- ++ ++ ++ ++ ++ -- Dynamic 1
Range 0
0xA ++ ++ ++ ++ ++ -- ++ - ++ -- ++ ++ -- -- ++
0xB -- -- ++ -- ++ -- o + -- ++ -- ++ ++ ++ -- vsg1
vgs2
0xC ++ ++ ++ ++ ++ + ++ -- ++ -- + -- -- - ++

Scaled Input Parameters

vds2
0xD -- o ++ ++ -- ++ -- o -- ++ -- ++ -- ++ -- vsg3
vsg4
0xE ++ ++ ++ ++ + + ++ -- ++ -- + -- -- - ++ vsg5
0xF -- o ++ -- o -- -- o -- ++ -- ++ ++ ++ -- vsd5
vsd6
id1

Table II. Template estimator performances (++ = best, + = good, id2

ib1

o = average, - = poor, -- = bad) for ∆X1 (I), ∆X2 (II), ∆X3 (III) ib2
ib3

Expression for SRn

tage of using a template estimator over using the full expression is 2e9

Coefficient Values
paid by a small loss of accuracy. Also notice the low fitting time of 1.5e9

the second-order polynomial template, which has a template com- 1e9

plexity that is almost equal to the estimated templates. However, it 0.5e9

is outperformed by the estimated templates when the fit quality is 0

taken into concern. Dynamic 1

Range 0

vsg1

Posynomial Expression Generation for SRn with ∆ X1 vgs2

Scaled Input Parameters

vds2
0.25 vsg3
full template of equation (8) vsg4
estimated template variant 0x0 vsg5
vsd5
0.20 estimated template variant 0x1 vsd6
estimated template variant 0xE id1
id2
estimated template variant 0xF
q0 [−]

0.15 ib1
quadratic polynomial template ib2
ib3

0.10

Expression for −SRp

0.05

8e8
0
Coefficient Values

0 50 100 150 20
6e8
Fitting Time [sec]
4e8

Figure 7. Trade-off between fitting time and obtained accuracy 2e8

when generating a posynomial expression for SR n using ∆X1 0

Dynamic 1
Range 0

vsg1
Resulting models vgs2
Scaled Input Parameters

vds2

The obtained number of terms in the resulting expressions, the fit- vsg3
vsg4
vsg5
ting time and the fit-quality parameters can be found in Table III. vsd5
vsd6
id1
We can clearly observe that the fit quality improves with smaller id2

hypercube widths (∆X1 > ∆X2 > ∆X3 ) and that the expres-
ib1
ib2
ib3

sions based on the estimated templates are a good trade-off be- Input parameter legend Coefficient legend

tween generation time and accuracy. Also take note of the small 1st power −1st power 2nd power positive coefficient negative coefficient

number of terms needed for the expressions. The fact that the fit
Figure 8. Graphical representation of the expression for Av,LF ,
quality of the expression based on the full template is sometimes SR p and SR n fitted for ∆X3
outperformed by the expressions based on the estimated template
indicates that the fit routine itself can be improved.

∆X1 ∆X2 ∆X3

of the expressions for −Av,LF , −SRp and SRn in Fig. 8. Every
param terms time q0 q1 terms time q0 q1 terms time q0 q1 column in the figure corresponds to one term. The bottom part
[#] [sec] [-] [-] [#] [sec] [-] [-] [#] [sec] [-] [-]
Full template of eqn. (9)
of the figure identifies all xi , xj input parameter combinations in-
-Av ,LF 21 227.4 0.026 0.039 24 257.3 0.021 0.030 10 226.9 0.017 0.017 volved, using a color code. The color code indicating the value
-fu 25 210,7 0.115 0.177 23 250.4 0.096 0.126 14 242.9 0.054 0.062 of the exponents can be found in the input parameter legend. The
-PM 21 194.1 0.081 0.080 19 244.1 0.039 0.049 18 261.6 0.024 0.023
-SRp 19 202.4 0.125 0.164 25 202.9 0.095 0.127 14 193.7 0.059 0.076 colored bars appearing in the top part each represent the value of a
SRn 24 183.4 0.116 0.146 22 214.0 0.115 0.149 9 202.9 0.076 0.078 coefficient. Coefficient values that normally would not be visible
Estimated template (0xE & 0xF)
-Av ,LF 19 68.3 0.024 0.035 18 77.0 0.020 0.028 15 87.0 0.011 0.013 on the scale are indicated by bars below the axis. The relative dy-
-fu 18 68.5 0.127 0.176 11 70.0 0.118 0.152 13 79.4 0.091 0.087 namic range bargraphs for each term in the middle allow to easily
-PM 17 66.7 0.088 0.087 21 78.4 0.046 0.058 23 94.0 0.019 0.019
-SRp 19 70.6 0.123 0.137 14 73.0 0.144 0.186 15 81.0 0.050 0.058 locate the dominant design parameters occurring in a performance
-SR n 28 68.3 0.121 0.148 13 69.3 0.116 0.131 15 78.6 0.068 0.084 variable.
Table III. Complexity, generation time and fit-quality parameters The dynamic ranges of the terms of −Av,LF show two dominant
for the generated expressions terms: one linear term in −vGS ,M1 and one term inversely pro-
portional to vDS ,M2 . Indeed, if vGS ,M1 drops, than gmM1 in-
N creases (for constant ID1 , and hence Av,LF increases. Likewise if
Consider the graphical representations (generated by S-PR I SM)
vDS ,M2 increases, then both gmM2 and roM 2 increase, thus Av,LF A. Rodrı́guez-Vázquez, “Efficient symbolic computation of approxi-
increases. mated small-signal characteristics,” IEEE Journal of Solid-State Cir-
Examining its dominant terms, the interpretation of the expression cuits, vol. 30, pp. 327–330, Mar. 1995.
[11] C.-J. R. Shi and X.-D. Tan, “Symbolic analysis of large analog cir-
for −SR n is also straightforward. The term inversely proportional cuits with determinant decision diagrams,” in Proc. IEEE/ACM IC-
to iD,M1 reflects the fact that in negative slewing conditions all CAD, Nov. 1997.
input stage bias current is mirrored via M3a to M3b, forming the [12] O. Guerra, J. D. Rodrı́guez-Garcı́a, E. Roca, F. V. Fernández-
driving force to discharge the load capacitor. The interaction term Fernandéz, and A. Rodrı́guez-Vázquez, “A simplification before and
containing 1/vGS ,M2 indicates the beneficial effect of M2b’s low during generation methodology for symbolic large-circuit analysis,”
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Since iD,M1 > iD,M2 , we expect the expression for SRp to show pp. 958–963, June 1999.
no dependence on iD,M1 (as M2 goes in cut-off). The correspond- [14] W. Verhaegen and G. Gielen, “Efficient DDD–based symbolic analy-
ing terms are indeed negligible, However the large dependence on sis of large linear analog circuits,” in Proc. DAC, pp. 139–144, June
iD,M2 that one expects, cannot be found in the expression. Like- 2001.
wise, the dependence on vGS ,M1 and vGS ,M2 is totally unexpected. [15] M. M. Hassoun and K. S. McCarville, “Symbolic analysis of large-
scale networks using a hierarchical signal flowgraph approach,” Jour-
We did not (yet) find an explanation for this unobvious result. nal of Analog Integrated Circuits and Signal Processing, no. 3,
Finally, it must also be mentioned that for larger fitting hypercubes pp. 31–42, 1993.
— though their numerical accuracy is reasonable — it is much [16] M. Pierzchała and B. Rodanski, “Symbolic analysis of large-scale
harder to recognize the expected effects in the expressions. networks by circuit reduction to a two-port,” in Proc. SMACD Work-
shop, Oct. 1996.
5 Conclusions [17] O. Guerra, J. D. Rodrı́guez-Garcı́a, E. Roca, F. V. Fernández-
Fernandéz, and A. Rodrı́guez-Vázquez, “True hierarchical symbolic
We presented a fitting-based posynomial expression generation tech- analysis of large-scale analog integrated circuits.,” in Proc. SMACD
nique based on numerical simulations. The first experimental re- Workshop, pp. 164–168, Oct. 1998.
sults clearly show that the presented technique is able to generate [18] G. Dröge and E.-H. Horneber, “Symbolic calculation of poles and
zeros,” in Proc. SMACD Workshop, 1996.
short and reasonably accurate convex expressions for both linear
[19] G. Nebel, U. Kleine, and H. Pfleiderer, “Symbolic pole/zero calcula-
and nonlinear performance characteristics. However, additional re- tion using SANTAFE,” IEEE Journal of Solid-State Circuits, vol. 30,
search is needed to further mature the technique. More general and pp. 752–761, July 1995.
more powerful template estimators are needed to accomodate for [20] J. J. Hsu and C. Sechen, “Accurate extraction of simplified symbolic
larger fitting hypercubes and the nature of the paradoxical expres- pole/zero expressions for large analog ICs,” in Proc. IEEE ISCAS,
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[21] F. Constantinescu and M. Nitescu, “A new approach to symbolic pole
Besides presenting a new approach to symbolic analysis, we also
computation,” in Proc. ECCTD, pp. 665–658, 1995.
hope that this paper may be an impulse towards a shift in focus of [22] J. D. Rodrı́guez-Garcı́a, O. Guerra, F. V. Fernández-Fernandéz, and
the research on symbolic analysis. Generating short and usable ex- A. Rodrı́guez-Vázquez, “A symbolic pole/zero extraction methodoly
pressions should – in our view – be of more concern than extending based on analysis of circuit time-constants,” in Proc. DCIS, pp. 327–
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[23] P. Wambacq, G. Gielen, P. R. Kinget, and W. Sansen, “High-
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