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School of Electronics Engineering (Sense) : Class Number: VL2021220101854 Semester

The document discusses computer organization and architecture topics such as cache memory performance, memory address formats, average memory access time calculations, direct memory access techniques, and interrupt-driven input/output. It contains questions about comparing CPU execution times with and without cache misses, determining memory address formats, calculating average memory access times, detailing DMA module operations, and illustrating interrupt-driven and program-controlled I/O.

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62 views4 pages

School of Electronics Engineering (Sense) : Class Number: VL2021220101854 Semester

The document discusses computer organization and architecture topics such as cache memory performance, memory address formats, average memory access time calculations, direct memory access techniques, and interrupt-driven input/output. It contains questions about comparing CPU execution times with and without cache misses, determining memory address formats, calculating average memory access times, detailing DMA module operations, and illustrating interrupt-driven and program-controlled I/O.

Uploaded by

PAVAN
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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SCHOOL OF ELECTRONICS ENGINEERING (SENSE)

Discipline : B.Tech. ECE Course code : ECE3004

Subject : Computer Organization and Architecture

Max. Marks : 30 Time : 50 min

Class number: VL2021220101854 Semester: FALL 2021-22

CAT-2

Answer ALL Questions

S.No Question Marks CO BL


1. (a) Consider a CPU with clock cycle of 10ns that executes the program A in 150 6 2 L3
clock cycles and access the memory for 200 times during the execution. The
CPU uses the cache with miss rate of 6% and Miss Penalty time of 40 ns.
Compare the CPU execution time with and without Cache miss.

CPU execution time without cache miss = 150 * 10 ns = 1500 ns


CPU execution time with cache miss
No of cache miss (6% of 200 memory access) = 12
Total miss penalty time = 12 * 40 ns = 480 ns
CPU execution time with cache miss = execution time + penalty
= 1500ns + 480 ns = 1980ns
1.(b) Consider a CPU with clock cycle of 12ns that executes the program A in 150 6 2 L3
clock cycles and access the memory for 150 times during the execution. The
CPU uses the cache with miss rate of 8% and Miss Penalty time of 30 ns.
Compare the CPU execution time with and without Cache miss.

CPU execution time without cache miss = 150 * 12 ns = 1800 ns


CPU execution time with cache miss
No of cache miss (8% of 150 memory access) = 12
Total miss penalty time = 12 * 30 ns = 360 ns
CPU execution time with cache miss = execution time + penalty
= 1800ns + 360 ns = 2160ns
1.(c) Consider a CPU with clock cycle of 20ns that executes the program A in 110 6 2 L3
clock cycles and access the memory for 75 times during the execution. The
CPU uses the cache with miss rate of 6% and Miss Penalty time of 65 ns.
Compare the CPU execution time with and without Cache miss.

CPU execution time without cache miss = 110 * 20 ns = 2200 ns


CPU execution time with cache miss
No of cache miss (6% of 75 memory access) = 4.5
Total miss penalty time = 4.5 * 65 ns = 292.5 ns
CPU execution time with cache miss = execution time + penalty
= 2200ns + 292.5 ns = 2492.5 ns
2.(a) A digital computer has a main memory of 512 MB and cache memory of 2 10 3 L4
MB with block size of 128 bytes. Determine the address formats in case of

Total number of address bits = 29


i) Direct Mapping
Word = 7
Line = 14
Tag = 8
ii) Associative Mapping
Word = 7
Tag = 22
iii) Set Associative Mapping( four block make a set)
Word = 7
Set = 16
Tag = 6
2.(b) A digital computer has a main memory of 128 MB and cache memory of 1 10 3 L4
MB with block size of 4 kilo bytes. Determine the address formats in case
of
Total number of address bits = 27
i) Direct Mapping
Word = 12
Line = 8
Tag = 7
ii) Associative Mapping
Word = 12
Tag = 15
iii) Set Associative Mapping( eight block make a set)
Word = 12
Set = 5
Tag = 10

2.(c) A digital computer has a main memory of 16 MB and cache memory of 10 3 L4


512 KB with block size of 64 bytes. Determine the address formats in case
of
Total number of address bits = 24
i) Direct Mapping
Word = 6
Line = 13
Tag = 5
ii) Associative Mapping
Word = 6
Tag = 18
iii) Set Associative Mapping( eight block make a set)
Word = 6
Set = 10
Tag = 8
3.(a) Consider a computer with 4 levels of memory. Calculate the average 4 2 L4
memory access time, given the access time and miss rate given below

Memory Access Time(ns) Miss Rate

Cache 1 5 7%

Cache 2 7 10%

RAM 20 15%

HDD 100 -

AMAT = 5 + 0.07 (7 + .1 (20+.15(100))) = 5.735

3.(b) Consider a computer with 4 levels of memory. Calculate the average 5 2 L4


memory access time, given the access time and miss rate given below

Memory Access Time(ns) Miss Rate

Cache 1 5 3%

Cache 2 10 8%
RAM 40 30%

HDD 95 -

AMAT = 5 + 0.03 (10 + .08 (40+.3(95))) = 5.4644

3.(c) Consider a computer with 4 levels of memory. Calculate the average 5 2 L4


memory access time, given the access time and miss rate given below

Memory Access Time(ns) Miss Rate

Cache 1 8 3%

Cache 2 17 14%

RAM 35 26%

HDD 110 -

AMAT = 8 + 0.03 (17 + .14 (35+.26(110))) = 8.77712

4.(a) Detail the operation of DMA module. Analyze the single –bus, detached 10 1 L3
DMA, Single-bus integrated DMA-I/O, I/O Bus configurations with neat
diagrams.

4.(b) Illustrate the operation of Interrupt driven I/O and simple Interrupt 10 1 L3
processing with flowchart. Compare their performance with suitable
examples in I/O operations.

4.(c) Illustrate the operation of program controlled I/O and Interrupt 10 1 L3


driven I/O. Compare their performance with suitable examples in
I/O operation

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