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Logic Lec - 2 - 2022

The document discusses designing various digital logic circuits such as multiplexers, demultiplexers, decoders, encoders, and comparators using VHDL code. It provides examples of designing 1x4 multiplexers and demultiplexers, 4x16 decoders, 16x4 encoders, and 8-bit comparators. It also tasks the reader with designing specific logic circuits like a 3x8 decoder with enable pin and 16-bit comparator with enable pin and five outputs.

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Ahmed eltookhy
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© © All Rights Reserved
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65 views20 pages

Logic Lec - 2 - 2022

The document discusses designing various digital logic circuits such as multiplexers, demultiplexers, decoders, encoders, and comparators using VHDL code. It provides examples of designing 1x4 multiplexers and demultiplexers, 4x16 decoders, 16x4 encoders, and 8-bit comparators. It also tasks the reader with designing specific logic circuits like a 3x8 decoder with enable pin and 16-bit comparator with enable pin and five outputs.

Uploaded by

Ahmed eltookhy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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My website

https://AssemSite8.wix.com/site8

1
Microprocessor 2021-22
Design the following logic Multiplexer
based on VHDL code
inp0

inp1
Multiplexer Bitout
inp2

inp3
2
Sel

The
Entity
ports
Designing Multiplexer based on flowchart method
using simulator “FPGAdv 8.1”
Design the following logic De-multiplexer
(DeMUX) based on VHDL code
8 output1
8 output2
8
input DeMUX 8
output3
8
output4

2
Selector

The
Entity
ports
Designing DeMux 1X4
using Select-when
The standard Logic Decoder

From logical model point-of -view


It is combinational logic circuit has N inputs and up−to 𝟐𝑵
outputs

𝑵 Decoder 𝟐𝑵
Inputs
Outputs

It converts the formats of input data according to its


truth table.
Design the following standard logic Decoder
based on VHDL code

Four_Bits_in 4 16 Decoder_out
Decoder
Inputs Outputs Outputs
[4 bits] [16 bits] [hex]

0000 …00000001 0001


0001 …00000010 0002
0010 …00000100 0004
0011 …00001000 0008
0100 …00010000 0010
0101 …00100000 0020
---- ---- ----
---- ---- ----
1111 10000000… 8000
Designing Decoder
4X16 using Select-when

Note

in out
0000 ..0001
0001 ..0010
0010 ..0100
0011 ..1000
-- --
-- --
Your Task
Design Decoder 3X8 with enable pin
using “Case-when” based on VHDL
codes.
The standard Logic Encoder
From logical model point-of -view
It is combinational logic circuit has up−to 𝟐𝑵 inputs and N
outputs

Inputs Outputs
𝟐𝑵 Encoder 𝑵

It converts the input data according to its truth table


Design the following standard logic Encoder
based on VHDL code

16 4
Encoder_in Encoder Encoder_out

Input (hex) Out(binary)


0001 0000
0002 0001
Enable 0004 0010
0008 0011
0010 0100
0020 0101
0040 0110
------ --
-------- --
Designing Encoder 16X4
using Select-when

Note
Your Task
Design Encoder 8X3 using “Case-
when” with enable pin based on the
VHDL.
Design the following 8-bit logic Comparator based
on VHDL code

8 Less
Bus_1
Equal
Comparator
8 Grater
Bus_2
Designing comparator
using if-statement
Why we can’t use “Case-when” in
designing the logic Comparator?
Why we can’t use “Case-when” in designing
the comparator?

Because the “Case-when”


depending on a single variable while
any comparator needs 2 variables.
Your Task

Design 16-bit logic Comparator with


enable pin has five outputs (=, <, >,
<= and >=).
Designing comparator based on flowchart method
using simulator “FPGAdv 8.1”

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