PIB 18 CPLDs vs.

FPGAs: Comparing High-Capacity Programmable Logic

CPLDs vs. FPGAs

Comparing High-Capacity
Programmable Logic

February 1995, ver. 1 Product Information Bulletin 18

Introduction The high-capacity programmable logic device (HCPLD) market has

expanded dramatically in recent years with the introduction of new devices
and architectures. While these new devices offer greater design flexibility,
design engineers must sift through all available devices to determine the
best device for an application. Choosing the right device can lead to market
success, while choosing the wrong device can result in major project
setbacks.

To make an informed decision, designers need to understand the strengths

and limitations of different HCPLDs, specifically complex programmable
logic devices (CPLDs) and field-programmable gate arrays (FPGAs). This
product information bulletin provides guidelines on choosing the correct
devices for design applications and discusses the following topics.

❏ PLD market overview

❏ CPLD vs. FPGA architecture
❏ CPLD vs. FPGA interconnect structures
❏ CPLD vs. FPGA process alternatives
❏ CPLD vs. FPGA development software

PLD Market The PLD market consists of low- and high-capacity devices. Low-capacity
devices, called simple PLDs, typically contain fewer than 600 usable gates
Overview and include products such as PALs, GALs, and 22V10s. Simple PLDs are
manufactured using CMOS technology offering EPROM, EEPROM, and
FLASH memory elements.

HCPLDs typically contain more than 600 usable gates, and include both
CPLDs and FPGAs. HCPLDs are manufactured using CMOS technology
with EPROM, EEPROM, FLASH, SRAM, and antifuse options. HCPLDs
can be differentiated by their interconnect structure: CPLDs use continuous
interconnect structures, while FPGAs use segmented interconnect
structures. See Figure 1.

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A-PIB-018-01
 CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic PIB 18

Figure 1. Programmable Logic Market

Programmable
Logic
≤ 600 Gates > 600 Gates

Simple High-Capacity
PLDs PLDs
Segmented Continuous
Interconnect Interconnect

FPGAs CPLDs

EPROM EEPROM FLASH SRAM Antifuse EPROM EEPROM FLASH SRAM

Table 1 describes CPLD and FPGA features.

Table 1. CPLD vs. FPGA Features

Feature FPGAs CPLDs

Leading vendor Xilinx Altera
Density Medium to high Low to high
Interconnect structure Segmented Continuous
Timing Variable/unpredictable Fixed/predictable
CMOS options SRAM, antifuse EPROM, EEPROM, FLASH,
SRAM
Device performance Moderate High
Device utilization Moderate High
Hand-routing required Yes No
Reprogrammability Yes (SRAM only) Yes
In-circuit reconfigurability Yes (SRAM only) Yes (SRAM only)
In-system programmability No Yes (FLASH, EEPROM only)
Compilation times Slow Fast
Logic synthesis Yes (third-party only) Yes

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PIB 18 CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic

CPLDs use several different varieties of CMOS technology and architectural

CPLD vs. FPGA alternatives to address the wide range of logic design applications. EPROM-,
Architecture EEPROM-, and FLASH-based devices—such as the Altera Classic,
MAX 5000, MAX 7000, MAX9000, and FLASHlogic families—use a product-
term architecture that is optimized for combinatorial-intensive logic designs.
EPROM, EEPROM, and FLASH devices are reprogrammable and
nonvolatile. SRAM-based CPLDs, such as the Altera FLEX8000 family,
use a look-up table (LUT) architecture that is optimized for register-
intensive designs. SRAM-based devices offer in-circuit reconfigurability
for “on-the-fly” logic changes. Altera is the only CPLD vendor to offer all
four major CMOS processes—EPROM, EEPROM, FLASH, and SRAM—to
encompass the broadest range of logic design applications.

In contrast, most FPGAs use SRAM or one-time-programmable antifuse

memory elements. The granular architectures of FPGAs can implement a
wide range of applications, but tend to be less efficient than CPLD
architectures at implementing combinatorial-intensive logic designs.

While antifuse-based devices typically implement the same register-

intensive logic designs as SRAM-based FPGAs, they cannot be erased or
reconfigured. Whereas low-cost, simple PLDs—such as 22V10s—may not
require erasability and reconfigurability, these characteristics are essential
for HCPLDs. Typically, large designs that contain several thousand gates
require several design iterations. Computer simulation helps prevent design
errors; however, designers often need to test hardware or incorporate
unexpected changes to system specifications. With one-time-programmable
antifuse elements, multiple design iterations can result in thousands of
dollars of additional expenses in engineering time and device cost.

Figure 2 shows the logic design applications best suited for CPLD and
FPGA architectures.

Figure 2. Logic Design Applications

FPGAs
CPLDs

Combinatorial-Intensive Register-Intensive
Bus interfacing Data paths
Comparators Hardware emulation
High-speed wide decoders Gate-array prototyping
Large/fast state machines JTAG applications
High-speed glue logic Battery-powered applications
System video controllers Field-test equipment
PAL integration Image controllers

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CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic PIB 18

CPLDs and FPGAs use different interconnect structures: CPLDs use a

CPLD vs. FPGA continuous interconnect structure, while FPGAs use a segmented
Interconnect interconnect structure.
Structure The continuous interconnect structure of CPLDs consists of metal lines of
uniform length that traverse the entire length and width of the device.
Since the resistance and capacitance of all interconnect paths is fixed,
delays between any two logic cells in the device are predictable. This
uniformity of performance across the device minimizes signal skew.

The segmented interconnect structure of FPGAs consists of a matrix of

metal segments that run throughout the device. Depending on the type of
FPGA, either switch matrices or antifuses join the ends of these segments,
allowing signals to travel between logic cells. The number of segments
required to interconnect signals is neither constant nor predictable; therefore,
delays cannot be quantified until placement and routing has been
completed. See Figure 3.

Figure 3. CPLD vs. FPGA Routing Scheme

CPLD Continuous Interconnect FPGA Segmented Interconnect
Structure Structure

A B A B

C C

Fixed/Predictable Delay Variable/Unpredictable Delay

Interconnect structures affect the following device characteristics:

❏ Performance predictability
❏ In-system performance
❏ Logic utilization

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PIB 18 CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic

Performance Predictability
The constant delay between any two logic cells in a continuous interconnect
structure allows designers to predict the performance of a CPLD design.
The timing model for Altera CPLDs contains all parameters necessary for a
designer to predict the overall performance of a design, including
interconnect delays.

The total interconnect delay in a segmented interconnect structure is

directly proportional to the number of segments necessary to route a
signal. It is impossible to know this number until the logic design has been
completely placed and routed by the software. Even minor logic changes
can require major routing changes, affecting the performance characteristics
of the overall device. Timing models and interconnect delay parameters do
not exist for FPGAs because delays cannot be predicted.

In-System Performance
CPLDs are known for high in-system performance, which is a direct result
of their continuous interconnect structure and efficient signal routing.
CPLD delays are not cumulative; the delay the signal incurs is independent
of the path the signal takes. Signals that must travel to different locations in
the device arrive at their destinations with negligible signal skew.

In contrast, FPGA segmented interconnect delays are cumulative. As the

number of interconnect segments increases, the interconnect delay also
increases. If interconnect segments for a direct path are already used, a
signal must pass through a different path, i.e. more segments, to reach its
destination. Therefore, no two signals can be guaranteed to arrive at the
same time. Typically, one signal arrives after the other, which limits the
performance of the design. Signal skew and performance degradation
become more prevalent as more interconnect segments are used,
inefficiently routing signals through the device.

CPLDs offer higher performance than FPGAs of equivalent densities.

Device performance is verified by the Programmable Electronics
Performance Corporation (PREP), a consortium of PLD companies that
has established standard benchmarks for measuring the performance and
logic capacity of PLDs. Figure 4 shows the average benchmark speed
(ABS) of CPLDs and FPGAs with similar gate counts. ABS is calculated by
averaging the mean internal and external benchmark results for all PREP
benchmarks.

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CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic PIB 18

Figure 4. CPLD vs. FPGA Performance

100
CPLD
FPGA

80

60

PREP ABS (MHz)

40

20

0
Altera Altera Xilinx Xilinx Actel
EPF8282A-2 EPM7128-10 XC3142-2 XC3042-125 A1425A-2

Device
(≈ 2,500 Gates)
100 CPLD
FPGA

80

60

PREP ABS (MHz)

40

20

Altera Altera Xilinx Actel

EPF81188A-2 EPM9560-12 XC4010-4 A14100A-2
Device
(10,000 to 12,000 Gates)
MA
BLE E LE
CT
Presentations use or include the most
M
recent certified and/or uncertified PREP
RA

RO

A
PR OG

N IC

PLD Benchmark data which was

S

PREP measured according to Benchmark Suite

PER

IO N

#1, Versions 1.2 & 1.3.

AT
FO

R
R

M
AN PO Any analysis is not endorsed by PREP.
CE C OR

COMPANY

Logic Utilization
The logic cells in most FPGA architectures have fine granularity; therefore,
more logic cells are required to implement a function in an FPGA than in a
CPLD. Figure 5 shows the number of logic cells necessary to implement a
register-intensive design (16-bit up/down binary counter) and a
combinatorial-intensive design (24-bit decoder) in each architecture.

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PIB 18 CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic

Figure 5. Logic Utilization

Register-Intensive Design (16-Bit Up/Down Counter)
60
CPLD
FPGA
50

40

Logic Cells
Required 30

20

10

0
Altera Altera Xilinx Actel
MAX 7000 FLEX 8000 XC4000 ACT3
MAX 9000
Device Family

Combinatorial-Intensive Design (24-Bit Decoder)

20 CPLD
FPGA
16

12
Logic Cells
Required
8

0
Altera Altera Xilinx Actel
MAX 7000 FLEX 8000 XC4000 ACT3
MAX 9000
Device Family

Because the logic cell of an FPGA can contain only small portions of a
design, a heavy burden is placed on its segmented interconnect structure.
Therefore, any routing bottleneck adversely affects device utilization, as
well as device performance, as shown in Figure 4 earlier in the product
information bulletin. As design complexity increases, the probability of
routing conflicts also increases, ultimately leading to lower FPGA device
utilization.

Figure 6 shows the average benchmark capacity (ABC)—the average

number of benchmark instances implemented in a device across all PREP
benchmarks—of CPLDs and FPGAs with similar gate counts. These results
illustrate the lower device utilization in devices with segmented interconnect
structures.

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CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic PIB 18

Figure 6. CPLD vs. FPGA Capacity

16
CPLD
14 FPGA

12

10

PREP ABC (MHz) 8

0
Altera Xilinx
EPF8452A XC4004A
Device
(≈ 4,000 gates)

10
CPLD
FPGA
8

6
PREP ABC (MHz)
4

0
Altera Xilinx Actel
EPF8282A XC3042 1425A
Device M
MA
BLE E LE
CT
Presentations use or include the most
recent certified and/or uncertified PREP
RA

RO

(≈ 2,500 gates) A
PR OG

N IC

PLD Benchmark data which was

S

PREP measured according to Benchmark Suite

PER

IO N

#1, Versions 1.2 & 1.3.

AT
FO

R
R

M
AN PO Any analysis is not endorsed by PREP.
CE C OR

COMPANY

CPLD vs. FPGA PLD technology is measured in microns and metal layers. Micron size
represents the smallest dimension of a transistor within the device; metal
Process layers represent the number of levels in which metal is deposited in the
device. Current standard programmable logic process technologies are
Alternatives 0.8-micron CMOS dual-layer metal (DLM) and 1.0-micron CMOS DLM
technologies. Advances in both technologies provide higher performance
and lower costs, but depend on device architecture. Because of their
continuous interconnect structure, CPLDs benefit more from process
migrations than FPGAs.

The continuous interconnect structure of CPLDs has many metal lines that
traverse the entire device. These metal lines require few transistors to
connect them to logic cells (see Figure 3). CPLD architectures are metal-
optimized and benefit more from process migrations to triple-layer metal

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PIB 18 CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic

(TLM). For example, Altera’s FLEX 8000 family is built on a 0.6-micron,

TLM technology. Its three-dimensional FastTrack Interconnect structure
maps efficiently to three-layers of metal. Figure 7 illustrates the FLEX 8000
TLM advantage using an analogy. Assume that a 30,000 square foot building
needs to be built. This building can be two stories high and use 15,000
square feet of land, or it can be three stories high and use 10,000 square feet
of land. Each floor in this analogy represents a layer of metal. With the
TLM process, the usable density (i.e., the total size of the building) remains
the same, while the die size (i.e., the required amount of land) has been
dramatically reduced.

Figure 7. DLM vs. TLM Technology

Dual-Layer Metal (DLM) Triple-Layer Metal (TLM)

Die Size Die Size

A reduced die size—50% reduction for FLEX 8000A devices—translates to

higher performance and lower costs. FLEX 8000A devices, which use a
0.6-micron TLM process, dramatically increase performance over the
0.8-micron DLM process of FLEX 8000 devices. See Figure 8.

Figure 8. Performance Improvements

2.0

1.5

Relative ABS (MHz) 1.0

0.5

0
FLEX 8000 FLEX 8000A
Device Family

In contrast, a segmented interconnect structure contains relatively few

metal segments that must pass through numerous transistors to connect
logic cells. The large number of transistors in FPGA architectures limits die
size reductions, so FPGAs receive a lesser benefit from TLM process
migrations. Reducing the transistor size from 0.8-micron to 0.6-micron

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CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic PIB 18

shrinks FPGA die size. However, migrating from a DLM to TLM process
does not create additional layers in which to place transistors; therefore,
the die size of FPGAs remains relatively constant. Very few FPGA vendors
use a 0.6-micron, TLM process.

Figure 9 illustrates the limited improvements that FPGA devices achieve

from TLM process migration. FPGAs are limited by transistors, and can
only create a pyramid-like, three-layer structure with most of the area still
on the bottom layer. Without significant architectural changes, FPGA die
size reductions are limited.

Figure 9. Triple-Layer Metal Process

FPGAs CPLDs

Die Area Die Area

As programmable logic vendors continue to push process technology to

smaller dimensions and to increase the number of metal layers, the gap
between CPLD and FPGA performance and cost will be magnified. Metal-
optimized CPLD architectures will continually achieve higher performance
and lower costs than transistor-limited FPGAs.

CPLD vs. FPGA Fast, efficient development software, combined with an understandable
device architecture, is an integral part of any programmable logic solution.
Development Easy-to-use design entry, compilation, and simulation tools help increase
Software design productivity, contributing to the time-to-market advantages of
programmable logic. Altera’s easy-to-use MAX+PLUSII development
software provides designers with a fully integrated design tool that also
interfaces with standard CAE tools. In addition, MAX+PLUS II provides
the following features that increase the efficiency of CPLD designs.

❏ Efficient routing and logic utilization

❏ Quick compilation times
❏ Logic synthesis

Efficient Routing & Logic Utilization

The continuous routing structure of CPLDs allows the compiler to efficiently
fit a design. Altera’s MAX+PLUSII development software includes

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PIB 18 CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic

automatic logic synthesis, and provides 100% logic utilization with optimum
speed performance. These results are achieved without hand-routing.

In contrast, the FPGA‘s segmented interconnect structure hampers the

compiler‘s ability to fit a logic design. Designers must often hand-route
FPGA designs to obtain initial fits or to optimize critical nets. This procedure
requires designers to be intimately familiar with the device architecture
and tools. Even after days or weeks of hand-routing iterations, the result
may still be unsatisfactory due to unacceptable performance or poor device
utilization.

Quick Compilation Times

Compilation times are usually a function of design complexity. However,
a similar design may take hours to compile for FPGAs, while it takes only
minutes for CPLDs. See Figure 10. The FPGA segmented interconnect
structure, combined with fine-grained logic cells, requires the software to
attempt several place-and-route iterations. If routing bottlenecks are
encountered, the software must re-evaluate the entire design and use a
new placement and routing scheme.

Figure 10. MAX+PLUS II vs. FPGA Tools Compile Times

200

150

Minutes
100
FPGA Tools

50

MAX+PLUS II
0
5,000 10,000 15,000+
Gates

Logic Synthesis
Logic synthesis minimizes a design by removing redundant logic and
applying a set of optimization algorithms. Compilers from FPGA vendors
such as Actel and Xilinx do not provide logic synthesis. Instead, these
software packages perform technology mapping in which design
descriptions are “mapped” into a specific architecture by applying simple

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CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic PIB 18

place-and-route techniques. While these techniques may be acceptable for

simple PLDs, they are less efficient for HCPLDs.

As design size increases, high-level design descriptions become the most

efficient design entry technique. Hardware description languages (HDLs)
such as Verilog HDL, VHDL, and the Altera Hardware Description
Language (AHDL) allow designers to focus on system level requirements
rather than architectural details. Designers can rely on the software to
synthesize and optimize a design to a specific PLD architecture. Since
FPGA software does not synthesize designs, it is less efficient at
implementing high-level design descriptions. Altera is the first and only
programmable logic vendor with a development system that contains
advanced, multilevel logic synthesis algorithms to efficiently implement
high-level design descriptions.

Conclusion Altera CPLDs use a continuous interconnect structure that offers predictable
interconnect delays, high performance, and efficient logic utilization.
Because this structure is metal-optimized, it enables CPLDs to take full
advantage of advances in process technology, increasing performance and
reducing customer costs. CPLD development software provides automatic
logic synthesis and quick compile times.

In contrast, a segmented interconnect structure, found in Xilinx and Actel

FPGAs, has many limitations, including unpredictable timing, slow
performance, and poor device utilization. These devices are transistor-
limited, restricting the effectiveness of TLM process technology to reduce
die sizes. FPGA development software also requires extensive hand-routing
and requires long compilation times.

Spanning all major PLD technologies and the entire breadth of logic
applications, Altera CPLDs offer designers the most flexible and easy-to-
use programmable logic devices and development software in the industry.

Altera, MAX+PLUS, MAX, and FLEX are registered trademarks of Altera Corporation. The following are
trademarks of Altera Corporation: MAX+PLUS II, AHDL, FLEX 8000, MAX 7000, MAX 5000, FLEXlogic,
Classic, EPF8282, EPF8452, EPF81188, EPM7128, EPM7128E, EPM7160E, EPM7192E, EPM7256E. Altera
acknowledges the trademarks of other organizations for their respective products or services mentioned in this
document, specifically: Actel and ACT are trademarks of Actel Corporation. Verilog is a registered trademark of
Cadence Design Systems, Inc. PREP is a registered trademark of the Programmable Electronics Performance
2610 Orchard Parkway Corp. Xilinx is a trademark of Xilinx, Inc. Altera products marketed under trademarks are protected under
numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
San Jose, CA 95134-2020 performance of its semiconductor products to current specifications in accordance with Altera’s standard
(408) 894-7000 warranty, but reserves the right to make changes to any products and services at any time without notice. Altera
Applications Hotline: assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera Corporation. Altera
(800) 800-EPLD customers are advised to obtain the latest version of device specifications before relying on
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(408) 894-7104
U.S. and European patents pending
Literature Services:
(408) 894-7144 Copyright © 1995 Altera Corporation. All rights reserved.

Page 12 Altera Corporation