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Mysuru Royal Institute of Technology, Mandya.: Question Bank-2

The document contains questions related to VLSI design concepts like CMOS logic gates, MOS transistor design rules, scaling factors, arithmetic logic unit design and different adder circuits. Specific questions include drawing schematics for logic gates, listing design rules and layers for MOS processes, explaining cascaded inverters and drivers for large capacitive loads.

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38 views1 page

Mysuru Royal Institute of Technology, Mandya.: Question Bank-2

The document contains questions related to VLSI design concepts like CMOS logic gates, MOS transistor design rules, scaling factors, arithmetic logic unit design and different adder circuits. Specific questions include drawing schematics for logic gates, listing design rules and layers for MOS processes, explaining cascaded inverters and drivers for large capacitive loads.

Uploaded by

chaitragowda213_4732
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Mysuru Royal Institute of Technology, Mandya.

Department of Electronics & Communication Engineering.


Question Bank-2
Subject:VLSI Design. Code: 17EC63
Module 2
1. i. Draw the circuit schematic and stick diagram for CMOS 2 input NOR gate.
←
ii. Write the layout for the logic expression Y = A +BC using CMOS design.
iii. Draw the stick diagram for nMOS EX-OR gate
iv. Draw the circuit and stick diagram of two input NAND gate and two input NOR gate
using CMOS logic, use standard colour or monochrome codes
2. With neat sketches, explain λ based design rules for pMOS, nMOS and nMOS depletion mode
transistor.
3. List the colour, stick encoding, and mask layout encoding, layers for a simple metal nMOS process.
4. What are the different MOS layers? Explain λ based design rules applicable to MOS layers
and transistors.
5. Draw the circuit and stick diagram of two input NAND gate and two input NOR gate using
CMOS logic, use standard colour or monochrome codes
6. List the λ-based design rules for CMOS.
7. Define the sheet resistance and standard unit of capacitance ⧠Cg and delay unit of time Calculate
the ON resistance for nmos inverter with Rsn=10kΩ, Zpu=4 and zpd=1.

8. Explain cascaded inverters to drive large capacitive loads. Obtain an equation to find number of
stages.
9. Narrate the steps involved in calculating the sheet resistance of i)Transistor channels ii)nMOS
inverter iii)CMOS inverter.
10. Derive the expressions for rise time and fall time for CMOS inverter.
11. Obtain the expression for total delay for N stages of nmos and cmos inverters in terms of Width
factor f and delay τ.
12. Explain cascaded inverters as drivers , super buffers and Bicmos drivers for large capacitive loads.
13. Calculate the ON resistance for nMOS inverter with R sn=10 KΩ , Z PU =8∧Z pd=1.
Module 3
14. What are the scaling factors for:1) Gate capacitance C g 2)Max. Operating frequency f o
3)Current density J 4) power speed product PT 5) parasitic capacitance Cx 6) Power dissipation
per unit area. 7)Channel resistance 8) Saturation Current 9)oxide capacitance C o 10) Gate area A g
11) Qon 12) Gate delay Td 13) Power dissipation per gate 14) switching energy per gate .
15. How to implement arithmetic and logic operations with a standard adder? Explain with the help of
logic expressions.
16. What is structured design process? Explain.
17. Discuss the problem associated with VLSI Design.
18. List and explain the general considerations to be considered in digital system design
19. Explain the design of data path in 4 bit arithmetic processor with floor plan for 4 bit data path
20. Write MOS switch implementation of 4X4 crossbar switch.
21. Define regularity and explain the design of an ALU subsystem
22. Explain Manchester carry chain with expression and circuits.
23. List the 3 different techniques for carry generation and explain carry select adder with
optimization.
24. Explain carry skip adder with optimization.
25. Explain carry look ahead adder.

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