Assembly Language for x86 Processors

7th Edition
Kip Irvine

Chapter 2: x86 Processor

Architecture

Slides prepared by the author

Revision date: 1/15/2014

(c) Pearson Education, 2014. All rights reserved. You may modify and copy this slide show for your personal use, or for
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 Chapter Overview

• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• 64-bit Processors
• Components of an IA-32 Microcomputer
• Input-Output System

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 General Concepts

• Basic microcomputer design

• Instruction execution cycle
• Reading from memory
• How programs run

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 Basic Microcomputer Design
• clock synchronizes CPU operations
• control unit (CU) coordinates sequence of execution steps
• ALU performs arithmetic and bitwise processing

data bus

registers

I/O I/O
Central Processor Unit Memory Storage
Device Device
(CPU) Unit
#1 #2

ALU CU clock

control bus

address bus

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 Clock
• synchronizes all CPU and BUS operations
• machine (clock) cycle measures time of a single
operation
• clock is used to trigger events

one cycle

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 What's Next

• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• 64-Bit Processors
• Components of an IA-32 Microcomputer
• Input-Output System

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 Instruction Execution Cycle

• Fetch
• Decode
• Fetch operands
• Execute
• Store output

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 Reading from Memory
Multiple machine cycles are required when reading from
memory, because it responds much more slowly than the
CPU. The steps are:
1. Place the address of the value you want to read on the
address bus.
2. Assert (changing the value of) the processor’s RD
(read) pin.
3. Wait one clock cycle for the memory chips to respond.
4. Copy the data from the data bus into the destination
operand

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 Cache Memory

• High-speed expensive static RAM both inside and

outside the CPU.
• Level-1 cache: inside the CPU
• Level-2 cache: outside the CPU
• Cache hit: when data to be read is already in cache
memory
• Cache miss: when data to be read is not in cache
memory.

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 How a Program Runs
User

sends program
name to

Operating searches for Current

system program in directory

gets starting
cluster from returns to
System
loads and path
starts
Directory Program
entry

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 IA-32 Processor Architecture

• Modes of operation
• Basic execution environment
• Floating-point unit
• Intel Microprocessor history

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 Modes of Operation
• Protected mode
• native mode (Windows, Linux)
• Real-address mode
• native MS-DOS
• System management mode
• power management, system security, diagnostics

• Virtual-8086 mode
• hybrid of Protected
• each program has its own 8086 computer

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 Basic Execution Environment

• Addressable memory
• General-purpose registers
• Index and base registers
• Specialized register uses
• Status flags
• Floating-point, MMX, XMM registers

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 Addressable Memory

• Protected mode
• 4 GB
• 32-bit address
• Real-address and Virtual-8086 modes
• 1 MB space
• 20-bit address

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 General-Purpose Registers

Named storage locations inside the CPU, optimized for

speed.
32-bit General-Purpose Registers

EAX EBP
EBX ESP
ECX ESI
EDX EDI

16-bit Segment Registers

EFLAGS CS ES
SS FS
EIP
DS GS

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 Accessing Parts of Registers
• Use 8-bit name, 16-bit name, or 32-bit name
• Applies to EAX, EBX, ECX, and EDX
8 8

AH AL 8 bits + 8 bits

AX 16 bits

EAX 32 bits

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 Index and Base Registers

• Some registers have only a 16-bit name for their

lower half:

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 Some Specialized Register Uses (1 of 2)

• General-Purpose
• EAX – accumulator
• ECX – loop counter
• ESP – stack pointer
• ESI, EDI – index registers
• EBP – extended frame pointer (stack)
• Segment
• CS – code segment
• DS – data segment
• SS – stack segment
• ES, FS, GS - additional segments

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 Some Specialized Register Uses (2 of 2)

• EIP – instruction pointer

• EFLAGS
• status and control flags
• each flag is a single binary bit

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 Status Flags
• Carry
• unsigned arithmetic out of range
• Overflow
• signed arithmetic out of range
• Sign
• result is negative
• Zero
• result is zero
• Auxiliary Carry
• carry from bit 3 to bit 4
• Parity
• sum of 1 bits is an even number

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 Floating-Point, MMX, XMM Registers

• Eight 80-bit floating-point data registers ST(0)

• ST(0), ST(1), . . . , ST(7) ST(1)

ST(2)
• arranged in a stack
ST(3)
• used for all floating-point
ST(4)
arithmetic
ST(5)
• Eight 64-bit MMX registers
ST(6)
• Eight 128-bit XMM registers for single-
ST(7)
instruction multiple-data (SIMD) operations

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 What's Next

• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• 64-Bit Processors
• Components of an IA-32 Microcomputer
• Input-Output System

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 IA-32 Memory Management

• Real-address mode
• Calculating linear addresses
• Protected mode
• Multi-segment model
• Paging

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 Protected Mode (1 of 2)

• 4 GB addressable RAM
• (00000000 to FFFFFFFFh)
• Each program assigned a memory partition which
is protected from other programs
• Designed for multitasking
• Supported by Linux & MS-Windows

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 What's Next

• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• 64-Bit Processors
• Components of an IA-32 Microcomputer
• Input-Output System

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 64-Bit Processors

• 64-Bit Operation Modes

• Compatibility mode – can run existing 16-bit and 32-bit
applications (Windows supports only 32-bit apps in this
mode)
• 64-bit mode – Windows 64 uses this
• Basic Execution Environment
• addresses can be 64 bits (48 bits, in practice)
• 16 64-bit general purpose registers
• 64-bit instruction pointer named RIP

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 64-Bit General Purpose Registers
• 32-bit general purpose registers:
• EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, R8D,
R9D, R10D, R11D, R12D, R13D, R14D, R15D
• 64-bit general purpose registers:
• RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8, R9,
R10, R11, R12, R13, R14, R15

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 What's Next

• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• 64-Bit Processors
• Components of an IA-32 Microcomputer
• Input-Output System

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 Components of an IA-32 Microcomputer

• Motherboard
• Video output
• Memory
• Input-output ports

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 Motherboard
• CPU socket
• External cache memory slots
• Main memory slots
• BIOS chips
• Sound synthesizer chip (optional)
• Video controller chip (optional)
• IDE, parallel, serial, USB, video, keyboard, joystick,
network, and mouse connectors
• PCI bus connectors (expansion cards)

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 Intel D850MD Motherboard mouse, keyboard,
parallel, serial, and USB
Video
connectors
Audio chip

PCI slots
memory controller hub
Pentium 4 socket
AGP slot

dynamic RAM

Firmware hub

I/O Controller
Speaker Power connector
Battery
Diskette connector
Source: Intel® Desktop Board D850MD/D850MV Technical Product IDE drive connectors
Specification

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 Intel 965 Express Chipset

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 Video Output

• Video controller
• on motherboard, or on expansion card
• AGP (accelerated graphics port technology)*
• Video memory (VRAM)
• Video CRT Display
• uses raster scanning
• horizontal retrace
• vertical retrace
• Direct digital LCD monitors
• no raster scanning required

* This link may change over time.

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 Sample Video Controller (ATI Corp.)

• 128-bit 3D graphics
performance powered by
RAGE™ 128 PRO
• 3D graphics performance
• Intelligent TV-Tuner with
Digital VCR
• TV-ON-DEMAND™
• Interactive Program Guide
• Still image and MPEG-2 motion
video capture
• Video editing
• Hardware DVD video playback
• Video output to TV or VCR

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 Memory
• ROM
• read-only memory
• EPROM
• erasable programmable read-only memory
• Dynamic RAM (DRAM)
• inexpensive; must be refreshed constantly
• Static RAM (SRAM)
• expensive; used for cache memory; no refresh required
• Video RAM (VRAM)
• dual ported; optimized for constant video refresh
• CMOS RAM
• complimentary metal-oxide semiconductor
• system setup information
• See: Intel platform memory (Intel technology brief: link address may
change)

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 Input-Output Ports

• USB (universal serial bus)

• intelligent high-speed connection to devices
• up to 12 megabits/second
• USB hub connects multiple devices
• enumeration: computer queries devices
• supports hot connections
• Parallel
• short cable, high speed
• common for printers
• bidirectional, parallel data transfer
• Intel 8255 controller chip

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 Input-Output Ports (cont)

• Serial
• RS-232 serial port
• one bit at a time
• uses long cables and modems
• 16550 UART (universal asynchronous receiver
transmitter)
• programmable in assembly language

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 Device Interfaces

• ATA host adapters

• intelligent drive electronics (hard drive, CDROM)
• SATA (Serial ATA)
• inexpensive, fast, bidirectional
• FireWire
• high speed (800 MB/sec), many devices at once
• Bluetooth
• small amounts of data, short distances, low power
usage
• Wi-Fi (wireless Ethernet)
• IEEE 802.11 standard, faster than Bluetooth

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 What's Next

• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• Components of an IA-32 Microcomputer
• Input-Output System

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 Levels of Input-Output
• Level 3: High-level language function
• examples: C++, Java
• portable, convenient, not always the fastest
• Level 2: Operating system
• Application Programming Interface (API)
• extended capabilities, lots of details to master
• Level 1: BIOS
• drivers that communicate directly with devices
• OS security may prevent application-level code from working
at this level

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 Displaying a String of Characters

Application Program Level 3

When a HLL program

displays a string of OS Function Level 2

characters, the
following steps take
place: BIOS Function Level 1

Hardware Level 0

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 Programming levels

Assembly language programs can perform

input-output at each of the following levels:

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 Summary
• Central Processing Unit (CPU)
• Arithmetic Logic Unit (ALU)
• Instruction execution cycle
• Multitasking
• Floating Point Unit (FPU)
• Complex Instruction Set
• Real mode and Protected mode
• Motherboard components
• Memory types
• Input/Output and access levels

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 42 69 6E 61 72 79
What does this say?

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