For New Designs: SSC9522S Data Sheet
For New Designs: SSC9522S Data Sheet
Description Package
The SSC9522S is a controller IC (SMZ* method) for SOP18
half-bridge resonant type power supply, incorporating a
floating drive circuit for the high-side power MOSFET
drive.
The product achieves high efficiency, low noise and
high cost-performance power supply systems with few
external components.
*SMZ; Soft-switched Multi-resonant Zero Current
Not to Scale
switch (All switching periods work with soft switching
ns
operation.)
Electrical Characteristics
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Features ● Absolute maximum rating of VCC pin is 35 V
● Minimum oscillation frequency is 28.3 kHz (typ.)
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● Built-in floating drive circuit for high-side power
● Maximum oscillation frequency is 300 kHz (typ.)
MOSFET
D
● Soft Start Function
● Capacitive Mode Operation Detection Function
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(Pulse-by-pulse)
● Automatic Dead Time Adjustment Function
● Brown-in and Brown-out Function
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● Protections Applications
High-side Driver UVLO Protection
External Latched Shutdown Function ● Digital appliance
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Typical Application
m
m
R1
BR1
o
VAC
C1 R2
ec
R3
R
D1 R8
RB(H) DS(H)
ot
14 Q(H)
16
C10 D2
VB T1
VGH
RA(H)
N
REG RGS(H)
8 D51
15
VS
SSC9522S PC1
VSEN RB(L) DS(L)
1 Q(L)
U1 11
C51
VCC VGL Cv
2 RA(L)
C9 GND
RGS(L)
4 D52
9
RV
R4 C2
Ci
10 CRV
FB CSS OC RC
RC COM
3 5 6 7
External C11
power supply
R5 R6
R7
ROCP
C3
C4 PC1 C5 C6 C7 C8 C12
Contents
Description ------------------------------------------------------------------------------------------------------ 1
Contents --------------------------------------------------------------------------------------------------------- 2
1. Absolute Maximum Ratings----------------------------------------------------------------------------- 3
2. Electrical Characteristics -------------------------------------------------------------------------------- 4
3. Block Diagram --------------------------------------------------------------------------------------------- 6
4. Pin Configuration Definitions--------------------------------------------------------------------------- 6
5. Typical Application --------------------------------------------------------------------------------------- 7
ns
6. Physical Dimensions -------------------------------------------------------------------------------------- 8
ig
7. Marking Diagram ----------------------------------------------------------------------------------------- 8
8. Operational Description --------------------------------------------------------------------------------- 9
es
8.1 Resonant Circuit Operation ----------------------------------------------------------------------- 9
8.2 Startup Operation --------------------------------------------------------------------------------- 12
D
8.3 Soft Start Function -------------------------------------------------------------------------------- 13
8.4 High-side Driver ----------------------------------------------------------------------------------- 13
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8.5 Constant Output Voltage Control-------------------------------------------------------------- 13
8.6 Automatic Dead Time Adjustment Function ------------------------------------------------ 14
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8.7 Capacitive Mode Operation Detection Function -------------------------------------------- 15
8.8 Brown-in and Brown-out Function ------------------------------------------------------------ 16
8.9 External Latched Shutdown Function -------------------------------------------------------- 17
fo
ns
RC Pin Voltage VRC 7−4 − 6 to 6 V
ig
REG Pin Source Current IREG 8−4 − 20.0 mA
es
DC 9−4 − 2 to 2 mA
RV Pin Current IRV
9−4 − 100 to 100
D
Pulse 40 ns mA
VGL Pin Voltage VGL 11 − 4 − 0.3 to VREG + 0.3 V
ew
Voltage between VB Pin and VS
VB−VS 14 − 15 − 0.3 to 15.0 V
Pin
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VS Pin Voltage VS 15 − 4 − 1 to 600 V
VGH Pin Voltage VGH 16 − 4 VS − 0.3 to VB + 0.3 V
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*The pin 14, pin 15 and pin 16, are guaranteed 1000 V of ESD withstand voltage (Human body model).
Other pins are guaranteed 2000V of ESD withstand voltage.
en
m
o m
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R
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2. Electrical Characteristics
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); and current
coming out of the IC (sourcing) is negative current (−).
Unless otherwise specified, TA = 25 °C, VCC = 15 V.
Characteristic Symbol Conditions Pin Min. Typ. Max. Unit
Startup Circuit and Circuit Current
Operation Start Voltage VCC(ON) 2−4 10.2 11.8 13.0 V
Operation Stop Voltage (1)
VCC(OFF) 2−4 8.8 9.8 10.9 V
Circuit Current in Operation ICC(ON) 2−4 — — 20.0 mA
Circuit Current in Non-operation ICC(OFF) VCC = 9 V 2−4 — — 1.2 mA
ns
Circuit Current in Latched
ICC(L) VCC = 11 V 2−4 — — 1.2 mA
Shutdown Operation
ig
Soft Start
5−4 −0.21 −0.18 −0.15
es
CSS Pin Charge Current ICSS(C) mA
CSS Pin Reset Current ICSS(R) VCC = 9 V 5−4 1.0 1.8 2.4 mA
D
ON / OFF
ew
VSEN = 3 V
CSS Pin Threshold Voltage (2) VCSS(2) VOC = 0 V
5−4 0.50 0.59 0.68 V
Oscillator
rN
11 − 10
Minimum Oscillation Frequency f(MIN) VCC = 9 V 26.2 28.3 31.2 kHz
16 − 15
11 − 10
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16 − 15
11 − 10
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Standby Operation
Burst Oscillation frequency fCSS IFB = – 3.5 mA 5−4 70 105 130 Hz
m
Feedback control
m
Oscillation stop
Supply of Driver Circuit
R
REF Pin Output Voltage VREG IFB = – 2 mA 8−4 9.9 10.5 11.1 V
ot
(1)
VCC(OFF) < VCC(ON)
ns
VSEN Pin Threshold Voltage (ON) VSEN(ON) 1−4 1.32 1.42 1.52 V
ig
VSEN Pin Threshold Voltage
VSEN(OFF) 1−4 1.08 1.16 1.24 V
(OFF)
es
Detection of Voltage Resonant
D
Voltage Resonant Detection
VRV(1) 9−4 3.8 4.9 5.4 V
Voltage (1)
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Voltage Resonant Detection
VRV(2) 9−4 1.20 1.77 2.30 V
Voltage (2)
Detection of Current Resonant and OCP
rN
Capacitive Mode Operation 0.055 0.155 0.255 V
VRC 7−4
Detection Voltage –0.255 –0.155 –0.055 V
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OC Pin Threshold Voltage (Low) VOC(L) VCSS = 3 V 6−4 1.42 1.52 1.62 V
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OC Pin Threshold Voltage (High) VOC(H) VCSS = 3 V 6−4 1.69 1.83 1.97 V
en
VCSS = 3 V
CSS Pin Sink Current (Low) ICSS(L)
VOC = 1.65 V
5−4 1.0 1.8 2.4 mA
m
VCSS = 3 V
CSS Pin Sink Current (High) ICSS(H)
VOC = 2 V
5−4 12.0 20.0 28.0 mA
o
CSS Pin Sink Current (High Speed) ICSS(S) VRC = 2.8 V 5−4 11.0 18.3 25.0 mA
ec
CSS Pin Threshold Voltage (1) VCSS(1) 5−4 7.0 7.8 8.6 V
N
(2)
VCC(LA_OFF) < VCC(OFF)
3. Block Diagram
14 VB
VCC 2
UVLO
Start/Stop
Level 16 VGH
Reg/Bias
shift
OVP/TSD/Latch
15 VS
GND 4 High-side driver
VCC
ns
Input
VSEN 1
ig
sense 8 REG
Main logic
es
11 VGL
OLP
D
10 COM
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Frequency
FB 3 FB control Dead time
control rN RC detector 7 RC
Freq.
RV detector 9 RV
Max.
Soft-start/OC
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CSS 5
Standby control OC detector 6 OC
d
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en
5 CSS VB 14
6 OC Overcurrent Protection (OCP) signal input
6 OC (NC) 13
N
BR1 R8
SSC9522S PC1
1 RB(L) DS(L)
VSEN
Q(L)
ec
U1 C51
2 11
VCC
o VGL Cv
RA(L)
C9 4
m RGS(L)
R4 C2 3 5 6 7
en
C11
R5 R6
de
R7
ROCP
C3
C4 C6 C7 C8
d
PC1 C5 fo C12
http://www.sanken-ele.co.jp/en
SANKEN ELECTRIC CO.,LTD.
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D
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ns
7
SSC9522S
6. Physical Dimensions
● SOP18
ns
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es
D
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rN
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d
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NOTES:
● Dimension is in millimeters
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7. Marking Diagram
o
ec
18
SSC9522S
R
Part Number
SKYMD
ot
Lot Number
XXXX
N
ns
8.1 Resonant Circuit Operation with VIN. The series resonant circuit and the voltage
Figure 8-1 shows a basic RLC series resonant circuit. resonant capacitor CV are connected in parallel with Q(L).
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The series resonant circuit is comprised of a resonant
inductor LR, a primary winding P of a transformer T1
es
and a current resonant capacitor Ci.
R L C In the resonant transformer T1, the coupling between
D
primary winding and secondary winding is designed to
be poor so that the leakage inductance increases. By
ew
using it as LR, the series resonant circuit can be down
sized. The dotted mark in T1 shows the winding polarity,
Figure 8-1. RLC Series Resonant Circuit
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the secondary windings S1 and S2 are connected so that
the polarities are set to the same position shown in
Figure 8-3, and the winding numbers of each other are
The impedance of the circuit, Ż, is as the following
equal.
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Equation.
1
1 Ż = R + j �ω(LR + LP ) − � (5)
Ż = R + j �2πfL − � (2) ωCi
m
2πfC
1
m
ID(H)
R
Q(H) Series resonant circuit
f0 Frequency VDS(H)
VGH LR IS1
T1 VOUT
VIN (+)
Figure 8-2. Impedance of Resonant Circuit ID(L)
Q(L) Cv P S1
LP
In Equation (2), Ż becomes minimum value (= R) at VDS(L)
2πfL = 1/2πfC, and then ω is calculated by Equation VGL VCi S2
(3) . (−)
Ci
ICi IS2
1
ω = 2πf = (3) Figure 8-3. Current Resonant Power Supply Circuit
√LC
In the current resonant power supply, Q(H) and Q(L) are VGH
alternatively turned on and off. The on time and off time
of them are equal. There is a dead time between Q(H) on VGL
period and Q(L) on period. During the dead time, both
Q(H) and Q(L) are in off status.
VDS(H) VIN+VF(H)
The current resonant power supply is controlled by
the frequency control. When the output voltage
decreases, the IC makes the switching frequency low so ID(H)
that the output power is increased and the output voltage
is kept constant. This control must operate in the
inductance area (fSW > f0). Since the winding current is VDS(L)
delayed from the winding voltage in the inductance area,
the turn-on operation is ZCS (Zero Current Switching)
ID(L)
ns
and the turn-off operation is ZVS (Zero Voltage
Switching). Thus, the switching loss of Q(H) and Q(L) is
ig
nearly zero, ICi
In the capacitance area (fSW < f0), the current resonant
es
power supply operates as follows. When the output
voltage decreases, the switching frequency is decreased,
D
and then the output power is more decreased. Thus, the VCi
VIN
output voltage cannot be kept constant. Since the
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winding current goes ahead of the winding voltage in the
capacitance area, the operation with hard switching IS1
occurs in Q(H) and Q(L). Thus, the power loss increases.
rN
This operation in the capacitance area is called the
IS2
capacitive mode operation. The current resonant power
supply must be operated without the capacitive mode
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A B D E
operation (refer to Section 8.7 about details of it). C F
d
Figure 8-4 shows the basic operation waveform of Figure 8-4. The Basic Operation Waveforms of
de
current resonant power supply (see Figure 8-3 about the Current Resonant Power Supply
symbol in Figure 8-4). The current resonant waveforms
in normal operation are divided a period A to a period F.
en
ID(H)
In following description, ON LR
LP
ID(H) is the current of Q(H), VIN
m
Q(L) Cv
VF(L) is the forwerd voltage of Q(L), VCV
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Ci
VCi is Ci voltage, and VCi
VCV is CV voltage.
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2) Period B OFF
S2
After the secondary side current becomes zero, the
resonant current flows to the primary side only as Ci
shown in Figure 8-6 and Ci is charged by it.
Figure 8-6. Operation in Period B
3) Period C
Q(H)
Pireod C is the dead-time. Both Q(H) and Q(L) are in
off-state. OFF LR
LP
When Q(H) turns off, IL is flowed by the energy stored VIN
in the series resonant circuit as shown in Figure 8-7, IL
and CV is discharged. When VCV decreases to VF(L), Q(L) Cv
−ID(L) flows through the body diode of Q(L) and VCV is VCV
clamped to VF(L). OFF
-ID(L)
After that, Q(L) turns on. Since VDS(L) is nearly zero at
the point, Q(L) operates in ZVS and ZCS. Thus, Ci
switching loss is nearly zero.
Figure 8-7. Operation in Period C
4) Period D
ns
When Q(L) turns on, ID(L) flows as shown in Figure 8-8
and the primary winding voltage of the transformer Q(H)
ig
adds VCi. At the same time, energy is transferred to LR
OFF
the secondary circuit. When the primary winding
es
LP
VIN
voltage can not keep the secondary rectifier ON, the
ID(L)
D
energy to the secondary circuit is stopped. S1
Q(L) Cv
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5) Period E ON
S2 IS2
After the secondary side current becomes zero, the Ci
resonant current flows to the primary side only as
rN VCi
shown in Figure 8-9 and Ci is charged by it.
Figure 8-8. Operation in Period D
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6) Period F
This pireod is the dead-time. Both Q(H) and Q(L) are in
off-state. Q(H)
d
OFF LR
stored in the series resonant circuit as shown in Figure LP
VIN
8-10. CV is discharged. When VCV decreases to VIN +
en
ID(L)
VF(H), − ID(H) flows through body diode of Q(H) and
S1
Q(L) Cv
VCV is clamped to VIN + VF(H).
m
period A.
Q(H)
The above operation is repeated, the energy is
ot
-ID(H)
OFF LR
transferred to the secondary side from the resonant VIN
LP
N
circuit.
-IL
Q(L)
VCV
Cv
OFF
Ci
ns
voltage
circuit, and returns to the state before startup. VCSS(2)
ig
VGL pin
voltage
es
R1 External power supply
time
D
R2
C1 U1 Figure 8-14. Startup Waveforms
R3
VCC 2
ew
1
VSEN
CSS GND rN When the IC is supplied by the external power supply,
R4 5 4 tST is calculated by Equation (7).
C2 C3 tST is the total startup time until the IC starts a
C6
switching operation after VCC pin voltage reaches
VCC(ON).
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C6 × VCSS( 2 )
t ST = t ST1 = (7)
External power supply | I CSS( C ) |
en
CSS GND
● Without Brown-in and Brown-out Function
5 4
o
C6
period that until the VSEN pin voltage reaches to
R
t ST 2 = C2 × 380k (8)
N
8.3 Soft Start Function When the voltage of between the VB pin and the VS
pin, VB-S, increases to VBUV(ON) = 7.3 V or more, an
Figure 8-15 shows the waveform of the CSS pin in the internal high-side drive circuit starts operation. When
startup operation. VB-S decreases to VBUV(OFF) = 6.4 V or less, its drive
The IC has Soft Start Function to reduce stress of circuit stops operation.
peripheral component and prevent the capacitive mode In case the both ends of C10 are short, the IC is
operation. During the soft start operation, C6 connected protected by VBUV(OFF).
to the CSS pin is charged by the CSS Pin Charge D1 should use a fast recovery diode that is short
Current, ICSS(C) = − 0.18 mA. The oscillation frequency is recovery time and low leakage current. AG01A
varied by the CSS pin voltage. The oscillation frequency (Vrm = 600 V, Sanken product) is recommended when
becomes gradually low with the increasing CSS pin the maximum input voltage is 265V AC.
voltage. At same time, output power increases. When C10 should use film or ceramic capacitor that is the
the output voltage increases, the IC is operated with an low ESR and the low leakage current.
oscillation frequency controlled by feedback.
ns
If the overcurrent protection activates as soon as the D1 R8 Bootstrap circuit
IC starts and the CSS pin voltage is under the CSS Pin
ig
Threshold Voltage (2), VCSS(2) = 0.59 V, the IC stops 14
C10
VB VGH 16
es
switching operation. Since the period of the high peak D2
High- side
current of primary windings becomes short, the stress of Driver Q(H) T1
D
15
peripheral components is reduced. REG VS
8
When the IC becomes any of the following conditions, VGL
11
C9 Cv
ew
C6 is discharged by the CSS Pin Reset Current,
GND Q(L)
ICSS(R) = 1.8 mA. 4 Ci
U1 COM 10
OCP
CSS pin Figure 8-17 shows the FB pin peripheral circuit. The
de
Soft start
peropd oscillation frequency is controlled by the FB pin, the
output voltage is controlled to constant voltage (in
m
inductance area).
C6 is charged by -0.18mA When the FB pin current decreases to the FB Pin
m
VCSS(2)=0.59V
Source current at Burst Mode Start, ICONT(1) = − 2.5 mA
time or less at light load, the IC stops switching operation.
o
Primary
winding This operation reduces switching loss, and prevents the
ec
OCP
considered about the secular change of CTR and its
0A current ability for control should be set ICONT(2) = − 3.7
ot
time
mA (min.) or less. The recommend value of R6 is
560 Ω.
N
SW2
As shown in Figure 8-18, if the dead time is shorter 15 T1
VS
than the voltage resonant period, the power MOSFET is
turned on and off during the voltage resonant operation. Logic Q(L)
Cv
In this case, the power MOSFET turned on and off in VGL 11 VCV
hard switching operation, and the switching loss
increases. The Automatic Dead Time Adjustment SW1 Ci
10
COM
Function is the function that the ZVS (Zero Voltage
RC
Switching) operation of Q(H) and Q(L) is controlled RV CRV
9
automatically by the voltage resonant period detection of U1
IC. The voltage resonant period is varied by the power
ns
supply specifications (input voltage and output power, Figure 8-19. RV Pin Peripheral Circuit and Dead Time
etc.). However, the power supply with this function is Detection Circuit
ig
unnecessary to adjust the dead time for each power
supply specification.
es
Q(L) drain to dt dt
VGL source voltage,
D
VDS(L)
dv
time
ew
VGH Dead time
Differential
Q(H) D-S voltage, current,Δi
Loss increase by hard
rN
switching operation
VDS(H) time
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Figure 8-19 shows the RV pin peripheral circuit and and Q(H) turn off, this function operates as follows:
the internal dead time detection circuit. The external
m
and the RV pin. The value of CRV is about 5 pF. kept on state. The resonant current flows through CV,
The RV pin voltage is the divided voltage by resistors Ci and T1 (refer to Figure 8-19) and the CV voltage,
o
between the internal reference voltage, Reg, and the VCV, increases from 0 V. When VCV becomes
ec
GND pin. When the drain to source voltage of Q(L), Equation (11), the resonant current flows through the
VDS(L), increases, the differential current, Δi, flows body diode of Q(H) and VCV is clamped VIN + VF(H).
R
through CRV (refer to Figure 8-20). The dv/dt when The period that until VCV is clamped after VCV starts
VDS(L) increases is detected by Δi input to the RV pin. to increase is defined as the voltage resonant period.
ot
(11)
response improvement are achieved.
Δi is calculated by Equation (9). The CRV should be
Where, VIN is input voltage and VF(H) is the forward
adjusted in all condition including transient state so that
voltage of the body diode of Q(H)
Δi satisfies Equation (10).
If Δi is large, the capacitance of CRV is adjusted small.
In this time, the differential current, Δi, flows through
When dt is under 40 ns, Δi is ± 100 mA.
CRV. The RV pin voltage increases from the voltage
divided by internal resistors and becomes internal
dv clamped voltage. When the voltage resonant period
Δi=C RV × (9)
dt finishes and flowing Δi finishes, the RV pin voltage
starts to decrease. When the RV pin voltage becomes
100 (mA) × 40 (ns) the Voltage Resonant Detection Voltage (1),
Δi ≤ (10)
VRV(1) = 4.9 V, Q(H) is turned on and SW1 is turned off.
dt
The period that until SW1 is turned off after SW2 is When the RV pin is inputted the signal of VRV(1) and
turned on is defined as the automatically adjusted VRV(2), the IC is controlled ZVS (Zero Voltage
dead time. Switching) always by the Automatic Dead Time
Adjustment Function.
● Q(H) Turns Off In minimum output power at maximum input voltage
After Q(H) turns off, SW1 is turned on while SW2 is and maximum output power at minimum input voltage,
kept on state. The resonant current flows through CV, the ZCS (Zero Current Switching) operation of IC (the
Ci and T1 (refer to Figure 8-19) and the CV voltage, drain current flows through the body diode is about 1 μs
VCV, decrease from the input voltage, VIN. as shown in Figure 8-21), should be checked based on
When VCV becomes Equation (12), the resonant actual operation in the application.
current flows through the body diode of Q(L) and VCV
is clamped − VF(L). The period that until VCV is
clamped after VCV starts to decrease is defined as the 8.7 Capacitive Mode Operation Detection
ns
voltage resonant period. Function
VCV ≤ −VF( L )
ig
(12) The resonant power supply is operated in the
inductance area shown in Figure 8-22. In the capacitance
es
area, the power supply becomes the capacitive mode
Where, VF(L) is the forward voltage of the body diode
operation (refer to Section 8.1). In order to prevent the
D
of Q(L).
operation, the minimum oscillation frequency is needed
to be set higher than f0 on each power supply
In this time, the differential current, Δi, flows through
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specification.
CRV. The RV pin voltage decreases from the voltage
However, the IC has the capacitive mode operation
divided by internal resistors and becomes about the
Detection Function kept the frequency higher than f0.
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ground voltage. When the voltage resonant period
Thus, the minimum oscillation frequency setting is
finishes and flowing Δi finishes, the RV pin voltage
unnecessary and the power supply design is easier. In
starts to increase. When the RV pin voltage becomes
addition, the ability of transformer is improved because
fo
SW1 ON ON
m
OFF
Capacitance area Inductance area
m
ON
SW2
Impedance
OFF OFF
o
f0
Voltage Resonant fresuency
resonant
Q(L) drain to source
ot
period
voltage, VDS(L)=VCV Hard switching Sift switching
N
RV pin voltage
VRV(1)
VRV(2)
Uncontrollable operation
● Period in which the Q(H) is ON off, output short and dynamically output power
Figure 8-23 shows the RC pin waveform in the changing). In addition, the RC pin voltage should be
inductance area, and Figure 8-24 shows the RC pin within the absolute maximum voltage ± 6 V.
waveform in the capacitance area. Since ROCP and C11 are used by Overcurrent
In the inductance area, the RC pin voltage doesn’t Protection (OCP), these values should take account of
cross VRC = + 0.155 V in the downward direction OCP. If the RC pin voltage becomes more than the RC
during the on period of Q(H) as shown in Figure 8-23. pin threshold voltage (High speed), VRC(S) = 2.35 V, or
On the contrary, in the capacitance area, the RC pin less than VRC(S) = – 2.35 V, OCP becomes active (refer
voltage crosses VRC = + 0.155 V in the downward to Section 8.9).
direction. At this point, the capacitive mode operation
is detected. Thus, Q(H) is turned off, and Q(L) is turned 16
on, as shown in Figure 8-24. VGH
U1
15 T1
VS
● Period in which the Q(L) is On
ns
ID(H)
Contrary to the above of Q(H), in the capacitance area, VGL
11
Cv ID(L)
ig
the RC pin voltage crosses VRC = – 0.155 V in the
upward directiont during the on period of Q(L). At Ci
es
10
this point, the capacitive mode operation is detected. RC COM
GND CSS OC RC
Thus, Q(L) is turned off and Q(H) is turned on. 4 5 6 7 C12
D
As above, since the capacitive mode operation is R11
C14
ew
ROCP
detected by pulse-by-pulse and the operating C13
C8
frequency is synchronized with the frequency of the
capacitive mode operation, and the capacitive mode
rN
operation is prevented. Figure 8-25. RC pin peripheral circuit
VDS(H) OFF
fo
RC pin
operation of the IC is stopped by Brown-in and
de
voltage
VRC+ Brown-out Function. This function prevents excessive
0 input current and overheats.
en
VDS(H) OFF
● When the VSEN pin voltage is more than VSEN
o
0 ON
(OFF) = 1.16 V, the IC stops switching operation.
Capacitive mode
R
RC pin
VRC+ operation detection
voltage Given, the DC input voltage when the IC starts as
0 VIN(ON), the DC input voltage when the switching
ot
ns
reduce each applied voltage When Overcurrent Protection (OCP) is activated, the
C2 shown in Figure 8-26 is for reducing ripple output power is limited by detecting the drain current of
ig
voltage of detection voltage and making delay time. The the power MOSFET at pulse-by-pulse.
value of C2 is about 0.1 μF. The overcurrent is detected by the OC pin or the RC
es
The value of R1 to R4 and C2 should be selected pin. Figure 8-28 shows the peripheral circuit of the OC
D
based on actual operation in the application. pin and the RC pin.
When the Brown-in and Brown-out Function does not C11 is the bypass capacitor. Since C11 is smaller than
Ci, the detection current of ROCP becomes low. Thus, the
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be used, the detection resistance (R1, R2, R3, and R4) is
removed. C2 is for preventing malfunction caused by ROCP can reduce loss and be small resistor.
noise. The value of C2 is about 0.01 μF.
rN
Q(H)
16
VGH
R1 15 T1
fo
VAC U1 VS
R2 U1 Q(L) ID(H)
C1
d
11
VGL Cv
R3
1
de
VSEN Ci
10
R4 GND CSS OC RCRC COM
C2
en
4 GND 4 5 6 7 C11
m
R7
Figure 8-26. VSEN Pin Peripheral Circuit C8 ROCP
m
C7
C6
o
operation in the latch mode. When the VCC pin voltage cannot be calculated easy from the condition of the
is decreased to VCC(LA_OFF) = 8.2 V or less, the latch resonant power supply including input voltage and
N
account of both OCP and the capacitive mode 8.11 Overload Protection (OLP)
operation.
Figure 8-29 shows the FB pin peripheral circuit,
V OC ( L ) Figure 8-30 shows the FB pin waveform at Overload
R OCP ≒ Protection (OLP) operation.
C11 (17)
I D(H) × When the output power becomes overload state that
C11 + Ci the drain current is limited by Overcurrent Protection
(OCP) operation, the oscillation frequency increases.
● R7 and C7 are for high frequency noise reduction. When the oscillation frequency increases, the output
R7 is 100 Ω to 470 Ω. C7 is 100 pF to 1000 pF. voltage decreases and the current of the secondary
photo-coupler becomes zero. Thus, the feedback current
Table 8-1 shows the overcurrent detection voltage of flowing through the photo-coupler connected the FB pin
the OC pin and the RC pin, and the sink current of CSS becomes zero. As a result, C4 is charged by the FB Pin
Source Current IFB = − 25.5 μA, and the FB pin voltage
ns
pin. There are three OCP operations as follows:
increases. If the FB pin voltage increases to the FB Pin
Threshold Voltage VFB = 7.05 V, the IC stops switching
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1) Low Level OCP Detection
When the OC pin voltage becomes VOC(L) or more, C6 operation in the latch mode. When the VCC pin voltage
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connected to the CSS pin is discharged by the sink is decreased to VCC(LA_OFF) = 8.2 V or less or the VSEN
current ICSS(L). As a result, the oscillation frequency pin voltage is decreased to VSEN(OFF) = 1.16 V or less,
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increases, the output power is limited. the latch mode is released.
If the OC pin voltage decreases less than VOC(L) The stresses of the power MOSFET and the secondary
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during discharge of C6, the IC stops discharge of C6. side rectifier diode are reduced by OLP.
Given the time that until the FB pin voltage reaches to
2) High Level OCP Detection VFB as the OLP delay time, tDLY (refer to Figure 8-30).
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When the OC pin voltage becomes VOC(H) or more, C6 tDLY is calculated Equation (18).
is discharged by the sink current ICSS(H). Since ICSS(H) If R5 is 47 kΩ and C4 is 4.7 μF, tDLY becomes about
is eleven times of ICSS(L), the oscillation frequency 0.5 s.
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3) High Speed OCP Detection Where, IFB is the FB Pin Source Current − 25.5 μA.
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C5
ICSS(S). As a result, the oscillation frequency increases
at high speed, the output power is limited quickly. If
R
reducing the output power, the IC becomes the High Figure 8-29. FB Pin Peripheral Circuit
Speed OCP Detection and the Low Level OCP
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VFB=7.05V
Table 8-1. Overcurrent Detection Voltage and Sink
C7 is charged by -25.5µA
Current of CSS Pin
Detection CSS Pin
OCP Pins
Voltage Sink Current About 3V
The voltage of both end of
Low OC VOC(L) = 1.52 V ICSS(L) = 1.8 mA R1due to flowing -25.5µA
time
High OC VOC(H) = 1.83 V ICSS(H) = 20.0 mA Normal operation OLP opetation Latched shutdown
OC VOC(S) = 2.35 V
High OLP delay time, tDLY
VRC(S) = 2.35 V, ICSS(S) = 18.3 mA
Speed RC
– 2.35 V Figure 8-30. OLP Operation
ns
8.13 Thermal Shutdown (TSD) When the gate resistances are adjusted, the gate
waveforms should be checked that the dead time is
When the junction temperature of the IC reach to the
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ensured as shown in Figure 9-2.
Thermal Shutdown Temperature Tj(TSD) = 150 °C (min.),
Thermal Shutdown (TSD) is activated and the IC stops
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RB DS
switching operation in the latch mode. When the VCC Drain
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pin voltage is decreased to VCC(LA_OFF) = 8.2 V or less or Gate
the VSEN pin voltage is decreased to VSEN(OFF) = 1.16 V
or less, the latch mode is released. RA
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High-side
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● Input and Output Electrolytic Capacitor Low-side Dead time Dead time
m
ns
pin and the GND pin is recommended.
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4) Peripheral Components for the IC Control
These components should be placed close to the IC,
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Ci
and be connected to the IC pin as short as possible.
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Figure 9-3. High Frequency Current Loops (hatched 5) Bootstrap Circuit Components
areas) These components should be connected to the IC pin
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as short as possible, and the loop for these should be
In addition, the PCB circuit design should be taken
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account as follows:
Figure 9-4 shows the circuit design example. 6) Secondary side Rectifier Smoothing Circuit Trace
Layout
This is the trace of the rectifier smoothing loop,
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possible.
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D1 T1 D51
VCC NC
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2 17 Q(H)
C5 R8
Cf
C4 R5 FB VGH C51
3 16
R
SSC9522S
R6
(2)GND trace for IC PC1 GND VS
4 15
should be separate
ot
C10
C7 OC NC
6 13
D52
R7
U1
C8 RC NC
7 12
Q(L)
C9 REG VGL
8 11 Ci
C11
(4)Peripheral RV COM
components for IC ROCP 9 10
control should be
placed close to the IC
CRV
C12
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