IMPROVED LINE VOLTAGE ZERO-CROSSING DETECTION TECHNIQUES FOR PV

INVERTERS

Research student: T Abeyasekera

Supervisor: Dr. D J Atkinson

Abstract: This paper presents a comparison of two different zero-crossing detection techniques used in grid-
connected photovoltaic Inverters. The current controlled Inverter should be synchronised with the supply
grid to allow a steady power flow with a controlled power factor. The obvious and the most widely used
method is by using a zero crossing detector. This however, is prone to errors due to various distortions found
usually on the grid. A detailed grid distortion model is derived to be used for simulations. Two zero-crossing
techniques based on predictive filtering and Phase-locked loops are modelled and simulated for comparison.

I Introduction

Grid-connected Inverters require synchronising its II Grid voltage noise model

output current with the grid voltage. This is done
by generating a sinusoid of the same phase and Various non-linear loads connected to weak ac
frequency as of grid voltage. This is then used as a distribution systems contribute to Electromagnetic
reference to the PWM generator of the Inverter. pollution of the system. This includes harmonic
distortion, inter-harmonics, interference, flicker,
Currently a number of methods are in use. These commutation notches and dc component [1].
methods can be categorised in to three main groups
as follows: A test signal based on typical grid distortions
(Simulink model shown in fig 1) is simulated and
• Noise reduction in the distorted grid signal by shown in fig 2. The signal consists of a 50 Hz
adaptive or Predictive digital filtering sinusoid and its 3rd and 5th harmonic components,
• Use of Tracking filters (Phase Locked Loop which are the main harmonic components
techniques) encountered in the grid. The amplitudes of the 3rd
• Adaptive on-line Waveform reconstruction and 5th harmonics are set at 0.2 and 0.1
respectively, while the amplitude of the
The objective of a reliable zero-crossing detector fundamental is scaled to unity. The signal also
would be to track the in-phase fundamental contains a uniformly distributed white noise
component of the distorted grid signal, with the component, which depicts the high frequency noise
required dynamic response. An obvious obstacle to due to the edges of the switching in switching
this would be the noise content of the grid voltage power converters. [2]. A model to generate
signal. A detailed analysis was done and a model commutation notch type noise was developed. The
was developed to simulate grid supply distortions. model generates distortions with variable notch
This model has been used throughout to simulate depth (set to 1.5 times the line voltage amplitude)
different zero-crossing techniques under various and notch width. Notch width is set to 600 µs
types of distortions. [=6.(1/10 kHz)], which is reported to be a typical
This paper is divided in to three main parts. A grid value for commutation disturbances in PWM
voltage noise model is derived, modelled and Inverters [3].
simulated in part II. Section III and IV contains a
comparison of the first two techniques described
above. A statistical tool to measure accuracy of
zero crossing detection is designed and tested in
section IV.

1
 III Noise reduction in the distorted grid
signal - Design and simulation of a
Out1
predictive digital filter
voltage spike 2
IV Experimental results sin-out
Noise types described in sec. II, causes spurious
Fig2. Offset current drift of the sensor zero crossings at the output of the zero crossing
fundam ental detector (fig 4). This reduces the reliability of
supply grid phase detection and therefore makes
Scope the task of synchronising to the grid more difficult.
V.
3rd harm onic Conclusions and Further Work
The method described below is based on predictive
1
References digital filtering to minimise multiple zero crossings
signal+noise
caused by distortions in the grid. The filtered signal
5 th harmonic is then used to calculate the true phase and the
frequency of the grid signal. A sinusoidal signal
synthesised using this information, will serve as a
Noise
reference to the PWM generator of the Inverter. A
Time in secs simplified block diagram of the predictor is shown
in fig 3.
0.25
The Predictor is based on a Least Mean Square
dc offset (LMS) Adaptive filter, whose filter coefficients
change adaptively to reduce the error (in a Least
Mean Square sense) between the filter output and
the desired signal [5]. The predictive nature of the
algorithm guarantees zero phase shift between the
Fig 1 - Grid noise model in Simulink
grid and the filter output signal. The convergence
of the error is guaranteed only if the filter input
signal contains the noise component which is
uncorrelated with the desired signal. This condition
is achieved by delaying the noisy signal by one
sample (Z-1) before feeding in to the filter.

An IIR bandpass filter sampled at 100 HZ is used

to suppress the dc component of the distorted
signal. Phase shaping is used in designing this
filter to guarantee zero phase shift at the nominal
frequency.
Amplitude

Time in secs

Fig 2 -Typical distorted grid voltage signal, simulated

in Matlab using the grid voltage noise

2
 Signal + Noise

zero cross

zero cross

z-1 Predicted sine signal

signal+noise -1 In Out
z
z2+1.89627z+0.8989 nLMS
sin-out Err Taps
IIR Bandpass filter
grid-signal LMS
Noise model Adaptive Filter
predicted signal1

Sin + Noise1

Sine

Fig 3 - Simulink model of the predictive digital filter To work space

A - Simulation results

Time in secs

Fig 4 - Simulation results of a normalised distorted line voltage signal sample filtered through an adaptive
predictor

A clear improvement in zero crossing detection is to Implementation problems on a DSP

evident from the simulation results shown in fig 4. environment. Another disadvantage of this filter is
However the use of different sampling rates for its inability to attenuate commutation notches type
the IIR pre-filter and the LMS adaptive filter adds disturbances. A Median type filter used in cascade
is proposed in [1], for notch suppression.

3
 IV - Tracking filters - Phase Locked Loops
As seen from (1), a higher locking range requires
Another approach of improving zero crossing a higher bandwith (assuming ξ to be constant),
detection reliability is the use of tracking filters. which in contrary leaves the system vulnerable to
Tracking filters are basically, Phased Lock Loops high frequency noise. Since the closed loop
(PLL), designed to track the system could be modeled as a 2nd order system of
50 (+/- 2%) Hz grid voltage with required the type :
dynamic response. A survey of theoretical and
experimental work done on digital phase locked
loops (DPLL) was published by Lindsay et al. [4]. ω 2n
H ( s) = (2)
S 2 + 2.ζ .ω n .S + ω 2 n
Grid signal
Phase
Detector An optimum value for ξ (= 0.707) is found using
(PD) the Weiner optimisation criteria [1].
Low pass This guarantees the delicate trade-off between fast
filter (LPF) tracking and noise immunity of the PLL.

Voltage Another approach to this is to implement the PLL

Controlled with variable loop bandwidth (BL).
Oscillator In this method loop bandwidth will be a function
Output signal of the Lock In state of the PLL. In pre-lock state
BL will increased (by varying values of the low
pass filter) to accommodate quick Lock In. After
Fig 5 - Simplified block diagram of a PLL locking in to the signal BL will be restored to its
default, which will ensure noise imminuty of the
system.
The relative difference in phase is detected by the
PD and filtered through LPF to be fed in to
theVCO. The output of the VCO is a signal whose B - Simulation results
frequency is locked to the grid signal.
Robustness of the PLL is guranteed when the Design and simulation of a PLL has been done on
dynamic performance of the closed loop system Matlab / Simulink platform and results are shown
satisfies, both fast tacking and good filtering (low in fig 7 and fig 8.
pass) characteristics.However, both requirement
cannot be satisfied simultaneously, as they The model synthesises a sinusoid, tracking the
contradict each other. Hence a trade off is found phase and the frequency of a distorted grid. This
to optimise the filter’s performance. can then be directly used as a reference for the
Inverter PWM generator.
Lock in Range (∆ωL, given in (1)) is the the range
of frequencies where the PLL could lock in with
minimum time [6].

∆ωL ≈ 2*ξ*ωN (1)

where, ξ and ωN are damping factor and natural

frequency of resonance, of the system.

4
 signal+noise 1
0.42 26.2
0.04545s+1
gri d-signal
Phase detector Loop fil ter rad/Hz error/fi lter out

VCO

vco output

Fig 6 - Simulink model of a second order PLL

Frequency, Hz

Time in secs
Time in secs

Fig 7 - Simulation results Fig 8- Closed loop transient response of the

A - Input signal (50 Hz → 48 Hz) at t = 1sec PLL for a 2 Hz step change at t = 1 sec
B - PLL output waveform

V - Measuring the accuracy of zero-crossing the same frequency and phase. The misplacement
detection is measured in samples and put in to bins to give a
histogram output of the results.
The need for an efficient tool to measure the The algorithm is realised in Matlab m-code. Fig 9
accuracy of zero crossing detection has risen shows the results of the program run through
when comparing relative merits of different signal data obtained through simulation results of
techniques. The method proposed in this paper, sec. II (fig 4).
calculates misplacements of zero- crossings of a
given distorted signal, relative to an ideal signal of

5
 predicted signal zero crossing detection error PDF

probability density of zero crossings

0.8

0.6

0.4

0.2

0
-45 -40 -35 -30 -25 -20 -15 -10 -5 0
zero crossing detection error in samples

noisy signal zero crossing detection error PDF

probability density of zero crossings

0.35

0.3

0.25

0.2
0.15

0.1

0.05

0
-15 -10 -5 0 5 10 15
zero crossing detection error in samples

Fig 9 - Probability density functions of zero crossing detection error

VI - Conclusions

Models have been derived and simulated for two [2] Sami Valiviita, Zero-crossing detection of
different zero-crossing detection techniques. The distorted line voltages using 1-b
noise reduction approach based on Least Mean Measurements, IEEE trans. on Ind.
Square adaptive filtering requires different Electronics, vol. 46, No 5, pp917, October
sampling rates. Further, an additional block is 1999
needed to calculate the frequency and the phase
from the filter output. Hence the DSP [3] Kumar et al., A microprocessor-based dc
implementation of this will be computationally drive control scheme using predictive
intensive. On the contrary, the phase-locked loop Synchronisation, IEEE trans. on Ind.
approach has proved to be both simple and Electronics, vol. 40, No 4, pp445, August 1993
straightforward to implement.
Further work is continuing in this direction to [4] Lindsay W.C, Chak Ming Chie, A survey of
implement the Adaptive PLL algorithm in C digital phase-locked loops, proc. of IEEE, vol.
Language. This code can then be downloaded to 69, No 4, pp 410, April 1981
the TMS320C31 DSP for real-time zero-crossing
detection. A noise generator, based on the model [5] Widrow B, Stearns S.D, Adaptive Signal
described in sec.II, will be will be developed Processing, Prientice-Hall Int., Inc, 1985
combining the DSP and a power amplifier.
[6] Roland E. Best, Phase-locked loops -
Design, Simulation and Applications, McGraw
References -Hill, 1997

[1] Olli Vainio, S.J Ovaska, Digital filtering

for robust 50/60 Hz zero-crossing detectors,
IEEE trans. on Instrumentation and
measurement, vol. 45, No2, pp426, April 1995