Opcode Operand Description

MOV Rd, Rs This instruction copies the contents of the source register
Copy from M, Rs into the destination; the contents of the source register are
source to Rd, M not altered. If one of the operands is a memory location, its
destination location is specified by the contents of the HL registers.
Example: MOV B, C or MOV B, M
MVI Rd, data The 8-bit data is stored in the destination register or
Move immediate M, data memory. If the operand is a memory location, its location
8-bit is specified by the contents of the HL registers.
Example: MVI B, 57H or MVI M, 57H
LDA 16-bit address The contents of a memory location, specified by a 16-bit
Load address in the operand, are copied to the accumulator. The
accumulator contents of the source are not altered.
Example: LDA 2034H
LDAX B/D Reg. pair The contents of the designated register pair point to a
Load memory location. This instruction copies the contents of
accumulator that memory location into the accumulator. The contents of
indirect either the register pair or the memory location are not
altered.
Example: LDAX B
LXI Reg. pair, 16- The instruction loads 16-bit data in the register pair
Load register bit data designated in the operand.
pair immediate Example: LXI H, 2034H or LXI H, XYZ
LHLD 16-bit address The instruction copies the contents of the memory location
Load H and L pointed out by the 16-bit address into register L and copies
registers direct the contents of the next memory location into register H.
The contents of source memory locations are not altered.
Example: LHLD 2040H
STA 16-bit address The contents of the accumulator are copied into the
Store memory location specified by the operand. This is a 3-byte
accumulator instruction, the second byte specifies the low-order address
direct and the third byte specifies the high-order address.
Example: STA 4350H
STAX Reg. pair The contents of the accumulator are copied into the
Store memory location specified by the contents of the operand
accumulator (register pair).The contents of the accumulator are not
indirect altered.
Example: STAX B
SHLD 16-bit address The contents of register L are stored into the memory
Store H and L location specified by the 16-bit address in the operand and
registers direct the contents of H register are stored into the next memory
location by incrementing the operand. The contents of
registers HL are not altered. This is a 3-byte instruction,
the second byte specifies the low-order address and the
third byte specifies the high-order address.
Example: SHLD 2470H
XCHG none The contents of register H are exchanged with the contents
Exchange H and of register D, and the contents of register L are exchanged
L with D and E with the contents of register E.
Example: XCHG
SPHL none The instruction loads the contents of the H and L registers
Copy H and L into the stack pointer register, the contents of the H register
registers to the provide the high-order address and the contents of the L
stack pointer register provide the low-order address. The contents of the
H and L registers are not altered.
Example: SPHL
XTHL none The contents of the L register are exchanged with the stack
Exchange H and location pointed out by the contents of the stack pointer
L with top of register. The contents of the H register are exchanged with
stack the next stack location (SP+1); however, the contents of
the stack pointer register are not altered.
Example: XTHL
PUSH Reg. pair The contents of the register pair designated in the operand
Push register pair are copied onto the stack in the following sequence. The
onto stack stack pointer register is decremented and the contents of
the high-order register (B, D, H, A) are copied into that
 location. The stack pointer register is decremented again
and the contents of the low-order register (C, E, L, flags)
are copied to that location.
Example: PUSH B or PUSH A
POP Reg. pair The contents of the memory location pointed out by the
Pop off stack to stack pointer register are copied to the low-order register
register pair (C, E, L, status flags) of the operand. The stack pointer is
incremented by 1 and the contents of that memory location
are copied to the high-order register (B, D, H, A) of the
operand. The stack pointer register is again incremented by
1.
Example: POP H or POP A
OUT 8-bit port The contents of the accumulator are copied into the I/O
Output data from address port specified by the operand.
accumulator to a Example: OUT F8H
port with 8-bit
address

IN 8-bit port The contents of the input port designated in the operand
Input data to address are read and loaded into the accumulator.
accumulator Example: IN 8CH
from a port with
8-bit address

2. Arithmetic Instructions
Opcode Operand Description
ADD R The contents of the operand (register or memory) are added to
Add register or M the contents of the accumulator and the result is stored in the
memory to accumulator. If the operand is a memory location, its location
accumulator is specified by the contents of the HL registers. All flags are
modified to reflect the result of the addition.
Example: ADD B or ADD M
ADC R The contents of the operand (register or memory) and the
Add register to M Carry flag are added to the contents of the accumulator and
accumulator the result is stored in the accumulator. If the operand is a
with carry memory location, its location is specified by the contents of
the HL registers. All flags are modified to reflect the result of
the addition.
Example: ADC B or ADC M
ADI 8-bit data The 8-bit data (operand) is added to the contents of the
Add immediate accumulator and the result is stored in the accumulator. All
to accumulator flags are modified to reflect the result of the addition.
Example: ADI 45H
ACI 8-bit data The 8-bit data (operand) and the Carry flag are added to the
Add immediate contents of the accumulator and the result is stored in the
to accumulator accumulator. All flags are modified to reflect the result of the
with carry addition.
Example: ACI 45H
DAD Reg. pair The 16-bit contents of the specified register pair are added to
Add register the contents of the HL register and the sum is stored in the HL
pair to H and L register. The contents of the source register pair are not
registers altered. If the result is larger than 16 bits, the CY flag is set.
No other flags are affected.
Example: DAD H
SUB R The contents of the operand (register or memory) are
Subtract M subtracted from the contents of the accumulator, and the result
register or is stored in the accumulator. If the operand is a memory
memory from location, its location is specified by the contents of the HL
accumulator registers. All flags are modified to reflect the result of the
subtraction.
Example: SUB B or SUB M
SBB R The contents of the operand (register or memory) and the
Subtract source M Borrow flag are subtracted from the contents of the
and borrow accumulator and the result is placed in the accumulator. If the
from operand is a memory location, its location is specified by the
accumulator contents of the HL registers. All flags are modified to reflect
 the result of the subtraction.
Example: SBB B or SBB M
SUI 8-bit data The 8-bit data (operand) is subtracted from the contents of the
Subtract accumulator and the result is stored in the accumulator. All
immediate flags are modified to reflect the result of the subtraction.
from Example: SUI 45H
accumulator

SBI 8-bit data The 8-bit data (operand) and the Borrow flag are subtracted
Subtract from the contents of the accumulator and the result is stored in
immediate the accumulator. All flags are modified to reflect the result of
from the subtraction. Example: SBI 45H
accumulator
with borrow

INR R The contents of the designated register or memory) are

Increment M incremented by 1 and the result is stored in the same place. If
register or the operand is a memory location, its location is specified by
memory by 1 the contents of the HL registers.
Example: INR B or INR M
INX R The contents of the designated register pair are incremented
Increment by 1and the result is stored in the same place.
register pair by Example: INX H
1

DCR R The contents of the designated register or memory are

Decrement M decremented by 1 and the result is stored in the same place. If
register or the operand is a memory location, its location is specified by
memory by 1 the contents of the HL registers.
Example: DCR B or DCR M
DCX R The contents of the designated register pair are decremented
Decrement by 1and the result is stored in the same place.
register pair by Example: DCX H
1
DAA none The contents of the accumulator are changed from a binary
Decimal adjust value to two 4-bit binary coded decimal (BCD) digits. This is
accumulator the only instruction that uses the auxiliary flag to perform the
binary to BCD conversion, and the conversion procedure is
described below. S, Z, AC, P, CY flags are altered to reflect
the results of the operation.

If the value of the low-order 4-bits in the accumulator is

greater than 9 or if AC flag is set, the instruction adds 6 to the
low-order four bits.
If the value of the high-order 4-bit in the accumulator is
greater than 9 or if the Carry flag is set, the instruction adds 6
to the high-order four bits.
Example: DAA

3. Branching Instructions
Opcode Operand Description
JMP 16-bit address The program sequence is transferred to the memory location
Jump specified by the 16-bit address given in the operand.
unconditionally Example: JMP 2034H or JMP XYZ
The program sequence is transferred to the memory location
16-bit address specified by the 16-bit address given in the operand based on
Jump the specified flag of the PSW as described below.
conditionally Example: JZ 2034H or JZ XYZ

Opcode Description Flag Status

JC Jump on Carry CY = 1
JNC Jump on no Carry CY = 0
JP Jump on positive S=0
JM Jump on minus S=1
JZ Jump on zero Z=1
 JNZ Jump on no zero Z=0
JPE Jump on parity even P=1
JPO Jump on parity odd P=0

Opcode Operand Description

CALL 16-bit address The program sequence is transferred to the memory location
Unconditional specified by the 16-bit address given in the operand. Before
subroutine call the transfer, the address of the next instruction after CALL
(The contents of the program counter) is pushed onto the
stack.
Example: CALL 2034H or CALL XYZ
Call 16-bit address The program sequence is transferred to the memory location
conditionally specified by the 16-bit address given in the operand based on
the specified flag of the PSW as described below. Before the
transfer, the address of the next instruction after the call (the
contents of the program counter) is pushed onto the stack.
Example: CZ 2034H or CZ XYZ

Opcode Description Flag Status

CC Call on Carry CY = 1
CNC Call on no Carry CY = 0
CP Call on positive S=0
CM Call on minus S=1
CZ Call on zero Z=1
CNZ Call on no zero Z=0
CPE Call on parity even P=1
CPO Call on parity odd P=0

Opcode Operand Description

RET none The program sequence is transferred from the subroutine to
Return from the calling program. The two bytes from the top of the stack
subroutine are copied into the program counter, and program execution
unconditionally begins at the new address.
Example: RET
The program sequence is transferred from the subroutine to
Return from none the calling program based on the specified flag of the PSW as
subroutine described below. The two bytes from the top of the stack are
conditionally copied into the program counter, and program execution
begins at the new address.
Example: RZ

Opcode Description Flag Status

RC Return on Carry CY = 1
RNC Return on no Carry CY = 0
RP Return on positive S=0
RM Return on minus S=1
RZ Return on zero Z=1
RNZ Return on no zero Z=0
RPE Return on parity even P=1
RPO Return on parity odd P=0

Opcode Operand Description

PCHL none The contents of registers H and L are copied into the
Load program program counter. The contents of H are placed as the high-
counter with HL order byte and the contents of L as the low-order byte.
contents Example: PCHL
The RST instruction is equivalent to a 1-byte call instruction
RST 0-7 to one of eight memory locations depending upon the
Restart number.
The instructions are generally used in conjunction with
interrupts and inserted using external hardware. However
these can be used as software instructions in a program to
transfer program execution to one of the eight locations. The
 addresses are:
Instruction Restart Address
RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
The 8085 has four additional interrupts and these interrupts
generate RST instructions internally and thus do not require
any external hardware. These instructions and their Restart
addresses are:
Interrupt Restart Address
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

4. Logical Instructions
Opcode Operand Description
CMP R The contents of the operand (register or memory) are
Compare M compared with the contents of the accumulator. Both
register or contents are preserved.
memory with The result of the comparison is shown by setting the flags of
accumulator the PSW as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
 Example: CMP B or CMP M
CPI 8-bit data The second byte (8-bit data) is compared with the contents
Compare of the accumulator. The values being compared remain
immediate with unchanged. The result of the comparison is shown by setting
accumulator the flags of the
PSW as follows:
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
Example: CPI 89H
ANA R The contents of the accumulator are logically ANDed with
Logical AND M the contents the of the operand (register or memory), and the
register or result is placed in the accumulator. If the operand is a
memory with memory location, its address is specified by the contents of
accumulator HL registers.
S, Z, P are modified to reflect the result of the operation. CY
is reset. AC is set.
Example: ANA B or ANA M
ANI 8-bit data The contents of the accumulator are logically ANDed with
Logical AND the 8-bit data (operand) and the result is placed in the
immediate with accumulator.
accumulator S, Z, P are modified to reflect the result of the operation. CY
is reset. AC is set. Example: ANI 86H
XRA R The contents of the accumulator are Exclusive ORed with
Exclusive OR M the contents of the operand (register or memory), and the
register or result is placed in the accumulator. If the operand is a
memory with memory location, its address is specified by the contents of
accumulator HL registers.
S, Z, P are modified to reflect the result of the operation. CY
and AC are reset.
Example: XRA B or XRA M
XRI 8-bit data The contents of the accumulator are Exclusive ORed with
Exclusive OR the 8-bit data (operand) and the result is placed in the
immediate with accumulator.
accumulator S, Z, P are modified to reflect the result of the operation. CY
and AC are reset.
Example: XRI 86H
ORA R The contents of the accumulator are logically ORed with the
Logical OR M contents of the operand (register or memory), and the result
register or is placed in the accumulator. If the operand is a memory
memory with location, its address is specified by the contents of HL
accumulator registers.
S, Z, P are modified to reflect the result of the operation. CY
and AC are reset.
Example: ORA B or ORA M
ORI 8-bit data The contents of the accumulator are logically ORed with the
Logical OR 8-bit data (operand) and the result is placed in the
immediate with accumulator.
accumulator S, Z, P are modified to reflect the result of the operation.
CY and AC are reset.
Example: ORI 86H
RLC none Each binary bit of the accumulator is rotated left by one
Rotate position. Bit D7 is placed in the position of D0 as well as in
accumulator left the Carry flag. CY is modified according to bit D7. S, Z, P,
AC are not affected.
Example: RLC
RRC none Each binary bit of the accumulator is rotated right by one
Rotate position. Bit D0 is placed in the position of D7 as well as in
accumulator the Carry flag. CY is modified according to bit D0. S, Z, P,
right AC are not affected.
Example: RRC
RAL none Each binary bit of the accumulator is rotated left by one
Rotate position through the Carry flag. Bit D7 is placed in the
accumulator left Carry flag, and the Carry flag is placed in the least
through carry significant position D0. CY is modified according to bit D7.
S, Z, P, AC are not affected.
 Example: RAL
RAR none Each binary bit of the accumulator is rotated right by one
Rotate position
accumulator through the Carry flag. Bit
right through D0 is placed in the Carry flag, and the Carry flag is placed
carry in the most significant position D7. CY is modified
according to bit D0. S, Z, P, AC are not affected.
Example: RAR
CMA none The contents of the accumulator are complemented. No
Complement flags are affected.
accumulator Example: CMA
CMC none The Carry flag is complemented. No other flags are
Complement affected.
carry Example: CMC
STC none The Carry flag is set to 1. No other flags are affected.
Set Carry Example: STC

Opcode Operand Description

NOP none No operation is performed. The instruction is fetched and
No operation decoded. However no operation is executed.
Example: NOP
HLT none The CPU finishes executing the current instruction and halts
Halt and enter any further execution. An interrupt or reset is necessary to exit
wait state from the halt state.
Example: HLT
DI none The interrupt enable flip-flop is reset and all the interrupts
Disable except the TRAP are disabled. No flags are affected.
interrupts Example: DI
EI none The interrupt enable flip-flop is set and all interrupts are
Enable enabled. No flags are affected. After a system reset or the
interrupts acknowledgement of an interrupt, the interrupt enable flip-
flop is reset, thus disabling the interrupts. This instruction is
necessary to re-enable the interrupts (except TRAP).
Example: EI