Microprocessor & Microcontroller

UPCIE501

Course Notes prepared and compiled

By

Ananya Dastidar
Assistant Professor
Department of Instrumentation and Electronics Engineering

For

B.Tech., Fifth Semester

As per
CET, Bhubaneswar (Autonomous) Syllabus

DEPARTMENT OF INSTRUMENTATION AND ELECTRONICS ENGINEERING

(Specialization in SIGNAL PROCESSING ENGINEERING)
COLLEGE OF ENGINEERING AND TECHNOLOGY, BHUBANESWAR (AUTONOMOUS)
Academic Session, 2020-21

1| UPCIE501 Microprocessor & Microcontroller Module I

 Module I
(Microprocessor)

2| UPCIE501 Microprocessor & Microcontroller Module I

Lecture 3

INSTRCTION SET OF 8085

The instruction set of 8085 microprocessor is classified into the following types.
Data Transfer Instruction
Arithmetic Instructions
Logical Instructions
Branching Instructions
Control Instructions

Data Transfer Instructions

These instructions are used to transfer information from/ to memory or I/O device to/ from the
processor.
Opcode Operand Description
This instruction copies the contents of the source register into the
Copy from source to destination destination register; the contents of the source register are not
MOV Rd, Rs altered. If one of the operands is a memory location, its location is
MOV M, Rs specified by the contents of the HL registers.
MOV Rd, M Example: MOV B, C or MOV B, M

The 8-bit data is stored in the destination register or memory. If

Move immediate 8-bit
the operand is a memory location, its location is specified by the
MVI Rd, data
contents of the HL registers.
MVI M, data
Example: MVI B, 57H or MVI M, 57H
The contents of a memory location, specified by a
Load accumulator 16-bit address in the operand, are copied to the accumulator. The
LDA 16-bit address contents of the source are not altered.
Example: LDA 2034H
The contents of the designated register pair point to a memory
location. This instruction copies the contents of that memory
Load accumulator indirect
location into the accumulator. The contents of either the register
LDAX B/D Reg. pair
pair or the memory location are not altered.
Example: LDAX B
The instruction loads 16-bit data in the register pair designated in
Load register pair immediate
the operand.
LXI Reg. pair, 16-bit data
Example: LXI H, 2034H or LXI H, XYZ
The instruction copies the contents of the memory location pointed
out by the 16-bit address into register L and copies the contents of
Load H and L registers direct
the next memory location into register H. The contents of source
LHLD 16-bit address
memory locations are not altered.
Example: LHLD 2040H
The contents of the accumulator are copied into the memory
location specified by the operand. This is a 3-byte instruction, the
Store accumulator direct
second byte specifies the low-order address and the third byte
STA 16-bit address
specifies the high-order address.
Example: STA 4350H

3| UPCIE501 Microprocessor & Microcontroller Module I

 The contents of the accumulator are copied into the memory
Store accumulator indirect location specified by the contents of the operand (register
STAX Reg. pair pair). The contents of the accumulator are not altered.
Example: STAX B
The contents of register L are stored into the memory location
specified by the 16-bit address in the operand and the contents of H
register are stored into the next memory location by incrementing
Store H and L registers direct
the operand. The contents of registers HL are not altered. This is a
SHLD 16-bit address
3-byte instruction, the second byte specifies the low-order address
and the third byte specifies the high-order address.
Example: SHLD 2470H
The contents of register H are exchanged with the contents of
Exchange H and L with D and E register D, and the contents of register L are exchanged with the
XCHG none contents of register E.
Example: XCHG
The instruction loads the contents of the H and L registers into the
Copy H and L registers to the stack pointer register, the contents of the H register provide the
stack pointer high-order address and the contents of the L register provide the
SPHL none low-order address. The contents of the H and L registers are not
altered. Example: SPHL
The contents of the L register are exchanged with the stack
Exchange H and L with top of location pointed out by the contents of the stack pointer
stack register. The contents of the H register are exchanged with the
next stack location (SP+1); however, the contents of the stack
XTHL none
pointer register are not altered.
Example: XTHL
The contents of the register pair designated in the operand are
copied onto the stack in the following sequence. The stack pointer
register is decremented and the contents of the highorder register
Push register pair onto stack
(B, D, H, A) are copied into that location. The stack pointer
PUSH Reg. pair
register is decremented again and the contents of the low-order
register (C, E, L, flags) are copied to that location.
Example: PUSH B or PUSH H
The contents of the memory location pointed out by the stack
pointer register are copied to the low-order register (C, E, L, status
flags) of the operand. The stack pointer is incremented by 1 and
Pop off stack to register pair
the contents of that memory location are copied to the high-order
POP Reg. pair
register (B, D, H, A) of the operand. The stack pointer register is
again incremented by 1.
Example: POP H or POP B
Output data from accumulator The contents of the accumulator are copied into the I/O port
to a port with 8-bit address specified by the operand.
OUT 8-bit port address Example: OUT 80H
Input data to accumulator from The contents of the input port designated in the operand are read
a port with 8-bit address and loaded into the accumulator.
IN 8-bit port address Example: IN 81H

4| UPCIE501 Microprocessor & Microcontroller Module I

Arithmetic Instructions
These instructions are used to perform Arithmetic instructions.
Op-code Operand Description
The contents of the operand (register or memory) are
added to the contents of the Accumulator and the result is
Add register or memory to
stored in the accumulator. If the operand is a memory
accumulator
location, its location is specified by the contents of the
ADD R
HL registers. All flags are modified to reflect the result
ADD M
of the addition.
Example: ADD B or ADD M
The contents of the operand (register or memory) and the
Carry flag are added to the contents of the accumulator
Add register to accumulator with carry and the result is stored in the accumulator. If the operand
ADC R is a memory location, its location is specified by the
ADC M contents of the HL registers. All flags are modified to
reflect the result of the addition.
Example: ADC B or ADC M
The 8-bit data (operand) is added to the contents of the
accumulator and the result is stored in the
Add immediate to accumulator
accumulator. All flags are modified to reflect the result
ADI 8-bit data
of the addition.
Example: ADI 45H
The 8-bit data (operand) and the Carry flag are added to
Add immediate to accumulator with the contents of the accumulator and the result is stored in
carry the accumulator. All flags are modified to reflect the
ACI 8-bit data result of the addition.
Example: ACI 45H
The 16-bit contents of the specified register pair are
added to the contents of the HL register and the sum
Add register pair to H and L registers is stored in the HL register. The contents of the source
DAD Reg. pair register pair are not altered. If the result is larger than 16
bits, the CY flag is set. No other flags are affected.
Example: DAD H
The contents of the operand (register or memory) are
subtracted from the contents of the accumulator, and the
Subtract register or memory from result is stored in the accumulator. If the operand is a
accumulator memory location, its location is specified by the contents
SUB R of the HL registers. All flags are modified to reflect the
result of the subtraction.
Example: SUB B or SUB M
The contents of the operand (register or memory ) and
M the Borrow flag are subtracted from the contents of the
accumulator and the result is placed in the
Subtract source and borrow from
accumulator. If the operand is a memory location, its
accumulator
location is specified by the contents of the HL
SBB R
registers. All flags are modified to reflect the result of
the subtraction.
Example: SBB B or SBB M
5| UPCIE501 Microprocessor & Microcontroller Module I
 The 8-bit data (operand) is subtracted from the contents
of the accumulator and the result is stored in the
Subtract immediate from accumulator
accumulator. All flags are modified to reflect the result
SUI 8-bit data
of the subtraction.
Example: SUI 45H
The 8-bit data (operand) and the Borrow flag are
Subtract immediate from accumulator subtracted from the contents of the accumulator and the
with borrow result is stored in the accumulator. All flags are modified
SBI 8-bit data to reflect the result of the subtracion.
Example: SBI 45H
The contents of the designated register or memory) are
Increment register or memory by 1 incremented by 1 and the result is stored in the same
INR R place. If the operand is a memory location, its location is
INR M specified by the contents of the HL registers.
Example: INR B or INR M
The contents of the designated register pair are
Increment register pair by 1 incremented by 1 and the result is stored in the same
INX R place.
Example: INX H
The contents of the designated register or memory are
Decrement register or memory by 1 decremented by 1 and the result is stored in the same
DCR R place. If the operand is a memory location, its location is
DCR M specified by the contents of the HL registers.
Example: DCR B or DCR M
The contents of the designated register pair are
Decrement register pair by 1 decremented by 1 and the result is stored in the same
DCX R place.
Example: DCX H
The contents of the accumulator are changed from a
binary
value to two 4-bit binary coded decimal (BCD)
digits. This is the only instruction that uses the auxiliary
flag to perform the binary to BCD conversion. All flags -
S, Z, AC, P, CY are altered to reflect the results of the
Decimal adjust accumulator
operation. If the value of the low-order 4-bits in the
DAA none
accumulator is greater than 9 or if AC flag is set, the
instruction adds 6 to the low-order four bits. If the value
of the high-order 4-bits in the accumulator is greater than
9 or if the Carry flag is set, the instruction adds 6 to the
high-order four bits.
Example: DAA

21| UPCIE501 Microprocessor & Microcontroller Module I

Logical Instructions
These instructions are used to perform logical operations on data.
Opcode Operand Description

The contents of the operand (register or memory) are

compared with the contents of the accumulator. Both
contents are preserved.
Compare register or memory with
The result of the comparison is shown by setting the
accumulator
flags of the PSW as follows:
CMP R
if (A) < (reg/mem): carry flag is set
CMP M
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
Example: CMP B or CMP M
The second byte (8-bit data) is compared with the
contents of the accumulator. The values being
compared remain unchanged. The result of the
comparison is shown by setting the flags of the PSW as
Compare immediate with accumulator
follows:
CPI 8-bit data
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
Example: CPI 89H
The contents of the accumulator are logically ANDed
with the contents of the operand (register or memory),
Logical AND register or memory with and the result is placed in the accumulator. If the
accumulator operand is a memory location, its address is specified
ANA R by the contents of HL registers. S, Z, P are modified to
ANA M reflect the result of the operation. CY is reset. AC is
set.
Example: ANA B or ANA M
The contents of the accumulator are logically ANDed
with the 8-bit data (operand) and the result is placed in
Logical AND immediate with accumulator
the accumulator. S, Z, P are modified to reflect the
ANI 8-bit data
result of the operation. CY is reset. AC is set.
Example: ANI 86H
The contents of the accumulator are Exclusive ORed
with the contents of the operand (register or memory),
Exclusive OR register or memory with and the result is placed in the accumulator. If the
accumulator operand is a memory location, its address is specified
XRA R by the contents of HL registers. S, Z, P are modified to
XRA M reflect the result of the operation. CY and AC are
reset.
Example: XRA B or XRA M
The contents of the accumulator are Exclusive ORed
with the 8-bit data (operand) and the result is placed in
Exclusive OR immediate with accumulator
the accumulator. S, Z, P are modified to reflect the
XRI 8-bit data
result of the operation. CY and AC are reset.
Example: XRI 86H

22| UPCIE501 Microprocessor & Microcontroller Module I

 The contents of the accumulator are logically ORed
with the contents of the operand (register or memory),
Logical OR register or memory with and the result is placed in the accumulator. If the
accumulator operand is a memory location, its address is specified
ORA R by the contents of HL registers. S, Z, P are modified to
ORA M reflect the result of the operation. CY and AC are
reset.
Example: ORA B or ORA M
Logical OR immediate data with The contents of the accumulator are logically ORed
accumulator with the 8-bit data (operand) and the result is placed in
ORI 8-bit data the accumulator. S, Z, P are modified to reflect the
result of the operation. CY and AC are reset.
Example: ORI 86H
Each binary bit of the accumulator is rotated left by
one position. Bit D7 is placed in the position of D0 as
Rotate accumulator left
well as in the Carry flag. CY is modified according to
RLC none
bit D7. S, Z, P, AC are not affected.
Example: RLC

Rotate accumulator left (RLC)

Accumulator
CY D7 D6 D5 D4 D3 D2 D1 D0

Before Execution

D7 D6 D5 D4 D3 D2 D1 D0 D7

After Execution

If A=44H, CY=1 before execution what will be the value of A and carry bit of flag register after
execution.

Rotate accumulator right Each binary bit of the accumulator is rotated right by
RRC none one position. Bit D0 is placed in the position of D7 as
well as in the Carry flag. CY is modified according to
bit D0. S, Z, P, AC are not affected.
Example: RRC

Rotate accumulator right (RRC)

Accumulator
D7 D6 D5 D4 D3 D2 D1 D0 CY

Before Execution
23| UPCIE501 Microprocessor & Microcontroller Module I
 D0 D7 D6 D5 D4 D3 D2 D1 D0

After Execution

If A=44H, CY=1 before execution what will be the value of A and carry bit of flag register after
execution.

Each binary bit of the accumulator is rotated left by

Rotate accumulator left through carry one position through the Carry flag. Bit D7 is placed
in the Carry flag, and the Carry flag is placed in the
RAL none
least significant position D0. CY is modified
according to bit D7. S, Z, P, AC are not affected.
Example: RAL

Rotate accumulator left through carry (RAL)

Accumulator
CY D7 D6 D5 D4 D3 D2 D1 D0

Before Execution

D7 D6 D5 D4 D3 D2 D1 D0 CY

After Execution

If A=44H, CY=1 before execution what will be the value of A and carry bit of flag register after
execution.
Each binary bit of the accumulator is rotated right by
one position through the Carry flag. Bit D0 is placed
Rotate accumulator right through carry in the Carry flag, and the Carry flag is placed in the
RAR none most significant position D7. CY is modified
according to bit D0. S, Z, P, AC are not affected.
Example: RAR

Rotate accumulator right through carry (RAR)

Accumulator
D7 D6 D5 D4 D3 D2 D1 D0 CY

Before Execution

24| UPCIE501 Microprocessor & Microcontroller Module I

 CY D7 D6 D5 D4 D3 D2 D1 D0

After Execution
If A=44H, CY=1 before execution what will be the value of A and carry bit of flag register after
execution.
The contents of the accumulator are
Complement accumulator
Complemented. No flags are
CMA none
affected. Example: CMA
The Carry flag is complemented. No other flags are
Complement carry
Affected.
CMC none
Example: CMC
Set Carry The Carry flag is set to 1. No other flags are affected.
STC none Example: STC

Branching Instructions
These instructions are used to access subroutines or do implement loop.
Opcode Operand Description
Jump unconditionally The program sequence is transferred to the memory location
JMP 16-bit address specified by the 16-bit address given in the operand.
Example: JMP 76ADH
Jump conditionally
Jump Opcode XXXXH
XXXX16-bit Address
Opcode Description Flag Status
JC XXXXH Jump on Carry CY = 1 The program sequence is transferred to the memory location
JNC XXXXH Jump on no Carry CY = 0 specified by the 16-bit address given in the operand based on
JP XXXXH Jump on positive S = 0 the specified flag of the PSW as described below.
JM XXXXH Jump on minus S = 1 Example: JZ DEDB H
JZ XXXXH Jump on zero Z=1
JNZ XXXXH Jump on no zero Z=0
JPE XXXXH Jump on parity even P=1
JPO XXXXH Jump on parity odd P=0
The program sequence is transferred to the memory location
specified by the 16-bit address given in the operand. Before
Unconditional subroutine call
the transfer, the address of the next instruction after CALL
CALL opcode 16-bit address
(the contents of the program counter) is pushed onto the stack.
Example: CALL 4522H
Conditional subroutine call
XXXX16-bit address The program sequence is transferred to the memory location
Opcode Description Flag Status specified by the 16-bit address given in the operand based on
CC XXXXH Call on Carry CY = 1 the specified flag of the PSW as described below. Before the
CNC XXXXH Call on no Carry CY = 0 transfer, the address of the next instruction after the call (the
CP XXXXH Call on positive S = 0 contents of the program counter) is pushed onto the stack.
CM XXXXH Call on minus S = 1 Example: CZ 5566H
CZ XXXXH Call on zero Z=1

25| UPCIE501 Microprocessor & Microcontroller Module I

CNZ XXXXH Call on no zero Z=0
CPE XXXXH Call on parity even P = 1
CPO XXXXH Call on parity odd P = 0

The program sequence is transferred from the subroutine to

Return from subroutine unconditionally the calling program. The two bytes from the top of the stack
are copied into the program counter, and program execution
RET none begins at the new address.
Example: RET
Return from subroutine conditionally
Operand: none
Opcode Description Flag Status
The program sequence is transferred from the subroutine to
RC Return on Carry CY = 1
the calling program based on the specified flag of the PSW as
RNC Return on no Carry CY = 0
described below. The two bytes from the top of the stack are
RP Return on positive S=0
copied into the program counter, and program execution
RM Return on minus S=1
begins at the new address.
RZ Return on zero Z=1
Example: RZ
RNZ Return on no zero Z=0
RPE Return on parity even P = 1
RPO Return on parity odd P = 0
The contents of registers H and L are copied into the program
Load program counter with HL contents counter. The contents of H are placed as the high-order byte
PCHL and the contents of L as the low-order byte.
Example: PCHL
Restart
RST n
Instruction Restart Address
RST 0 0000H The RST instruction is equivalent to a 1-byte call instruction
RST 1 0008H to one of eight memory locations depending upon the number.
RST 2 0010H The instructions are generally used in conjunction with
RST 3 0018H interrupts and inserted using external hardware. However
RST 4 0020H these can be used as software instructions in a program to
RST 5 0028H transfer program execution to one of the eight locations.
RST 6 0030H
RST 7 0038H The 8085 has four additional interrupts and these interrupts
Interrupt Restart Address generate RST instructions internally and thus do not require
TRAP 0024H any external hardware.
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

26| UPCIE501 Microprocessor & Microcontroller Module I

Control Instructions
These instructions are used for control operations.

Opcode Operand Description

No operation No operation is performed. The instruction is fetched
NOP none and decoded. However no operation is executed. Example: NOP
Halt and enter wait state The CPU finishes executing the current instruction and halts any
HLT none further execution. An interrupt or reset is necessary to exit from the
halt state. Example: HLT
Disable interrupts The interrupt enable flip-flop is reset and all the interrupts except
DI none the TRAP are disabled. No flags are affected. Example: DI
The interrupt enable flip-flop is set and all interrupts are enabled.
No flags are affected. After a system reset or the acknowledgement
of an interrupt, the interrupt enable flipflop is reset, thus disabling the
interrupts. This instruction is necessary to reenable the interrupts
(except TRAP).
Enable interrupts Example:
EI none EI
This is a multipurpose instruction used to read the status of
interrupts
7.5, 6.5, 5.5 and read serial data input bit. The instruction loads
eight bits in the accumulator with the following interpretations.
D7 D6 D5 D4 D3 D2 D1 D0
SID I7 I6 I5 IE 7.5 6.5 5.5
Read interrupt mask
D7=serial input data bit
RIM none
D6, D5, D4=interrupts pending if bit=1
D3=interrupt enable; flip-flop is set if bit=1
D2, D1, D0=interrupt masked if bit=1
Example 49H = 0 1 0 0 1 0 0 1
RST 7.5 is pending.
Interrupt enable flip-flop is set
RST 7.5 and 6.5 are enabled. RST 5.5
masked. Example: RIM

27| UPCIE501 Microprocessor & Microcontroller Module I

 This is a multipurpose instruction and used to implement the 8085
interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the
accumulator contents as follows.
D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE xxx R7.5 MSE M7.5 M6.5 M5.5
D7=serial output data
D6=serial data enable (1=enable and 0=disable)
D4=if 1, reset RST 7.5 flip-flop
D3=if 1, mask set enable
D2, D1, D0=masks interrupts if bits=1
Set interrupt mask SOD – Serial Output Data: Bit D7 of the accumulator is latched into the SOD
SIM none output line and made available to a serial peripheral if bit D6=1. SDE – Serial
Data Enable: If this bit = 1, it enables the serial output. To implement serial
output, this bit needs to be enabled.
XXX – Don‟t care.
R7.5 – Reset RST 7.5: If this bit = 1, RST 7.5 flip-flop is reset. This is an
additional control to reset RST 7.5.
MSE – Mask Set Enable: If this bit is high, it enables the functions of
bits D2, D1, D0. This is a master control over all the interrupt masking bits. If
this bit is low, bits D2, D1, and D0 do not have any effect on the masks.
M7.5 – D2 = 0, RST 7.5 is enabled.
= 1, RST 7.5 is masked or disabled.
M6.5 – D1 = 0, RST 6.5 is enabled.
= 1, RST 6.5 is masked or disabled.
M5.5 – D0 = 0, RST 5.5 is enabled.
= 1, RST 5.5 is masked or disabled.
Example: SIM

28| UPCIE501 Microprocessor & Microcontroller Module I

8085 Opcode Sheet

Source:https://viaefiraz9.weebly.com/blog/download-opcode-sheet-for-8085-microprocessor-
programming

27| UPCIE501 Microprocessor & Microcontroller Module I

Instruction Format

An instruction is a command to the microprocessor to perform a given task on a specified data.

Each instruction has two parts: one is task to be performed, called the operation code (opcode),
and the second is the data to be operated on, called the operand. The operand (or data) can be
specified in various ways. It may include 8-bit (or 16-bit ) data, an internal register, a memory
location, or 8-bit (or 16-bit) address.
In some instructions, the operand is implicit.

Instruction word size

The 8085 instruction set is classified into the following three groups according to
word size:
1. One-word or 1-byte instructions
2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions

In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor. However,
instructions are commonly referred to in terms of bytes rather than words.

One-Byte Instructions
A 1-byte instruction includes the opcode and operand in the same byte. Operand(s) are internal
register and are coded into the instruction. These instructions are stored in 8- bit binary format in
memory; each requires one memory location. The assembly language instruction is written as
opcode
Examples- MOV A, B
SUB B
CMA
These instructions are 1-byte instructions performing three different tasks.
In the first instruction, both operand registers are specified.
In the second instruction, the operand B is specified and the accumulator is assumed.
In the third instruction, the accumulator is assumed to be the implicit operand.

Two-Byte Instructions
In a two-byte instruction, the first byte specifies the operation code and the second byte specifies
the operand. The instruction would require two memory locations for storage in memory. The
assembly language instruction is written as opcode+data byte
Examples
MVI A, 45H coded as 3EH, 45H as two contiguous bytes. This is an example of immediate
addressing.
ADI 33H
OUT 80H
The first instruction moves the immediate data (45H) into the destination register, Accumulator
The second instruction adds the immediate data (33H) to the contents of the Accumulator

28| UPCIE501 Microprocessor & Microcontroller Module I

 The third instruction send the content of the Accumulator to the Output port (device)
connected to port address 80H.

Three-Byte
Instructions
In a three-byte instruction, the first byte specifies the opcode, and the following two
bytes specify the 16-bit address. Note that the second byte is the low-order address and the third
byte is the high-order address. This instruction would require three memory locations to
store in memory. The assembly language instruction is written as opcode + data byte + data
byte

For example:
LXI rp,
4500H
rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data bytes are
16- bit data in L H order of significance.
LXI H,4500H (21H, 00H, 45H in three bytes). This is also immediate
addressing. LDA 2500H
A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as 3AH
34H
21
H.
This is also an example of direct
addressing.

Tas
k

Enlist the addressing Modes, no of bytes of the following

instructions

Instruction Addressing Modes No of bytes Op-code

MOV B, C
SUI 35H
RAL
STA
4321H
MOV A,M

29| UPCIE501 Microprocessor & Microcontroller Module I