Ordering number : ENA2244A

STK554U392A-E
Thick-Film Hybrid IC

Inverter Power H-IC

http://onsemi.com
for 3-phase Motor Drive

Overview
This “Inverter Power H-IC” is highly integrated device containing all High Voltage (HV) control from HV-DC to
3-phase outputs in a single small SIP module. Output stage uses IGBT/FRD technology and implements Under Voltage
Protection (UVP) and Over Current Protection (OCP) with a Fault Detection output flag. Internal Boost diodes are
provided for high side gate boost drive.
Function
 Single control power supply due to Internal bootstrap circuit for high side pre-driver circuit
 All control inputs and status outputs are at low voltage levels directly compatible with microcontrollers.
 A single power supply drive is enabled through the use of bootstrap circuits for upper power supplies
 Built-in dead-time for shoot-thru protection
 Having open emitter output for low side IGBTs; individual shunt resistor per phase for OCP
 Externally accessible embedded thermistor for substrate temperature measurement
 Shutdown function ‘ITRIP’ to disable all operations of the 6 phase output stage by external input
Certification
 UL1557 (File number: E339285).
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter Symbol Remarks Ratings Unit
Supply voltage VCC V+ to U-, V-, W-, surge<500V *1 450 V
Collector-emitter voltage VCE V+ to U, V, W or U, V, W, to U-, V-, W- 600 V
V+,U-,V-,W-,U,V,W terminal current ±15 A
Output current Io
V+,U-,V-,W-,U,V,W terminal current, Tc=100C ±8 A
Output peak current Iop V+,U-,V-,W-,U,V,W terminal current, P.W.=1ms ±30 A
Pre-driver voltage VD1,2,3,4 VB1 to U, VB2 to V, VB3 to W, VDD to VSS *2 20 V
Input signal voltage VIN HIN1, 2, 3, LIN1, 2, 3 0.3 to VDD V
FLTEN terminal voltage VFLTEN FLTEN terminal 0.3 to VDD V
Maximum power dissipation Pd IGBT per 1 channel 35 W
Junction temperature Tj IGBT, FRD, Pre-Driver IC 150 C
Storage temperature Tstg 40 to +125 C
Operating case
Tc H-IC case 40 to +100 C
temperature
Tightening torque A screw part *3 0.9 Nm
Withstand voltage Vis 50Hz sine wave AC 1 minute *4 2000 VRMS
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1: Surge voltage developed by the switching operation due to the wiring inductance between + and U-(V-, W-) terminal.
*2: VD1=VB1 to U, VD2=VB2 to V, VD3=VB3 to W, VD4=VDD to VSS terminal voltage.
*3: Flatness of the heat-sink should be less than 50m to +100m.
*4: Test conditions : AC2500V, 1 second

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of this data sheet.

Semiconductor Components Industries, LLC, 2013

December, 2013 Ver. 131209DS D1913HK 018-13-0051/N0613HK No.A2244-1/15
 STK554U392A-E

Electrical Characteristics at Tc = 25C, VD1, VD2, VD3, VD4 = 15V

Test
Parameter Symbol Conditions MIN TYP MAX Unit
circuit

Power output section

Collector-emitter cut-off current ICE VCE = 600V - - 100 μA

Fig.1
Bootstrap diode reverse current IR(BD) VR(BD) = 600V - - 100 μA
Collector to emitter saturation voltage Ic = 15A, Tj=25C - 1.7 2.4
VCE(SAT) Fig.2 V
Ic = 8A, Tj=100C - 1.4 -
IF = -15A, Tj=25C - 1.9 2.6
Diode forward voltage VF Fig.3 V
IF = -8A, Tj=100C - 1.4 -
θj-c(T) IGBT - - 3.5
Junction to case thermal resistance - C /W
θj-c(D) FWD - - 5
Control (Pre-driver) section
VD1,2,3 = 15V - 0.08 0.4
Pre-driver power dissipation ID Fig.4 mA
VD4 = 15V - 1.6 4
High level Input voltage Vin H HIN1,HIN2,HIN3, - 2.5 - - V
Low level Input voltage Vin L LIN1,LIN2,LIN3 to VSS - - - 0.8 V
Logic 1 input leakage current IIN+ VIN=+3.3V - - 100 143 μA
Logic 0 input leakage current IIN- VIN=0V - - - 2 μA
FLTEN terminal sink current IoSD FAULT:ON / VFLTEN=0.1V - - 2 - mA
From time fault condition
FLTEN clearance delay time FLTCLR - 1.55 1.9 2.25 ms
clear
VEN+ VEN rising - - - 2.5 V
FLTEN Threshold
VEN- VEN falling - 0.8 - - V
ITRIP threshold voltage VITRIP ITRIP(16) to VSS(29) - 0.44 0.49 0.54 V
ITRIP to shutdown propagation delay tITRIP - 340 550 800 ns
ITRIP blanking time tITRIPBL - 250 350 - ns
VCCUV+
VCC and VBS supply undervoltage protection reset - 10.5 11.1 11.7 V
VBSUV+
VCCUV-
VCC and VBS supply undervoltage protection set - 10.3 10.9 11.5 V
VBSUV-
VCCUVH
VCC and VBS supply undervoltage hysteresis - 0.14 0.2 - V
VBSUVH
Thermistor for substrate temperature Resistance between
Rt - 42.3 47 51.7 kΩ
Monitor TH(27) and VSS(29)

Reference voltage is “VSS” terminal voltage unless otherwise specified.

No.A2244-2/15
 STK554U392A-E

Test
Parameter Symbol Conditions MIN TYP MAX Unit
circuit

Switching Character

t ON Io = 15A - 0.45 -
Switching time Fig.5 μs
t OFF Inductive load - 0.55 -
+
Turn-on switching loss Eon Io=15A,V =300V, - 410 - μJ
Turn-off switching loss Eoff VDD=15V,L=650uH Fig.5 - 390 - μJ
Total switching loss Etot Tc=25C - 800 - μJ
+
Turn-on switching loss Eon Io=8A,V =300V, - 270 - μJ
Turn-off switching loss Eoff VDD=15V,L=650uH Fig.5 - 280 - μJ
Total switching loss Etot Tc=100C - 550 - μJ
+
Diode reverse recovery energy Erec Io=8A, V =400V, VDD=15V, - - 8.5 - μJ
Diode reverse recovery time Trr L=650uH, Tc=100C - - 60 - ns
Reverse bias safe operating area RBSOA Io = 30A, VCE = 450V - Full square- -
Short circuit safe operating area SCSOA VCE = 400V, Tc=100C - 4 - - μs
Between U(V,W) to
Allowable offset voltage slew rate dv/dt - 50 - 50 V/ns
U-(V-,W-)

Reference voltage is “VSS” terminal voltage unless otherwise specified.

Notes

1. The pre-drive power supply low voltage protection has approximately 200mV of hysteresis and operates as follows.
Upper side : The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will
continue till the input signal will turn ‘low’.
Lower side : The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input
signal voltage.

2. When assembling the H-IC on the heat sink the tightening torque range is 0.6Nm to 0.9Nm.

3. The pre-drive low voltage protection protects the device when the pre-drive supply voltage falls due to an operating malfunction.

4. When use the over-current protection with external shunt resistor, please set the current protection level to be equal to or less than the
rating of output peak current (Iop).

No.A2244-3/15
 STK554U392A-E

Module Pin-Out Description

Pin Name Description

1 VB3 High Side Floating Supply Voltage 3
2 W, VS3 Output 3 - High Side Floating Supply Offset Voltage
3 - Without pin
4 - Without pin
5 VB2 High Side Floating Supply voltage 2
6 V,VS2 Output 2 - High Side Floating Supply Offset Voltage
7 - Without pin
8 - Without pin
9 VB1 High Side Floating Supply voltage 1
10 U,VS1 Output 1 - High Side Floating Supply Offset Voltage
11 - Without pin
12 - Without pin
13 V+ Positive Bus Input Voltage
14 - Without pin
15 - Without pin
16 ITRIP Current protection pin
17 U- Low Side Emitter Connection - Phase U
18 FLTEN Enable input / Fault output
19 V- Low Side Emitter Connection - Phase V
20 HIN1 Logic Input High Side Gate Driver - Phase U
21 W- Low Side Emitter Connection - Phase W
22 HIN2 Logic Input High Side Gate Driver - Phase V
23 HIN3 Logic Input High Side Gate Driver - Phase W
24 LIN1 Logic Input Low Side Gate Driver - Phase U
25 LIN2 Logic Input Low Side Gate Driver - Phase V
26 LIN3 Logic Input Low Side Gate Driver - Phase W
27 TH Thermistor output
28 VDD +15V Main Supply
29 VSS Negative Main Supply

No.A2244-4/15
 STK554U392A-E

Equivalent Block Diagram

VB3( 1)
W,VS3( 2)

VB2( 5)
V,VS2( 6)

VB1( 9)
U,VS1(10)

V+ (13)
DB DB DB U.V. U.V. U.V.

U- (17)
V- (19)
W- (21)
Level Level Level
Shifter Shifter Shifter

HIN1(20)
HIN2(22)
HIN3(23) Logic Logic
Logic
LIN1(24)
LIN2(25)
LIN3(26)
Thermistor
TH(27)
Shutdown
ITRIP(16)

VDD(28)
Under voltage + S Q
VSS(29) Detect -
Timer
Enable/Disable R
Vref
Latch time about 2ms
FLTEN(18)

No.A2244-5/15
 STK554U392A-E

Test Circuit
(The tested phase : U+ shows the upper side of the U phase and U- shows the lower side of the U phase.)

 ICE / IR(BD)

ICE
U+ V+ W+ U- V- W- 9 M A
M 13 13 13 10 6 2 VD1=15V
10
N 10 6 2 17 19 21
5
U(BD) V(BD) W(BD) VD2=15V
6 VCE
M 9 5 1
N 29 29 29 1
VD3=15V
2

28
VD4=15V
29 N

Fig.1

 VCE(SAT) (Test by pulse)

9 M
U+ V+ W+ U- V- W- VD1=15V
M 13 13 13 10 6 2 10
N 10 6 2 17 19 21
5
m 20 22 23 24 25 26 VD2=15V
6
V Ic
1
VD3=15V VCE(SAT)
2

28
VD4=15V
5V m N
29
16

 VF (Test by pulse)
Fig.2

U+ V+ W+ U- V- W- M
M 13 13 13 10 6 2
N 10 6 2 17 19 21
V VF IF

Fig.3

 ID

VD1 VD2 VD3 VD4 ID

M 9 5 1 28 A M
N 10 6 2 29 VD*

Fig.4

No.A2244-6/15
 STK554U392A-E

 Switching time (The circuit is a representative example of the lower side U phase.)

9 13
Input signal VD1=15V
(0 to 5V) 10

5
VD2=15V
90% 6 10 Vcc

Io 1 CS
VD3=15V
10% 2
28
VD4=15V Io
tON tOFF
Input signal 24 17
29
16

Fig.5

 RB-SOA (The circuit is a representative example of the lower side U phase.)

Input signal
(0 to 5V)
9 13
VD1=15V
10

5
VD2=15V
6 10 Vcc
Io
1 CS
VD3=15V
2
28
VD4=15V Io

Input signal 24 17
29
16

Fig.6

No.A2244-7/15
 STK554U392A-E

Input / Output Timing Chart

VBS undervoltage protection reset signal
ON

HIN1,2,3
OFF

LIN1,2,3

VDD undervoltage protection reset voltage

VDD *2

VBS undervoltage protection reset voltage

*3
VB1,2,3
VIT≥0.54V
*4
ITRIP terminal
Voltage VIT<0.44V

FLTEN

ON
*1
Upper
U, V, W
OFF

*1
Lower
U ,V, W

Automatically reset after protection

(typ.2ms)

Notes:
1. *1 shows the prevention of shoot-thru via control logic, however, more dead time must be added to account for switching delay
externally.

2. *2 when VDD decreases all gate output signals will go low and cut off all 6 IGBT outputs. When VDD rises the operation will resume
immediately.

3. *3 when the upper side voltage at VB1, VB2 and VB3 drops only the corresponding upper side output is turned off. The outputs return to
normal operation immediately after the upper side gate voltage rises.

4. *4 when VITRIP exceeds threshold all IGBT’s are turned off and normal operation resumes 2ms (typ) after over current condition is
removed.

No.A2244-8/15
 STK554U392A-E

Logic level table

V+

Ho FLTEN Itrip HIN1,2,3 LIN1,2,3 U,V,W

HIN1,2,3 1 0 1 0 Vbus
(15,16,17)
IC U,V,W 1 0 0 1 0
Driver (8,5,2) 1 0 0 0 Off
LIN1,2,3
(18,19,20) 1 0 1 1 Off

Lo 1 1 X X Off
0 X X X Off

Sample Application Circuit

STK554U392A-E
VB1: 9
CB1
U,VS1:10
V+:3

CI CS
Vcc VB2: 5
CB2
V,VS2: 6
U-:7
RSU VB3: 1
V-:19
CB3
RSV W,VS3: 2
W-:21
RSW
Op-Amp,
Controller

U,VS1:10 HIN1:20
HIN2:22
HIN3:23 Control
LIN1:24 Circuit
LIN2:25 (5V)
V,VS2: 6 LIN3:26
TH:27
FLTEN:18
RS,
ITRIP:16 Controller RP RTH
VDD:28
CD4
W,VS3: 2 VSS:29
VD4=15V

No.A2244-9/15
 STK554U392A-E

Recommended Operating Condition at Tc = 25C

Item Symbol Conditions Min. Typ. Max. Unit

Supply voltage VCC V+ to U-(V-,W-) 0 280 450 V

Pre-driver VD1,2,3 VB1 to U,VB2 to V,VB3 to W 12.5 15 17.5

V
supply voltage VD4 VDD to VSS *1 13.5 15 16.5

ON-state input voltage VIN(ON) HIN1,HIN2,HIN3, 3.0 - 5.0

V
OFF-state input voltage VIN(OFF) LIN1,LIN2,LIN3 0 - 0.3

PWM frequency fPWM 1 - 20 kHz

Dead time DT Turn-off to turn-on (external) 0.5 - - μs

Allowable input pulse width PWIN ON and OFF 1 - - μs

Tightening torque ‘M3’ type screw 0.6 - 0.9 Nm

*1 Pre-drive power supply (VD4=15±1.5V) must have the capacity of Io=20mA (DC), 0.5A (Peak).

Usage Precaution

1. This H-IC includes internal bootstrap diode and resistor. By adding a bootstrap capacitor “CB”, a high side drive voltage is
generated; each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47μF,
however, this value needs to be verified prior to production. If selecting the capacitance more than 47μF (±20%), connect a resistor
(about 20Ω) in series between each 3-phase upper side power supply terminals (VB1,2,3) and each bootstrap capacitor.
When not using the bootstrap circuit, each upper side pre-drive power supply requires an external independent power supply.

2. It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of surge
voltages. Recommended value of “CS” is in the range of 0.1 to 10μF.

3. The “FLTEN” terminal (Pin 18) is I/O terminal; Fault output / Enable input. It is used to indicate an internal fault condition of the
module and also can be used to disable the module operation.

4. Inside the H-IC, a thermistor used as the temperature monitor for internal subatrate is connected between VSS terminal and TH
terminal, therefore, an external pull up resistor connected between the TH terminal and an external power supply should be used.
The temperature monitor example application is as follows, please refer the Fig.10, and Fig.11 below.

5. The pull-down resistor (:33kΩ(typ)) is connected with the inside of the signal input terminal, but please connect the pull-down
resistor(about 2.2 to 3.3kΩ) outside to decrease the influence of the noise by wiring etc.

6. As protection of H-IC to the unusual current by a short circuit etc,, it recommends installing shunt resistors and an over-current
protection circuit outside. Moreover, for safety, a fuse on Vcc line is recommended.

7. Disconnection of terminals U, V, or W during normal motor operation will cause damage to H-IC, use caution with this connection.
.
8. The “ITRIP” terminal (Pin 16) is the input terminal to shut down. When VITRIP exceeds threshold (0.44V to 0.54V) all IGBT’s are
turned off. And normal operation resumes 2ms (typ) after over current condition is removed. Therefore, please turn all the input
signals off (Low) in case of detecting error at the “FLTEN” terminal.

9. When input pulse width is less than 1μs, an output may not react to the pulse. (Both ON signal and OFF signal)

 This data shows the example of the application circuit, and does not guarantee a design as the mass production set.

No.A2244-10/15
 STK554U392A-E

The characteristic of thermistor

Parameter Symbol Condition Min Typ. Max Unit

Resistance R25 T = 25C 44.6 47.0 49.4 kΩ
Resistance R125 T = 125C 1.28 1.41 1.53 kΩ
B-Constant(25-50C) B 4010 4050 4091 K
Temperature Range 40 +125 C

Fig.10 Variation of thermistor resistance with temperature

Condition
Pull-up resistor = 4.7kphm
Pull-up voltage of TH = 5V

Fig.11 Variation of temperature sense voltage with thermistor temperature

No.A2244-11/15
 STK554U392A-E

Maximum Phase current

Fig.12 Maximum sinusoidal phase current as function of switching frequency

At Tc=100C, Vcc=300V

Switching waveform

X:100ns/div

Ic: 5A/div

Vce: 100V/div

Fig. 13 IGBT Turn-on. Typical turn-on waveform at Tc=100C, Vcc=300V, Ic=15A

X:100ns/div

Vce: 100V/div

Ic: 5A/div

Fig. 14 IGBT Turn-off. Typical turn-off waveform Tc=100C, Vcc=300V, Ic=15A

No.A2244-12/15
 STK554U392A-E

CB capacitor value calculation for bootstrap circuit

Calculate condition

Item Symbol Value Unit

Upper side power supply. VBS 15 V
Total gate charge of output power IGBT at 15V. Qg 132 nC
Upper side power supply low voltage protection. UVLO 12 V
Upper side power dissipation. IDmax 400 μA
ON time required for CB voltage to fall from 15V to UVLO Ton-max - s

Capacitance calculation formula

CB must not be discharged below to the upper limit of the UVLO - the maximum allowable on-time (Ton-max) of the upper side is
calculated as follows:

VBS * CB – Qg – IDmax * Ton-max = UVLO * CB

CB = (Qg + IDmax * Ton-max) / (VBS – UVLO)

The relationship between Ton-max and CB becomes as follows. CB is recommended to be approximately 3 times the value calculated
above. The recommended value of CB is in the range of 1 to 47μF, however, the value needs to be verified prior to production.

CB vs Ton-max
Bootstrap Capacitance CB [uF]

Ton-max[ms]
Fig15. Ton-max vs CB characteristic

No.A2244-13/15
 STK554U392A-E

Package Dimensions
(unit : mm)

SIP29 56x21.8
CASE 127BW
ISSUE O
missing pin : 3,4,7,8,11,12,14,15
56.0

3.4
R1.7

21.8
(10.9)
13.9
1 29

0.5
5.0
+0 . 2
0.5−0.05
+0 . 2 3.2
1.27 0.6 −0.05
+0 . 1
1.27 × 28=35.56 6.7−0.5

46.2
5.7
2.0

50.0
62.0

No.A2244-14/15
 STK554U392A-E
ORDERING INFORMATION
Device Package Shipping (Qty / Packing)
SIP29 56x21.8
STK554U392A-E (Pb-Free) 8 / Tube

ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for
any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the
part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PS No.A2244-15/15